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a5fa4e9c02
* Order patch application Per discussion with @demarchi this PR adds ordering to the patch application. This alos add some encoding 00000 series - is for px4 non up streamable changes 60000 (bp) series - is for back ports 90000 series - is for wip that shold make it upstream * Restore 00010-workarround-for-flash-data-cache-corruption Extract this from the 90000-wip-inflight-to-upstream.patch and orders it. * Moved upstreamed 0dbf44e flash fix to bp patch * Moved upstreamed 5481087 cdcacm fix to bp patch * Moved upstreamed ec85425 STM32F7 copy paste errors to bp patch * Moved upstreamed 20e7237 HSI should not be turned off to bp patch * Moved upstreamed ca895b9 Adding missing CONFIG_ prefix to bp patch * Moved upstreamed 169b398 STM32: Fixes the bkp reference counter issue to bp patch * Moved upstreamed 550d259 STM32F7: Fixes the bkp reference counter issue to bp patch * Moved upstreamed 02825f3 STM32F3X: Add missing STM32_BKP_BASE to bp patch * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Renamed for ordering and classification * Order Patches by Name
30 lines
1.0 KiB
Diff
30 lines
1.0 KiB
Diff
diff --git NuttX/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c NuttX/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
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index 5e2ba73..adda863 100644
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--- NuttX/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
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+++ NuttX/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
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@@ -95,10 +95,10 @@ static inline void rcc_reset(void)
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putreg32(0x00000000, STM32_RCC_CFGR);
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- /* Reset HSION, HSEON, CSSON and PLLON bits */
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+ /* Reset HSEON, CSSON and PLLON bits */
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regval = getreg32(STM32_RCC_CR);
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- regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
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+ regval &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
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putreg32(regval, STM32_RCC_CR);
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/* Reset PLLCFGR register to reset default */
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@@ -619,11 +619,6 @@ static void stm32_stdclockconfig(void)
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volatile int32_t timeout;
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#ifdef STM32_BOARD_USEHSI
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- /* Enable Internal High-Speed Clock (HSI) */
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-
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- regval = getreg32(STM32_RCC_CR);
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- regval |= RCC_CR_HSION; /* Enable HSI */
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- putreg32(regval, STM32_RCC_CR);
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/* Wait until the HSI is ready (or until a timeout elapsed) */
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