From d2bc3a534fba07e3ff88ff65f3323bd578363341 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Mon, 31 Jul 2017 16:38:53 -1000 Subject: [PATCH] px4nucleoF767ZI-v1:Fixed STM32_RCC_DCKCFGR2_DSISRC C&P error in upstream was:RCC_DCKCFGR2_DSISEL_48MHZ is RCC_DCKCFGR2_DSISEL_PHY --- nuttx-configs/px4nucleoF767ZI-v1/include/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nuttx-configs/px4nucleoF767ZI-v1/include/board.h b/nuttx-configs/px4nucleoF767ZI-v1/include/board.h index cfcf8fba42..f98922fff7 100755 --- a/nuttx-configs/px4nucleoF767ZI-v1/include/board.h +++ b/nuttx-configs/px4nucleoF767ZI-v1/include/board.h @@ -163,7 +163,7 @@ #define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLL #define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ #define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ -#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_48MHZ +#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_PHY /* Several prescalers allow the configuration of the two AHB buses, the