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KakuteF7: enable SPI DMA for SPI 4
DMA for SPI 1 left disabled because the SD card does not work when enabling it.
This commit is contained in:
Beat Küng
Daniel Agar
@@ -37,6 +37,7 @@
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include "board_dma_map.h"
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#include <nuttx/config.h>
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102
boards/holybro/kakutef7/nuttx-config/include/board_dma_map.h
Normal file
102
boards/holybro/kakutef7/nuttx-config/include/board_dma_map.h
Normal file
@@ -0,0 +1,102 @@
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/****************************************************************************
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*
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* Copyright (c) 2020 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#pragma once
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/*
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| DMA1 | Stream 0 | Stream 1 | Stream 2 | Stream 3 | Stream 4 | Stream 5 | Stream 6 | Stream 7 |
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|------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|
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| Channel 0 | SPI3_RX_1 | SPDIFRX_DT | SPI3_RX_2 | SPI2_RX | SPI2_TX | SPI3_TX_1 | SPDIFRX_CS | SPI3_TX_2 |
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| Channel 1 | I2C1_RX | I2C3_RX | TIM7_UP_1 | - | TIM7_UP_2 | I2C1_RX_1 | I2C1_TX | I2C1_TX_1 |
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| Channel 2 | TIM4_CH1 | - | I2C4_RX | TIM4_CH2 | - | I2C4_RX | TIM4_UP | TIM4_CH3 |
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| Channel 3 | - | TIM2_UP_1 | I2C3_RX_1 | - | I2C3_TX | TIM2_CH1 | TIM2_CH2 | TIM2_UP_2 |
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| | | TIM2_CH3 | | | | | TIM2_CH4_1 | TIM2_CH4_2 |
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| Channel 4 | UART5_RX | USART3_RX | UART4_RX | USART3_TX_1 | UART4_TX | USART2_RX | USART2_TX | UART5_TX |
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| Channel 5 | UART8_TX | UART7_TX | TIM3_CH4 | UART7_RX | TIM3_CH1 | TIM3_CH2 | UART8_RX | TIM3_CH3 |
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| | | | TIM3_UP | | TIM3_TRIG | | | |
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| Channel 6 | TIM5_CH3 | TIM5_CH4_1 | TIM5_CH1 | TIM5_CH4_2 | TIM5_CH2 | - | TIM5_UP_2 | - |
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| | TIM5_UP_1 | TIM5_TRIG_1 | | TIM5_TRIG_2 | | | | |
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| Channel 7 | - | TIM6_UP | I2C2_RX | I2C2_RX_1 | USART3_TX_2 | DAC1 | DAC2 | I2C2_TX |
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| Channel 8 | I2C3_TX | I2C4_RX | - | - | I2C2_TX | - | I2C4_TX | - |
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| Channel 9 | - | SPI2_RX | - | - | - | - | SPI2_TX | - |
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| | | | | | | | | |
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| Usage | | | TIM3_UP | | | USART2_RX | TIM5_UP_2 | |
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| DMA2 | Stream 0 | Stream 1 | Stream 2 | Stream 3 | Stream 4 | Stream 5 | Stream 6 | Stream 7 |
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|------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|
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| Channel 0 | ADC1_1 | SAI1_A | TIM8_CH1_1 | SAI1_A_1 | ADC1_2 | SAI1_B_1 | TIM1_CH1_1 | SAI2_B_2 |
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| | | | TIM8_CH2_1 | | | | TIM1_CH2_1 | |
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| | | | TIM8_CH3_1 | | | | TIM1_CH3_1 | |
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| Channel 1 | - | DCMI_1 | ADC2_1 | ADC2_2 | SAI1_B | SPI6_TX | SPI6_RX | DCMI_2 |
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| Channel 2 | ADC3_1 | ADC3_2 | - | SPI5_RX_1 | SPI5_TX_1 | CRYP_OUT | CRYP_IN | HASH_IN |
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| Channel 3 | SPI1_RX_1 | - | SPI1_RX_2 | SPI1_TX_1 | SAI2_A | SPI1_TX_2 | SAI2_B | QUADSPI |
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| Channel 4 | SPI4_RX_1 | SPI4_TX_1 | USART1_RX_1 | SDMMC1_1 | - | USART1_RX_2 | SDMMC1_2 | USART1_TX |
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| Channel 5 | - | USART6_RX_1 | USART6_RX_2 | SPI4_RX_2 | SPI4_TX_2 | - | USART6_TX_1 | USART6_TX_2 |
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| Channel 6 | TIM1_TRIG_1 | TIM1_CH1_2 | TIM1_CH2_2 | TIM1_CH1 | TIM1_CH4 | TIM1_UP | TIM1_CH3_2 | - |
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| | | | | | TIM1_TRIG_2 | | | |
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| | | | | | TIM1_COM | | | |
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| Channel 7 | - | TIM8_UP | TIM8_CH1_2 | TIM8_CH2_2 | TIM8_CH3_2 | SPI5_RX_2 | SPI5_TX_2 | TIM8_CH4 |
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| | | | | | | | | TIM8_TRIG |
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| | | | | | | | | TIM8_COM |
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| Channel 8 | DSFDM1_FLT0 | DSFDM1_FLT1 | DSFDM1_FLT2 | DSFDM1_FLT3 | DSFDM1_FLT0 | DSFDM1_FLT1 | DSFDM1_FLT2 | DSFDM1_FLT3 |
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| Channel 9 | JPEG_IN | JPEG_OUT | SPI4_TX | JPEG_IN | JPEG_OUT | SPI5_RX | - | - |
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| Channel 10 | SAI1_B | SAI2_B | SAI2_A | - | - | - | SAI1_A | - |
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| Channel 11 | SDMMC2 | - | QUADSPI | - | - | SDMMC2 | - | - |
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| | | | | | | | | |
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| Usage | SPI4_RX_1 | TIM8_UP | | | SPI4_TX_2 | TIM1_UP | | |
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*/
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// DMA1 Channel/Stream Selections
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//--------------------------------------------//---------------------------//----------------
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// AVAILABLE // DMA1, Stream 0
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// AVAILABLE // DMA1, Stream 1
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// DMAMAP_TIM3_UP // DMA1, Stream 2, Channel 5 (DSHOT)
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// AVAILABLE // DMA1, Stream 3
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// AVAILABLE // DMA1, Stream 4
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// DMAMAP_USART2_RX // DMA1, Stream 5, Channel 4
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// DMAMAP_TIM5_UP_2 // DMA1, Stream 6, Channel 6 (DSHOT)
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// AVAILABLE // DMA1, Stream 7
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// DMA2 Channel/Stream Selections
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//--------------------------------------------//---------------------------//----------------
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#define DMAMAP_SPI4_RX DMAMAP_SPI4_RX_1 // DMA2, Stream 0, Channel 4 (SPI sensors)
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// DMAMAP_TIM8_UP // DMA2, Stream 1, Channel 7 (DSHOT)
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// AVAILABLE // DMA1, Stream 2
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// AVAILABLE // DMA1, Stream 3
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#define DMAMAP_SPI4_TX DMAMAP_SPI4_TX_2 // DMA2, Stream 4, Channel 5 (SPI sensors)
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// DMAMAP_TIM1_UP // DMA2, Stream 5, Channel 6 (DSHOT)
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// AVAILABLE // DMA1, Stream 6
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// AVAILABLE // DMA1, Stream 7
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@@ -167,6 +167,7 @@ CONFIG_STM32F7_BBSRAM_FILES=5
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CONFIG_STM32F7_BKPSRAM=y
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CONFIG_STM32F7_DMA1=y
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CONFIG_STM32F7_DMA2=y
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CONFIG_STM32F7_DMACAPABLE=y
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CONFIG_STM32F7_I2C1=y
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CONFIG_STM32F7_I2C_DYNTIMEO=y
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CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP=10
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@@ -182,6 +183,10 @@ CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y
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CONFIG_STM32F7_SPI1=y
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CONFIG_STM32F7_SPI2=y
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CONFIG_STM32F7_SPI4=y
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CONFIG_STM32F7_SPI4_DMA=y
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CONFIG_STM32F7_SPI4_DMA_BUFFER=1024
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CONFIG_STM32F7_SPI_DMA=y
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CONFIG_STM32F7_SPI_DMATHRESHOLD=8
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CONFIG_STM32F7_UART4=y
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CONFIG_STM32F7_UART7=y
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CONFIG_STM32F7_USART1=y
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