yemai/bizhang_-obav
1
0
Fork 0
mirror of https://gitee.com/xiaohuolufeihua/bizhang_-obav.git synced 2026-05-22 01:12:31 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fixes for STM32 ADC driver on the F4; LC17xx LED initial state

Browse Source 
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4257 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
2012-01-03 23:25:49 +00:00
parent 77f614d624
commit a2f9aff906
6 changed files with 83 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files

100
nuttx/arch/arm/src/stm32/stm32_adc.c
View File

@@ -162,7 +162,7 @@ static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable);
static int adc_timinit(FAR struct stm32_dev_s *priv); static int adc_timinit(FAR struct stm32_dev_s *priv);
#endif #endif
#ifdef CONFIG_ADC_DMA #ifdef CONFIG_STM32_STM32F40XX
static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable); static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable);
#endif #endif
@@ -226,7 +226,7 @@ static struct stm32_dev_s g_adcpriv2 =
.intf = 2; .intf = 2;
.base = STM32_ADC2_BASE, .base = STM32_ADC2_BASE,
#ifdef ADC2_HAVE_TIMER #ifdef ADC2_HAVE_TIMER
.trigger = CONFIG_STM32_ADC2_TIMTRIG; .trigger = CONFIG_STM32_ADC2_TIMTRIG,
.tbase = ADC2_TIMER_BASE, .tbase = ADC2_TIMER_BASE,
.extsel = ADC2_EXTSEL_VALUE, .extsel = ADC2_EXTSEL_VALUE,
.pclck = ADC2_TIMER_PCLK_FREQUENCY, .pclck = ADC2_TIMER_PCLK_FREQUENCY,
@@ -253,10 +253,10 @@ static struct stm32_dev_s g_adcpriv3 =
.irq = STM32_IRQ_ADC, .irq = STM32_IRQ_ADC,
.isr = adc123_interrupt, .isr = adc123_interrupt,
#endif #endif
.intf = 3; .intf = 3,
.base = STM32_ADC3_BASE, .base = STM32_ADC3_BASE,
#ifdef ADC3_HAVE_TIMER #ifdef ADC3_HAVE_TIMER
.trigger = CONFIG_STM32_ADC3_TIMTRIG; .trigger = CONFIG_STM32_ADC3_TIMTRIG,
.tbase = ADC3_TIMER_BASE, .tbase = ADC3_TIMER_BASE,
.extsel = ADC3_EXTSEL_VALUE, .extsel = ADC3_EXTSEL_VALUE,
.pclck = ADC3_TIMER_PCLK_FREQUENCY, .pclck = ADC3_TIMER_PCLK_FREQUENCY,
@@ -485,27 +485,31 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
uint16_t ccenable; uint16_t ccenable;
uint16_t ccer; uint16_t ccer;
uint16_t egr; uint16_t egr;
avdbg("Initializing timers extsel = %d\n", priv->extsel);
/* If the timer base address is zero, then this ADC was not configured to /* If the timer base address is zero, then this ADC was not configured to
* use a timer. * use a timer.
*/ */
regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET);
#ifdef CONFIG_STM32_STM32F10XX
if (!priv->tbase) if (!priv->tbase)
{ {
/* Configure the ADC to use the selected timer and timer channel as the trigger /* Configure the ADC to use the selected timer and timer channel as the trigger
* EXTTRIG: External Trigger Conversion mode for regular channels DISABLE * EXTTRIG: External Trigger Conversion mode for regular channels DISABLE
*/ */
regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET);
regval &= ~ADC_CR2_EXTTRIG; regval &= ~ADC_CR2_EXTTRIG;
adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval); adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
return OK; return OK;
} }
else else
{ {
regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET);
regval |= ADC_CR2_EXTTRIG; regval |= ADC_CR2_EXTTRIG;
} }
#endif
/* EXTSEL selection: These bits select the external event used to trigger /* EXTSEL selection: These bits select the external event used to trigger
* the start of conversion of a regular group. NOTE: * the start of conversion of a regular group. NOTE:
@@ -803,14 +807,14 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
* *
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_ADC_DMA #ifdef CONFIG_STM32_STM32F40XX
static void adc_startconv(struct stm32_dev_s *priv, bool enable) static void adc_startconv(struct stm32_dev_s *priv, bool enable)
{ {
uint32_t regval; uint32_t regval;
avdbg("enable: %d\n", enable); avdbg("enable: %d\n", enable);
regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET); regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET);
if (enable) if (enable)
{ {
/* Start conversion of regular channles */ /* Start conversion of regular channles */
@@ -961,6 +965,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
uint32_t regval; uint32_t regval;
int offset; int offset;
int i; int i;
int ret;
avdbg("intf: ADC%d\n", priv->intf); avdbg("intf: ADC%d\n", priv->intf);
flags = irqsave(); flags = irqsave();
@@ -1014,21 +1019,24 @@ static void adc_reset(FAR struct adc_dev_s *dev)
/* Initialize the Analog watchdog enable */ /* Initialize the Analog watchdog enable */
regval |= ADC_CR1_AWDEN; regval |= ADC_CR1_AWDEN;
regval |= (priv->chanlist[0] << ADC_CR1_AWDCH_SHIFT);
/* Enable interrupt flags */ /* Enable interrupt flags */
regval |= ADC_CR1_ALLINTS; regval |= ADC_CR1_ALLINTS;
adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval);
/* ADC CCR configuration */
#ifdef CONFIG_STM32_STM32F40XX #ifdef CONFIG_STM32_STM32F40XX
regval |= adc_getreg(priv, STM32_ADC_CCR_OFFSET);
regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | ADC_CCR_DMA_MASK | /* Enable or disable Overrun interrupt */
ADC_CCR_ADCPRE_MASK | ADC_CCR_VBATE | ADC_CCR_TSVREFE);
regval |= (ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED | ADC_CCR_ADCPRE_DIV2); regval &= ~ADC_CR1_OVRIE;
adc_putreg(priv, STM32_ADC_CCR_OFFSET, regval);
/* Set the resolution of the conversion */
regval |= ACD_CR1_RES_12BIT;
#endif #endif
adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval);
/* ADC CR2 Configuration */ /* ADC CR2 Configuration */
@@ -1041,22 +1049,15 @@ static void adc_reset(FAR struct adc_dev_s *dev)
/* Set ALIGN (Right = 0) */ /* Set ALIGN (Right = 0) */
regval &= ~ADC_CR2_ALIGN; regval &= ~ADC_CR2_ALIGN;
adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
#ifdef CONFIG_STM32_STM32F40XX
#if 0 /* External trigger enable for regular channels */
#ifdef CONFIG_STM32_STM32F10XX
/* ADC reset calibaration register */ regval |= ACD_CR2_EXTEN_RISING;
regval |= ADC_CR2_RSTCAL;
adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
usleep(5);
/* A/D Calibration */
regval |= ADC_CR2_CAL;
adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
#endif
#endif #endif
adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
/* Configuration of the channel conversions */ /* Configuration of the channel conversions */
regval = adc_getreg(priv, STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED; regval = adc_getreg(priv, STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED;
@@ -1078,6 +1079,16 @@ static void adc_reset(FAR struct adc_dev_s *dev)
{ {
regval |= (uint32_t)priv->chanlist[i] << offset; regval |= (uint32_t)priv->chanlist[i] << offset;
} }
/* ADC CCR configuration */
#ifdef CONFIG_STM32_STM32F40XX
regval = getreg32(STM32_ADC_CCR);
regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | ADC_CCR_DMA_MASK |
ADC_CCR_ADCPRE_MASK | ADC_CCR_VBATE | ADC_CCR_TSVREFE);
regval |= (ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED | ADC_CCR_ADCPRE_DIV2);
putreg32(regval, STM32_ADC_CCR);
#endif
/* Set the number of conversions */ /* Set the number of conversions */
@@ -1101,12 +1112,16 @@ static void adc_reset(FAR struct adc_dev_s *dev)
adbg("Error initializing the timers\n"); adbg("Error initializing the timers\n");
} }
#else #else
#ifdef CONFIG_STM32_STM32F10XX
/* Set ADON (Again) to start the conversion. Only if Timers are not /* Set ADON (Again) to start the conversion. Only if Timers are not
* configured as triggers * configured as triggers
*/ */
adc_enable(priv, true); adc_enable(priv, true);
#endif #else
adc_startconv(priv, true);
#endif /* CONFIG_STM32_STM32F10XX */
#endif /* ADC_HAVE_TIMER */
irqrestore(flags); irqrestore(flags);
@@ -1118,6 +1133,10 @@ static void adc_reset(FAR struct adc_dev_s *dev)
adc_getreg(priv, STM32_ADC_SQR1_OFFSET), adc_getreg(priv, STM32_ADC_SQR1_OFFSET),
adc_getreg(priv, STM32_ADC_SQR2_OFFSET), adc_getreg(priv, STM32_ADC_SQR2_OFFSET),
adc_getreg(priv, STM32_ADC_SQR3_OFFSET)); adc_getreg(priv, STM32_ADC_SQR3_OFFSET));
#ifdef CONFIG_STM32_STM32F40XX
avdbg("CCR: 0x%08x\n",
getreg32(STM32_ADC_CCR));
#endif
} }
/**************************************************************************** /****************************************************************************
@@ -1228,7 +1247,7 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
* *
****************************************************************************/ ****************************************************************************/
static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
{ {
return -ENOTTY; return -ENOTTY;
} }
@@ -1251,14 +1270,21 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
uint32_t adcsr; uint32_t adcsr;
int32_t value; int32_t value;
/* Identifies the interruption AWD or EOC */ /* Identifies the interruption AWD, OVR or EOC */
adcsr = adc_getreg(priv, STM32_ADC_SR_OFFSET); adcsr = adc_getreg(priv, STM32_ADC_SR_OFFSET);
if ((adcsr & ADC_SR_AWD) != 0) if ((adcsr & ADC_SR_AWD) != 0)
{ {
adbg("WARNING: Analog Watchdog, Value converted out of range!\n"); alldbg("WARNING: Analog Watchdog, Value converted out of range!\n");
} }
#ifdef CONFIG_STM32_STM32F40XX
if ((adcsr & ADC_SR_OVR) != 0)
{
alldbg("WARNING: Overrun has ocurred!\n");
}
#endif
/* EOC: End of conversion */ /* EOC: End of conversion */
if ((adcsr & ADC_SR_EOC) != 0) if ((adcsr & ADC_SR_EOC) != 0)

7
nuttx/configs/olimex-lpc1766stk/src/lpc1766stk_internal.h
View File

@@ -127,10 +127,13 @@
* -------------------------------- ---- -------------- * -------------------------------- ---- --------------
* P1[25]/MC1A/MAT1[1] 39 LED1 * P1[25]/MC1A/MAT1[1] 39 LED1
* P0[4]/I2SRX_CLK/RD2/CAP2[0] 81 LED2/ACC IRQ * P0[4]/I2SRX_CLK/RD2/CAP2[0] 81 LED2/ACC IRQ
*
* LEDs are connected to +3.3V through a diode on one side and must be pulled
* low (through a resistor) on the LPC17xx side in order to illuminuate them.
*/ */
#define LPC1766STK_LED1 (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT1 | GPIO_PIN25) #define LPC1766STK_LED1 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN25)
#define LPC1766STK_LED2 (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORT0 | GPIO_PIN4) #define LPC1766STK_LED2 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN4)
/* Buttons GPIO PIN SIGNAL NAME /* Buttons GPIO PIN SIGNAL NAME
* -------------------------------- ---- -------------- * -------------------------------- ---- --------------

2
nuttx/configs/stm3240g-eval/README.txt
View File

@@ -603,7 +603,9 @@ Where <subdir> is one of the following:
CONFIG_ADC=y : Enable the generic ADC infrastructure CONFIG_ADC=y : Enable the generic ADC infrastructure
CONFIG_STM32_ADC3=y : Enable ADC3 CONFIG_STM32_ADC3=y : Enable ADC3
CONFIG_STM32_TIM1=y : Enable Timer 1
CONFIG_STM32_TIM1_ADC3=y : Assign timer 1 to driver ADC3 sampling CONFIG_STM32_TIM1_ADC3=y : Assign timer 1 to driver ADC3 sampling
CONFIG_STM32_ADC3_SAMPLE_FREQUENCY=100 : Select a sampling frequency
See also apps/examples/README.txt See also apps/examples/README.txt

3
nuttx/configs/stm3240g-eval/src/up_adc.c
View File

@@ -40,6 +40,7 @@
#include <nuttx/config.h> #include <nuttx/config.h>
#include <errno.h>
#include <debug.h> #include <debug.h>
#include <nuttx/analog/adc.h> #include <nuttx/analog/adc.h>
@@ -136,7 +137,7 @@ int adc_devinit(void)
/* Call stm32_adcinitialize() to get an instance of the ADC interface */ /* Call stm32_adcinitialize() to get an instance of the ADC interface */
adc = stm32_adcinitialize(1, g_chanlist, ADC3_NCHANNELS); adc = stm32_adcinitialize(3, g_chanlist, ADC3_NCHANNELS);
if (adc == NULL) if (adc == NULL)
{ {
adbg("ERROR: Failed to get ADC interface\n"); adbg("ERROR: Failed to get ADC interface\n");

11
nuttx/configs/sure-pic32mx/README.txt
View File

@@ -329,7 +329,6 @@ PIC32MX Configuration Options
CONFIG_PIC32MX_USBDEV - USB device CONFIG_PIC32MX_USBDEV - USB device
CONFIG_PIC32MX_USBHOST - USB host CONFIG_PIC32MX_USBHOST - USB host
PIC32MX Configuration Settings PIC32MX Configuration Settings
DEVCFG0: DEVCFG0:
CONFIG_PIC32MX_DEBUGGER - Background Debugger Enable. Default 3 (disabled). The CONFIG_PIC32MX_DEBUGGER - Background Debugger Enable. Default 3 (disabled). The
@@ -431,3 +430,13 @@ Where <subdir> is one of the following:
ostest: ostest:
This configuration directory, performs a simple OS test using This configuration directory, performs a simple OS test using
apps/examples/ostest. apps/examples/ostest.
nsh:
Configures the NuttShell (nsh) located at apps/examples/nsh. The
Configuration enables only the serial NSH interface.
The examples/usbterm program can be included as an NSH built-in
function by defined the following in your .config file:
CONFIG_USBEV=y : Enable basic USB device support
CONFIG_PIC32MX_USBDEV=y : Enable PIC32 USB device support

2
nuttx/drivers/can.c
View File

@@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* drivers/can.c * drivers/can.c
* *
* Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2008-2009, 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without