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Fix offset to STM32 F1 AFIO EXTICR register

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git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4309 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
2012-01-18 17:48:46 +00:00
parent de66b638e1
commit 9b5078804f
3 changed files with 34 additions and 29 deletions
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5
nuttx/ChangeLog
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@@ -2376,3 +2376,8 @@
code complete, but still untested. code complete, but still untested.
* confgs/sim/*/Make.defs and arch/sim/src/Makefile: Add support for building * confgs/sim/*/Make.defs and arch/sim/src/Makefile: Add support for building
a 32-bit executable on a 64-bit Linux target. a 32-bit executable on a 64-bit Linux target.
* configs/sure-pic32mx/src/up_leds.c: Correct GPIOs used for LEDs. The wrong
pins were being used.
* arch/arm/src/stm32/chip/stm32f10xxx_gpio.h: Correct offset to one AFIO EXICR
register.

6
nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h
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@@ -1,8 +1,8 @@
/************************************************************************************ /************************************************************************************
* arch/arm/src/stm32/chip/stm32f10xxx_gpio.h * arch/arm/src/stm32/chip/stm32f10xxx_gpio.h
* *
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@@ -136,7 +136,7 @@
#define STM32_AFIO_MAPR (STM32_AFIO_BASE+STM32_AFIO_MAPR_OFFSET) #define STM32_AFIO_MAPR (STM32_AFIO_BASE+STM32_AFIO_MAPR_OFFSET)
#define STM32_AFIO_EXTICR(p) (STM32_AFIO_BASE+STM32_AFIO_EXTICR_OFFSET(p)) #define STM32_AFIO_EXTICR(p) (STM32_AFIO_BASE+STM32_AFIO_EXTICR_OFFSET(p))
#define STM32_AFIO_EXTICR1 (STM32_AFIO_BASE+STM32_AFIO_EXTICR1_OFFSET) #define STM32_AFIO_EXTICR1 (STM32_AFIO_BASE+STM32_AFIO_EXTICR1_OFFSET)
#define STM32_AFIO_EXTICR2 (STM32_AFIO_BASE+STM32_AFIO_EXTICR3_OFFSET) #define STM32_AFIO_EXTICR2 (STM32_AFIO_BASE+STM32_AFIO_EXTICR2_OFFSET)
#define STM32_AFIO_EXTICR3 (STM32_AFIO_BASE+STM32_AFIO_EXTICR3_OFFSET) #define STM32_AFIO_EXTICR3 (STM32_AFIO_BASE+STM32_AFIO_EXTICR3_OFFSET)
#define STM32_AFIO_EXTICR4 (STM32_AFIO_BASE+STM32_AFIO_EXTICR4_OFFSET) #define STM32_AFIO_EXTICR4 (STM32_AFIO_BASE+STM32_AFIO_EXTICR4_OFFSET)

2
nuttx/arch/arm/src/stm32/stm32_exti.c
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@@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/stm32/stm32_exti.c * arch/arm/src/stm32/stm32_exti.c
* *
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
* Copyright (C) 2011 Uros Platise. All rights reserved. * Copyright (C) 2011 Uros Platise. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* Uros Platise <uros.platise@isotel.eu> * Uros Platise <uros.platise@isotel.eu>