From 7edd07f8cbc9da3da62c365b0ec5ab78d69ec76d Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 29 Jan 2016 12:18:41 -1000 Subject: [PATCH] Rebased on master, removing the default_rate field and using default to 0 for rates --- src/drivers/stm32/drv_io_timer.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/drivers/stm32/drv_io_timer.c b/src/drivers/stm32/drv_io_timer.c index 13acd717ec..327bfdeec9 100644 --- a/src/drivers/stm32/drv_io_timer.c +++ b/src/drivers/stm32/drv_io_timer.c @@ -413,6 +413,10 @@ static int io_timer_init_timer(unsigned timer) rCCER(timer) = 0; rCCMR1(timer) = 0; rCCMR2(timer) = 0; + rCCR1(timer) = 0; + rCCR2(timer) = 0; + rCCR3(timer) = 0; + rCCR4(timer) = 0; rCCER(timer) = 0; rDCR(timer) = 0; @@ -548,10 +552,11 @@ int io_timer_channel_init(unsigned channel, io_timer_channel_mode_t mode, * The beauty here is that per DocID018909 Rev 8 18.3.5 Input capture mode * As soon as CCxS (in SSMRx becomes different from 00, the channel is configured * in input and the TIMx_CCR1 register becomes read-only. - * so the next line does nothing + * so the next line does nothing in capture mode and initializes an PWM out to + * 0 */ - REG(timer, ccr_offset) = timer_io_channels[channel].default_value; + REG(timer, ccr_offset) = 0; /* on PWM Out ccer_setbits is 0 */