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io timer: remove some fields from io_timers_t and split out channel indexes

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- reduces amount of board configuration required
- removes the cyclic dependency between io_timers_t and timer_io_channels_t

Fixes a bug in the fmuk66-v3 config: the 2. timer has 3 channels associated
not 2.
Fixes a bug in the modelai config: the 2. timer has 4 channels associated.
This commit is contained in:
Beat Küng
2020-01-03 10:02:47 +01:00
committed by David Sidrane
parent 8020e82c1c
commit 62b4f3487a
28 changed files with 581 additions and 301 deletions
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44
boards/px4/fmu-v5x/src/timer_config.c
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@@ -79,15 +79,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
.dshot = {
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM1_UP,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 4u /* CCR1, CCR2, CCR3 and CCR4 */
}
},
{
@@ -95,15 +90,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM4EN,
.clock_freq = STM32_APB1_TIM4_CLKIN,
.first_channel_index = 4,
.last_channel_index = 5,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4,
.dshot = {
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM4_UP,
.start_ccr_register = TIM_DMABASE_CCR2,
.channels_number = 2u /* CCR2 and CCR3 */
}
},
{
@@ -111,9 +101,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM12EN,
.clock_freq = STM32_APB1_TIM12_CLKIN,
.first_channel_index = 6,
.last_channel_index = 7,
.handler = io_timer_handler2,
.vectorno = STM32_IRQ_TIM12,
},
{
@@ -121,9 +108,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM5EN,
.clock_freq = STM32_APB1_TIM5_CLKIN,
.first_channel_index = 8,
.last_channel_index = 10,
.handler = io_timer_handler3,
.vectorno = STM32_IRQ_TIM5,
},
{
@@ -131,13 +115,35 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM2EN,
.clock_freq = STM32_APB1_TIM2_CLKIN,
.first_channel_index = 11,
.last_channel_index = 11,
.handler = io_timer_handler4,
.vectorno = STM32_IRQ_TIM2,
},
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 2,
},
{
.first_channel_index = 6,
.channel_count = 2,
},
{
.first_channel_index = 8,
.channel_count = 3,
},
{
.first_channel_index = 11,
.channel_count = 1,
}
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM1_CH4OUT,