io timer: remove some fields from io_timers_t and split out channel indexes

- reduces amount of board configuration required
- removes the cyclic dependency between io_timers_t and timer_io_channels_t

Fixes a bug in the fmuk66-v3 config: the 2. timer has 3 channels associated
not 2.
Fixes a bug in the modelai config: the 2. timer has 4 channels associated.
This commit is contained in:
Beat Küng
2020-01-03 10:02:47 +01:00
committed by David Sidrane
parent 8020e82c1c
commit 62b4f3487a
28 changed files with 581 additions and 301 deletions

View File

@@ -56,15 +56,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIMCC,
.dshot = {
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_DMA12_TIM1UP_0,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 4u /* CCR1, CCR2, CCR3 and CCR4 */
}
},
{
@@ -72,19 +67,27 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1LENR,
.clock_bit = RCC_APB1LENR_TIM4EN,
.clock_freq = STM32_APB1_TIM4_CLKIN,
.first_channel_index = 4,
.last_channel_index = 4,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4,
.dshot = {
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_DMA12_TIM4UP_0,
.start_ccr_register = TIM_DMABASE_CCR2,
.channels_number = 1u /* CCR2 */
}
},
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 1,
}
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM1_CH4OUT,

View File

@@ -56,15 +56,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM3EN,
.clock_freq = STM32_APB1_TIM3_CLKIN,
.first_channel_index = 0,
.last_channel_index = 1,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM3,
.dshot = {
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM3_UP,
.start_ccr_register = TIM_DMABASE_CCR3,
.channels_number = 2u /* CCR3 and CCR4 */
}
},
{
@@ -72,15 +67,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 2,
.last_channel_index = 3,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM1CC,
.dshot = {
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM1_UP,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 2u /* CCR1 and CCR2 */
}
},
{
@@ -88,15 +78,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM8EN,
.clock_freq = STM32_APB2_TIM8_CLKIN,
.first_channel_index = 4,
.last_channel_index = 4,
.handler = io_timer_handler2,
.vectorno = STM32_IRQ_TIM8CC,
.dshot = {
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM8_UP,
.start_ccr_register = TIM_DMABASE_CCR4,
.channels_number = 1u /* CCR4 */
}
},
{
@@ -104,19 +89,35 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM5EN,
.clock_freq = STM32_APB1_TIM5_CLKIN,
.first_channel_index = 5,
.last_channel_index = 5,
.handler = io_timer_handler3,
.vectorno = STM32_IRQ_TIM5,
.dshot = {
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM5_UP_2,
.start_ccr_register = TIM_DMABASE_CCR4,
.channels_number = 1u /* CCR4 */
}
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 2,
},
{
.first_channel_index = 2,
.channel_count = 2,
},
{
.first_channel_index = 4,
.channel_count = 1,
},
{
.first_channel_index = 5,
.channel_count = 1,
},
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM3_CH3OUT,