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https://gitee.com/xiaohuolufeihua/bizhang_-obav.git
synced 2026-05-22 01:12:31 +00:00
io timer: remove some fields from io_timers_t and split out channel indexes
- reduces amount of board configuration required - removes the cyclic dependency between io_timers_t and timer_io_channels_t Fixes a bug in the fmuk66-v3 config: the 2. timer has 3 channels associated not 2. Fixes a bug in the modelai config: the 2. timer has 4 channels associated.
This commit is contained in:
@@ -56,15 +56,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
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.clock_register = STM32_RCC_APB2ENR,
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.clock_bit = RCC_APB2ENR_TIM1EN,
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.clock_freq = STM32_APB2_TIM1_CLKIN,
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.first_channel_index = 0,
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.last_channel_index = 3,
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.handler = io_timer_handler0,
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.vectorno = STM32_IRQ_TIMCC,
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.dshot = {
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.dma_base = STM32_DMA1_BASE,
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.dmamap = DMAMAP_DMA12_TIM1UP_0,
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.start_ccr_register = TIM_DMABASE_CCR1,
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.channels_number = 4u /* CCR1, CCR2, CCR3 and CCR4 */
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}
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},
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{
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@@ -72,19 +67,27 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
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.clock_register = STM32_RCC_APB1LENR,
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.clock_bit = RCC_APB1LENR_TIM4EN,
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.clock_freq = STM32_APB1_TIM4_CLKIN,
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.first_channel_index = 4,
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.last_channel_index = 4,
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.handler = io_timer_handler1,
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.vectorno = STM32_IRQ_TIM4,
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.dshot = {
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.dma_base = STM32_DMA1_BASE,
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.dmamap = DMAMAP_DMA12_TIM4UP_0,
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.start_ccr_register = TIM_DMABASE_CCR2,
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.channels_number = 1u /* CCR2 */
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}
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},
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};
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__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
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.element = {
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{
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.first_channel_index = 0,
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.channel_count = 4,
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},
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{
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.first_channel_index = 4,
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.channel_count = 1,
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}
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}
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};
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__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
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{
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.gpio_out = GPIO_TIM1_CH4OUT,
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@@ -56,15 +56,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
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.clock_register = STM32_RCC_APB1ENR,
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.clock_bit = RCC_APB1ENR_TIM3EN,
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.clock_freq = STM32_APB1_TIM3_CLKIN,
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.first_channel_index = 0,
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.last_channel_index = 1,
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.handler = io_timer_handler0,
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.vectorno = STM32_IRQ_TIM3,
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.dshot = {
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.dma_base = STM32_DMA1_BASE,
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.dmamap = DMAMAP_TIM3_UP,
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.start_ccr_register = TIM_DMABASE_CCR3,
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.channels_number = 2u /* CCR3 and CCR4 */
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}
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},
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{
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@@ -72,15 +67,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
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.clock_register = STM32_RCC_APB2ENR,
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.clock_bit = RCC_APB2ENR_TIM1EN,
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.clock_freq = STM32_APB2_TIM1_CLKIN,
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.first_channel_index = 2,
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.last_channel_index = 3,
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.handler = io_timer_handler1,
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.vectorno = STM32_IRQ_TIM1CC,
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.dshot = {
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.dma_base = STM32_DMA2_BASE,
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.dmamap = DMAMAP_TIM1_UP,
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.start_ccr_register = TIM_DMABASE_CCR1,
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.channels_number = 2u /* CCR1 and CCR2 */
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}
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},
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{
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@@ -88,15 +78,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
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.clock_register = STM32_RCC_APB2ENR,
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.clock_bit = RCC_APB2ENR_TIM8EN,
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.clock_freq = STM32_APB2_TIM8_CLKIN,
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.first_channel_index = 4,
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.last_channel_index = 4,
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.handler = io_timer_handler2,
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.vectorno = STM32_IRQ_TIM8CC,
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.dshot = {
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.dma_base = STM32_DMA2_BASE,
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.dmamap = DMAMAP_TIM8_UP,
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.start_ccr_register = TIM_DMABASE_CCR4,
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.channels_number = 1u /* CCR4 */
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}
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},
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{
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@@ -104,19 +89,35 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
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.clock_register = STM32_RCC_APB1ENR,
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.clock_bit = RCC_APB1ENR_TIM5EN,
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.clock_freq = STM32_APB1_TIM5_CLKIN,
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.first_channel_index = 5,
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.last_channel_index = 5,
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.handler = io_timer_handler3,
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.vectorno = STM32_IRQ_TIM5,
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.dshot = {
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.dma_base = STM32_DMA1_BASE,
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.dmamap = DMAMAP_TIM5_UP_2,
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.start_ccr_register = TIM_DMABASE_CCR4,
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.channels_number = 1u /* CCR4 */
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}
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}
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};
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__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
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.element = {
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{
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.first_channel_index = 0,
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.channel_count = 2,
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},
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{
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.first_channel_index = 2,
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.channel_count = 2,
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},
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{
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.first_channel_index = 4,
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.channel_count = 1,
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},
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{
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.first_channel_index = 5,
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.channel_count = 1,
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},
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}
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};
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__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
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{
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.gpio_out = GPIO_TIM3_CH3OUT,
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