From 5c7a9204a2eb5c46578e83588ee4884edb477bf9 Mon Sep 17 00:00:00 2001
From: David Sidrane <David.Sidrane@NscDg.com>
Date: Thu, 1 Apr 2021 10:38:58 -0700
Subject: [PATCH] mro ctrl-zero-h7-oem:Add remaining SRAM4 & DTCM to heap

---
 boards/mro/ctrl-zero-h7-oem/nuttx-config/nsh/defconfig     | 6 ++----
 boards/mro/ctrl-zero-h7-oem/nuttx-config/scripts/script.ld | 6 +++++-
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/boards/mro/ctrl-zero-h7-oem/nuttx-config/nsh/defconfig b/boards/mro/ctrl-zero-h7-oem/nuttx-config/nsh/defconfig
index 5c9cb55a07..932842c900 100644
--- a/boards/mro/ctrl-zero-h7-oem/nuttx-config/nsh/defconfig
+++ b/boards/mro/ctrl-zero-h7-oem/nuttx-config/nsh/defconfig
@@ -90,7 +90,7 @@ CONFIG_MEMSET_OPTSPEED=y
 CONFIG_MMCSD=y
 CONFIG_MMCSD_SDIO=y
 CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE=y
-CONFIG_MM_REGIONS=3
+CONFIG_MM_REGIONS=4
 CONFIG_MTD=y
 CONFIG_MTD_BYTE_WRITE=y
 CONFIG_MTD_PARTITION=y
@@ -165,8 +165,6 @@ CONFIG_STM32H7_BKPSRAM=y
 CONFIG_STM32H7_DMA1=y
 CONFIG_STM32H7_DMA2=y
 CONFIG_STM32H7_DMACAPABLE=y
-CONFIG_STM32H7_DTCMEXCLUDE=y
-CONFIG_STM32H7_DTCM_PROCFS=y
 CONFIG_STM32H7_FLOWCONTROL_BROKEN=y
 CONFIG_STM32H7_I2C1=y
 CONFIG_STM32H7_I2C3=y
@@ -219,8 +217,8 @@ CONFIG_UART7_RXBUFSIZE=600
 CONFIG_UART7_TXBUFSIZE=1500
 CONFIG_UART8_BAUD=57600
 CONFIG_UART8_RXBUFSIZE=600
-CONFIG_UART8_TXBUFSIZE=1500
 CONFIG_UART8_SERIAL_CONSOLE=y
+CONFIG_UART8_TXBUFSIZE=1500
 CONFIG_USART2_BAUD=57600
 CONFIG_USART2_IFLOWCONTROL=y
 CONFIG_USART2_OFLOWCONTROL=y
diff --git a/boards/mro/ctrl-zero-h7-oem/nuttx-config/scripts/script.ld b/boards/mro/ctrl-zero-h7-oem/nuttx-config/scripts/script.ld
index c60859c051..50f6307bc5 100644
--- a/boards/mro/ctrl-zero-h7-oem/nuttx-config/scripts/script.ld
+++ b/boards/mro/ctrl-zero-h7-oem/nuttx-config/scripts/script.ld
@@ -199,8 +199,12 @@ SECTIONS
 	} > AXI_SRAM
 
 	/* Emit the the D3 power domain section for locating BDMA data */
-	.sram4 (NOLOAD) :
+
+	.sram4_reserve (NOLOAD) :
 	{
+		*(.sram4)
+		. = ALIGN(4);
+		_sram4_heap_start = ABSOLUTE(.);
 	} > SRAM4