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Finishes the PWM driver for the STM32

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git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4206 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
2011-12-20 18:28:50 +00:00
parent 025c867f10
commit 5a714f6d99
9 changed files with 119 additions and 23 deletions
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16
nuttx/configs/stm3240g-eval/README.txt
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@@ -14,6 +14,7 @@ Contents
- STM3240G-EVAL-specific Configuration Options
- LEDs
- Ethernet
- PWM
- Configurations
Development Environment
@@ -203,6 +204,21 @@ events as follows:
on a small proportion of the time.
*** LED2 may also flicker normally if signals are processed.
PWM
===
The STM3240G-Eval has no real on-board PWM devices, but the board can be configured to output
a pulse train using TIM4 CH2. This pin is used by FSMC is connect to CN5 just for this
purpose:
PD13 FSMC_A18 / MC_TIM4_CH2 pin 33 (EnB)
FSMC must be disabled in this case! PD13 is available at:
Daughterboard Extension Connector, CN3, pin 32 - available
TFT LCD Connector, CN19, pin 17 -- not available without removing the LCD.
Motor Control Connector CN15, pin 33 -- no available unless to connect SB14.
STM3240G-EVAL-specific Configuration Options
============================================

24
nuttx/configs/stm3240g-eval/include/board.h
View File

@@ -126,14 +126,34 @@
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
/* Timers driven from APB1 will be twice PCLK1 */
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
/* Timers driven from APB12will be twice PCLK2 */
#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY)
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1