mirror of
https://gitee.com/xiaohuolufeihua/bizhang_-obav.git
synced 2026-05-21 01:12:11 +00:00
icm20948: accumulated minor improvements and cleanup
- remove interrupt perf counter and instead only count misses - minor style changes to stay in sync with the other Invensense drivers
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@@ -51,7 +51,7 @@ ICM20948::ICM20948(I2CSPIBusOption bus_option, int bus, uint32_t device, enum Ro
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_px4_gyro(get_device_id(), ORB_PRIO_DEFAULT, rotation)
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{
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if (drdy_gpio != 0) {
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_drdy_interval_perf = perf_alloc(PC_INTERVAL, MODULE_NAME": DRDY interval");
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_drdy_missed_perf = perf_alloc(PC_COUNT, MODULE_NAME": DRDY missed");
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}
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ConfigureSampleRate(_px4_gyro.get_max_rate_hz());
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@@ -82,7 +82,7 @@ ICM20948::~ICM20948()
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perf_free(_fifo_empty_perf);
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perf_free(_fifo_overflow_perf);
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perf_free(_fifo_reset_perf);
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perf_free(_drdy_interval_perf);
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perf_free(_drdy_missed_perf);
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delete _slave_ak09916_magnetometer;
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}
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@@ -125,7 +125,7 @@ void ICM20948::print_status()
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perf_print_counter(_fifo_empty_perf);
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perf_print_counter(_fifo_overflow_perf);
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perf_print_counter(_fifo_reset_perf);
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perf_print_counter(_drdy_interval_perf);
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perf_print_counter(_drdy_missed_perf);
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if (_slave_ak09916_magnetometer) {
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@@ -154,7 +154,7 @@ void ICM20948::RunImpl()
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// PWR_MGMT_1: Device Reset
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RegisterWrite(Register::BANK_0::PWR_MGMT_1, PWR_MGMT_1_BIT::DEVICE_RESET);
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_reset_timestamp = now;
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_consecutive_failures = 0;
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_failure_count = 0;
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_state = STATE::WAIT_FOR_RESET;
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ScheduleDelayed(100_ms);
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break;
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@@ -231,8 +231,8 @@ void ICM20948::RunImpl()
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case STATE::FIFO_READ: {
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if (_data_ready_interrupt_enabled) {
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// scheduled from interrupt if _drdy_fifo_read_samples was set
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if (_drdy_fifo_read_samples.fetch_and(0) == _fifo_gyro_samples) {
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perf_count_interval(_drdy_interval_perf, now);
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if (_drdy_fifo_read_samples.fetch_and(0) != _fifo_gyro_samples) {
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perf_count(_drdy_missed_perf);
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}
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// push backup schedule back
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@@ -263,22 +263,25 @@ void ICM20948::RunImpl()
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} else if (samples >= 1) {
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if (FIFORead(now, samples)) {
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success = true;
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_consecutive_failures = 0;
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if (_failure_count > 0) {
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_failure_count--;
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}
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}
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}
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}
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if (!success) {
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_consecutive_failures++;
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_failure_count++;
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// full reset if things are failing consistently
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if (_consecutive_failures > 10) {
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if (_failure_count > 10) {
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Reset();
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return;
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}
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}
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if (!success || hrt_elapsed_time(&_last_config_check_timestamp) > 10_ms) {
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if (!success || hrt_elapsed_time(&_last_config_check_timestamp) > 100_ms) {
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// check configuration registers periodically or immediately following any failure
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if (RegisterCheck(_register_bank0_cfg[_checked_register_bank0])
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&& RegisterCheck(_register_bank2_cfg[_checked_register_bank2])
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@@ -442,12 +445,12 @@ int ICM20948::DataReadyInterruptCallback(int irq, void *context, void *arg)
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void ICM20948::DataReady()
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{
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const uint8_t count = _drdy_count.fetch_add(1) + 1;
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uint8_t expected = 0;
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uint32_t expected = 0;
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// at least the required number of samples in the FIFO
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if ((count >= _fifo_gyro_samples) && _drdy_fifo_read_samples.compare_exchange(&expected, _fifo_gyro_samples)) {
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if (((_drdy_count.fetch_add(1) + 1) >= _fifo_gyro_samples)
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&& _drdy_fifo_read_samples.compare_exchange(&expected, _fifo_gyro_samples)) {
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_drdy_count.store(0);
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ScheduleNow();
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}
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@@ -163,17 +163,17 @@ private:
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perf_counter_t _fifo_empty_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO empty")};
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perf_counter_t _fifo_overflow_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO overflow")};
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perf_counter_t _fifo_reset_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO reset")};
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perf_counter_t _drdy_interval_perf{nullptr};
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perf_counter_t _drdy_missed_perf{nullptr};
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hrt_abstime _reset_timestamp{0};
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hrt_abstime _last_config_check_timestamp{0};
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hrt_abstime _temperature_update_timestamp{0};
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unsigned _consecutive_failures{0};
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int _failure_count{0};
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enum REG_BANK_SEL_BIT _last_register_bank {REG_BANK_SEL_BIT::USER_BANK_0};
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px4::atomic<uint8_t> _drdy_fifo_read_samples{0};
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px4::atomic<uint8_t> _drdy_count{0};
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px4::atomic<uint32_t> _drdy_fifo_read_samples{0};
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px4::atomic<uint32_t> _drdy_count{0};
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bool _data_ready_interrupt_enabled{false};
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enum class STATE : uint8_t {
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@@ -186,7 +186,7 @@ private:
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STATE _state{STATE::RESET};
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uint16_t _fifo_empty_interval_us{1250}; // default 1250 us / 800 Hz transfer interval
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uint8_t _fifo_gyro_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / GYRO_RATE))};
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uint32_t _fifo_gyro_samples{static_cast<uint32_t>(_fifo_empty_interval_us / (1000000 / GYRO_RATE))};
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uint8_t _checked_register_bank0{0};
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static constexpr uint8_t size_register_bank0_cfg{6};
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@@ -86,7 +86,7 @@ void ICM20948_AK09916::Run()
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// CNTL3 SRST: Soft reset
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_icm20948.I2CSlaveRegisterWrite(I2C_ADDRESS_DEFAULT, (uint8_t)Register::CNTL3, CNTL3_BIT::SRST);
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_reset_timestamp = hrt_absolute_time();
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_consecutive_failures = 0;
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_failure_count = 0;
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_state = STATE::READ_WHO_AM_I;
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ScheduleDelayed(100_ms);
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break;
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@@ -146,15 +146,17 @@ void ICM20948_AK09916::Run()
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success = true;
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_consecutive_failures = 0;
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if (_failure_count > 0) {
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_failure_count--;
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}
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}
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}
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if (!success) {
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perf_count(_bad_transfer_perf);
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_consecutive_failures++;
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_failure_count++;
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if (_consecutive_failures > 10) {
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if (_failure_count > 10) {
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Reset();
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return;
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}
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@@ -93,7 +93,7 @@ private:
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hrt_abstime _reset_timestamp{0};
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hrt_abstime _last_config_check_timestamp{0};
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unsigned _consecutive_failures{0};
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int _failure_count{0};
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enum class STATE : uint8_t {
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RESET,
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