2020-05-22 00:09:30 -04:00
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/****************************************************************************
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*
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* Copyright (c) 2020 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#include "ICM20948.hpp"
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#include "AKM_AK09916_registers.hpp"
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using namespace time_literals;
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static constexpr int16_t combine(uint8_t msb, uint8_t lsb)
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{
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return (msb << 8u) | lsb;
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}
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ICM20948::ICM20948(I2CSPIBusOption bus_option, int bus, uint32_t device, enum Rotation rotation, int bus_frequency,
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spi_mode_e spi_mode, spi_drdy_gpio_t drdy_gpio, bool enable_magnetometer) :
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SPI(DRV_IMU_DEVTYPE_ICM20948, MODULE_NAME, bus, device, spi_mode, bus_frequency),
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I2CSPIDriver(MODULE_NAME, px4::device_bus_to_wq(get_device_id()), bus_option, bus),
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_drdy_gpio(drdy_gpio),
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2020-08-16 22:21:04 -04:00
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_px4_accel(get_device_id(), rotation),
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_px4_gyro(get_device_id(), rotation)
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2020-05-22 00:09:30 -04:00
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{
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2020-06-18 11:11:34 -04:00
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if (drdy_gpio != 0) {
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2020-07-09 11:33:41 -04:00
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_drdy_missed_perf = perf_alloc(PC_COUNT, MODULE_NAME": DRDY missed");
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2020-06-18 11:11:34 -04:00
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}
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2020-05-22 00:09:30 -04:00
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ConfigureSampleRate(_px4_gyro.get_max_rate_hz());
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if (enable_magnetometer) {
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_slave_ak09916_magnetometer = new AKM_AK09916::ICM20948_AK09916(*this, rotation);
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if (_slave_ak09916_magnetometer) {
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for (auto &r : _register_bank3_cfg) {
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if (r.reg == Register::BANK_3::I2C_SLV4_CTRL) {
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r.set_bits = I2C_SLV4_CTRL_BIT::I2C_MST_DLY;
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} else if (r.reg == Register::BANK_3::I2C_MST_CTRL) {
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r.set_bits = I2C_MST_CTRL_BIT::I2C_MST_P_NSR | I2C_MST_CTRL_BIT::I2C_MST_CLK_400_kHz;
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} else if (r.reg == Register::BANK_3::I2C_MST_DELAY_CTRL) {
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r.set_bits = I2C_MST_DELAY_CTRL_BIT::I2C_SLVX_DLY_EN;
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}
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}
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}
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}
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}
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ICM20948::~ICM20948()
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{
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perf_free(_bad_register_perf);
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perf_free(_bad_transfer_perf);
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perf_free(_fifo_empty_perf);
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perf_free(_fifo_overflow_perf);
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perf_free(_fifo_reset_perf);
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2020-07-09 11:33:41 -04:00
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perf_free(_drdy_missed_perf);
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2020-05-22 00:09:30 -04:00
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delete _slave_ak09916_magnetometer;
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}
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int ICM20948::init()
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{
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int ret = SPI::init();
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if (ret != PX4_OK) {
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DEVICE_DEBUG("SPI::init failed (%i)", ret);
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return ret;
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}
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return Reset() ? 0 : -1;
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}
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bool ICM20948::Reset()
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{
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_state = STATE::RESET;
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2020-06-18 11:11:34 -04:00
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DataReadyInterruptDisable();
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2020-05-22 00:09:30 -04:00
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ScheduleClear();
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ScheduleNow();
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return true;
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}
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void ICM20948::exit_and_cleanup()
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{
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DataReadyInterruptDisable();
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I2CSPIDriverBase::exit_and_cleanup();
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}
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void ICM20948::print_status()
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{
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I2CSPIDriverBase::print_status();
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2020-06-18 11:11:34 -04:00
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PX4_INFO("FIFO empty interval: %d us (%.1f Hz)", _fifo_empty_interval_us, 1e6 / _fifo_empty_interval_us);
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2020-05-22 00:09:30 -04:00
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perf_print_counter(_bad_register_perf);
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perf_print_counter(_bad_transfer_perf);
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perf_print_counter(_fifo_empty_perf);
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perf_print_counter(_fifo_overflow_perf);
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perf_print_counter(_fifo_reset_perf);
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2020-07-09 11:33:41 -04:00
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perf_print_counter(_drdy_missed_perf);
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2020-05-22 00:09:30 -04:00
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if (_slave_ak09916_magnetometer) {
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_slave_ak09916_magnetometer->PrintInfo();
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}
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}
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int ICM20948::probe()
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{
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const uint8_t whoami = RegisterRead(Register::BANK_0::WHO_AM_I);
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if (whoami != WHOAMI) {
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DEVICE_DEBUG("unexpected WHO_AM_I 0x%02x", whoami);
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return PX4_ERROR;
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}
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return PX4_OK;
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}
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void ICM20948::RunImpl()
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{
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2020-06-18 11:11:34 -04:00
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const hrt_abstime now = hrt_absolute_time();
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2020-05-22 00:09:30 -04:00
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switch (_state) {
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case STATE::RESET:
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// PWR_MGMT_1: Device Reset
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RegisterWrite(Register::BANK_0::PWR_MGMT_1, PWR_MGMT_1_BIT::DEVICE_RESET);
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2020-06-18 11:11:34 -04:00
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_reset_timestamp = now;
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2020-07-09 11:33:41 -04:00
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_failure_count = 0;
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2020-05-22 00:09:30 -04:00
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_state = STATE::WAIT_FOR_RESET;
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2020-06-18 11:11:34 -04:00
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ScheduleDelayed(100_ms);
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2020-05-22 00:09:30 -04:00
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break;
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case STATE::WAIT_FOR_RESET:
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// The reset value is 0x00 for all registers other than the registers below
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if ((RegisterRead(Register::BANK_0::WHO_AM_I) == WHOAMI)
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&& (RegisterRead(Register::BANK_0::PWR_MGMT_1) == 0x41)) {
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2020-06-18 11:11:34 -04:00
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// Wakeup and reset
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RegisterWrite(Register::BANK_0::PWR_MGMT_1, PWR_MGMT_1_BIT::CLKSEL_0);
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RegisterWrite(Register::BANK_0::USER_CTRL,
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USER_CTRL_BIT::I2C_MST_EN | USER_CTRL_BIT::I2C_IF_DIS | USER_CTRL_BIT::SRAM_RST | USER_CTRL_BIT::I2C_MST_RST);
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2020-05-22 00:09:30 -04:00
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// if reset succeeded then configure
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_state = STATE::CONFIGURE;
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2020-06-18 11:11:34 -04:00
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ScheduleDelayed(100_ms);
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2020-05-22 00:09:30 -04:00
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} else {
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// RESET not complete
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2020-06-18 11:11:34 -04:00
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if (hrt_elapsed_time(&_reset_timestamp) > 1000_ms) {
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2020-05-22 00:09:30 -04:00
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PX4_DEBUG("Reset failed, retrying");
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_state = STATE::RESET;
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ScheduleDelayed(100_ms);
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} else {
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2021-04-04 21:18:16 -04:00
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PX4_DEBUG("Reset not complete, check again in 100 ms");
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ScheduleDelayed(100_ms);
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2020-05-22 00:09:30 -04:00
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}
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}
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break;
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case STATE::CONFIGURE:
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if (Configure()) {
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// start AK09916 magnetometer (I2C aux)
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if (_slave_ak09916_magnetometer) {
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_slave_ak09916_magnetometer->Reset();
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}
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// if configure succeeded then start reading from FIFO
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_state = STATE::FIFO_READ;
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if (DataReadyInterruptConfigure()) {
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_data_ready_interrupt_enabled = true;
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// backup schedule as a watchdog timeout
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2020-06-18 11:11:34 -04:00
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ScheduleDelayed(100_ms);
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2020-05-22 00:09:30 -04:00
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} else {
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_data_ready_interrupt_enabled = false;
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ScheduleOnInterval(_fifo_empty_interval_us, _fifo_empty_interval_us);
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}
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FIFOReset();
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} else {
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2020-06-18 11:11:34 -04:00
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// CONFIGURE not complete
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if (hrt_elapsed_time(&_reset_timestamp) > 1000_ms) {
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PX4_DEBUG("Configure failed, resetting");
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_state = STATE::RESET;
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} else {
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PX4_DEBUG("Configure failed, retrying");
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}
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ScheduleDelayed(100_ms);
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2020-05-22 00:09:30 -04:00
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}
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break;
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case STATE::FIFO_READ: {
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if (_data_ready_interrupt_enabled) {
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2020-06-18 11:11:34 -04:00
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// scheduled from interrupt if _drdy_fifo_read_samples was set
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2020-07-09 11:33:41 -04:00
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if (_drdy_fifo_read_samples.fetch_and(0) != _fifo_gyro_samples) {
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perf_count(_drdy_missed_perf);
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2020-05-22 00:09:30 -04:00
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}
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2020-06-18 11:11:34 -04:00
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// push backup schedule back
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ScheduleDelayed(_fifo_empty_interval_us * 2);
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2020-05-22 00:09:30 -04:00
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}
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2020-06-18 11:11:34 -04:00
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// always check current FIFO count
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bool success = false;
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const uint16_t fifo_count = FIFOReadCount();
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2020-05-22 00:09:30 -04:00
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2020-06-18 11:11:34 -04:00
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if (fifo_count >= FIFO::SIZE) {
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FIFOReset();
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perf_count(_fifo_overflow_perf);
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} else if (fifo_count == 0) {
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perf_count(_fifo_empty_perf);
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2020-05-22 00:09:30 -04:00
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2020-06-18 11:11:34 -04:00
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} else {
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// FIFO count (size in bytes) should be a multiple of the FIFO::DATA structure
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const uint8_t samples = (fifo_count / sizeof(FIFO::DATA) / SAMPLES_PER_TRANSFER) *
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SAMPLES_PER_TRANSFER; // round down to nearest
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if (samples > FIFO_MAX_SAMPLES) {
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// not technically an overflow, but more samples than we expected or can publish
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FIFOReset();
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perf_count(_fifo_overflow_perf);
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} else if (samples >= 1) {
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if (FIFORead(now, samples)) {
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success = true;
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2020-07-09 11:33:41 -04:00
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if (_failure_count > 0) {
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_failure_count--;
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}
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2020-06-18 11:11:34 -04:00
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}
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}
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2020-05-22 00:09:30 -04:00
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}
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2020-06-18 11:11:34 -04:00
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if (!success) {
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2020-07-09 11:33:41 -04:00
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_failure_count++;
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2020-05-22 00:09:30 -04:00
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2020-06-18 11:11:34 -04:00
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// full reset if things are failing consistently
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2020-07-09 11:33:41 -04:00
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if (_failure_count > 10) {
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2020-06-18 11:11:34 -04:00
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Reset();
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return;
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2020-05-22 00:09:30 -04:00
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}
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}
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2020-07-09 11:33:41 -04:00
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if (!success || hrt_elapsed_time(&_last_config_check_timestamp) > 100_ms) {
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2020-06-18 11:11:34 -04:00
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// check configuration registers periodically or immediately following any failure
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if (RegisterCheck(_register_bank0_cfg[_checked_register_bank0])
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&& RegisterCheck(_register_bank2_cfg[_checked_register_bank2])
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&& RegisterCheck(_register_bank3_cfg[_checked_register_bank3])
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2020-05-22 00:09:30 -04:00
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) {
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2020-06-18 11:11:34 -04:00
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_last_config_check_timestamp = now;
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2020-05-22 00:09:30 -04:00
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_checked_register_bank0 = (_checked_register_bank0 + 1) % size_register_bank0_cfg;
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_checked_register_bank2 = (_checked_register_bank2 + 1) % size_register_bank2_cfg;
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_checked_register_bank3 = (_checked_register_bank3 + 1) % size_register_bank3_cfg;
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|
|
|
|
|
|
|
} else {
|
2020-06-18 11:11:34 -04:00
|
|
|
// register check failed, force reset
|
|
|
|
|
perf_count(_bad_register_perf);
|
|
|
|
|
Reset();
|
2020-05-22 00:09:30 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
} else {
|
2020-06-18 11:11:34 -04:00
|
|
|
// periodically update temperature (~1 Hz)
|
|
|
|
|
if (hrt_elapsed_time(&_temperature_update_timestamp) >= 1_s) {
|
2020-05-22 00:09:30 -04:00
|
|
|
UpdateTemperature();
|
2020-06-18 11:11:34 -04:00
|
|
|
_temperature_update_timestamp = now;
|
2020-05-22 00:09:30 -04:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ICM20948::ConfigureAccel()
|
|
|
|
|
{
|
|
|
|
|
const uint8_t ACCEL_FS_SEL = RegisterRead(Register::BANK_2::ACCEL_CONFIG) & (Bit2 | Bit1); // 2:1 ACCEL_FS_SEL[1:0]
|
|
|
|
|
|
|
|
|
|
switch (ACCEL_FS_SEL) {
|
|
|
|
|
case ACCEL_FS_SEL_2G:
|
|
|
|
|
_px4_accel.set_scale(CONSTANTS_ONE_G / 16384.f);
|
|
|
|
|
_px4_accel.set_range(2.f * CONSTANTS_ONE_G);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case ACCEL_FS_SEL_4G:
|
|
|
|
|
_px4_accel.set_scale(CONSTANTS_ONE_G / 8192.f);
|
|
|
|
|
_px4_accel.set_range(4.f * CONSTANTS_ONE_G);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case ACCEL_FS_SEL_8G:
|
|
|
|
|
_px4_accel.set_scale(CONSTANTS_ONE_G / 4096.f);
|
|
|
|
|
_px4_accel.set_range(8.f * CONSTANTS_ONE_G);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case ACCEL_FS_SEL_16G:
|
|
|
|
|
_px4_accel.set_scale(CONSTANTS_ONE_G / 2048.f);
|
|
|
|
|
_px4_accel.set_range(16.f * CONSTANTS_ONE_G);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ICM20948::ConfigureGyro()
|
|
|
|
|
{
|
|
|
|
|
const uint8_t GYRO_FS_SEL = RegisterRead(Register::BANK_2::GYRO_CONFIG_1) & (Bit2 | Bit1); // 2:1 GYRO_FS_SEL[1:0]
|
|
|
|
|
|
2020-06-12 11:20:43 -04:00
|
|
|
float range_dps = 0.f;
|
|
|
|
|
|
2020-05-22 00:09:30 -04:00
|
|
|
switch (GYRO_FS_SEL) {
|
|
|
|
|
case GYRO_FS_SEL_250_DPS:
|
2020-06-12 11:20:43 -04:00
|
|
|
range_dps = 250.f;
|
2020-05-22 00:09:30 -04:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case GYRO_FS_SEL_500_DPS:
|
2020-06-12 11:20:43 -04:00
|
|
|
range_dps = 500.f;
|
2020-05-22 00:09:30 -04:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case GYRO_FS_SEL_1000_DPS:
|
2020-06-12 11:20:43 -04:00
|
|
|
range_dps = 1000.f;
|
2020-05-22 00:09:30 -04:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case GYRO_FS_SEL_2000_DPS:
|
2020-06-12 11:20:43 -04:00
|
|
|
range_dps = 2000.f;
|
2020-05-22 00:09:30 -04:00
|
|
|
break;
|
|
|
|
|
}
|
2020-06-12 11:20:43 -04:00
|
|
|
|
|
|
|
|
_px4_gyro.set_scale(math::radians(range_dps / 32768.f));
|
|
|
|
|
_px4_gyro.set_range(math::radians(range_dps));
|
2020-05-22 00:09:30 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ICM20948::ConfigureSampleRate(int sample_rate)
|
|
|
|
|
{
|
|
|
|
|
// round down to nearest FIFO sample dt * SAMPLES_PER_TRANSFER
|
2020-06-18 11:11:34 -04:00
|
|
|
const float min_interval = FIFO_SAMPLE_DT * SAMPLES_PER_TRANSFER;
|
2020-05-22 00:09:30 -04:00
|
|
|
_fifo_empty_interval_us = math::max(roundf((1e6f / (float)sample_rate) / min_interval) * min_interval, min_interval);
|
|
|
|
|
|
|
|
|
|
_fifo_gyro_samples = roundf(math::min((float)_fifo_empty_interval_us / (1e6f / GYRO_RATE), (float)FIFO_MAX_SAMPLES));
|
|
|
|
|
|
|
|
|
|
// recompute FIFO empty interval (us) with actual gyro sample limit
|
|
|
|
|
_fifo_empty_interval_us = _fifo_gyro_samples * (1e6f / GYRO_RATE);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ICM20948::SelectRegisterBank(enum REG_BANK_SEL_BIT bank)
|
|
|
|
|
{
|
|
|
|
|
if (bank != _last_register_bank) {
|
|
|
|
|
// select BANK_0
|
|
|
|
|
uint8_t cmd_bank_sel[2] {};
|
|
|
|
|
cmd_bank_sel[0] = static_cast<uint8_t>(Register::BANK_0::REG_BANK_SEL);
|
|
|
|
|
cmd_bank_sel[1] = bank;
|
|
|
|
|
transfer(cmd_bank_sel, cmd_bank_sel, sizeof(cmd_bank_sel));
|
|
|
|
|
|
|
|
|
|
_last_register_bank = bank;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool ICM20948::Configure()
|
|
|
|
|
{
|
2020-06-18 11:11:34 -04:00
|
|
|
// first set and clear all configured register bits
|
|
|
|
|
for (const auto ®_cfg : _register_bank0_cfg) {
|
|
|
|
|
RegisterSetAndClearBits(reg_cfg.reg, reg_cfg.set_bits, reg_cfg.clear_bits);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (const auto ®_cfg : _register_bank2_cfg) {
|
|
|
|
|
RegisterSetAndClearBits(reg_cfg.reg, reg_cfg.set_bits, reg_cfg.clear_bits);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (const auto ®_cfg : _register_bank3_cfg) {
|
|
|
|
|
RegisterSetAndClearBits(reg_cfg.reg, reg_cfg.set_bits, reg_cfg.clear_bits);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// now check that all are configured
|
2020-05-22 00:09:30 -04:00
|
|
|
bool success = true;
|
|
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
for (const auto ®_cfg : _register_bank0_cfg) {
|
|
|
|
|
if (!RegisterCheck(reg_cfg)) {
|
2020-05-22 00:09:30 -04:00
|
|
|
success = false;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
for (const auto ®_cfg : _register_bank2_cfg) {
|
|
|
|
|
if (!RegisterCheck(reg_cfg)) {
|
2020-05-22 00:09:30 -04:00
|
|
|
success = false;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
for (const auto ®_cfg : _register_bank3_cfg) {
|
|
|
|
|
if (!RegisterCheck(reg_cfg)) {
|
2020-05-22 00:09:30 -04:00
|
|
|
success = false;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ConfigureAccel();
|
|
|
|
|
ConfigureGyro();
|
|
|
|
|
|
|
|
|
|
return success;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int ICM20948::DataReadyInterruptCallback(int irq, void *context, void *arg)
|
|
|
|
|
{
|
|
|
|
|
static_cast<ICM20948 *>(arg)->DataReady();
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ICM20948::DataReady()
|
|
|
|
|
{
|
2020-07-09 11:33:41 -04:00
|
|
|
uint32_t expected = 0;
|
2020-05-22 00:09:30 -04:00
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
// at least the required number of samples in the FIFO
|
2020-07-09 11:33:41 -04:00
|
|
|
if (((_drdy_count.fetch_add(1) + 1) >= _fifo_gyro_samples)
|
|
|
|
|
&& _drdy_fifo_read_samples.compare_exchange(&expected, _fifo_gyro_samples)) {
|
|
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
_drdy_count.store(0);
|
2020-05-22 00:09:30 -04:00
|
|
|
ScheduleNow();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool ICM20948::DataReadyInterruptConfigure()
|
|
|
|
|
{
|
2020-06-18 11:11:34 -04:00
|
|
|
// TODO: enable data ready interrupt
|
|
|
|
|
return false;
|
|
|
|
|
#if 0
|
|
|
|
|
|
2020-05-22 00:09:30 -04:00
|
|
|
if (_drdy_gpio == 0) {
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Setup data ready on falling edge
|
|
|
|
|
return px4_arch_gpiosetevent(_drdy_gpio, false, true, true, &DataReadyInterruptCallback, this) == 0;
|
2020-06-18 11:11:34 -04:00
|
|
|
#endif
|
2020-05-22 00:09:30 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool ICM20948::DataReadyInterruptDisable()
|
|
|
|
|
{
|
2020-06-18 11:11:34 -04:00
|
|
|
// TODO: enable data ready interrupt
|
|
|
|
|
return false;
|
|
|
|
|
#if 0
|
|
|
|
|
|
2020-05-22 00:09:30 -04:00
|
|
|
if (_drdy_gpio == 0) {
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return px4_arch_gpiosetevent(_drdy_gpio, false, false, false, nullptr, nullptr) == 0;
|
2020-06-18 11:11:34 -04:00
|
|
|
#endif
|
2020-05-22 00:09:30 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template <typename T>
|
2020-06-18 11:11:34 -04:00
|
|
|
bool ICM20948::RegisterCheck(const T ®_cfg)
|
2020-05-22 00:09:30 -04:00
|
|
|
{
|
|
|
|
|
bool success = true;
|
|
|
|
|
|
|
|
|
|
const uint8_t reg_value = RegisterRead(reg_cfg.reg);
|
|
|
|
|
|
|
|
|
|
if (reg_cfg.set_bits && ((reg_value & reg_cfg.set_bits) != reg_cfg.set_bits)) {
|
|
|
|
|
PX4_DEBUG("0x%02hhX: 0x%02hhX (0x%02hhX not set)", (uint8_t)reg_cfg.reg, reg_value, reg_cfg.set_bits);
|
|
|
|
|
success = false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (reg_cfg.clear_bits && ((reg_value & reg_cfg.clear_bits) != 0)) {
|
|
|
|
|
PX4_DEBUG("0x%02hhX: 0x%02hhX (0x%02hhX not cleared)", (uint8_t)reg_cfg.reg, reg_value, reg_cfg.clear_bits);
|
|
|
|
|
success = false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return success;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template <typename T>
|
|
|
|
|
uint8_t ICM20948::RegisterRead(T reg)
|
|
|
|
|
{
|
|
|
|
|
uint8_t cmd[2] {};
|
|
|
|
|
cmd[0] = static_cast<uint8_t>(reg) | DIR_READ;
|
2020-06-18 11:11:34 -04:00
|
|
|
SelectRegisterBank(reg);
|
2020-05-22 00:09:30 -04:00
|
|
|
transfer(cmd, cmd, sizeof(cmd));
|
|
|
|
|
return cmd[1];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template <typename T>
|
|
|
|
|
void ICM20948::RegisterWrite(T reg, uint8_t value)
|
|
|
|
|
{
|
|
|
|
|
uint8_t cmd[2] { (uint8_t)reg, value };
|
2020-06-18 11:11:34 -04:00
|
|
|
SelectRegisterBank(reg);
|
2020-05-22 00:09:30 -04:00
|
|
|
transfer(cmd, cmd, sizeof(cmd));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
template <typename T>
|
|
|
|
|
void ICM20948::RegisterSetAndClearBits(T reg, uint8_t setbits, uint8_t clearbits)
|
|
|
|
|
{
|
|
|
|
|
const uint8_t orig_val = RegisterRead(reg);
|
|
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
uint8_t val = (orig_val & ~clearbits) | setbits;
|
2020-05-22 00:09:30 -04:00
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
if (orig_val != val) {
|
|
|
|
|
RegisterWrite(reg, val);
|
2020-05-22 00:09:30 -04:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uint16_t ICM20948::FIFOReadCount()
|
|
|
|
|
{
|
2021-04-04 21:18:16 -04:00
|
|
|
SelectRegisterBank(REG_BANK_SEL_BIT::USER_BANK_0);
|
|
|
|
|
|
2020-05-22 00:09:30 -04:00
|
|
|
// read FIFO count
|
|
|
|
|
uint8_t fifo_count_buf[3] {};
|
|
|
|
|
fifo_count_buf[0] = static_cast<uint8_t>(Register::BANK_0::FIFO_COUNTH) | DIR_READ;
|
|
|
|
|
|
|
|
|
|
if (transfer(fifo_count_buf, fifo_count_buf, sizeof(fifo_count_buf)) != PX4_OK) {
|
|
|
|
|
perf_count(_bad_transfer_perf);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return combine(fifo_count_buf[1], fifo_count_buf[2]);
|
|
|
|
|
}
|
|
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
bool ICM20948::FIFORead(const hrt_abstime ×tamp_sample, uint8_t samples)
|
2020-05-22 00:09:30 -04:00
|
|
|
{
|
2021-04-04 21:18:16 -04:00
|
|
|
SelectRegisterBank(REG_BANK_SEL_BIT::USER_BANK_0);
|
|
|
|
|
|
2020-05-22 00:09:30 -04:00
|
|
|
FIFOTransferBuffer buffer{};
|
|
|
|
|
const size_t transfer_size = math::min(samples * sizeof(FIFO::DATA) + 3, FIFO::SIZE);
|
|
|
|
|
|
|
|
|
|
if (transfer((uint8_t *)&buffer, (uint8_t *)&buffer, transfer_size) != PX4_OK) {
|
|
|
|
|
perf_count(_bad_transfer_perf);
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
const uint16_t fifo_count_bytes = combine(buffer.FIFO_COUNTH, buffer.FIFO_COUNTL);
|
|
|
|
|
|
|
|
|
|
if (fifo_count_bytes >= FIFO::SIZE) {
|
|
|
|
|
perf_count(_fifo_overflow_perf);
|
|
|
|
|
FIFOReset();
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
const uint8_t fifo_count_samples = fifo_count_bytes / sizeof(FIFO::DATA);
|
2020-05-22 00:09:30 -04:00
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
if (fifo_count_samples == 0) {
|
|
|
|
|
perf_count(_fifo_empty_perf);
|
|
|
|
|
return false;
|
2020-05-22 00:09:30 -04:00
|
|
|
}
|
|
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
const uint16_t valid_samples = math::min(samples, fifo_count_samples);
|
|
|
|
|
|
2020-05-22 00:09:30 -04:00
|
|
|
if (valid_samples > 0) {
|
2020-06-18 11:11:34 -04:00
|
|
|
ProcessGyro(timestamp_sample, buffer.f, valid_samples);
|
2020-05-22 00:09:30 -04:00
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
if (ProcessAccel(timestamp_sample, buffer.f, valid_samples)) {
|
2020-05-22 00:09:30 -04:00
|
|
|
return true;
|
|
|
|
|
}
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|
|
|
|
}
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|
|
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|
|
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|
|
|
return false;
|
|
|
|
|
}
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|
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void ICM20948::FIFOReset()
|
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|
|
|
{
|
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|
|
perf_count(_fifo_reset_perf);
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|
|
// FIFO_RST: reset FIFO
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RegisterSetBits(Register::BANK_0::FIFO_RST, FIFO_RST_BIT::FIFO_RESET);
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RegisterClearBits(Register::BANK_0::FIFO_RST, FIFO_RST_BIT::FIFO_RESET);
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// reset while FIFO is disabled
|
2020-06-18 11:11:34 -04:00
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|
_drdy_count.store(0);
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|
_drdy_fifo_read_samples.store(0);
|
2020-05-22 00:09:30 -04:00
|
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}
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static bool fifo_accel_equal(const FIFO::DATA &f0, const FIFO::DATA &f1)
|
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|
|
|
{
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|
|
return (memcmp(&f0.ACCEL_XOUT_H, &f1.ACCEL_XOUT_H, 6) == 0);
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}
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|
2020-06-18 11:11:34 -04:00
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bool ICM20948::ProcessAccel(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples)
|
2020-05-22 00:09:30 -04:00
|
|
|
{
|
2020-05-31 21:25:13 -04:00
|
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|
sensor_accel_fifo_s accel{};
|
2020-05-22 00:09:30 -04:00
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accel.timestamp_sample = timestamp_sample;
|
2020-06-18 11:11:34 -04:00
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accel.samples = 0;
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accel.dt = FIFO_SAMPLE_DT * SAMPLES_PER_TRANSFER;
|
2020-05-22 00:09:30 -04:00
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|
|
bool bad_data = false;
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|
|
// accel data is doubled in FIFO, but might be shifted
|
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|
|
int accel_first_sample = 1;
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|
if (samples >= 4) {
|
2020-06-18 11:11:34 -04:00
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|
if (fifo_accel_equal(fifo[0], fifo[1]) && fifo_accel_equal(fifo[2], fifo[3])) {
|
2020-05-22 00:09:30 -04:00
|
|
|
// [A0, A1, A2, A3]
|
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|
|
// A0==A1, A2==A3
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|
accel_first_sample = 1;
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|
2020-06-18 11:11:34 -04:00
|
|
|
} else if (fifo_accel_equal(fifo[1], fifo[2])) {
|
2020-05-22 00:09:30 -04:00
|
|
|
// [A0, A1, A2, A3]
|
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|
|
|
// A0, A1==A2, A3
|
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|
|
accel_first_sample = 0;
|
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|
|
|
|
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|
|
|
} else {
|
2020-06-18 11:11:34 -04:00
|
|
|
// no matching accel samples is an error
|
2020-05-22 00:09:30 -04:00
|
|
|
bad_data = true;
|
2020-06-18 11:11:34 -04:00
|
|
|
perf_count(_bad_transfer_perf);
|
2020-05-22 00:09:30 -04:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
for (int i = accel_first_sample; i < samples; i = i + SAMPLES_PER_TRANSFER) {
|
|
|
|
|
int16_t accel_x = combine(fifo[i].ACCEL_XOUT_H, fifo[i].ACCEL_XOUT_L);
|
|
|
|
|
int16_t accel_y = combine(fifo[i].ACCEL_YOUT_H, fifo[i].ACCEL_YOUT_L);
|
|
|
|
|
int16_t accel_z = combine(fifo[i].ACCEL_ZOUT_H, fifo[i].ACCEL_ZOUT_L);
|
2020-05-22 00:09:30 -04:00
|
|
|
|
|
|
|
|
// sensor's frame is +x forward, +y left, +z up
|
|
|
|
|
// flip y & z to publish right handed with z down (x forward, y right, z down)
|
2020-06-18 11:11:34 -04:00
|
|
|
accel.x[accel.samples] = accel_x;
|
|
|
|
|
accel.y[accel.samples] = (accel_y == INT16_MIN) ? INT16_MAX : -accel_y;
|
|
|
|
|
accel.z[accel.samples] = (accel_z == INT16_MIN) ? INT16_MAX : -accel_z;
|
|
|
|
|
accel.samples++;
|
2020-05-22 00:09:30 -04:00
|
|
|
}
|
|
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
_px4_accel.set_error_count(perf_event_count(_bad_register_perf) + perf_event_count(_bad_transfer_perf) +
|
|
|
|
|
perf_event_count(_fifo_empty_perf) + perf_event_count(_fifo_overflow_perf));
|
2020-05-22 00:09:30 -04:00
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
if (accel.samples > 0) {
|
|
|
|
|
_px4_accel.updateFIFO(accel);
|
|
|
|
|
}
|
2020-05-22 00:09:30 -04:00
|
|
|
|
|
|
|
|
return !bad_data;
|
|
|
|
|
}
|
|
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
void ICM20948::ProcessGyro(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples)
|
2020-05-22 00:09:30 -04:00
|
|
|
{
|
2020-05-31 21:25:13 -04:00
|
|
|
sensor_gyro_fifo_s gyro{};
|
2020-05-22 00:09:30 -04:00
|
|
|
gyro.timestamp_sample = timestamp_sample;
|
|
|
|
|
gyro.samples = samples;
|
2020-06-18 11:11:34 -04:00
|
|
|
gyro.dt = FIFO_SAMPLE_DT;
|
2020-05-22 00:09:30 -04:00
|
|
|
|
|
|
|
|
for (int i = 0; i < samples; i++) {
|
2020-06-18 11:11:34 -04:00
|
|
|
const int16_t gyro_x = combine(fifo[i].GYRO_XOUT_H, fifo[i].GYRO_XOUT_L);
|
|
|
|
|
const int16_t gyro_y = combine(fifo[i].GYRO_YOUT_H, fifo[i].GYRO_YOUT_L);
|
|
|
|
|
const int16_t gyro_z = combine(fifo[i].GYRO_ZOUT_H, fifo[i].GYRO_ZOUT_L);
|
2020-05-22 00:09:30 -04:00
|
|
|
|
|
|
|
|
// sensor's frame is +x forward, +y left, +z up
|
|
|
|
|
// flip y & z to publish right handed with z down (x forward, y right, z down)
|
|
|
|
|
gyro.x[i] = gyro_x;
|
|
|
|
|
gyro.y[i] = (gyro_y == INT16_MIN) ? INT16_MAX : -gyro_y;
|
|
|
|
|
gyro.z[i] = (gyro_z == INT16_MIN) ? INT16_MAX : -gyro_z;
|
|
|
|
|
}
|
|
|
|
|
|
2020-06-18 11:11:34 -04:00
|
|
|
_px4_gyro.set_error_count(perf_event_count(_bad_register_perf) + perf_event_count(_bad_transfer_perf) +
|
|
|
|
|
perf_event_count(_fifo_empty_perf) + perf_event_count(_fifo_overflow_perf));
|
|
|
|
|
|
2020-05-22 00:09:30 -04:00
|
|
|
_px4_gyro.updateFIFO(gyro);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ICM20948::UpdateTemperature()
|
|
|
|
|
{
|
|
|
|
|
// read current temperature
|
|
|
|
|
uint8_t temperature_buf[3] {};
|
|
|
|
|
temperature_buf[0] = static_cast<uint8_t>(Register::BANK_0::TEMP_OUT_H) | DIR_READ;
|
2020-06-18 11:11:34 -04:00
|
|
|
SelectRegisterBank(REG_BANK_SEL_BIT::USER_BANK_0);
|
2020-05-22 00:09:30 -04:00
|
|
|
|
|
|
|
|
if (transfer(temperature_buf, temperature_buf, sizeof(temperature_buf)) != PX4_OK) {
|
|
|
|
|
perf_count(_bad_transfer_perf);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const int16_t TEMP_OUT = combine(temperature_buf[1], temperature_buf[2]);
|
|
|
|
|
const float TEMP_degC = (TEMP_OUT / TEMPERATURE_SENSITIVITY) + TEMPERATURE_OFFSET;
|
|
|
|
|
|
|
|
|
|
if (PX4_ISFINITE(TEMP_degC)) {
|
|
|
|
|
_px4_accel.set_temperature(TEMP_degC);
|
|
|
|
|
_px4_gyro.set_temperature(TEMP_degC);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ICM20948::I2CSlaveRegisterWrite(uint8_t slave_i2c_addr, uint8_t reg, uint8_t val)
|
|
|
|
|
{
|
|
|
|
|
RegisterWrite(Register::BANK_3::I2C_SLV0_ADDR, slave_i2c_addr);
|
|
|
|
|
RegisterWrite(Register::BANK_3::I2C_SLV0_REG, reg);
|
|
|
|
|
RegisterWrite(Register::BANK_3::I2C_SLV0_DO, val);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ICM20948::I2CSlaveExternalSensorDataEnable(uint8_t slave_i2c_addr, uint8_t reg, uint8_t size)
|
|
|
|
|
{
|
|
|
|
|
RegisterWrite(Register::BANK_3::I2C_SLV0_ADDR, slave_i2c_addr | I2C_SLV0_ADDR_BIT::I2C_SLV0_RNW);
|
|
|
|
|
RegisterWrite(Register::BANK_3::I2C_SLV0_REG, reg);
|
|
|
|
|
RegisterWrite(Register::BANK_3::I2C_SLV0_CTRL, size | I2C_SLV0_CTRL_BIT::I2C_SLV0_EN);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool ICM20948::I2CSlaveExternalSensorDataRead(uint8_t *buffer, uint8_t length)
|
|
|
|
|
{
|
|
|
|
|
bool ret = false;
|
|
|
|
|
|
|
|
|
|
if (buffer != nullptr && length <= 24) {
|
|
|
|
|
// max EXT_SENS_DATA 24 bytes
|
|
|
|
|
uint8_t transfer_buffer[24 + 1] {};
|
|
|
|
|
transfer_buffer[0] = static_cast<uint8_t>(Register::BANK_0::EXT_SLV_SENS_DATA_00) | DIR_READ;
|
2020-06-18 11:11:34 -04:00
|
|
|
SelectRegisterBank(REG_BANK_SEL_BIT::USER_BANK_0);
|
2020-05-22 00:09:30 -04:00
|
|
|
|
|
|
|
|
if (transfer(transfer_buffer, transfer_buffer, length + 1) == PX4_OK) {
|
|
|
|
|
ret = true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// copy data after cmd back to return buffer
|
|
|
|
|
memcpy(buffer, &transfer_buffer[1], length);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|