310 lines
9.6 KiB
C
310 lines
9.6 KiB
C
/**
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*********************************************************************************
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*
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* @file ald_pmu.h
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* @brief Header file of PMU module driver.
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*
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* @version V1.0
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* @date 04 Dec 2019
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* @author AE Team
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* @note
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* Change Logs:
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* Date Author Notes
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* 04 Dec 2019 AE Team The first version
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*
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* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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**********************************************************************************
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*/
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#ifndef __ALD_PMU_H__
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#define __ALD_PMU_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "utils.h"
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#include "ald_syscfg.h"
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#include "ald_bkpc.h"
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/** @addtogroup ES32FXXX_ALD
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* @{
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*/
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/** @addtogroup PMU
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* @{
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*/
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/** @defgroup PMU_Public_Macros PMU Public Macros
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* @{
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*/
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#define PMU_LPSTOP_ENABLE() \
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do { \
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SYSCFG_UNLOCK(); \
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SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); \
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SYSCFG_LOCK(); \
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} while (0)
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#define PMU_LPSTOP_DISABLE() \
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do { \
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SYSCFG_UNLOCK(); \
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CLEAR_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); \
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SYSCFG_LOCK(); \
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} while (0)
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#define PMU_FLASH_MODE_IDLE() \
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do { \
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SYSCFG_UNLOCK(); \
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CLEAR_BIT(PMU->CR0, PMU_CR0_SFPD_MSK); \
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SYSCFG_LOCK(); \
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} while (0)
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#define PMU_FLASH_MODE_WAIT() \
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do { \
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SYSCFG_UNLOCK(); \
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SET_BIT(PMU->CR0, PMU_CR0_SFPD_MSK); \
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SYSCFG_LOCK(); \
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} while (0)
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#define PMU_MTSTOP_ENABLE() \
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do { \
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SYSCFG_UNLOCK(); \
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SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); \
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SYSCFG_LOCK(); \
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} while (0)
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#define PMU_MTSTOP_DISABLE() \
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do { \
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SYSCFG_UNLOCK(); \
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CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); \
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SYSCFG_LOCK(); \
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} while (0)
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#define PMU_VREF_ENABLE() \
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do { \
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SYSCFG_UNLOCK(); \
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SET_BIT(PMU->VREFCR, PMU_VREFCR_VREFEN_MSK); \
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SYSCFG_LOCK(); \
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} while (0)
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#define PMU_VREF_DISABLE() \
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do { \
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SYSCFG_UNLOCK(); \
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CLEAR_BIT(PMU->VREFCR, PMU_VREFCR_VREFEN_MSK); \
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SYSCFG_LOCK(); \
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} while (0)
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#define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS))
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/**
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* @}
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*/
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/** @defgroup PMU_Public_Types PMU Public Types
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* @{
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*/
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/**
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* @brief Low power mode
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*/
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typedef enum {
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PMU_LP_STOP1 = 0x0U, /**< Stop1 */
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PMU_LP_STOP2 = 0x1U, /**< Stop2 */
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PMU_LP_STANDBY = 0x2U, /**< Standby */
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} pmu_lp_mode_t;
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/**
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* @brief LDO_18 mode
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*/
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typedef enum {
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PMU_LDO_18_DRV_HIGH = 0x0U, /**< High drive */
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PMU_LDO_18_DRV_LOW = 0x1U, /**< Low drive */
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PMU_LDO_18_HOLD = 0x2U, /**< Hold */
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PMU_LDO_18_OFF = 0x3U, /**< Turn off */
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} pmu_ldo_18_mode_t;
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typedef enum {
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PMU_SR_WUF = (1U << 0), /**< WakeUp status */
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PMU_SR_STANDBYF = (1U << 1), /**< Standby status */
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PMU_SR_USBRDY = (1U << 2), /**< USB Readby status */
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PMU_SR_RSTAT = (1U << 3), /**< RUN/LPRUAN status */
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} pmu_status_t;
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/**
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* @brief LVD voltage select
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*/
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typedef enum {
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PMU_LVD_VOL_SEL_2_2 = 0x0U, /**< 2.2V ~ 2.25V */
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PMU_LVD_VOL_SEL_2_4 = 0x1U, /**< 2.4V ~ 2.45V */
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PMU_LVD_VOL_SEL_2_6 = 0x2U, /**< 2.6V ~ 2.65V */
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PMU_LVD_VOL_SEL_2_8 = 0x3U, /**< 2.8V ~ 2.85V */
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PMU_LVD_VOL_SEL_3_0 = 0x4U, /**< 3.0V ~ 3.05V */
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PMU_LVD_VOL_SEL_3_2 = 0x5U, /**< 3.2V ~ 3.25V */
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PMU_LVD_VOL_SEL_3_4 = 0x6U, /**< 3.4V ~ 3.45V */
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PMU_LVD_VOL_SEL_3_6 = 0x7U, /**< 3.6V ~ 3.65V */
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PMU_LVD_VOL_SEL_3_8 = 0x8U, /**< 3.8V ~ 3.85V */
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PMU_LVD_VOL_SEL_4_0 = 0x9U, /**< 4.0V ~ 4.05V */
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PMU_LVD_VOL_SEL_4_2 = 0xAU, /**< 4.2V ~ 4.25V */
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PMU_LVD_VOL_SEL_4_4 = 0xBU, /**< 4.4V ~ 4.45V */
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PMU_LVD_VOL_SEL_4_6 = 0xCU, /**< 4.6V ~ 4.65V */
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PMU_LVD_VOL_SEL_4_8 = 0xDU, /**< 4.8V ~ 4.85V */
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PMU_LVD_VOL_SEL_EXT = 0xFU, /**< Select external input. It must be 1.2V */
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} pmu_lvd_voltage_sel_t;
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/**
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* @brief LVD trigger mode
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*/
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typedef enum {
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PMU_LVD_TRIGGER_RISING_EDGE = 0x0U, /**< Rising edge */
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PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U, /**< Falling edge */
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PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U, /**< High level */
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PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U, /**< Low level */
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PMU_LVD_TRIGGER_RISING_FALLING = 0x4U, /**< Rising and falling edge */
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} pmu_lvd_trigger_mode_t;
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/**
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* @brief LDO output voltage selest in low power mode
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*/
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typedef enum {
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PMU_LDO_LPMODE_OUTPUT_0_9 = 0x0U, /**< 0.9V */
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PMU_LDO_LPMODE_OUTPUT_1_0 = 0x1U, /**< 1.0V */
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PMU_LDO_LPMODE_OUTPUT_1_1 = 0x2U, /**< 1.1V */
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PMU_LDO_LPMODE_OUTPUT_1_2 = 0x3U, /**< 1.2V */
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} pmu_ldo_lpmode_output_t;
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typedef enum {
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PMU_POWER_SRAM0 = 0x1U, /**< SRAM0 */
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PMU_POWER_SRAM1 = 0x2U, /**< SRAM1 */
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PMU_POWER_SRAM2 = 0x4U, /**< SRAM2 */
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PMU_POWER_SRAM3 = 0x8U, /**< SRAM3 */
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PMU_POWER_SRAM4 = 0x10U, /**< SRAM4 */
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PMU_POWER_SRAM5 = 0x20U, /**< SRAM5 */
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PMU_POWER_CAN = 0x100U, /**< CAN */
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PMU_POWER_QSPI = 0x400U, /**< QSPI */
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PMU_POWER_USB = 0x800U, /**< USB */
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PMU_POWER_ROM = 0x1000U, /**< ROM */
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} pmu_perh_power_t;
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/**
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* @}
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*/
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/**
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* @defgroup PMU_Private_Macros PMU Private Macros
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* @{
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*/
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#define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \
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((x) == PMU_LP_STOP2) || \
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((x) == PMU_LP_STANDBY))
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#define IS_PMU_LDO18_MODE(x) (((x) == PMU_LDO_18_DRV_HIGH) || \
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((x) == PMU_LDO_18_DRV_LOW) || \
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((x) == PMU_LDO_18_HOLD) || \
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((x) == PMU_LDO_18_OFF))
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#define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || \
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((x) == PMU_SR_STANDBYF) || \
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((x) == PMU_SR_USBRDY) || \
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((x) == PMU_SR_RSTAT))
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#define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_2) || \
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((x) == PMU_LVD_VOL_SEL_2_4) || \
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((x) == PMU_LVD_VOL_SEL_2_6) || \
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((x) == PMU_LVD_VOL_SEL_2_8) || \
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((x) == PMU_LVD_VOL_SEL_3_0) || \
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((x) == PMU_LVD_VOL_SEL_3_2) || \
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((x) == PMU_LVD_VOL_SEL_3_4) || \
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((x) == PMU_LVD_VOL_SEL_3_6) || \
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((x) == PMU_LVD_VOL_SEL_3_8) || \
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((x) == PMU_LVD_VOL_SEL_4_0) || \
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((x) == PMU_LVD_VOL_SEL_4_2) || \
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((x) == PMU_LVD_VOL_SEL_4_4) || \
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((x) == PMU_LVD_VOL_SEL_4_6) || \
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((x) == PMU_LVD_VOL_SEL_4_8) || \
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((x) == PMU_LVD_VOL_SEL_EXT))
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#define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \
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((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \
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((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \
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((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \
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((x) == PMU_LVD_TRIGGER_RISING_FALLING))
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#define IS_PMU_LDO_LPMODE_OUTPUT(x) (((x) == PMU_LDO_LPMODE_OUTPUT_0_9) || \
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((x) == PMU_LDO_LPMODE_OUTPUT_1_0) || \
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((x) == PMU_LDO_LPMODE_OUTPUT_1_1) || \
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((x) == PMU_LDO_LPMODE_OUTPUT_1_2))
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#define IS_PMU_PERH_POWER(x) (((x) == PMU_POWER_SRAM0) || \
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((x) == PMU_POWER_SRAM1) || \
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((x) == PMU_POWER_SRAM2) || \
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((x) == PMU_POWER_SRAM3) || \
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((x) == PMU_POWER_SRAM4) || \
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((x) == PMU_POWER_SRAM5) || \
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((x) == PMU_POWER_CAN) || \
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((x) == PMU_POWER_QSPI) || \
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((x) == PMU_POWER_USB) || \
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((x) == PMU_POWER_ROM))
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/**
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* @}
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*/
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/** @addtogroup PMU_Public_Functions
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* @{
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*/
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/** @addtogroup PMU_Public_Functions_Group1
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* @{
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*/
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/* Low power mode select */
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__STATIC_INLINE__ void ald_pmu_sleep()
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{
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__WFI();
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}
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__STATIC_INLINE__ void ald_pmu_sleep_deep()
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{
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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__WFI();
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}
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void ald_pmu_stop1_enter(void);
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void ald_pmu_stop2_enter(void);
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void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level);
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void ald_pmu_ldo_12_config(type_func_t state);
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void ald_pmu_ldo_18_config(pmu_ldo_18_mode_t mode);
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#ifdef ES32F336x /* MCU Series: ES32F336x */
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void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state);
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#endif
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flag_status_t ald_pmu_get_status(pmu_status_t sr);
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void ald_pmu_clear_status(pmu_status_t sr);
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void ald_pmu_perh_power_config(pmu_perh_power_t perh, type_func_t state);
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/**
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* @}
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*/
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/** @addtogroup PMU_Public_Functions_Group2
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* @{
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*/
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/* LVD configure */
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void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state);
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void ald_lvd_irq_handler(void);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ALD_PMU_H__ */
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