225 lines
6.9 KiB
C
225 lines
6.9 KiB
C
/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include "usbd_core.h"
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#include "usbh_core.h"
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#include "usb_dwc2_param.h"
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#include <riscv_io.h>
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#include "sysctl_rst.h"
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#include "ioremap.h"
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#include "mmu.h"
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#include "cache.h"
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extern rt_mmu_info mmu_info;
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#if defined(ENABLE_CHERRY_USB) || defined(PKG_USING_CHERRYUSB) || defined(RT_USING_CHERRYUSB)
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#define DEFAULT_USB_HCLK_FREQ_MHZ 200
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uint32_t SystemCoreClock = (DEFAULT_USB_HCLK_FREQ_MHZ * 1000 * 1000);
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const uintptr_t usb_dev_addr[2] = { 0x91500000UL, 0x91540000UL };
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#define USB_IDPULLUP0 (1 << 4)
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#define USB_DMPULLDOWN0 (1 << 8)
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#define USB_DPPULLDOWN0 (1 << 9)
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const struct dwc2_user_params param_common = {
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.phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
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#ifdef CONFIG_USB_DWC2_DMA_ENABLE
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.device_dma_enable = true,
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#else
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.device_dma_enable = false,
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#endif
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.device_dma_desc_enable = false,
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.device_rx_fifo_size = (3016 - 16 - 256 * 8),
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.device_tx_fifo_size = {
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[0] = 16, // 64 byte
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[1] = 512, // 1024 byte, double buffer
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[2] = 256, // 1024 byte
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[3] = 512, // 1024 byte, double buffer
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[4] = 256, // 1024 byte
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[5] = 256, // 1024 byte
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[6] = 256, // 1024 byte
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[7] = 0,
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[8] = 0,
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[9] = 0,
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[10] = 0,
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[11] = 0,
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[12] = 0,
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[13] = 0,
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[14] = 0,
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[15] = 0 },
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.host_dma_desc_enable = false,
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.host_rx_fifo_size = 3016 - 128 * 2 - 256 * 2,
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.host_nperio_tx_fifo_size = 128 * 2, // 512 byte, double buffer
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.host_perio_tx_fifo_size = 256 * 2, // 1024 byte, double buffer
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.device_gccfg = 0,
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.host_gccfg = 0
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};
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#ifndef CONFIG_USB_DWC2_CUSTOM_PARAM
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void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params)
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{
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memcpy(params, ¶m_common, sizeof(struct dwc2_user_params));
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#ifdef CONFIG_USB_DWC2_CUSTOM_FIFO
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struct usb_dwc2_user_fifo_config s_dwc2_fifo_config;
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dwc2_get_user_fifo_config(reg_base, &s_dwc2_fifo_config);
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params->device_rx_fifo_size = s_dwc2_fifo_config.device_rx_fifo_size;
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for (uint8_t i = 0; i < MAX_EPS_CHANNELS; i++) {
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params->device_tx_fifo_size[i] = s_dwc2_fifo_config.device_tx_fifo_size[i];
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}
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#endif
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}
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#endif
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// USB Host
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#if defined(ENABLE_CHERRY_USB_HOST) || defined(PKG_CHERRYUSB_HOST) || defined(RT_CHERRYUSB_HOST)
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static void usb_hc_interrupt_cb(int irq, void *arg_pv)
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{
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USBH_IRQHandler((uint8_t)(uintptr_t)arg_pv);
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}
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void usb_hc_low_level_init(struct usbh_bus *bus)
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{
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uint32_t *hs_reg;
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uint32_t usb_ctl3;
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if ((uintptr_t)rt_hw_mmu_v2p(&mmu_info, (void *)bus->hcd.reg_base) == usb_dev_addr[0]) {
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if (!sysctl_reset(SYSCTL_RESET_USB0)) {
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USB_LOG_ERR("reset usb0 fail\n");
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}
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hs_reg = (uint32_t *)rt_ioremap((void *)(0x91585000 + 0x7C), 0x1000);
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usb_ctl3 = *hs_reg | USB_IDPULLUP0;
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*hs_reg = usb_ctl3 | (USB_DMPULLDOWN0 | USB_DPPULLDOWN0);
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rt_iounmap(hs_reg);
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rt_hw_interrupt_install(173, usb_hc_interrupt_cb, (void *)(uintptr_t)bus->hcd.hcd_id, "usbh0");
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rt_hw_interrupt_umask(173);
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} else {
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if (!sysctl_reset(SYSCTL_RESET_USB1)) {
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USB_LOG_ERR("reset usb1 fail\n");
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}
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hs_reg = (uint32_t *)rt_ioremap((void *)(0x91585000 + 0x9C), 0x1000);
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usb_ctl3 = *hs_reg | USB_IDPULLUP0;
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*hs_reg = usb_ctl3 | (USB_DMPULLDOWN0 | USB_DPPULLDOWN0);
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rt_iounmap(hs_reg);
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rt_hw_interrupt_install(174, usb_hc_interrupt_cb, (void *)(uintptr_t)bus->hcd.hcd_id, "usbh1");
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rt_hw_interrupt_umask(174);
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}
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}
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void usb_hc_low_level_deinit(struct usbh_bus *bus)
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{
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if ((uintptr_t)rt_hw_mmu_v2p(&mmu_info, (void *)bus->hcd.reg_base) == usb_dev_addr[0]) {
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rt_hw_interrupt_mask(173);
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} else {
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rt_hw_interrupt_mask(174);
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}
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}
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#endif // ENABLE_CHERRY_USB_HOST
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// USB Device
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#if defined(ENABLE_CHERRY_USB_DEVICE) || defined(PKG_CHERRYUSB_DEVICE) || defined(RT_CHERRYUSB_DEVICE)
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static void usb_dc_interrupt_cb(int irq, void *arg_pv)
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{
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USBD_IRQHandler((uint8_t)(uintptr_t)arg_pv);
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}
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void usb_dc_low_level_init(uint8_t busid)
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{
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if ((uintptr_t)rt_hw_mmu_v2p(&mmu_info, (void *)g_usbdev_bus[busid].reg_base) == usb_dev_addr[0]) {
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if (!sysctl_reset(SYSCTL_RESET_USB0)) {
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USB_LOG_ERR("reset usb0 fail\n");
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}
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uint32_t *hs_reg = (uint32_t *)rt_ioremap((void *)(0x91585000 + 0x7C), 0x1000);
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*hs_reg = 0x37;
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rt_iounmap(hs_reg);
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rt_hw_interrupt_install(173, usb_dc_interrupt_cb, (void *)(uintptr_t)busid, "usbd0");
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rt_hw_interrupt_umask(173);
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} else {
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if (!sysctl_reset(SYSCTL_RESET_USB1)) {
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USB_LOG_ERR("reset usb1 fail\n");
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}
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uint32_t *hs_reg = (uint32_t *)rt_ioremap((void *)(0x91585000 + 0x9C), 0x1000);
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*hs_reg = 0x37;
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rt_iounmap(hs_reg);
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rt_hw_interrupt_install(174, usb_dc_interrupt_cb, (void *)(uintptr_t)busid, "usbd1");
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rt_hw_interrupt_umask(174);
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}
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}
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void usb_dc_low_level_deinit(uint8_t busid)
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{
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if ((uintptr_t)rt_hw_mmu_v2p(&mmu_info, (void *)g_usbdev_bus[busid].reg_base) == usb_dev_addr[0]) {
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rt_hw_interrupt_mask(173);
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} else {
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rt_hw_interrupt_mask(174);
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}
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}
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#endif // ENABLE_CHERRY_USB_DEVICE
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void usbd_dwc2_delay_ms(uint8_t ms)
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{
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rt_thread_mdelay(ms);
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}
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#ifdef CONFIG_USB_DCACHE_ENABLE
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void usb_dcache_clean(uintptr_t addr, size_t size)
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{
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rt_hw_cpu_dcache_clean((void *)addr, size);
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}
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void usb_dcache_invalidate(uintptr_t addr, size_t size)
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{
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rt_hw_cpu_dcache_invalidate((void *)addr, size);
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}
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void usb_dcache_flush(uintptr_t addr, size_t size)
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{
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rt_hw_cpu_dcache_clean_flush((void *)addr, size);
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}
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#endif
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#endif // ENABLE_CHERRY_USB
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