326 lines
12 KiB
C
326 lines
12 KiB
C
/*
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* Copyright (c) 2024, sakumisu
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sys_driver.h"
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#include "gpio_driver.h"
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#include <driver/gpio.h>
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#include <driver/gpio_types.h>
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#include <driver/int.h>
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#include "bk_misc.h"
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#include "usbd_core.h"
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#include "usbh_core.h"
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#include "usb_musb_reg.h"
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#define USB_BASE_ADDR SOC_USB_REG_BASE
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#if (CONFIG_SOC_BK7271)
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#define REG_AHB2_USB_OTG_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x80)))
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#define REG_AHB2_USB_DMA_ENDP (*((volatile unsigned char *)(USB_BASE_ADDR + 0x84)))
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#define REG_AHB2_USB_VTH (*((volatile unsigned char *)(USB_BASE_ADDR + 0x88)))
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#define REG_AHB2_USB_GEN (*((volatile unsigned char *)(USB_BASE_ADDR + 0x8C)))
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#define REG_AHB2_USB_STAT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x90)))
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#define REG_AHB2_USB_INT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x94)))
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#define REG_AHB2_USB_RESET (*((volatile unsigned char *)(USB_BASE_ADDR + 0x98)))
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#define REG_AHB2_USB_DEV_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x9C)))
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#elif (CONFIG_SOC_BK7256XX)
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#define REG_AHB2_USB_OTG_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x280)))
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#define REG_AHB2_USB_DMA_ENDP (*((volatile unsigned char *)(USB_BASE_ADDR + 0x284)))
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#define REG_AHB2_USB_VTH (*((volatile unsigned char *)(USB_BASE_ADDR + 0x288)))
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#define REG_AHB2_USB_GEN (*((volatile unsigned char *)(USB_BASE_ADDR + 0x28C)))
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#define REG_AHB2_USB_STAT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x290)))
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#define REG_AHB2_USB_INT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x294)))
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#define REG_AHB2_USB_RESET (*((volatile unsigned char *)(USB_BASE_ADDR + 0x298)))
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#define REG_AHB2_USB_DEV_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x29C)))
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#elif (CONFIG_SOC_BK7236XX) || (CONFIG_SOC_BK7239XX) || (CONFIG_SOC_BK7286XX)
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#define REG_AHB2_USB_DEVICE_ID (*((volatile unsigned char *)(USB_BASE_ADDR + 0x280)))
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#define REG_AHB2_USB_VERSION_ID (*((volatile unsigned char *)(USB_BASE_ADDR + 0x284)))
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#define REG_AHB2_USB_GLOBAL_CTRL (*((volatile unsigned char *)(USB_BASE_ADDR + 0x288)))
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#define REG_AHB2_USB_DEVICE_STATUS (*((volatile unsigned char *)(USB_BASE_ADDR + 0x28c)))
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#define REG_AHB2_USB_OTG_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x290)))
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#define REG_AHB2_USB_DMA_ENDP (*((volatile unsigned char *)(USB_BASE_ADDR + 0x294)))
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#define REG_AHB2_USB_VTH (*((volatile unsigned char *)(USB_BASE_ADDR + 0x298)))
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#define REG_AHB2_USB_GEN (*((volatile unsigned char *)(USB_BASE_ADDR + 0x29C)))
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#define REG_AHB2_USB_STAT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x2A0)))
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#define REG_AHB2_USB_INT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x2A4)))
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#define REG_AHB2_USB_RESET (*((volatile unsigned char *)(USB_BASE_ADDR + 0x2A8)))
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#define REG_AHB2_USB_DEV_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x2AC)))
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#define REG_USB_USR_700 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x700)))
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#define REG_USB_USR_704 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x704)))
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#define REG_USB_USR_708 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x708)))
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#define REG_USB_USR_70C (*((volatile unsigned long *)(USB_BASE_ADDR + 0x70C)))
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#define REG_USB_USR_710 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x710)))
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#define REG_USB_USR_714 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x714)))
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#define REG_USB_PHY_00 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x400)))
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#define REG_USB_PHY_01 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x404)))
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#endif
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#define USB_DP_CAPABILITY_VALUE (0xF)
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#define USB_DN_CAPABILITY_VALUE (0xF)
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#define NANENG_PHY_FC_REG01 (0x01 * 4)
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#define NANENG_PHY_FC_REG02 (0x02 * 4)
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#define NANENG_PHY_FC_REG03 (0x03 * 4)
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#define NANENG_PHY_FC_REG04 (0x04 * 4)
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#define NANENG_PHY_FC_REG05 (0x05 * 4)
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#define NANENG_PHY_FC_REG06 (0x06 * 4)
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#define NANENG_PHY_FC_REG07 (0x07 * 4)
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#define NANENG_PHY_FC_REG08 (0x08 * 4)
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#define NANENG_PHY_FC_REG09 (0x09 * 4)
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#define NANENG_PHY_FC_REG0A (0x0A * 4)
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#define NANENG_PHY_FC_REG0B (0x0B * 4)
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#define NANENG_PHY_FC_REG0C (0x0C * 4)
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#define NANENG_PHY_FC_REG0D (0x0D * 4)
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#define NANENG_PHY_FC_REG0E (0x0E * 4)
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#define NANENG_PHY_FC_REG0F (0x0F * 4)
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#define NANENG_PHY_FC_REG0F_BYTE 0x0F
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#define NANENG_PHY_FC_REG10 (0x10 * 4)
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#define NANENG_PHY_FC_REG11 (0x11 * 4)
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#define NANENG_PHY_FC_REG12 (0x12 * 4)
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#define NANENG_PHY_FC_REG13 (0x13 * 4)
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#define NANENG_PHY_FC_REG14 (0x14 * 4)
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#define NANENG_PHY_FC_REG15 (0x15 * 4)
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#define NANENG_PHY_FC_REG16 (0x16 * 4)
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#define NANENG_PHY_FC_REG17 (0x17 * 4)
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#define NANENG_PHY_FC_REG18 (0x18 * 4)
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#define NANENG_PHY_FC_REG19 (0x19 * 4)
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#define NANENG_PHY_FC_REG1A (0x1A * 4)
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#define NANENG_PHY_FC_REG1B (0x1B * 4)
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#define NANENG_PHY_FC_REG1C (0x1C * 4)
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#define NANENG_PHY_FC_REG1D (0x1D * 4)
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#define NANENG_PHY_FC_REG1E (0x1E * 4)
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#define NANENG_PHY_FC_REG1F (0x1F * 4)
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#if CONFIG_USB_MUSB_EP_NUM != 8
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#error beken chips only support 8 endpoints
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#endif
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#if CONFIG_USB_MUSB_PIPE_NUM != 8
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#error beken chips only support 8 pipes
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#endif
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// clang-format off
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static struct musb_fifo_cfg musb_device_table[] = {
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{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, },
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{ .ep_num = 1, .style = FIFO_TX, .maxpacket = 1024, },
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{ .ep_num = 1, .style = FIFO_RX, .maxpacket = 1024, },
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{ .ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
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{ .ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
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{ .ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
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{ .ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
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{ .ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
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{ .ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
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{ .ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
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{ .ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
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{ .ep_num = 6, .style = FIFO_TXRX, .maxpacket = 512, },
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{ .ep_num = 7, .style = FIFO_TXRX, .maxpacket = 512, }
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};
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static struct musb_fifo_cfg musb_host_table[] = {
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{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, },
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{ .ep_num = 1, .style = FIFO_TX, .maxpacket = 1024, },
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{ .ep_num = 1, .style = FIFO_RX, .maxpacket = 1024, },
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{ .ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
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{ .ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
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{ .ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
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{ .ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
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{ .ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
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{ .ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
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{ .ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
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{ .ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
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{ .ep_num = 6, .style = FIFO_TXRX, .maxpacket = 512, },
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{ .ep_num = 7, .style = FIFO_TXRX, .maxpacket = 512, }
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};
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// clang-format on
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uint8_t usbd_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg)
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{
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*cfg = musb_device_table;
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return sizeof(musb_device_table) / sizeof(musb_device_table[0]);
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}
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uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg)
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{
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*cfg = musb_host_table;
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return sizeof(musb_host_table) / sizeof(musb_host_table[0]);
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}
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uint32_t usb_get_musb_ram_size(void)
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{
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return 8192;
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}
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extern void USBD_IRQHandler(uint8_t busid);
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void USBD_IRQ(void)
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{
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USBD_IRQHandler(0);
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}
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static void bk_analog_layer_usb_sys_related_ops(uint32_t usb_mode, bool ops)
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{
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extern void delay(INT32 num);
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#if 0
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sys_drv_usb_analog_phy_en(ops, NULL);
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sys_drv_usb_analog_speed_en(ops, NULL);
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sys_drv_usb_analog_ckmcu_en(ops, NULL);
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#endif
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if (ops) {
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sys_drv_usb_clock_ctrl(true, NULL);
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delay(100);
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#if 0
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sys_drv_usb_analog_deepsleep_en(false);
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#endif
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sys_drv_usb_analog_dp_capability(USB_DP_CAPABILITY_VALUE);
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sys_drv_usb_analog_dn_capability(USB_DN_CAPABILITY_VALUE);
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if (!sys_hal_psram_ldo_status()) {
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sys_drv_psram_ldo_enable(1);
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}
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sys_drv_usb_analog_phy_en(1, NULL);
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if (usb_mode == 0) {
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REG_USB_USR_708 = 0x0;
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REG_USB_USR_710 &= ~(0x1 << 7);
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delay(100);
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REG_USB_USR_710 |= (0x1 << 15);
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//REG_USB_USR_710 |= (0x1<<14);
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REG_USB_USR_710 |= (0x1 << 16);
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REG_USB_USR_710 |= (0x1 << 17);
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REG_USB_USR_710 |= (0x1 << 18);
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REG_USB_USR_710 |= (0x1 << 19);
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REG_USB_USR_710 &= ~(0x1 << 20);
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REG_USB_USR_710 |= (0x1 << 21);
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REG_USB_USR_710 |= (0x0 << 0);
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REG_USB_USR_710 |= (0x1 << 5);
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REG_USB_USR_710 |= (0x1 << 6);
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REG_USB_USR_710 |= (0x1 << 9);
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REG_USB_USR_710 |= (0x1 << 10);
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REG_USB_USR_710 |= (0x1 << 1);
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REG_USB_USR_710 |= (0x1 << 7);
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REG_USB_USR_708 = 0x1;
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#if 0
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REG_USB_PHY_00 = 0x08;
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REG_USB_PHY_01 = 0x02;
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REG_USB_USR_710 |= (0x1<< 8);
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while(1){
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reg = REG_USB_USR_70C;
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if(reg & 0x100){
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USB_DRIVER_LOGI("SelfTest Fin!\r\n");
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USB_DRIVER_LOGI("test end!\r\n");
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break;
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} else {
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USB_DRIVER_LOGI("70c_reg:0x%x\r\n", reg);
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delay(10000);
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}
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}
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REG_USB_PHY_00 &= ~0x08;
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REG_USB_PHY_01 &= ~0x02;
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REG_USB_USR_710 &= ~(0x1<< 8);
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#endif
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} else {
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REG_USB_USR_710 |= (0x1 << 15);
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REG_USB_USR_710 |= (0x1 << 14);
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REG_USB_USR_710 |= (0x1 << 16);
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REG_USB_USR_710 |= (0x1 << 17);
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REG_USB_USR_710 |= (0x1 << 18);
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REG_USB_USR_710 |= (0x1 << 19);
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REG_USB_USR_710 &= ~(0x1 << 20);
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REG_USB_USR_710 |= (0x1 << 21);
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REG_USB_USR_710 |= (0x0 << 0);
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REG_USB_USR_710 |= (0x1 << 5);
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REG_USB_USR_710 |= (0x1 << 6);
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REG_USB_USR_710 |= (0x1 << 9);
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REG_USB_USR_710 |= (0x1 << 10);
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REG_USB_USR_710 |= (0x1 << 7);
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REG_USB_USR_708 = 0x1;
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}
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} else {
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sys_drv_usb_analog_phy_en(0, NULL);
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sys_drv_usb_clock_ctrl(false, NULL);
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}
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}
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void usb_dc_low_level_init(void)
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{
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#if CONFIG_SYS_CPU0
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bk_pm_module_vote_sleep_ctrl(PM_SLEEP_MODULE_NAME_USB_1, 0x0, 0x0);
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#endif
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bk_analog_layer_usb_sys_related_ops(1, true);
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bk_gpio_set_output_high(CONFIG_USB_VBAT_CONTROL_GPIO_ID);
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bk_pm_module_vote_cpu_freq(PM_DEV_ID_USB_1, PM_CPU_FRQ_120M);
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sys_hal_usb_analog_phy_en(true);
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sys_drv_usb_clock_ctrl(true, NULL);
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sys_drv_int_enable(USB_INTERRUPT_CTRL_BIT);
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bk_int_isr_register(INT_SRC_USB, USBD_IRQ, NULL);
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bk_int_set_priority(INT_SRC_USB, 2);
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}
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void usb_dc_low_level_deinit(void)
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{
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bk_pm_module_vote_cpu_freq(PM_DEV_ID_USB_1, PM_CPU_FRQ_DEFAULT);
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sys_hal_usb_analog_phy_en(false);
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sys_drv_usb_clock_ctrl(false, NULL);
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sys_drv_int_disable(USB_INTERRUPT_CTRL_BIT);
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bk_int_isr_unregister(INT_SRC_USB);
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bk_analog_layer_usb_sys_related_ops(1, false);
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sys_drv_dev_clk_pwr_up(CLK_PWR_ID_USB_1, CLK_PWR_CTRL_PWR_DOWN);
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}
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void usbd_musb_delay_ms(uint8_t ms)
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{
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/* implement later */
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}
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extern void USBH_IRQHandler(uint8_t busid);
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void USBH_IRQ(void)
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{
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USBH_IRQHandler(0);
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}
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#define NANENG_PHY_CFG 1
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#define USB_PHY_BASE (SOC_USB_REG_BASE + 0x400)
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#define HWREG(x) \
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(*((volatile uint32_t *)(x)))
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#define HWREGH(x) \
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(*((volatile uint16_t *)(x)))
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#define HWREGB(x) \
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(*((volatile uint8_t *)(x)))
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void usb_hc_low_level_init(struct usbh_bus *bus)
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{
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#if CONFIG_SYS_CPU0
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bk_pm_module_vote_sleep_ctrl(PM_SLEEP_MODULE_NAME_USB_1, 0x0, 0x0);
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#endif
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bk_analog_layer_usb_sys_related_ops(0, true);
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bk_gpio_set_output_high(CONFIG_USB_VBAT_CONTROL_GPIO_ID);
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#if NANENG_PHY_CFG
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//NANENG_PHY_CFG_HSRX_TEST
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HWREGB(USB_PHY_BASE + NANENG_PHY_FC_REG0F) |= (0x1 << 4);
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//disconnect value 640mv
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HWREGB(USB_PHY_BASE + NANENG_PHY_FC_REG0B) = 0x7C;
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#endif
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bk_int_isr_register(INT_SRC_USB, USBH_IRQ, NULL);
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sys_drv_int_enable(USB_INTERRUPT_CTRL_BIT);
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}
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void usb_hc_low_level_deinit(struct usbh_bus *bus)
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{
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sys_drv_int_disable(USB_INTERRUPT_CTRL_BIT);
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bk_int_isr_unregister(INT_SRC_USB);
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sys_drv_dev_clk_pwr_up(CLK_PWR_ID_USB_1, CLK_PWR_CTRL_PWR_DOWN);
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bk_analog_layer_usb_sys_related_ops(0, false);
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} |