702 lines
18 KiB
C
702 lines
18 KiB
C
#include "usbd_core.h"
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#include "usb_musb_reg.h"
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#ifdef USB_MUSB_SUNXI
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#define SUNXI_SRAMC_BASE 0x01c00000
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#define SUNXI_USB0_BASE 0x01c13000
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#define USBC_REG_o_PHYCTL 0x0404
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#ifndef USB_BASE
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#define USB_BASE (SUNXI_USB0_BASE)
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#endif
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#ifndef USBD_IRQHandler
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#define USBD_IRQHandler USB_INT_Handler //use actual usb irq name instead
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void USBD_IRQHandler(int, void *);
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#endif
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#define MUSB_IND_TXMAP_OFFSET 0x80
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#define MUSB_IND_TXCSRL_OFFSET 0x82
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#define MUSB_IND_TXCSRH_OFFSET 0x83
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#define MUSB_IND_RXMAP_OFFSET 0x84
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#define MUSB_IND_RXCSRL_OFFSET 0x86
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#define MUSB_IND_RXCSRH_OFFSET 0x87
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#define MUSB_IND_RXCOUNT_OFFSET 0x88
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#define MUSB_FIFO_OFFSET 0x00
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#else
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#ifndef USBD_IRQHandler
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#define USBD_IRQHandler USB_INT_Handler //use actual usb irq name instead
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#endif
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#ifndef USB_BASE
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#define USB_BASE (0x40086400UL)
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#endif
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#define MUSB_IND_TXMAP_OFFSET 0x10
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#define MUSB_IND_TXCSRL_OFFSET 0x12
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#define MUSB_IND_TXCSRH_OFFSET 0x13
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#define MUSB_IND_RXMAP_OFFSET 0x14
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#define MUSB_IND_RXCSRL_OFFSET 0x16
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#define MUSB_IND_RXCSRH_OFFSET 0x17
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#define MUSB_IND_RXCOUNT_OFFSET 0x18
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#define MUSB_FIFO_OFFSET 0x20
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#endif // USB_MUSB_SUNXI
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#ifndef USB_NUM_BIDIR_ENDPOINTS
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#define USB_NUM_BIDIR_ENDPOINTS 8
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#endif
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#define USB_TXMAPx_BASE (USB_BASE + MUSB_IND_TXMAP_OFFSET)
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#define USB_RXMAPx_BASE (USB_BASE + MUSB_IND_RXMAP_OFFSET)
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#define USB_TXCSRLx_BASE (USB_BASE + MUSB_IND_TXCSRL_OFFSET)
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#define USB_RXCSRLx_BASE (USB_BASE + MUSB_IND_RXCSRL_OFFSET)
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#define USB_TXCSRHx_BASE (USB_BASE + MUSB_IND_TXCSRH_OFFSET)
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#define USB_RXCSRHx_BASE (USB_BASE + MUSB_IND_RXCSRH_OFFSET)
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#define USB_RXCOUNTx_BASE (USB_BASE + MUSB_IND_RXCOUNT_OFFSET)
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#define USB_FIFO_BASE(ep_idx) (USB_BASE + MUSB_FIFO_OFFSET + 0x4 * ep_idx)
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#define USB ((volatile USB0_Type *)USB_BASE)
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#define HWREG(x) \
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(*((volatile uint32_t *)(x)))
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#define HWREGH(x) \
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(*((volatile uint16_t *)(x)))
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#define HWREGB(x) \
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(*((volatile uint8_t *)(x)))
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typedef enum {
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USB_EP0_STATE_SETUP = 0x0, /**< SETUP DATA */
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USB_EP0_STATE_IN_DATA = 0x1, /**< IN DATA */
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USB_EP0_STATE_IN_STATUS = 0x2, /**< IN status*/
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USB_EP0_STATE_OUT_DATA = 0x3, /**< OUT DATA */
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USB_EP0_STATE_OUT_STATUS = 0x4, /**< OUT status */
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} ep0_state_t;
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/* Endpoint state */
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struct usb_dc_ep_state {
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/** Endpoint max packet size */
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uint16_t ep_mps;
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/** Endpoint Transfer Type.
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* May be Bulk, Interrupt, Control or Isochronous
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*/
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uint8_t ep_type;
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uint8_t ep_stalled; /** Endpoint stall flag */
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};
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/* Driver state */
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struct usb_dc_config_priv {
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volatile uint8_t dev_addr;
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volatile uint32_t fifo_size_offset;
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struct usb_setup_packet setup;
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struct usb_dc_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/
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struct usb_dc_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
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} usb_dc_cfg;
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volatile uint8_t usb_ep0_state = USB_EP0_STATE_SETUP;
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volatile uint16_t ep0_last_size = 0;
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/* get current active ep */
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static uint8_t USBC_GetActiveEp(void)
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{
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return USB->EPIDX;
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}
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/* set the active ep */
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static void USBC_SelectActiveEp(uint8_t ep_index)
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{
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USB->EPIDX = ep_index;
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}
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static void usb_musb_write_packet(uint8_t ep_idx, uint8_t *buffer, uint16_t len)
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{
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uint32_t *buf32;
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uint8_t *buf8;
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uint32_t count32;
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uint32_t count8;
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int i;
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if ((size_t)buffer & 0x03) {
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buf8 = buffer;
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for (i = 0; i < len; i++) {
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HWREGB(USB_FIFO_BASE(ep_idx)) = *buf8++;
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}
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} else {
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count32 = len >> 2;
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count8 = len & 0x03;
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buf32 = (uint32_t *)buffer;
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while (count32--) {
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HWREG(USB_FIFO_BASE(ep_idx)) = *buf32++;
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}
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buf8 = (uint8_t *)buf32;
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while (count8--) {
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HWREGB(USB_FIFO_BASE(ep_idx)) = *buf8++;
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}
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}
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}
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static void usb_musb_read_packet(uint8_t ep_idx, uint8_t *buffer, uint16_t len)
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{
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uint32_t *buf32;
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uint8_t *buf8;
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uint32_t count32;
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uint32_t count8;
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int i;
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if ((size_t)buffer & 0x03) {
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buf8 = buffer;
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for (i = 0; i < len; i++) {
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*buf8++ = HWREGB(USB_FIFO_BASE(ep_idx));
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}
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} else {
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count32 = len >> 2;
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count8 = len & 0x03;
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buf32 = (uint32_t *)buffer;
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while (count32--) {
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*buf32++ = HWREG(USB_FIFO_BASE(ep_idx));
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}
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buf8 = (uint8_t *)buf32;
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while (count8--) {
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*buf8++ = HWREGB(USB_FIFO_BASE(ep_idx));
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}
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}
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}
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static uint32_t usb_musb_get_fifo_size(uint16_t mps, uint16_t *used)
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{
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uint32_t size;
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for (uint8_t i = USB_TXFIFOSZ_SIZE_8; i <= USB_TXFIFOSZ_SIZE_2048; i++) {
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size = (8 << i);
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if (mps <= size) {
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*used = size;
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return i;
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}
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}
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*used = 0;
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return USB_TXFIFOSZ_SIZE_8;
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}
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__WEAK void usb_dc_low_level_init(void)
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{
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}
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__WEAK void usb_dc_low_level_deinit(void)
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{
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}
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int usb_dc_init(void)
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{
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memset(&usb_dc_cfg, 0, sizeof(struct usb_dc_config_priv));
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usb_dc_cfg.out_ep[0].ep_mps = USB_CTRL_EP_MPS;
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usb_dc_cfg.out_ep[0].ep_type = 0x00;
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usb_dc_cfg.in_ep[0].ep_mps = USB_CTRL_EP_MPS;
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usb_dc_cfg.in_ep[0].ep_type = 0x00;
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usb_dc_cfg.fifo_size_offset = USB_CTRL_EP_MPS;
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usb_dc_low_level_init();
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#ifdef CONFIG_USB_HS
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USB->POWER |= USB_POWER_HSENAB;
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#else
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USB->POWER &= ~USB_POWER_HSENAB;
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#endif
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USB->EPIDX = 0;
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USB->FADDR = 0;
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USB->DEVCTL |= USB_DEVCTL_SESSION;
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/* Enable USB interrupts */
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USB->IE = USB_IE_RESET;
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USB->TXIE = USB_TXIE_EP0;
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USB->RXIE = 0;
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USB->POWER |= USB_POWER_SOFTCONN;
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return 0;
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}
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int usb_dc_deinit(void)
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{
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return 0;
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}
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int usbd_set_address(const uint8_t addr)
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{
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if (addr == 0) {
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USB->FADDR = 0;
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}
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usb_dc_cfg.dev_addr = addr;
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return 0;
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}
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int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
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{
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uint16_t used = 0;
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uint16_t fifo_size = 0;
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uint8_t ep_idx = USB_EP_GET_IDX(ep_cfg->ep_addr);
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uint8_t old_ep_idx;
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uint32_t ui32Flags = 0;
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uint16_t ui32Register = 0;
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if (ep_idx == 0) {
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return 0;
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}
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old_ep_idx = USBC_GetActiveEp();
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USBC_SelectActiveEp(ep_idx);
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if (USB_EP_DIR_IS_OUT(ep_cfg->ep_addr)) {
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usb_dc_cfg.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
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usb_dc_cfg.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
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USB->RXIE |= (1 << ep_idx);
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HWREGH(USB_RXMAPx_BASE) = ep_cfg->ep_mps;
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//
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// Allow auto clearing of RxPktRdy when packet of size max packet
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// has been unloaded from the FIFO.
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//
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if (ui32Flags & USB_EP_AUTO_CLEAR) {
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ui32Register = USB_RXCSRH1_AUTOCL;
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}
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//
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// Configure the DMA mode.
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//
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if (ui32Flags & USB_EP_DMA_MODE_1) {
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ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD;
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} else if (ui32Flags & USB_EP_DMA_MODE_0) {
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ui32Register |= USB_RXCSRH1_DMAEN;
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}
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//
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// If requested, disable NYET responses for high-speed bulk and
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// interrupt endpoints.
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//
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if (ui32Flags & USB_EP_DIS_NYET) {
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ui32Register |= USB_RXCSRH1_DISNYET;
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}
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//
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// Enable isochronous mode if requested.
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//
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if (ep_cfg->ep_type == 0x01) {
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ui32Register |= USB_RXCSRH1_ISO;
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}
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HWREGB(USB_RXCSRHx_BASE) = ui32Register;
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// Reset the Data toggle to zero.
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if (HWREGB(USB_RXCSRLx_BASE) & USB_RXCSRL1_RXRDY)
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HWREGB(USB_RXCSRLx_BASE) = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
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else
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HWREGB(USB_RXCSRLx_BASE) = USB_RXCSRL1_CLRDT;
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fifo_size = usb_musb_get_fifo_size(ep_cfg->ep_mps, &used);
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USB->RXFIFOSZ = fifo_size & 0x0f;
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USB->RXFIFOADD = (usb_dc_cfg.fifo_size_offset >> 3);
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usb_dc_cfg.fifo_size_offset += used;
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} else {
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usb_dc_cfg.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
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usb_dc_cfg.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
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USB->TXIE |= (1 << ep_idx);
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HWREGH(USB_TXMAPx_BASE) = ep_cfg->ep_mps;
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//
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// Allow auto setting of TxPktRdy when max packet size has been loaded
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// into the FIFO.
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//
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if (ui32Flags & USB_EP_AUTO_SET) {
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ui32Register |= USB_TXCSRH1_AUTOSET;
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}
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//
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// Configure the DMA mode.
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//
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if (ui32Flags & USB_EP_DMA_MODE_1) {
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ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD;
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} else if (ui32Flags & USB_EP_DMA_MODE_0) {
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ui32Register |= USB_TXCSRH1_DMAEN;
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}
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//
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// Enable isochronous mode if requested.
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//
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if (ep_cfg->ep_type == 0x01) {
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ui32Register |= USB_TXCSRH1_ISO;
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}
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HWREGB(USB_TXCSRHx_BASE) = ui32Register;
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// Reset the Data toggle to zero.
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if (HWREGB(USB_TXCSRLx_BASE) & USB_TXCSRL1_TXRDY)
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HWREGB(USB_TXCSRLx_BASE) = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
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else
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HWREGB(USB_TXCSRLx_BASE) = USB_TXCSRL1_CLRDT;
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fifo_size = usb_musb_get_fifo_size(ep_cfg->ep_mps, &used);
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USB->TXFIFOSZ = fifo_size & 0x0f;
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USB->TXFIFOADD = (usb_dc_cfg.fifo_size_offset >> 3);
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usb_dc_cfg.fifo_size_offset += used;
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}
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USBC_SelectActiveEp(old_ep_idx);
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return 0;
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}
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int usbd_ep_close(const uint8_t ep)
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{
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return 0;
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}
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int usbd_ep_set_stall(const uint8_t ep)
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{
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uint8_t ep_idx = USB_EP_GET_IDX(ep);
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uint8_t old_ep_idx;
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old_ep_idx = USBC_GetActiveEp();
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USBC_SelectActiveEp(ep_idx);
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if (USB_EP_DIR_IS_OUT(ep)) {
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if (ep_idx == 0x00) {
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HWREGB(USB_TXCSRLx_BASE) |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC);
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} else {
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HWREGB(USB_RXCSRLx_BASE) |= USB_RXCSRL1_STALL;
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}
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} else {
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if (ep_idx == 0x00) {
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HWREGB(USB_TXCSRLx_BASE) |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC);
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} else {
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HWREGB(USB_TXCSRLx_BASE) |= USB_TXCSRL1_STALL;
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}
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}
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USBC_SelectActiveEp(old_ep_idx);
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return 0;
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}
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int usbd_ep_clear_stall(const uint8_t ep)
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{
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uint8_t ep_idx = USB_EP_GET_IDX(ep);
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uint8_t old_ep_idx;
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old_ep_idx = USBC_GetActiveEp();
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USBC_SelectActiveEp(ep_idx);
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if (USB_EP_DIR_IS_OUT(ep)) {
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if (ep_idx == 0x00) {
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HWREGB(USB_TXCSRLx_BASE) &= ~USB_CSRL0_STALLED;
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} else {
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// Clear the stall on an OUT endpoint.
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HWREGB(USB_RXCSRLx_BASE) &= ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED);
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// Reset the data toggle.
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HWREGB(USB_RXCSRLx_BASE) |= USB_RXCSRL1_CLRDT;
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}
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} else {
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if (ep_idx == 0x00) {
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HWREGB(USB_TXCSRLx_BASE) &= ~USB_CSRL0_STALLED;
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} else {
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// Clear the stall on an IN endpoint.
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HWREGB(USB_TXCSRLx_BASE) &= ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED);
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// Reset the data toggle.
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HWREGB(USB_TXCSRLx_BASE) |= USB_TXCSRL1_CLRDT;
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}
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}
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USBC_SelectActiveEp(old_ep_idx);
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return 0;
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}
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int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
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{
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return 0;
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}
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int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes)
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{
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int ret = 0;
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uint8_t ep_idx = USB_EP_GET_IDX(ep);
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uint32_t timeout = 0xffffff;
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uint8_t old_ep_idx;
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old_ep_idx = USBC_GetActiveEp();
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USBC_SelectActiveEp(ep_idx);
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if (!data && data_len) {
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ret = -1;
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goto _RET;
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}
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if (ep_idx == 0x00) {
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while (HWREGB(USB_TXCSRLx_BASE) & USB_CSRL0_TXRDY) {
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if (HWREGB(USB_TXCSRLx_BASE) & USB_CSRL0_ERROR) {
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ret = -2;
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goto _RET;
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}
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if (!(timeout--)) {
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ret = -3;
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goto _RET;
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}
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}
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} else {
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while (HWREGB(USB_TXCSRLx_BASE) & USB_TXCSRL1_TXRDY) {
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if ((HWREGB(USB_TXCSRLx_BASE) & USB_TXCSRL1_ERROR) || (HWREGB(USB_TXCSRLx_BASE) & USB_TXCSRL1_UNDRN)) {
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ret = -2;
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goto _RET;
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}
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if (!(timeout--)) {
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ret = -3;
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goto _RET;
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}
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}
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}
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if (!data_len) {
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ret = 0;
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goto _RET;
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}
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ep0_last_size = data_len;
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if (data_len > usb_dc_cfg.in_ep[ep_idx].ep_mps) {
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data_len = usb_dc_cfg.in_ep[ep_idx].ep_mps;
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}
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usb_musb_write_packet(ep_idx, (uint8_t *)data, data_len);
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if (ep_idx != 0) {
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HWREGB(USB_TXCSRLx_BASE) = USB_TXCSRL1_TXRDY;
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}
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if (ret_bytes) {
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*ret_bytes = data_len;
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}
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_RET:
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USBC_SelectActiveEp(old_ep_idx);
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return ret;
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}
|
|
|
|
int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_t *read_bytes)
|
|
{
|
|
int ret = 0;
|
|
uint8_t ep_idx = USB_EP_GET_IDX(ep);
|
|
uint32_t read_count;
|
|
uint8_t old_ep_idx;
|
|
|
|
old_ep_idx = USBC_GetActiveEp();
|
|
USBC_SelectActiveEp(ep_idx);
|
|
if (!data && max_data_len) {
|
|
ret = -1;
|
|
goto _RET;
|
|
}
|
|
|
|
if (!max_data_len) {
|
|
if (ep_idx != 0x00) {
|
|
HWREGB(USB_RXCSRLx_BASE) &= ~(USB_RXCSRL1_RXRDY);
|
|
}
|
|
ret = 0;
|
|
goto _RET;
|
|
}
|
|
|
|
if (ep_idx == 0x00) {
|
|
if (usb_ep0_state == USB_EP0_STATE_SETUP) {
|
|
memcpy(data, (uint8_t *)&usb_dc_cfg.setup, 8);
|
|
} else {
|
|
read_count = HWREGH(USB_RXCOUNTx_BASE);
|
|
read_count = MIN(read_count, max_data_len);
|
|
usb_musb_read_packet(0, data, read_count);
|
|
}
|
|
} else {
|
|
read_count = HWREGH(USB_RXCOUNTx_BASE);
|
|
read_count = MIN(read_count, max_data_len);
|
|
usb_musb_read_packet(ep_idx, data, read_count);
|
|
}
|
|
|
|
if (read_bytes) {
|
|
*read_bytes = read_count;
|
|
}
|
|
|
|
_RET:
|
|
USBC_SelectActiveEp(old_ep_idx);
|
|
return ret;
|
|
}
|
|
|
|
static void handle_ep0(void)
|
|
{
|
|
uint8_t ep0_status = USB->CSRL0;
|
|
|
|
if (ep0_status & USB_CSRL0_STALLED) {
|
|
USB->CSRL0 &= ~USB_CSRL0_STALLED;
|
|
return;
|
|
}
|
|
|
|
if (ep0_status & USB_CSRL0_SETEND) {
|
|
USB->CSRL0 = USB_CSRL0_SETENDC;
|
|
}
|
|
|
|
if (usb_dc_cfg.dev_addr > 0) {
|
|
USB->FADDR = usb_dc_cfg.dev_addr;
|
|
usb_dc_cfg.dev_addr = 0;
|
|
}
|
|
|
|
switch (usb_ep0_state) {
|
|
case USB_EP0_STATE_SETUP:
|
|
if (ep0_status & USB_CSRL0_RXRDY) {
|
|
uint32_t read_count = HWREGH(USB_RXCOUNTx_BASE);
|
|
|
|
if (read_count != 8) {
|
|
return;
|
|
}
|
|
|
|
usb_musb_read_packet(0, (uint8_t *)&usb_dc_cfg.setup, 8);
|
|
if (usb_dc_cfg.setup.wLength) {
|
|
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_RXRDYC;
|
|
} else {
|
|
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND;
|
|
}
|
|
|
|
usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
|
|
|
|
if (usb_dc_cfg.setup.wLength) {
|
|
if (usb_dc_cfg.setup.bmRequestType & 0x80) {
|
|
usb_ep0_state = USB_EP0_STATE_IN_DATA;
|
|
if (ep0_last_size > usb_dc_cfg.in_ep[0].ep_mps) {
|
|
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_TXRDY;
|
|
} else {
|
|
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND;
|
|
usb_ep0_state = USB_EP0_STATE_OUT_STATUS;
|
|
}
|
|
} else {
|
|
usb_ep0_state = USB_EP0_STATE_OUT_DATA;
|
|
}
|
|
} else {
|
|
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND;
|
|
usb_ep0_state = USB_EP0_STATE_IN_STATUS;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case USB_EP0_STATE_IN_DATA:
|
|
usbd_event_notify_handler(USBD_EVENT_EP0_IN_NOTIFY, NULL);
|
|
if (ep0_last_size > usb_dc_cfg.in_ep[0].ep_mps) {
|
|
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_TXRDY;
|
|
} else {
|
|
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND;
|
|
usb_ep0_state = USB_EP0_STATE_OUT_STATUS;
|
|
}
|
|
break;
|
|
case USB_EP0_STATE_IN_STATUS:
|
|
usb_ep0_state = USB_EP0_STATE_SETUP;
|
|
break;
|
|
case USB_EP0_STATE_OUT_DATA:
|
|
if (ep0_status & USB_CSRL0_RXRDY) {
|
|
usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
|
|
if (usb_dc_cfg.setup.wLength > usb_dc_cfg.out_ep[0].ep_mps) {
|
|
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_RXRDYC;
|
|
} else {
|
|
usb_ep0_state = USB_EP0_STATE_IN_STATUS;
|
|
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND;
|
|
}
|
|
}
|
|
break;
|
|
case USB_EP0_STATE_OUT_STATUS:
|
|
usb_ep0_state = USB_EP0_STATE_SETUP;
|
|
break;
|
|
}
|
|
}
|
|
|
|
#ifdef USB_MUSB_SUNXI
|
|
void USBD_IRQHandler(int irq, void *args)
|
|
#else
|
|
void USBD_IRQHandler(void)
|
|
#endif
|
|
{
|
|
uint32_t is;
|
|
uint32_t txis;
|
|
uint32_t rxis;
|
|
uint8_t old_ep_idx;
|
|
|
|
is = USB->IS;
|
|
txis = USB->TXIS;
|
|
rxis = USB->RXIS;
|
|
|
|
old_ep_idx = USBC_GetActiveEp();
|
|
/* Receive a reset signal from the USB bus */
|
|
if (is & USB_IS_RESET) {
|
|
usbd_event_notify_handler(USBD_EVENT_RESET, NULL);
|
|
USB->TXIE = USB_TXIE_EP0;
|
|
USB->RXIE = 0;
|
|
|
|
for (uint8_t i = 1; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
|
|
USB->EPIDX = i;
|
|
USB->TXFIFOSZ = 0;
|
|
USB->TXFIFOADD = 0;
|
|
USB->RXFIFOSZ = 0;
|
|
USB->RXFIFOADD = 0;
|
|
}
|
|
usb_dc_cfg.fifo_size_offset = USB_CTRL_EP_MPS;
|
|
}
|
|
|
|
if (is & USB_IS_SOF) {
|
|
}
|
|
|
|
if (is & USB_IS_RESUME) {
|
|
}
|
|
|
|
if (is & USB_IS_SUSPEND) {
|
|
}
|
|
|
|
USB->IS = is; // clear isr flag
|
|
txis &= USB->TXIE;
|
|
/* Handle EP0 interrupt */
|
|
if (txis & USB_TXIE_EP0) {
|
|
USBC_SelectActiveEp(0);
|
|
handle_ep0();
|
|
txis &= ~USB_TXIE_EP0;
|
|
USB->TXIS = USB_TXIE_EP0; // clear isr flag
|
|
}
|
|
|
|
while (txis) {
|
|
uint8_t ep_idx = __builtin_ctz(txis);
|
|
USBC_SelectActiveEp(ep_idx);
|
|
if (HWREGB(USB_TXCSRLx_BASE) & USB_TXCSRL1_UNDRN) {
|
|
HWREGB(USB_TXCSRLx_BASE) &= ~USB_TXCSRL1_UNDRN;
|
|
}
|
|
usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(0x80 | ep_idx));
|
|
txis &= ~(1 << ep_idx);
|
|
USB->TXIS = (1 << ep_idx); // clear isr flag
|
|
}
|
|
|
|
rxis &= USB->RXIE;
|
|
while (rxis) {
|
|
uint8_t ep_idx = __builtin_ctz(rxis);
|
|
USBC_SelectActiveEp(ep_idx);
|
|
if (HWREGB(USB_RXCSRLx_BASE) & USB_RXCSRL1_RXRDY)
|
|
usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(ep_idx & 0x7f));
|
|
rxis &= ~(1 << ep_idx);
|
|
USB->RXIS = (1 << ep_idx); // clear isr flag
|
|
}
|
|
|
|
USBC_SelectActiveEp(old_ep_idx);
|
|
}
|