291 lines
9.1 KiB
C
291 lines
9.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "esp_idf_version.h"
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#include "esp_intr_alloc.h"
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#include "esp_private/usb_phy.h"
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#include "soc/periph_defs.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "usbd_core.h"
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#include "usbh_core.h"
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#include "usb_dwc2_param.h"
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#define GET_USB_INDEX(reg_base) 0
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#define GET_USB_INTR_SOURCE(reg_base) ETS_USB_INTR_SOURCE
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#define GET_USB_PHY_TARGET(reg_base) USB_PHY_TARGET_INT
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#define GET_USB_PHY_SPEED(reg_base) USB_PHY_SPEED_UNDEFINED
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#ifdef CONFIG_IDF_TARGET_ESP32S2
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#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ
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#define DEFAULT_USB_INTR_SOURCE ETS_USB_INTR_SOURCE
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#elif CONFIG_IDF_TARGET_ESP32S3
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#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ
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#define DEFAULT_USB_INTR_SOURCE ETS_USB_INTR_SOURCE
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#elif CONFIG_IDF_TARGET_ESP32P4
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#undef GET_USB_INDEX
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#define GET_USB_INDEX(reg_base) ((reg_base) == (void*)ESP_USB_HS0_BASE ? 0 : 1)
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#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
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#define DEFAULT_USB_INTR_SOURCE ETS_USB_OTG_INTR_SOURCE
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#define USB_FS_INTR_SOURCE ETS_USB_OTG11_CH0_INTR_SOURCE
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#undef GET_USB_INTR_SOURCE
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#define GET_USB_INTR_SOURCE(reg_base) ((reg_base) == (void*)ESP_USB_HS0_BASE ? DEFAULT_USB_INTR_SOURCE : USB_FS_INTR_SOURCE)
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#undef GET_USB_PHY_TARGET
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#define GET_USB_PHY_TARGET(reg_base) ((reg_base) == (void*)ESP_USB_HS0_BASE ? USB_PHY_TARGET_UTMI : USB_PHY_TARGET_INT)
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#undef GET_USB_PHY_SPEED
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#define GET_USB_PHY_SPEED(reg_base) ((reg_base) == (void*)ESP_USB_HS0_BASE ? USB_PHY_SPEED_HIGH : USB_PHY_SPEED_FULL)
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#else
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#define DEFAULT_CPU_FREQ_MHZ 160
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#endif
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uint32_t SystemCoreClock = (DEFAULT_CPU_FREQ_MHZ * 1000 * 1000);
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static usb_phy_handle_t s_phy_handle[SOC_USB_OTG_PERIPH_NUM] = {NULL};
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static intr_handle_t s_interrupt_handle[SOC_USB_OTG_PERIPH_NUM] = {NULL};
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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const struct dwc2_user_params param_fs = {
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.phy_type = DWC2_PHY_TYPE_PARAM_FS,
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.device_dma_enable = true,
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.device_dma_desc_enable = false,
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.device_rx_fifo_size = (200 - 16 * 7),
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.device_tx_fifo_size = {
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[0] = 16, // 64 byte
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[1] = 16, // 64 byte
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[2] = 16, // 64 byte
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[3] = 16, // 64 byte
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[4] = 16, // 64 byte
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[5] = 16, // 64 byte
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[6] = 16, // 64 byte
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[7] = 0,
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[8] = 0,
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[9] = 0,
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[10] = 0,
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[11] = 0,
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[12] = 0,
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[13] = 0,
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[14] = 0,
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[15] = 0 },
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.host_dma_desc_enable = false,
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.host_rx_fifo_size = 80,
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.host_nperio_tx_fifo_size = 60, // 240 byte
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.host_perio_tx_fifo_size = 60, // 240 byte
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};
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#elif CONFIG_IDF_TARGET_ESP32P4
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const struct dwc2_user_params param_fs = {
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.phy_type = DWC2_PHY_TYPE_PARAM_FS,
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.device_dma_enable = true,
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.device_dma_desc_enable = false,
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.device_rx_fifo_size = (200 - 16 * 7),
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.device_tx_fifo_size = {
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[0] = 16, // 64 byte
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[1] = 16, // 64 byte
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[2] = 16, // 64 byte
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[3] = 16, // 64 byte
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[4] = 16, // 64 byte
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[5] = 16, // 64 byte
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[6] = 16, // 64 byte
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[7] = 0,
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[8] = 0,
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[9] = 0,
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[10] = 0,
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[11] = 0,
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[12] = 0,
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[13] = 0,
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[14] = 0,
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[15] = 0 },
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.host_dma_desc_enable = false,
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.host_rx_fifo_size = (200 - 60 - 60),
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.host_nperio_tx_fifo_size = 60, // 240 byte
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.host_perio_tx_fifo_size = 60, // 240 byte
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};
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const struct dwc2_user_params param_hs = {
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.phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
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.device_dma_enable = true,
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.device_dma_desc_enable = false,
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.device_rx_fifo_size = (896 - 16 - 128 - 128 - 128 - 128 - 16 - 16),
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.device_tx_fifo_size = {
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[0] = 16, // 64 byte
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[1] = 128, // 512 byte
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[2] = 128, // 512 byte
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[3] = 128, // 512 byte
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[4] = 128, // 512 byte
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[5] = 16, // 64 byte
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[6] = 16, // 64 byte
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[7] = 0,
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[8] = 0,
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[9] = 0,
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[10] = 0,
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[11] = 0,
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[12] = 0,
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[13] = 0,
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[14] = 0,
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[15] = 0 },
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.host_dma_desc_enable = false,
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.host_rx_fifo_size = (896 - 128 - 128),
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.host_nperio_tx_fifo_size = 128, // 512 byte
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.host_perio_tx_fifo_size = 128, // 512 byte
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};
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#endif
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static void usb_dc_interrupt_cb(void *arg_pv)
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{
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extern void USBD_IRQHandler(uint8_t busid);
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uint8_t busid = (uintptr_t)arg_pv;
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USBD_IRQHandler(busid);
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}
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void usb_dc_low_level_init(uint8_t busid)
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{
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esp_err_t ret;
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void *reg_base = (void*)g_usbdev_bus[busid].reg_base;
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(void)reg_base;
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usb_phy_config_t phy_config = {
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.controller = USB_PHY_CTRL_OTG,
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.otg_mode = USB_OTG_MODE_DEVICE,
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};
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phy_config.target = GET_USB_PHY_TARGET(reg_base);
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phy_config.otg_speed = GET_USB_PHY_SPEED(reg_base);
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ret = usb_new_phy(&phy_config, &s_phy_handle[GET_USB_INDEX(reg_base)]);
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if (ret != ESP_OK) {
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USB_LOG_ERR("USB Phy Init Failed!\r\n");
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return;
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}
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uintptr_t arg = busid;
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// TODO: Check when to enable interrupt
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ret = esp_intr_alloc(GET_USB_INTR_SOURCE(reg_base), ESP_INTR_FLAG_LOWMED, usb_dc_interrupt_cb, (void *)arg, &s_interrupt_handle[GET_USB_INDEX(reg_base)]);
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if (ret != ESP_OK) {
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USB_LOG_ERR("USB Interrupt Init Failed!\r\n");
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return;
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}
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USB_LOG_INFO("cherryusb, version: " CHERRYUSB_VERSION_STR "\r\n");
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}
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void usb_dc_low_level_deinit(uint8_t busid)
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{
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void *reg_base = (void*)g_usbdev_bus[busid].reg_base;
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(void)reg_base;
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if (s_interrupt_handle[GET_USB_INDEX(reg_base)]) {
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esp_intr_free(s_interrupt_handle[GET_USB_INDEX(reg_base)]);
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s_interrupt_handle[GET_USB_INDEX(reg_base)] = NULL;
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}
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if (s_phy_handle[GET_USB_INDEX(reg_base)]) {
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usb_del_phy(s_phy_handle[GET_USB_INDEX(reg_base)]);
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s_phy_handle[GET_USB_INDEX(reg_base)] = NULL;
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}
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}
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static void usb_hc_interrupt_cb(void *arg_pv)
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{
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extern void USBH_IRQHandler(uint8_t busid);
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uint8_t busid = (uintptr_t)arg_pv;
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USBH_IRQHandler(busid);
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}
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void usb_hc_low_level_init(struct usbh_bus *bus)
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{
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void *reg_base = (void*)bus->hcd.reg_base;
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(void)reg_base;
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// Host Library defaults to internal PHY
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usb_phy_config_t phy_config = {
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.controller = USB_PHY_CTRL_OTG,
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.otg_mode = USB_OTG_MODE_HOST,
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.otg_speed = USB_PHY_SPEED_UNDEFINED, // In Host mode, the speed is determined by the connected device
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.ext_io_conf = NULL,
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.otg_io_conf = NULL,
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};
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phy_config.target = GET_USB_PHY_TARGET(reg_base);
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esp_err_t ret = usb_new_phy(&phy_config, &s_phy_handle[GET_USB_INDEX(reg_base)]);
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if (ret != ESP_OK) {
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USB_LOG_ERR("USB Phy Init Failed!\r\n");
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return;
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}
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uintptr_t arg = bus->busid;
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// TODO: Check when to enable interrupt
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ret = esp_intr_alloc(GET_USB_INTR_SOURCE(reg_base), ESP_INTR_FLAG_LOWMED, usb_hc_interrupt_cb, (void*)(arg), &s_interrupt_handle[GET_USB_INDEX(reg_base)]);
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if (ret != ESP_OK) {
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USB_LOG_ERR("USB Interrupt Init Failed!\r\n");
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return;
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}
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USB_LOG_INFO("cherryusb, version: " CHERRYUSB_VERSION_STR "\r\n");
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}
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void usb_hc_low_level_deinit(struct usbh_bus *bus)
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{
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void *reg_base = (void*)bus->hcd.reg_base;
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(void)reg_base;
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if (s_interrupt_handle[GET_USB_INDEX(reg_base)]) {
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esp_intr_free(s_interrupt_handle[GET_USB_INDEX(reg_base)]);
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s_interrupt_handle[GET_USB_INDEX(reg_base)] = NULL;
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}
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if (s_phy_handle[GET_USB_INDEX(reg_base)]) {
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usb_del_phy(s_phy_handle[GET_USB_INDEX(reg_base)]);
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s_phy_handle[GET_USB_INDEX(reg_base)] = NULL;
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}
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}
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void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params)
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{
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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memcpy(params, ¶m_fs, sizeof(struct dwc2_user_params));
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#elif CONFIG_IDF_TARGET_ESP32P4
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if (reg_base == ESP_USB_HS0_BASE) {
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memcpy(params, ¶m_hs, sizeof(struct dwc2_user_params));
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} else {
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memcpy(params, ¶m_fs, sizeof(struct dwc2_user_params));
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}
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#endif
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#ifdef CONFIG_USB_DWC2_CUSTOM_FIFO
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struct usb_dwc2_user_fifo_config s_dwc2_fifo_config;
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dwc2_get_user_fifo_config(reg_base, &s_dwc2_fifo_config);
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params->device_rx_fifo_size = s_dwc2_fifo_config.device_rx_fifo_size;
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for (uint8_t i = 0; i < MAX_EPS_CHANNELS; i++)
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{
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params->device_tx_fifo_size[i] = s_dwc2_fifo_config.device_tx_fifo_size[i];
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}
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#endif
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}
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void usbd_dwc2_delay_ms(uint8_t ms)
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{
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vTaskDelay(pdMS_TO_TICKS(ms));
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}
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#ifdef CONFIG_USB_DCACHE_ENABLE
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#include "esp_cache.h"
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void usb_dcache_clean(uintptr_t addr, size_t size)
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{
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if (size == 0)
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return;
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esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M);
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}
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void usb_dcache_invalidate(uintptr_t addr, size_t size)
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{
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if (size == 0)
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return;
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esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_M2C);
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}
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void usb_dcache_flush(uintptr_t addr, size_t size)
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{
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if (size == 0)
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return;
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esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_DIR_M2C);
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}
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#endif |