552 lines
22 KiB
C
552 lines
22 KiB
C
/**
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*********************************************************************************
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*
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* @file ald_uart.h
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* @brief Header file of UART module library.
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*
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* @version V1.0
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* @date 21 Nov 2019
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* @author AE Team
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* @note
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* Change Logs:
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* Date Author Notes
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* 21 Nov 2019 AE Team The first version
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*
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* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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**********************************************************************************
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*/
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#ifndef __ALD_UART_H__
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#define __ALD_UART_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "utils.h"
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#include "ald_dma.h"
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/** @addtogroup ES32FXXX_ALD
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* @{
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*/
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/** @addtogroup UART
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* @{
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*/
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/**
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* @defgroup UART_Public_Macros UART Public Macros
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* @{
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*/
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#define UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK))
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#define UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK))
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#define UART_TX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK))
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#define UART_TX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK))
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#define UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK))
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#define UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK))
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#define UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK))
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#define UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK))
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#define UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK))
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#define UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK))
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#define UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK))
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#define UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK))
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#define UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK))
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#define UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK))
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#define UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK))
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#define UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK))
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#define UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK))
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#define UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK))
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#define UART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FCON, UART_FCON_TFRST_MSK))
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#define UART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FCON, UART_FCON_RFRST_MSK))
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#define UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK))
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#define UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK))
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#define UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK))
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#define UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK))
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#define UART_AUTOBR_REPT(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABRREPT_MSK))
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#define UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR))
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#define UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS))
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#define UART_ENABLE_SCARD_CLK(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK))
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#define UART_DISABLE_SCARD_CLK(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK))
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#define UART_ENABLE_SCARD_NACK(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK))
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#define UART_DISABLE_SCARD_NACK(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK))
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#define UART_SCARD_ENABLE(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK))
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#define UART_SCARD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK))
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/**
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* @}
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*/
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/** @defgroup UART_Public_Types UART Public Types
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* @{
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*/
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/**
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* @brief UART word length
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*/
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typedef enum {
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UART_WORD_LENGTH_8B = 0x0U, /**< 8-bits */
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UART_WORD_LENGTH_7B = 0x1U, /**< 7-bits */
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UART_WORD_LENGTH_6B = 0x2U, /**< 6-bits */
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UART_WORD_LENGTH_5B = 0x3U, /**< 5-bits */
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} uart_word_length_t;
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/**
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* @brief UART stop bits
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*/
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typedef enum {
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UART_STOP_BITS_1 = 0x0U, /**< 1-bits */
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UART_STOP_BITS_2 = 0x1U, /**< 2-bits */
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UART_STOP_BITS_0_5 = 0x0U, /**< 0.5-bits, using smartcard mode */
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UART_STOP_BITS_1_5 = 0x1U, /**< 1.5-bits, using smartcard mode */
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} uart_stop_bits_t;
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/**
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* @brief UART parity
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*/
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typedef enum {
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UART_PARITY_NONE = 0x0U, /**< Not parity */
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UART_PARITY_ODD = 0x1U, /**< Odd parity */
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UART_PARITY_EVEN = 0x3U, /**< Even parity */
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} uart_parity_t;
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/**
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* @brief UART mode
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*/
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typedef enum {
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UART_MODE_UART = 0x0U, /**< UART */
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UART_MODE_LIN = 0x1U, /**< LIN */
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UART_MODE_IrDA = 0x2U, /**< IrDA */
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UART_MODE_RS485 = 0x3U, /**< RS485 */
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UART_MODE_HDSEL = 0x4U, /**< Single-wire half-duplex */
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UART_MODE_SCARD = 0x5U, /**< Smart card */
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} uart_mode_t;
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/**
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* @brief UART hardware flow control
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*/
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typedef enum {
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UART_HW_FLOW_CTL_DISABLE = 0x0U, /**< Auto-flow-control disable */
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UART_HW_FLOW_CTL_ENABLE = 0x1U, /**< Auto-flow-control enable */
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} uart_hw_flow_ctl_t;
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/**
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* @brief ALD UART state
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*/
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typedef enum {
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UART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */
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UART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
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UART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */
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UART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */
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UART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */
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UART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */
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UART_STATE_TIMEOUT = 0x03U, /**< Timeout state */
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UART_STATE_ERROR = 0x04U, /**< Error */
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} uart_state_t;
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/**
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* @brief UART error codes
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*/
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typedef enum {
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UART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */
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UART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */
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UART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */
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UART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */
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UART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */
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UART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */
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} uart_error_t;
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/**
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* @brief UART init structure definition
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*/
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typedef struct {
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uint32_t baud; /**< Specifies the uart communication baud rate */
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uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */
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uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */
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uart_parity_t parity; /**< Specifies the parity mode */
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uart_mode_t mode; /**< Specifies uart mode */
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uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */
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} uart_init_t;
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/**
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* @brief UART handle structure definition
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*/
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typedef struct uart_handle_s {
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UART_TypeDef *perh; /**< UART registers base address */
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uart_init_t init; /**< UART communication parameters */
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uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */
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uint16_t tx_size; /**< UART Tx Transfer size */
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uint16_t tx_count; /**< UART Tx Transfer Counter */
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uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */
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uint16_t rx_size; /**< UART Rx Transfer size */
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uint16_t rx_count; /**< UART Rx Transfer Counter */
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dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */
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dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */
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lock_state_t lock; /**< Locking object */
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uart_state_t state; /**< UART communication state */
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uart_error_t err_code; /**< UART Error code */
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void (*tx_cplt_cbk)(struct uart_handle_s *arg); /**< Tx completed callback */
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void (*rx_cplt_cbk)(struct uart_handle_s *arg); /**< Rx completed callback */
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void (*error_cbk)(struct uart_handle_s *arg); /**< error callback */
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} uart_handle_t;
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/**
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* @brief UART RS485 configure structure definition
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*/
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typedef struct {
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type_func_t normal; /**< Normal mode */
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type_func_t dir; /**< Auto-direction mode */
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type_func_t invert; /**< Address detection invert */
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uint8_t addr; /**< Address for compare */
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} uart_rs485_config_t;
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/**
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* @brief Smart_card Rx/Tx handle retry time
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*/
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typedef enum {
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SCARD_RETRY_CNT0 = 0x0U, /**< retry time 0 */
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SCARD_RETRY_CNT1 = 0x1U, /**< retry time 1 */
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SCARD_RETRY_CNT2 = 0x2U, /**< retry time 2 */
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SCARD_RETRY_CNT3 = 0x3U, /**< retry time 3 */
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SCARD_RETRY_CNT4 = 0x4U, /**< retry time 4 */
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SCARD_RETRY_CNT5 = 0x5U, /**< retry time 5 */
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SCARD_RETRY_CNT6 = 0x6U, /**< retry time 6 */
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SCARD_RETRY_CNT7 = 0x7U, /**< retry time 7 */
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} scard_retry_t;
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/**
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* @brief UART Smart card configure structure definition
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*/
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typedef struct {
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uint8_t block_len; /**< Specifies the data block length.*/
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uint8_t pt; /**< Specifies the protect time*/
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scard_retry_t retry; /**< Specifies retry time.*/
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uint8_t clk_div; /**< Specifies the clock division.*/
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type_func_t clk_out; /**< Specifies the clock out */
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} uart_scard_config_t;
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/**
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* @brief LIN detection break length
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*/
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typedef enum {
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LIN_BREAK_LEN_10B = 0x0U, /**< 10-bit break */
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LIN_BREAK_LEN_11B = 0x1U, /**< 11-bit break */
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} uart_lin_break_len_t;
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/**
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* @brief UART TXFIFO size
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*/
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typedef enum {
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UART_TXFIFO_EMPTY = 0x0U, /**< Empty */
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UART_TXFIFO_2BYTE = 0x1U, /**< 2-Bytes */
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UART_TXFIFO_4BYTE = 0x2U, /**< 4-Bytes */
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UART_TXFIFO_8BYTE = 0x3U, /**< 8-Bytes */
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} uart_txfifo_t;
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/**
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* @brief UART RXFIFO size
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*/
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typedef enum {
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UART_RXFIFO_1BYTE = 0x0U, /**< 1-Byte */
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UART_RXFIFO_4BYTE = 0x1U, /**< 4-Bytes */
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UART_RXFIFO_8BYTE = 0x2U, /**< 8-Bytes */
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UART_RXFIFO_14BYTE = 0x3U, /**< 14-Bytes */
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} uart_rxfifo_t;
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/**
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* @brief UART auto-baud mode
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*/
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typedef enum {
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UART_ABRMOD_1_TO_0 = 0x0U, /**< Detect bit0:1, bit1:0 */
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UART_ABRMOD_1 = 0x1U, /**< Detect bit0:1 */
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UART_ABRMOD_0_TO_1 = 0x2U, /**< Detect bit0:0, bit1:1 */
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} uart_auto_baud_mode_t;
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/**
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* @brief UART DMA Requests
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*/
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typedef enum {
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UART_DMA_REQ_TX = 0x0U, /**< TX dma */
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UART_DMA_REQ_RX = 0x1U, /**< RX dma */
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} uart_dma_req_t;
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/**
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* @brief UART status types
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*/
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typedef enum {
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UART_STATUS_PERR = (1U << 0), /**< Parity error */
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UART_STATUS_FERR = (1U << 1), /**< Framing error */
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UART_STATUS_BKERR = (1U << 2), /**< Break error */
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UART_STATUS_CTSSTA = (1U << 3), /**< Clear to send status */
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UART_STATUS_RSBUSY = (1U << 8), /**< Receive shif register busy */
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UART_STATUS_RFTH = (1U << 9), /**< Receive FIFO trigger threshold */
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UART_STATUS_RFEMPTY = (1U << 10), /**< Receive FIFO empty */
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UART_STATUS_RFFULL = (1U << 11), /**< Receive FIFO full */
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UART_STATUS_RFOERR = (1U << 12), /**< Reveive FIFO overrun error */
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UART_STATUS_RFUERR = (1U << 13), /**< Receive FIFO underrun error */
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UART_STATUS_TSBUSY = (1U << 14), /**< Transmit shit register busy */
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UART_STATUS_TFTH = (1U << 15), /**< Transmit FIFO trigger threshold */
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UART_STATUS_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */
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UART_STATUS_TFFULL = (1U << 17), /**< Transmit FIFO full */
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UART_STATUS_TFOERR = (1U << 18), /**< Transmit FIFO overrun error */
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} uart_status_t;
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/**
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* @brief UART interrupt types
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*/
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typedef enum {
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UART_IT_RXBERR = (1U << 0), /**< Receiver byte error */
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UART_IT_ABEND = (1U << 1), /**< Auto-Baud rate detection end */
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UART_IT_ABTO = (1U << 2), /**< Auto-Baud rate detection timeout */
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UART_IT_DCTS = (1U << 3), /**< Delta CTS status */
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UART_IT_RXTO = (1U << 4), /**< Receiver timeout */
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UART_IT_ADDRM = (1U << 5), /**< Addredd match */
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UART_IT_LINBK = (1U << 6), /**< Lin break detection */
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UART_IT_EOB = (1U << 7), /**< End of block */
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UART_IT_NOISE = (1U << 8), /**< Start bit noise detection */
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UART_IT_RFTH = (1U << 9), /**< Receive FIFO trigger threshold */
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UART_IT_RFFULL = (1U << 11), /**< Receive FIFO full */
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UART_IT_RFOERR = (1U << 12), /**< Receive FIFO overrun */
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UART_IT_RFUERR = (1U << 13), /**< Reveive FIFO underrun */
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UART_IT_TBC = (1U << 14), /**< Transmit shift register empty */
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UART_IT_TFTH = (1U << 15), /**< Transmit FIFO trigger threshold */
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UART_IT_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */
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UART_IT_TFOVER = (1U << 18), /**< Transmit FIFO overrun */
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} uart_it_t;
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/**
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* @brief UART flags types
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*/
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typedef enum {
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UART_IF_RXBERR = (1U << 0), /**< Receiver byte error */
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UART_IF_ABEND = (1U << 1), /**< Auto-Baud rate detection end */
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UART_IF_ABTO = (1U << 2), /**< Auto-Baud rate detection timeout */
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UART_IF_DCTS = (1U << 3), /**< Delta CTS status */
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UART_IF_RXTO = (1U << 4), /**< Receiver timeout */
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UART_IF_ADDRM = (1U << 5), /**< Addredd match */
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UART_IF_LINBK = (1U << 6), /**< Lin break detection */
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UART_IF_EOB = (1U << 7), /**< End of block */
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UART_IF_NOISE = (1U << 8), /**< Start bit noise detection */
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UART_IF_RFTH = (1U << 9), /**< Receive FIFO trigger threshold */
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UART_IF_RFFULL = (1U << 11), /**< Receive FIFO full */
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UART_IF_RFOERR = (1U << 12), /**< Receive FIFO overrun */
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UART_IF_RFUERR = (1U << 13), /**< Reveive FIFO underrun */
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UART_IF_TBC = (1U << 14), /**< Transmit shift register empty */
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UART_IF_TFTH = (1U << 15), /**< Transmit FIFO trigger threshold */
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UART_IF_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */
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UART_IF_TFOVER = (1U << 18), /**< Transmit FIFO overrun */
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} uart_flag_t;
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/**
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* @}
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*/
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/** @defgroup UART_Private_Macros UART Private Macros
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* @{
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*/
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#define IS_UART_SCARD(x)(((x) == UART4) || \
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((x) == UART5))
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#define IS_UART_ALL(x) (((x) == UART0) || \
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((x) == UART1) || \
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((x) == UART2) || \
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((x) == UART3) || \
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((x) == UART4) || \
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((x) == UART5))
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#define IS_UART_WORD_LENGTH(x) (((x) == UART_WORD_LENGTH_5B) || \
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((x) == UART_WORD_LENGTH_6B) || \
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((x) == UART_WORD_LENGTH_7B) || \
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((x) == UART_WORD_LENGTH_8B))
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#define IS_UART_STOPBITS(x) (((x) == UART_STOP_BITS_1) || \
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((x) == UART_STOP_BITS_2) || \
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((x) == UART_STOP_BITS_0_5) || \
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((x) == UART_STOP_BITS_1_5))
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#define IS_UART_PARITY(x) (((x) == UART_PARITY_NONE) || \
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((x) == UART_PARITY_ODD) || \
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((x) == UART_PARITY_EVEN))
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|
#define IS_UART_MODE(x) (((x) == UART_MODE_UART) || \
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((x) == UART_MODE_LIN) || \
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((x) == UART_MODE_IrDA) || \
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|
((x) == UART_MODE_HDSEL) || \
|
|
((x) == UART_MODE_SCARD) || \
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|
((x) == UART_MODE_RS485))
|
|
#define IS_UART_HARDWARE_FLOW_CONTROL(x) \
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|
(((x) == UART_HW_FLOW_CTL_DISABLE) || \
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|
((x) == UART_HW_FLOW_CTL_ENABLE))
|
|
#define IS_UART_LIN_BREAK_LEN(x) (((x) == LIN_BREAK_LEN_10B) || \
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|
((x) == LIN_BREAK_LEN_11B))
|
|
#define IS_UART_TXFIFO_TYPE(x) (((x) == UART_TXFIFO_EMPTY) || \
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|
((x) == UART_TXFIFO_2BYTE) || \
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|
((x) == UART_TXFIFO_4BYTE) || \
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|
((x) == UART_TXFIFO_8BYTE))
|
|
#define IS_UART_RXFIFO_TYPE(x) (((x) == UART_RXFIFO_1BYTE) || \
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|
((x) == UART_RXFIFO_4BYTE) || \
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|
((x) == UART_RXFIFO_8BYTE) || \
|
|
((x) == UART_RXFIFO_14BYTE))
|
|
#define IS_UART_AUTO_BAUD_MODE(x) (((x) == UART_ABRMOD_1_TO_0) || \
|
|
((x) == UART_ABRMOD_1) || \
|
|
((x) == UART_ABRMOD_0_TO_1))
|
|
#define IS_UART_DMA_REQ(x) (((x) == UART_DMA_REQ_TX) || \
|
|
((x) == UART_DMA_REQ_RX))
|
|
#define IS_UART_STATUS(x) (((x) == UART_STATUS_PERR) || \
|
|
((x) == UART_STATUS_FERR) || \
|
|
((x) == UART_STATUS_BKERR) || \
|
|
((x) == UART_STATUS_CTSSTA) || \
|
|
((x) == UART_STATUS_RSBUSY) || \
|
|
((x) == UART_STATUS_RFEMPTY) || \
|
|
((x) == UART_STATUS_RFFULL) || \
|
|
((x) == UART_STATUS_RFOERR) || \
|
|
((x) == UART_STATUS_RFUERR) || \
|
|
((x) == UART_STATUS_TSBUSY) || \
|
|
((x) == UART_STATUS_RFTH) || \
|
|
((x) == UART_STATUS_TFTH) || \
|
|
((x) == UART_STATUS_TFEMPTY) || \
|
|
((x) == UART_STATUS_TFFULL) || \
|
|
((x) == UART_STATUS_TFOERR))
|
|
#define IS_UART_IT(x) (((x) == UART_IT_RXBERR) || \
|
|
((x) == UART_IT_ABEND) || \
|
|
((x) == UART_IT_ABTO) || \
|
|
((x) == UART_IT_DCTS) || \
|
|
((x) == UART_IT_RXTO) || \
|
|
((x) == UART_IT_ADDRM) || \
|
|
((x) == UART_IT_LINBK) || \
|
|
((x) == UART_IT_EOB) || \
|
|
((x) == UART_IT_NOISE) || \
|
|
((x) == UART_IT_RFTH) || \
|
|
((x) == UART_IT_RFFULL) || \
|
|
((x) == UART_IT_RFOERR) || \
|
|
((x) == UART_IT_RFUERR) || \
|
|
((x) == UART_IT_TBC) || \
|
|
((x) == UART_IT_TFTH) || \
|
|
((x) == UART_IT_TFEMPTY) || \
|
|
((x) == UART_IT_TFOVER))
|
|
#define IS_UART_IF(x) (((x) == UART_IF_RXBERR) || \
|
|
((x) == UART_IF_ABEND) || \
|
|
((x) == UART_IF_ABTO) || \
|
|
((x) == UART_IF_DCTS) || \
|
|
((x) == UART_IF_RXTO) || \
|
|
((x) == UART_IF_ADDRM) || \
|
|
((x) == UART_IF_LINBK) || \
|
|
((x) == UART_IF_EOB) || \
|
|
((x) == UART_IF_NOISE) || \
|
|
((x) == UART_IF_RFTH) || \
|
|
((x) == UART_IF_RFFULL) || \
|
|
((x) == UART_IF_RFOERR) || \
|
|
((x) == UART_IF_RFUERR) || \
|
|
((x) == UART_IF_TBC) || \
|
|
((x) == UART_IF_TFTH) || \
|
|
((x) == UART_IF_TFEMPTY) || \
|
|
((x) == UART_IF_TFOVER))
|
|
#define IS_UART_SCARD_CLK(x) (((x) <= 0x1F))
|
|
#define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21))
|
|
#define IS_UART_DATA(x) ((x) <= 0x1FF)
|
|
|
|
#define UART_STATE_TX_MASK (1U << 4)
|
|
#define UART_STATE_RX_MASK (1U << 5)
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup UART_Public_Functions
|
|
* @{
|
|
*/
|
|
|
|
/** @addtogroup UART_Public_Functions_Group1
|
|
* @{
|
|
*/
|
|
/* Initialization functions */
|
|
void ald_uart_init(uart_handle_t *hperh);
|
|
void ald_uart_reset(uart_handle_t *hperh);
|
|
void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config);
|
|
void ald_uart_scard_config(uart_handle_t *hperh, uart_scard_config_t *config);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup UART_Public_Functions_Group2
|
|
* @{
|
|
*/
|
|
/* IO operation functions */
|
|
ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
|
|
ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
|
|
ald_status_t ald_uart_send_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
|
|
ald_status_t ald_uart_recv_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
|
|
ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size);
|
|
ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size);
|
|
ald_status_t ald_uart_recv_frame_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out);
|
|
|
|
ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
|
|
ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
|
|
ald_status_t ald_uart_dma_pause(uart_handle_t *hperh);
|
|
ald_status_t ald_uart_dma_resume(uart_handle_t *hperh);
|
|
ald_status_t ald_uart_dma_stop(uart_handle_t *hperh);
|
|
|
|
void ald_uart_irq_handler(uart_handle_t *hperh);
|
|
void ald_uart_irq_handler_fast(uart_handle_t *hperh);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup UART_Public_Functions_Group3
|
|
* @{
|
|
*/
|
|
/* Peripheral Control functions */
|
|
void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state);
|
|
void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state);
|
|
void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config);
|
|
void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config);
|
|
void uart_lin_break_detect_irq(uart_handle_t *hperh, type_func_t status);
|
|
void ald_uart_lin_send_break(uart_handle_t *hperh);
|
|
void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len);
|
|
void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode);
|
|
ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout);
|
|
it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it);
|
|
flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status);
|
|
flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag);
|
|
flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag);
|
|
void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup UART_Public_Functions_Group4
|
|
* @{
|
|
*/
|
|
/* Peripheral State and Errors functions */
|
|
uart_state_t ald_uart_get_state(uart_handle_t *hperh);
|
|
uint32_t ald_uart_get_error(uart_handle_t *hperh);
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __ALD_UART_H__ */
|