143 lines
4.2 KiB
C
143 lines
4.2 KiB
C
/**
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*********************************************************************************
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*
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* @file ald_sram.h
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* @brief Header file of EBI_SRAM driver
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*
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* @version V1.0
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* @date 07 Dec 2019
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* @author AE Team
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* @note
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* Change Logs:
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* Date Author Notes
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* 07 Dec 2019 AE Team The first version
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*
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* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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**********************************************************************************
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*/
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#ifndef __ALD_SRAM_H__
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#define __ALD_SRAM_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "ald_ebi.h"
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#include "ald_dma.h"
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/** @addtogroup ES32FXXX_ALD
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* @{
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*/
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/** @addtogroup SRAM
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* @{
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*/
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/** @defgroup SRAM_Public_Types SRAM Public Types
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* @{
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*/
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/**
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* @brief ALD SRAM State structures definition
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*/
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typedef enum {
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ALD_SRAM_STATE_RESET = 0x00U, /**< SRAM not yet initialized or disabled */
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ALD_SRAM_STATE_READY = 0x01U, /**< SRAM initialized and ready for use */
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ALD_SRAM_STATE_BUSY = 0x02U, /**< SRAM internal process is ongoing */
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ALD_SRAM_STATE_ERROR = 0x03U, /**< SRAM error state */
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ALD_SRAM_STATE_PROTECTED = 0x04U /**< SRAM peripheral NORSRAM device write protected */
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} ald_sram_state_t;
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/**
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* @brief SRAM handle Structure definition
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*/
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typedef struct {
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EBI_NOR_SRAM_TypeDef *instance; /**< Register base address */
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EBI_NOR_SRAM_EXTENDED_TypeDef *ext; /**< Extended mode register base address */
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ald_ebi_nor_sram_init_t init; /**< SRAM device control configuration parameters */
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lock_state_t lock; /**< SRAM locking object */
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__IO ald_sram_state_t state; /**< SRAM device access state */
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dma_handle_t hdma; /**< SRAM DMA Handle parameters */
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void(*cplt_cbk)(void *arg); /**< DMA transmit completely callback function */
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} sram_handle_t;
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/**
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* @}
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*/
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/** @addtogroup SRAM_Public_Functions
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* @{
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*/
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/** @addtogroup SRAM_Public_Functions_Group1
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* @{
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*/
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/* Initialization functions */
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ald_status_t ald_sram_init(sram_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing);
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ald_status_t ald_sram_deinit(sram_handle_t *hperh);
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/**
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* @}
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*/
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/** @addtogroup SRAM_Public_Functions_Group2
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* @{
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*/
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/* I/O operation functions */
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ald_status_t ald_sram_read_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size);
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ald_status_t ald_sram_write_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size);
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ald_status_t ald_sram_read_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size);
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ald_status_t ald_sram_write_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size);
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ald_status_t ald_sram_read_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size);
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ald_status_t ald_sram_write_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size);
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#ifdef ALD_DMA
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ald_status_t ald_sram_read_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch);
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ald_status_t ald_sram_write_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch);
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#endif
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/**
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* @}
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*/
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/** @addtogroup SRAM_Public_Functions_Group3
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* @{
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*/
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/* Control functions */
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ald_status_t ald_sram_write_enable(sram_handle_t *hperh);
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ald_status_t ald_sram_write_disable(sram_handle_t *hperh);
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/**
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* @}
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*/
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/** @addtogroup SRAM_Public_Functions_Group4
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* @{
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*/
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/* State functions */
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ald_sram_state_t ald_sram_get_state(sram_handle_t *hperh);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ALD_SRAM_H__ */
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