Compare commits
11 Commits
v1.5.3-rc2
...
v1.5.3.99
| Author | SHA1 | Date | |
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18fc474696 | ||
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fd49804470 | ||
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af556f4f03 | ||
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901adfe19b | ||
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6e2434a83c | ||
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dba6022bc9 | ||
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f9fbf881ba | ||
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de844391bd | ||
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5ffe9cbe7f | ||
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047c872e99 | ||
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fc05e18231 |
@@ -474,7 +474,7 @@ if PKG_USING_CHERRYUSB
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config PKG_USING_CHERRYUSB_LATEST_VERSION
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bool "latest"
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config PKG_USING_CHERRYUSB_V010502
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config PKG_USING_CHERRYUSB_V010503
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bool "v1.5.3"
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config PKG_USING_CHERRYUSB_V010502
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bool "v1.5.2"
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2
VERSION
2
VERSION
@@ -1,5 +1,5 @@
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VERSION_MAJOR = 1
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VERSION_MINOR = 5
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PATCHLEVEL = 3
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VERSION_TWEAK = 0
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VERSION_TWEAK = 99
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EXTRAVERSION = 0
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@@ -306,16 +306,6 @@ int usbh_cdc_ecm_eth_output(uint32_t buflen)
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return usbh_submit_urb(&g_cdc_ecm_class.bulkout_urb);
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}
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__WEAK void usbh_cdc_ecm_run(struct usbh_cdc_ecm *cdc_ecm_class)
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{
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(void)cdc_ecm_class;
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}
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__WEAK void usbh_cdc_ecm_stop(struct usbh_cdc_ecm *cdc_ecm_class)
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{
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(void)cdc_ecm_class;
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}
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const struct usbh_class_driver cdc_ecm_class_driver = {
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.driver_name = "cdc_ecm",
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.connect = usbh_cdc_ecm_connect,
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@@ -386,16 +386,6 @@ int usbh_cdc_ncm_eth_output(uint32_t buflen)
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return usbh_submit_urb(&g_cdc_ncm_class.bulkout_urb);
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}
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__WEAK void usbh_cdc_ncm_run(struct usbh_cdc_ncm *cdc_ncm_class)
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{
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(void)cdc_ncm_class;
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}
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__WEAK void usbh_cdc_ncm_stop(struct usbh_cdc_ncm *cdc_ncm_class)
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{
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(void)cdc_ncm_class;
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}
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const struct usbh_class_driver cdc_ncm_class_driver = {
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.driver_name = "cdc_ncm",
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.connect = usbh_cdc_ncm_connect,
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10
class/vendor/net/usbh_asix.c
vendored
10
class/vendor/net/usbh_asix.c
vendored
@@ -795,16 +795,6 @@ int usbh_asix_eth_output(uint32_t buflen)
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return usbh_submit_urb(&g_asix_class.bulkout_urb);
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}
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__WEAK void usbh_asix_run(struct usbh_asix *asix_class)
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{
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(void)asix_class;
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}
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__WEAK void usbh_asix_stop(struct usbh_asix *asix_class)
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{
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(void)asix_class;
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}
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static const uint16_t asix_id_table[][2] = {
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{ 0x0B95, 0x772B },
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{ 0x0B95, 0x7720 },
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10
class/vendor/net/usbh_rtl8152.c
vendored
10
class/vendor/net/usbh_rtl8152.c
vendored
@@ -2251,16 +2251,6 @@ int usbh_rtl8152_eth_output(uint32_t buflen)
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return usbh_submit_urb(&g_rtl8152_class.bulkout_urb);
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}
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__WEAK void usbh_rtl8152_run(struct usbh_rtl8152 *rtl8152_class)
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{
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(void)rtl8152_class;
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}
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__WEAK void usbh_rtl8152_stop(struct usbh_rtl8152 *rtl8152_class)
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{
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(void)rtl8152_class;
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}
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static const uint16_t rtl_id_table[][2] = {
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{ 0x0BDA, 0x8152 },
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{ 0, 0 },
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@@ -578,16 +578,6 @@ int usbh_rndis_eth_output(uint32_t buflen)
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return usbh_submit_urb(&g_rndis_class.bulkout_urb);
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}
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__WEAK void usbh_rndis_run(struct usbh_rndis *rndis_class)
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{
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(void)rndis_class;
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}
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__WEAK void usbh_rndis_stop(struct usbh_rndis *rndis_class)
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{
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(void)rndis_class;
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}
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static const struct usbh_class_driver rndis_class_driver = {
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.driver_name = "rndis",
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.connect = usbh_rndis_connect,
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@@ -16,6 +16,6 @@
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#endif
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#define CHERRYUSB_VERSION 0x010503
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#define CHERRYUSB_VERSION_STR "v1.5.3"
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#define CHERRYUSB_VERSION_STR "v1.5.3.99"
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#endif
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@@ -19,7 +19,7 @@ struct usbotg_core_priv {
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bool usbd_initialized;
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usbd_event_handler_t device_event_callback;
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usbh_event_handler_t host_event_callback;
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uint8_t current_mode;
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uint8_t request_mode;
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usb_osal_sem_t change_sem;
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usb_osal_thread_t change_thread;
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} g_usbotg_core[CONFIG_USB_OTG_MAX_BUS];
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@@ -66,9 +66,9 @@ static void usbotg_rolechange_thread(void *argument)
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while (1) {
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if (usb_osal_sem_take(g_usbotg_core[busid].change_sem, USB_OSAL_WAITING_FOREVER) == 0) {
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if (g_usbotg_core[busid].current_mode == USBOTG_MODE_HOST) {
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if (g_usbotg_core[busid].request_mode == USBOTG_MODE_HOST) {
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usbotg_host_initialize(busid);
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} else if (g_usbotg_core[busid].current_mode == USBOTG_MODE_DEVICE) {
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} else if (g_usbotg_core[busid].request_mode == USBOTG_MODE_DEVICE) {
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usbotg_device_initialize(busid);
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}
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}
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@@ -110,13 +110,13 @@ int usbotg_deinitialize(uint8_t busid)
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USB_ASSERT_MSG(busid < CONFIG_USB_OTG_MAX_BUS, "bus overflow\r\n");
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if (g_usbotg_core[busid].usbd_initialized) {
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g_usbotg_core[busid].usbd_initialized = false;
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usbd_deinitialize(busid);
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g_usbotg_core[busid].usbd_initialized = false;
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}
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if (g_usbotg_core[busid].usbh_initialized) {
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g_usbotg_core[busid].usbh_initialized = false;
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usbh_deinitialize(busid);
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g_usbotg_core[busid].usbh_initialized = false;
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}
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if (g_usbotg_core[busid].change_thread) {
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@@ -135,7 +135,7 @@ void usbotg_trigger_role_change(uint8_t busid, uint8_t mode)
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{
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USB_ASSERT_MSG(busid < CONFIG_USB_OTG_MAX_BUS, "bus overflow\r\n");
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g_usbotg_core[busid].current_mode = mode;
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g_usbotg_core[busid].request_mode = mode;
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if (g_usbotg_core[busid].change_sem) {
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usb_osal_sem_give(g_usbotg_core[busid].change_sem);
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@@ -146,9 +146,9 @@ void USBOTG_IRQHandler(uint8_t busid)
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{
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USB_ASSERT_MSG(busid < CONFIG_USB_OTG_MAX_BUS, "bus overflow\r\n");
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if (g_usbotg_core[busid].current_mode == USBOTG_MODE_HOST && g_usbotg_core[busid].usbh_initialized) {
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if (g_usbotg_core[busid].usbh_initialized) {
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USBH_IRQHandler(busid);
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} else if (g_usbotg_core[busid].current_mode == USBOTG_MODE_DEVICE && g_usbotg_core[busid].usbd_initialized) {
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} else if (g_usbotg_core[busid].usbd_initialized) {
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USBD_IRQHandler(busid);
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}
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}
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@@ -123,12 +123,12 @@
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AUDIO_AS_FEEDBACK_DESCRIPTOR_LEN(1))
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#endif
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#define AUDIO_AC_SIZ (AUDIO_SIZEOF_AC_HEADER_DESC(2) + \
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AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \
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AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(2, 1) + \
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AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \
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AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \
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AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(2, 1) + \
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#define AUDIO_AC_SIZ (AUDIO_SIZEOF_AC_HEADER_DESC(2) + \
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AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \
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AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM, 1) + \
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AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \
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AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \
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AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM, 1) + \
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AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC)
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#ifdef CONFIG_USBDEV_ADVANCE_DESC
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@@ -83,7 +83,7 @@ static const uint8_t *device_quality_descriptor_callback(uint8_t speed)
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static const char *string_descriptor_callback(uint8_t speed, uint8_t index)
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{
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if (index > 3) {
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if (index > 4) {
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return NULL;
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}
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return string_descriptors[index];
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@@ -65,14 +65,23 @@ void usb_osal_thread_delete(usb_osal_thread_t thread)
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void usb_osal_thread_schedule_other(void)
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{
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struct tcb_s *tcb = nxsched_self();
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const int old_priority = tcb->sched_priority;
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struct sched_param param;
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int old_priority;
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nxsched_set_priority(tcb, SCHED_PRIORITY_MIN);
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/* Get current priority (pid=0 means current task) */
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assert(sched_getparam(0, ¶m) == 0);
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old_priority = param.sched_priority;
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/* Set to minimum priority to yield CPU to other tasks */
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param.sched_priority = SCHED_PRIORITY_MIN;
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assert(sched_setparam(0, ¶m) == 0);
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/* Yield CPU to other tasks */
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sched_yield();
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nxsched_set_priority(tcb, old_priority);
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/* Restore original priority */
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param.sched_priority = old_priority;
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assert(sched_setparam(0, ¶m) == 0);
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}
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usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count)
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@@ -30,6 +30,14 @@
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#error TCPIP_THREAD_STACKSIZE must be >= 1024
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#endif
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#if !defined(CONFIG_USBHOST_PLATFORM_CDC_ECM) && \
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!defined(CONFIG_USBHOST_PLATFORM_CDC_RNDIS) && \
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!defined(CONFIG_USBHOST_PLATFORM_CDC_NCM) && \
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!defined(CONFIG_USBHOST_PLATFORM_ASIX) && \
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!defined(CONFIG_USBHOST_PLATFORM_RTL8152)
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#error "Please enable at least one USB Ethernet platform in usb_config.h or Kconfig"
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#endif
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// #define CONFIG_USBHOST_PLATFORM_CDC_ECM
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// #define CONFIG_USBHOST_PLATFORM_CDC_RNDIS
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// #define CONFIG_USBHOST_PLATFORM_CDC_NCM
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@@ -48,6 +48,14 @@
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#error RT_LWIP_TCPTHREAD_STACKSIZE must be >= 2048
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#endif
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#if !defined(CONFIG_USBHOST_PLATFORM_CDC_ECM) && \
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!defined(CONFIG_USBHOST_PLATFORM_CDC_RNDIS) && \
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!defined(CONFIG_USBHOST_PLATFORM_CDC_NCM) && \
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!defined(CONFIG_USBHOST_PLATFORM_ASIX) && \
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!defined(CONFIG_USBHOST_PLATFORM_RTL8152)
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#error "Please enable at least one USB Ethernet platform in usb_config.h or Kconfig"
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#endif
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// #define CONFIG_USBHOST_PLATFORM_CDC_ECM
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// #define CONFIG_USBHOST_PLATFORM_CDC_RNDIS
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// #define CONFIG_USBHOST_PLATFORM_CDC_NCM
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@@ -339,22 +339,6 @@ static inline void dwc2_chan_enable_csplit(struct usbh_bus *bus, uint8_t ch_num,
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}
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}
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static inline void dwc2_chan_reenable(struct usbh_bus *bus, uint8_t ch_num)
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{
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__IO uint32_t tmpreg;
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uint8_t is_oddframe;
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is_oddframe = (((uint32_t)USB_OTG_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;
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USB_OTG_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
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USB_OTG_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;
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/* Set host channel enable */
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tmpreg = USB_OTG_HC(ch_num)->HCCHAR;
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tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
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tmpreg |= USB_OTG_HCCHAR_CHENA;
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USB_OTG_HC(ch_num)->HCCHAR = tmpreg;
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}
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|
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static void dwc2_halt(struct usbh_bus *bus, uint8_t ch_num)
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{
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volatile uint32_t ChannelEna = (USB_OTG_HC(ch_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;
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@@ -751,7 +735,7 @@ int usb_hc_init(struct usbh_bus *bus)
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}
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|
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if (g_dwc2_hcd[bus->hcd.hcd_id].hw_params.snpsid > 0x4F54292AU) {
|
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USB_OTG_HOST->HCFG |= USB_OTG_HFIR_RELOAD_CTRL;
|
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USB_OTG_HOST->HFIR |= USB_OTG_HFIR_RELOAD_CTRL;
|
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}
|
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|
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/* Clear all pending HC Interrupts */
|
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@@ -1215,12 +1199,15 @@ static void dwc2_inchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num)
|
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/* restart ssplit transfer */
|
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switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) {
|
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case USB_ENDPOINT_TYPE_CONTROL:
|
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chan->do_csplit = 0;
|
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dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length);
|
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break;
|
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case USB_ENDPOINT_TYPE_BULK:
|
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chan->do_csplit = 0;
|
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dwc2_chan_enable_csplit(bus, ch_num, false);
|
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dwc2_chan_reenable(bus, ch_num);
|
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dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length);
|
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break;
|
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case USB_ENDPOINT_TYPE_INTERRUPT:
|
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chan->do_csplit = 0;
|
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dwc2_chan_enable_csplit(bus, ch_num, false);
|
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urb->errorcode = -USB_ERR_NAK;
|
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dwc2_urb_waitup(urb);
|
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@@ -1235,17 +1222,39 @@ static void dwc2_inchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num)
|
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}
|
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} else if (chan_intstatus & USB_OTG_HCINT_ACK) {
|
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if (chan->do_ssplit) {
|
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/* start ssplit transfer */
|
||||
/* start csplit transfer */
|
||||
chan->do_csplit = 1;
|
||||
chan->ssplit_frame = dwc2_get_full_frame_num(bus);
|
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dwc2_chan_enable_csplit(bus, ch_num, true);
|
||||
dwc2_chan_reenable(bus, ch_num);
|
||||
switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) {
|
||||
case USB_ENDPOINT_TYPE_CONTROL:
|
||||
dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length);
|
||||
break;
|
||||
case USB_ENDPOINT_TYPE_BULK:
|
||||
case USB_ENDPOINT_TYPE_INTERRUPT:
|
||||
dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else if (chan_intstatus & USB_OTG_HCINT_NYET) {
|
||||
if (chan->do_ssplit) {
|
||||
/* restart csplit transfer */
|
||||
dwc2_chan_enable_csplit(bus, ch_num, true);
|
||||
dwc2_chan_reenable(bus, ch_num);
|
||||
chan->do_csplit = 1;
|
||||
chan->ssplit_frame = dwc2_get_full_frame_num(bus);
|
||||
switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) {
|
||||
case USB_ENDPOINT_TYPE_CONTROL:
|
||||
dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length);
|
||||
break;
|
||||
case USB_ENDPOINT_TYPE_BULK:
|
||||
case USB_ENDPOINT_TYPE_INTERRUPT:
|
||||
dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
urb->errorcode = -USB_ERR_NAK;
|
||||
dwc2_urb_waitup(urb);
|
||||
@@ -1352,12 +1361,15 @@ static void dwc2_outchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num)
|
||||
/* restart ssplit transfer */
|
||||
switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) {
|
||||
case USB_ENDPOINT_TYPE_CONTROL:
|
||||
chan->do_csplit = 0;
|
||||
dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length);
|
||||
break;
|
||||
case USB_ENDPOINT_TYPE_BULK:
|
||||
chan->do_csplit = 0;
|
||||
dwc2_chan_enable_csplit(bus, ch_num, false);
|
||||
dwc2_chan_reenable(bus, ch_num);
|
||||
dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length);
|
||||
break;
|
||||
case USB_ENDPOINT_TYPE_INTERRUPT:
|
||||
chan->do_csplit = 0;
|
||||
dwc2_chan_enable_csplit(bus, ch_num, false);
|
||||
urb->errorcode = -USB_ERR_NAK;
|
||||
dwc2_urb_waitup(urb);
|
||||
@@ -1372,17 +1384,39 @@ static void dwc2_outchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num)
|
||||
}
|
||||
} else if (chan_intstatus & USB_OTG_HCINT_ACK) {
|
||||
if (chan->do_ssplit) {
|
||||
/* start ssplit transfer */
|
||||
/* start csplit transfer */
|
||||
chan->do_csplit = 1;
|
||||
chan->ssplit_frame = dwc2_get_full_frame_num(bus);
|
||||
dwc2_chan_enable_csplit(bus, ch_num, true);
|
||||
dwc2_chan_reenable(bus, ch_num);
|
||||
switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) {
|
||||
case USB_ENDPOINT_TYPE_CONTROL:
|
||||
dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length);
|
||||
break;
|
||||
case USB_ENDPOINT_TYPE_BULK:
|
||||
case USB_ENDPOINT_TYPE_INTERRUPT:
|
||||
dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else if (chan_intstatus & USB_OTG_HCINT_NYET) {
|
||||
if (chan->do_ssplit) {
|
||||
/* restart csplit transfer */
|
||||
dwc2_chan_enable_csplit(bus, ch_num, true);
|
||||
dwc2_chan_reenable(bus, ch_num);
|
||||
chan->do_csplit = 1;
|
||||
chan->ssplit_frame = dwc2_get_full_frame_num(bus);
|
||||
switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) {
|
||||
case USB_ENDPOINT_TYPE_CONTROL:
|
||||
dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer + urb->actual_length - 8, urb->transfer_buffer_length);
|
||||
break;
|
||||
case USB_ENDPOINT_TYPE_BULK:
|
||||
case USB_ENDPOINT_TYPE_INTERRUPT:
|
||||
dwc2_bulk_intr_urb_init(bus, ch_num, urb, urb->transfer_buffer + urb->actual_length, urb->transfer_buffer_length);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
urb->errorcode = -USB_ERR_NAK;
|
||||
dwc2_urb_waitup(urb);
|
||||
|
||||
@@ -1,18 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2025, YC113
|
||||
* Copyright (c) 2026, HakumenJean
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-01-06 HakumenJean first version
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include "usbh_core.h"
|
||||
#include "usb_hc_ehci.h"
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_WITH_OHCI
|
||||
#include "usb_hc_ohci.h"
|
||||
#endif
|
||||
|
||||
#include "hal_clk.h"
|
||||
#include "hal_reset.h"
|
||||
#include "interrupt.h"
|
||||
#include "drv_reg_base.h"
|
||||
#include "drv_clock.h"
|
||||
|
||||
#if CONFIG_USBHOST_MAX_BUS != 2
|
||||
#error "t113 has 2 usb host controller"
|
||||
@@ -34,6 +43,13 @@
|
||||
#error "t113 usb ehci no iso register"
|
||||
#endif
|
||||
|
||||
#define USB0_OTG_BASE_ADDR (0x04100000U)
|
||||
#define USB0_PHY_BASE_ADDR (0x04100400U)
|
||||
#define USB0_EHCI_BASE_ADDR (0x04101000U)
|
||||
|
||||
#define USB1_EHCI_BASE_ADDR (0x04200000U)
|
||||
#define USB1_PHY_BASE_ADDR (0x04200800U)
|
||||
|
||||
void usb_select_phyTohci(void)
|
||||
{
|
||||
*(volatile rt_uint32_t *)(USB0_OTG_BASE_ADDR + 0x420) &= ~(1 << 0);
|
||||
@@ -41,55 +57,52 @@ void usb_select_phyTohci(void)
|
||||
|
||||
void usb_gate_open(rt_uint8_t busid)
|
||||
{
|
||||
rt_uint32_t addr;
|
||||
|
||||
addr = (rt_uint32_t)&CCU->usb0_clk + busid * 4;
|
||||
|
||||
if(busid == 0) {
|
||||
if (busid == 0) {
|
||||
/* otg gate open*/
|
||||
CCU->usb_bgr |= 1 << 8;
|
||||
hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_BUS_OTG));
|
||||
|
||||
/* otg bus reset */
|
||||
CCU->usb_bgr &= ~(1 << 24);
|
||||
sdelay(10);
|
||||
CCU->usb_bgr |= (1 << 24);
|
||||
sdelay(10);
|
||||
hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_BUS_OTG));
|
||||
|
||||
/* ehci gate open */
|
||||
hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_BUS_EHCI0));
|
||||
|
||||
/* ehci bus reset */
|
||||
hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_BUS_EHCI0));
|
||||
|
||||
/* ohci gate open */
|
||||
hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_BUS_OHCI0));
|
||||
|
||||
/* ohci bus reset */
|
||||
hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_BUS_OHCI0));
|
||||
|
||||
/* clock enable */
|
||||
hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_USB_OHCI0));
|
||||
|
||||
/* reset phy */
|
||||
hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_USB_PHY0));
|
||||
|
||||
/* otg phy select */
|
||||
usb_select_phyTohci();
|
||||
} else {
|
||||
/* ehci gate open */
|
||||
hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_BUS_EHCI1));
|
||||
|
||||
/* ehci bus reset */
|
||||
hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_BUS_EHCI1));
|
||||
|
||||
/* ohci gate open */
|
||||
hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_BUS_OHCI1));
|
||||
|
||||
/* ohci bus reset */
|
||||
hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_BUS_OHCI1));
|
||||
|
||||
/* clock enable */
|
||||
hal_clock_enable(hal_clock_get(HAL_SUNXI_CCU, CLK_USB_OHCI1));
|
||||
|
||||
/* reset phy */
|
||||
hal_reset_control_reset(hal_reset_control_get(HAL_SUNXI_RESET, RST_USB_PHY1));
|
||||
}
|
||||
|
||||
/* ehci gate open */
|
||||
CCU->usb_bgr |= (1 << 4) << busid;
|
||||
|
||||
/* ehci bus reset */
|
||||
CCU->usb_bgr &= ~((1 << 20) << busid);
|
||||
sdelay(10);
|
||||
CCU->usb_bgr |= (1 << 20) << busid;
|
||||
sdelay(10);
|
||||
|
||||
/* ohci gate open */
|
||||
CCU->usb_bgr |= 1 << busid;
|
||||
|
||||
/* ohci bus reset */
|
||||
CCU->usb_bgr &= ~((1 << 16) << busid);
|
||||
sdelay(10);
|
||||
CCU->usb_bgr |= (1 << 16) << busid;
|
||||
sdelay(10);
|
||||
|
||||
sdelay(10);
|
||||
|
||||
/* clock enable */
|
||||
*(volatile rt_uint32_t *)addr &= ~(3 << 24);
|
||||
*(volatile rt_uint32_t *)addr |= (1 << 31) | (1 << 24);
|
||||
|
||||
/* reset phy */
|
||||
*(volatile rt_uint32_t *)addr &= ~(1 << 30);
|
||||
sdelay(10);
|
||||
*(volatile rt_uint32_t *)addr |= 1 << 30;
|
||||
sdelay(10);
|
||||
|
||||
/* otg phy select */
|
||||
if(busid == 0) usb_select_phyTohci();
|
||||
|
||||
USB_LOG_DBG("usb%d gate : %X, clock : %X\n", busid, CCU->usb_bgr, *(volatile rt_uint32_t *)addr);
|
||||
}
|
||||
|
||||
void usb_clean_siddp(struct usbh_bus *bus)
|
||||
@@ -109,10 +122,10 @@ void usb_hci_set_passby(struct usbh_bus *bus)
|
||||
|
||||
void t113_ehci_isr(int vector, void *arg)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
|
||||
struct usbh_bus *bus = (struct usbh_bus *)arg;
|
||||
|
||||
rt_interrupt_enter();
|
||||
|
||||
USB_LOG_DBG("t113_ehci_isr");
|
||||
|
||||
extern void USBH_IRQHandler(uint8_t busid);
|
||||
@@ -125,10 +138,10 @@ void t113_ehci_isr(int vector, void *arg)
|
||||
|
||||
void t113_ohci_isr(int vector, void *arg)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
|
||||
struct usbh_bus *bus = (struct usbh_bus *)arg;
|
||||
|
||||
rt_interrupt_enter();
|
||||
|
||||
USB_LOG_DBG("t113_ohci_isr");
|
||||
|
||||
extern void OHCI_IRQHandler(uint8_t busid);
|
||||
@@ -149,8 +162,9 @@ void usb_hc_low_level_init(struct usbh_bus *bus)
|
||||
usb_hci_set_passby(bus);
|
||||
|
||||
/* register EHCI interrupt callback */
|
||||
vector = T113_IRQ_USB0_EHCI + (bus->busid > 0 ? 3 : 0);
|
||||
vector = SUNXI_IRQ_USB0_EHCI + (bus->busid > 0 ? 3 : 0);
|
||||
rt_hw_interrupt_install(vector, t113_ehci_isr, bus, RT_NULL);
|
||||
rt_hw_interrupt_set_priority(vector, 11 << 4);
|
||||
rt_hw_interrupt_umask(vector);
|
||||
|
||||
/* register OHCI interrupt callback */
|
||||
@@ -196,8 +210,26 @@ int __usbh_init(void)
|
||||
#ifdef PKG_CHERRYUSB_HOST
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
INIT_ENV_EXPORT(__usbh_init);
|
||||
|
||||
#ifdef CONFIG_USB_DCACHE_ENABLE
|
||||
void usb_dcache_clean(uintptr_t addr, size_t size)
|
||||
{
|
||||
rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)addr, size);
|
||||
}
|
||||
|
||||
void usb_dcache_invalidate(uintptr_t addr, size_t size)
|
||||
{
|
||||
rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)addr, size);
|
||||
}
|
||||
|
||||
void usb_dcache_flush(uintptr_t addr, size_t size)
|
||||
{
|
||||
rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)addr, size);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -17,7 +17,7 @@
|
||||
#undef USB_POWER_RESUME
|
||||
|
||||
#ifndef CONFIG_USB_MUSB_SIFLI
|
||||
#error must define CONFIG_USB_MUSB_SIFLI when use sunxi chips
|
||||
#error must define CONFIG_USB_MUSB_SIFLI when use sifli chips
|
||||
#endif
|
||||
|
||||
#include "bf0_hal.h"
|
||||
|
||||
@@ -524,7 +524,7 @@ static uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port)
|
||||
return speed;
|
||||
}
|
||||
|
||||
static int musb_pipe_alloc(void)
|
||||
static int musb_pipe_alloc(struct usbh_bus *bus)
|
||||
{
|
||||
int chidx;
|
||||
uintptr_t flags;
|
||||
@@ -769,7 +769,7 @@ int usbh_submit_urb(struct usbh_urb *urb)
|
||||
if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_CONTROL) {
|
||||
chidx = 0;
|
||||
} else {
|
||||
chidx = musb_pipe_alloc();
|
||||
chidx = musb_pipe_alloc(bus);
|
||||
if (chidx == -1) {
|
||||
return -USB_ERR_NOMEM;
|
||||
}
|
||||
@@ -1023,9 +1023,11 @@ void USBH_IRQHandler(uint8_t busid)
|
||||
|
||||
bus = &g_usbhost_bus[busid];
|
||||
|
||||
#if 0
|
||||
if (!(HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) & USB_DEVCTL_HOST)) {
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
is = HWREGB(USB_BASE + MUSB_IS_OFFSET);
|
||||
txis = HWREGH(USB_BASE + MUSB_TXIS_OFFSET);
|
||||
|
||||
@@ -217,10 +217,9 @@ static int usbh_hci_host_rcv_pkt(uint8_t *data, uint32_t len)
|
||||
buf = usbh_bt_acl_recv(data, remaining);
|
||||
break;
|
||||
|
||||
case USB_BLUETOOTH_HCI_SCO:
|
||||
case USB_BLUETOOTH_HCI_ISO:
|
||||
buf = usbh_bt_iso_recv(data, remaining);
|
||||
break;
|
||||
|
||||
default:
|
||||
USB_LOG_ERR("Unknown HCI type %u\r\n", pkt_indicator);
|
||||
return -1;
|
||||
|
||||
Reference in New Issue
Block a user