fix(port/dwc2/usb_glue_st): fix GCCFG in stm32h7rs

Signed-off-by: sakumisu <1203593632@qq.com>

CMakeLists.txt

@@ -71,7 +71,7 @@ elseif(ESP_PLATFORM)
         ${cherryusb_incs}
         ${freertos_include}
         PRIV_REQUIRES
-        usb esp_mm
+        usb esp_mm esp_netif
         LDFRAGMENTS
         ${ldfragments}
     )

README.md

@@ -204,7 +204,7 @@ TODO
 |AllwinnerTech  |  F1C100S/F1C200S | musb |[cherryusb_rtt_f1c100s](https://github.com/CherryUSB/cherryusb_rtt_f1c100s)|<= latest | the same with musb |
 |Bekencorp      |  bk7256/bk7258 | musb |[bk_idk](https://github.com/CherryUSB/bk_idk)| v0.7.0 | the same with musb |
 |Sophgo         |  cv18xx | dwc2 |[cvi_alios_open](https://github.com/CherryUSB/cvi_alios_open)| v0.7.0 | TBD |
-|WCH            |  CH32V307/ch58x | ch32_usbfs/ch32_usbhs/ch58x |[wch_repo](https://github.com/CherryUSB/cherryusb_wch)|<= v0.10.2 | TBD |
+|WCH            |  CH32V307/ch58x | ch32_usbfs/ch32_usbhs/ch58x |[wch_repo](https://github.com/CherryUSB/cherryusb_wch)|<= v0.10.2/>=v1.5.0 | TBD |
 
 ## Package Support
 

README_zh.md

@@ -204,7 +204,7 @@ TODO
 |AllwinnerTech  |  F1C100S/F1C200S | musb |[cherryusb_rtt_f1c100s](https://github.com/CherryUSB/cherryusb_rtt_f1c100s)|<= latest | the same with musb |
 |Bekencorp      |  bk7256/bk7258 | musb |[bk_idk](https://github.com/CherryUSB/bk_idk)| v0.7.0 | the same with musb |
 |Sophgo         |  cv18xx | dwc2 |[cvi_alios_open](https://github.com/CherryUSB/cvi_alios_open)| v0.7.0 | TBD |
-|WCH            |  CH32V307/ch58x | ch32_usbfs/ch32_usbhs/ch58x |[wch_repo](https://github.com/CherryUSB/cherryusb_wch)|<= v0.10.2 | TBD |
+|WCH            |  CH32V307/ch58x | ch32_usbfs/ch32_usbhs/ch58x |[wch_repo](https://github.com/CherryUSB/cherryusb_wch)|<= v0.10.2/>=v1.5.0 | TBD |
 
 ## 软件包支持
 

cherryusb.cmake

@@ -257,7 +257,11 @@ if(CONFIG_CHERRYUSB_HOST)
     OR CONFIG_CHERRYUSB_HOST_RTL8152
     OR CONFIG_CHERRYUSB_HOST_BL616
     )
-        list(APPEND cherryusb_srcs platform/lwip/usbh_lwip.c)
+        if("${CONFIG_CHERRYUSB_OSAL}" STREQUAL "idf")
+            list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/platform/idf/usbh_net.c)
+        else()
+            list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/platform/lwip/usbh_lwip.c)
+        endif()
     endif()
 
     if(CONFIG_CHERRYUSB_HOST_EHCI_BL)

class/msc/usbd_msc.c

@@ -807,7 +807,9 @@ static bool SCSI_CBWDecode(uint8_t busid, uint32_t nbytes)
                 //ret = SCSI_verify10(NULL, 0);
                 ret = false;
                 break;
-
+            case SCSI_CMD_SYNCHCACHE10:
+                ret = true;
+                break;
             default:
                 SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND);
                 USB_LOG_WRN("unsupported cmd:0x%02x\r\n", g_usbd_msc[busid].cbw.CB[0]);

class/vendor/net/usbh_rtl8152.c

@@ -1138,7 +1138,7 @@ static void ocp_write_dword(struct usbh_rtl8152 *tp, uint16_t type, uint16_t ind
 static uint16_t ocp_read_word(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index)
 {
     uint32_t data;
-    uint32_t tmp;
+    uint32_t tmp = 0;
     uint16_t byen = BYTE_EN_WORD;
     uint8_t shift = index & 2;
 
@@ -1178,7 +1178,7 @@ static void ocp_write_word(struct usbh_rtl8152 *tp, uint16_t type, uint16_t inde
 static uint8_t ocp_read_byte(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index)
 {
     uint32_t data;
-    uint32_t tmp;
+    uint32_t tmp = 0;
     uint8_t shift = index & 3;
 
     index &= ~3;
@@ -1254,7 +1254,7 @@ static inline int r8152_mdio_read(struct usbh_rtl8152 *tp, uint32_t reg_addr)
 static uint8_t usbh_rtl8152_get_version(struct usbh_rtl8152 *rtl8152_class)
 {
     uint8_t version;
-    uint32_t temp;
+    uint32_t temp = 0;
     uint32_t ocp_data;
 
     usbh_rtl8152_read_regs(rtl8152_class, PLA_TCR0, MCU_TYPE_PLA, 4, &temp);

docs/source/support/index.rst

@@ -24,6 +24,11 @@
 
 .. figure:: img/mtpdev.png
 
+- 从机 TMC 类驱动
+
+.. figure:: img/tmcdev1.png
+.. figure:: img/tmcdev2.png
+
 - USB 网卡类高性能版本优化,包含 CDC-NCM, CDC-RNDIS, 私有类驱动（支持多包发送和接收），下面举例 RNDIS
 
 .. figure:: img/rndistx.png

docs/source/usb/usb2.0_basic.rst

@@ -138,6 +138,10 @@ USB 对这个问题的解决办法，就是强制插 0，也就是（位填充
 在数据被NRZI编码之前，在数据流中每六个连续的1之后插入一个0，以强制NRZI数据流中的过渡，这使接收器逻辑至少每七位有一次数据转换，以保证数据和时钟的锁定。比特填充是从同步模式开始启用。结束同步模式的数据 "一 "被算作是序列中的第一个 "一"。序列中的第一个。除了高速EOP期间，发射器的位填充总是被强制执行。如果需要按照
 位填充规则的要求，零位将被插入，即使它是数据包结束（EOP）信号前的最后一位。接收器必须对NRZI数据进行解码，识别填充位，并将其丢弃。
 
+.. caution:: 以下内容可以用一张图概括，了解即可，没有必要死记硬背
+
+.. figure:: img/usbstruct.png
+
 USB 字段(域)
 ---------------------
 

docs/source/version.rst

@@ -106,7 +106,7 @@ v1.5.0
 
 - **协议栈内部全局 buffer 需要使用 USB_ALIGN_UP 对齐, 用于开启 dcache 并且不使能 nocache 时使用**
 - **完善 ehci/ohci dcache 模式下的处理**， add CONFIG_USB_EHCI_DESC_DCACHE_ENABLE for qh&qtd&itd, add CONFIG_USB_OHCI_DESC_DCACHE_ENABLE for ed&td
-- **平台代码更新，平台相关转移到 platform，增加 lvgl 键鼠支持，blackmagic 支持，filex 支持**
+- **平台代码更新，平台相关转移到 platform，增加 lvgl 键鼠支持，blackmagic 支持，filex 支持, zephyr disk支持，esp-idf netif支持**
 - **device sof callback 支持**
 - **dwc2 、fsdev st 下实现底层 API 和中断，直接调用 HAL_PCD_MSP 和 HAL_HCD_MSP，不需要用户复制粘贴**
 - **DWC2 实现 SPLIT 功能，高速模式下支持外部高速 hub 对接 FS/LS 设备**
@@ -116,11 +116,13 @@ v1.5.0
 - rndis/ECM device， msc demo 更新，支持 rt-thread 下免修改
 - **memcpy 全部使用 usb_memcpy 替换，arm 库存在非对其访问问题**
 - **重构 device mtp 驱动（收费使用）**
+- **device tmc 驱动（收费使用）**
 - **重构device video 传输，直接在图像数据中填充 uvc header，达到zero memcpy**
 - **增加 usb_osal_thread_schedule_other api，用于在释放 class 资源之前，先释放所有 class 线程，避免释放 class 资源以后线程还在使用该 class 资源**
-- **dwc2 device 增加 dcache 功能，可用于 STM32H7/H7R/ESP32P4**
+- **dwc2 device 增加 dcache 功能，可用于 cortex-M7/ESP32P4**
 - **bouffalo/hpm/esp/st/nxp dcache api 支持**
-- ch32 device iso 更新
+- ch32 device iso 更新，IP 目录重新分类
 - cmake，scons，kconfig 更新
-- 使用 USB_ASSERT_MSG 对部分代码检查
-- N32H4，mm32f5 支持
+- 使用 USB_ASSERT_MSG 对部分代码检查，全面性 warning 修复
+- N32H4/MM32F5 device 支持
+- 默认使能 CONFIG_USBDEV_ADVANCE_DESC

osal/idf/usb_config.h

@@ -168,7 +168,7 @@
 #define CONFIG_USBHOST_PSC_PRIO 0
 #endif
 #ifndef CONFIG_USBHOST_PSC_STACKSIZE
-#define CONFIG_USBHOST_PSC_STACKSIZE 2048
+#define CONFIG_USBHOST_PSC_STACKSIZE 4096
 #endif
 
 //#define CONFIG_USBHOST_GET_STRING_DESC

platform/fatfs/usbh_fatfs.c

@@ -36,7 +36,7 @@ int USB_disk_read(BYTE *buff, LBA_t sector, UINT count)
     align_buf = (uint8_t *)buff;
 #ifdef CONFIG_USB_DCACHE_ENABLE
     if ((uint32_t)buff & (CONFIG_USB_ALIGN_SIZE - 1)) {
-        align_buf = (uint8_t *)memalign(CONFIG_USB_ALIGN_SIZE, count * active_msc_class->blocksize);
+        align_buf = (uint8_t *)aligned_alloc(CONFIG_USB_ALIGN_SIZE, count * active_msc_class->blocksize);
         if (!align_buf) {
             printf("msc get align buf failed\r\n");
             return -USB_ERR_NOMEM;
@@ -66,7 +66,7 @@ int USB_disk_write(const BYTE *buff, LBA_t sector, UINT count)
     align_buf = (uint8_t *)buff;
 #ifdef CONFIG_USB_DCACHE_ENABLE
     if ((uint32_t)buff & (CONFIG_USB_ALIGN_SIZE - 1)) {
-        align_buf = (uint8_t *)memalign(CONFIG_USB_ALIGN_SIZE, count * active_msc_class->blocksize);
+        align_buf = (uint8_t *)aligned_alloc(CONFIG_USB_ALIGN_SIZE, count * active_msc_class->blocksize);
         if (!align_buf) {
             printf("msc get align buf failed\r\n");
             return -USB_ERR_NOMEM;

platform/idf/usbh_net.c

@@ -0,0 +1,408 @@
+/*
+ * Copyright (c) 2025, Loogg
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdlib.h>
+#include <inttypes.h>
+#include "lwip/netif.h"
+#include "esp_log.h"
+#include "esp_event.h"
+#include "esp_check.h"
+#include "esp_netif.h"
+#include "usbh_core.h"
+
+#if TCPIP_THREAD_STACKSIZE < 1024
+#error TCPIP_THREAD_STACKSIZE must be >= 1024
+#endif
+
+// #define CONFIG_USBHOST_PLATFORM_CDC_ECM
+// #define CONFIG_USBHOST_PLATFORM_CDC_RNDIS
+// #define CONFIG_USBHOST_PLATFORM_CDC_NCM
+// #define CONFIG_USBHOST_PLATFORM_ASIX
+// #define CONFIG_USBHOST_PLATFORM_RTL8152
+// #define CONFIG_USBHOST_PLATFORM_BL616
+
+struct usbh_net_netif_glue {
+    esp_netif_driver_base_t base;
+    esp_event_handler_instance_t ins_got_ip;
+    void *usbh_class;
+    esp_err_t (*transmit)(void *h, void *buffer, size_t len);
+};
+
+static void usbh_net_input_common(struct usbh_net_netif_glue *netif_glue, uint8_t *buf, uint32_t len)
+{
+    uint8_t *input_buf = buf;
+
+#if !LWIP_TCPIP_CORE_LOCKING_INPUT
+    input_buf = usb_osal_malloc(len);
+    if (input_buf == NULL) {
+        USB_LOG_ERR("No memory to alloc input buffer\r\n");
+        return;
+    }
+    usb_memcpy(input_buf, buf, len);
+#endif
+
+    esp_netif_receive(netif_glue->base.netif, input_buf, len, NULL);
+}
+
+static void usbh_net_free(void *h, void *buffer)
+{
+#if !LWIP_TCPIP_CORE_LOCKING_INPUT
+    usb_osal_free(buffer);
+#endif
+}
+
+static esp_err_t usbh_net_post_attach(esp_netif_t *esp_netif, void *args)
+{
+    struct usbh_net_netif_glue *netif_glue = (struct usbh_net_netif_glue *)args;
+
+    netif_glue->base.netif = esp_netif;
+
+    // set driver related config to esp-netif
+    esp_netif_driver_ifconfig_t driver_ifconfig = {
+        .handle = netif_glue,
+        .transmit = netif_glue->transmit,
+        .driver_free_rx_buffer = usbh_net_free,
+    };
+
+    ESP_ERROR_CHECK(esp_netif_set_driver_config(esp_netif, &driver_ifconfig));
+
+    return ESP_OK;
+}
+
+static void usbh_net_action_got_ip(void *handler_args, esp_event_base_t base, int32_t event_id, void *event_data)
+{
+    struct usbh_net_netif_glue *netif_glue = (struct usbh_net_netif_glue *)handler_args;
+    ip_event_got_ip_t *event = (ip_event_got_ip_t *)event_data;
+    const esp_netif_ip_info_t *ip_info = &event->ip_info;
+    USB_LOG_INFO("NETIF %s Got IP Address\r\n", esp_netif_get_ifkey(netif_glue->base.netif));
+    USB_LOG_INFO("IP:" IPSTR "\r\n", IP2STR(&ip_info->ip));
+    USB_LOG_INFO("MASK:" IPSTR "\r\n", IP2STR(&ip_info->netmask));
+    USB_LOG_INFO("GW:" IPSTR "\r\n\r\n", IP2STR(&ip_info->gw));
+}
+
+static esp_err_t usbh_net_netif_glue_init_common(struct usbh_net_netif_glue *netif_glue, void *usbh_class, esp_err_t (*transmit)(void *h, void *buffer, size_t len))
+{
+    netif_glue->usbh_class = usbh_class;
+    netif_glue->transmit = transmit;
+    netif_glue->base.post_attach = usbh_net_post_attach;
+
+    return esp_event_handler_instance_register(IP_EVENT, IP_EVENT_ETH_GOT_IP, usbh_net_action_got_ip, netif_glue, &netif_glue->ins_got_ip);
+}
+
+static esp_err_t usbh_net_netif_glue_deinit_common(struct usbh_net_netif_glue *netif_glue)
+{
+    return esp_event_handler_instance_unregister(IP_EVENT, IP_EVENT_ETH_GOT_IP, netif_glue->ins_got_ip);
+}
+
+#ifdef CONFIG_USBHOST_PLATFORM_CDC_ECM
+#include "usbh_cdc_ecm.h"
+
+struct usbh_net_netif_glue g_cdc_ecm_netif_glue;
+
+static esp_err_t usbh_cdc_ecm_transmit(void *h, void *buffer, size_t len)
+{
+    int ret;
+    (void)h;
+
+    usb_memcpy(usbh_cdc_ecm_get_eth_txbuf(), buffer, len);
+    ret = usbh_cdc_ecm_eth_output(len);
+    if (ret < 0) {
+        return ESP_FAIL;
+    }
+
+    return ESP_OK;
+}
+
+void usbh_cdc_ecm_eth_input(uint8_t *buf, uint32_t buflen)
+{
+    usbh_net_input_common(&g_cdc_ecm_netif_glue, buf, buflen);
+}
+
+void usbh_cdc_ecm_run(struct usbh_cdc_ecm *cdc_ecm_class)
+{
+    memset(&g_cdc_ecm_netif_glue, 0, sizeof(struct usbh_net_netif_glue));
+
+    esp_netif_inherent_config_t base_cfg = ESP_NETIF_INHERENT_DEFAULT_ETH();
+    base_cfg.if_key = "u0";
+    base_cfg.if_desc = "usbh cdc ecm";
+
+    esp_netif_config_t netif_cfg = ESP_NETIF_DEFAULT_ETH();
+    netif_cfg.base = &base_cfg;
+    esp_netif_t *esp_netif = esp_netif_new(&netif_cfg);
+
+    usbh_net_netif_glue_init_common(&g_cdc_ecm_netif_glue, cdc_ecm_class, usbh_cdc_ecm_transmit);
+    esp_netif_attach(esp_netif, &g_cdc_ecm_netif_glue.base);
+
+    esp_netif_set_mac(esp_netif, cdc_ecm_class->mac);
+
+    esp_netif_action_start(esp_netif, NULL, 0, NULL);
+    esp_netif_action_connected(esp_netif, NULL, 0, NULL);
+
+    usb_osal_thread_create("usbh_cdc_ecm_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_cdc_ecm_rx_thread, NULL);
+}
+
+void usbh_cdc_ecm_stop(struct usbh_cdc_ecm *cdc_ecm_class)
+{
+    (void)cdc_ecm_class;
+
+    usbh_net_netif_glue_deinit_common(&g_cdc_ecm_netif_glue);
+    esp_netif_action_stop(g_cdc_ecm_netif_glue.base.netif, NULL, 0, NULL);
+    esp_netif_destroy(g_cdc_ecm_netif_glue.base.netif);
+}
+#endif
+
+#ifdef CONFIG_USBHOST_PLATFORM_CDC_RNDIS
+#include "usbh_rndis.h"
+
+struct usb_osal_timer *timer_handle;
+
+static void rndis_dev_keepalive_timeout(void *arg)
+{
+    struct usbh_rndis *rndis_class = (struct usbh_rndis *)arg;
+    usbh_rndis_keepalive(rndis_class);
+}
+
+void timer_init(struct usbh_rndis *rndis_class)
+{
+    timer_handle = usb_osal_timer_create("rndis_keepalive", 5000, rndis_dev_keepalive_timeout, rndis_class, true);
+    if (NULL != timer_handle) {
+        usb_osal_timer_start(timer_handle);
+    } else {
+        USB_LOG_ERR("timer creation failed! \r\n");
+        for (;;) {
+            ;
+        }
+    }
+}
+
+struct usbh_net_netif_glue g_rndis_netif_glue;
+
+static esp_err_t usbh_rndis_transmit(void *h, void *buffer, size_t len)
+{
+    int ret;
+    (void)h;
+
+    usb_memcpy(usbh_rndis_get_eth_txbuf(), buffer, len);
+    ret = usbh_rndis_eth_output(len);
+    if (ret < 0) {
+        return ESP_FAIL;
+    }
+
+    return ESP_OK;
+}
+
+void usbh_rndis_eth_input(uint8_t *buf, uint32_t buflen)
+{
+    usbh_net_input_common(&g_rndis_netif_glue, buf, buflen);
+}
+
+void usbh_rndis_run(struct usbh_rndis *rndis_class)
+{
+    memset(&g_rndis_netif_glue, 0, sizeof(struct usbh_net_netif_glue));
+
+    esp_netif_inherent_config_t base_cfg = ESP_NETIF_INHERENT_DEFAULT_ETH();
+    base_cfg.if_key = "u2";
+    base_cfg.if_desc = "usbh rndis";
+
+    esp_netif_config_t netif_cfg = ESP_NETIF_DEFAULT_ETH();
+    netif_cfg.base = &base_cfg;
+    esp_netif_t *esp_netif = esp_netif_new(&netif_cfg);
+
+    usbh_net_netif_glue_init_common(&g_rndis_netif_glue, rndis_class, usbh_rndis_transmit);
+    esp_netif_attach(esp_netif, &g_rndis_netif_glue.base);
+
+    esp_netif_set_mac(esp_netif, rndis_class->mac);
+
+    esp_netif_action_start(esp_netif, NULL, 0, NULL);
+    esp_netif_action_connected(esp_netif, NULL, 0, NULL);
+
+    usb_osal_thread_create("usbh_rndis_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_rndis_rx_thread, NULL);
+
+    //timer_init(rndis_class);
+}
+
+void usbh_rndis_stop(struct usbh_rndis *rndis_class)
+{
+    (void)rndis_class;
+
+    usbh_net_netif_glue_deinit_common(&g_rndis_netif_glue);
+    esp_netif_action_stop(g_rndis_netif_glue.base.netif, NULL, 0, NULL);
+    esp_netif_destroy(g_rndis_netif_glue.base.netif);
+
+    // xTimerStop(timer_handle, 0);
+    // xTimerDelete(timer_handle, 0);
+}
+#endif
+
+#ifdef CONFIG_USBHOST_PLATFORM_CDC_NCM
+#include "usbh_cdc_ncm.h"
+
+struct usbh_net_netif_glue g_cdc_ncm_netif_glue;
+
+static esp_err_t usbh_cdc_ncm_transmit(void *h, void *buffer, size_t len)
+{
+    int ret;
+    (void)h;
+
+    usb_memcpy(usbh_cdc_ncm_get_eth_txbuf(), buffer, len);
+    ret = usbh_cdc_ncm_eth_output(len);
+    if (ret < 0) {
+        return ESP_FAIL;
+    }
+
+    return ESP_OK;
+}
+
+void usbh_cdc_ncm_eth_input(uint8_t *buf, uint32_t buflen)
+{
+    usbh_net_input_common(&g_cdc_ncm_netif_glue, buf, buflen);
+}
+
+void usbh_cdc_ncm_run(struct usbh_cdc_ncm *cdc_ncm_class)
+{
+    memset(&g_cdc_ncm_netif_glue, 0, sizeof(struct usbh_net_netif_glue));
+
+    esp_netif_inherent_config_t base_cfg = ESP_NETIF_INHERENT_DEFAULT_ETH();
+    base_cfg.if_key = "u1";
+    base_cfg.if_desc = "usbh cdc ncm";
+
+    esp_netif_config_t netif_cfg = ESP_NETIF_DEFAULT_ETH();
+    netif_cfg.base = &base_cfg;
+    esp_netif_t *esp_netif = esp_netif_new(&netif_cfg);
+
+    usbh_net_netif_glue_init_common(&g_cdc_ncm_netif_glue, cdc_ncm_class, usbh_cdc_ncm_transmit);
+    esp_netif_attach(esp_netif, &g_cdc_ncm_netif_glue.base);
+
+    esp_netif_set_mac(esp_netif, cdc_ncm_class->mac);
+
+    esp_netif_action_start(esp_netif, NULL, 0, NULL);
+    esp_netif_action_connected(esp_netif, NULL, 0, NULL);
+
+    usb_osal_thread_create("usbh_cdc_ncm_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_cdc_ncm_rx_thread, NULL);
+}
+
+void usbh_cdc_ncm_stop(struct usbh_cdc_ncm *cdc_ncm_class)
+{
+    (void)cdc_ncm_class;
+
+    usbh_net_netif_glue_deinit_common(&g_cdc_ncm_netif_glue);
+    esp_netif_action_stop(g_cdc_ncm_netif_glue.base.netif, NULL, 0, NULL);
+    esp_netif_destroy(g_cdc_ncm_netif_glue.base.netif);
+}
+#endif
+
+#ifdef CONFIG_USBHOST_PLATFORM_ASIX
+#include "usbh_asix.h"
+
+struct usbh_net_netif_glue g_asix_netif_glue;
+
+static esp_err_t usbh_asix_transmit(void *h, void *buffer, size_t len)
+{
+    int ret;
+    (void)h;
+
+    usb_memcpy(usbh_asix_get_eth_txbuf(), buffer, len);
+    ret = usbh_asix_eth_output(len);
+    if (ret < 0) {
+        return ESP_FAIL;
+    }
+
+    return ESP_OK;
+}
+
+void usbh_asix_eth_input(uint8_t *buf, uint32_t buflen)
+{
+    usbh_net_input_common(&g_asix_netif_glue, buf, buflen);
+}
+
+void usbh_asix_run(struct usbh_asix *asix_class)
+{
+    memset(&g_asix_netif_glue, 0, sizeof(struct usbh_net_netif_glue));
+
+    esp_netif_inherent_config_t base_cfg = ESP_NETIF_INHERENT_DEFAULT_ETH();
+    base_cfg.if_key = "u3";
+    base_cfg.if_desc = "usbh asix";
+
+    esp_netif_config_t netif_cfg = ESP_NETIF_DEFAULT_ETH();
+    netif_cfg.base = &base_cfg;
+    esp_netif_t *esp_netif = esp_netif_new(&netif_cfg);
+
+    usbh_net_netif_glue_init_common(&g_asix_netif_glue, asix_class, usbh_asix_transmit);
+    esp_netif_attach(esp_netif, &g_asix_netif_glue.base);
+
+    esp_netif_set_mac(esp_netif, asix_class->mac);
+
+    esp_netif_action_start(esp_netif, NULL, 0, NULL);
+    esp_netif_action_connected(esp_netif, NULL, 0, NULL);
+
+    usb_osal_thread_create("usbh_asix_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_asix_rx_thread, NULL);
+}
+
+void usbh_asix_stop(struct usbh_asix *asix_class)
+{
+    (void)asix_class;
+
+    usbh_net_netif_glue_deinit_common(&g_asix_netif_glue);
+    esp_netif_action_stop(g_asix_netif_glue.base.netif, NULL, 0, NULL);
+    esp_netif_destroy(g_asix_netif_glue.base.netif);
+}
+#endif
+
+#ifdef CONFIG_USBHOST_PLATFORM_RTL8152
+#include "usbh_rtl8152.h"
+
+struct usbh_net_netif_glue g_rtl8152_netif_glue;
+
+static esp_err_t usbh_rtl8152_transmit(void *h, void *buffer, size_t len)
+{
+    int ret;
+    (void)h;
+
+    usb_memcpy(usbh_rtl8152_get_eth_txbuf(), buffer, len);
+    ret = usbh_rtl8152_eth_output(len);
+    if (ret < 0) {
+        return ESP_FAIL;
+    }
+
+    return ESP_OK;
+}
+
+void usbh_rtl8152_eth_input(uint8_t *buf, uint32_t buflen)
+{
+    usbh_net_input_common(&g_rtl8152_netif_glue, buf, buflen);
+}
+
+void usbh_rtl8152_run(struct usbh_rtl8152 *rtl8152_class)
+{
+    memset(&g_rtl8152_netif_glue, 0, sizeof(struct usbh_net_netif_glue));
+
+    esp_netif_inherent_config_t base_cfg = ESP_NETIF_INHERENT_DEFAULT_ETH();
+    base_cfg.if_key = "u4";
+    base_cfg.if_desc = "usbh rtl8152";
+
+    esp_netif_config_t netif_cfg = ESP_NETIF_DEFAULT_ETH();
+    netif_cfg.base = &base_cfg;
+    esp_netif_t *esp_netif = esp_netif_new(&netif_cfg);
+
+    usbh_net_netif_glue_init_common(&g_rtl8152_netif_glue, rtl8152_class, usbh_rtl8152_transmit);
+    esp_netif_attach(esp_netif, &g_rtl8152_netif_glue.base);
+
+    esp_netif_set_mac(esp_netif, rtl8152_class->mac);
+
+    esp_netif_action_start(esp_netif, NULL, 0, NULL);
+    esp_netif_action_connected(esp_netif, NULL, 0, NULL);
+
+    usb_osal_thread_create("usbh_rtl8152_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_rtl8152_rx_thread, NULL);
+}
+
+void usbh_rtl8152_stop(struct usbh_rtl8152 *rtl8152_class)
+{
+    (void)rtl8152_class;
+
+    usbh_net_netif_glue_deinit_common(&g_rtl8152_netif_glue);
+    esp_netif_action_stop(g_rtl8152_netif_glue.base.netif, NULL, 0, NULL);
+    esp_netif_destroy(g_rtl8152_netif_glue.base.netif);
+}
+#endif

platform/rtthread/usb_check.c

@@ -1,4 +1,5 @@
 #include "rtthread.h"
+#include "usb_config.h"
 
 #if defined(PKG_CHERRYUSB_HOST) || defined(RT_CHERRYUSB_HOST)
 
@@ -11,3 +12,20 @@
 #endif
 
 #endif
+
+#if defined(ARCH_ARM_CORTEX_M7) ||                                          \
+    defined(SOC_HPM6000) || defined(SOC_HPM6E00) || defined(SOC_HPM6P00) || \
+    defined(BSP_USING_BL61X) || defined(BSP_USING_BL808)
+#ifndef RT_USING_CACHE
+#error RT_USING_CACHE must be enabled in this chip
+#endif
+#endif
+
+#ifdef RT_USING_CACHE
+#ifndef CONFIG_USB_DCACHE_ENABLE
+#error CONFIG_USB_DCACHE_ENABLE must be enabled
+#endif
+#if RT_ALIGN_SIZE != 32 && RT_ALIGN_SIZE != 64
+#error RT_ALIGN_SIZE must be cacheline to 32 or 64
+#endif
+#endif

platform/rtthread/usbh_dfs.c

@@ -19,22 +19,6 @@
 #define CONFIG_USB_DFS_MOUNT_POINT "/"
 #endif
 
-#if defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7RS) ||\
-    defined(SOC_HPM5000) || defined(SOC_HPM6000) || defined(SOC_HPM6E00) || defined(BSP_USING_BL61X)
-#ifndef RT_USING_CACHE
-#error usbh msc must enable RT_USING_CACHE in this chip
-#endif
-#if RT_ALIGN_SIZE != 32 && RT_ALIGN_SIZE != 64
-#error usbh msc must set cache line to 32 or 64
-#endif
-#endif
-
-#ifdef RT_USING_CACHE
-#ifndef CONFIG_USB_DCACHE_ENABLE
-#error CONFIG_USB_DCACHE_ENABLE must be enabled to use msc disk
-#endif
-#endif
-
 static rt_err_t rt_udisk_init(rt_device_t dev)
 {
     struct usbh_msc *msc_class = (struct usbh_msc *)dev->user_data;

port/bouffalolab/usb_dc_bl.c

@@ -478,6 +478,11 @@ int usb_dc_init(uint8_t busid)
 
     regval = getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET);
     regval |= USB_SFRST_HOV;
+#ifdef CONFIG_USB_HS
+    regval &= ~USB_FORCE_FS;
+#else
+    regval |= USB_FORCE_FS;
+#endif
     putreg32(regval, BFLB_USB_BASE + USB_DEV_CTL_OFFSET);
 
     while (getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET) & USB_SFRST_HOV) {

port/ch32/README.md

@@ -2,4 +2,15 @@
 
 ## Support Chip List
 
-- CH32V30x
+## CH32FS
+
+- CH32V30X/CH32V20X/CH32V10X/CH32X035
+
+## CH32HS
+
+- CH32V30X
+
+## CH58X
+
+- CH57X/CH58X(usbfs)
+- CH585(usbhs)

port/ch32/ch32fs/usb_dc_usbfs.c

@@ -404,8 +404,8 @@ void USBD_IRQHandler(uint8_t busid)
     }
 }
 
-void OTG_FS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
-void OTG_FS_IRQHandler(void)
+void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+void USBFS_IRQHandler(void)
 {
     extern void USBD_IRQHandler(uint8_t busid);
     USBD_IRQHandler(0);

port/ch32/ch58x/usb_ch585_usbhs_dc.c

@@ -1,5 +1,5 @@
 #include "usbd_core.h"
-#include "ch585_usbhs_reg.h"
+#include "usb_ch585_usbhs_reg.h"
 
 /**
  * @brief   Related register macro
@@ -507,7 +507,7 @@ void USBD_IRQHandler(uint8_t busid)
         R8_U2EP0_RX_CTRL = USBHS_UEP_R_RES_ACK;
         CH585_USBHS_DEV->INT_FG = USBHS_UDIF_BUS_RST;
     } else if (intflag & USBHS_UDIF_SUSPEND) {
-        if (CH585_USBHS_DEV->MIS_ST & 0x04) {
+        if (CH585_USBHS_DEV->MIS_ST & USBHS_UDMS_SUSPEND) {
             /* Suspend */
         } else {
             /* Wake up */

port/ch32/ch58x/usb_ch585_usbhs_reg.h

@@ -1,3 +1,8 @@
+/*
+ * Copyright (c) 2024, sakumisu
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #pragma once
 
 /**********************************/

port/dwc2/usb_glue_esp.c

@@ -41,7 +41,11 @@ void usb_dc_low_level_init(uint8_t busid)
     usb_phy_config_t phy_config = {
         .controller = USB_PHY_CTRL_OTG,
         .otg_mode = USB_OTG_MODE_DEVICE,
+#if CONFIG_IDF_TARGET_ESP32P4 // ESP32-P4 has 2 USB-DWC peripherals, each with its dedicated PHY. We support HS+UTMI only ATM.
+        .target = USB_PHY_TARGET_UTMI,
+#else
         .target = USB_PHY_TARGET_INT,
+#endif
     };
 
     esp_err_t ret = usb_new_phy(&phy_config, &s_phy_handle);
@@ -87,7 +91,11 @@ void usb_hc_low_level_init(struct usbh_bus *bus)
     // Host Library defaults to internal PHY
     usb_phy_config_t phy_config = {
         .controller = USB_PHY_CTRL_OTG,
+#if CONFIG_IDF_TARGET_ESP32P4 // ESP32-P4 has 2 USB-DWC peripherals, each with its dedicated PHY. We support HS+UTMI only ATM.
+        .target = USB_PHY_TARGET_UTMI,
+#else
         .target = USB_PHY_TARGET_INT,
+#endif
         .otg_mode = USB_OTG_MODE_HOST,
         .otg_speed = USB_PHY_SPEED_UNDEFINED, // In Host mode, the speed is determined by the connected device
         .ext_io_conf = NULL,
@@ -136,16 +144,25 @@ void usbd_dwc2_delay_ms(uint8_t ms)
 
 void usb_dcache_clean(uintptr_t addr, size_t size)
 {
+    if (size == 0)
+        return;
+
     esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M);
 }
 
 void usb_dcache_invalidate(uintptr_t addr, size_t size)
 {
+    if (size == 0)
+        return;
+
     esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_M2C);
 }
 
 void usb_dcache_flush(uintptr_t addr, size_t size)
 {
+    if (size == 0)
+        return;
+
     esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_DIR_M2C);
 }
 #endif

port/dwc2/usb_glue_st.c

@@ -178,7 +178,7 @@ uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base)
     usb_hsphy_init(25000000U);
     return (1 << 23); /* Enable USB HS PHY USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN;*/
 #elif __has_include("stm32h7rsxx.h")
-    return (1 << 21);
+    return ((1 << 23) | (1 << 24));
 #else
     return 0;
 #endif
@@ -205,6 +205,8 @@ uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base)
     USB_OTG_GLB->GCCFG = (1 << 23);
     usb_hsphy_init(25000000U);
     return (1 << 23); /* Enable USB HS PHY USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN;*/
+#elif __has_include("stm32h7rsxx.h")
+    return (1 << 25);
 #else
     return 0;
 #endif

port/dwc2/usb_hc_dwc2.c

@@ -273,8 +273,6 @@ static inline void dwc2_chan_splt_init(struct usbh_bus *bus, uint8_t ch_num)
 
 static void dwc2_chan_init(struct usbh_bus *bus, uint8_t ch_num, uint8_t devaddr, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps, uint8_t speed)
 {
-    uint32_t regval;
-
     /* Clear old interrupt conditions for this host channel. */
     USB_OTG_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;
 
@@ -326,16 +324,11 @@ static inline void dwc2_chan_transfer(struct usbh_bus *bus, uint8_t ch_num, uint
 static void dwc2_halt(struct usbh_bus *bus, uint8_t ch_num)
 {
     volatile uint32_t ChannelEna = (USB_OTG_HC(ch_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;
-    volatile uint32_t HcEpType = (USB_OTG_HC(ch_num)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
-    volatile uint32_t SplitEna = (USB_OTG_HC(ch_num)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31;
     volatile uint32_t count = 0U;
     volatile uint32_t value;
 
-    /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels.
-     At the end of the next uframe/frame (in the worst case), the core generates a channel halted
-     and disables the channel automatically. */
-    if ((((USB_OTG_GLB->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) &&
-        ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR))))) {
+    if (((USB_OTG_GLB->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) &&
+        (ChannelEna == 0U)) {
         return;
     }
 
@@ -1304,7 +1297,7 @@ static void dwc2_outchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num)
 
 static void dwc2_port_irq_handler(struct usbh_bus *bus)
 {
-    __IO uint32_t hprt0, hprt0_dup, regval;
+    __IO uint32_t hprt0, hprt0_dup;
 
     /* Handle Host Port Interrupts */
     hprt0 = USB_OTG_HPRT;
@@ -1334,7 +1327,7 @@ static void dwc2_port_irq_handler(struct usbh_bus *bus)
             if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) {
                 USB_OTG_HOST->HFIR = 6000U;
                 if ((USB_OTG_HOST->HCFG & USB_OTG_HCFG_FSLSPCS) != USB_OTG_HCFG_FSLSPCS_1) {
-                    regval = USB_OTG_HOST->HCFG;
+                    uint32_t regval = USB_OTG_HOST->HCFG;
                     regval &= ~USB_OTG_HCFG_FSLSPCS;
                     regval |= USB_OTG_HCFG_FSLSPCS_1;
                     USB_OTG_HOST->HCFG = regval;
@@ -1342,7 +1335,7 @@ static void dwc2_port_irq_handler(struct usbh_bus *bus)
             } else {
                 USB_OTG_HOST->HFIR = 48000U;
                 if ((USB_OTG_HOST->HCFG & USB_OTG_HCFG_FSLSPCS) != USB_OTG_HCFG_FSLSPCS_0) {
-                    regval = USB_OTG_HOST->HCFG;
+                    uint32_t regval = USB_OTG_HOST->HCFG;
                     regval &= ~USB_OTG_HCFG_FSLSPCS;
                     regval |= USB_OTG_HCFG_FSLSPCS_0;
                     USB_OTG_HOST->HCFG = regval;