check intf num when arg is valid

- fix descriptor endpoint attribute error and add audiov2 feedback descriptor

Signed-off-by: Zhihong Chen <zhihong.chen@hpmicro.com>

README.md

@@ -2,19 +2,37 @@
 
 [中文版](./README_zh.md)
 
-CherryUSB is a tiny, beautiful and portable USB host and device stack for embedded system with USB ip.
+CherryUSB is a tiny, beautiful and portable USB host and device stack for embedded system with USB IP.
 
 ![CherryUSB](./docs/assets/usb_outline.png)
 
 ## Why choose
 
-- Streamlined code with small memory usage which also can be further trimmed
-- Comprehensive class drivers and all master and slave class drivers are templated,making it easy for users to add new class drivers and find patterns when learning
-- The APIs available to the users are very few and clearly categorised. Device: initialisation + registration apis, command callback apis, data sending and receiving apis; Host: initialisation + lookup apis, data sending and receiving apis
-- Tree-based programming with a hierarchy of code that makes it easy for the user to sort out function call relationships, enumerations and class-driven loading processes
-- Standardised porting interface, no need to rewrite the driver for the same ip, and porting drivers are templated to make it easier for users to add new ports
-- The use of the device or host transceiver apis are equivalent to the use of the uart tx/rx dma, and there is no limit to the length
-- Capable of achieving theoretical USB hardware bandwidth
+### Easy to study USB
+
+In order to make it easier for users to learn USB basics, enumeration, driver loading and IP drivers, the code has been written with the following advantages:
+
+- Lean code, simple logic, no complex C syntax
+- Tree-based programming with cascading code
+- Class-drivers and porting-drivers are templating and simplification
+- Clear API classification (slave: initialisation, registration api, command callback api, data sending and receiving api; host: initialisation, lookup api, data sending and receiving api)
+
+### Easy to use  USB
+
+In order to facilitate the use of the USB interface and to take into account the fact that users have learned about uart and dma, the following advantages have been designed for the data sending and receiving class of interface:
+
+- Equivalent to using uart tx dma/uart rx dma
+- There is no limit to the length of send and receive, the user does not need to care about the USB packetization process (the porting driver does the packetization process)
+
+### Easy to bring out USB performance
+
+Taking into account USB performance issues and trying to achieve the theoretical bandwidth of the USB hardware, the design of the data transceiver class interface has the following advantages:
+
+- Porting drivers directly to registers, no abstraction layer encapsulation
+- Memory zero copy
+- If IP has DMA then uses DMA mode (DMA with hardware packetization)
+- Unlimited length make it easier to interface with hardware DMA and take advantage of DMA
+- Subcontracting function is handled in interrupt
 
 ## Directoy Structure
 
@@ -36,13 +54,12 @@ CherryUSB is a tiny, beautiful and portable USB host and device stack for embedd
 |:-------------:|:---------------------------:|
 |class          |  usb class driver           |
 |common         |  usb spec macros and utils  |
-|core           |  usb core implementation  |
-|demo           |  different chips demo     |
-|osal           |  os wrapper              |
-|docs           |  doc for guiding         |
-|packet capture |  packet capture file     |
-|port           |  usb dcd and hcd porting |
-|tools           |  tool used url          |
+|core           |  usb core implementation    |
+|demo           |  different chips demo       |
+|osal           |  os wrapper                 |
+|docs           |  doc for guiding            |
+|port           |  usb dcd and hcd porting    |
+|tools          |  tool url                   |
 
 ## Device Stack Overview
 
@@ -50,7 +67,7 @@ CherryUSB Device Stack provides a unified framework of functions for standard de
 
 CherryUSB Device Stack has the following functions：
 
-- Support USB2.0 full and high speed
+- Support USB2.0 full and high speed, USB3.0 super speed
 - Support endpoint irq callback register by users, let users do whatever they wants in endpoint irq callback.
 - Support Composite Device
 - Support Communication Device Class (CDC)
@@ -100,7 +117,7 @@ CherryUSB Host Stack resource usage (GCC 10.2 with -O2):
 |   file        |  FLASH (Byte)  |  No Cache RAM (Byte)            |  RAM (Byte)                 |  Heap (Byte)                    |
 |:-------------:|:--------------:|:-------------------------------:|:---------------------------:|:-------------------------------:|
 |usbh_core.c    |  4417          | 512                             | 28                          | sizeof(struct usbh_urb)         |
-|usbh_hub.c     |  4895          | 32 + 1* (1+n) | 16 + sizeof(struct usbh_hub) * (1+n)          | 0                               |
+|usbh_hub.c     |  4895          | 32 + 4* (1+n) | 16 + sizeof(struct usbh_hub) * (1+n)          | 0                               |
 |usbh_cdc_acm.c |  1064          | 7                               | 4                           | sizeof(struct usbh_cdc_acm) * x |
 |usbh_msc.c     |  1776          | 32                              | 4                           | sizeof(struct usbh_msc) * x     |
 |usbh_hid.c     |  922           | 128                             | 4                           | sizeof(struct usbh_hid) * x     |
@@ -131,25 +148,23 @@ USB basic concepts and how the CherryUSB Device stack is implemented, see [Cherr
 
 ## Demo Repo
 
-Note: After version 0.4.1, the dcd drivers have been refactored and some repositories are not maintained for a long time, so if you use a higher version, you need to update it yourself.
-
 |   Manufacturer       |  CHIP or Series    | USB IP| Repo Url |Corresponds to master version|
 |:--------------------:|:------------------:|:-----:|:--------:|:---------------------------:|
-|Bouffalolab    |  BL702/BL616/BL808 | bouffalolab/ehci|[bl_mcu_sdk](https://github.com/CherryUSB/cherryusb_bouffalolab)| latest |
-|ST    |  STM32F103C8T6 | fsdev |[stm32f103_repo](https://github.com/sakumisu/CherryUSB/tree/master/demo/stm32/usb_device/stm32f103c8t6)|latest |
-|ST    |  STM32F4 | dwc2 |[stm32f429_device_repo](https://github.com/sakumisu/CherryUSB/tree/master/demo/stm32/usb_device/stm32f429igt6)   [stm32f429_host_repo](https://github.com/sakumisu/CherryUSB/tree/master/demo/stm32/usb_host/stm32f429igt6)|latest |
-|ST    |  STM32H7 | dwc2 |[stm32h743_device_repo](https://github.com/sakumisu/CherryUSB/tree/master/demo/stm32/usb_device/stm32h743vbt6)   [stm32h743_host_repo](https://github.com/sakumisu/CherryUSB/tree/master/demo/stm32/usb_host/stm32h743xih6)|latest |
-|HPMicro    |  HPM6750 | hpm/ehci |[hpm_repo](https://github.com/CherryUSB/cherryusb_hpmicro)|v0.6.0 |
-|Essemi    |  ES32F36xx | musb |[es32f369_repo](https://github.com/sakumisu/CherryUSB/tree/master/demo/es32)|latest |
-|AllwinnerTech    |  F1C100S | musb |[cherryusb_rtt_f1c100s](https://github.com/CherryUSB/cherryusb_rtt_f1c100s)|latest |
-|Phytium |  e2000 | xhci |[phytium _repo](https://gitee.com/phytium_embedded/phytium-standalone-sdk)|latest |
-|Raspberry pi |  rp2040 | rp2040 |[rp2040_repo](https://github.com/sakumisu/CherryUSB/tree/master/demo/rp2040)|latest |
+|Bouffalolab    |  BL702/BL616/BL808 | bouffalolab/ehci|[bouffalo_sdk](https://github.com/CherryUSB/cherryusb_bouffalolab)| latest |
+|ST    |  STM32F1x | fsdev |[stm32_repo](https://github.com/CherryUSB/cherryusb_stm32)|latest |
+|ST    |  STM32F4/STM32H7 | dwc2 |[stm32_repo](https://github.com/CherryUSB/cherryusb_stm32)|latest |
+|HPMicro    |  HPM6750 | hpm/ehci |[hpm_sdk](https://github.com/CherryUSB/cherryusb_hpmicro)|v0.7.0 |
+|Essemi    |  ES32F36xx | musb |[es32f369_repo](https://github.com/CherryUSB/cherryusb_es32)|latest |
+|AllwinnerTech    |  F1C100S/F1C200S | musb |[cherryusb_rtt_f1c100s](https://github.com/CherryUSB/cherryusb_rtt_f1c100s)|latest |
+|Phytium |  e2000 | xhci |[phytium_repo](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk)|latest |
+|Raspberry pi |  rp2040 | rp2040 |[pico-examples](https://github.com/CherryUSB/pico-examples)|latest |
 |WCH    |  CH32V307/ch58x | ch32_usbfs/ch32_usbhs/ch58x |[wch_repo](https://github.com/CherryUSB/cherryusb_wch)|latest |
 |Nordicsemi |  Nrf52840 | nrf5x |[nrf5x_repo](https://github.com/CherryUSB/cherryusb_nrf5x)|latest |
+|Espressif    |  esp32s3 | dwc2 |[esp32_repo](https://github.com/CherryUSB/cherryusb_esp32)|latest |
+|Bekencorp    |  BK72xx | musb |[armino](https://github.com/CherryUSB/armino)|v0.7.0 |
+|Sophgo    |  cv18xx | dwc2 |[cvi_alios_open](https://github.com/CherryUSB/cvi_alios_open)|v0.7.0 |
 |Nuvoton    |  Nuc442 | nuvoton |[nuc442_repo](https://github.com/CherryUSB/cherryusb_nuc442)|v0.4.1 |
 |Geehy    |  APM32E10x APM32F0xx| fsdev |[apm32_repo](https://github.com/CherryUSB/cherryusb_apm32)|v0.4.1 |
-|Espressif    |  esp32 | dwc2 |[esp32_repo](https://github.com/CherryUSB/cherryusb_esp32)|v0.4.1 |
-|Mindmotion    |  MM32L3xx | mm32 |[mm32_repo](https://github.com/CherryUSB/cherryusb_mm32)|v0.4.1 |
 
 ## Contact
 

README_zh.md

@@ -2,19 +2,37 @@
 
 [English](./README.md)
 
-CherryUSB 是一个小而美的、可移植性高的、用于嵌入式系统(带 USB ip)的 USB 主从协议栈。
+CherryUSB 是一个小而美的、可移植性高的、用于嵌入式系统(带 USB IP)的 USB 主从协议栈。
 
 ![CherryUSB](./docs/assets/usb_outline.png)
 
 ## 为什么选择
 
-- 代码精简，并且内存占用极小，详细参考下面表格，而且还可进一步的裁剪
-- 全面的 class 驱动，并且主从 class 驱动全部模板化，方便用户增加新的 class 驱动以及学习的时候查找规律
-- 可供用户使用的 API 非常少，并且分类清晰。从机：初始化 + 注册类、命令回调类、数据收发类；主机：初始化 + 查找类、数据收发类
-- 树状化编程，代码层层递进，方便用户理清函数调用关系、枚举和 class 驱动加载过程
-- 标准化的 porting 接口，相同 ip 无需重写驱动，并且 porting 驱动也进行了模板化，方便用户新增 porting。
-- 主从收发接口的使用等价于 uart tx/rx dma 的使用，长度也没有限制
-- 能够达到 USB 硬件理论带宽
+### 易于学习 USB
+
+为了方便用户学习 USB 基本知识、枚举、驱动加载、IP 驱动，因此，编写的代码具备以下优点：
+
+- 代码精简，逻辑简单，无复杂 C 语言语法
+- 树状化编程，代码层层递进
+- Class 驱动和 porting 驱动模板化、精简化
+- API 分类清晰（从机：初始化、注册类、命令回调类、数据收发类；主机：初始化、查找类、数据收发类）
+
+### 易于使用 USB
+
+为了方便用户使用 USB 接口，考虑到用户学习过 uart 和 dma，因此，设计的数据收发类接口具备以下优点：
+
+- 等价于使用 uart tx dma/uart rx dma
+- 收发长度没有限制，用户不需要关心 USB 分包过程（porting 驱动做分包过程）
+
+### 易于发挥 USB 性能
+
+考虑到 USB 性能问题，尽量达到 USB 硬件理论带宽，因此，设计的数据收发类接口具备以下优点：
+
+- Porting 驱动直接对接寄存器，无抽象层封装
+- Memory zero copy
+- IP 如果带 DMA 则使用 DMA 模式（DMA 带硬件分包功能）
+- 长度无限制，方便对接硬件 DMA 并且发挥 DMA 的优势
+- 分包功能在中断中处理
 
 ## 目录结构
 
@@ -26,22 +44,20 @@ CherryUSB 是一个小而美的、可移植性高的、用于嵌入式系统(带
 ├── demo
 ├── docs
 ├── osal
-├── packet capture
 └── port
 └── tools
 ```
 
 |   目录名       |  描述                          |
-|:-------------:|:------------------------------:|
+|:-------------:|:-------------------------------:|
 |class          |  usb class 类主从驱动           |
 |common         |  usb spec 定义、常用宏、标准接口定义 |
-|core           |  usb 主从协议栈核心实现            |
-|demo           |  示例                          |
-|docs           |  文档                          |
+|core           |  usb 主从协议栈核心实现          |
+|demo           |  示例                            |
+|docs           |  文档                            |
 |osal           |  os 封装层                       |
-|packet capture |  抓包文件（需要使用力科软件打开）|
 |port           |  usb 主从需要实现的 porting 接口 |
-|tools           |  工具链接                       |
+|tools          |  工具链接                        |
 
 ## Device 协议栈简介
 
@@ -49,7 +65,7 @@ CherryUSB Device 协议栈对标准设备请求、CLASS 请求、VENDOR 请求
 
 CherryUSB Device 协议栈当前实现以下功能：
 
-- 支持 USB2.0 全速和高速设备
+- 支持 USB2.0 全速和高速设备，USB3.0 超速设备
 - 支持端点中断注册功能，porting 给用户自己处理中断里的数据
 - 支持复合设备
 - 支持 Communication Device Class (CDC)
@@ -99,7 +115,7 @@ CherryUSB Host 协议栈资源占用说明（GCC 10.2 with -O2）：
 |   file        |  FLASH (Byte)  |  No Cache RAM (Byte)            |  RAM (Byte)                 |  Heap (Byte)                    |
 |:-------------:|:--------------:|:-------------------------------:|:---------------------------:|:-------------------------------:|
 |usbh_core.c    |  4417          | 512                             | 28                          | sizeof(struct usbh_urb)         |
-|usbh_hub.c     |  4895          | 32 + 1* (1+n) | 16 + sizeof(struct usbh_hub) * (1+n)          | 0                               |
+|usbh_hub.c     |  4895          | 32 + 4* (1+n) | 16 + sizeof(struct usbh_hub) * (1+n)          | 0                               |
 |usbh_cdc_acm.c |  1064          | 7                               | 4                           | sizeof(struct usbh_cdc_acm) * x |
 |usbh_msc.c     |  1776          | 32                              | 4                           | sizeof(struct usbh_msc) * x     |
 |usbh_hid.c     |  922           | 128                             | 4                           | sizeof(struct usbh_hid) * x     |
@@ -130,25 +146,23 @@ USB 基本知识点与 CherryUSB Device 协议栈是如何编写的，参考 [Ch
 
 ## 示例仓库
 
-注意：0.4.1 版本以后 dcd 驱动进行了重构，部分仓库不做长期维护，所以如果使用高版本需要自行更新
-
 |   厂商               |  芯片或者系列      | USB IP| 仓库链接 |      对应 master 版本        |
 |:--------------------:|:------------------:|:-----:|:--------:|:---------------------------:|
-|Bouffalolab    |  BL702/BL616/BL808 | bouffalolab/ehci|[bl_mcu_sdk](https://github.com/CherryUSB/cherryusb_bouffalolab)| latest |
-|ST    |  STM32F103C8T6 | fsdev |[stm32f103_repo](https://github.com/sakumisu/CherryUSB/tree/master/demo/stm32/usb_device/stm32f103c8t6)|latest |
-|ST    |  STM32F4 | dwc2 |[stm32f429_device_repo](https://github.com/sakumisu/CherryUSB/tree/master/demo/stm32/usb_device/stm32f429igt6)   [stm32f429_host_repo](https://github.com/sakumisu/CherryUSB/tree/master/demo/stm32/usb_host/stm32f429igt6)|latest |
-|ST    |  STM32H7 | dwc2 |[stm32h743_device_repo](https://github.com/sakumisu/CherryUSB/tree/master/demo/stm32/usb_device/stm32h743vbt6)   [stm32h743_host_repo](https://github.com/sakumisu/CherryUSB/tree/master/demo/stm32/usb_host/stm32h743xih6)|latest |
-|HPMicro    |  HPM6750 | hpm/ehci |[hpm_repo](https://github.com/CherryUSB/cherryusb_hpmicro)|v0.6.0 |
-|Essemi    |  ES32F36xx | musb |[es32f369_repo](https://github.com/sakumisu/CherryUSB/tree/master/demo/es32)|latest |
-|AllwinnerTech    |  F1C100S | musb |[cherryusb_rtt_f1c100s](https://github.com/CherryUSB/cherryusb_rtt_f1c100s)|latest |
-|Phytium |  e2000 | xhci |[phytium _repo](https://gitee.com/phytium_embedded/phytium-standalone-sdk)|latest |
-|Raspberry pi |  rp2040 | rp2040 |[rp2040_repo](https://github.com/sakumisu/CherryUSB/tree/master/demo/rp2040)|latest |
+|Bouffalolab    |  BL702/BL616/BL808 | bouffalolab/ehci|[bouffalo_sdk](https://github.com/CherryUSB/cherryusb_bouffalolab)| latest |
+|ST    |  STM32F1x | fsdev |[stm32_repo](https://github.com/CherryUSB/cherryusb_stm32)|latest |
+|ST    |  STM32F4/STM32H7 | dwc2 |[stm32_repo](https://github.com/CherryUSB/cherryusb_stm32)|latest |
+|HPMicro    |  HPM6750 | hpm/ehci |[hpm_sdk](https://github.com/CherryUSB/cherryusb_hpmicro)|v0.7.0 |
+|Essemi    |  ES32F36xx | musb |[es32f369_repo](https://github.com/CherryUSB/cherryusb_es32)|latest |
+|AllwinnerTech    |  F1C100S/F1C200S | musb |[cherryusb_rtt_f1c100s](https://github.com/CherryUSB/cherryusb_rtt_f1c100s)|latest |
+|Phytium |  e2000 | xhci |[phytium_repo](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk)|latest |
+|Raspberry pi |  rp2040 | rp2040 |[pico-examples](https://github.com/CherryUSB/pico-examples)|latest |
 |WCH    |  CH32V307/ch58x | ch32_usbfs/ch32_usbhs/ch58x |[wch_repo](https://github.com/CherryUSB/cherryusb_wch)|latest |
 |Nordicsemi |  Nrf52840 | nrf5x |[nrf5x_repo](https://github.com/CherryUSB/cherryusb_nrf5x)|latest |
+|Espressif    |  esp32s3 | dwc2 |[esp32_repo](https://github.com/CherryUSB/cherryusb_esp32)|latest |
+|Bekencorp    |  BK72xx | musb |[armino](https://github.com/CherryUSB/armino)|v0.7.0 |
+|Sophgo    |  cv18xx | dwc2 |[cvi_alios_open](https://github.com/CherryUSB/cvi_alios_open)|v0.7.0 |
 |Nuvoton    |  Nuc442 | nuvoton |[nuc442_repo](https://github.com/CherryUSB/cherryusb_nuc442)|v0.4.1 |
 |Geehy    |  APM32E10x APM32F0xx| fsdev |[apm32_repo](https://github.com/CherryUSB/cherryusb_apm32)|v0.4.1 |
-|Espressif    |  esp32 | dwc2 |[esp32_repo](https://github.com/CherryUSB/cherryusb_esp32)|v0.4.1 |
-|Mindmotion    |  MM32L3xx | mm32 |[mm32_repo](https://github.com/CherryUSB/cherryusb_mm32)|v0.4.1 |
 
 ## Contact
 

cherryusb_config_template.h

@@ -6,7 +6,7 @@
 #ifndef CHERRYUSB_CONFIG_H
 #define CHERRYUSB_CONFIG_H
 
-#define CHERRYUSB_VERSION 0x000800
+#define CHERRYUSB_VERSION 0x000900
 
 /* ================ USB common Configuration ================ */
 

class/audio/usb_audio.h

@@ -760,7 +760,7 @@ struct audio_cs_ep_ep_general_descriptor {
     __VA_ARGS__,                     /* bmaControls(0) Mute */                   \
     0x00                             /* iTerminal */
 
-#define AUDIO_AS_DESCRIPTOR_INIT(bInterfaceNumber, bTerminalLink, bNrChannels, bSubFrameSize, bBitResolution, bEndpointAddress, wMaxPacketSize, bInterval, ...) \
+#define AUDIO_AS_DESCRIPTOR_INIT(bInterfaceNumber, bTerminalLink, bNrChannels, bSubFrameSize, bBitResolution, bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval, ...) \
     0x09,                            /* bLength */                                                                       \
     USB_DESCRIPTOR_TYPE_INTERFACE,   /* bDescriptorType */                                                               \
     bInterfaceNumber,                /* bInterfaceNumber */                                                              \
@@ -797,7 +797,7 @@ struct audio_cs_ep_ep_general_descriptor {
     0x09,                            /* bLength */                                                                       \
     USB_DESCRIPTOR_TYPE_ENDPOINT,    /* bDescriptorType */                                                               \
     bEndpointAddress,                /* bEndpointAddress : IN endpoint 1 */                                              \
-    0x01,                            /* bmAttributes */                                                                  \
+    bmAttributes,                    /* bmAttributes */                                                                  \
     WBVAL(wMaxPacketSize),           /* wMaxPacketSize */                                                                \
     bInterval,                       /* bInterval : one packet per frame */                                              \
     0x00,                            /* bRefresh */                                                                      \
@@ -1033,7 +1033,7 @@ struct audio_v2_control_range3_param_block {
     __VA_ARGS__,                     /* bmaControls(0) Mute */        \
     0x00                             /* iTerminal */
 
-#define AUDIO_V2_AS_DESCRIPTOR_INIT(bInterfaceNumber, bTerminalLink, bNrChannels, bmChannelConfig, bSubslotSize, bBitResolution, bEndpointAddress, wMaxPacketSize, bInterval) \
+#define AUDIO_V2_AS_DESCRIPTOR_INIT(bInterfaceNumber, bTerminalLink, bNrChannels, bmChannelConfig, bSubslotSize, bBitResolution, bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \
     0x09,                            /* bLength */                                                                                                                        \
     USB_DESCRIPTOR_TYPE_INTERFACE,   /* bDescriptorType */                                                                                                                \
     bInterfaceNumber,                /* bInterfaceNumber */                                                                                                               \
@@ -1071,7 +1071,7 @@ struct audio_v2_control_range3_param_block {
     0x07,                            /* bLength */                                                                                                                        \
     USB_DESCRIPTOR_TYPE_ENDPOINT,    /* bDescriptorType */                                                                                                                \
     bEndpointAddress,                /* bEndpointAddress 3 out endpoint for Audio */                                                                                      \
-    0x01,                            /* bmAttributes */                                                                                                                   \
+    bmAttributes,                    /* bmAttributes */                                                                                                                   \
     WBVAL(wMaxPacketSize),           /* XXXX wMaxPacketSize in Bytes (SampleRate * SlotByteSize * NumChannels) */                                                               \
     bInterval,                       /* bInterval */                                                                                                                      \
     0x08,                            /* bLength */                                                                                                                        \
@@ -1083,9 +1083,66 @@ struct audio_v2_control_range3_param_block {
     0x00,                            /* wLockDelay */                                                                                                                     \
     0x00
 
+#define AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_INIT(bInterfaceNumber, bTerminalLink, bNrChannels, bmChannelConfig, bSubslotSize, bBitResolution, bEndpointAddress, wMaxPacketSize, bInterval, bFeedbackEndpointAddress) \
+    0x09,                            /* bLength */                                                                                                                        \
+    USB_DESCRIPTOR_TYPE_INTERFACE,   /* bDescriptorType */                                                                                                                \
+    bInterfaceNumber,                /* bInterfaceNumber */                                                                                                               \
+    0x00,                            /* bAlternateSetting */                                                                                                              \
+    0x00,                            /* bNumEndpoints */                                                                                                                  \
+    USB_DEVICE_CLASS_AUDIO,          /* bInterfaceClass */                                                                                                                \
+    AUDIO_SUBCLASS_AUDIOSTREAMING,   /* bInterfaceSubClass */                                                                                                             \
+    AUDIO_PROTOCOLv20,               /* bInterfaceProtocol */                                                                                                             \
+    0x00,                            /* iInterface */                                                                                                                     \
+    0x09,                            /* bLength */                                                                                                                        \
+    USB_DESCRIPTOR_TYPE_INTERFACE,   /* bDescriptorType */                                                                                                                \
+    bInterfaceNumber,                /* bInterfaceNumber */                                                                                                               \
+    0x01,                            /* bAlternateSetting */                                                                                                              \
+    0x02,                            /* bNumEndpoints */                                                                                                                  \
+    USB_DEVICE_CLASS_AUDIO,          /* bInterfaceClass */                                                                                                                \
+    AUDIO_SUBCLASS_AUDIOSTREAMING,   /* bInterfaceSubClass */                                                                                                             \
+    AUDIO_PROTOCOLv20,               /* bInterfaceProtocol */                                                                                                             \
+    0x00,                            /* iInterface */                                                                                                                     \
+    0x10,                            /* bLength */                                                                                                                        \
+    AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */                                                                                                                \
+    AUDIO_STREAMING_GENERAL,         /* bDescriptorSubtype */                                                                                                             \
+    bTerminalLink,                   /* bTerminalLink : Unit ID of the Output or Input Terminal*/                                                                         \
+    0x00,                            /* bmControls */                                                                                                                     \
+    AUDIO_FORMAT_TYPE_I,             /* bFormatType : AUDIO_FORMAT_TYPE_I */                                                                                              \
+    DBVAL(AUDIO_V2_FORMAT_PCM),      /* bmFormats PCM */                                                                                                                  \
+    bNrChannels,                     /* bNrChannels */                                                                                                                    \
+    DBVAL(bmChannelConfig),          /* bmChannelConfig */                                                                                                                \
+    0x00,                            /* iChannelNames */                                                                                                                  \
+    0x06,                            /* bLength */                                                                                                                        \
+    AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */                                                                                                                \
+    AUDIO_STREAMING_FORMAT_TYPE,     /* bDescriptorSubtype */                                                                                                             \
+    AUDIO_FORMAT_TYPE_I,             /* bFormatType */                                                                                                                    \
+    bSubslotSize,                    /* bSubslotSize */                                                                                                                   \
+    bBitResolution,                  /* bBitResolution */                                                                                                                 \
+    0x07,                            /* bLength */                                                                                                                        \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,    /* bDescriptorType */                                                                                                                \
+    bEndpointAddress,                /* bEndpointAddress 3 out endpoint for Audio */                                                                                      \
+    0x05,                            /* bmAttributes: TransferType=Isochronous  SyncType=Asynchronous  EndpointType=Data*/                                                \
+    WBVAL(wMaxPacketSize),           /* XXXX wMaxPacketSize in Bytes (SampleRate * SlotByteSize * NumChannels) */                                                         \
+    bInterval,                       /* bInterval */                                                                                                                      \
+    0x08,                            /* bLength */                                                                                                                        \
+    AUDIO_ENDPOINT_DESCRIPTOR_TYPE,  /* bDescriptorType */                                                                                                                \
+    AUDIO_ENDPOINT_GENERAL,          /* bDescriptor */                                                                                                                    \
+    0x00,                            /* bmAttributes */                                                                                                                   \
+    0x00,                            /* bmControls */                                                                                                                     \
+    0x00,                            /* bLockDelayUnits */                                                                                                                \
+    0x00,                            /* wLockDelay */                                                                                                                     \
+    0x00,                                                                                                                                                                 \
+    0x07,                            /* bLength */                                                                                                                        \
+    USB_DESCRIPTOR_TYPE_ENDPOINT,    /* bDescriptorType */                                                                                                                \
+    bFeedbackEndpointAddress,        /* bFeedbackEndpointAddress Revise Dir to bEndpointAddress */                                                                        \
+    0x11,                            /* bmAttributes: TransferType=Isochronous  SyncType=None  EndpointType=Feedback */                                                   \
+    WBVAL(4),                        /* XXXX wMaxPacketSize in Bytes */                                                                                                   \
+    bInterval                        /* bInterval */                                                                                                                      \
+
 // clang-format on
 
 #define AUDIO_V2_AS_DESCRIPTOR_INIT_LEN (0x09 + 0x09 + 0x10 + 0x06 + 0x07 + 0x08)
+#define AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_INIT_LEN (0x09 + 0x09 + 0x10 + 0x06 + 0x07 + 0x08 + 0x07)
 
 #define AUDIO_SAMPLE_FREQ_NUM(num) (uint8_t)(num), (uint8_t)((num >> 8))
 #define AUDIO_SAMPLE_FREQ_3B(frq)  (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16))

class/audio/usbh_audio.c

@@ -159,10 +159,70 @@ int usbh_audio_close(struct usbh_audio *audio_class, const char *name)
     setup->wLength = 0;
 
     ret = usbh_control_transfer(audio_class->hport->ep0, setup, NULL);
-    if (ret < 0) {
-        return ret;
+
+    return ret;
+}
+
+int usbh_audio_set_volume(struct usbh_audio *audio_class, const char *name, uint8_t ch, uint8_t volume)
+{
+    struct usb_setup_packet *setup = audio_class->hport->setup;
+    int ret;
+    uint8_t intf = 0xff;
+    uint8_t feature_id = 0xff;
+    uint16_t volume_hex;
+
+    for (size_t i = 0; i < audio_class->module_num; i++) {
+        if (strcmp(name, audio_class->module[i].name) == 0) {
+            intf = audio_class->ctrl_intf;
+            feature_id = audio_class->module[i].feature_unit_id;
+        }
     }
 
+    if (intf == 0xff) {
+        return -ENODEV;
+    }
+
+    setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE;
+    setup->bRequest = AUDIO_REQUEST_SET_CUR;
+    setup->wValue = (AUDIO_FU_CONTROL_VOLUME << 8) | ch;
+    setup->wIndex = (feature_id << 8) | intf;
+    setup->wLength = 2;
+
+    volume_hex = -0xDB00 / 100 * volume + 0xdb00;
+
+    memcpy(g_audio_buf, &volume_hex, 2);
+    ret = usbh_control_transfer(audio_class->hport->ep0, setup, NULL);
+
+    return ret;
+}
+
+int usbh_audio_set_mute(struct usbh_audio *audio_class, const char *name, uint8_t ch, bool mute)
+{
+    struct usb_setup_packet *setup = audio_class->hport->setup;
+    int ret;
+    uint8_t intf = 0xff;
+    uint8_t feature_id = 0xff;
+
+    for (size_t i = 0; i < audio_class->module_num; i++) {
+        if (strcmp(name, audio_class->module[i].name) == 0) {
+            intf = audio_class->ctrl_intf;
+            feature_id = audio_class->module[i].feature_unit_id;
+        }
+    }
+
+    if (intf == 0xff) {
+        return -ENODEV;
+    }
+
+    setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE;
+    setup->bRequest = AUDIO_REQUEST_SET_CUR;
+    setup->wValue = (AUDIO_FU_CONTROL_MUTE << 8) | ch;
+    setup->wIndex = (feature_id << 8) | intf;
+    setup->wLength = 1;
+
+    memcpy(g_audio_buf, &mute, 1);
+    ret = usbh_control_transfer(audio_class->hport->ep0, setup, g_audio_buf);
+
     return ret;
 }
 
@@ -362,12 +422,13 @@ static int usbh_audio_ctrl_disconnect(struct usbh_hubport *hport, uint8_t intf)
             usbh_pipe_free(audio_class->isoout);
         }
 
-        usbh_audio_stop(audio_class);
+        if (hport->config.intf[intf].devname[0] != '\0') {
+            USB_LOG_INFO("Unregister Audio Class:%s\r\n", hport->config.intf[intf].devname);
+            usbh_audio_stop(audio_class);
+        }
+
         memset(audio_class, 0, sizeof(struct usbh_audio));
         usb_free(audio_class);
-
-        if (hport->config.intf[intf].devname[0] != '\0')
-            USB_LOG_INFO("Unregister Audio Class:%s\r\n", hport->config.intf[intf].devname);
     }
 
     return ret;

class/audio/usbh_audio.h

@@ -61,6 +61,8 @@ extern "C" {
 
 int usbh_audio_open(struct usbh_audio *audio_class, const char *name, uint32_t samp_freq);
 int usbh_audio_close(struct usbh_audio *audio_class, const char *name);
+int usbh_audio_set_volume(struct usbh_audio *audio_class, const char *name, uint8_t ch, uint8_t volume);
+int usbh_audio_set_mute(struct usbh_audio *audio_class, const char *name, uint8_t ch, bool mute);
 
 void usbh_audio_run(struct usbh_audio *audio_class);
 void usbh_audio_stop(struct usbh_audio *audio_class);

class/cdc/usbd_cdc.c

@@ -16,6 +16,7 @@ static int cdc_acm_class_interface_request_handler(struct usb_setup_packet *setu
                 setup->bRequest);
 
     struct cdc_line_coding line_coding;
+    struct cdc_line_coding line_coding_last;
     bool dtr, rts;
     uint8_t intf_num = LO_BYTE(setup->wIndex);
 
@@ -46,7 +47,13 @@ static int cdc_acm_class_interface_request_handler(struct usb_setup_packet *setu
                         line_coding.bDataBits,
                         parity_name[line_coding.bParityType],
                         stop_name[line_coding.bCharFormat]);
-            usbd_cdc_acm_set_line_coding(intf_num, &line_coding);
+
+            /* check if current line coding is the same with last, if they are the same, do not set line coding */
+            usbd_cdc_acm_get_line_coding(intf_num, &line_coding_last);
+            if (memcmp(&line_coding_last, &line_coding, sizeof(struct cdc_line_coding))) {
+                usbd_cdc_acm_set_line_coding(intf_num, &line_coding);
+            }
+
             break;
 
         case CDC_REQUEST_SET_CONTROL_LINE_STATE: {
@@ -80,22 +87,12 @@ static int cdc_acm_class_interface_request_handler(struct usb_setup_packet *setu
     return 0;
 }
 
-static void cdc_notify_handler(uint8_t event, void *arg)
-{
-    switch (event) {
-        case USBD_EVENT_RESET:
-            break;
-        default:
-            break;
-    }
-}
-
 struct usbd_interface *usbd_cdc_acm_init_intf(struct usbd_interface *intf)
 {
     intf->class_interface_handler = cdc_acm_class_interface_request_handler;
     intf->class_endpoint_handler = NULL;
     intf->vendor_handler = NULL;
-    intf->notify_handler = cdc_notify_handler;
+    intf->notify_handler = NULL;
 
     return intf;
 }

class/cdc/usbh_cdc_acm.c

@@ -124,13 +124,7 @@ static int usbh_cdc_acm_connect(struct usbh_hubport *hport, uint8_t intf)
 
 #ifdef CONFIG_USBHOST_CDC_ACM_NOTIFY
     ep_desc = &hport->config.intf[intf].altsetting[0].ep[0].ep_desc;
-    ep_cfg.ep_addr = ep_desc->bEndpointAddress;
-    ep_cfg.ep_type = ep_desc->bmAttributes & USB_ENDPOINT_TYPE_MASK;
-    ep_cfg.ep_mps = ep_desc->wMaxPacketSize;
-    ep_cfg.ep_interval = ep_desc->bInterval;
-    ep_cfg.hport = hport;
-    usbh_pipe_alloc(&cdc_acm_class->intin, &ep_cfg);
-
+    usbh_hport_activate_epx(&cdc_acm_class->intin, hport, ep_desc);
 #endif
     for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[0].intf_desc.bNumEndpoints; i++) {
         ep_desc = &hport->config.intf[intf + 1].altsetting[0].ep[i].ep_desc;
@@ -167,12 +161,13 @@ static int usbh_cdc_acm_disconnect(struct usbh_hubport *hport, uint8_t intf)
             usbh_pipe_free(cdc_acm_class->bulkout);
         }
 
-        usbh_cdc_acm_stop(cdc_acm_class);
+        if (hport->config.intf[intf].devname[0] != '\0') {
+            USB_LOG_INFO("Unregister CDC ACM Class:%s\r\n", hport->config.intf[intf].devname);
+            usbh_cdc_acm_stop(cdc_acm_class);
+        }
+
         memset(cdc_acm_class, 0, sizeof(struct usbh_cdc_acm));
         usb_free(cdc_acm_class);
-
-        if (hport->config.intf[intf].devname[0] != '\0')
-            USB_LOG_INFO("Unregister CDC ACM Class:%s\r\n", hport->config.intf[intf].devname);
     }
 
     return ret;
@@ -190,12 +185,10 @@ static int usbh_cdc_data_disconnect(struct usbh_hubport *hport, uint8_t intf)
 
 __WEAK void usbh_cdc_acm_run(struct usbh_cdc_acm *cdc_acm_class)
 {
-
 }
 
 __WEAK void usbh_cdc_acm_stop(struct usbh_cdc_acm *cdc_acm_class)
 {
-
 }
 
 const struct usbh_class_driver cdc_acm_class_driver = {

class/hid/usb_hid.h

@@ -387,7 +387,7 @@
 #define HID_KBD_USAGE_PAGEDOWN        0x4e /* Keyboard PageDown */
 #define HID_KBD_USAGE_RIGHT           0x4f /* eyboard RightArrow */
 #define HID_KBD_USAGE_LEFT            0x50 /* Keyboard LeftArrow */
-#define HID_KBD_USAGE_DOWN            0x5a /* Keyboard DownArrow */
+#define HID_KBD_USAGE_DOWN            0x51 /* Keyboard DownArrow */
 #define HID_KBD_USAGE_UP              0x52 /* Keyboard UpArrow */
 #define HID_KBD_USAGE_KPDNUMLOCK      0x53 /* Keypad Num Lock and Clear */
 #define HID_KBD_USAGE_KPDNUMLOCKCLEAR 0x53 /* Keypad Num Lock and Clear */

class/hid/usbd_hid.c

@@ -17,8 +17,7 @@ static int hid_class_interface_request_handler(struct usb_setup_packet *setup, u
     switch (setup->bRequest) {
         case HID_REQUEST_GET_REPORT:
             /* report id ,report type */
-            (*data)[0] = usbh_hid_get_report(intf_num, LO_BYTE(setup->wValue), HI_BYTE(setup->wValue));
-            *len = 1;
+            usbh_hid_get_report(intf_num, LO_BYTE(setup->wValue), HI_BYTE(setup->wValue), data, len);
             break;
         case HID_REQUEST_GET_IDLE:
             (*data)[0] = usbh_hid_get_idle(intf_num, LO_BYTE(setup->wValue));
@@ -61,9 +60,10 @@ struct usbd_interface *usbd_hid_init_intf(struct usbd_interface *intf, const uin
     return intf;
 }
 
-__WEAK uint8_t usbh_hid_get_report(uint8_t intf, uint8_t report_id, uint8_t report_type)
+__WEAK void usbh_hid_get_report(uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t **data, uint32_t *len)
 {
-    return 0;
+    (*data[0]) = 0;
+    *len = 1;
 }
 
 __WEAK uint8_t usbh_hid_get_idle(uint8_t intf, uint8_t report_id)
@@ -76,7 +76,7 @@ __WEAK uint8_t usbh_hid_get_protocol(uint8_t intf)
     return 0;
 }
 
-__WEAK void usbh_hid_set_report(uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t *report, uint8_t report_len)
+__WEAK void usbh_hid_set_report(uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t *report, uint32_t report_len)
 {
 }
 

class/hid/usbd_hid.h

@@ -20,10 +20,10 @@ void usbd_hid_descriptor_register(uint8_t intf_num, const uint8_t *desc);
 void usbd_hid_report_descriptor_register(uint8_t intf_num, const uint8_t *desc, uint32_t desc_len);
 
 /* Setup request command callback api */
-uint8_t usbh_hid_get_report(uint8_t intf, uint8_t report_id, uint8_t report_type);
+void usbh_hid_get_report(uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t **data, uint32_t *len);
 uint8_t usbh_hid_get_idle(uint8_t intf, uint8_t report_id);
 uint8_t usbh_hid_get_protocol(uint8_t intf);
-void usbh_hid_set_report(uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t *report, uint8_t report_len);
+void usbh_hid_set_report(uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t *report, uint32_t report_len);
 void usbh_hid_set_idle(uint8_t intf, uint8_t report_id, uint8_t duration);
 void usbh_hid_set_protocol(uint8_t intf, uint8_t protocol);
 

class/hid/usbh_hid.c

@@ -169,12 +169,13 @@ int usbh_hid_disconnect(struct usbh_hubport *hport, uint8_t intf)
             usbh_pipe_free(hid_class->intout);
         }
 
-        usbh_hid_stop(hid_class);
+        if (hport->config.intf[intf].devname[0] != '\0') {
+            USB_LOG_INFO("Unregister HID Class:%s\r\n", hport->config.intf[intf].devname);
+            usbh_hid_stop(hid_class);
+        }
+
         memset(hid_class, 0, sizeof(struct usbh_hid));
         usb_free(hid_class);
-
-        if (hport->config.intf[intf].devname[0] != '\0')
-            USB_LOG_INFO("Unregister HID Class:%s\r\n", hport->config.intf[intf].devname);
     }
 
     return ret;
@@ -182,12 +183,10 @@ int usbh_hid_disconnect(struct usbh_hubport *hport, uint8_t intf)
 
 __WEAK void usbh_hid_run(struct usbh_hid *hid_class)
 {
-
 }
 
 __WEAK void usbh_hid_stop(struct usbh_hid *hid_class)
 {
-
 }
 
 const struct usbh_class_driver hid_class_driver = {

class/hub/usb_hub.h

@@ -7,7 +7,8 @@
 #define USB_HUB_H
 
 /* HUB Class Descriptor Types */
-#define HUB_DESCRIPTOR_TYPE_HUB 0x29
+#define HUB_DESCRIPTOR_TYPE_HUB  0x29
+#define HUB_DESCRIPTOR_TYPE_HUB3 0x2A
 
 /* Hub class requests */
 #define HUB_REQUEST_GET_STATUS      USB_REQUEST_GET_STATUS
@@ -19,6 +20,7 @@
 #define HUB_REQUEST_RESET_TT        (0x09)
 #define HUB_REQUEST_GET_TT_STATE    (0x0a)
 #define HUB_REQUEST_STOP_TT         (0x0b)
+#define HUB_REQUEST_SET_HUB_DEPTH   (0x0C)
 
 /* Hub class features */
 #define HUB_FEATURE_HUB_C_LOCALPOWER  (0x0)

class/hub/usbh_hub.c

@@ -14,10 +14,12 @@
 
 #define EXTHUB_FIRST_INDEX 2
 
+#if CONFIG_USBHOST_MAX_EXTHUBS > 0
 static uint32_t g_devinuse = 0;
+#endif
 
 USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_hub_buf[32];
-USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_hub_intbuf[CONFIG_USBHOST_MAX_EXTHUBS + 1][1];
+USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_hub_intbuf[CONFIG_USBHOST_MAX_EXTHUBS + 1][CONFIG_USB_ALIGN_SIZE];
 
 usb_slist_t hub_class_head = USB_SLIST_OBJECT_INIT(hub_class_head);
 
@@ -36,6 +38,13 @@ static void usbh_hub_thread_wakeup(struct usbh_hub *hub);
 
 static const char *speed_table[] = { "error-speed", "low-speed", "full-speed", "high-speed", "wireless-speed", "super-speed", "superplus-speed" };
 
+#ifdef CONFIG_USBHOST_XHCI
+struct usbh_hubport *usbh_get_roothub_port(unsigned int port)
+{
+    return &roothub.child[port - 1];
+}
+#endif
+
 #if CONFIG_USBHOST_MAX_EXTHUBS > 0
 static int usbh_hub_devno_alloc(void)
 {
@@ -65,6 +74,7 @@ static void usbh_hub_register(struct usbh_hub *hub)
     usb_slist_add_tail(&hub_class_head, &hub->list);
 }
 
+#if CONFIG_USBHOST_MAX_EXTHUBS > 0
 static void usbh_hub_unregister(struct usbh_hub *hub)
 {
     usb_slist_remove(&hub_class_head, &hub->list);
@@ -79,7 +89,16 @@ static int _usbh_hub_get_hub_descriptor(struct usbh_hub *hub, uint8_t *buffer)
 
     setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE;
     setup->bRequest = USB_REQUEST_GET_DESCRIPTOR;
-    setup->wValue = HUB_DESCRIPTOR_TYPE_HUB << 8;
+
+    /* TODO: hub descriptor has some difference between USB 2.0 and USB 3.x,
+       and we havn't handle the difference here */
+    if ((hub->parent->speed == USB_SPEED_SUPER) ||
+        (hub->parent->speed == USB_SPEED_SUPER_PLUS)) {
+        setup->wValue = HUB_DESCRIPTOR_TYPE_HUB3 << 8;
+    } else {
+        setup->wValue = HUB_DESCRIPTOR_TYPE_HUB << 8;
+    }
+
     setup->wIndex = 0;
     setup->wLength = USB_SIZEOF_HUB_DESC;
 
@@ -111,6 +130,7 @@ static int _usbh_hub_get_status(struct usbh_hub *hub, uint8_t *buffer)
     memcpy(buffer, g_hub_buf, 2);
     return ret;
 }
+#endif
 
 static int _usbh_hub_get_portstatus(struct usbh_hub *hub, uint8_t port, struct hub_port_status *port_status)
 {
@@ -163,6 +183,22 @@ static int _usbh_hub_clear_feature(struct usbh_hub *hub, uint8_t port, uint8_t f
     return usbh_control_transfer(hub->parent->ep0, setup, NULL);
 }
 
+static int _usbh_hub_set_depth(struct usbh_hub *hub, uint16_t depth)
+{
+    struct usb_setup_packet *setup;
+
+    setup = hub->parent->setup;
+
+    setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE;
+    setup->bRequest = HUB_REQUEST_SET_HUB_DEPTH;
+    setup->wValue = depth;
+    setup->wIndex = 0;
+    setup->wLength = 0;
+
+    return usbh_control_transfer(hub->parent->ep0, setup, NULL);
+}
+
+#if CONFIG_USBHOST_MAX_EXTHUBS > 0
 static int parse_hub_descriptor(struct usb_hub_descriptor *desc, uint16_t length)
 {
     if (desc->bLength != USB_SIZEOF_HUB_DESC) {
@@ -184,6 +220,7 @@ static int parse_hub_descriptor(struct usb_hub_descriptor *desc, uint16_t length
     }
     return 0;
 }
+#endif
 
 static int usbh_hub_get_portstatus(struct usbh_hub *hub, uint8_t port, struct hub_port_status *port_status)
 {
@@ -239,6 +276,24 @@ static int usbh_hub_clear_feature(struct usbh_hub *hub, uint8_t port, uint8_t fe
     }
 }
 
+static int usbh_hub_set_depth(struct usbh_hub *hub, uint16_t depth)
+{
+    struct usb_setup_packet roothub_setup;
+    struct usb_setup_packet *setup;
+
+    if (hub->is_roothub) {
+        setup = &roothub_setup;
+        setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE;
+        setup->bRequest = HUB_REQUEST_SET_HUB_DEPTH;
+        setup->wValue = depth;
+        setup->wIndex = 0;
+        setup->wLength = 0;
+        return usbh_roothub_control(setup, NULL);
+    } else {
+        return _usbh_hub_set_depth(hub, depth);
+    }
+}
+
 #if CONFIG_USBHOST_MAX_EXTHUBS > 0
 static void hub_int_complete_callback(void *arg, int nbytes)
 {
@@ -291,6 +346,20 @@ static int usbh_hub_connect(struct usbh_hubport *hport, uint8_t intf)
         return -1;
     }
 
+    if (hport->speed == USB_SPEED_SUPER) {
+        uint16_t depth = 0;
+        struct usbh_hubport *parent = hport->parent->parent;
+        while (parent) {
+            depth++;
+            parent = parent->parent->parent;
+        }
+
+        ret = usbh_hub_set_depth(hub, depth);
+        if (ret < 0) {
+            return ret;
+        }
+    }
+
     for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) {
         ret = usbh_hub_set_feature(hub, port + 1, HUB_PORT_FEATURE_POWER);
         if (ret < 0) {
@@ -496,9 +565,25 @@ static void usbh_hub_events(struct usbh_hub *hub)
                         speed = USB_SPEED_HIGH;
                     } else if (portstatus & HUB_PORT_STATUS_LOW_SPEED) {
                         speed = USB_SPEED_LOW;
-                    } else {
+                    }
+#ifdef CONFIG_USBHOST_XHCI
+                    else {
+                        extern uint8_t usbh_get_port_speed(struct usbh_hub * hub, const uint8_t port);
+
+                        /* USB3.0 speed cannot get from portstatus, checkout port speed instead */
+                        uint8_t super_speed = usbh_get_port_speed(hub, port + 1);
+                        if (super_speed > USB_SPEED_HIGH) {
+                            /* assert that when using USB 3.0 ports, attached device must also be USB 3.0 speed */
+                            speed = super_speed;
+                        } else {
+                            speed = USB_SPEED_FULL;
+                        }
+                    }
+#else
+                    else {
                         speed = USB_SPEED_FULL;
                     }
+#endif
 
                     child = &hub->child[port];
                     /** release child sources first */
@@ -509,14 +594,14 @@ static void usbh_hub_events(struct usbh_hub *hub)
                     child->connected = true;
                     child->port = port + 1;
                     child->speed = speed;
-					
+
                     USB_LOG_INFO("New %s device on Hub %u, Port %u connected\r\n", speed_table[speed], hub->index, port + 1);
 
                     /* Configure EP0 with the default maximum packet size */
                     usbh_hport_activate_ep0(child);
 
                     if (usbh_enumerate(child) < 0) {
-						/** release child sources */
+                        /** release child sources */
                         usbh_hubport_release(child);
                         USB_LOG_ERR("Port %u enumerate fail\r\n", port + 1);
                     }
@@ -524,7 +609,9 @@ static void usbh_hub_events(struct usbh_hub *hub)
                     child = &hub->child[port];
                     /** release child sources */
                     usbh_hubport_release(child);
-                    USB_LOG_ERR("Failed to enable port %u\r\n", port + 1);
+
+                    /** some USB 3.0 ip may failed to enable USB 2.0 port for USB 3.0 device */
+                    USB_LOG_WRN("Failed to enable port %u\r\n", port + 1);
 
                     continue;
                 }
@@ -551,7 +638,7 @@ static void usbh_hub_thread(void *argument)
 
     usb_hc_init();
     while (1) {
-        ret = usb_osal_mq_recv(hub_mq, (uint32_t *)&hub, 0xffffffff);
+        ret = usb_osal_mq_recv(hub_mq, (uintptr_t *)&hub, 0xffffffff);
         if (ret < 0) {
             continue;
         }
@@ -574,7 +661,7 @@ static void usbh_roothub_register(void)
 
 static void usbh_hub_thread_wakeup(struct usbh_hub *hub)
 {
-    usb_osal_mq_send(hub_mq, (uint32_t)hub);
+    usb_osal_mq_send(hub_mq, (uintptr_t)hub);
 }
 
 void usbh_roothub_thread_wakeup(uint8_t port)

class/msc/usbh_msc.c

@@ -53,36 +53,32 @@ static int usbh_msc_get_maxlun(struct usbh_msc *msc_class, uint8_t *buffer)
 
 static void usbh_msc_cbw_dump(struct CBW *cbw)
 {
-#if 0
     int i;
 
-    USB_LOG_INFO("CBW:\r\n");
-    USB_LOG_INFO("  signature: 0x%08x\r\n", (unsigned int)cbw->dSignature);
-    USB_LOG_INFO("  tag:       0x%08x\r\n", (unsigned int)cbw->dTag);
-    USB_LOG_INFO("  datlen:    0x%08x\r\n", (unsigned int)cbw->dDataLength);
-    USB_LOG_INFO("  flags:     0x%02x\r\n", cbw->bmFlags);
-    USB_LOG_INFO("  lun:       0x%02x\r\n", cbw->bLUN);
-    USB_LOG_INFO("  cblen:    0x%02x\r\n", cbw->bCBLength);
+    USB_LOG_DBG("CBW:\r\n");
+    USB_LOG_DBG("  signature: 0x%08x\r\n", (unsigned int)cbw->dSignature);
+    USB_LOG_DBG("  tag:       0x%08x\r\n", (unsigned int)cbw->dTag);
+    USB_LOG_DBG("  datlen:    0x%08x\r\n", (unsigned int)cbw->dDataLength);
+    USB_LOG_DBG("  flags:     0x%02x\r\n", cbw->bmFlags);
+    USB_LOG_DBG("  lun:       0x%02x\r\n", cbw->bLUN);
+    USB_LOG_DBG("  cblen:    0x%02x\r\n", cbw->bCBLength);
 
-    USB_LOG_INFO("CB:\r\n");
+    USB_LOG_DBG("CB:\r\n");
     for (i = 0; i < cbw->bCBLength; i += 8) {
-        USB_LOG_INFO("  0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\r\n",
-                     cbw->CB[i], cbw->CB[i + 1], cbw->CB[i + 2],
-                     cbw->CB[i + 3], cbw->CB[i + 4], cbw->CB[i + 5],
-                     cbw->CB[i + 6], cbw->CB[i + 7]);
+        USB_LOG_DBG("  0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\r\n",
+                    cbw->CB[i], cbw->CB[i + 1], cbw->CB[i + 2],
+                    cbw->CB[i + 3], cbw->CB[i + 4], cbw->CB[i + 5],
+                    cbw->CB[i + 6], cbw->CB[i + 7]);
     }
-#endif
 }
 
 static void usbh_msc_csw_dump(struct CSW *csw)
 {
-#if 0
-    USB_LOG_INFO("CSW:\r\n");
-    USB_LOG_INFO("  signature: 0x%08x\r\n", (unsigned int)csw->dSignature);
-    USB_LOG_INFO("  tag:       0x%08x\r\n", (unsigned int)csw->dTag);
-    USB_LOG_INFO("  residue:   0x%08x\r\n", (unsigned int)csw->dDataResidue);
-    USB_LOG_INFO("  status:    0x%02x\r\n", csw->bStatus);
-#endif
+    USB_LOG_DBG("CSW:\r\n");
+    USB_LOG_DBG("  signature: 0x%08x\r\n", (unsigned int)csw->dSignature);
+    USB_LOG_DBG("  tag:       0x%08x\r\n", (unsigned int)csw->dTag);
+    USB_LOG_DBG("  residue:   0x%08x\r\n", (unsigned int)csw->dDataResidue);
+    USB_LOG_DBG("  status:    0x%02x\r\n", csw->bStatus);
 }
 
 static inline int usbh_msc_bulk_in_transfer(struct usbh_msc *msc_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout)
@@ -113,9 +109,65 @@ static inline int usbh_msc_bulk_out_transfer(struct usbh_msc *msc_class, uint8_t
     return ret;
 }
 
-static inline int usbh_msc_scsi_testunitready(struct usbh_msc *msc_class)
+int usbh_bulk_cbw_csw_xfer(struct usbh_msc *msc_class, struct CBW *cbw, struct CSW *csw, uint8_t *buffer)
 {
     int nbytes;
+
+    usbh_msc_cbw_dump(cbw);
+
+    /* Send the CBW */
+    nbytes = usbh_msc_bulk_out_transfer(msc_class, (uint8_t *)cbw, USB_SIZEOF_MSC_CBW, CONFIG_USBHOST_MSC_TIMEOUT);
+    if (nbytes < 0) {
+        USB_LOG_ERR("cbw transfer error\r\n");
+        goto __err_exit;
+    }
+
+    if (cbw->dDataLength != 0) {
+        if (cbw->CB[0] == SCSI_CMD_WRITE10) {
+            nbytes = usbh_msc_bulk_out_transfer(msc_class, buffer, cbw->dDataLength, CONFIG_USBHOST_MSC_TIMEOUT);
+        } else if (cbw->CB[0] == SCSI_CMD_READCAPACITY10) {
+            nbytes = usbh_msc_bulk_in_transfer(msc_class, buffer, cbw->dDataLength, CONFIG_USBHOST_MSC_TIMEOUT);
+            if (nbytes >= 0) {
+                /* Save the capacity information */
+                msc_class->blocknum = GET_BE32(&buffer[0]) + 1;
+                msc_class->blocksize = GET_BE32(&buffer[4]);
+            }
+        } else {
+            nbytes = usbh_msc_bulk_in_transfer(msc_class, buffer, cbw->dDataLength, CONFIG_USBHOST_MSC_TIMEOUT);
+        }
+
+        if (nbytes < 0) {
+            USB_LOG_ERR("msc data transfer error\r\n");
+            goto __err_exit;
+        }
+    }
+
+    /* Receive the CSW */
+    memset(csw, 0, USB_SIZEOF_MSC_CSW);
+    nbytes = usbh_msc_bulk_in_transfer(msc_class, (uint8_t *)csw, USB_SIZEOF_MSC_CSW, CONFIG_USBHOST_MSC_TIMEOUT);
+    if (nbytes < 0) {
+        USB_LOG_ERR("csw transfer error\r\n");
+        goto __err_exit;
+    }
+
+    usbh_msc_csw_dump(csw);
+
+    /* check csw status */
+    if (csw->dSignature != MSC_CSW_Signature) {
+        USB_LOG_ERR("csw signature error\r\n");
+        return -EINVAL;
+    }
+
+    if (csw->bStatus != 0) {
+        USB_LOG_ERR("csw bStatus %d\r\n", csw->bStatus);
+        return -EINVAL;
+    }
+__err_exit:
+    return nbytes < 0 ? (int)nbytes : 0;
+}
+
+static inline int usbh_msc_scsi_testunitready(struct usbh_msc *msc_class)
+{
     struct CBW *cbw;
 
     /* Construct the CBW */
@@ -126,22 +178,11 @@ static inline int usbh_msc_scsi_testunitready(struct usbh_msc *msc_class)
     cbw->bCBLength = SCSICMD_TESTUNITREADY_SIZEOF;
     cbw->CB[0] = SCSI_CMD_TESTUNITREADY;
 
-    usbh_msc_cbw_dump(cbw);
-    /* Send the CBW */
-    nbytes = usbh_msc_bulk_out_transfer(msc_class, (uint8_t *)cbw, USB_SIZEOF_MSC_CBW, CONFIG_USBHOST_MSC_TIMEOUT);
-    if (nbytes >= 0) {
-        /* Receive the CSW */
-        nbytes = usbh_msc_bulk_in_transfer(msc_class, g_msc_buf, USB_SIZEOF_MSC_CSW, CONFIG_USBHOST_MSC_TIMEOUT);
-        if (nbytes >= 0) {
-            usbh_msc_csw_dump((struct CSW *)g_msc_buf);
-        }
-    }
-    return nbytes < 0 ? (int)nbytes : 0;
+    return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, NULL);
 }
 
 static inline int usbh_msc_scsi_requestsense(struct usbh_msc *msc_class)
 {
-    int nbytes;
     struct CBW *cbw;
 
     /* Construct the CBW */
@@ -150,31 +191,16 @@ static inline int usbh_msc_scsi_requestsense(struct usbh_msc *msc_class)
     cbw->dSignature = MSC_CBW_Signature;
 
     cbw->bmFlags = 0x80;
-    cbw->bCBLength = SCSIRESP_FIXEDSENSEDATA_SIZEOF;
-    cbw->dDataLength = SCSICMD_REQUESTSENSE_SIZEOF;
+    cbw->dDataLength = SCSIRESP_FIXEDSENSEDATA_SIZEOF;
+    cbw->bCBLength = SCSICMD_REQUESTSENSE_SIZEOF;
     cbw->CB[0] = SCSI_CMD_REQUESTSENSE;
     cbw->CB[4] = SCSIRESP_FIXEDSENSEDATA_SIZEOF;
 
-    usbh_msc_cbw_dump(cbw);
-    /* Send the CBW */
-    nbytes = usbh_msc_bulk_out_transfer(msc_class, (uint8_t *)cbw, USB_SIZEOF_MSC_CBW, CONFIG_USBHOST_MSC_TIMEOUT);
-    if (nbytes >= 0) {
-        /* Receive the sense data response */
-        nbytes = usbh_msc_bulk_in_transfer(msc_class, g_msc_buf, SCSIRESP_FIXEDSENSEDATA_SIZEOF, CONFIG_USBHOST_MSC_TIMEOUT);
-        if (nbytes >= 0) {
-            /* Receive the CSW */
-            nbytes = usbh_msc_bulk_in_transfer(msc_class, g_msc_buf, USB_SIZEOF_MSC_CSW, CONFIG_USBHOST_MSC_TIMEOUT);
-            if (nbytes >= 0) {
-                usbh_msc_csw_dump((struct CSW *)g_msc_buf);
-            }
-        }
-    }
-    return nbytes < 0 ? (int)nbytes : 0;
+    return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, g_msc_buf);
 }
 
 static inline int usbh_msc_scsi_inquiry(struct usbh_msc *msc_class)
 {
-    int nbytes;
     struct CBW *cbw;
 
     /* Construct the CBW */
@@ -188,26 +214,11 @@ static inline int usbh_msc_scsi_inquiry(struct usbh_msc *msc_class)
     cbw->CB[0] = SCSI_CMD_INQUIRY;
     cbw->CB[4] = SCSIRESP_INQUIRY_SIZEOF;
 
-    usbh_msc_cbw_dump(cbw);
-    /* Send the CBW */
-    nbytes = usbh_msc_bulk_out_transfer(msc_class, (uint8_t *)cbw, USB_SIZEOF_MSC_CBW, CONFIG_USBHOST_MSC_TIMEOUT);
-    if (nbytes >= 0) {
-        /* Receive the sense data response */
-        nbytes = usbh_msc_bulk_in_transfer(msc_class, g_msc_buf, SCSIRESP_INQUIRY_SIZEOF, CONFIG_USBHOST_MSC_TIMEOUT);
-        if (nbytes >= 0) {
-            /* Receive the CSW */
-            nbytes = usbh_msc_bulk_in_transfer(msc_class, g_msc_buf, USB_SIZEOF_MSC_CSW, CONFIG_USBHOST_MSC_TIMEOUT);
-            if (nbytes >= 0) {
-                usbh_msc_csw_dump((struct CSW *)g_msc_buf);
-            }
-        }
-    }
-    return nbytes < 0 ? (int)nbytes : 0;
+    return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, g_msc_buf);
 }
 
 static inline int usbh_msc_scsi_readcapacity10(struct usbh_msc *msc_class)
 {
-    int nbytes;
     struct CBW *cbw;
 
     /* Construct the CBW */
@@ -220,29 +231,11 @@ static inline int usbh_msc_scsi_readcapacity10(struct usbh_msc *msc_class)
     cbw->bCBLength = SCSICMD_READCAPACITY10_SIZEOF;
     cbw->CB[0] = SCSI_CMD_READCAPACITY10;
 
-    usbh_msc_cbw_dump(cbw);
-    /* Send the CBW */
-    nbytes = usbh_msc_bulk_out_transfer(msc_class, (uint8_t *)cbw, USB_SIZEOF_MSC_CBW, CONFIG_USBHOST_MSC_TIMEOUT);
-    if (nbytes >= 0) {
-        /* Receive the sense data response */
-        nbytes = usbh_msc_bulk_in_transfer(msc_class, g_msc_buf, SCSIRESP_READCAPACITY10_SIZEOF, CONFIG_USBHOST_MSC_TIMEOUT);
-        if (nbytes >= 0) {
-            /* Save the capacity information */
-            msc_class->blocknum = GET_BE32(&g_msc_buf[0]) + 1;
-            msc_class->blocksize = GET_BE32(&g_msc_buf[4]);
-            /* Receive the CSW */
-            nbytes = usbh_msc_bulk_in_transfer(msc_class, g_msc_buf, USB_SIZEOF_MSC_CSW, CONFIG_USBHOST_MSC_TIMEOUT);
-            if (nbytes >= 0) {
-                usbh_msc_csw_dump((struct CSW *)g_msc_buf);
-            }
-        }
-    }
-    return nbytes < 0 ? (int)nbytes : 0;
+    return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, g_msc_buf);
 }
 
 int usbh_msc_scsi_write10(struct usbh_msc *msc_class, uint32_t start_sector, const uint8_t *buffer, uint32_t nsectors)
 {
-    int nbytes;
     struct CBW *cbw;
 
     /* Construct the CBW */
@@ -257,26 +250,11 @@ int usbh_msc_scsi_write10(struct usbh_msc *msc_class, uint32_t start_sector, con
     SET_BE32(&cbw->CB[2], start_sector);
     SET_BE16(&cbw->CB[7], nsectors);
 
-    usbh_msc_cbw_dump(cbw);
-    /* Send the CBW */
-    nbytes = usbh_msc_bulk_out_transfer(msc_class, (uint8_t *)cbw, USB_SIZEOF_MSC_CBW, CONFIG_USBHOST_MSC_TIMEOUT);
-    if (nbytes >= 0) {
-        /* Send the user data */
-        nbytes = usbh_msc_bulk_out_transfer(msc_class, (uint8_t *)buffer, msc_class->blocksize * nsectors, CONFIG_USBHOST_MSC_TIMEOUT);
-        if (nbytes >= 0) {
-            /* Receive the CSW */
-            nbytes = usbh_msc_bulk_in_transfer(msc_class, g_msc_buf, USB_SIZEOF_MSC_CSW, CONFIG_USBHOST_MSC_TIMEOUT);
-            if (nbytes >= 0) {
-                usbh_msc_csw_dump((struct CSW *)g_msc_buf);
-            }
-        }
-    }
-    return nbytes < 0 ? (int)nbytes : 0;
+    return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, (uint8_t *)buffer);
 }
 
 int usbh_msc_scsi_read10(struct usbh_msc *msc_class, uint32_t start_sector, const uint8_t *buffer, uint32_t nsectors)
 {
-    int nbytes;
     struct CBW *cbw;
 
     /* Construct the CBW */
@@ -292,21 +270,7 @@ int usbh_msc_scsi_read10(struct usbh_msc *msc_class, uint32_t start_sector, cons
     SET_BE32(&cbw->CB[2], start_sector);
     SET_BE16(&cbw->CB[7], nsectors);
 
-    usbh_msc_cbw_dump(cbw);
-    /* Send the CBW */
-    nbytes = usbh_msc_bulk_out_transfer(msc_class, (uint8_t *)cbw, USB_SIZEOF_MSC_CBW, CONFIG_USBHOST_MSC_TIMEOUT);
-    if (nbytes >= 0) {
-        /* Receive the user data */
-        nbytes = usbh_msc_bulk_in_transfer(msc_class, (uint8_t *)buffer, msc_class->blocksize * nsectors, CONFIG_USBHOST_MSC_TIMEOUT);
-        if (nbytes >= 0) {
-            /* Receive the CSW */
-            nbytes = usbh_msc_bulk_in_transfer(msc_class, g_msc_buf, USB_SIZEOF_MSC_CSW, CONFIG_USBHOST_MSC_TIMEOUT);
-            if (nbytes >= 0) {
-                usbh_msc_csw_dump((struct CSW *)g_msc_buf);
-            }
-        }
-    }
-    return nbytes < 0 ? (int)nbytes : 0;
+    return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, (uint8_t *)buffer);
 }
 
 static int usbh_msc_connect(struct usbh_hubport *hport, uint8_t intf)
@@ -345,8 +309,11 @@ static int usbh_msc_connect(struct usbh_hubport *hport, uint8_t intf)
 
     ret = usbh_msc_scsi_testunitready(msc_class);
     if (ret < 0) {
-        USB_LOG_ERR("Fail to scsi_testunitready\r\n");
-        return ret;
+        ret = usbh_msc_scsi_requestsense(msc_class);
+        if (ret < 0) {
+            USB_LOG_ERR("Fail to scsi_testunitready\r\n");
+            return ret;
+        }
     }
     ret = usbh_msc_scsi_inquiry(msc_class);
     if (ret < 0) {
@@ -392,12 +359,13 @@ static int usbh_msc_disconnect(struct usbh_hubport *hport, uint8_t intf)
             usbh_pipe_free(msc_class->bulkout);
         }
 
-        usbh_msc_stop(msc_class);
+        if (hport->config.intf[intf].devname[0] != '\0') {
+            USB_LOG_INFO("Unregister MSC Class:%s\r\n", hport->config.intf[intf].devname);
+            usbh_msc_stop(msc_class);
+        }
+
         memset(msc_class, 0, sizeof(struct usbh_msc));
         usb_free(msc_class);
-
-        if (hport->config.intf[intf].devname[0] != '\0')
-            USB_LOG_INFO("Unregister MSC Class:%s\r\n", hport->config.intf[intf].devname);
     }
 
     return ret;
@@ -405,12 +373,10 @@ static int usbh_msc_disconnect(struct usbh_hubport *hport, uint8_t intf)
 
 __WEAK void usbh_msc_run(struct usbh_msc *msc_class)
 {
-
 }
 
 __WEAK void usbh_msc_stop(struct usbh_msc *msc_class)
 {
-
 }
 
 const struct usbh_class_driver msc_class_driver = {

class/mtp/usbh_mtp.c

@@ -21,37 +21,22 @@ static int usbh_mtp_connect(struct usbh_hubport *hport, uint8_t intf)
     }
 
     memset(mtp_class, 0, sizeof(struct usbh_mtp));
-
     mtp_class->hport = hport;
-    mtp_class->ctrl_intf = intf;
-    mtp_class->data_intf = intf + 1;
+    mtp_class->intf = intf;
 
     hport->config.intf[intf].priv = mtp_class;
-    hport->config.intf[intf + 1].priv = NULL;
-    strncpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN);
 
 #ifdef CONFIG_USBHOST_MTP_NOTIFY
-    ep_desc = &hport->config.intf[intf].ep[0].ep_desc;
-    ep_cfg.ep_addr = ep_desc->bEndpointAddress;
-    ep_cfg.ep_type = ep_desc->bmAttributes & USB_ENDPOINT_TYPE_MASK;
-    ep_cfg.ep_mps = ep_desc->wMaxPacketSize;
-    ep_cfg.ep_interval = ep_desc->bInterval;
-    ep_cfg.hport = hport;
-    usbh_pipe_alloc(&mtp_class->intin, &ep_cfg);
-
+    ep_desc = &hport->config.intf[intf].altsetting[0].ep[0].ep_desc;
+    usbh_hport_activate_epx(&mtp_class->intin, hport, ep_desc);
 #endif
-    for (uint8_t i = 0; i < hport->config.intf[intf + 1].intf_desc.bNumEndpoints; i++) {
-        ep_desc = &hport->config.intf[intf + 1].ep[i].ep_desc;
+    for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[0].intf_desc.bNumEndpoints; i++) {
+        ep_desc = &hport->config.intf[intf + 1].altsetting[0].ep[i].ep_desc;
 
-        ep_cfg.ep_addr = ep_desc->bEndpointAddress;
-        ep_cfg.ep_type = ep_desc->bmAttributes & USB_ENDPOINT_TYPE_MASK;
-        ep_cfg.ep_mps = ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_MASK;;
-        ep_cfg.ep_interval = ep_desc->bInterval;
-        ep_cfg.hport = hport;
         if (ep_desc->bEndpointAddress & 0x80) {
-            usbh_pipe_alloc(&mtp_class->bulkin, &ep_cfg);
+            usbh_hport_activate_epx(&mtp_class->bulkin, hport, ep_desc);
         } else {
-            usbh_pipe_alloc(&mtp_class->bulkout, &ep_cfg);
+            usbh_hport_activate_epx(&mtp_class->bulkout, hport, ep_desc);
         }
     }
 
@@ -77,14 +62,12 @@ static int usbh_mtp_disconnect(struct usbh_hubport *hport, uint8_t intf)
             usbh_pipe_free(mtp_class->bulkout);
         }
 
-        usb_free(mtp_class);
-
-        if (hport->config.intf[intf].devname[0] != '\0')
+        if (hport->config.intf[intf].devname[0] != '\0') {
             USB_LOG_INFO("Unregister MTP Class:%s\r\n", hport->config.intf[intf].devname);
+        }
 
-        memset(hport->config.intf[intf].devname, 0, CONFIG_USBHOST_DEV_NAMELEN);
-        hport->config.intf[intf].priv = NULL;
-        hport->config.intf[intf + 1].priv = NULL;
+        memset(mtp_class, 0, sizeof(struct usbh_mtp));
+        usb_free(mtp_class);
     }
 
     return ret;

class/printer/usbd_printer.c

@@ -7,7 +7,8 @@
 #include "usbd_printer.h"
 
 struct printer_cfg_priv {
-    uint8_t *device_id;
+    const uint8_t *device_id;
+    uint8_t device_id_len;
     uint8_t port_status;
 } usbd_printer_cfg;
 
@@ -19,7 +20,8 @@ static int printer_class_interface_request_handler(struct usb_setup_packet *setu
 
     switch (setup->bRequest) {
         case PRINTER_REQUEST_GET_DEVICE_ID:
-
+            memcpy(*data, usbd_printer_cfg.device_id, usbd_printer_cfg.device_id_len);
+            *len = usbd_printer_cfg.device_id_len;
             break;
         case PRINTER_REQUEST_GET_PORT_SATTUS:
 
@@ -46,18 +48,14 @@ static void printer_notify_handler(uint8_t event, void *arg)
     }
 }
 
-struct usbd_interface *usbd_printer_alloc_intf(void)
+struct usbd_interface *usbd_printer_init_intf(struct usbd_interface *intf, const uint8_t *device_id, uint8_t device_id_len)
 {
-    struct usbd_interface *intf = usb_malloc(sizeof(struct usbd_interface));
-    if (intf == NULL) {
-        USB_LOG_ERR("no mem to alloc intf\r\n");
-        return NULL;
-    }
-
     intf->class_interface_handler = printer_class_interface_request_handler;
     intf->class_endpoint_handler = NULL;
     intf->vendor_handler = NULL;
     intf->notify_handler = printer_notify_handler;
 
+    usbd_printer_cfg.device_id = device_id;
+    usbd_printer_cfg.device_id_len = device_id_len;
     return intf;
-}
+}

class/printer/usbd_printer.h

@@ -12,8 +12,8 @@
 extern "C" {
 #endif
 
-/* Alloc printer interface driver */
-struct usbd_interface *usbd_printer_alloc_intf(void);
+/* Init printer interface driver */
+struct usbd_interface *usbd_printer_init_intf(struct usbd_interface *intf, const uint8_t *device_id, uint8_t device_id_len);
 
 #ifdef __cplusplus
 }

class/printer/usbh_printer.c

@@ -69,18 +69,13 @@ static int usbh_printer_connect(struct usbh_hubport *hport, uint8_t intf)
 
     hport->config.intf[intf].priv = printer_class;
 
-    for (uint8_t i = 0; i < hport->config.intf[intf + 1].intf_desc.bNumEndpoints; i++) {
-        ep_desc = &hport->config.intf[intf + 1].ep[i].ep_desc;
+    for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[0].intf_desc.bNumEndpoints; i++) {
+        ep_desc = &hport->config.intf[intf + 1].altsetting[0].ep[i].ep_desc;
 
-        ep_cfg.ep_addr = ep_desc->bEndpointAddress;
-        ep_cfg.ep_type = ep_desc->bmAttributes & USB_ENDPOINT_TYPE_MASK;
-        ep_cfg.ep_mps = ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_MASK;
-        ep_cfg.ep_interval = ep_desc->bInterval;
-        ep_cfg.hport = hport;
         if (ep_desc->bEndpointAddress & 0x80) {
-            usbh_pipe_alloc(&printer_class->bulkin, &ep_cfg);
+            usbh_hport_activate_epx(&printer_class->bulkin, hport, ep_desc);
         } else {
-            usbh_pipe_alloc(&printer_class->bulkout, &ep_cfg);
+            usbh_hport_activate_epx(&printer_class->bulkout, hport, ep_desc);
         }
     }
 
@@ -90,7 +85,7 @@ static int usbh_printer_connect(struct usbh_hubport *hport, uint8_t intf)
 
     USB_LOG_INFO("Register Printer Class:%s\r\n", hport->config.intf[intf].devname);
 
-    return ret;
+    return 0;
 }
 
 static int usbh_printer_disconnect(struct usbh_hubport *hport, uint8_t intf)
@@ -108,13 +103,12 @@ static int usbh_printer_disconnect(struct usbh_hubport *hport, uint8_t intf)
             usbh_pipe_free(printer_class->bulkout);
         }
 
-        usb_free(printer_class);
-
-        if (hport->config.intf[intf].devname[0] != '\0')
+        if (hport->config.intf[intf].devname[0] != '\0') {
             USB_LOG_INFO("Unregister Printer Class:%s\r\n", hport->config.intf[intf].devname);
+        }
 
-        memset(hport->config.intf[intf].devname, 0, CONFIG_USBHOST_DEV_NAMELEN);
-        hport->config.intf[intf].priv = NULL;
+        memset(printer_class, 0, sizeof(struct usbh_printer));
+        usb_free(printer_class);
     }
 
     return ret;

class/video/usbd_video.c

@@ -576,10 +576,10 @@ static int usbd_video_stream_request_handler(struct usb_setup_packet *setup, uin
         case VIDEO_VS_PROBE_CONTROL:
             switch (setup->bRequest) {
                 case VIDEO_REQUEST_SET_CUR:
-                    //memcpy((uint8_t *)usbd_video_cfg.probe, *data, setup->wLength);
+                    //memcpy((uint8_t *)&usbd_video_cfg.probe, *data, setup->wLength);
                     break;
                 case VIDEO_REQUEST_GET_CUR:
-                    *data = (uint8_t *)&usbd_video_cfg.probe;
+                    memcpy(*data, (uint8_t *)&usbd_video_cfg.probe, setup->wLength);
                     *len = sizeof(struct video_probe_and_commit_controls);
                     break;
 
@@ -587,7 +587,7 @@ static int usbd_video_stream_request_handler(struct usb_setup_packet *setup, uin
                 case VIDEO_REQUEST_GET_MAX:
                 case VIDEO_REQUEST_GET_RES:
                 case VIDEO_REQUEST_GET_DEF:
-                    *data = (uint8_t *)&usbd_video_cfg.probe;
+                    memcpy(*data, (uint8_t *)&usbd_video_cfg.probe, setup->wLength);
                     *len = sizeof(struct video_probe_and_commit_controls);
                     break;
                 case VIDEO_REQUEST_GET_LEN:
@@ -608,17 +608,17 @@ static int usbd_video_stream_request_handler(struct usb_setup_packet *setup, uin
         case VIDEO_VS_COMMIT_CONTROL:
             switch (setup->bRequest) {
                 case VIDEO_REQUEST_SET_CUR:
-                    //memcpy((uint8_t *)usbd_video_cfg.commit, *data, setup->wLength);
+                    //memcpy((uint8_t *)&usbd_video_cfg.commit, *data, setup->wLength);
                     break;
                 case VIDEO_REQUEST_GET_CUR:
-                    *data = (uint8_t *)&usbd_video_cfg.commit;
+                    memcpy(*data, (uint8_t *)&usbd_video_cfg.commit, setup->wLength);
                     *len = sizeof(struct video_probe_and_commit_controls);
                     break;
                 case VIDEO_REQUEST_GET_MIN:
                 case VIDEO_REQUEST_GET_MAX:
                 case VIDEO_REQUEST_GET_RES:
                 case VIDEO_REQUEST_GET_DEF:
-                    *data = (uint8_t *)&usbd_video_cfg.commit;
+                    memcpy(*data, (uint8_t *)&usbd_video_cfg.commit, setup->wLength);
                     *len = sizeof(struct video_probe_and_commit_controls);
                     break;
 
@@ -640,7 +640,7 @@ static int usbd_video_stream_request_handler(struct usb_setup_packet *setup, uin
         case VIDEO_VS_STREAM_ERROR_CODE_CONTROL:
             switch (setup->bRequest) {
                 case VIDEO_REQUEST_GET_CUR:
-                    *data = &usbd_video_cfg.error_code;
+                    (*data)[0] = usbd_video_cfg.error_code;
                     *len = 1;
                     break;
                 case VIDEO_REQUEST_GET_INFO:

class/video/usbh_video.c

@@ -27,49 +27,6 @@ USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_video_buf[128];
 
 static const char *format_type[] = { "uncompressed", "mjpeg" };
 
-static int __s_r_1370705v[256] = { 0 };
-static int __s_b_1732446u[256] = { 0 };
-static int __s_g_337633u[256] = { 0 };
-static int __s_g_698001v[256] = { 0 };
-
-void usbh_video_inityuyv2rgb_table(void)
-{
-    for (int i = 0; i < 256; i++) {
-        __s_r_1370705v[i] = (1.370705 * (i - 128));
-        __s_b_1732446u[i] = (1.732446 * (i - 128));
-        __s_g_337633u[i] = (0.337633 * (i - 128));
-        __s_g_698001v[i] = (0.698001 * (i - 128));
-    }
-}
-
-void usbh_video_yuyv2rgb565(void *input, void *output, uint32_t len)
-{
-    int y0, u, y1, v;
-    uint8_t r, g, b;
-    int val;
-
-    for (uint32_t i = 0; i < len / 4; i++) {
-        y0 = (int)(((uint8_t *)input)[i * 4 + 0]);
-        u = (int)(((uint8_t *)input)[i * 4 + 1]);
-        y1 = (int)(((uint8_t *)input)[i * 4 + 2]);
-        v = (int)(((uint8_t *)input)[i * 4 + 3]);
-        val = y0 + __s_r_1370705v[v];
-        r = (val < 0) ? 0 : ((val > 255) ? 255 : (uint8_t)val);
-        val = y0 - __s_g_337633u[u] - __s_g_698001v[v];
-        g = (val < 0) ? 0 : ((val > 255) ? 255 : (uint8_t)val);
-        val = y0 + __s_b_1732446u[u];
-        b = (val < 0) ? 0 : ((val > 255) ? 255 : (uint8_t)val);
-        ((uint16_t *)output)[i * 2] = (uint16_t)(b >> 3) | ((uint16_t)(g >> 2) << 5) | ((uint16_t)(r >> 3) << 11);
-        val = y1 + __s_r_1370705v[v];
-        r = (val < 0) ? 0 : ((val > 255) ? 255 : (uint8_t)val);
-        val = y1 - __s_g_337633u[u] - __s_g_698001v[v];
-        g = (val < 0) ? 0 : ((val > 255) ? 255 : (uint8_t)val);
-        val = y1 + __s_b_1732446u[u];
-        b = (val < 0) ? 0 : ((val > 255) ? 255 : (uint8_t)val);
-        ((uint16_t *)output)[i * 2 + 1] = (uint16_t)(b >> 3) | ((uint16_t)(g >> 2) << 5) | ((uint16_t)(r >> 3) << 11);
-    }
-}
-
 static int usbh_video_devno_alloc(struct usbh_video *video_class)
 {
     int devno;
@@ -117,6 +74,7 @@ int usbh_video_get_cur(struct usbh_video *video_class, uint8_t intf, uint8_t ent
 int usbh_video_set_cur(struct usbh_video *video_class, uint8_t intf, uint8_t entity_id, uint8_t cs, uint8_t *buf, uint16_t len)
 {
     struct usb_setup_packet *setup = video_class->hport->setup;
+    int ret;
 
     setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE;
     setup->bRequest = VIDEO_REQUEST_SET_CUR;
@@ -126,7 +84,9 @@ int usbh_video_set_cur(struct usbh_video *video_class, uint8_t intf, uint8_t ent
 
     memcpy(g_video_buf, buf, len);
 
-    return usbh_control_transfer(video_class->hport->ep0, setup, g_video_buf);
+    ret = usbh_control_transfer(video_class->hport->ep0, setup, g_video_buf);
+    usb_osal_msleep(5);
+    return ret;
 }
 
 int usbh_videostreaming_get_cur_probe(struct usbh_video *video_class)
@@ -427,9 +387,7 @@ static int usbh_video_ctrl_connect(struct usbh_hubport *hport, uint8_t intf)
     usbh_video_list_info(video_class);
 
     snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, video_class->minor);
-#ifdef CONFIG_USBHOST_UVC_YUV2RGB
-    inityuyv2rgb_table();
-#endif
+
     USB_LOG_INFO("Register Video Class:%s\r\n", hport->config.intf[intf].devname);
 
     usbh_video_run(video_class);
@@ -453,12 +411,13 @@ static int usbh_video_ctrl_disconnect(struct usbh_hubport *hport, uint8_t intf)
             usbh_pipe_free(video_class->isoout);
         }
 
-        usbh_video_stop(video_class);
+        if (hport->config.intf[intf].devname[0] != '\0') {
+            USB_LOG_INFO("Unregister Video Class:%s\r\n", hport->config.intf[intf].devname);
+            usbh_video_stop(video_class);
+        }
+
         memset(video_class, 0, sizeof(struct usbh_video));
         usb_free(video_class);
-
-        if (hport->config.intf[intf].devname[0] != '\0')
-            USB_LOG_INFO("Unregister Video Class:%s\r\n", hport->config.intf[intf].devname);
     }
 
     return ret;
@@ -474,6 +433,7 @@ static int usbh_video_streaming_disconnect(struct usbh_hubport *hport, uint8_t i
     return 0;
 }
 
+#if 0
 void usbh_videostreaming_parse_mjpeg(struct usbh_urb *urb, struct usbh_videostreaming *stream)
 {
     struct usbh_iso_frame_packet *iso_packet;
@@ -511,29 +471,33 @@ void usbh_videostreaming_parse_mjpeg(struct usbh_urb *urb, struct usbh_videostre
             continue;
         }
 
-        if ((stream->bufoffset == 0) && (iso_packet[i].transfer_buffer[header_len] != 0xff) && (iso_packet[i].transfer_buffer[header_len + 1] != 0xd8)) {
+        if ((stream->bufoffset == 0) && ((iso_packet[i].transfer_buffer[header_len] != 0xff) || (iso_packet[i].transfer_buffer[header_len + 1] != 0xd8))) {
             stream->bufoffset = 0;
             continue;
         }
 
-        data_offset = iso_packet[i].transfer_buffer[0];
-        data_len = iso_packet[i].actual_length - iso_packet[i].transfer_buffer[0];
+        data_offset = header_len;
+        data_len = iso_packet[i].actual_length - header_len;
 
-        usbh_videostreaming_output(&iso_packet[i].transfer_buffer[data_offset], data_len);
+        /** do something here */
 
         stream->bufoffset += data_len;
 
         if (iso_packet[i].transfer_buffer[1] & (1 << 1)) {
-            if ((iso_packet[i].transfer_buffer[iso_packet[i].actual_length - 2] != 0xff) && (iso_packet[i].transfer_buffer[iso_packet[i].actual_length - 1] != 0xd9)) {
+            if ((iso_packet[i].transfer_buffer[iso_packet[i].actual_length - 2] != 0xff) || (iso_packet[i].transfer_buffer[iso_packet[i].actual_length - 1] != 0xd9)) {
                 stream->bufoffset = 0;
                 continue;
             }
+
+            /** do something here */
+
             if (stream->video_one_frame_callback) {
                 stream->video_one_frame_callback(stream);
             }
             stream->bufoffset = 0;
         }
     }
+    /** do something here */
 }
 
 void usbh_videostreaming_parse_yuyv2(struct usbh_urb *urb, struct usbh_videostreaming *stream)
@@ -574,20 +538,26 @@ void usbh_videostreaming_parse_yuyv2(struct usbh_urb *urb, struct usbh_videostre
             continue;
         }
 
-        data_offset = iso_packet[i].transfer_buffer[0];
-        data_len = iso_packet[i].actual_length - iso_packet[i].transfer_buffer[0];
+        data_offset = header_len;
+        data_len = iso_packet[i].actual_length - header_len;
+
+        /** do something here */
 
-        usbh_videostreaming_output(&iso_packet[i].transfer_buffer[data_offset], data_len);
         stream->bufoffset += data_len;
 
         if (iso_packet[i].transfer_buffer[1] & (1 << 1)) {
-            if (stream->video_one_frame_callback) {
+            /** do something here */
+
+            if (stream->video_one_frame_callback && (stream->bufoffset == stream->buflen)) {
                 stream->video_one_frame_callback(stream);
             }
             stream->bufoffset = 0;
         }
     }
+
+    /** do something here */
 }
+#endif
 
 __WEAK void usbh_video_run(struct usbh_video *video_class)
 {

class/video/usbh_video.h

@@ -17,14 +17,14 @@ struct usbh_video_resolution {
 };
 
 struct usbh_video_format {
-    struct usbh_video_resolution frame[8];
+    struct usbh_video_resolution frame[12];
     uint8_t format_type;
     uint8_t num_of_frames;
 };
 
 struct usbh_videostreaming {
-    uint8_t *bufbase;
     uint32_t bufoffset;
+    uint32_t buflen;
     void (*video_one_frame_callback)(struct usbh_videostreaming *stream);
 };
 

class/wireless/usbh_rndis.c

@@ -9,7 +9,7 @@
 
 #define DEV_FORMAT "/dev/rndis"
 
-USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_buf[1024];
+USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_buf[4096];
 
 static int usbh_rndis_init_msg_transfer(struct usbh_rndis *rndis_class)
 {
@@ -81,7 +81,7 @@ int usbh_rndis_query_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid,
     setup->wIndex = 0;
     setup->wLength = sizeof(rndis_query_msg_t);
 
-    ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)&cmd);
+    ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)cmd);
     if (ret < 0) {
         USB_LOG_ERR("oid:%08x send error, ret: %d\r\n", (unsigned int)oid, ret);
         return ret;
@@ -205,7 +205,7 @@ int usbh_rndis_keepalive(struct usbh_rndis *rndis_class)
     setup->wIndex = 0;
     setup->wLength = sizeof(rndis_keepalive_msg_t);
 
-    ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)&cmd);
+    ret = usbh_control_transfer(rndis_class->hport->ep0, setup, (uint8_t *)cmd);
     if (ret < 0) {
         USB_LOG_ERR("keepalive send error, ret: %d\r\n", ret);
         return ret;
@@ -259,14 +259,7 @@ static int usbh_rndis_connect(struct usbh_hubport *hport, uint8_t intf)
 
 #ifdef CONFIG_USBHOST_RNDIS_NOTIFY
     ep_desc = &hport->config.intf[intf].altsetting[0].ep[0].ep_desc;
-    ep_cfg.ep_addr = ep_desc->bEndpointAddress;
-    ep_cfg.ep_type = ep_desc->bmAttributes & USB_ENDPOINT_TYPE_MASK;
-    ep_cfg.ep_mps = ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_MASK;
-
-    ep_cfg.ep_interval = ep_desc->bInterval;
-    ep_cfg.hport = hport;
-    usbh_pipe_alloc(&rndis_class->intin, &ep_cfg);
-
+    usbh_hport_activate_epx(&rndis_class->intin, hport, ep_desc);
 #endif
     for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[0].intf_desc.bNumEndpoints; i++) {
         ep_desc = &hport->config.intf[intf + 1].altsetting[0].ep[i].ep_desc;
@@ -395,12 +388,13 @@ static int usbh_rndis_disconnect(struct usbh_hubport *hport, uint8_t intf)
             usbh_pipe_free(rndis_class->bulkout);
         }
 
-        usbh_rndis_stop(rndis_class);
+        if (hport->config.intf[intf].devname[0] != '\0') {
+            USB_LOG_INFO("Unregister RNDIS Class:%s\r\n", hport->config.intf[intf].devname);
+            usbh_rndis_stop(rndis_class);
+        }
+
         memset(rndis_class, 0, sizeof(struct usbh_rndis));
         usb_free(rndis_class);
-
-        if (hport->config.intf[intf].devname[0] != '\0')
-            USB_LOG_INFO("Unregister RNDIS Class:%s\r\n", hport->config.intf[intf].devname);
     }
 
     return ret;

common/usb_dc.h

@@ -143,15 +143,37 @@ int usbd_ep_start_read(const uint8_t ep, uint8_t *data, uint32_t data_len);
 
 /* usb dcd irq callback */
 
+/**
+ * @brief Usb connect irq callback.
+ */
+void usbd_event_connect_handler(void);
+
+/**
+ * @brief Usb disconnect irq callback.
+ */
+void usbd_event_disconnect_handler(void);
+
+/**
+ * @brief Usb resume irq callback.
+ */
+void usbd_event_resume_handler(void);
+
+/**
+ * @brief Usb suspend irq callback.
+ */
+void usbd_event_suspend_handler(void);
+
 /**
  * @brief Usb reset irq callback.
  */
 void usbd_event_reset_handler(void);
+
 /**
  * @brief Usb setup packet recv irq callback.
  * @param[in]  psetup  setup packet.
  */
 void usbd_event_ep0_setup_complete_handler(uint8_t *psetup);
+
 /**
  * @brief In ep transfer complete irq callback.
  * @param[in]  ep        Endpoint address corresponding to the one
@@ -159,6 +181,7 @@ void usbd_event_ep0_setup_complete_handler(uint8_t *psetup);
  * @param[in]  nbytes    How many nbytes have transferred.
  */
 void usbd_event_ep_in_complete_handler(uint8_t ep, uint32_t nbytes);
+
 /**
  * @brief Out ep transfer complete irq callback.
  * @param[in]  ep        Endpoint address corresponding to the one
@@ -167,10 +190,6 @@ void usbd_event_ep_in_complete_handler(uint8_t ep, uint32_t nbytes);
  */
 void usbd_event_ep_out_complete_handler(uint8_t ep, uint32_t nbytes);
 
-/**
- * @}
- */
-
 #ifdef __cplusplus
 }
 #endif

common/usb_def.h

@@ -11,6 +11,9 @@
 #define USB_2_0 0x0200
 /* Set USB version to 2.1 so that the host will request the BOS descriptor */
 #define USB_2_1 0x0210
+#define USB_3_0 0x0300
+#define USB_3_1 0x0310
+#define USB_3_2 0x0320
 
 /* Device speeds */
 #define USB_SPEED_UNKNOWN    0 /* Transfer rate not yet set */

common/usb_hc.h

@@ -85,15 +85,15 @@ uint16_t usbh_get_frame_number(void);
 int usbh_roothub_control(struct usb_setup_packet *setup, uint8_t *buf);
 
 /**
- * @brief reconfig control endpoint pipe.
+ * @brief reconfig endpoint pipe.
  *
  * @param pipe A memory allocated for pipe.
  * @param dev_addr device address.
- * @param ep_mps control endpoint max packet size.
- * @param speed port speed
+ * @param ep_mps endpoint max packet size.
+ * @param mult endpoint additional transcation
  * @return On success will return 0, and others indicate fail.
  */
-int usbh_ep0_pipe_reconfigure(usbh_pipe_t pipe, uint8_t dev_addr, uint8_t ep_mps, uint8_t speed);
+int usbh_ep_pipe_reconfigure(usbh_pipe_t pipe, uint8_t dev_addr, uint8_t ep_mps, uint8_t mult);
 
 /**
  * @brief Allocate pipe for endpoint

common/usb_log.h

@@ -52,25 +52,25 @@
 #if (CONFIG_USB_DBG_LEVEL >= USB_DBG_LOG)
 #define USB_LOG_DBG(fmt, ...) usb_dbg_log_line("D", 0, fmt, ##__VA_ARGS__)
 #else
-#define USB_LOG_DBG(...)
+#define USB_LOG_DBG(...)  {}
 #endif
 
 #if (CONFIG_USB_DBG_LEVEL >= USB_DBG_INFO)
 #define USB_LOG_INFO(fmt, ...) usb_dbg_log_line("I", 32, fmt, ##__VA_ARGS__)
 #else
-#define USB_LOG_INFO(...)
+#define USB_LOG_INFO(...) {}
 #endif
 
 #if (CONFIG_USB_DBG_LEVEL >= USB_DBG_WARNING)
 #define USB_LOG_WRN(fmt, ...) usb_dbg_log_line("W", 33, fmt, ##__VA_ARGS__)
 #else
-#define USB_LOG_WRN(...)
+#define USB_LOG_WRN(...) {}
 #endif
 
 #if (CONFIG_USB_DBG_LEVEL >= USB_DBG_ERROR)
 #define USB_LOG_ERR(fmt, ...) usb_dbg_log_line("E", 31, fmt, ##__VA_ARGS__)
 #else
-#define USB_LOG_ERR(...)
+#define USB_LOG_ERR(...) {}
 #endif
 
 #define USB_LOG_RAW(...) CONFIG_USB_PRINTF(__VA_ARGS__)
@@ -82,4 +82,4 @@ void usb_assert(const char *filename, int linenum);
             usb_assert(__FILE__, __LINE__); \
     } while (0)
 
-#endif /* USB_LOG_H */
+#endif /* USB_LOG_H */

core/usbd_core.c

@@ -289,7 +289,8 @@ static bool usbd_get_descriptor(uint16_t type_index, uint8_t **data, uint32_t *l
             return false;
         }
 
-        *data = (uint8_t *)msosv1_desc->string;
+        //*data = (uint8_t *)msosv1_desc->string;
+        memcpy(*data, (uint8_t *)msosv1_desc->string, msosv1_desc->string_len);
         *len = msosv1_desc->string_len;
 
         return true;
@@ -300,7 +301,8 @@ static bool usbd_get_descriptor(uint16_t type_index, uint8_t **data, uint32_t *l
             return false;
         }
 
-        *data = bos_desc->string;
+        //*data = bos_desc->string;
+        memcpy(*data, (uint8_t *)bos_desc->string, bos_desc->string_len);
         *len = bos_desc->string_len;
         return true;
     }
@@ -517,6 +519,11 @@ static bool usbd_std_device_req_handler(struct usb_setup_packet *setup, uint8_t
         case USB_REQUEST_CLEAR_FEATURE:
         case USB_REQUEST_SET_FEATURE:
             if (value == USB_FEATURE_REMOTE_WAKEUP) {
+                if (setup->bRequest == USB_REQUEST_SET_FEATURE) {
+                    usbd_event_handler(USBD_EVENT_SET_REMOTE_WAKEUP);
+                } else {
+                    usbd_event_handler(USBD_EVENT_CLR_REMOTE_WAKEUP);
+                }
             } else if (value == USB_FEATURE_TEST_MODE) {
 #ifdef CONFIG_USBDEV_TEST_MODE
                 usbd_core_cfg.test_mode = true;
@@ -553,7 +560,7 @@ static bool usbd_std_device_req_handler(struct usb_setup_packet *setup, uint8_t
                 usbd_core_cfg.configuration = value;
                 usbd_core_cfg.configured = true;
                 usbd_class_event_notify_handler(USBD_EVENT_CONFIGURED, NULL);
-                usbd_configure_done_callback();
+                usbd_event_handler(USBD_EVENT_CONFIGURED);
             }
             *len = 0;
             break;
@@ -609,7 +616,8 @@ static bool usbd_std_interface_req_handler(struct usb_setup_packet *setup,
                     struct usbd_interface *intf = usb_slist_entry(i, struct usbd_interface, list);
 
                     if (intf->intf_num == intf_num) {
-                        *data = (uint8_t *)intf->hid_report_descriptor;
+                        //*data = (uint8_t *)intf->hid_report_descriptor;
+                        memcpy(*data, intf->hid_report_descriptor, intf->hid_report_descriptor_len);
                         *len = intf->hid_report_descriptor_len;
                         return true;
                     }
@@ -768,7 +776,7 @@ static int usbd_class_request_handler(struct usb_setup_packet *setup, uint8_t **
         {
             struct usbd_interface *intf = usb_slist_entry(i, struct usbd_interface, list);
 
-            if (intf->class_endpoint_handler && (intf->intf_num == ((setup->wIndex >> 8) & 0xFF))) {
+            if (intf->class_endpoint_handler) {
                 return intf->class_endpoint_handler(setup, data, len);
             }
         }
@@ -841,13 +849,15 @@ static int usbd_vendor_request_handler(struct usb_setup_packet *setup, uint8_t *
             switch (setup->wIndex) {
                 case 0x04:
                     USB_LOG_INFO("get Compat ID\r\n");
-                    *data = (uint8_t *)msosv1_desc->compat_id;
+                    //*data = (uint8_t *)msosv1_desc->compat_id;
+                    memcpy(*data, msosv1_desc->compat_id, msosv1_desc->compat_id_len);
                     *len = msosv1_desc->compat_id_len;
 
                     return 0;
                 case 0x05:
                     USB_LOG_INFO("get Compat id properties\r\n");
-                    *data = (uint8_t *)msosv1_desc->comp_id_property;
+                    //*data = (uint8_t *)msosv1_desc->comp_id_property;
+                    memcpy(*data, msosv1_desc->comp_id_property, msosv1_desc->comp_id_property_len);
                     *len = msosv1_desc->comp_id_property_len;
 
                     return 0;
@@ -861,7 +871,8 @@ static int usbd_vendor_request_handler(struct usb_setup_packet *setup, uint8_t *
             switch (setup->wIndex) {
                 case WINUSB_REQUEST_GET_DESCRIPTOR_SET:
                     USB_LOG_INFO("GET MS OS 2.0 Descriptor\r\n");
-                    *data = (uint8_t *)msosv2_desc->compat_id;
+                    //*data = (uint8_t *)msosv2_desc->compat_id;
+                    memcpy(*data, msosv2_desc->compat_id, msosv2_desc->compat_id_len);
                     *len = msosv2_desc->compat_id_len;
                     return 0;
                 default:
@@ -900,7 +911,7 @@ static bool usbd_setup_request_handler(struct usb_setup_packet *setup, uint8_t *
         case USB_REQUEST_STANDARD:
             if (usbd_standard_request_handler(setup, data, len) < 0) {
 #ifndef CONFIG_USB_HS
-                if ((setup->bRequest == 0x06) && (setup->wValue = 0x0600)) {
+                if ((setup->bRequest == 0x06) && (setup->wValue == 0x0600)) {
                     USB_LOG_WRN("Ignore DQD in fs\r\n"); /* Device Qualifier Descriptor */
                     return false;
                 }
@@ -939,30 +950,37 @@ static void usbd_class_event_notify_handler(uint8_t event, void *arg)
     {
         struct usbd_interface *intf = usb_slist_entry(i, struct usbd_interface, list);
 
-        if (intf->notify_handler) {
-            intf->notify_handler(event, arg);
+        if (arg) {
+            struct usb_interface_descriptor *desc = (struct usb_interface_descriptor *)arg;
+            if (intf->notify_handler && (desc->bInterfaceNumber == (intf->intf_num))) {
+                intf->notify_handler(event, arg);
+            }
+        } else {
+            if (intf->notify_handler) {
+                intf->notify_handler(event, arg);
+            }
         }
     }
 }
 
 void usbd_event_connect_handler(void)
 {
-    usbd_class_event_notify_handler(USBD_EVENT_CONNECTED, NULL);
+    usbd_event_handler(USBD_EVENT_CONNECTED);
 }
 
 void usbd_event_disconnect_handler(void)
 {
-    usbd_class_event_notify_handler(USBD_EVENT_DISCONNECTED, NULL);
+    usbd_event_handler(USBD_EVENT_DISCONNECTED);
 }
 
 void usbd_event_resume_handler(void)
 {
-    usbd_class_event_notify_handler(USBD_EVENT_RESUME, NULL);
+    usbd_event_handler(USBD_EVENT_RESUME);
 }
 
 void usbd_event_suspend_handler(void)
 {
-    usbd_class_event_notify_handler(USBD_EVENT_SUSPEND, NULL);
+    usbd_event_handler(USBD_EVENT_SUSPEND);
 }
 
 void usbd_event_reset_handler(void)
@@ -985,6 +1003,7 @@ void usbd_event_reset_handler(void)
     usbd_ep_open(&ep0_cfg);
 
     usbd_class_event_notify_handler(USBD_EVENT_RESET, NULL);
+    usbd_event_handler(USBD_EVENT_RESET);
 }
 
 void usbd_event_ep0_setup_complete_handler(uint8_t *psetup)
@@ -1117,7 +1136,7 @@ void usbd_event_ep_in_complete_handler(uint8_t ep, uint32_t nbytes)
     }
 #else
     tx_msg[ep & 0x7f].nbytes = nbytes;
-    usb_osal_mq_send(usbd_tx_mq, (uint32_t)&tx_msg[ep & 0x7f]);
+    usb_osal_mq_send(usbd_tx_mq, (uintptr_t)&tx_msg[ep & 0x7f]);
 #endif
 }
 
@@ -1129,7 +1148,7 @@ void usbd_event_ep_out_complete_handler(uint8_t ep, uint32_t nbytes)
     }
 #else
     rx_msg[ep & 0x7f].nbytes = nbytes;
-    usb_osal_mq_send(usbd_rx_mq, (uint32_t)&rx_msg[ep & 0x7f]);
+    usb_osal_mq_send(usbd_rx_mq, (uintptr_t)&rx_msg[ep & 0x7f]);
 #endif
 }
 
@@ -1140,7 +1159,7 @@ static void usbdev_tx_thread(void *argument)
     int ret;
 
     while (1) {
-        ret = usb_osal_mq_recv(usbd_tx_mq, (uint32_t *)&msg, 0xffffffff);
+        ret = usb_osal_mq_recv(usbd_tx_mq, (uintptr_t *)&msg, 0xffffffff);
         if (ret < 0) {
             continue;
         }
@@ -1159,7 +1178,7 @@ static void usbdev_rx_thread(void *argument)
     int ret;
 
     while (1) {
-        ret = usb_osal_mq_recv(usbd_rx_mq, (uint32_t *)&msg, 0xffffffff);
+        ret = usb_osal_mq_recv(usbd_rx_mq, (uintptr_t *)&msg, 0xffffffff);
         if (ret < 0) {
             continue;
         }
@@ -1174,8 +1193,11 @@ static void usbdev_rx_thread(void *argument)
 #ifdef CONFIG_USBDEV_ADVANCE_DESC
 void usbd_desc_register(struct usb_descriptor *desc)
 {
+    memset(&usbd_core_cfg, 0, sizeof(struct usbd_core_cfg_priv));
+
     usbd_core_cfg.descriptors = desc;
     usbd_core_cfg.intf_offset = 0;
+
     tx_msg[0].ep = 0x80;
     tx_msg[0].cb = usbd_event_ep0_in_complete_handler;
     rx_msg[0].ep = 0x00;
@@ -1184,8 +1206,11 @@ void usbd_desc_register(struct usb_descriptor *desc)
 #else
 void usbd_desc_register(const uint8_t *desc)
 {
+    memset(&usbd_core_cfg, 0, sizeof(struct usbd_core_cfg_priv));
+
     usbd_core_cfg.descriptors = desc;
     usbd_core_cfg.intf_offset = 0;
+
     tx_msg[0].ep = 0x80;
     tx_msg[0].cb = usbd_event_ep0_in_complete_handler;
     rx_msg[0].ep = 0x00;
@@ -1267,3 +1292,29 @@ int usbd_deinitialize(void)
 #endif
     return 0;
 }
+
+__WEAK void usbd_event_handler(uint8_t event)
+{
+    switch (event) {
+        case USBD_EVENT_RESET:
+            break;
+        case USBD_EVENT_CONNECTED:
+            break;
+        case USBD_EVENT_DISCONNECTED:
+            break;
+        case USBD_EVENT_RESUME:
+            break;
+        case USBD_EVENT_SUSPEND:
+            break;
+        case USBD_EVENT_CONFIGURED:
+            usbd_configure_done_callback();
+            break;
+        case USBD_EVENT_SET_REMOTE_WAKEUP:
+            break;
+        case USBD_EVENT_CLR_REMOTE_WAKEUP:
+            break;
+
+        default:
+            break;
+    }
+}

core/usbd_core.h

@@ -35,8 +35,10 @@ enum usbd_event_type {
     USBD_EVENT_RESUME,       /** USB connection resumed by the HOST */
 
     /* USB DEVICE STATUS */
-    USBD_EVENT_CONFIGURED,    /** USB configuration done */
-    USBD_EVENT_SET_INTERFACE, /** USB interface selected */
+    USBD_EVENT_CONFIGURED,        /** USB configuration done */
+    USBD_EVENT_SET_INTERFACE,     /** USB interface selected */
+    USBD_EVENT_SET_REMOTE_WAKEUP, /** USB set remote wakeup */
+    USBD_EVENT_CLR_REMOTE_WAKEUP, /** USB clear remote wakeup */
     USBD_EVENT_UNKNOWN
 };
 
@@ -93,6 +95,8 @@ void usbd_configure_done_callback(void);
 int usbd_initialize(void);
 int usbd_deinitialize(void);
 
+void usbd_event_handler(uint8_t event);
+
 #ifdef __cplusplus
 }
 #endif

core/usbh_core.c

@@ -412,6 +412,7 @@ int usbh_enumerate(struct usbh_hubport *hport)
 {
     struct usb_interface_descriptor *intf_desc;
     struct usb_setup_packet *setup;
+    struct usb_device_descriptor *dev_desc;
     int dev_addr;
     uint16_t ep_mps;
     int ret;
@@ -435,10 +436,19 @@ int usbh_enumerate(struct usbh_hubport *hport)
     parse_device_descriptor(hport, (struct usb_device_descriptor *)ep0_request_buffer, 8);
 
     /* Extract the correct max packetsize from the device descriptor */
-    ep_mps = ((struct usb_device_descriptor *)ep0_request_buffer)->bMaxPacketSize0;
+    dev_desc = (struct usb_device_descriptor *)ep0_request_buffer;
+    if (dev_desc->bcdUSB >= USB_3_0) {
+        ep_mps = 1 << dev_desc->bMaxPacketSize0;
+    } else {
+        ep_mps = dev_desc->bMaxPacketSize0;
+    }
+
+    USB_LOG_DBG("Device rev=%04x cls=%02x sub=%02x proto=%02x size=%d\r\n",
+                dev_desc->bcdUSB, dev_desc->bDeviceClass, dev_desc->bDeviceSubClass,
+                dev_desc->bDeviceProtocol, ep_mps);
 
     /* Reconfigure EP0 with the correct maximum packet size */
-    usbh_ep0_pipe_reconfigure(hport->ep0, 0, ep_mps, hport->speed);
+    usbh_ep_pipe_reconfigure(hport->ep0, 0, ep_mps, 0);
 
 #ifdef CONFIG_USBHOST_XHCI
     extern int usbh_get_xhci_devaddr(usbh_pipe_t * pipe);
@@ -478,7 +488,7 @@ int usbh_enumerate(struct usbh_hubport *hport)
     hport->dev_addr = dev_addr;
 
     /* And reconfigure EP0 with the correct address */
-    usbh_ep0_pipe_reconfigure(hport->ep0, dev_addr, ep_mps, hport->speed);
+    usbh_ep_pipe_reconfigure(hport->ep0, dev_addr, ep_mps, 0);
 
     /* Read the full device descriptor */
     setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE;
@@ -619,10 +629,6 @@ int usbh_enumerate(struct usbh_hubport *hport)
         hport->config.intf[i].class_driver = class_driver;
         USB_LOG_INFO("Loading %s class driver\r\n", class_driver->driver_name);
         ret = CLASS_CONNECT(hport, i);
-        if (ret < 0) {
-            CLASS_DISCONNECT(hport, i);
-            goto errout;
-        }
     }
 
 errout:
@@ -795,4 +801,4 @@ int lsusb(int argc, char **argv)
     }
 
     return 0;
-}
+}

core/usbh_core.h

@@ -149,6 +149,9 @@ struct usbh_hubport {
     uint8_t *raw_config_desc;
     struct usb_setup_packet *setup;
     struct usbh_hub *parent;
+#ifdef CONFIG_USBHOST_XHCI
+    uint32_t protocol; /* port protocol, for xhci, some ports are USB2.0, others are USB3.0 */
+#endif
 };
 
 struct usbh_hub {

demo/audio_v1_mic_multichan_template.c

@@ -68,7 +68,7 @@ const uint8_t audio_descriptor[] = {
     AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x01, AUDIO_INTERM_MIC, IN_CHANNEL_NUM, INPUT_CH_ENABLE),
     AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x02, 0x01, 0x01, INPUT_CTRL),
     AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x03, AUDIO_TERMINAL_STREAMING, 0x02),
-    AUDIO_AS_DESCRIPTOR_INIT(0x01, 0x03, IN_CHANNEL_NUM, 2, 16, AUDIO_IN_EP, AUDIO_IN_PACKET, EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_FREQ)),
+    AUDIO_AS_DESCRIPTOR_INIT(0x01, 0x03, IN_CHANNEL_NUM, 2, 16, AUDIO_IN_EP, 0x05, AUDIO_IN_PACKET, EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_FREQ)),
     ///////////////////////////////////////
     /// string0 descriptor
     ///////////////////////////////////////
@@ -188,16 +188,19 @@ void audio_init()
     usbd_initialize();
 }
 
-USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[2048];
+USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[AUDIO_IN_PACKET];
 
 void audio_test()
 {
     while (1) {
         if (tx_flag) {
-            memset(write_buffer, 'a', 2048);
+            memset(write_buffer, 'a', AUDIO_IN_PACKET);
             ep_tx_busy_flag = true;
-            usbd_ep_start_write(AUDIO_IN_EP, write_buffer, 2048);
+            usbd_ep_start_write(AUDIO_IN_EP, write_buffer, AUDIO_IN_PACKET);
             while (ep_tx_busy_flag) {
+                if (tx_flag == false) {
+                    break;
+                }
             }
         }
     }

demo/audio_v1_mic_speaker_multichan_template.c

@@ -59,9 +59,9 @@ const uint8_t audio_descriptor[] = {
     AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_TERMINAL_STREAMING, 0x02, 0x0003),
     AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x05, 0x04, 0x01, 0x03, 0x00, 0x00),
     AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x06, AUDIO_OUTTERM_SPEAKER, 0x05),
-    AUDIO_AS_DESCRIPTOR_INIT(0x01, 0x04, 0x02, AUDIO_SPEAKER_FRAME_SIZE_BYTE, AUDIO_SPEAKER_RESOLUTION_BIT, AUDIO_OUT_EP, AUDIO_OUT_PACKET,\
+    AUDIO_AS_DESCRIPTOR_INIT(0x01, 0x04, 0x02, AUDIO_SPEAKER_FRAME_SIZE_BYTE, AUDIO_SPEAKER_RESOLUTION_BIT, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET,\
                              EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_SPEAKER_FREQ)),
-    AUDIO_AS_DESCRIPTOR_INIT(0x02, 0x03, 0x02, AUDIO_MIC_FRAME_SIZE_BYTE, AUDIO_MIC_RESOLUTION_BIT, AUDIO_IN_EP, AUDIO_IN_PACKET,\
+    AUDIO_AS_DESCRIPTOR_INIT(0x02, 0x03, 0x02, AUDIO_MIC_FRAME_SIZE_BYTE, AUDIO_MIC_RESOLUTION_BIT, AUDIO_IN_EP, 0x05, AUDIO_IN_PACKET,\
                              EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_MIC_FREQ)),
     ///////////////////////////////////////
     /// string0 descriptor
@@ -137,7 +137,7 @@ const uint8_t audio_descriptor[] = {
     0x00
 };
 
-USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[2048];
+USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[AUDIO_IN_PACKET];
 USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t out_buffer[AUDIO_OUT_PACKET];
 
 volatile bool tx_flag = 0;
@@ -166,12 +166,6 @@ void usbd_audio_close(uint8_t intf)
     }
 }
 
-#ifdef CONFIG_USB_HS
-#define AUDIO_OUT_EP_MPS 512
-#else
-#define AUDIO_OUT_EP_MPS 64
-#endif
-
 volatile bool ep_tx_busy_flag = false;
 
 void usbd_configure_done_callback(void)
@@ -223,11 +217,14 @@ void audio_test()
 {
     while (1) {
         if (tx_flag) {
-            //            memset(write_buffer, 'a', 2048);
-            //            ep_tx_busy_flag = true;
-            //            usbd_ep_start_write(AUDIO_IN_EP, write_buffer, 2048);
-            //            while (ep_tx_busy_flag) {
-            //            }
+            memset(write_buffer, 'a', AUDIO_IN_PACKET);
+            ep_tx_busy_flag = true;
+            usbd_ep_start_write(AUDIO_IN_EP, write_buffer, AUDIO_IN_PACKET);
+            while (ep_tx_busy_flag) {
+                if (tx_flag == false) {
+                    break;
+                }
+            }
         }
     }
 }

demo/audio_v2_mic_multichan_template.c

@@ -18,8 +18,9 @@
 #define HALF_WORD_BYTES 2  //2 half word (one channel)
 #define SAMPLE_BITS     16 //16 bit per channel
 
+#define BMCONTROL (AUDIO_V2_FU_CONTROL_MUTE | AUDIO_V2_FU_CONTROL_VOLUME)
+
 #define IN_CHANNEL_NUM 2
-#define BMCONTROL      (AUDIO_V2_FU_CONTROL_MUTE | AUDIO_V2_FU_CONTROL_VOLUME)
 
 #if IN_CHANNEL_NUM == 1
 #define INPUT_CTRL      DBVAL(BMCONTROL), DBVAL(BMCONTROL)
@@ -72,7 +73,7 @@ const uint8_t audio_descriptor[] = {
     AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x02, AUDIO_INTERM_MIC, 0x01, IN_CHANNEL_NUM, INPUT_CH_ENABLE, 0x0000),
     AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x03, 0x02, INPUT_CTRL),
     AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_TERMINAL_STREAMING, 0x03, 0x01, 0x0000),
-    AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x04, IN_CHANNEL_NUM, INPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_IN_EP, (AUDIO_IN_PACKET + 4), EP_INTERVAL),
+    AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x04, IN_CHANNEL_NUM, INPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_IN_EP, 0x05, (AUDIO_IN_PACKET + 4), EP_INTERVAL),
     ///////////////////////////////////////
     /// string0 descriptor
     ///////////////////////////////////////

demo/audio_v2_mic_speaker_multichan_template.c

@@ -19,6 +19,8 @@
 #define HALF_WORD_BYTES 2  //2 half word (one channel)
 #define SAMPLE_BITS     16 //16 bit per channel
 
+#define BMCONTROL (AUDIO_V2_FU_CONTROL_MUTE | AUDIO_V2_FU_CONTROL_VOLUME)
+
 #define IN_CHANNEL_NUM 2
 
 #if IN_CHANNEL_NUM == 1
@@ -81,8 +83,6 @@
 #define AUDIO_OUT_PACKET ((uint32_t)((AUDIO_FREQ * HALF_WORD_BYTES * OUT_CHANNEL_NUM) / 1000))
 #define AUDIO_IN_PACKET  ((uint32_t)((AUDIO_FREQ * HALF_WORD_BYTES * IN_CHANNEL_NUM) / 1000))
 
-#define BMCONTROL (AUDIO_V2_FU_CONTROL_MUTE | AUDIO_V2_FU_CONTROL_VOLUME)
-
 #define USB_AUDIO_CONFIG_DESC_SIZ (9 +                                                     \
                                    AUDIO_V2_AC_DESCRIPTOR_INIT_LEN +                       \
                                    AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC +                  \
@@ -118,8 +118,8 @@ uint8_t audio_descriptor[] = {
     AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x06, AUDIO_INTERM_MIC, 0x05, IN_CHANNEL_NUM, INPUT_CH_ENABLE, 0x0000),
     AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x07, 0x06, INPUT_CTRL),
     AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x08, AUDIO_TERMINAL_STREAMING, 0x07, 0x05, 0x0000),
-    AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x02, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_OUT_EP, AUDIO_OUT_PACKET, EP_INTERVAL),
-    AUDIO_V2_AS_DESCRIPTOR_INIT(0x02, 0x08, IN_CHANNEL_NUM, INPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_IN_EP, (AUDIO_IN_PACKET + 4), EP_INTERVAL),
+    AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x02, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, EP_INTERVAL),
+    AUDIO_V2_AS_DESCRIPTOR_INIT(0x02, 0x08, IN_CHANNEL_NUM, INPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_IN_EP, 0x05, (AUDIO_IN_PACKET + 4), EP_INTERVAL),
     ///////////////////////////////////////
     /// string0 descriptor
     ///////////////////////////////////////

demo/audio_v2_speaker_multichan_template.c

@@ -18,6 +18,8 @@
 #define HALF_WORD_BYTES 2  //2 half word (one channel)
 #define SAMPLE_BITS     16 //16 bit per channel
 
+#define BMCONTROL (AUDIO_V2_FU_CONTROL_MUTE | AUDIO_V2_FU_CONTROL_VOLUME)
+
 #define OUT_CHANNEL_NUM 2
 
 #if OUT_CHANNEL_NUM == 1
@@ -48,8 +50,6 @@
 
 #define AUDIO_OUT_PACKET ((uint32_t)((AUDIO_FREQ * HALF_WORD_BYTES * OUT_CHANNEL_NUM) / 1000))
 
-#define BMCONTROL (AUDIO_V2_FU_CONTROL_MUTE | AUDIO_V2_FU_CONTROL_VOLUME)
-
 #define USB_AUDIO_CONFIG_DESC_SIZ (9 +                                                     \
                                    AUDIO_V2_AC_DESCRIPTOR_INIT_LEN +                       \
                                    AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC +                  \
@@ -72,7 +72,7 @@ const uint8_t audio_descriptor[] = {
     AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x02, AUDIO_TERMINAL_STREAMING, 0x01, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, 0x0000),
     AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x03, 0x02, OUTPUT_CTRL),
     AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_OUTTERM_SPEAKER, 0x03, 0x01, 0x0000),
-    AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x02, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_OUT_EP, AUDIO_OUT_PACKET, EP_INTERVAL),
+    AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x02, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, EP_INTERVAL),
     ///////////////////////////////////////
     /// string0 descriptor
     ///////////////////////////////////////

demo/cmsis-dap_v2.1_tempate.c

@@ -227,7 +227,7 @@ void usb_dap_recv_callback(uint8_t ep, uint32_t nbytes)
     }
     actual_len = DAP_ProcessCommand(USB_Request, USB_Response);
 
-    usbd_ep_start_write(DAP_IN_EP, USB_Response, actual_len);
+    usbd_ep_start_write(DAP_IN_EP, USB_Response, actual_len & 0xffff);
     usbd_ep_start_read(ep, USB_Request, DAP_PACKET_SIZE);
 }
 
@@ -281,4 +281,4 @@ void daplink_init(void)
     usbd_add_endpoint(&cdc_in_ep);
 
     usbd_initialize();
-}
+}

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_acmp.h

@@ -1,317 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_acmp.h
-  * @brief   Header file of ACMP module driver.
-  *
-  * @version V1.0
-  * @date    26 Jun 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          26 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_ACMP_H__
-#define __ALD_ACMP_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup ACMP
-  * @{
-  */
-
-/** @defgroup ACMP_Public_Types ACMP Public Types
-  * @{
-  */
-
-/**
-  * @brief ACMP interrupt
-  */
-typedef enum {
-	ACMP_IT_EDGE   = (1U << 0),	/**< Edge interrupt bit */
-	ACMP_IT_WARMUP = (1U << 1),	/**< Warm up interrupt bit */
-} acmp_it_t;
-
-/**
-  * @brief ACMP interrupt flag
-  */
-typedef enum {
-	ACMP_FLAG_EDGE   = (1U << 0),	/**< Edge interrupt flag */
-	ACMP_FLAG_WARMUP = (1U << 1),	/**< Warm up interrupt flag */	
-} acmp_flag_t;
-
-/**
-  * @brief ACMP status flag
-  */
-typedef enum {
-	ACMP_STATUS_ACT = (1U << 0),	/**< Edge status flag */
-	ACMP_STATUS_OUT = (1U << 1),	/**< Warm up status flag */
-} acmp_status_t;
-
-/**
-  * @brief ACMP positive input
-  */
-typedef enum {
-	ACMP_POS_CH0 = 0x0U,	/**< Channel 0 as positive input */
-	ACMP_POS_CH1 = 0x1U,	/**< Channel 1 as positive input */
-	ACMP_POS_CH2 = 0x2U,	/**< Channel 2 as positive input */
-	ACMP_POS_CH3 = 0x3U,	/**< Channel 3 as positive input */
-	ACMP_POS_CH4 = 0x4U,	/**< Channel 4 as positive input */
-	ACMP_POS_CH5 = 0x5U,	/**< Channel 5 as positive input */
-	ACMP_POS_CH6 = 0x6U,	/**< Channel 6 as positive input */
-	ACMP_POS_CH7 = 0x7U,	/**< Channel 7 as positive input */
-} acmp_pos_input_t;
-
-/**
-  * @brief ACMP negative input
-  */
-typedef enum {
-	ACMP_NEG_CH0  = 0x0U, 	/**< Channel 0 as negative input */
-	ACMP_NEG_CH1  = 0x1U, 	/**< Channel 1 as negative input */
-	ACMP_NEG_CH2  = 0x2U, 	/**< Channel 2 as negative input */
-	ACMP_NEG_CH3  = 0x3U, 	/**< Channel 3 as negative input */
-	ACMP_NEG_CH4  = 0x4U, 	/**< Channel 4 as negative input */
-	ACMP_NEG_CH5  = 0x5U, 	/**< Channel 5 as negative input */
-	ACMP_NEG_CH6  = 0x6U, 	/**< Channel 6 as negative input */
-	ACMP_NEG_CH7  = 0x7U, 	/**< Channel 7 as negative input */
-	ACMP_NEG_1V25 = 0x8U, 	/**< 1.25v as negative input */
-	ACMP_NEG_2V5  = 0x9U, 	/**< 2.5v as negative input */
-	ACMP_NEG_VDD  = 0xAU,	/**< VDD as negative input */
-} acmp_neg_input_t;
-
-/**
-  * @brief ACMP mode
-  */
-typedef enum {
-	ACMP_ULTRA_LOW_POWER = 0x0U,	/**< Ultra low power mode */
-	ACMP_LOW_POWER       = 0x1U,	/**< Low power mode */
-	ACMP_MIDDLE_POWER    = 0x2U,	/**< Middle power mode */
-	ACMP_HIGH_POWER      = 0x3U,	/**< High power mode */
-} acmp_mode_t;
-
-/**
-  * @brief ACMP warm-up time
-  */
-typedef enum {
-	ACMP_4_PCLK   = 0x0U,	/**< 4 hfperclk cycles */
-	ACMP_8_PCLK   = 0x1U,	/**< 4 hfperclk cycles */
-	ACMP_16_PCLK  = 0x2U,	/**< 4 hfperclk cycles */
-	ACMP_32_PCLK  = 0x3U,	/**< 4 hfperclk cycles */
-	ACMP_64_PCLK  = 0x4U,	/**< 4 hfperclk cycles */
-	ACMP_128_PCLK = 0x5U,	/**< 4 hfperclk cycles */
-	ACMP_256_PCLK = 0x6U,	/**< 4 hfperclk cycles */
-	ACMP_512_PCLK = 0x7U,	/**< 4 hfperclk cycles */
-} acmp_warm_time_t;
-
-/**
-  * @brief ACMP hysteresis level
-  */
-typedef enum {
-	ACMP_HYST_0  = 0x0U,	/**< No hysteresis */
-	ACMP_HYST_15 = 0x1U,	/**< 15mV hysteresis */
-	ACMP_HYST_22 = 0x2U,	/**< 22mV hysteresis */
-	ACMP_HYST_29 = 0x3U,	/**< 29mV hysteresis */
-	ACMP_HYST_36 = 0x4U,	/**< 36mV hysteresis */
-	ACMP_HYST_43 = 0x5U,	/**< 43mV hysteresis */
-	ACMP_HYST_50 = 0x6U,	/**< 50mV hysteresis */
-	ACMP_HYST_57 = 0x7U,	/**< 57mV hysteresis */
-} acmp_hystsel_t;
-
-/**
-  * @brief ACMP inactive state
-  */
-typedef enum {
-	ACMP_INACTVAL_LOW  = 0x0U,	/**< The inactive value is 0 */
-	ACMP_INACTVAL_HIGH = 0x1U,	/**< The inactive value is 1 */
-} acmp_inactval_t;
-
-/**
-  * @brief which edges set up interrupt
-  */
-typedef enum {
-	ACMP_EDGE_NONE = 0x0U,	/**< Disable EDGE interrupt */
-	ACMP_EDGE_FALL = 0x1U,	/**< Falling edges set EDGE interrupt */
-	ACMP_EDGE_RISE = 0x2U,	/**< rise edges set EDGE interrupt */
-	ACMP_EDGE_ALL  = 0x3U,	/**< Falling edges and rise edges set EDGE interrupt */
-} acmp_edge_t;
-
-/**
-  * @brief ACMP output function
-  */
-typedef enum {
-	ACMP_OUT_DISABLE = 0x0U,	/**< Disable acmp output */
-	ACMP_OUT_ENABLE  = 0x1U,	/**< Enable acmp output */
-} acmp_out_func_t;
-
-/**
-  * @brief ACMP init structure definition
-  */
-typedef struct {
-	acmp_mode_t mode;           	/**< ACMP operation mode */
-	acmp_warm_time_t warm_time; 	/**< ACMP warm up time */
-	acmp_hystsel_t hystsel;     	/**< ACMP hysteresis level */
-	acmp_pos_input_t p_port;  	/**< ACMP positive port select */
-	acmp_neg_input_t n_port;  	/**< ACMP negative port select */
-	acmp_inactval_t inactval;   	/**< ACMP inavtive output value */
-	type_func_t out_inv;		/**< ACMP output inverse */
-	acmp_edge_t edge;           	/**< Select edges to set interrupt flag */
-	uint8_t vdd_level;          	/**< Select scaling factor for CDD reference level, MAX is 63 */
-} acmp_init_t;
-
-/**
-  * @brief  ACMP Handle Structure definition
-  */
-typedef struct acmp_handle_s {
-	ACMP_TypeDef *perh;	/**< Register base address */
-	acmp_init_t init;  	/**< ACMP required parameters */
-	lock_state_t lock; 	/**< Locking object */
-
-	void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg);	/**< ACMP warm-up complete callback */
-	void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg);  	/**< ACMP edge trigger callback */
-} acmp_handle_t;
-/**
-  * @}
-  */
-
-/** @defgroup ACMP_Public_Macros ACMP Public Macros
-  * @{
-  */
-#define ACMP_ENABLE(handle) 	(SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
-#define ACMP_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup ACMP_Private_Macros   ACMP Private Macros
-  * @{
-  */
-#define IS_ACMP_TYPE(x) 		(((x) == ACMP0) || \
-                                         ((x) == ACMP1) || \
-				         ((x) == ACMP2))
-#define IS_ACMP_MODE_TYPE(x)		(((x) == ACMP_ULTRA_LOW_POWER) || \
-					 ((x) == ACMP_LOW_POWER)       || \
-					 ((x) == ACMP_MIDDLE_POWER)    || \
-					 ((x) == ACMP_HIGH_POWER))
-#define IS_ACMP_IT_TYPE(x) 		(((x) == ACMP_IT_EDGE)  || \
-				         ((x) == ACMP_IT_WARMUP))
-#define IS_ACMP_FLAG_TYPE(x) 		(((x) == ACMP_FLAG_EDGE) || \
-				         ((x) == ACMP_FLAG_WARMUP))
-#define IS_ACMP_STATUS_TYPE(x) 	        (((x) == ACMP_STATUS_ACT) || \
-				         ((x) == ACMP_STATUS_OUT))
-#define IS_ACMP_POS_INPUT_TYPE(x) 	(((x) == ACMP_POS_CH0) || \
-				         ((x) == ACMP_POS_CH1) || \
-				         ((x) == ACMP_POS_CH2) || \
-				         ((x) == ACMP_POS_CH3) || \
-				         ((x) == ACMP_POS_CH4) || \
-				         ((x) == ACMP_POS_CH5) || \
-				         ((x) == ACMP_POS_CH6) || \
-				         ((x) == ACMP_POS_CH7))
-#define IS_ACMP_NEG_INPUT_TYPE(x) 	(((x) == ACMP_NEG_CH0)  || \
-				         ((x) == ACMP_NEG_CH1)  || \
-				         ((x) == ACMP_NEG_CH2)  || \
-				         ((x) == ACMP_NEG_CH3)  || \
-				         ((x) == ACMP_NEG_CH4)  || \
-				         ((x) == ACMP_NEG_CH5)  || \
-				         ((x) == ACMP_NEG_CH6)  || \
-				         ((x) == ACMP_NEG_CH7)  || \
-				         ((x) == ACMP_NEG_1V25) || \
-				         ((x) == ACMP_NEG_2V5)  || \
-				         ((x) == ACMP_NEG_VDD))
-#define IS_ACMP_WARM_UP_TIME_TYPE(x)    (((x) == ACMP_4_PCLK)   || \
-				         ((x) == ACMP_8_PCLK)   || \
-				         ((x) == ACMP_16_PCLK)  || \
-				         ((x) == ACMP_32_PCLK)  || \
-				         ((x) == ACMP_64_PCLK)  || \
-				         ((x) == ACMP_128_PCLK) || \
-				         ((x) == ACMP_256_PCLK) || \
-				         ((x) == ACMP_512_PCLK))
-#define IS_ACMP_HYSTSEL_TYPE(x)         (((x) == ACMP_HYST_0)  || \
-				         ((x) == ACMP_HYST_15) || \
-				         ((x) == ACMP_HYST_22) || \
-				         ((x) == ACMP_HYST_29) || \
-				         ((x) == ACMP_HYST_36) || \
-				         ((x) == ACMP_HYST_43) || \
-				         ((x) == ACMP_HYST_50) || \
-				         ((x) == ACMP_HYST_57))
-#define IS_ACMP_INACTVAL_TYPE(x) 	(((x) == ACMP_INACTVAL_LOW) || \
-				         ((x) == ACMP_INACTVAL_HIGH))
-#define IS_ACMP_EDGE_TYPE(x) 	        (((x) == ACMP_EDGE_NONE) || \
-					 ((x) == ACMP_EDGE_FALL) || \
-				         ((x) == ACMP_EDGE_RISE) || \
-					 ((x) == ACMP_EDGE_ALL))
-/**
-  * @}
-  */
-
-/** @addtogroup ACMP_Public_Functions
-  * @{
-  */
-
-/** @addtogroup ACMP_Public_Functions_Group1
-  * @{
-  */
-ald_status_t ald_acmp_init(acmp_handle_t *hperh);
-/**
-  * @}
-  */
-/** @addtogroup ACMP_Public_Functions_Group2
-  * @{
-  */
-void ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state);
-it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it);
-flag_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag);
-flag_status_t ald_acmp_get_mask_flag_status(acmp_handle_t *hperh, acmp_flag_t flag);
-void ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag);
-/**
-  * @}
-  */
-/** @addtogroup ACMP_Public_Functions_Group3
-  * @{
-  */
-void ald_acmp_irq_handler(acmp_handle_t *hperh);
-void ald_acmp_out_config(acmp_handle_t *hperh, type_func_t state);
-uint8_t ald_acmp_out_result(acmp_handle_t *hperh);
-flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#ifdef __cplusplus
-extern "C" }
-#endif
-#endif

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_adc.h

@@ -1,579 +0,0 @@
-/**
-  ******************************************************************************
- * @file    ald_adc.h
- * @brief   Header file of ADC Module library.
- *
- * @version V1.0
- * @date    28 Jun 2019
- * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          28 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
- */
-
-#ifndef __ALD_ADC_H__
-#define __ALD_ADC_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-#include "ald_pis.h"
-#include "ald_timer.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup ADC
-  * @{
-  */
-
-/** @defgroup ADC_Pubulic_Types ADC Pubulic Types
-  * @{
-  */
-
-/**
-  * @brief ADC  State structures definition
-  */
-typedef enum {
-	ADC_STATE_RESET    = 0x0U,	/**< ADC not yet initialized or disabled */
-	ADC_STATE_READY    = 0x1U,	/**< ADC peripheral ready for use */
-	ADC_STATE_BUSY     = 0x2U,	/**< ADC is busy to internal process */
-	ADC_STATE_TIMEOUT  = 0x4U,	/**< TimeOut occurrence */
-	ADC_STATE_ERROR    = 0x8U,	/**< Internal error occurrence */
-	ADC_STATE_BUSY_N   = 0x10U,	/**< Normal channel busy */
-	ADC_STATE_BUSY_I   = 0x20U,	/**< Insert channel busy */
-	ADC_STATE_BUSY_WDG = 0x40U,	/**< Insert channel busy */
-} adc_state_t;
-
-/**
-  *@brief ADC Error Code
-  */
-typedef enum {
-	ADC_ERROR_NONE     = 0x0U,	/**< No error */
-	ADC_ERROR_INTERNAL = 0x1U,	/**< ADC IP internal error*/
-	ADC_ERROR_OVR      = 0x2U,	/**< Overrun error */
-	ADC_ERROR_DMA      = 0x4U, 	/**< DMA transfer error */
-} adc_error_t;
-
-/**
-  *@brief ADC data alignment
-  */
-typedef enum {
-	ADC_DATAALIGN_RIGHT = 0x0U,	/**< ADC data alignment right */
-	ADC_DATAALIGN_LEFT  = 0x1U,	/**< ADC data alignment left */
-} adc_align_t;
-
-/**
-  *@brief ADC config  hannal trigger the EOC IT mode
-  */
-typedef enum {
-	ADC_NCHESEL_MODE_ALL = 0x0U,	/**< ADC set RCHE after convert sequence finish */
-	ADC_NCHESEL_MODE_ONE = 0x1U,	/**< ADC set RCHE after one convert finish */
-} adc_nchesel_t;
-
-/**
-  *@brief  ADC channels
-  */
-typedef enum {
-	ADC_CHANNEL_0  = 0x0U, 	/**< ADC channel 0 */
-	ADC_CHANNEL_1  = 0x1U, 	/**< ADC channel 1 */
-	ADC_CHANNEL_2  = 0x2U, 	/**< ADC channel 2 */
-	ADC_CHANNEL_3  = 0x3U, 	/**< ADC channel 3 */
-	ADC_CHANNEL_4  = 0x4U, 	/**< ADC channel 4 */
-	ADC_CHANNEL_5  = 0x5U, 	/**< ADC channel 5 */
-	ADC_CHANNEL_6  = 0x6U, 	/**< ADC channel 6 */
-	ADC_CHANNEL_7  = 0x7U, 	/**< ADC channel 7 */
-	ADC_CHANNEL_8  = 0x8U, 	/**< ADC channel 8 */
-	ADC_CHANNEL_9  = 0x9U, 	/**< ADC channel 9 */
-	ADC_CHANNEL_10 = 0xAU, 	/**< ADC channel 10 */
-	ADC_CHANNEL_11 = 0xBU, 	/**< ADC channel 11 */
-	ADC_CHANNEL_12 = 0xCU, 	/**< ADC channel 12 */
-	ADC_CHANNEL_13 = 0xDU, 	/**< ADC channel 13 */
-	ADC_CHANNEL_14 = 0xEU, 	/**< ADC channel 14 */
-	ADC_CHANNEL_15 = 0xFU, 	/**< ADC channel 15 */
-	ADC_CHANNEL_16 = 0x10U,	/**< ADC channel 16 */
-	ADC_CHANNEL_17 = 0x11U,	/**< ADC channel 17 */
-	ADC_CHANNEL_18 = 0x12U,	/**< ADC channel 18 */
-} adc_channel_t;
-
-/**
-  *@brief  ADC sampling times
-  */
-typedef enum {
-	ADC_SAMPLETIME_1  = 0x0U,	/**< ADC sampling times 1 clk */
-	ADC_SAMPLETIME_2  = 0x1U,	/**< ADC sampling times 2 clk */
-	ADC_SAMPLETIME_4  = 0x2U,	/**< ADC sampling times 4 clk */
-	ADC_SAMPLETIME_15 = 0x3U,	/**< ADC sampling times 15 clk */
-} adc_samp_t;
-
-/**
-  *@brief   ADC index channel in normal group
-  */
-typedef enum {
-	ADC_NCH_IDX_1  = 0x1U, 	/**< ADC normal channel index 1 */
-	ADC_NCH_IDX_2  = 0x2U, 	/**< ADC normal channel index 2 */
-	ADC_NCH_IDX_3  = 0x3U, 	/**< ADC normal channel index 3 */
-	ADC_NCH_IDX_4  = 0x4U, 	/**< ADC normal channel index 4 */
-	ADC_NCH_IDX_5  = 0x5U, 	/**< ADC normal channel index 5 */
-	ADC_NCH_IDX_6  = 0x6U, 	/**< ADC normal channel index 6 */
-	ADC_NCH_IDX_7  = 0x7U, 	/**< ADC normal channel index 7 */
-	ADC_NCH_IDX_8  = 0x8U, 	/**< ADC normal channel index 8 */
-	ADC_NCH_IDX_9  = 0x9U, 	/**< ADC normal channel index 9 */
-	ADC_NCH_IDX_10 = 0xAU, 	/**< ADC normal channel index 10 */
-	ADC_NCH_IDX_11 = 0xBU, 	/**< ADC normal channel index 11 */
-	ADC_NCH_IDX_12 = 0xCU, 	/**< ADC normal channel index 12 */
-	ADC_NCH_IDX_13 = 0xDU, 	/**< ADC normal channel index 13 */
-	ADC_NCH_IDX_14 = 0xEU, 	/**< ADC normal channel index 14 */
-	ADC_NCH_IDX_15 = 0xFU, 	/**< ADC normal channel index 15 */
-	ADC_NCH_IDX_16 = 0x10U,	/**< ADC normal channel index 16 */
-} adc_nch_idx_t;
-
-/**
-  * @brief ADC index channel in insert group
-  */
-typedef enum {
-	ADC_ICH_IDX_1 = 0x1U,	/**< ADC insert channel index 1 */
-	ADC_ICH_IDX_2 = 0x2U,	/**< ADC insert channel index 2 */
-	ADC_ICH_IDX_3 = 0x3U,	/**< ADC insert channel index 3 */
-	ADC_ICH_IDX_4 = 0x4U,	/**< ADC insert channel index 4 */
-} adc_ich_idx_t;
-
-/**
-  * @brief ADC analog watchdog mode
-  */
-typedef enum {
-	ADC_ANAWTD_NONE       = 0x0U,     	/**< No watch dog */
-	ADC_ANAWTD_SING_NM    = 0x800200U,	/**< One normal channel watch dog */
-	ADC_ANAWTD_SING_IST   = 0x400200U,	/**< One insert channel Injec watch dog */
-	ADC_ANAWTD_SING_NMIST = 0xC00200U,	/**< One normal and insert channel watch dog */
-	ADC_ANAWTD_ALL_NM     = 0x800000U,	/**< All normal channel watch dog */
-	ADC_ANAWTD_ALL_IST    = 0x400000U,	/**< All insert channel watch dog */
-	ADC_ANAWTD_ALL_NMIST  = 0xC00000U,	/**< All normal and insert channel watch dog */
-} adc_ana_wdg_t;
-
-/**
-  * @brief ADC Event type
-  */
-typedef enum {
-	ADC_AWD_EVENT = (1U << 0),	/**< ADC analog watch dog event */
-} adc_event_type_t;
-
-/**
-  * @brief ADC interrupts definition
-  */
-typedef enum {
-	ADC_IT_NCH = (1U << 5), 	/**< ADC it normal */
-	ADC_IT_AWD = (1U << 6), 	/**< ADC it awd */
-	ADC_IT_ICH = (1U << 7), 	/**< ADC it insert */
-	ADC_IT_OVR = (1U << 26),	/**< ADC it overring */
-} adc_it_t;
-
-/**
-  * @brief ADC flags definition
-  */
-typedef enum {
-	ADC_FLAG_AWD  = (1U << 0),	/**<ADC flag awd */
-	ADC_FLAG_NCH  = (1U << 1),	/**<ADC flag normal mode complete */
-	ADC_FLAG_ICH  = (1U << 2),	/**<ADC flag insert mode complete*/
-	ADC_FLAG_OVR  = (1U << 3),	/**<ADC flag ovr */
-	ADC_FLAG_NCHS = (1U << 8),	/**<ADC flag normal start */
-	ADC_FLAG_ICHS = (1U << 9),	/**<ADC flag insert start */
-} adc_flag_t;
-
-/**
-  * @brief ADC CLD DIV definition
-  */
-typedef enum {
-	ADC_CKDIV_1   = 0x0U,	/**< ADC CLK DIV 1 */
-	ADC_CKDIV_2   = 0x1U,	/**< ADC CLK DIV 2 */
-	ADC_CKDIV_4   = 0x2U,	/**< ADC CLK DIV 4 */
-	ADC_CKDIV_8   = 0x3U,	/**< ADC CLK DIV 8 */
-	ADC_CKDIV_16  = 0x4U,	/**< ADC CLK DIV 16 */
-	ADC_CKDIV_32  = 0x5U,	/**< ADC CLK DIV 32 */
-	ADC_CKDIV_64  = 0x6U,	/**< ADC CLK DIV 64 */
-	ADC_CKDIV_128 = 0x7U,	/**< ADC CLK DIV 128 */
-} adc_clk_div_t;
-
-/**
-  * @brief ADC negative reference voltage definition
-  */
-typedef enum {
-	ADC_NEG_REF_VSS   = 0x0U,	/**< ADC negative regerence voltage vss */
-	ADC_NEG_REF_VREFN = 0x1U,	/**< ADC negative regerence voltage vrefn */
-} adc_neg_ref_t;
-
-/**
-  * @brief ADC positive reference voltage definition
-  */
-typedef enum {
-	ADC_POS_REF_VDD        = 0x0U,	/**< ADC positive reference is VDD */
-	ADC_POS_REF_2V         = 0x1U,	/**< ADC positive reference is 2V internal voltage */
-	ADC_POS_REF_VREEFP     = 0x2U,	/**< ADC positive reference is VREEFP */
-	ADC_POS_REF_VREEFP_BUF = 0x3U,	/**< ADC positive reference is VREEFP BUFFER */
-} adc_pos_ref_t;
-
-/**
-  * @brief ADC numbers of normal conversion channals
-  */
-typedef enum {
-	ADC_NCH_NR_1  = 0x0U,	/**< ADC number of normal conversion 1 */
-	ADC_NCH_NR_2  = 0x1U,	/**< ADC number of normal conversion 2 */
-	ADC_NCH_NR_3  = 0x2U,	/**< ADC number of normal conversion 3 */
-	ADC_NCH_NR_4  = 0x3U,	/**< ADC number of normal conversion 4 */
-	ADC_NCH_NR_5  = 0x4U,	/**< ADC number of normal conversion 5 */
-	ADC_NCH_NR_6  = 0x5U,	/**< ADC number of normal conversion 6 */
-	ADC_NCH_NR_7  = 0x6U,	/**< ADC number of normal conversion 7 */
-	ADC_NCH_NR_8  = 0x7U,	/**< ADC number of normal conversion 8 */
-	ADC_NCH_NR_9  = 0x8U,	/**< ADC number of normal conversion 9 */
-	ADC_NCH_NR_10 = 0x9U,	/**< ADC number of normal conversion 10 */
-	ADC_NCH_NR_11 = 0xAU,	/**< ADC number of normal conversion 11 */
-	ADC_NCH_NR_12 = 0xBU,	/**< ADC number of normal conversion 12 */
-	ADC_NCH_NR_13 = 0xCU,	/**< ADC number of normal conversion 13 */
-	ADC_NCH_NR_14 = 0xDU,	/**< ADC number of normal conversion 14 */
-	ADC_NCH_NR_15 = 0xEU,	/**< ADC number of normal conversion 15 */
-	ADC_NCH_NR_16 = 0xFU,	/**< ADC number of normal conversion 16 */
-} adc_nch_nr_t;
-
-/**
-  * @brief ADC numbers of insert conversion channals
-  */
-typedef enum {
-	ADC_ICH_NR_1 = 0x0U,	/**< ADC number of insert conversion 1 */
-	ADC_ICH_NR_2 = 0x1U,	/**< ADC number of insert conversion 2 */
-	ADC_ICH_NR_3 = 0x2U,	/**< ADC number of insert conversion 3 */
-	ADC_ICH_NR_4 = 0x3U,	/**< ADC number of insert conversion 4 */
-} adc_ich_nr_t;
-
-/**
-  * @brief ADC discontinuous mode choose
-  */
-typedef enum {
-	ADC_ALL_DISABLE = 0x0U,	/**< ADC discontinuous mode all disable */
-	ADC_NCH_DISC_EN = 0x1U,	/**< ADC normal channel discontinuous mode enable */
-	ADC_ICH_DISC_EN = 0x2U,	/**< ADC insert channel discontinuous mode enable */
-} adc_disc_mode_t;
-
-/**
-  * @brief ADC numbers of channals in discontinuous conversion mode
-  */
-typedef enum {
-	ADC_DISC_NR_1 = 0x0U,	/**< ADC number of discontinuous conversion 1 */
-	ADC_DISC_NR_2 = 0x1U,	/**< ADC number of discontinuous conversion 2 */
-	ADC_DISC_NR_3 = 0x2U,	/**< ADC number of discontinuous conversion 3 */
-	ADC_DISC_NR_4 = 0x3U,	/**< ADC number of discontinuous conversion 4 */
-	ADC_DISC_NR_5 = 0x4U,	/**< ADC number of discontinuous conversion 5 */
-	ADC_DISC_NR_6 = 0x5U,	/**< ADC number of discontinuous conversion 6 */
-	ADC_DISC_NR_7 = 0x6U,	/**< ADC number of discontinuous conversion 7 */
-	ADC_DISC_NR_8 = 0x7U,	/**< ADC number of discontinuous conversion 8 */
-} adc_disc_nr_t;
-
-/**
-  * @brief ADC resolution of conversion
-  */
-typedef enum {
-	ADC_CONV_BIT_6  = 0x0U,	/**< ADC resolution of conversion 6 */
-	ADC_CONV_BIT_8  = 0x1U,	/**< ADC resolution of conversion 8 */
-	ADC_CONV_BIT_10 = 0x2U,	/**< ADC resolution of conversion 10 */
-	ADC_CONV_BIT_12 = 0x3U,	/**< ADC resolution of conversion 12 */
-} adc_conv_bit_t;
-
-/**
-  * @brief ADC external trigger mode choose
-  */
-typedef enum {
-	ADC_ETS_DISABLE   = 0x0U,	/**< ADC external trigger function disable */
-	ADC_ETS_RISE      = 0x1U,	/**< rise edge trigger ADC */
-	ADC_ETS_FALL      = 0x2U,	/**< fall edge trigger ADC */
-	ADC_ETS_RISE_FALL = 0x3U,	/**< both rise and fall edge trigger ADC */
-} adc_ets_t;
-
-/**
-  * @brief ADC trigger conversion mode
-  */
-
-
-/**
-  * @brief  Structure definition of ADC and normal group initialization
-  */
-typedef struct {
-	adc_align_t align;		/**< Specifies ADC data alignment */
-	type_func_t scan;         	/**< Choose scan mode enable or not */
-	type_func_t cont;       	/**< Choose continuous mode enable or not */
-	adc_nch_nr_t nch_nr;  		/**< Length of normal ranks will be converted */
-	adc_ich_nr_t ich_nr;            /**< Length of insert ranks will be converted */
-	adc_disc_mode_t disc;    	/**< Discontinuous mode enable or not */
-	adc_disc_nr_t disc_nr;		/**< Number of discontinuous conversions channel */
-	adc_conv_bit_t data_bit;   	/**< The precision of conversion */
-	adc_clk_div_t div;		/**< ADCCLK divider */
-	adc_nchesel_t nche_sel;		/**< Trigger the NCHE FALG mode */
-	adc_neg_ref_t n_ref;    	/**< The negative reference voltage*/
-	adc_pos_ref_t p_ref;    	/**< The positive reference voltage*/
-} adc_init_t;
-
-/**
-  * @brief  Structure definition of ADC channel for normal group
-  */
-typedef struct {
-	adc_channel_t ch;	/**< The channel to configure into ADC normal group */
-	adc_nch_idx_t idx;	/**< The rank in the normal group sequencer */
-	adc_samp_t samp;	/**< Sampling time value to be set */
-} adc_nch_conf_t;
-
-/**
-  * @brief  ADC Configuration analog watchdog definition
-  */
-typedef struct {
-	adc_ana_wdg_t mode;	/**< Configures the ADC analog watchdog mode*/
-	adc_channel_t ch;	/**< Selects which ADC channel to monitor by analog watchdog */
-	type_func_t interrupt;	/**< Whether the analog watchdog is configured in interrupt */
-	uint32_t high_thrd;	/**< The ADC analog watchdog High threshold value. */
-	uint32_t low_thrd;	/**< The ADC analog watchdog Low threshold value. */
-} adc_analog_wdg_conf_t;
-
-/**
-  * @brief  ADC Configuration insert Channel structure definition
-  */
-typedef struct {
-	adc_channel_t ch;	/**< Selection of ADC channel to configure */
-	adc_ich_idx_t idx;	/**< Rank in the insert group sequencer */
-	adc_samp_t samp;	/**< Sampling time value for selected channel */
-	uint32_t offset;	/**< The offset about converted data */
-	adc_ich_nr_t nr;	/**< The number of insert ranks */
-	type_func_t auto_m;	/**< insert sequence's auto function */
-} adc_ich_conf_t;
-
-/**
-  * @brief  ADC handle Structure definition
-  */
-typedef struct adc_handle_s {
-	ADC_TypeDef *perh;			/**< Register base address */
-	adc_init_t init;			/**< ADC required parameters */
-
-	dma_handle_t hdma;			/**< Pointer DMA Handler */
-	pis_handle_t hpis;			/**< Pointer PIS Handler for connect adc and dma */
-
-	lock_state_t lock;			/**< ADC locking object */
-	adc_state_t state;			/**< ADC communication state  */
-	adc_error_t error_code;			/**< ADC Error code */
-
-	void (*normal_cplt_cbk)( struct adc_handle_s *arg);  	/**< Regluar Conversion complete callback */
-	void (*insert_cplt_cbk)( struct adc_handle_s *arg);  	/**< insert Conversion complete callback */
-	void (*wdg_cbk)( struct adc_handle_s *arg);		/**< Level out of window callback */
-	void (*error_cbk)(struct adc_handle_s *arg);      	/**< adc error callback */
-	void (*ovr_cbk)(struct adc_handle_s *arg);	      	/**< adc ovr callback */
-} adc_handle_t;
-
-/**
-  * @brief Timer trigger adc config structure definition
-  */
-typedef struct {
-	uint32_t time;		/**< Timer period time uint: us */	
-	uint16_t size;		/**< Adc convert times */	
-	uint16_t *buf;		/**< Convert data buffer */	
-	adc_neg_ref_t n_ref;	/**< The negative reference voltage for adc*/
-	adc_pos_ref_t p_ref;	/**< The positive reference voltage for adc*/
-	adc_channel_t adc_ch;	/**< Adc channel */	
-	uint8_t dma_ch;		/**< Dma channel */	
-	TIMER_TypeDef *p_timer;	/**< Timer peripheral */	
-	ADC_TypeDef *p_adc;	/**< Adc peripheral */	
-	void (*cplt_cbk)( struct adc_handle_s *arg);	/**< Conversion complete callback */
-
-	/* private variable */
-	lock_state_t lock;	/**< Locking object */
-	pis_handle_t h_pis;	/**< Handle of PIS module */
-	dma_handle_t h_dma;	/**< Handle of DMA module */
-	timer_handle_t h_timer;	/**< Handle of TIMER module */
-	adc_handle_t h_adc;	/**< Handle of ADC module */
-	adc_nch_conf_t config;	/**< Struct for chanel configure */
-	adc_ich_conf_t i_config;/**< Struct for insert channel configuration */
-} adc_timer_config_t;
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Public_Macros ADC Public Macros
-  * @{
-  */
-#define ADC_ENABLE(handle) 		(SET_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK))
-#define ADC_DISABLE(handle) 		(CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK))
-#define ADC_NH_TRIG_BY_SOFT(handle)	(SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK))
-#define ADC_IH_TRIG_BY_SOFT(handle)	(SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK))
-#define ADC_RESET_HANDLE_STATE(handle)	((handle)->state = ADC_STATE_RESET)
-#define ADC_VREF_OUT_ENABLE(handle)	(SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))
-#define ADC_VREF_OUT_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))
-#define ADC_NETS_ENABLE(handle, mode)	(MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, (mode) << ADC_CON1_NETS_POSS))
-#define ADC_IETS_ENABLE(handle, mode)	(MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, (mode) << ADC_CON1_IETS_POSS))
-#define ADC_NETS_DISABLE(handle)	(MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, 0 << ADC_CON1_NETS_POSS))
-#define ADC_IETS_DISABLE(handle)	(MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, 0 << ADC_CON1_IETS_POSS))
-#define ADC_SPEED_HIGH_ENABLE(handle)	(SET_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK))
-#define ADC_SPEED_HIGH_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK))
-#define ADC_CALIBRATE_ENABLE(handle)	(SET_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK))
-#define ADC_CALIBRATE_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Private_Macros ADC Private Macros
-  * @{
-  */
-#define IS_ADC_ICH_IDX_TYPE(x)			((x) <= ADC_ICH_IDX_4)
-#define IS_ADC_NCH_IDX_TYPE(x)			((x) <= ADC_NCH_IDX_16)
-#define IS_ADC_SAMPLING_TIMES_TYPE(x)		(((x) == ADC_SAMPLETIME_1) || \
-                                                 ((x) == ADC_SAMPLETIME_2) || \
-					         ((x) == ADC_SAMPLETIME_4) || \
-					         ((x) == ADC_SAMPLETIME_15))
-#define IS_ADC_CHANNELS_TYPE(x)			((x) <= ADC_CHANNEL_18)
-#define IS_ADC_DATA_ALIGN_TYPE(x)		(((x) == ADC_DATAALIGN_RIGHT) || \
-                                                 ((x) == ADC_DATAALIGN_LEFT))
-#define IS_ADC_ANALOG_WTD_MODE_TYPE(x)  	(((x) == ADC_ANAWTD_NONE)       || \
-						 ((x) == ADC_ANAWTD_SING_NM)    || \
-						 ((x) == ADC_ANAWTD_SING_IST)   || \
-						 ((x) == ADC_ANAWTD_SING_NMIST) || \
-						 ((x) == ADC_ANAWTD_ALL_NM)     || \
-						 ((x) == ADC_ANAWTD_ALL_IST)    || \
-						 ((x) == ADC_ANAWTD_ALL_NMIST))
-#define IS_ADC_IT_TYPE(x)			(((x) == ADC_IT_NCH) || \
-						 ((x) == ADC_IT_AWD) || \
-						 ((x) == ADC_IT_ICH) ||  \
-						 ((x) == ADC_IT_OVR ))
-#define IS_ADC_FLAGS_TYPE(x)			(((x) == ADC_FLAG_AWD)  || \
-						 ((x) == ADC_FLAG_NCH)  || \
-						 ((x) == ADC_FLAG_ICH)  || \
-						 ((x) == ADC_FLAG_OVR)  || \
-						 ((x) == ADC_FLAG_NCHS) || \
-						 ((x) == ADC_FLAG_ICHS))
-#define IS_ADC_CLK_DIV_TYPE(x)			(((x) == ADC_CKDIV_1)   || \
-						 ((x) == ADC_CKDIV_2)   || \
-						 ((x) == ADC_CKDIV_4)   || \
-						 ((x) == ADC_CKDIV_8)   || \
-						 ((x) == ADC_CKDIV_16)  || \
-						 ((x) == ADC_CKDIV_32)  || \
-						 ((x) == ADC_CKDIV_64)  || \
-						 ((x) == ADC_CKDIV_128))
-#define IS_ADC_NEG_REF_VOLTAGE_TYPE(x)		(((x) == ADC_NEG_REF_VSS ) || \
-                                                 ((x) == ADC_NEG_REF_VREFN ))
-#define IS_POS_REF_VOLTAGE_TYPE(x)		(((x) == ADC_POS_REF_VDD)    || \
-						 ((x) == ADC_POS_REF_2V) || \
-						 ((x) == ADC_POS_REF_VREEFP) || \
-						 ((x) == ADC_POS_REF_VREEFP_BUF))
-#define IS_ADC_NCH_NR_TYPE(x)			((x) <= ADC_NCH_NR_16)
-#define IS_ADC_ICH_NR_TYPE(x)			((x) <= ADC_ICH_NR_4)
-#define IS_ADC_DISC_NR_TYPE(x)			((x) <= ADC_DISC_NR_8)
-#define IS_ADC_CONV_BIT_TYPE(x)			(((x) == ADC_CONV_BIT_12) || \
-                                                 ((x) == ADC_CONV_BIT_6)  || \
-						 ((x) == ADC_CONV_BIT_8)  || \
-						 ((x) == ADC_CONV_BIT_10))
-#define IS_ADC_TYPE(x) 				(((x) == ADC0) || \
-						 ((x) == ADC1))
-#define IS_ADC_NCHESEL_MODE_TYPE(x)		(((x) == ADC_NCHESEL_MODE_ALL) || \
-						 ((x) == ADC_NCHESEL_MODE_ONE))
-#define IS_ADC_EVENT_TYPE(x)			((x) == ADC_AWD_EVENT)
-#define IS_ADC_IST_OFFSET_TYPE(x)		((x) <= 0xfff)
-#define IS_HTR_TYPE(x)				((x) <= 0xfff)
-#define IS_LTR_TYPE(x)				((x) <= 0xfff)
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Public_Functions
-  * @{
-  */
-
-/** @addtogroup ADC_Public_Functions_Group1
-  * @{
-  */
-ald_status_t ald_adc_init(adc_handle_t *hperh);
-ald_status_t ald_adc_reset(adc_handle_t *hperh);
-void ald_adc_offset_adjust(uint32_t refmv);
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Public_Functions_Group2
-  * @{
-  */
-ald_status_t ald_adc_normal_start(adc_handle_t *hperh);
-ald_status_t ald_adc_normal_stop(adc_handle_t *hperh);
-ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout);
-ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout);
-ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh);
-ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh);
-#ifdef ALD_DMA
-ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel);
-ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel);
-ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config);
-ald_status_t ald_adc_timer_trigger_insert(adc_timer_config_t *config);
-#endif
-uint32_t ald_adc_normal_get_value(adc_handle_t *hperh);
-ald_status_t ald_adc_insert_start(adc_handle_t *hperh);
-ald_status_t ald_adc_insert_stop(adc_handle_t *hperh);
-ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout);
-ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh);
-ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh);
-uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t ih_rank);
-void ald_adc_irq_handler(adc_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Public_Functions_Group3
-  * @{
-  */
-ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config);
-ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config);
-ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config);
-void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state);
-it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it);
-flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag);
-void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag);
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Public_Functions_Group4
-  * @{
-  */
-uint32_t ald_adc_get_state(adc_handle_t *hperh);
-uint32_t ald_adc_get_error(adc_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
- extern "C" }
-#endif
-
-#endif /* __ALD_ADC_H */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_bkpc.h

@@ -1,212 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_bkpc.h
-  * @brief   Header file of BKPC module driver.
-  *
-  * @version V1.0
-  * @date    15 Dec 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          15 Dec 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_BKPC_H__
-#define __ALD_BKPC_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup BKPC
-  * @{
-  */
-
-/** @defgroup BKPC_Public_Macros BKPC Public Macros
-  * @{
-  */
-#define BKPC_LOCK()		(WRITE_REG(BKPC->PROT, 0U))
-#define BKPC_UNLOCK()		(WRITE_REG(BKPC->PROT, 0x9669AA55U))
-#define BKPC_LRC_ENABLE()			\
-do {						\
-	BKPC_UNLOCK();				\
-	SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);	\
-	BKPC_LOCK();				\
-} while (0)
-#define BKPC_LRC_DISABLE()			\
-do {						\
-	BKPC_UNLOCK();				\
-	CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);	\
-	BKPC_LOCK();				\
-} while (0)
-#define BKPC_LOSM_ENABLE()			\
-do {						\
-	BKPC_UNLOCK();				\
-	SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);	\
-	BKPC_LOCK();				\
-} while (0)
-#define BKPC_LOSM_DISABLE()			\
-do {						\
-	BKPC_UNLOCK();				\
-	CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\
-	BKPC_LOCK();				\
-} while (0)
-#define BKPC_LOSC_ENABLE()			\
-do {						\
-	BKPC_UNLOCK();				\
-	SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);	\
-	BKPC_LOCK();				\
-} while (0)
-#define BKPC_LOSC_DISABLE()			\
-do {						\
-	BKPC_UNLOCK();				\
-	CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\
-	BKPC_LOCK();				\
-} while (0)
-
-
-#define BKPC_MRST_WAKEUP_ENABLE()			\
-do {							\
-	BKPC_UNLOCK();					\
-	SET_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK);	\
-	BKPC_LOCK();					\
-} while (0)
-#define BKPC_MRST_WAKEUP_DISABLE()			\
-do {							\
-	BKPC_UNLOCK();					\
-	CLEAR_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK);	\
-	BKPC_LOCK();					\
-} while (0)
-
-/**
-  * @}
-  */
-
-/** @defgroup BKPC_Public_Types BKPC Public Types
-  * @{
-  */
-/**
-  * @brief BKPC preipheral clock select.
-  */
-typedef enum {
-	BKPC_PREH_CLK_LOSM    = 0x0U,	/**< LOSM */
-	BKPC_PREH_CLK_LRC     = 0x1U,	/**< LRC */
-	BKPC_PREH_CLK_HRC_1M  = 0x2U,	/**< HRC down to 1MHz */
-	BKPC_PREH_CLK_HOSC_1M = 0x3U,	/**< HOSC down to 1MHz */
-} bkpc_preh_clk_t;
-
-/**
-  * @brief Standby wakeup port select
-  */
-typedef enum {
-	PMU_STANDBY_PORT_SEL_PA0  = 0x0U,	/**< Wakeup by PA0 */
-	PMU_STANDBY_PORT_SEL_PA1  = 0x1U,	/**< Wakeup by PA1 */
-	PMU_STANDBY_PORT_SEL_PA2  = 0x2U,	/**< Wakeup by PA2 */
-	PMU_STANDBY_PORT_SEL_PA3  = 0x3U,	/**< Wakeup by PA3 */
-	PMU_STANDBY_PORT_SEL_PA4  = 0x4U,	/**< Wakeup by PA4 */
-	PMU_STANDBY_PORT_SEL_PA5  = 0x5U,	/**< Wakeup by PA5 */
-	PMU_STANDBY_PORT_SEL_PA6  = 0x6U,	/**< Wakeup by PA6 */
-	PMU_STANDBY_PORT_SEL_PA7  = 0x7U,	/**< Wakeup by PA7 */
-	PMU_STANDBY_PORT_SEL_NONE = 0xFU,	/**< Wakeup by other source */
-} bkpc_wakeup_port_t;
-
-/**
-  * @brief Standby wakeup level
-  */
-typedef enum {
-	PMU_STANDBY_LEVEL_HIGH = 0x0U,	/**< High level */
-	PMU_STANDBY_LEVEL_LOW  = 0x1U,	/**< Low level */
-} bkpc_wakeup_level_t;
-
-/**
-  * @}
-  */
-
-/**
-  * @defgroup BKPC_Private_Macros BKPC Private Macros
-  * @{
-  */
-#define IS_BKPC_WAKEUP_PORT(x)	(((x) == PMU_STANDBY_PORT_SEL_PA0) || \
-                                 ((x) == PMU_STANDBY_PORT_SEL_PA1) || \
-                                 ((x) == PMU_STANDBY_PORT_SEL_PA2) || \
-                                 ((x) == PMU_STANDBY_PORT_SEL_PA3) || \
-                                 ((x) == PMU_STANDBY_PORT_SEL_PA4) || \
-                                 ((x) == PMU_STANDBY_PORT_SEL_PA5) || \
-                                 ((x) == PMU_STANDBY_PORT_SEL_PA6) || \
-                                 ((x) == PMU_STANDBY_PORT_SEL_PA7) || \
-                                 ((x) == PMU_STANDBY_PORT_SEL_NONE))
-#define IS_BKPC_WAKEUP_LEVEL(x)	(((x) == PMU_STANDBY_LEVEL_HIGH) || \
-                                 ((x) == PMU_STANDBY_LEVEL_LOW))
-#define IS_BKPC_PREH_CLOCK(x)	(((x) == BKPC_PREH_CLK_LOSM) || \
-                                 ((x) == BKPC_PREH_CLK_LRC) || \
-                                 ((x) == BKPC_PREH_CLK_HRC_1M) || \
-                                 ((x) == BKPC_PREH_CLK_HOSC_1M))
-#define IS_BKPC_RAM_IDX(x)	((x) < 32)
-/**
-  * @}
-  */
-
-/** @addtogroup BKPC_Public_Functions
-  * @{
-  */
-/** @addtogroup BKPC_Public_Functions_Group1
-  * @{
-  */
-/* control functions */
-extern void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level);
-extern void ald_bkpc_rtc_clock_config(bkpc_preh_clk_t clock);
-extern void ald_bkpc_tsense_clock_config(bkpc_preh_clk_t clock);
-/**
-  * @}
-  */
-/** @addtogroup BKPC_Public_Functions_Group2
-  * @{
-  */
-/* IO operation functions */
-extern void ald_bkpc_write_ram(uint8_t idx, uint32_t value);
-extern uint32_t ald_bkpc_read_ram(uint8_t idx);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_BKPC_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_calc.h

@@ -1,68 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_calc.h
-  * @brief   Header file of CALC module driver.
-  *
-  * @version V1.0
-  * @date    26 Jun 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          26 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_CALC_H__
-#define __ALD_CALC_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup CALC
-  * @{
-  */
-
-/** @addtogroup CALC_Public_Functions
-  * @{
-  */
-extern uint32_t ald_calc_sqrt(uint32_t data);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_CALC_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_can.h

@@ -1,492 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ald_can.h
-  * @brief   Header file of CAN Module driver.
-  *
-  * @version V1.0
-  * @date    16 Apr 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          16 Apr 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_CAN_H
-#define __ALD_CAN_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup CAN
-  * @{
-  */
-
-/** @defgroup CAN_Public_Types CAN Public Types
-  * @{
-  */
-/**
-  * @brief  ALD State structures definition
-  */
-typedef enum {
-	CAN_STATE_RESET           = 0x00U,	/**< CAN not yet initialized or disabled */
-	CAN_STATE_READY           = 0x01U,	/**< CAN initialized and ready for use */
-	CAN_STATE_BUSY            = 0x02U,	/**< CAN process is ongoing */
-	CAN_STATE_BUSY_TX         = 0x11U,	/**< CAN process is ongoing */
-	CAN_STATE_BUSY_RX0        = 0x21U,	/**< CAN process is ongoing */
-	CAN_STATE_BUSY_RX1        = 0x41U,	/**< CAN process is ongoing */
-	CAN_STATE_BUSY_TX_RX0     = 0x31U,	/**< CAN process is ongoing */
-	CAN_STATE_BUSY_TX_RX1     = 0x51U,	/**< CAN process is ongoing */
-	CAN_STATE_BUSY_RX0_RX1    = 0x61U,	/**< CAN process is ongoing */
-	CAN_STATE_BUSY_TX_RX0_RX1 = 0x71U,	/**< CAN process is ongoing */
-	CAN_STATE_TIMEOUT         = 0x04U,	/**< CAN in Timeout state */
-	CAN_STATE_ERROR           = 0x08U,	/**< CAN error state */
-} can_state_t;
-
-/**
-  * @brief CAN Error Code
-  */
-typedef enum {
-	CAN_ERROR_NONE = 0x00U,		/**< No error */
-	CAN_ERROR_EWG  = 0x01U,		/**< EWG error */
-	CAN_ERROR_EPV  = 0x02U,		/**< EPV error */
-	CAN_ERROR_BOF  = 0x04U,		/**< BOF error */
-	CAN_ERROR_STF  = 0x08U,		/**< Stuff error */
-	CAN_ERROR_FOR  = 0x10U,		/**< Form error */
-	CAN_ERROR_ACK  = 0x20U,		/**< Acknowledgment error */
-	CAN_ERROR_BR   = 0x40U,		/**< Bit recessive */
-	CAN_ERROR_BD   = 0x80U,		/**< LEC dominant */
-	CAN_ERROR_CRC  = 0x100U,	/**< LEC transfer error */
-	CAN_ERROR_UNK  = 0x200U,	/**< Unknown error */
-} can_error_t;
-
-/**
-  * @brief CAN Operating Mode
-  */
- typedef enum {
-	CAN_MODE_NORMAL          =  0x00U,	/**< Normal mode */
-	CAN_MODE_LOOPBACK        =  0x01U,	/**< Loopback mode */
-	CAN_MODE_SILENT          =  0x02U,	/**< Silent mode */
-	CAN_MODE_SILENT_LOOPBACK =  0x03U,  	/**< Loopback combined with silent mode */
-} can_operate_mode_t;
-
-/**
-  * @brief CAN Synchronization Jump Width
-  */
-typedef enum {
-	CAN_SJW_1 = 0x0U,	/**< 1 time quantum */
-	CAN_SJW_2 = 0x1U,	/**< 2 time quantum */
-	CAN_SJW_3 = 0x2U,	/**< 3 time quantum */
-	CAN_SJW_4 = 0x3U,	/**< 4 time quantum */
-} can_sjw_t;
-
-/**
-  * @brief CAN Time Quantum in Bit Segment 1
-  */
-typedef enum {
-	CAN_SEG1_1  = 0x0U,	/**< 1 time quantum */
-	CAN_SEG1_2  = 0x1U,	/**< 2 time quantum */
-	CAN_SEG1_3  = 0x2U,	/**< 3 time quantum */
-	CAN_SEG1_4  = 0x3U,	/**< 4 time quantum */
-	CAN_SEG1_5  = 0x4U,	/**< 5 time quantum */
-	CAN_SEG1_6  = 0x5U,	/**< 6 time quantum */
-	CAN_SEG1_7  = 0x6U,	/**< 7 time quantum */
-	CAN_SEG1_8  = 0x7U,	/**< 8 time quantum */
-	CAN_SEG1_9  = 0x8U,	/**< 9 time quantum */
-	CAN_SEG1_10 = 0x9U,	/**< 10 time quantum */
-	CAN_SEG1_11 = 0xAU,	/**< 11 time quantum */
-	CAN_SEG1_12 = 0xBU,	/**< 12 time quantum */
-	CAN_SEG1_13 = 0xCU,	/**< 13 time quantum */
-	CAN_SEG1_14 = 0xDU,	/**< 14 time quantum */
-	CAN_SEG1_15 = 0xEU,	/**< 15 time quantum */
-	CAN_SEG1_16 = 0xFU,	/**< 16 time quantum */
-} can_seg1_t;
-
-/**
-  * @brief CAN Time Quantum in Bit Segment 2
-  */
-typedef enum {
-	CAN_SEG2_1 = 0x0U,	/**< 1 time quantum */
-	CAN_SEG2_2 = 0x1U,     	/**< 2 time quantum */
-	CAN_SEG2_3 = 0x2U,     	/**< 3 time quantum */
-	CAN_SEG2_4 = 0x3U,     	/**< 4 time quantum */
-	CAN_SEG2_5 = 0x4U,     	/**< 5 time quantum */
-	CAN_SEG2_6 = 0x5U,     	/**< 6 time quantum */
-	CAN_SEG2_7 = 0x6U,     	/**< 7 time quantum */
-	CAN_SEG2_8 = 0x7U,     	/**< 8 time quantum */
-} can_seg2_t;
-
-/**
-  * @brief CAN Filter Mode
-  */
-typedef enum {
-	CAN_FILTER_MODE_MASK = 0x0U,	/**< Identifier mask mode */
-	CAN_FILTER_MODE_LIST = 0x1U,	/**< Identifier list mode */
-} can_filter_mode_t;
-
-/**
-  * @brief CAN Filter Scale
-  */
-typedef enum {
-	CAN_FILTER_SCALE_16 = 0x0U,	/**< Two 16-bit filters */
-	CAN_FILTER_SCALE_32 = 0x1U,	/**< One 32-bit filter */
-} can_filter_scale_t;
-
-/**
-  * @brief CAN Filter fifo
-  */
-typedef enum {
-	CAN_FILTER_FIFO0 = 0x0U,	/**< FIFO 0 assignment for filter */
-	CAN_FILTER_FIFO1 = 0x1U,	/**< FIFO 1 assignment for filter */
-} can_filter_fifo_t;
-
-/**
-  * @brief CAN Identifier Type
-  */
-typedef enum {
-	CAN_ID_STD = 0x0U,	/**< Standard Id */
-	CAN_ID_EXT = 0x1U,	/**< Extended Id */
-} can_id_type_t;
-
-/**
-  * @brief CAN Remote Transmission Request
-  */
-typedef enum {
-	CAN_RTR_DATA   = 0x0U,	/**< Data frame */
-	CAN_RTR_REMOTE = 0x1U, 	/**< Remote frame */
-} can_remote_req_t;
-
-/**
-  * @brief CAN Transmit Constants
-  */
-typedef enum {
-	CAN_TX_MAILBOX_0    = 0x0U,	/**< TX mailbox index 0 */
-	CAN_TX_MAILBOX_1    = 0x1U,	/**< TX mailbox index 1 */
-	CAN_TX_MAILBOX_2    = 0x2U,	/**< TX mailbox index 2 */
-	CAN_TX_MAILBOX_NONE = 0x3U,	/**< MailBox can't be used */
-} can_tx_mailbox_t;
-
-/**
-  * @brief  CAN Receive fifo Number
-  */
-typedef enum {
-	CAN_RX_FIFO0 = 0x0U,	/**< CAN fifo 0 used to receive */
-	CAN_RX_FIFO1 = 0x1U,	/**< CAN fifo 1 used to receive */
-} can_rx_fifo_t;
-
-/**
-  * @brief  CAN Flags
-  */
-typedef enum {
-	CAN_FLAG_SLPS   = (1U << 1),			/**< Sleep acknowledge flag */
-	CAN_FLAG_ERR    = (1U << 2),			/**< Error flag*/
-	CAN_FLAG_WK     = (1U << 3),			/**< Wake up flag */
-	CAN_FLAG_SLP    = (1U << 4),			/**< Sleep acknowledge flag */
-	CAN_FLAG_M0REQC = (1U << 20) | (1U << 0),	/**< Request MailBox0 flag */
-	CAN_FLAG_M0TXC  = (1U << 20) | (1U << 1),	/**< Transmission OK MailBox0 flag */
-	CAN_FLAG_M1REQC = (1U << 20) | (1U << 8),	/**< Request MailBox1 flag */
-	CAN_FLAG_M1TXC  = (1U << 20) | (1U << 9),	/**< Transmission OK MailBox1 flag */
-	CAN_FLAG_M2REQC = (1U << 20) | (1U << 16),	/**< Request MailBox2 flag */
-	CAN_FLAG_M2TXC  = (1U << 20) | (1U << 17),	/**< Transmission OK MailBox2 flag */
-	CAN_FLAG_TXM0   = (1U << 20) | (1U << 26),	/**< Transmit mailbox 0 empty flag */
-	CAN_FLAG_TXM1   = (1U << 20) | (1U << 27),	/**< Transmit mailbox 1 empty flag */
-	CAN_FLAG_TXM2   = (1U << 20) | (1U << 28),	/**< Transmit mailbox 2 empty flag */
-	CAN_FLAG_FF0    = (2U << 20) | (1U << 3),	/**< FIFO 0 Full flag */
-	CAN_FLAG_FOV0   = (2U << 20) | (1U << 4),	/**< FIFO 0 Overrun flag */
-	CAN_FLAG_FF1    = (3U << 20) | (1U << 3),	/**< FIFO 1 Full flag */
-	CAN_FLAG_FOV1   = (3U << 20) | (1U << 4),	/**< FIFO 1 Overrun flag */
-	CAN_FLAG_WARN   = (4U << 20) | (1U << 0),	/**< Error warning flag */
-	CAN_FLAG_PERR   = (4U << 20) | (1U << 1),	/**< Error passive flag */
-	CAN_FLAG_BOF    = (4U << 20) | (1U << 2),	/**< Bus-Off flag */
-} can_flag_t;
-
-/**
-  * @brief CAN Interrupts
-  */
-typedef enum {
-	CAN_IT_TXM   = (1U << 0),	/**< Transmit mailbox empty interrupt bit */
-	CAN_IT_FP0   = (1U << 1),	/**< FIFO0 message pending interrupt bit */
-	CAN_IT_FF0   = (1U << 2),	/**< FIFO0 full interrupt bit */
-	CAN_IT_FOV0  = (1U << 3),	/**< FIFO0 overrun interrupt bit */
-	CAN_IT_FP1   = (1U << 4),	/**< FIFO1 message pending interrupt bit */
-	CAN_IT_FF1   = (1U << 5),	/**< FIFO1 full interrupt bit */
-	CAN_IT_FOV1  = (1U << 6),	/**< FIFO1 overrun interrupt bit */
-	CAN_IT_WARN  = (1U << 8),	/**< Error warning interrupt bit */
-	CAN_IT_PERR  = (1U << 9),	/**< Error passive interrupt bit */
-	CAN_IT_BOF   = (1U << 10),	/**< Bus-off interrupt bit */
-	CAN_IT_PRERR = (1U << 11),	/**< Last error code interrupt bit */
-	CAN_IT_ERR   = (1U << 15),	/**< Error interrupt bit */
-	CAN_IT_WK    = (1U << 16),	/**< wake-up interrupt bit */
-	CAN_IT_SLP   = (1U << 17),	/**< sleep interrupt bit */
-} can_it_t;
-
-/**
-  * @brief CAN filter configuration structure definition
-  */
-typedef struct {
-	uint32_t id_high;		/**< Specifies the filter identification number */
-	uint32_t id_low;		/**< Specifies the filter identification number */
-	uint32_t mask_id_high;		/**< Specifies the filter mask number or identification number */
-	uint32_t mask_id_low;		/**< Specifies the filter mask number or identification number */
-	can_filter_fifo_t fifo;		/**< Specifies the fifo (0 or 1) which will be assigned to the filter. */
-	uint32_t number;		/**< Specifies the filter which will be initialized. */
-	can_filter_mode_t mode;		/**< Specifies the filter mode to be initialized. */
-	can_filter_scale_t scale;	/**< Specifies the filter scale. */
-	type_func_t active;		/**< Enable or disable the filter. */
-} can_filter_t;
-
-/**
-  * @brief CAN init structure definition
-  */
-typedef struct {
-	uint32_t psc;			/**< Specifies the length of a time quantum. */
-	can_operate_mode_t mode;	/**< Specifies the CAN operating mode. */
-	can_sjw_t sjw;			/**< Specifies the maximum number of time quanta the CAN hardware is
-	                                       allowed to lengthen or shorten a bit to perform resynchronization. */
-	can_seg1_t seg1;		/**< Specifies the number of time quanta in Bit Segment 1. */
-	can_seg2_t seg2;		/**< Specifies the number of time quanta in Bit Segment 2. */
-	type_func_t ttcm;		/**< Enable or disable the time triggered communication mode. */
-	type_func_t abom;		/**< Enable or disable the automatic bus-off management. */
-	type_func_t awk;		/**< Enable or disable the automatic wake-up mode. */
-	type_func_t artx;		/**< Enable or disable the non-automatic retransmission mode. */
-	type_func_t rfom;		/**< Enable or disable the Receive fifo Locked mode. */
-	type_func_t txmp;		/**< Enable or disable the transmit fifo priority. */
-} can_init_t;
-
-/**
-  * @brief CAN Tx message structure definition
-  */
-typedef struct {
-	uint32_t std;		/**< Specifies the standard identifier. */
-	uint32_t ext;		/**< Specifies the extended identifier. */
-	can_id_type_t type;	/**< Specifies the type of identifier for the message that will be transmitted. */
-	can_remote_req_t rtr;	/**< Specifies the type of frame for the message that will be transmitted. */
-	uint32_t len;		/**< Specifies the length of the frame that will be transmitted. */
-	uint8_t data[8];	/**< Contains the data to be transmitted. */
-} can_tx_msg_t;
-
-/**
-  * @brief CAN Rx message structure definition
-  */
-typedef struct {
-	uint32_t std;		/**< Specifies the standard identifier. */
-	uint32_t ext;		/**< Specifies the extended identifier. */
-	can_id_type_t type;	/**< Specifies the type of identifier for the message that will be received. */
-	can_remote_req_t rtr;	/**< Specifies the type of frame for the received message. */
-	uint32_t len;		/**< Specifies the length of the frame that will be received. */
-	uint8_t data[8];	/**< Contains the data to be received. */
-	uint32_t fmi;		/**< Specifies the index of the filter the message stored in the mailbox passes through. */
-	can_rx_fifo_t num;	/**< Specifies the receive fifo number. */
-} can_rx_msg_t;
-
-/**
-  * @brief CAN handle Structure definition
-  */
-typedef struct can_handle_s {
-	CAN_TypeDef *perh;	/**< Register base address */
-	can_init_t init;	/**< CAN required parameters */
-	can_rx_msg_t *rx0_msg;	/**< Pointer to receive message from FIFO0 */
-	can_rx_msg_t *rx1_msg;	/**< Pointer to receive message from FIFO1 */
-	lock_state_t lock;	/**< CAN locking object */
-	can_state_t state;	/**< CAN communication state */
-	can_error_t err;	/**< CAN Error code */
-
-	void (*tx_cplt_cbk)(struct can_handle_s *arg);				/**< Tx completed callback */
-	void (*rx_cplt_cbk)(struct can_handle_s *arg, can_rx_fifo_t num);	/**< Rx completed callback */
-	void (*error_cbk)(struct can_handle_s *arg);				/**< error callback */
-} can_handle_t;
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Public_Macro CAN Public Macros
-  * @{
-  */
-#define CAN_RESET_HANDLE_STATE(x)	((x)->state = CAN_STATE_RESET)
-#define CAN_RX_MSG_PENDING(x, y)	(((y) == CAN_RX_FIFO0) ? \
-	(READ_BIT((x)->perh->RXF0, CAN_RXF0_PEND_MSK)) : (READ_BIT((x)->perh->RXF1, CAN_RXF1_PEND_MSK)))
-#define CAN_DBG_FREEZE(x, y)	(MODIFY_REG((x)->perh->CON, CAN_CON_DBGSTP_MSK, (y) << CAN_CON_DBGSTP_POS))
-#define CAN_TX_STAMP_ENABLE(x, y)	(SET_BIT((x)->perh->TxMailBox[(y)].TXFCON, CAN_TXFCON0_TXGT_MSK))
-#define CAN_TX_STAMP_DISABLE(x, y)	(CLEAR_BIT((x)->perh->TxMailBox[(y)].TXFCON, CAN_TXFCON0_TXGT_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Private_Macros CAN Private Macros
-  * @{
-  */
-#define IS_CAN_ALL(x)	((x) == CAN0)
-#define IS_CAN_FILTER_NUMBER(x) ((x) <= 13)
-#define IS_CAN_MODE(x)	(((x) == CAN_MODE_NORMAL)   || \
-                         ((x) == CAN_MODE_LOOPBACK) || \
-                         ((x) == CAN_MODE_SILENT)   || \
-                         ((x) == CAN_MODE_SILENT_LOOPBACK))
-#define IS_CAN_SJW(x)	(((x) == CAN_SJW_1) || \
-                         ((x) == CAN_SJW_2) || \
-                         ((x) == CAN_SJW_3) || \
-                         ((x) == CAN_SJW_4))
-#define IS_CAN_BS1(x)	((x) <= CAN_SEG1_16)
-#define IS_CAN_BS2(x)	((x) <= CAN_SEG2_8)
-#define IS_CAN_FILTER_MODE(x)	(((x) == CAN_FILTER_MODE_MASK) || \
-                                 ((x) == CAN_FILTER_MODE_LIST))
-#define IS_CAN_FILTER_SCALE(x)	(((x) == CAN_FILTER_SCALE_16) || \
-                                 ((x) == CAN_FILTER_SCALE_32))
-#define IS_CAN_FILTER_FIFO(x)	(((x) == CAN_FILTER_FIFO0) || \
-                                 ((x) == CAN_FILTER_FIFO1))
-#define IS_CAN_IDTYPE(x)	(((x) == CAN_ID_STD) || \
-                                 ((x) == CAN_ID_EXT))
-#define IS_CAN_RTR(x)	(((x) == CAN_RTR_DATA) || ((x) == CAN_RTR_REMOTE))
-#define IS_CAN_FIFO(x)	(((x) == CAN_RX_FIFO0) || ((x) == CAN_RX_FIFO1))
-#define IS_CAN_TX_MAILBOX(x)	((x) <= CAN_TX_MAILBOX_NONE)
-#define IS_CAN_STDID(x)		((x) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(x)		((x) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DATA_LEN(x)	((x) <= ((uint8_t)0x08))
-#define IS_CAN_PRESCALER(x)	(((x) >= 1) && ((x) <= 1024))
-#define IS_CAN_GET_FLAG(x)	(((x)  == CAN_FLAG_SLPS)   || \
-                                  ((x) == CAN_FLAG_ERR)    || \
-                                  ((x) == CAN_FLAG_WK)     || \
-                                  ((x) == CAN_FLAG_SLP)    || \
-                                  ((x) == CAN_FLAG_M0REQC) || \
-                                  ((x) == CAN_FLAG_M0TXC)  || \
-                                  ((x) == CAN_FLAG_M1REQC) || \
-                                  ((x) == CAN_FLAG_M1TXC)  || \
-                                  ((x) == CAN_FLAG_M2REQC) || \
-                                  ((x) == CAN_FLAG_M2TXC)  || \
-                                  ((x) == CAN_FLAG_TXM0)   || \
-                                  ((x) == CAN_FLAG_TXM1)   || \
-                                  ((x) == CAN_FLAG_TXM2)   || \
-                                  ((x) == CAN_FLAG_FF0)    || \
-                                  ((x) == CAN_FLAG_FOV0)   || \
-                                  ((x) == CAN_FLAG_FF1)    || \
-                                  ((x) == CAN_FLAG_FOV1)   || \
-                                  ((x) == CAN_FLAG_WARN)   || \
-                                  ((x) == CAN_FLAG_PERR)   || \
-                                  ((x) == CAN_FLAG_BOF))
-#define IS_CAN_CLEAR_FLAG(x)	(((x)  == CAN_FLAG_ERR)    || \
-                                  ((x) == CAN_FLAG_WK)     || \
-                                  ((x) == CAN_FLAG_SLP)    || \
-                                  ((x) == CAN_FLAG_M0REQC) || \
-                                  ((x) == CAN_FLAG_M1REQC) || \
-                                  ((x) == CAN_FLAG_M2REQC) || \
-                                  ((x) == CAN_FLAG_FF0)    || \
-                                  ((x) == CAN_FLAG_FOV0)   || \
-                                  ((x) == CAN_FLAG_FF1)    || \
-                                  ((x) == CAN_FLAG_FOV1))
-#define IS_CAN_IT(x)		(((x)  == CAN_IT_TXM)   || \
-                                  ((x) == CAN_IT_FP0) || \
-                                  ((x) == CAN_IT_FF0) || \
-                                  ((x) == CAN_IT_FOV0) || \
-                                  ((x) == CAN_IT_FP1) || \
-                                  ((x) == CAN_IT_FF1)   || \
-                                  ((x) == CAN_IT_FOV1)  || \
-                                  ((x) == CAN_IT_WARN)   || \
-				  ((x) == CAN_IT_PERR) || \
-                                  ((x) == CAN_IT_BOF) || \
-                                  ((x) == CAN_IT_PRERR) || \
-                                  ((x) == CAN_IT_ERR)   || \
-                                  ((x) == CAN_IT_WK)  || \
-                                  ((x) == CAN_IT_SLP))
-#define CAN_TIMEOUT_VALUE	100
-#define CAN_STATE_TX_MASK	(1U << 4)
-#define CAN_STATE_RX0_MASK	(1U << 5)
-#define CAN_STATE_RX1_MASK	(1U << 6)
-
-/**
-  * @}
-  */
-
-/** @addtogroup CAN_Public_Functions
-  * @{
-  */
-
-/** @addtogroup CAN_Public_Functions_Group1
-  *  @{
-  */
-/* Initialization functions */
-void ald_can_reset(can_handle_t *hperh);
-ald_status_t ald_can_init(can_handle_t *hperh);
-ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config);
-/**
-  * @}
-  */
-
-/** @addtogroup CAN_Public_Functions_Group2
-  * @{
-  */
-/* IO operation functions */
-ald_status_t ald_can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout);
-ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg);
-ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout);
-ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg);
-/**
-  * @}
-  */
-
-/** @addtogroup CAN_Public_Functions_Group3
-  * @{
-  */
-/* Control function */
-ald_status_t ald_can_sleep(can_handle_t *hperh);
-ald_status_t ald_can_wake_up(can_handle_t *hperh);
-void ald_can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box);
-void ald_can_irq_handler(can_handle_t *hperh);
-type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box);
-void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state);
-it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it);
-flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag);
-void ald_can_clear_flag_status(can_handle_t *hperh, can_flag_t flag);
-/**
-  * @}
-  */
-
-/** @addtogroup CAN_Public_Functions_Group4
-  * @{
-  */
-/* State and Error functions */
-can_state_t ald_can_get_state(can_handle_t *hperh);
-can_error_t ald_can_get_error(can_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_CAN_H */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_cmu.h

@@ -1,805 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_cmu.h
-  * @brief   Header file of CMU module driver.
-  *
-  * @version V1.0
-  * @date    22 Nov 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          22 Nov 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_CMU_H__
-#define __ALD_CMU_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_syscfg.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup CMU
-  * @{
-  */
-
-/** @defgroup CMU_Public_Macros CMU Public Macros
-  * @{
-  */
-#define CMU_HRC_SEL_BY_SW()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->CFGR, CMU_CFGR_HRCFCS_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_HRC_SEL_BY_CFGW()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFCS_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_HRC_DIV_1MHZ_ENABLE()			\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC1MEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_HRC_DIV_1MHZ_DISABLE()			\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HRC1MEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_HOSC_DIV_1MHZ_ENABLE()			\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSC1MEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_HOSC_DIV_1MHZ_DISABLE()			\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSC1MEN_MSK);\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LOSC_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LOSC_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LRC_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LRC_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_ULRC_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_ULRC_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-
-/* Low power mode control */
-#define CMU_LP_LRC_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LP_LRC_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LP_LOSC_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LP_LOSC_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LP_HRC_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LP_HRC_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LP_HOSC_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define CMU_LP_HOSC_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-/**
-  * @}
-  */
-
-
-/** @defgroup CMU_Public_Types CMU Public Types
-  * @{
-  */
-/**
-  * @brief CMU state structure definition
-  */
-typedef	enum {
-	CMU_CLOCK_HRC  = 0x1U,	/**< HRC */
-	CMU_CLOCK_LRC  = 0x2U,	/**< LRC */
-	CMU_CLOCK_LOSC = 0x3U,	/**< LOSC */
-	CMU_CLOCK_PLL1 = 0x4U,	/**< PLL1 */
-	CMU_CLOCK_HOSC = 0x5U,	/**< HOSC */
-} cmu_clock_t;
-
-/**
-  * @brief PLL1 output clock
-  */
-typedef enum {
-	CMU_PLL1_OUTPUT_36M = 0x0U,	/**< x9  (36MHz) */
-	CMU_PLL1_OUTPUT_48M = 0x1U,	/**< x12 (48MHz) */
-#if defined(ES32F36xx) || defined(ES32F39xx)
-	CMU_PLL1_OUTPUT_72M = 0x2U,	/**< x18 (72MHz) */
-	CMU_PLL1_OUTPUT_96M = 0x3U,	/**< x24 (96MHz) */
-#endif
-} cmu_pll1_output_t;
-
-/**
-  * @brief PLL1 referance clock
-  */
-typedef enum {
-	CMU_PLL1_INPUT_HRC_6  = 0x0U,	/**< HRC  / 6 */
-	CMU_PLL1_INPUT_PLL2   = 0x1U,	/**< PLL2 */
-	CMU_PLL1_INPUT_HOSC   = 0x2U,	/**< HOSC / 1 */
-	CMU_PLL1_INPUT_HOSC_2 = 0x3U,	/**< HOSC / 2 */
-	CMU_PLL1_INPUT_HOSC_3 = 0x4U,	/**< HOSC / 3 */
-	CMU_PLL1_INPUT_HOSC_4 = 0x5U,	/**< HOSC / 4 */
-	CMU_PLL1_INPUT_HOSC_5 = 0x6U,	/**< HOSC / 5 */
-	CMU_PLL1_INPUT_HOSC_6 = 0x7U,	/**< HOSC / 6 */
-} cmu_pll1_input_t;
-
-/**
-  * @brief HOSC range
-  */
-typedef enum {
-	CMU_HOSC_2M  = 0x0U,	/**< 0~2MHz */
-	CMU_HOSC_4M  = 0x1U,	/**< 2~4MHz */
-	CMU_HOSC_8M  = 0x2U,	/**< 4~8MHz */
-	CMU_HOSC_16M = 0x3U,	/**< 8~16MHz */
-	CMU_HOSC_24M = 0x4U,	/**< 16~24MHz */
-} cmu_hosc_range_t;
-
-/**
-  * @brief Safe clock source type
-  */
-typedef enum {
-	CMU_SAFE_CLK_HOSC = 0x0U,	/**< HOSC */
-	CMU_SAFE_CLK_LOSC = 0x1U,	/**< LOSC */
-	CMU_SAFE_CLK_PLL  = 0x2U,	/**< PLL */
-} cmu_clock_safe_type_t;
-
-/**
-  * @brief Frequency division select bit
-  */
-typedef enum {
-	CMU_DIV_1    = 0x0U,	/**< Division by 1 */
-	CMU_DIV_2    = 0x1U,	/**< Division by 2 */
-	CMU_DIV_4    = 0x2U,	/**< Division by 4 */
-	CMU_DIV_8    = 0x3U,	/**< Division by 8 */
-	CMU_DIV_16   = 0x4U,	/**< Division by 16 */
-	CMU_DIV_32   = 0x5U,	/**< Division by 32 */
-	CMU_DIV_64   = 0x6U,	/**< Division by 64 */
-	CMU_DIV_128  = 0x7U,	/**< Division by 128 */
-	CMU_DIV_256  = 0x8U,	/**< Division by 256 */
-	CMU_DIV_512  = 0x9U,	/**< Division by 512 */
-	CMU_DIV_1024 = 0xAU,	/**< Division by 1024 */
-	CMU_DIV_2048 = 0xBU,	/**< Division by 2048 */
-	CMU_DIV_4096 = 0xCU,	/**< Division by 4096 */
-} cmu_div_t;
-
-/**
-  * @brief Bus type
-  */
-typedef enum {
-	CMU_HCLK_1 = 0x0U,	/**< AHB1 bus */
-	CMU_HCLK_2 = 0x1U,	/**< AHB2 bus */
-	CMU_SYS    = 0x2U,	/**< SYS bus */
-	CMU_PCLK_1 = 0x3U,	/**< APB1 bus */
-	CMU_PCLK_2 = 0x4U,	/**< APB2 bus */
-} cmu_bus_t;
-
-/**
-  * @brief Output high clock select
-  */
-typedef enum {
-	CMU_OUTPUT_HIGH_SEL_HOSC   = 0x0U,	/**< Select HOSC */
-	CMU_OUTPUT_HIGH_SEL_LOSC   = 0x1U,	/**< Select LOSC */
-	CMU_OUTPUT_HIGH_SEL_HRC    = 0x2U,	/**< Select HRC */
-	CMU_OUTPUT_HIGH_SEL_LRC    = 0x3U,	/**< Select LRC */
-	CMU_OUTPUT_HIGH_SEL_HOSM   = 0x4U,	/**< Select HOSM */
-	CMU_OUTPUT_HIGH_SEL_PLL1   = 0x5U,	/**< Select PLL1 */
-	CMU_OUTPUT_HIGH_SEL_PLL2   = 0x6U,	/**< Select PLL2 */
-	CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7U,	/**< Select SYSCLK */
-} cmu_output_high_sel_t;
-
-/**
-  * @brief Output frequency division
-  */
-typedef enum {
-	CMU_OUTPUT_DIV_1   = 0x0U,	/**< Division by 1 */
-	CMU_OUTPUT_DIV_2   = 0x1U,	/**< Division by 2 */
-	CMU_OUTPUT_DIV_4   = 0x2U,	/**< Division by 4 */
-	CMU_OUTPUT_DIV_8   = 0x3U,	/**< Division by 8 */
-	CMU_OUTPUT_DIV_16  = 0x4U,	/**< Division by 16 */
-	CMU_OUTPUT_DIV_32  = 0x5U,	/**< Division by 32 */
-	CMU_OUTPUT_DIV_64  = 0x6U,	/**< Division by 64 */
-	CMU_OUTPUT_DIV_128 = 0x7U,	/**< Division by 128 */
-} cmu_output_high_div_t;
-
-/**
-  * @brief Output low clock select
-  */
-typedef enum {
-	CMU_OUTPUT_LOW_SEL_LOSC = 0x0U,	/**< Select LOSC */
-	CMU_OUTPUT_LOW_SEL_LRC  = 0x1U,	/**< Select LRC */
-	CMU_OUTPUT_LOW_SEL_LOSM = 0x2U,	/**< Select LOSM */
-	CMU_OUTPUT_LOW_SEL_BUZZ = 0x3U,	/**< Select BUZZ */
-	CMU_OUTPUT_LOW_SEL_ULRC = 0x4U,	/**< Select ULRC */
-} cmu_output_low_sel_t;
-
-/**
-  * @brief BUZZ frequency division
-  */
-typedef enum {
-	CMU_BUZZ_DIV_2   = 0x0U,	/**< Division by 2 */
-	CMU_BUZZ_DIV_4   = 0x1U,	/**< Division by 4 */
-	CMU_BUZZ_DIV_8   = 0x2U,	/**< Division by 8 */
-	CMU_BUZZ_DIV_16  = 0x3U,	/**< Division by 16 */
-	CMU_BUZZ_DIV_32  = 0x4U,	/**< Division by 32 */
-	CMU_BUZZ_DIV_64  = 0x5U,	/**< Division by 64 */
-	CMU_BUZZ_DIV_128 = 0x6U,	/**< Division by 128 */
-	CMU_BUZZ_DIV_256 = 0x7U,	/**< Division by 256 */
-} cmu_buzz_div_t;
-
-/**
-  * @brief Low power peripheral clock select
-  */
-typedef enum {
-	CMU_LP_PERH_CLOCK_SEL_PCLK2   = 0x0U,	/**< Select PCLK2 */
-	CMU_LP_PERH_CLOCK_SEL_PLL1    = 0x1U,	/**< Select PLL1 */
-	CMU_LP_PERH_CLOCK_SEL_PLL2    = 0x2U,	/**< Select PLL2 */
-	CMU_LP_PERH_CLOCK_SEL_HRC     = 0x3U,	/**< Select HRC */
-	CMU_LP_PERH_CLOCK_SEL_HOSC    = 0x4U,	/**< Select HOSC */
-	CMU_LP_PERH_CLOCK_SEL_LRC     = 0x5U,	/**< Select LRC */
-	CMU_LP_PERH_CLOCK_SEL_LOSC    = 0x6U,	/**< Select LOSC */
-	CMU_LP_PERH_CLOCK_SEL_ULRC    = 0x7U,	/**< Select ULRC */
-	CMU_LP_PERH_CLOCK_SEL_HRC_1M  = 0x8U,	/**< Select HRC down to 1MHz */
-	CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9U,	/**< Select HOSC down to 1MHz  */
-	CMU_LP_PERH_CLOCK_SEL_LOSM    = 0xAU,	/**< Select LOSM */
-	CMU_LP_PERH_CLOCK_SEL_HOSM    = 0xBU,	/**< Select HOSM */
-} cmu_lp_perh_clock_sel_t;
-
-/**
-  * @brief LCD clock select
-  */
-typedef enum {
-	CMU_LCD_SEL_LOSM    = 0x0U,	/**< Select LOSM */
-	CMU_LCD_SEL_LOSC    = 0x1U,	/**< Select LOSC */
-	CMU_LCD_SEL_LRC     = 0x2U,	/**< Select LRC */
-	CMU_LCD_SEL_ULRC    = 0x3U,	/**< Select ULRC */
-	CMU_LCD_SEL_HRC_1M  = 0x4U,	/**< Select HRC down to 1MHz */
-	CMU_LCD_SEL_HOSC_1M = 0x5U,	/**< Select HOSC down to 1MHz */
-} cmu_lcd_clock_sel_t;
-
-/**
-  * @brief QSPI clock select
-  */
-typedef enum {
-	CMU_QSPI_CLOCK_SEL_PCLK1 = 0x0U,	/**< Select PCLK1 */
-	CMU_QSPI_CLOCK_SEL_HCLK2 = 0x1U,	/**< Select HCLK2 */
-	CMU_QSPI_CLOCK_SEL_HRC   = 0x2U,	/**< Select HRC */
-	CMU_QSPI_CLOCK_SEL_HOSC  = 0x3U,	/**< Select HOSC */
-	CMU_QSPI_CLOCK_SEL_PLL1  = 0x4U,	/**< Select PLL1 */
-	CMU_QSPI_CLOCK_SEL_HOSM  = 0x5U,	/**< Select HOSC security management */
-} cmu_qspi_clock_sel_t;
-
-/**
-  * @brief USB clock select
-  */
-typedef enum {
-	CMU_USB_CLOCK_SEL_HOSC  = 0x0U,	/**< Select HOSC */
-	CMU_USB_CLOCK_SEL_HRC   = 0x1U,	/**< Select HRC */
-	CMU_USB_CLOCK_SEL_PCLK1 = 0x2U,	/**< Select PCLK1 */
-	CMU_USB_CLOCK_SEL_PLL1  = 0x3U,	/**< Select PLL1 */
-	CMU_USB_CLOCK_SEL_HOSM  = 0x4U,	/**< Select HOSC security management */
-} cmu_usb_clock_sel_t;
-
-/**
-  * @brief USB clock division
-  */
-typedef enum {
-	CMU_USB_DIV_1    = 0x0U,	/**< Division by 1 */
-	CMU_USB_DIV_2    = 0x1U,	/**< Division by 2 */
-	CMU_USB_DIV_4    = 0x2U,	/**< Division by 4 */
-	CMU_USB_DIV_8    = 0x3U,	/**< Division by 8 */
-	CMU_USB_DIV_16   = 0x4U,	/**< Division by 16 */
-	CMU_USB_DIV_32   = 0x5U,	/**< Division by 32 */
-	CMU_USB_DIV_64   = 0x6U,	/**< Division by 64 */
-	CMU_USB_DIV_128  = 0x7U,	/**< Division by 128 */
-	CMU_USB_DIV_256  = 0x8U,	/**< Division by 256 */
-	CMU_USB_DIV_512  = 0x9U,	/**< Division by 512 */
-	CMU_USB_DIV_1024 = 0xAU,	/**< Division by 1024 */
-	CMU_USB_DIV_2048 = 0xBU,	/**< Division by 2048 */
-	CMU_USB_DIV_4096 = 0xCU,	/**< Division by 4096 */
-} cmu_usb_div_t;
-
-/**
-  * @brief Peripheral clock enable/disable
-  * @verbatim
-      In this module, for the convenience of code maintenance,
-      TIMERx is used to indicate the sequence of the timer peripheral.
-      Different product series TIMERx represent different meanings:
-      1. For ES32F36xx series:
-      TIMER0 ----> AD16C4T0
-      TIMER1 ----> AD16C4T1
-      TIMER2 ----> GP32C4T0
-      TIMER3 ----> GP32C4T1
-      TIMER4 ----> BS16T0
-      TIMER5 ----> BS16T1
-      TIMER6 ----> GP16C4T0
-      TIMER7 ----> GP16C4T1
-
-      2. For ES32F393x/ES32F336x/ES32F392x series:
-      TIMER0 ----> GP16C4T0
-      TIMER1 ----> GP16C4T1
-      TIMER2 ----> GP32C4T0
-      TIMER3 ----> GP32C4T1
-      TIMER4 ----> BS16T0
-      TIMER5 ----> BS16T1
-      TIMER6 ----> GP16C4T2
-      TIMER7 ----> GP16C4T3
-    @endverbatim
-  */
-typedef enum {
-	CMU_PERH_GPIO    = (1U << 0),			/**< GPIO */
-	CMU_PERH_CRC     = (1U << 1),			/**< CRC */
-	CMU_PERH_CALC    = (1U << 2),			/**< CALC */
-	CMU_PERH_CRYPT   = (1U << 3),			/**< CRYPT */
-	CMU_PERH_TRNG    = (1U << 4),			/**< TRNG */
-	CMU_PERH_PIS     = (1U << 5),			/**< PIS */
-	CMU_PERH_EBI     = (1U << 6),			/**< EBI */
-	CMU_PERH_QSPI_H  = (1U << 7),			/**< QSPI AHB */
-	CMU_PERH_DMA     = (1U << 8),			/**< DMA */
-	CMU_PERH_USB     = (1U << 10),			/**< USB */
-	CMU_PERH_ECC     = (1U << 11),			/**< ECC */
-	CMU_PERH_TIMER0  = (1U << 0)  | (1U << 27),	/**< TIMER0 */
-	CMU_PERH_TIMER1  = (1U << 1)  | (1U << 27),	/**< TIMER1 */
-	CMU_PERH_TIMER2  = (1U << 2)  | (1U << 27),	/**< TIMER2 */
-	CMU_PERH_TIMER3  = (1U << 3)  | (1U << 27),	/**< TIMER3 */
-	CMU_PERH_TIMER4  = (1U << 4)  | (1U << 27),	/**< TIMER4 */
-	CMU_PERH_TIMER5  = (1U << 5)  | (1U << 27),	/**< TIMER5 */
-	CMU_PERH_TIMER6  = (1U << 6)  | (1U << 27),	/**< TIMER6 */
-	CMU_PERH_TIMER7  = (1U << 7)  | (1U << 27),	/**< TIMER7 */
-	CMU_PERH_UART0   = (1U << 8)  | (1U << 27),	/**< UART0 */
-	CMU_PERH_UART1   = (1U << 9)  | (1U << 27),	/**< UART1 */
-	CMU_PERH_UART2   = (1U << 10) | (1U << 27),	/**< UART2 */
-	CMU_PERH_UART3   = (1U << 11) | (1U << 27),	/**< UART3 */
-	CMU_PERH_UART4   = (1U << 12) | (1U << 27),	/**< UART4 */
-	CMU_PERH_UART5   = (1U << 13) | (1U << 27),	/**< UART5 */
-	CMU_PERH_SPI0    = (1U << 16) | (1U << 27),	/**< SPI0 */
-	CMU_PERH_SPI1    = (1U << 17) | (1U << 27),	/**< SPI1 */
-	CMU_PERH_SPI2    = (1U << 18) | (1U << 27),	/**< SPI2 */
-	CMU_PERH_I2C0    = (1U << 20) | (1U << 27),	/**< I2C0 */
-	CMU_PERH_I2C1    = (1U << 21) | (1U << 27),	/**< I2C1 */
-	CMU_PERH_CAN     = (1U << 24) | (1U << 27),	/**< CAN */
-	CMU_PERH_QSPI_P  = (1U << 25) | (1U << 27),	/**< QSPI APB */
-	CMU_PERH_LPTIM0  = (1U << 0)  | (1U << 28),	/**< LPTIM0 */
-	CMU_PERH_LPUART0 = (1U << 2)  | (1U << 28),	/**< LPUART0 */
-	CMU_PERH_ADC0    = (1U << 4)  | (1U << 28),	/**< ADC0 */
-	CMU_PERH_ADC1    = (1U << 5)  | (1U << 28),	/**< ADC1 */
-	CMU_PERH_ACMP0   = (1U << 6)  | (1U << 28),	/**< ACMP0 */
-	CMU_PERH_ACMP1   = (1U << 7)  | (1U << 28),	/**< ACMP1 */
-	CMU_PERH_OPAMP   = (1U << 8)  | (1U << 28),	/**< OPAMP */
-	CMU_PERH_DAC0    = (1U << 9)  | (1U << 28),	/**< DAC0 */
-	CMU_PERH_ACMP2   = (1U << 11) | (1U << 28),	/**< ACMP2 */
-	CMU_PERH_WWDT    = (1U << 12) | (1U << 28),	/**< WWDT */
-	CMU_PERH_LCD     = (1U << 13) | (1U << 28),	/**< LCD */
-	CMU_PERH_IWDT    = (1U << 14) | (1U << 28),	/**< IWDT */
-	CMU_PERH_RTC     = (1U << 15) | (1U << 28),	/**< RTC */
-	CMU_PERH_TSENSE  = (1U << 16) | (1U << 28),	/**< TSENSE */
-	CMU_PERH_BKPC    = (1U << 17) | (1U << 28),	/**< BKPC */
-	CMU_PERH_DBGC    = (1U << 19) | (1U << 28),	/**< DBGC */
-	CMU_PERH_ALL     = (0x7FFFFFFFU),		/**< ALL */
-} cmu_perh_t;
-
-/**
-  * @brief CMU interrupt type
-  */
-typedef enum {
-	CMU_LOSC_STOP    = 0x0U,	/**< LOSC STOP INTERRUPT */
-	CMU_HOSC_STOP    = 0x1U,	/**< HOSC STOP INTERRUPT */
-	CMU_PLL1_UNLOCK  = 0x2U,	/**< PLL1 UNLOCK INTERRUPT */
-	CMU_LOSC_START   = 0x3U,	/**< LOSC START INTERRUPT */
-	CMU_HOSC_START   = 0x4U,	/**< HOSC START INTERRUPT */
-} cmu_security_t;
-
-/**
-  * @brief CMU clock state type
-  */
-typedef enum {
-	CMU_CLOCK_STATE_HOSCACT = (1U << 0),	/**< HOSC active */
-	CMU_CLOCK_STATE_LOSCACT = (1U << 1),	/**< LOSC active */
-	CMU_CLOCK_STATE_HRCACT  = (1U << 2),	/**< HRC active */
-	CMU_CLOCK_STATE_LRCACT  = (1U << 3),	/**< LRC active */
-	CMU_CLOCK_STATE_ULRCACT = (1U << 4),	/**< ULRC active */
-	CMU_CLOCK_STATE_PLL1ACT = (1U << 8),	/**< PLL1 active */
-	CMU_CLOCK_STATE_PLL2ACT = (1U << 9),	/**< PLL2 active */
-	CMU_CLOCK_STATE_HOSCRDY = (1U << 16),	/**< HOSC ready */
-	CMU_CLOCK_STATE_LOSCRDY = (1U << 17),	/**< LOSC ready */
-	CMU_CLOCK_STATE_HRCRDY  = (1U << 18),	/**< HRC ready */
-	CMU_CLOCK_STATE_LRCRDY  = (1U << 19),	/**< LRC ready */
-	CMU_CLOCK_STATE_PLL1RDY = (1U << 24),	/**< PLL1 ready */
-	CMU_CLOCK_STATE_PLL2RDY = (1U << 25),	/**< PLL2 ready */
-} cmu_clock_state_t;
-
-/**
-  * @brief Stop1 clock select type
-  */
-typedef enum {
-	CMU_STOP1_CLOCK_LRC     = 0x0U,	/**< LRC */
-	CMU_STOP1_CLOCK_HRC_24M = 0x1U,	/**< HRC 24MHz */
-	CMU_STOP1_CLOCK_HRC_2M  = 0x2U,	/**< HRC 2MHz */
-	CMU_STOP1_CLOCK_HRC_1M  = 0x3U,	/**< HRC divides to 1MHz */
-	CMU_STOP1_CLOCK_HOSC    = 0x4U,	/**< HOSC */
-	CMU_STOP1_CLOCK_HOSC_1M = 0x5U,	/**< HOSC divides to 1MHz */
-	CMU_STOP1_CLOCK_HOSCM   = 0x6U,	/**< HOSC security management */
-} cmu_stop1_clock_t;
-
-/**
-  * @}
-  */
-
-/**
-  * @defgroup CMU_Private_Macros CMU Private Macros
-  * @{
-  */
-#define IS_CMU_CLOCK(x)		(((x) == CMU_CLOCK_HRC)  || \
-                                 ((x) == CMU_CLOCK_LRC)  || \
-                                 ((x) == CMU_CLOCK_LOSC) || \
-                                 ((x) == CMU_CLOCK_PLL1) || \
-                                 ((x) == CMU_CLOCK_HOSC))
-#if defined(ES32F36xx) || defined(ES32F39xx)
-#define IS_CMU_PLL1_OUTPUT(x)	(((x) == CMU_PLL1_OUTPUT_36M) || \
-                                 ((x) == CMU_PLL1_OUTPUT_48M) || \
-                                 ((x) == CMU_PLL1_OUTPUT_72M) || \
-                                 ((x) == CMU_PLL1_OUTPUT_96M))
-#endif
-#ifdef ES32F336x
-#define IS_CMU_PLL1_OUTPUT(x)	(((x) == CMU_PLL1_OUTPUT_36M) || \
-                                 ((x) == CMU_PLL1_OUTPUT_48M))
-#endif
-#define IS_CMU_PLL1_INPUT(x)	(((x) == CMU_PLL1_INPUT_HRC_6)  || \
-                                 ((x) == CMU_PLL1_INPUT_PLL2)   || \
-                                 ((x) == CMU_PLL1_INPUT_HOSC)   || \
-                                 ((x) == CMU_PLL1_INPUT_HOSC_2) || \
-                                 ((x) == CMU_PLL1_INPUT_HOSC_3) || \
-                                 ((x) == CMU_PLL1_INPUT_HOSC_4) || \
-                                 ((x) == CMU_PLL1_INPUT_HOSC_5) || \
-                                 ((x) == CMU_PLL1_INPUT_HOSC_6))
-#define IS_CMU_HOSC_RANGE(x)	(((x) == CMU_HOSC_2M)  || \
-                                 ((x) == CMU_HOSC_4M)  || \
-                                 ((x) == CMU_HOSC_8M)  || \
-                                 ((x) == CMU_HOSC_16M) || \
-                                 ((x) == CMU_HOSC_24M))
-#define IS_CMU_DIV(x)		(((x) == CMU_DIV_1)    || \
-                                 ((x) == CMU_DIV_2)    || \
-                                 ((x) == CMU_DIV_4)    || \
-                                 ((x) == CMU_DIV_8)    || \
-                                 ((x) == CMU_DIV_16)   || \
-                                 ((x) == CMU_DIV_32)   || \
-                                 ((x) == CMU_DIV_64)   || \
-                                 ((x) == CMU_DIV_128)  || \
-                                 ((x) == CMU_DIV_256)  || \
-                                 ((x) == CMU_DIV_512)  || \
-                                 ((x) == CMU_DIV_1024) || \
-                                 ((x) == CMU_DIV_2048) || \
-                                 ((x) == CMU_DIV_4096))
-#define IS_CMU_BUS(x)		(((x) == CMU_HCLK_1) || \
-                                 ((x) == CMU_HCLK_2) || \
-                                 ((x) == CMU_SYS)    || \
-                                 ((x) == CMU_PCLK_1) || \
-                                 ((x) == CMU_PCLK_2))
-#define IS_CMU_OUTPUT_HIGH_SEL(x)	(((x) == CMU_OUTPUT_HIGH_SEL_HOSC) || \
-                                         ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \
-                                         ((x) == CMU_OUTPUT_HIGH_SEL_HRC)  || \
-                                         ((x) == CMU_OUTPUT_HIGH_SEL_LRC)  || \
-                                         ((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \
-                                         ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \
-                                         ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \
-                                         ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK))
-#define IS_CMU_OUTPUT_HIGH_DIV(x)	(((x) == CMU_OUTPUT_DIV_1)  || \
-                                         ((x) == CMU_OUTPUT_DIV_2)  || \
-                                         ((x) == CMU_OUTPUT_DIV_4)  || \
-                                         ((x) == CMU_OUTPUT_DIV_8)  || \
-                                         ((x) == CMU_OUTPUT_DIV_16) || \
-                                         ((x) == CMU_OUTPUT_DIV_32) || \
-                                         ((x) == CMU_OUTPUT_DIV_64) || \
-                                         ((x) == CMU_OUTPUT_DIV_128))
-#define IS_CMU_OUTPUT_LOW_SEL(x)	(((x) == CMU_OUTPUT_LOW_SEL_LOSC) || \
-                                         ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \
-                                         ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \
-                                         ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \
-                                         ((x) == CMU_OUTPUT_LOW_SEL_ULRC))
-#define IS_CMU_SAFE_CLOCK_TYPE(x)	(((x) == CMU_SAFE_CLK_HOSC) || \
-                                         ((x) == CMU_SAFE_CLK_LOSC) || \
-                                         ((x) == CMU_SAFE_CLK_PLL))
-#define IS_CMU_BUZZ_DIV(x)	(((x) == CMU_BUZZ_DIV_2)   || \
-                                 ((x) == CMU_BUZZ_DIV_4)   || \
-                                 ((x) == CMU_BUZZ_DIV_8)   || \
-                                 ((x) == CMU_BUZZ_DIV_16)  || \
-                                 ((x) == CMU_BUZZ_DIV_32)  || \
-                                 ((x) == CMU_BUZZ_DIV_64)  || \
-                                 ((x) == CMU_BUZZ_DIV_128) || \
-                                 ((x) == CMU_BUZZ_DIV_256))
-#define IS_CMU_LP_PERH_CLOCK_SEL(x)	(((x) == CMU_LP_PERH_CLOCK_SEL_PCLK2)   || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1)    || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2)    || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_HRC)     || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC)    || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_LRC)     || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_LOSC)    || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_ULRC)    || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M)  || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM)    || \
-                                         ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM))
-#define IS_CMU_LCD_CLOCK_SEL(x)	(((x) == CMU_LCD_SEL_LOSM)   || \
-                                 ((x) == CMU_LCD_SEL_LOSC)   || \
-                                 ((x) == CMU_LCD_SEL_LRC)    || \
-                                 ((x) == CMU_LCD_SEL_ULRC)   || \
-                                 ((x) == CMU_LCD_SEL_HRC_1M) || \
-                                 ((x) == CMU_LCD_SEL_HOSC_1M))
-#define IS_CMU_QSPI_CLOCK_SEL(x)	(((x) == CMU_QSPI_CLOCK_SEL_PCLK1) || \
-                                         ((x) == CMU_QSPI_CLOCK_SEL_HCLK2) || \
-                                         ((x) == CMU_QSPI_CLOCK_SEL_HRC)   || \
-                                         ((x) == CMU_QSPI_CLOCK_SEL_HOSC)  || \
-                                         ((x) == CMU_QSPI_CLOCK_SEL_PLL1)  || \
-                                         ((x) == CMU_QSPI_CLOCK_SEL_HOSM))
-#define IS_CMU_USB_CLOCK_SEL(x)	(((x) == CMU_USB_CLOCK_SEL_HOSC)  || \
-                                 ((x) == CMU_USB_CLOCK_SEL_HRC)   || \
-                                 ((x) == CMU_USB_CLOCK_SEL_PCLK1) || \
-                                 ((x) == CMU_USB_CLOCK_SEL_PLL1)  || \
-                                 ((x) == CMU_USB_CLOCK_SEL_HOSM))
-#define IS_CMU_USB_DIV(x)	(((x) == CMU_USB_DIV_1)    || \
-                                 ((x) == CMU_USB_DIV_2)    || \
-                                 ((x) == CMU_USB_DIV_4)    || \
-                                 ((x) == CMU_USB_DIV_8)    || \
-                                 ((x) == CMU_USB_DIV_16)   || \
-                                 ((x) == CMU_USB_DIV_32)   || \
-                                 ((x) == CMU_USB_DIV_64)   || \
-                                 ((x) == CMU_USB_DIV_128)  || \
-                                 ((x) == CMU_USB_DIV_256)  || \
-                                 ((x) == CMU_USB_DIV_512)  || \
-                                 ((x) == CMU_USB_DIV_1024) || \
-                                 ((x) == CMU_USB_DIV_2048) || \
-                                 ((x) == CMU_USB_DIV_4096))
-#define IS_CMU_PERH(x)		(((x) == CMU_PERH_GPIO)    || \
-                                 ((x) == CMU_PERH_CRC)     || \
-                                 ((x) == CMU_PERH_CALC)    || \
-                                 ((x) == CMU_PERH_CRYPT)   || \
-                                 ((x) == CMU_PERH_TRNG)    || \
-                                 ((x) == CMU_PERH_PIS)     || \
-				 ((x) == CMU_PERH_EBI)     || \
-				 ((x) == CMU_PERH_QSPI_H)  || \
-				 ((x) == CMU_PERH_DMA)     || \
-				 ((x) == CMU_PERH_USB)     || \
-				 ((x) == CMU_PERH_ECC)     || \
-                                 ((x) == CMU_PERH_TIMER0)  || \
-                                 ((x) == CMU_PERH_TIMER1)  || \
-                                 ((x) == CMU_PERH_TIMER2)  || \
-                                 ((x) == CMU_PERH_TIMER3)  || \
-                                 ((x) == CMU_PERH_TIMER4)  || \
-                                 ((x) == CMU_PERH_TIMER5)  || \
-                                 ((x) == CMU_PERH_TIMER6)  || \
-                                 ((x) == CMU_PERH_TIMER7)  || \
-                                 ((x) == CMU_PERH_UART0)   || \
-                                 ((x) == CMU_PERH_UART1)   || \
-                                 ((x) == CMU_PERH_UART2)   || \
-                                 ((x) == CMU_PERH_UART3)   || \
-                                 ((x) == CMU_PERH_UART4)   || \
-                                 ((x) == CMU_PERH_UART5)   || \
-                                 ((x) == CMU_PERH_SPI0)    || \
-                                 ((x) == CMU_PERH_SPI1)    || \
-                                 ((x) == CMU_PERH_SPI2)    || \
-                                 ((x) == CMU_PERH_I2C0)    || \
-                                 ((x) == CMU_PERH_I2C1)    || \
-                                 ((x) == CMU_PERH_CAN)     || \
-				 ((x) == CMU_PERH_QSPI_P)  || \
-                                 ((x) == CMU_PERH_LPTIM0)  || \
-                                 ((x) == CMU_PERH_LPUART0) || \
-                                 ((x) == CMU_PERH_ADC0)    || \
-                                 ((x) == CMU_PERH_ADC1)    || \
-                                 ((x) == CMU_PERH_ACMP0)   || \
-                                 ((x) == CMU_PERH_ACMP1)   || \
-                                 ((x) == CMU_PERH_OPAMP)   || \
-                                 ((x) == CMU_PERH_DAC0)    || \
-				 ((x) == CMU_PERH_ACMP2)   || \
-                                 ((x) == CMU_PERH_WWDT)    || \
-                                 ((x) == CMU_PERH_LCD)     || \
-                                 ((x) == CMU_PERH_IWDT)    || \
-                                 ((x) == CMU_PERH_RTC)     || \
-                                 ((x) == CMU_PERH_TSENSE)  || \
-                                 ((x) == CMU_PERH_BKPC)    || \
-                                 ((x) == CMU_PERH_DBGC)    || \
-                                 ((x) == CMU_PERH_ALL))
-#define IS_CMU_CLOCK_STATE(x)	(((x) == CMU_CLOCK_STATE_HOSCACT) || \
-                                 ((x) == CMU_CLOCK_STATE_LOSCACT) || \
-				 ((x) == CMU_CLOCK_STATE_HRCACT)  || \
-				 ((x) == CMU_CLOCK_STATE_LRCACT)  || \
-				 ((x) == CMU_CLOCK_STATE_ULRCACT) || \
-				 ((x) == CMU_CLOCK_STATE_PLL1ACT) || \
-				 ((x) == CMU_CLOCK_STATE_PLL2ACT) || \
-				 ((x) == CMU_CLOCK_STATE_HOSCRDY) || \
-				 ((x) == CMU_CLOCK_STATE_LOSCRDY) || \
-				 ((x) == CMU_CLOCK_STATE_HRCRDY)  || \
-				 ((x) == CMU_CLOCK_STATE_LRCRDY)  || \
-				 ((x) == CMU_CLOCK_STATE_PLL1RDY) || \
-				 ((x) == CMU_CLOCK_STATE_PLL2RDY))
-#define IS_CMU_STOP1_CLOCK(x)	(((x) == CMU_STOP1_CLOCK_LRC) || \
-                                 ((x) == CMU_STOP1_CLOCK_HRC_24M) || \
-				 ((x) == CMU_STOP1_CLOCK_HRC_2M)  || \
-				 ((x) == CMU_STOP1_CLOCK_HRC_1M)  || \
-				 ((x) == CMU_STOP1_CLOCK_HOSC) || \
-				 ((x) == CMU_STOP1_CLOCK_HOSC_1M) || \
-				 ((x) == CMU_STOP1_CLOCK_HOSCM))
-/**
-  * @}
-  */
-
-/** @addtogroup CMU_Public_Functions
-  * @{
-  */
-/** @addtogroup CMU_Public_Functions_Group1
-  * @{
-  */
-/* System clock configure */
-ald_status_t ald_cmu_clock_config_default(void);
-ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock);
-void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output);
-uint32_t ald_cmu_get_clock(void);
-/**
-  * @}
-  */
-
-/** @addtogroup CMU_Public_Functions_Group2
-  * @{
-  */
-/* BUS division control */
-void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div);
-uint32_t ald_cmu_get_hclk1_clock(void);
-uint32_t ald_cmu_get_hclk2_clock(void);
-uint32_t ald_cmu_get_sys_clock(void);
-uint32_t ald_cmu_get_pclk1_clock(void);
-uint32_t ald_cmu_get_pclk2_clock(void);
-/**
-  * @}
-  */
-
-/** @addtogroup CMU_Public_Functions_Group3
-  * @{
-  */
-/* Clock safe configure */
-void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status);
-void ald_cmu_losc_safe_config(type_func_t status);
-void ald_cmu_pll_safe_config(type_func_t status);
-uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type);
-flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr);
-void ald_cmu_irq_handler(void);
-void ald_cmu_irq_cbk(cmu_security_t se);
-/**
-  * @}
-  */
-
-/** @addtogroup CMU_Public_Functions_Group4
-  * @{
-  */
-/* Clock output configure */
-void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel,
-		cmu_output_high_div_t div, type_func_t status);
-void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status);
-/**
-  * @}
-  */
-
-/** @addtogroup CMU_Public_Functions_Group5
-  * @{
-  */
-/* Peripheral Clock configure */
-void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status);
-void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock);
-void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock);
-void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock);
-void ald_cmu_qspi_clock_select(cmu_qspi_clock_sel_t clock);
-void ald_cmu_usb_clock_config(cmu_usb_clock_sel_t clock, cmu_usb_div_t div);
-void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status);
-void ald_cmu_stop1_clock_sel(cmu_stop1_clock_t clock);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_CMU_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_crc.h

@@ -1,212 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_crc.h
-  * @brief   Header file of CRC module driver.
-  *
-  * @version V1.0
-  * @date    18 Jun 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          18 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_CRC_H__
-#define __ALD_CRC_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup CRC
-  * @{
-  */
-
-/** @defgroup CRC_Public_Types CRC Public Types
-  * @{
-  */
-
-/**
-  * @brief CRC mode
-  */
-typedef enum {
-	CRC_MODE_CCITT = 0U,	/**< Ccitt */
-	CRC_MODE_8     = 1U,	/**< Crc8 */
-	CRC_MODE_16    = 2U,	/**< Crc16 */
-	CRC_MODE_32    = 3U,	/**< Crc32 */
-} crc_mode_t;
-
-/**
-  * @brief CRC input length
-  */
-typedef enum {
-	CRC_LEN_AUTO    = 0U,	/**< Auto */
-	CRC_DATASIZE_8  = 1U,	/**< Byte */
-	CRC_DATASIZE_16 = 2U,	/**< Half word */
-	CRC_DATASIZE_32 = 3U,	/**< Word */
-} crc_datasize_t;
-
-/**
-  * @brief CRC whether write error or no
-  */
-typedef enum {
-	CRC_WERR_NO  = 0U,	/**< No error */
-	CRC_WERR_ERR = 1U,	/**< Error */
-} crc_werr_t;
-
-/**
-  * @brief CRC state structures definition
-  */
-typedef enum {
-	CRC_STATE_RESET = 0x0U,	/**< Peripheral is not initialized */
-	CRC_STATE_READY = 0x1U,	/**< Peripheral Initialized and ready for use */
-	CRC_STATE_BUSY  = 0x2U,	/**< An internal process is ongoing */
-	CRC_STATE_ERROR = 0x4U,	/**< Error */
-} crc_state_t;
-
-/**
-  * @brief CRC init structure definition
-  */
-typedef struct {
-	crc_mode_t mode;	/**< CRC mode */
-	type_func_t data_rev;	/**< CRC data reverse or no */
-	type_func_t data_inv;	/**< CRC data inverse or no */
-	type_func_t chs_rev; 	/**< CRC check sum reverse or no */
-	type_func_t chs_inv; 	/**< CRC check sum inverse or no */
-	uint32_t seed;		/**< CRC seed */
-} crc_init_t;
-
-/**
-  * @brief  CRC Handle Structure definition
-  */
-typedef struct crc_handle_s {
-	CRC_TypeDef *perh;	/**< Register base address */
-	crc_init_t init;  	/**< CRC required parameters */
-	uint8_t *cal_buf; 	/**< The pointer of preparing buffer */
-	uint32_t *cal_res;	/**< The pointer of result */
-
-	dma_handle_t hdma;	/**< CRC DMA handle parameters */
-
-	lock_state_t lock;	/**< Locking object */
-	crc_state_t state;	/**< CRC operation state */
-
-	void (*cal_cplt_cbk)(struct crc_handle_s *arg);	/**< Calculate completed callback */
-	void (*err_cplt_cbk)(struct crc_handle_s *arg);	/**< Calculate error callback */
-} crc_handle_t;
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Public_Macros CRC Public Macros
-  * @{
-  */
-#define CRC_ENABLE(handle)		(SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
-#define CRC_DISABLE(handle)		(CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
-#define CRC_RESET(handle)		(SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK))
-#define CRC_DMA_ENABLE(handle) 		(SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
-#define CRC_DMA_DISABLE(handle) 	(CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
-#define CRC_CLEAR_ERROR_FLAG(handle)	(SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Private_Macros   CRC Private Macros
-  * @{
-  */
-#define IS_CRC(x) 	((x) == CRC)
-#define IS_CRC_MODE(x) 	(((x) == CRC_MODE_CCITT) || \
-			 ((x) == CRC_MODE_8)     || \
-			 ((x) == CRC_MODE_16)    || \
-			 ((x) == CRC_MODE_32))
-/**
-  * @}
-  */
-
-/** @addtogroup CRC_Public_Functions
-  * @{
-  */
-
-/** @addtogroup CRC_Public_Functions_Group1
-  * @{
-  */
-ald_status_t ald_crc_init(crc_handle_t *hperh);
-void ald_crc_reset(crc_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup CRC_Public_Functions_Group2
-  * @{
-  */
-uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size);
-uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size);
-uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size);
-/**
-  * @}
-  */
-
-
-/** @addtogroup CRC_Public_Functions_Group3
-  * @{
-  */
-ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
-ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
-ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
-ald_status_t ald_crc_dma_pause(crc_handle_t *hperh);
-ald_status_t ald_crc_dma_resume(crc_handle_t *hperh);
-ald_status_t ald_crc_dma_stop(crc_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup CRC_Public_Functions_Group4
-  * @{
-  */
-crc_state_t ald_crc_get_state(crc_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_CRC_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_crypt.h

@@ -1,341 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_crypt.h
-  * @brief   Header file of CRYPT module driver.
-  *
-  * @version V1.0
-  * @date    19 Jun 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          19 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_CRYPT_H__
-#define __ALD_CRYPT_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup CRYPT
-  * @{
-  */
-
-/** @defgroup CRYPT_Public_Types CRYPT Public Types
-  * @{
-  */
-
-/**
-  * @brief CRYPT encrypt or decrypt select
-  */
-typedef enum {
-	CRYPT_DECRYPT = 0U,	/**< Decrypt */
-	CRYPT_ENCRYPT = 1U,	/**< Encrypt */
-} crypt_encs_t;
-
-/**
-  * @brief CRYPT aes key select
-  */
-typedef enum {
-	CRYPT_BITS_128 = 0U,	/**< 128bit key for aes */
-	CRYPT_BITS_192 = 1U,	/**< 192bit key for aes */
-	CRYPT_BITS_256 = 2U,	/**< 256bit key for aes */
-} crypt_aesks_t;
-
-/**
-  * @brief CRYPT mode select
-  */
-typedef enum {
-	CRYPT_MODE_ECB = 0U,	/**< ECB */
-	CRYPT_MODE_CBC = 1U,	/**< CBC */
-	CRYPT_MODE_CTR = 2U,	/**< CTR */
-} crypt_mode_t;
-
-/**
-  * @brief CRYPT data type
-  */
-typedef enum {
-	CRYPT_DATA_CHANGE_NO = 0U,	/**< No exchange */
-	CRYPT_DATA_CHANGE_16 = 1U,	/**< 16bit exchange */
-	CRYPT_DATA_CHANGE_8  = 2U,	/**< 8bit exchange */
-	CRYPT_DATA_CHANGE_1  = 3U,	/**< 1bit exchange */
-} crypt_datatype_t;
-
-/**
-  * @brief CRYPT des key select
-  */
-typedef enum {
-	CRYPT_KEYS_2 = 0U,	/**< 2 key for des */
-	CRYPT_KEYS_3 = 1U,	/**< 3 key for des */
-	CRYPT_KEYS_1 = 2U,	/**< 1 key for des */
-} crypt_desks_t;
-
-/**
-  * @brief CRYPT crypt select
-  */
-typedef enum {
-	CRYPT_CRYSEL_AES = 0U,	/**< AES */
-	CRYPT_CRYSEL_DES = 1U,	/**< DES */
-} crypt_crysel_t;
-
-/**
-  * @brief CRYPT interrupt
-  */
-typedef enum {
-	CRYPT_IT_IT = 0x80U,	/**< Interrupt */
-} crypt_it_t;
-
-/**
-  * @brief CRYPT interrupt flag
-  */
-typedef enum {
-	CRYPT_FLAG_AESIF = 0x1U,  	/**< Aes flag */
-	CRYPT_FLAG_DESIF = 0x2U,  	/**< Des flag */
-	CRYPT_FLAG_DONE  = 0x100U,	/**< Complete flag */
-} crypt_flag_t;
-
-/**
-  * @brief CRYPT key select
-  */
-typedef enum {
-	CRYPT_AES_BITS_128 = 0x4U,	/**< 128bit key of aes */
-	CRYPT_AES_BITS_192 = 0x6U,	/**< 192bit key of aes */
-	CRYPT_AES_BITS_256 = 0x8U,	/**< 192bit key of ase */
-	CRYPT_DES_KEYS_1   = 0x12U,	/**< 1 key of des */
-	CRYPT_DES_KEYS_2   = 0x14U,	/**< 2 key of des */
-	CRYPT_DES_KEYS_3   = 0x16U,	/**< 3 key of des */
-} crypt_ks_t;
-
-/**
-  * @brief CRYPT state structures definition
-  */
-typedef enum {
-	CRYPT_STATE_RESET = 0x0U,	/**< Peripheral is not initialized */
-	CRYPT_STATE_READY = 0x1U,	/**< Peripheral Initialized and ready for use */
-	CRYPT_STATE_BUSY  = 0x2U,	/**< An internal process is ongoing */
-	CRYPT_STATE_ERROR = 0x4U,	/**< Error */
-} crypt_state_t;
-
-/**
-  * @brief CRYPT key length
-  */
-typedef enum {
-	KEY_2_LEN = 2U,	/**< Key's lenth is 2 */
-	KEY_4_LEN = 4U,	/**< Key's lenth is 4 */
-	KEY_6_LEN = 6U,	/**< Key's lenth is 6 */
-	KEY_8_LEN = 8U,	/**< Key's lenth is 8 */
-} crypt_key_len_t;
-
-/**
-  * @brief CRYPT iv length
-  */
-typedef enum {
-	IV_2_LEN = 2U,	/**< iv's lenth is 2 */
-	IV_4_LEN = 4U,	/**< iv's lenth is 4 */
-} crypt_ivr_len_t;
-
-/**
-  * @brief CRYPT data type
-  */
-typedef enum {
-	DATA_32_BIT = 0U,	/**< 32 bit data,don't swap */
-	DATA_16_BIT = 1U,	/**< 16 bit data,swap */
-	DATA_8_BIT  = 2U,	/**< 8 bit data,swap */
-	DATA_1_BIT  = 3U,	/**< 1 bit data, swap */
-} crypt_data_t;
-
-/**
-  * @brief CRYPT init structure definition
-  */
-typedef struct {
-	crypt_mode_t mode;    	/**< Crypt mode */
-	crypt_data_t type;    	/**< Data type select */
-	crypt_ks_t key;		/**< Key select */
-} crypt_init_t;
-
-/**
-  * @brief  CRYPT Handle Structure definition
-  */
-typedef struct crypt_handle_s {
-	CRYPT_TypeDef *perh;	/**< Register base address */
-	crypt_init_t init;  	/**< CRYPT required parameters */
-
-	dma_handle_t hdma_m2p;	/**< CRYPT DMA handle parameters memory to crypt module */
-	dma_handle_t hdma_p2m;	/**< CRYPT DMA handle parameters crypt module to memory */
-
-	uint8_t *plain_text; 	/**< Pointer to plain text */
-	uint8_t *cipher_text;	/**< Pointer to cipher text */
-	uint32_t size;       	/**< The size of crypt data buf */
-	uint32_t count;      	/**< The count of crypt data buf */
-	uint32_t step;       	/**< The step of once crypt 2(des) or 4(aes) */
-	uint32_t dir;        	/**< ENCRYPT or DECRYPT */
-	uint32_t iv[4];     	/**< The iv of crypt */
-	uint32_t iv_size;	/**< The iv size */
-	uint32_t key[8];     	/**< The key of crypt */
-	uint32_t key_size;	/**< The key size */
-	lock_state_t lock;   	/**< Locking object */
-	crypt_state_t state; 	/**< CRYPT operation state */
-
-	void (*crypt_cplt_cbk)(struct crypt_handle_s *arg);	/**< Crypt completed callback */
-	void (*err_cplt_cbk)(struct crypt_handle_s *arg);  	/**< Crypt error callback */
-} crypt_handle_t;
-/**
-  * @}
-  */
-
-/** @defgroup CRYPT_Public_Macros CRYPT Public Macros
-  * @{
-  */
-#define CRYPT_GO(handle) 		(SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK))
-#define CRYPT_FIFOEN_ENABLE(handle) 	(SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
-#define CRYPT_FIFOEN_DISABLE(handle) 	(CLEAR_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
-#define CRYPT_IVEN_ENABLE(handle) 	(SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
-#define CRYPT_IVEN_DISABLE(handle) 	(CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
-#define CRYPT_IE_ENABLE(handle)		(SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
-#define CRYPT_IE_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
-#define CRYPT_DMA_ENABLE(handle)	(SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
-#define CRYPT_DMA_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
-#define CRYPT_SETDIR(handle, dir)	do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS);	\
-					   (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0)
-#define CRYPT_WRITE_FIFO(handle, data)  ((handle)->perh->FIFO = (data))
-#define CRYPT_READ_FIFO(handle)		((handle)->perh->FIFO)
-/**
-  * @}
-  */
-
-/** @defgroup CRYPT_Private_Macros   CRYPT Private Macros
-  * @{
-  */
-#define IS_CRYPT(x)		((x) == CRYPT)
-#define IS_CRYPT_MODE(x) 	(((x) == CRYPT_MODE_ECB) ||   \
-				 ((x) == CRYPT_MODE_CBC) ||   \
-				 ((x) == CRYPT_MODE_CTR))
-#define IS_CRYPT_KS(x) 		(((x) == CRYPT_AES_BITS_128) || \
-				 ((x) == CRYPT_AES_BITS_192) || \
-				 ((x) == CRYPT_AES_BITS_256) || \
-				 ((x) == CRYPT_DES_KEYS_1)   || \
-				 ((x) == CRYPT_DES_KEYS_2)   || \
-				 ((x) == CRYPT_DES_KEYS_3))
-#define IS_CRYPT_IT(x)		((x) == CRYPT_IT_IT)
-#define IS_CRYPT_FLAG(x) 	(((x) == CRYPT_FLAG_AESIF) || \
-				 ((x) == CRYPT_FLAG_DESIF) || \
-				 ((x) == CRYPT_FLAG_DONE))
-#define IS_CRYPT_IV_LEN(x)	(((x) == IV_2_LEN) || \
-				 ((x) == IV_4_LEN))
-#define IS_CRYPT_KEY_LEN(x)	(((x) == KEY_2_LEN) || \
-				 ((x) == KEY_4_LEN) || \
-				 ((x) == KEY_6_LEN) || \
-				 ((x) == KEY_8_LEN))
-/**
-  * @}
-  */
-
-/** @addtogroup CRYPT_Public_Functions
-  * @{
-  */
-
-/** @addtogroup CRYPT_Public_Functions_Group1
-  * @{
-  */
-extern ald_status_t ald_crypt_init(crypt_handle_t *hperh);
-extern ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t * key, crypt_key_len_t len);
-extern ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t * key, crypt_key_len_t len);
-extern ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t * iv, crypt_ivr_len_t len);
-extern ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t * iv, crypt_ivr_len_t len);
-/**
-  * @}
-  */
-
-/** @addtogroup CRYPT_Public_Functions_Group2
-  * @{
-  */
-extern ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t * plain_text, uint8_t * cipher_text, uint32_t size);
-extern ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t * cipher_text, uint8_t * plain_text, uint32_t size);
-extern ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag);
-extern ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size);
-extern ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size);
-
-extern ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t * plain_text,
-             uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
-extern ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t * cipher_text,
-               uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
-
-/**
-  * @}
-  */
-
-/** @addtogroup CRYPT_Public_Functions_Group3
-  * @{
-  */
-
-extern ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh);
-extern ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh);
-extern ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh);
-
-extern void ald_crypt_irq_handler(crypt_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup CRYPT_Public_Functions_Group4
-  * @{
-  */
-extern void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state);
-extern flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag);
-extern void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag);
-extern it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it);
-/**
-  * @}
-  */
-
-/** @addtogroup CRYPT_Public_Functions_Group5
-  * @{
-  */
-extern crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_dac.h

@@ -1,321 +0,0 @@
-/**
-  ******************************************************************************
- * @file    ald_dac.h
- * @brief   Header file of DAC Module library.
- *
- * @version V1.0
- * @date    28 Jun 2019
- * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          28 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
- */
-
-#ifndef __ALD_DAC_H__
-#define __ALD_DAC_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup DAC
-  * @{
-  */
-
-/** @defgroup DAC_Pubulic_Types DAC Pubulic Types
-  * @{
-  */
-/**
-  * @brief DAC channel
-  */
-typedef enum {
-	DAC_CHANNEL_0    = 1U,	/**< DAC channel 0 */
-	DAC_CHANNEL_1    = 2U,	/**< DAC channel 1 */
-	DAC_CHANNEL_COMB = 3U,	/**< DAC channel 0 and 1 */
-} dac_channel_t;
-
-/**
-  * @brief DAC convert mode
-  */
-typedef enum {
-	DAC_CONV_MODE_CONTINUOUS = 0U,	/**< DAC set in continuous mode */
-	DAC_CONV_MODE_SAMPLEHOLD = 1U,	/**< DAC set in sample/hold mode */
-	DAC_CONV_MODE_SAMPLEOFF  = 2U,	/**< DAC set in sample/shut off mode */
-} dac_conv_mode_t;
-
-/**
-  * @brief DAC out mode
-  */
-typedef enum {
-	DAC_OUTPUT_DISABLE = 0U,	/**< DAC output disable */
-	DAC_OUTPUT_PIN     = 1U,	/**< DAC output to pin enable */
-	DAC_OUTPUT_ADC     = 2U,	/**< DAC output to adc and acmp enable */
-	DAC_OUTPUT_PIN_ADC = 3U,	/**< DAC output to pin, adc and acmp enable */
-} dac_out_mode_t;
-
-/**
-  * @brief DAC pis input channel
-  */
-typedef enum {
-	DAC_PIS_CH_0  = 0U,	/**< PIS channel 0 triggers DAC channel conversion */
-	DAC_PIS_CH_1  = 1U,	/**< PIS channel 1 triggers DAC channel conversion */
-	DAC_PIS_CH_2  = 2U,	/**< PIS channel 2 triggers DAC channel conversion */
-	DAC_PIS_CH_3  = 3U,	/**< PIS channel 3 triggers DAC channel conversion */
-	DAC_PIS_CH_4  = 4U,	/**< PIS channel 4 triggers DAC channel conversion */
-	DAC_PIS_CH_5  = 5U,	/**< PIS channel 5 triggers DAC channel conversion */
-	DAC_PIS_CH_6  = 6U,	/**< PIS channel 6 triggers DAC channel conversion */
-	DAC_PIS_CH_7  = 7U,	/**< PIS channel 7 triggers DAC channel conversion */
-	DAC_PIS_CH_8  = 8U,	/**< PIS channel 8 triggers DAC channel conversion */
-	DAC_PIS_CH_9  = 9U,	/**< PIS channel 9 triggers DAC channel conversion */
-	DAC_PIS_CH_10 = 10U,	/**< PIS channel 10 triggers DAC channel conversion */
-	DAC_PIS_CH_11 = 11U,	/**< PIS channel 11 triggers DAC channel conversion */
-} dac_pissel_t;
-
-/**
-  * @brief DAC negative reference voltage definition
-  */
-typedef enum {
-	DAC_NEG_REF_VSS   = 0x0U,	/**< DAC negative regerence voltage vss */
-	DAC_NEG_REF_VREFN = 0x1U,	/**< DAC negative regerence voltage vrefn */
-} dac_neg_ref_t;
-
-/**
-  * @brief DAC positive reference voltage definition
-  */
-typedef enum {
-	DAC_POS_REF_VDD        = 0x0U,	/**< DAC posotove reference is VDD */
-	DAC_POS_REF_2V         = 0x1U,	/**< DAC posotove reference is internal 2V */
-	DAC_POS_REF_VREEFP     = 0x2U,	/**< DAC posotove reference is VREEFP */
-	DAC_POS_REF_VREEFP_BUF = 0x3U,	/**< DAC posotove reference is VREEFP BUFFER */
-} dac_pos_ref_t;
-
-/**
-  * @brief Refresh interval select
-  */
-typedef enum {
-	DAC_REFRESH_8  = 0U,	/**< Channel refreshed every 8 cycles */
-	DAC_REFRESH_16 = 1U,	/**< Channel refreshed every 16 cycles */
-	DAC_REFRESH_32 = 2U,	/**< Channel refreshed every 32 cycles */
-	DAC_REFRESH_64 = 3U,	/**< Channel refreshed every 64 cycles */
-} dac_refresh_t;
-
-/**
-  * @brief DAC prescale
-  */
-typedef enum {
-	DAC_PRES_DIV_1   = 0U,	/**< No division */
-	DAC_PRES_DIV_2   = 1U,	/**< 2 clock division */
-	DAC_PRES_DIV_4   = 2U,	/**< 4 clock division */
-	DAC_PRES_DIV_8   = 3U,	/**< 8 clock division */
-	DAC_PRES_DIV_16  = 4U,	/**< 16 clock division */
-	DAC_PRES_DIV_32  = 5U,	/**< 32 clock division */
-	DAC_PRES_DIV_64  = 6U,	/**< 64 clock division */
-	DAC_PRES_DIV_128 = 7U,	/**< 128 clock division */
-} dac_prescale_div_t;
-
-/**
-  * @brief DAC output trigger select
-  */
-typedef enum {
-	DAC_TRIGGER_BY_DATA = 0U,	/**< Channel is triggered by CHxDATA or COMBDATA write */
-	DAC_TRIGGER_BY_PIS  = 1U,	/**< Channel is triggered by PIS input */
-} dac_trigger_t;
-
-/**
-  * @brief DAC interrupt type
-  */
-typedef enum {
-	DAC_IT_CH0    = (1U << 0),	/**< Channel 0 conversion complete interrupt */
-	DAC_IT_CH1    = (1U << 1),	/**< Channel 1 conversion complete interrupt */
-	DAC_IT_CH0_UF = (1U << 4),	/**< Channel 0 data underflow interrupt */
-	DAC_IT_CH1_UF = (1U << 5),	/**< Channel 1 data underflow interrupt */
-} dac_it_t;
-
-/**
-  * @brief DAC interrupt flag type
-  */
-typedef enum {
-	DAC_FLAG_CH0    = (1U << 0),	/**< Channel 0 conversion complete interrupt flag */
-	DAC_FLAG_CH1    = (1U << 1),	/**< Channel 1 conversion complete interrupt flag */
-	DAC_FLAG_CH0_UF = (1U << 4),	/**< Channel 0 data underflow interrupt flag */
-	DAC_FLAG_CH1_UF = (1U << 5),	/**< Channel 1 data underflow interrupt flag */		
-} dac_flag_t;
-
-/**
-  * @brief DAC state flag
-  */
-typedef enum {
-	DAC_CH0_BSY = (1U << 0),	/**< Channel_0 is BUSY */
-	DAC_CH1_BSY = (1U << 1),	/**< Channel_1 is BUSY */
-} dac_status_t;
-
-/**
-  * @brief DAC init structure definition
-  */
-typedef struct {
-	dac_conv_mode_t conv_mode;	/**< Conversion mode */
-	dac_out_mode_t out_mode;	/**< Select output mode */
-	dac_refresh_t refresh;		/**< Refresh interval select */
-	dac_prescale_div_t div;		/**< Prescaler setting */
-	type_func_t ch0_reset;		/**< Select if prescaler is reset on channel 0 start */
-	type_func_t o_ctrl_pis;		/**< Enable pis control of dac output enable */
-	type_func_t sine;		/**< Sine mode enable/disable */
-	type_func_t diff;		/**< Differential mode enable/disable */
-	dac_neg_ref_t n_ref;		/**< The negative reference voltage select */
-	dac_pos_ref_t p_ref;		/**< The positive reference voltage select */
-} dac_init_t;
-
-/**
-  * @brief DAC channel initialize structure definition
-  */
-typedef struct {
-	type_func_t enable;	/**< DAC channel output enable/disable */
-	dac_trigger_t trigger;	/**< Select channel conversion trigger */
-	type_func_t refresh_en;	/**< Set automatic refresh of channel function */
-	dac_pissel_t pis_ch;	/**< Select channel pis input channel */
-} dac_channel_config_t;
-
-/**
-  * @brief  DAC handle Structure definition
-  */
-typedef struct dac_handle_s {
-	DAC_TypeDef *perh;	/**< Register base address */
-	dac_init_t init;	/**< DAC initialize parameters */
-	lock_state_t lock;	/**< Locking object */
-
-	void (*cbk)(struct dac_handle_s *arg, uint32_t event);	/**< DAC event callback */
-} dac_handle_t;
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Public_Macros DAC Public Macros
-  * @{
-  */
-#define DAC_CH0_ENABLE()	(SET_BIT(DAC0->CH0CTRL, DAC_CH0CTRL_EN_MSK))
-#define DAC_CH1_ENABLE()	(SET_BIT(DAC0->CH1CTRL, DAC_CH1CTRL_EN_MSK))
-#define DAC_CH0_DISABLE()	(CLEAR_BIT(DAC0->CH0CTRL, DAC_CH0CTRL_EN_MSK))
-#define DAC_CH1_DISABLE()	(CLEAR_BIT(DAC0->CH1CTRL, DAC_CH1CTRL_EN_MSK))
-
-#define DAC_EVENT_CH0_CPLT	0x0
-#define DAC_EVENT_CH1_CPLT	0x1
-#define DAC_EVENT_CH0_UF	0x2
-#define DAC_EVENT_CH1_UF	0x3
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Private_Macros DAC Private Macros
-  * @{
-  */
-#define IS_DAC_TYPE(x)			((x) == DAC0)
-#define IS_DAC_CONVERT_TYPE(x)		(((x) == DAC_CONV_MODE_CONTINUOUS) || \
-					 ((x) == DAC_CONV_MODE_SAMPLEHOLD) || \
-					 ((x) == DAC_CONV_MODE_SAMPLEOFF))
-#define IS_DAC_OUTPUT_TYPE(x)		(((x) == DAC_OUTPUT_DISABLE) || \
-					 ((x) == DAC_OUTPUT_PIN)     || \
-					 ((x) == DAC_OUTPUT_ADC)     || \
-					 ((x) == DAC_OUTPUT_PIN_ADC))
-#define IS_DAC_NEG_REFRESH_TYPE(x)	(((x) == DAC_NEG_REF_VSS)  || \
-					 ((x) == DAC_NEG_REF_VREFN))
-#define IS_DAC_POS_REFRESH_TYPE(x)	(((x) == DAC_POS_REF_VDD)  || \
-					 ((x) == DAC_POS_REF_2V) || \
-					 ((x) == DAC_POS_REF_VREEFP) || \
-					 ((x) == DAC_POS_REF_VREEFP_BUF))
-#define IS_DAC_REFRESH_TYPE(x)		(((x) == DAC_REFRESH_8)  || \
-					 ((x) == DAC_REFRESH_16) || \
-					 ((x) == DAC_REFRESH_32) || \
-					 ((x) == DAC_REFRESH_64))
-#define IS_DAC_CHANNEL_TYPE(x)		(((x) == DAC_CHANNEL_0) || \
-					 ((x) == DAC_CHANNEL_1) || \
-					 ((x) == DAC_CHANNEL_COMB))
-#define IS_DAC_PRESCALE_TYPE(x)		(((x) == DAC_PRES_DIV_1) || \
-					 ((x) == DAC_PRES_DIV_2) || \
-					 ((x) == DAC_PRES_DIV_4) || \
-					 ((x) == DAC_PRES_DIV_8) || \
-					 ((x) == DAC_PRES_DIV_16) || \
-					 ((x) == DAC_PRES_DIV_32) || \
-					 ((x) == DAC_PRES_DIV_64) || \
-					 ((x) == DAC_PRES_DIV_128))
-#define IS_DAC_INTERRUPT_TYPE(x)	(((x) == DAC_IT_CH0)    || \
-					 ((x) == DAC_IT_CH1)    || \
-					 ((x) == DAC_IT_CH0_UF) || \
-					 ((x) == DAC_IT_CH1_UF))
-#define IS_DAC_FLAG_TYPE(x)		(((x) == DAC_FLAG_CH0)    || \
-					 ((x) == DAC_FLAG_CH1)    || \
-					 ((x) == DAC_FLAG_CH0_UF) || \
-					 ((x) == DAC_FLAG_CH1_UF))
-#define IS_DAC_PISSEL_CH_TYPE(x)	(((x) == DAC_PIS_CH_0)  || \
-					 ((x) == DAC_PIS_CH_1)  || \
-					 ((x) == DAC_PIS_CH_2)  || \
-					 ((x) == DAC_PIS_CH_3)  || \
-					 ((x) == DAC_PIS_CH_4)  || \
-					 ((x) == DAC_PIS_CH_5)  || \
-					 ((x) == DAC_PIS_CH_6)  || \
-					 ((x) == DAC_PIS_CH_7)  || \
-					 ((x) == DAC_PIS_CH_8)  || \
-					 ((x) == DAC_PIS_CH_9)  || \
-					 ((x) == DAC_PIS_CH_10) || \
-					 ((x) == DAC_PIS_CH_11))
-#define IS_DAC_STATUS_TYPE(x)		(((x) == DAC_CH0_BSY) || \
-					 ((x) == DAC_CH1_BSY))
-#define IS_DAC_TRIGGER_TYPE(x)		(((x) == DAC_TRIGGER_BY_DATA) || \
-					 ((x) == DAC_TRIGGER_BY_PIS))
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Public_Functions
-  * @{
-  */
-ald_status_t ald_dac_reset(dac_handle_t *hperh);
-ald_status_t ald_dac_init(dac_handle_t *hperh);
-ald_status_t ald_dac_channel_config(dac_handle_t *hperh, dac_channel_config_t *config, dac_channel_t ch);
-void ald_dac_output_set(dac_handle_t *hperh, dac_channel_t ch, uint32_t value);
-flag_status_t ald_dac_get_status(dac_handle_t *hperh, dac_status_t status);
-void ald_dac_interrupt_config(dac_handle_t *hperh, dac_it_t it, type_func_t state);
-it_status_t ald_dac_get_it_status(dac_handle_t *hperh, dac_it_t it);
-flag_status_t ald_dac_get_flag_status(dac_handle_t *hperh, dac_flag_t flag);
-flag_status_t ald_dac_get_mask_flag_status(dac_handle_t *hperh, dac_flag_t flag);
-void ald_dac_clear_flag_status(dac_handle_t *hperh, dac_flag_t flag);
-void ald_dac_irq_handler(dac_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
- extern "C" }
-#endif
-
-#endif /* __ALD_DAC_H */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_dbgc.h

@@ -1,172 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_dbgc.h
-  * @brief   DEBUGCON module driver.
-  *
-  * @version V1.0
-  * @date    04 Jun 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          04 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_DBGC_H__
-#define __ALD_DBGC_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup DBGC DBGC
-  * @brief DBGC module driver
-  * @{
-  */
-
-
-
-/** @defgroup DBGC_Public_Types DBGC Public Types
-  * @{
-  */
-/**
-  * @brief Debug mode select
-  */
-typedef enum {
-	DEBC_MODE_SLEEP   = (1U << 0),	/**< Sleep mode */
-	DEBC_MODE_STOP1   = (1U << 1),	/**< STOP1 mode */
-	DEBC_MODE_STOP2   = (1U << 2),	/**< STOP2 mode */
-	DEBC_MODE_STANDBY = (1U << 3),	/**< Standby mode */
-} dbgc_mode_t;
-
-/**
-  * @brief Debug peripheral select
-  */
-typedef enum {
-	DEBC_PERH_TIMER0  = (1U << 0),			/**< AD16C4T0 */
-	DEBC_PERH_TIMER1  = (1U << 1),			/**< BS16T0 */
-	DEBC_PERH_TIMER2  = (1U << 2),			/**< GP16C2T0 */
-	DEBC_PERH_TIMER3  = (1U << 3),			/**< GP16C2T1 */
-	DEBC_PERH_TIMER4  = (1U << 4),			/**< BS16T1 */
-	DEBC_PERH_TIMER5  = (1U << 5),			/**< BS16T2 */
-	DEBC_PERH_TIMER6  = (1U << 6),			/**< GP16C4T0 */
-	DEBC_PERH_TIMER7  = (1U << 7),			/**< BS16T3 */
-	DEBC_PERH_I2C0    = (1U << 8),			/**< I2C0 SMBUS */
-	DEBC_PERH_I2C1    = (1U << 9),			/**< I2C1 SMBUS */
-	DEBC_PERH_CAN     = (1U << 12),			/**< CAN */
-	DEBC_PERH_LPTIM0  = (1U << 0)  | (1U << 16),	/**< LPTIM0 */
-	DEBC_PERH_IWDT    = (1U << 8)  | (1U << 16),	/**< IWDT */
-	DEBC_PERH_WWDT    = (1U << 9)  | (1U << 16),	/**< WWDT */
-	DEBC_PERH_RTC     = (1U << 10) | (1U << 16),	/**< RTC */
-} dbgc_perh_t;
-/**
-  * @}
-  */
-
-/** @defgroup DBGC_Public_Functions DBGC Public Functions
-  * @{
-  */
-/**
-  * @brief  Gets version.
-  * @retval Version
-  */
-__INLINE uint32_t ald_dbgc_get_rev_id(void)
-{
-	return (DBGC->IDCODE >> 16);
-}
-
-/**
-  * @brief  Gets core id.
-  * @retval Core id
-  */
-__INLINE uint32_t ald_dbgc_get_core_id(void)
-{
-	return (DBGC->IDCODE >> 12) & 0xF;
-}
-
-/**
-  * @brief  Gets device id
-  * @retval device id
-  */
-__INLINE uint32_t ald_dbgc_get_device_id(void)
-{
-	return DBGC->IDCODE & 0xFFF;
-}
-
-/**
-  * @brief  Configures low power debug mode
-  * @param  mode: The mode of low power.
-  * @param  state: ENABLE/DISABLE
-  * @retval None
-  */
-__INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state)
-{
-	if (state)
-		SET_BIT(DBGC->CR, mode);
-	else
-		CLEAR_BIT(DBGC->CR, mode);
-}
-
-/**
-  * @brief  Configures peripheral debug mode
-  * @param  perh: The peripheral.
-  * @param  state: ENABLE/DISABLE
-  * @retval None
-  */
-__INLINE void ald_dbgc_perh_config(dbgc_perh_t perh, type_func_t state)
-{
-	if ((perh >> 16) & 0x1) {
-		if (state)
-			SET_BIT(DBGC->APB2FZ, perh);
-		else
-			CLEAR_BIT(DBGC->APB2FZ, perh);
-	}
-	else {
-		if (state)
-			SET_BIT(DBGC->APB1FZ, perh);
-		else
-			CLEAR_BIT(DBGC->APB1FZ, perh);
-	}
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_dma.h

@@ -1,446 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_dma.h
-  * @brief   DMA module Library.
-  *
-  * @version V1.0
-  * @date    09 Nov 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          09 Nov 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_DMA_H__
-#define __ALD_DMA_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup DMA
-  * @{
-  */
-
-/**
-  * @defgroup DMA_Public_Macros DMA Public Macros
-  * @{
-  */
-#define DMA_CH_COUNT	12U
-#define DMA_ERR		31U
-/**
-  * @}
-  */
-
-/**
-  * @defgroup DMA_Public_Types DMA Public Types
-  * @{
-  */
-
-/**
-  * @brief Input source to DMA channel
-  * @verbatim
-      In this module, for the convenience of code maintenance,
-      TIMERx is used to indicate the sequence of the timer peripheral.
-      Different product series TIMERx represent different meanings:
-      1. For ES32F36xx series:
-      TIMER0 ----> AD16C4T0
-      TIMER1 ----> AD16C4T1
-      TIMER2 ----> GP32C4T0
-      TIMER3 ----> GP32C4T1
-      TIMER4 ----> BS16T0
-      TIMER5 ----> BS16T1
-      TIMER6 ----> GP16C4T0
-      TIMER7 ----> GP16C4T1
-
-      2. For ES32F393x/ES32F336x/ES32F392x series:
-      TIMER0 ----> GP16C4T0
-      TIMER1 ----> GP16C4T1
-      TIMER2 ----> GP32C4T0
-      TIMER3 ----> GP32C4T1
-      TIMER4 ----> BS16T0
-      TIMER5 ----> BS16T1
-      TIMER6 ----> GP16C4T2
-      TIMER7 ----> GP16C4T3
-    @endverbatim
-  */
-typedef enum {
-	DMA_MSEL_NONE    = 0x0U,	/**< NONE */
-	DMA_MSEL_GPIO    = 0x1U,	/**< GPIO */
-	DMA_MSEL_CRYPT   = 0x2U,	/**< CRYPT */
-	DMA_MSEL_DAC0    = 0x4U,	/**< DAC0 */
-	DMA_MSEL_ADC0    = 0x6U,	/**< ADC0 */
-	DMA_MSEL_CRC     = 0x7U,	/**< CRC */
-	DMA_MSEL_UART0   = 0x8U,	/**< UART0 */
-	DMA_MSEL_UART1   = 0x9U,	/**< UART1 */
-	DMA_MSEL_UART2   = 0xAU,	/**< UART2 */
-	DMA_MSEL_UART3   = 0xBU,	/**< UART3 */
-	DMA_MSEL_UART4   = 0xCU,	/**< UART4 */
-	DMA_MSEL_UART5   = 0xDU,	/**< UART5 */
-	DMA_MSEL_SPI0    = 0xEU,	/**< SPI0 */
-	DMA_MSEL_SPI1    = 0xFU,	/**< SPI1 */
-	DMA_MSEL_I2C0    = 0x10U,	/**< I2C0 */
-	DMA_MSEL_I2C1    = 0x11U,	/**< I2C1 */
-	DMA_MSEL_TIMER0  = 0x12U,	/**< TIMER0 */
-	DMA_MSEL_TIMER1  = 0x13U,	/**< TIMER1 */
-	DMA_MSEL_TIMER2  = 0x14U,	/**< TIMER2 */
-	DMA_MSEL_TIMER3  = 0x15U,	/**< TIMER3 */
-	DMA_MSEL_LPUART0 = 0x18U,	/**< LPUART0 */
-	DMA_MSEL_SPI2    = 0x1AU,	/**< SPI2 */
-	DMA_MSEL_TIMER4  = 0x1BU,	/**< TIMER4 */
-	DMA_MSEL_TIMER5  = 0x1CU,	/**< TIMER5 */
-	DMA_MSEL_TIMER6  = 0x1DU,	/**< TIMER6 */
-	DMA_MSEL_TIMER7  = 0x1EU,	/**< TIMER7 */
-	DMA_MSEL_ADC1    = 0x1FU,	/**< ADC1 */
-	DMA_MSEL_PIS     = 0x20U,	/**< PIS */
-	DMA_MSEL_TRNG    = 0x21U,	/**< TRNG */
-	DMA_MSEL_QSPI    = 0x22U,	/**< QSPI */
-	DMA_MSEL_USB     = 0x23U,	/**< USB */
-} dma_msel_t;
-
-/**
-  * @brief Input signal to DMA channel
-  */
-typedef enum {
-	DMA_MSIGSEL_NONE           = 0x0U,	/**< NONE */
-	DMA_MSIGSEL_EXTI_0         = 0x0U,	/**< External interrupt 0 */
-	DMA_MSIGSEL_EXTI_1         = 0x1U,	/**< External interrupt 1 */
-	DMA_MSIGSEL_EXTI_2         = 0x2U,	/**< External interrupt 2 */
-	DMA_MSIGSEL_EXTI_3         = 0x3U,	/**< External interrupt 3 */
-	DMA_MSIGSEL_EXTI_4         = 0x4U,	/**< External interrupt 4 */
-	DMA_MSIGSEL_EXTI_5         = 0x5U,	/**< External interrupt 5 */
-	DMA_MSIGSEL_EXTI_6         = 0x6U,	/**< External interrupt 6 */
-	DMA_MSIGSEL_EXTI_7         = 0x7U,	/**< External interrupt 7 */
-	DMA_MSIGSEL_EXTI_8         = 0x8U,	/**< External interrupt 8 */
-	DMA_MSIGSEL_EXTI_9         = 0x9U,	/**< External interrupt 9 */
-	DMA_MSIGSEL_EXTI_10        = 0xAU,	/**< External interrupt 10 */
-	DMA_MSIGSEL_EXTI_11        = 0xBU,	/**< External interrupt 11 */
-	DMA_MSIGSEL_EXTI_12        = 0xCU,	/**< External interrupt 12 */
-	DMA_MSIGSEL_EXTI_13        = 0xDU,	/**< External interrupt 13 */
-	DMA_MSIGSEL_EXTI_14        = 0xEU,	/**< External interrupt 14 */
-	DMA_MSIGSEL_EXTI_15        = 0xFU,	/**< External interrupt 15 */
-	DMA_MSIGSEL_CRYPT_WRITE    = 0x0U,	/**< CRYPT write mode */
-	DMA_MSIGSEL_CRYPT_READ     = 0x1U,	/**< CRYPT read mode */
-	DMA_MSIGSEL_DAC0_CH0       = 0x0U,	/**< DAC0 channel 0 complete */
-	DMA_MSIGSEL_DAC0_CH1       = 0x1U,	/**< DAC0 channel 1 complete */
-	DMA_MSIGSEL_ADC       	   = 0x0U,	/**< ADC mode */
-	DMA_MSIGSEL_UART_TXEMPTY   = 0x0U,	/**< UART0/UART1/UART2/UART3 transmit */
-	DMA_MSIGSEL_UART_RNR       = 0x1U,	/**< UART0/UART1/UART2/UART3 receive */
-	DMA_MSIGSEL_UART45_RNR     = 0x0U,	/**< UART4/UART5 reveive */
-	DMA_MSIGSEL_UART45_TXEMPTY = 0x1U,	/**< UART4/UART5 transmit */
-	DMA_MSIGSEL_SPI_RNR        = 0x0U,	/**< SPI receive */
-	DMA_MSIGSEL_SPI_TXEMPTY    = 0x1U,	/**< SPI transmit */
-	DMA_MSIGSEL_I2C_RNR        = 0x0U,	/**< I2C receive */
-	DMA_MSIGSEL_I2C_TXEMPTY    = 0x1U,	/**< I2C transmit */
-	DMA_MSIGSEL_TIMER_CH1      = 0x0U,	/**< TIM channal 1 */
-	DMA_MSIGSEL_TIMER_CH2      = 0x1U,	/**< TIM channal 2 */
-	DMA_MSIGSEL_TIMER_CH3      = 0x2U,	/**< TIM channal 3 */
-	DMA_MSIGSEL_TIMER_CH4      = 0x3U,	/**< TIM channal 4 */
-	DMA_MSIGSEL_TIMER_TRI      = 0x4U,	/**< TIM trigger */
-	DMA_MSIGSEL_TIMER_COMP     = 0x5U,	/**< TIM compare */
-	DMA_MSIGSEL_TIMER_UPDATE   = 0x6U,	/**< TIM update */
-	DMA_MSIGSEL_LPUART_RNR     = 0x0U,	/**< LPUART receive */
-	DMA_MSIGSEL_LPUART_TXEMPTY = 0x1U,	/**< LPUART transmit */
-	DMA_MSIGSEL_PIS_CH0        = 0x0U,	/**< PIS channal 0 */
-	DMA_MSIGSEL_PIS_CH1        = 0x1U,	/**< PIS channal 1 */
-	DMA_MSIGSEL_PIS_CH2        = 0x2U,	/**< PIS channal 2 */
-	DMA_MSIGSEL_PIS_CH3        = 0x3U,	/**< PIS channal 3 */
-	DMA_MSIGSEL_PIS_CH4        = 0x4U,	/**< PIS channal 4 */
-	DMA_MSIGSEL_PIS_CH5        = 0x5U,	/**< PIS channal 5 */
-	DMA_MSIGSEL_PIS_CH6        = 0x6U,	/**< PIS channal 6 */
-	DMA_MSIGSEL_PIS_CH7        = 0x7U,	/**< PIS channal 7 */
-	DMA_MSIGSEL_PIS_CH8        = 0x8U,	/**< PIS channal 8 */
-	DMA_MSIGSEL_PIS_CH9        = 0x9U,	/**< PIS channal 9 */
-	DMA_MSIGSEL_PIS_CH10       = 0xAU,	/**< PIS channal 10 */
-	DMA_MSIGSEL_PIS_CH11       = 0xBU,	/**< PIS channal 11 */
-	DMA_MSIGSEL_PIS_CH12       = 0xCU,	/**< PIS channal 12 */
-	DMA_MSIGSEL_PIS_CH13       = 0xDU,	/**< PIS channal 13 */
-	DMA_MSIGSEL_PIS_CH14       = 0xEU,	/**< PIS channal 14 */
-	DMA_MSIGSEL_PIS_CH15       = 0xFU,	/**< PIS channal 15 */
-	DMA_MSIGSEL_QSPI_WRITE     = 0x0U,	/**< QSPI Write */
-	DMA_MSIGSEL_QSPI_READ      = 0x1U,	/**< QSPI Read */
-	DMA_MSIGSEL_EP_TX1         = 0x0U,	/**< USB TX Endport 0 */
-	DMA_MSIGSEL_EP_TX2         = 0x1U,	/**< USB TX Endport 1 */
-	DMA_MSIGSEL_EP_TX3         = 0x2U,	/**< USB TX Endport 2 */
-	DMA_MSIGSEL_EP_TX4         = 0x3U,	/**< USB TX Endport 3 */
-	DMA_MSIGSEL_EP_TX5         = 0x4U,	/**< USB TX Endport 4 */
-	DMA_MSIGSEL_EP_RX1         = 0x8U,	/**< USB RX Endport 0 */
-	DMA_MSIGSEL_EP_RX2         = 0x9U,	/**< USB RX Endport 1 */
-	DMA_MSIGSEL_EP_RX3         = 0xAU,	/**< USB RX Endport 2 */
-	DMA_MSIGSEL_EP_RX4         = 0xBU,	/**< USB RX Endport 3 */
-	DMA_MSIGSEL_EP_RX5         = 0xCU,	/**< USB RX Endport 4 */	
-} dma_msigsel_t;
-
-/**
-  * @brief DMA Descriptor control type
-  */
-typedef union {
-	struct {
-		uint32_t cycle_ctrl    :3;	/**< DMA operating mode @ref dma_cycle_ctrl_t */
-		uint32_t next_useburst :1;	/**< Uses the alternate data structure when complete a DMA cycle */
-		uint32_t n_minus_1     :10;	/**< Represent the total number of DMA transfers that DMA cycle contains. */
-		uint32_t R_power       :4;	/**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
-		uint32_t src_prot_ctrl :3;	/**< Control the state of HPROT when reads the source data. */
-		uint32_t dst_prot_ctrl :3;	/**< Control the state of HPROT when writes the destination data */
-		uint32_t src_size      :2;	/**< Source data size @ref dma_data_size_t */
-		uint32_t src_inc       :2;	/**< Control the source address increment. @ref dma_data_inc_t */
-		uint32_t dst_size      :2;	/**< Destination data size. @ref dma_data_size_t */
-		uint32_t dst_inc       :2;	/**< Destination address increment. @ref dma_data_inc_t */
-	};
-	uint32_t word;
-} dma_ctrl_t;
-
-/**
-  * @brief Channel control data structure
-  */
-typedef struct {
-	void *src;		/**< Source data end pointer */
-	void *dst;		/**< Destination data end pointer */
-	dma_ctrl_t ctrl;	/**< Control data configuration @ref dma_ctrl_t */
-	uint32_t use;		/**< Reserve for user */
-} dma_descriptor_t;
-
-/**
-  * @brief data increment
-  */
-typedef enum {
-	DMA_DATA_INC_BYTE     = 0x0U,	/**< Address increment by byte */
-	DMA_DATA_INC_HALFWORD = 0x1U,	/**< Address increment by halfword */
-	DMA_DATA_INC_WORD     = 0x2U,	/**< Address increment by word */
-	DMA_DATA_INC_NONE     = 0x3U,	/**< No increment */
-} dma_data_inc_t;
-
-/**
-  * @brief Data size
-  */
-typedef enum {
-	DMA_DATA_SIZE_BYTE     = 0x0U,	/**< Byte */
-	DMA_DATA_SIZE_HALFWORD = 0x1U,	/**< Halfword */
-	DMA_DATA_SIZE_WORD     = 0x2U,	/**< Word */
-} dma_data_size_t;
-
-/**
-  * @brief The operating mode of the DMA cycle
-  */
-typedef enum {
-	DMA_CYCLE_CTRL_NONE             = 0x0U,	/**< Stop */
-	DMA_CYCLE_CTRL_BASIC            = 0x1U,	/**< Basic */
-	DMA_CYCLE_CTRL_AUTO             = 0x2U,	/**< Auto-request */
-	DMA_CYCLE_CTRL_PINGPONG         = 0x3U,	/**< Ping-pong */
-	DMA_CYCLE_CTRL_MEM_SG_PRIMARY   = 0x4U,	/**< Memory scatter-gather using the primary structure */
-	DMA_CYCLE_CTRL_MEM_SG_ALTERNATE = 0x5U,	/**< Memory scatter-gather using the alternate structure */
-	DMA_CYCLE_CTRL_PER_SG_PRIMARY   = 0x6U,	/**< Peripheral scatter-gather using the primary structure */
-	DMA_CYCLE_CTRL_PER_SG_ALTERNATE = 0x7U,	/**< Peripheral scatter-gather using the alternate structure */
-} dma_cycle_ctrl_t;
-
-/**
-  * @brief Control how many DMA transfers can occur
-  *        before the controller re-arbitrates
-  */
-typedef enum {
-	DMA_R_POWER_1    = 0x0U,	/**< Arbitrates after each DMA transfer */
-	DMA_R_POWER_2    = 0x1U,	/**< Arbitrates after 2 DMA transfer */
-	DMA_R_POWER_4    = 0x2U,	/**< Arbitrates after 4 DMA transfer */
-	DMA_R_POWER_8    = 0x3U,	/**< Arbitrates after 8 DMA transfer */
-	DMA_R_POWER_16   = 0x4U,	/**< Arbitrates after 16 DMA transfer */
-	DMA_R_POWER_32   = 0x5U,	/**< Arbitrates after 32 DMA transfer */
-	DMA_R_POWER_64   = 0x6U,	/**< Arbitrates after 64 DMA transfer */
-	DMA_R_POWER_128  = 0x7U,	/**< Arbitrates after 128 DMA transfer */
-	DMA_R_POWER_256  = 0x8U,	/**< Arbitrates after 256 DMA transfer */
-	DMA_R_POWER_512  = 0x9U,	/**< Arbitrates after 512 DMA transfer */
-	DMA_R_POWER_1024 = 0xAU,	/**< Arbitrates after 1024 DMA transfer */
-} dma_arbiter_config_t;
-
-/**
-  * @brief Callback function pointer and param
-  */
-typedef struct {
-	void (*cplt_cbk)(void *arg);	/**< DMA transfers complete callback */
-	void (*err_cbk)(void* arg);	/**< DMA occurs error callback */
-	void *cplt_arg;			/**< The parameter of cplt_cbk() */
-	void *err_arg;			/**< The parameter of err_cbk() */
-} dma_call_back_t;
-
-/**
-  * @brief DMA channal configure structure
-  */
-typedef struct {
-	void *src;			/**< Source data begin pointer */
-	void *dst;			/**< Destination data begin pointer */
-	uint16_t size;			/**< The total number of DMA transfers that DMA cycle contains */
-	dma_data_size_t data_width;	/**< Data width, @ref dma_data_size_t */
-	dma_data_inc_t src_inc;		/**< Source increment type. @ref dma_data_inc_t */
-	dma_data_inc_t dst_inc;		/**< Destination increment type. @ref dma_data_inc_t */
-	dma_arbiter_config_t R_power;	/**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
-	type_func_t primary;		/**< Use primary descriptor or alternate descriptor */
-	type_func_t burst;		/**< Enable/Disable the useburst setting for this channel */
-	type_func_t high_prio;		/**< High priority or default priority */
-	type_func_t interrupt;		/**< Enable/disable interrupt */
-	dma_msel_t msel;		/**< Input source to DMA channel @ref dma_msel_t */
-	dma_msigsel_t msigsel;		/**< Input signal to DMA channel @ref dma_msigsel_t */
-	uint8_t channel;		/**< Channel index */
-} dma_config_t;
-
-/**
-  * @brief DMA handle structure definition
-  */
-typedef struct {
-	DMA_TypeDef *perh;		/**< DMA registers base address */
-	dma_config_t config;		/**< Channel configure structure. @ref dma_config_t */
-	void (*cplt_cbk)(void *arg);	/**< DMA transfers complete callback */
-	void (*err_cbk)(void *arg);	/**< DMA bus occurs error callback */
-	void *cplt_arg;			/**< The parameter of cplt_cbk() */
-	void *err_arg;			/**< The parameter of err_cbk() */
-} dma_handle_t;
-
-/**
-  * @brief Descriptor complete state
-  */
-typedef enum {
-	DMA_DESCP_CPLT_PRI = 0x0U,	/**< Primary descriptor has been completed */
-	DMA_DESCP_CPLT_ALT = 0x1U,	/**< Alternate descriptor has been completed */
-	DMA_DESCP_CPLT_ALL = 0x2U,	/**< Both primary and alternate descriptors have been completed */
-} dma_descrp_cplt_t;
-/**
-  * @}
-  */
-
-/**
-  * @defgroup DMA_Private_Macros DMA Private Macros
-  * @{
-  */
-#define IS_DMA_MSEL_TYPE(x)	((x) <= DMA_MSEL_USB)
-#define IS_DMA_MSIGSEL_TYPE(x)	((x) <= 0xF)
-#define IS_DMA_DATAINC_TYPE(x)  (((x) == DMA_DATA_INC_BYTE)     || \
-                                 ((x) == DMA_DATA_INC_HALFWORD) || \
-                                 ((x) == DMA_DATA_INC_WORD)     || \
-                                 ((x) == DMA_DATA_INC_NONE))
-#define IS_DMA_DATASIZE_TYPE(x)  (((x) == DMA_DATA_SIZE_BYTE)     || \
-                                  ((x) == DMA_DATA_SIZE_HALFWORD) || \
-                                  ((x) == DMA_DATA_SIZE_WORD))
-#define IS_CYCLECTRL_TYPE(x)  (((x) == DMA_CYCLE_CTRL_NONE)             || \
-                               ((x) == DMA_CYCLE_CTRL_BASIC)            || \
-                               ((x) == DMA_CYCLE_CTRL_AUTO)             || \
-                               ((x) == DMA_CYCLE_CTRL_PINGPONG)         || \
-                               ((x) == DMA_CYCLE_CTRL_MEM_SG_PRIMARY)   || \
-                               ((x) == DMA_CYCLE_CTRL_MEM_SG_ALTERNATE) || \
-                               ((x) == DMA_CYCLE_CTRL_PER_SG_PRIMARY)   || \
-                               ((x) == DMA_CYCLE_CTRL_PER_SG_ALTERNATE))
-#define IS_DMA_ARBITERCONFIG_TYPE(x)  (((x) == DMA_R_POWER_1)   || \
-                                       ((x) == DMA_R_POWER_2)   || \
-                                       ((x) == DMA_R_POWER_4)   || \
-                                       ((x) == DMA_R_POWER_8)   || \
-                                       ((x) == DMA_R_POWER_16)  || \
-                                       ((x) == DMA_R_POWER_32)  || \
-                                       ((x) == DMA_R_POWER_64)  || \
-                                       ((x) == DMA_R_POWER_128) || \
-                                       ((x) == DMA_R_POWER_256) || \
-                                       ((x) == DMA_R_POWER_512) || \
-                                       ((x) == DMA_R_POWER_1024))
-#define IS_DMA(x)		((x) == DMA0)
-#define IS_DMA_CHANNEL(x)	((x) <= 11)
-#define IS_DMA_DATA_SIZE(x)	((x) <= 1024)
-#define IS_DMA_IT_TYPE(x)	(((x) <= 11) || ((x) == 31))
-/**
-  * @}
-  */
-
-/**
-  * @addtogroup DMA_Public_Functions
-  * @{
-  */
-
-/** @addtogroup DMA_Public_Functions_Group1
-  * @{
-  */
-/* Initialization functions */
-extern void ald_dma_reset(DMA_TypeDef *DMAx);
-extern void ald_dma_init(DMA_TypeDef *DMAx);
-extern void ald_dma_config_struct(dma_config_t *p);
-extern void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory);
-/**
-  * @}
-  */
-
-
-/** @addtogroup DMA_Public_Functions_Group2
-  * @{
-  */
-/* Configure DMA channel functions */
-extern void ald_dma_config_auto(dma_handle_t *hperh);
-extern void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size);
-extern void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst,
-                                        uint16_t size, uint8_t channel, void (*cbk)(void *arg));
-extern void ald_dma_config_basic(dma_handle_t *hperh);
-extern void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size);
-extern void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel,
-                                 dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg));
-extern void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config,
-                                       uint8_t first, void (*cbk)(void *arg));
-extern void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc,
-                                       uint32_t nr, uint8_t channel, void (*cbk)(void *arg));
-extern void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst,
-                    dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg));
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Public_Functions_Group3
-  * @{
-  */
-/* DMA control functions */
-extern void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state);
-extern void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state);
-extern it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel);
-extern flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel);
-extern void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel);
-extern dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel);
-extern void ald_dma_irq_handler(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/*__ALD_DMA_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_ebi.h

@@ -1,602 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_ebi.h
-  * @brief   Header file of EBI module driver.
-  *
-  * @version V1.0
-  * @date    20 Nov 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          20 Nov 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-
-#ifndef __ALD_EBI_H__
-#define __ALD_EBI_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup EBI
-  * @{
-  */
-
-/**
-  * @defgroup EBI_Public_Macros EBI Public Macros
-  * @{
-  */
-#define EBI_NOR_SRAM_TypeDef		EBI_Bank1_TypeDef
-#define EBI_NOR_SRAM_EXTENDED_TypeDef	EBI_Bank1E_TypeDef
-#define EBI_NAND_TypeDef		EBI_Bank2_3_TypeDef
-#define EBI_LCD_TypeDef			EBI_Bank1_LCD_TypeDef
-#define EBI_NOR_SRAM_DEVICE		EBI_Bank1
-#define EBI_NOR_SRAM_EXTENDED_DEVICE	EBI_Bank1E
-#define EBI_NAND_DEVICE			EBI_Bank2_3
-#define EBI_LCD_DEVICE			EBI_Bank1_LCD
-#define EBI_NAND_BANK2			0x00000010U
-#define EBI_NAND_BANK3			0x00000100U
-
-/* PCTRLR register clear mask */
-#define PCTRLR_CLEAR_MASK    ((uint32_t)(EBI_PCTRLRx_WAITEN_MSK | EBI_PCTRLRx_MEMBKEN_MSK   | \
-                                      EBI_PCTRLRx_MEMTYP_MSK    | EBI_PCTRLRx_DATBUSWID_MSK | \
-                                      EBI_PCTRLRx_ECCEN_MSK     | EBI_PCTRLRx_CRDLY_MSK     | \
-                                      EBI_PCTRLRx_ARDLY_MSK     | EBI_PCTRLRx_ECCPSIZE_MSK))
-
-/* PMEMR register clear mask */
-#define PMEMR_CLEAR_MASK   ((uint32_t)(EBI_PMEMRx_MEMSETUP_MSK  | EBI_PMEMRx_MEMWAIT_MSK | \
-                                       EBI_PMEMRx_MEMHOLD_MSK   | EBI_PMEMRx_MEMHIZT_MSK))
-
-/* PATTR register clear mask */
-#define PATTR_CLEAR_MASK   ((uint32_t)(EBI_PATTRx_ATTSETUP_MSK  | EBI_PATTRx_ATTWAIT_MSK | \
-                                       EBI_PATTRx_ATTHOLD_MSK   | EBI_PATTRx_ATTHIZT_MSK))
-
-/* BCTRLR register clear mask */
-#define BCTRLR_CLEAR_MASK		((uint32_t)(EBI_BCTRLRx_FLASHACCEN_MSK  | EBI_BCTRLRx_MUXEN_MSK  | \
-                                                   EBI_BCTRLRx_MEMTYP_MSK    | EBI_BCTRLRx_MEMWID_MSK    | \
-                                                   EBI_BCTRLRx_BURSTEN_MSK   | EBI_BCTRLRx_WAITPOL_MSK   | \
-                                                   EBI_BCTRLRx_WRAPMODE_MSK  | EBI_BCTRLRx_WAITCFG_MSK   | \
-                                                   EBI_BCTRLRx_WREN_MSK      | EBI_BCTRLRx_WAITEN_MSK    | \
-                                                   EBI_BCTRLRx_EXTMODEN_MSK  | EBI_BCTRLRx_ASYNCWAIT_MSK | \
-                                                   EBI_BCTRLRx_RWCBURSTEN_MSK))
-/* BTR register clear mask */
-#define BTR_CLEAR_MASK                 ((uint32_t)(EBI_BTRx_ADDATASETUP_MSK | EBI_BTRx_ADDHOLD_MSK  | \
-                                                   EBI_BTRx_DATAHOLD_MSK    | EBI_BTRx_BUSTURN_MSK  | \
-                                                   EBI_BTRx_CLKDIV_MSK      | EBI_BTRx_DATALAT_MSK  | \
-                                                   EBI_BTRx_ACCMODE_MSK))
-
-/* BWRTR register clear mask */
-#define BWTR_CLEAR_MASK                ((uint32_t)(EBI_BWRTRx_ADDATASETUP_MSK | EBI_BWRTRx_ADDHOLD_MSK | \
-                                                   EBI_BWRTRx_DATAHOLD_MSK | EBI_BWRTRx_BUSTURN_MSK    | \
-                                                   EBI_BWRTRx_ACCMODE_MSK))
-
-#define LCDCTRL_CLEAR_MASK		((uint32_t)(EBI_LCDCTRLx_HSYNCPOL_POS | EBI_LCDCTRLx_VSYNCPOL_MSK | \
-						    EBI_LCDCTRLx_DENPOL_MSK   | EBI_LCDCTRLx_LCDEN_MSK	  | \
-						    EBI_LCDCTRLx_LCDINT_MSK   | EBI_LCDCTRLx_DCLKPOL_MSK  | \
-						    EBI_LCDCTRLx_DATASETUP_MSK))
-/**
-  * @}
-  */  
-
-/** @defgroup EBI_Public_Types EBI Public Types
-  * @{
-  */  
-
-/** 
-  * @brief EBI Access Mode
-  */
-typedef enum {
-	EBI_ACCESS_MODE_A = 0x0U,		/**< EBI access mode A */
-	EBI_ACCESS_MODE_B = (0x1U << 28),	/**< EBI access mode B */
-	EBI_ACCESS_MODE_C = (0x2U << 28),	/**< EBI access mode C */
-	EBI_ACCESS_MODE_D = (0x3U << 28),	/**< EBI access mode D */
-} ebi_access_mode_t;
-
-/**
-  * @brief EBI NORSRAM Timing parameters structure definition
-  */
-typedef struct {
-	uint32_t addr_setup;	/**< Address setup HCLK cycles number, the value between 0 and 15 */
-	uint32_t addr_hold;	/**< Address hold HCLK cycles number, the value between 0 and 15 */ 
-	uint32_t data_setup;	/**< Data setup HCLK cycles number, the value between 1 and 255 */ 
-	uint32_t bus_dur;	/**< Bus turnaround duration HCLK cycles, the value between 0 and 15 */
-	uint32_t div;		/**< Defines the period of CLK clock signal, the value between 2 and 16 */
-	uint32_t latency;	/**< Issue clock cycles before getting the first data, the value between  2 and 17 */
-	ebi_access_mode_t mode;	/**< Specifies the asynchronous access mode */
-} ald_ebi_nor_sram_timing_t;
-
-/** 
-  * @brief EBI_Wait_feature EBI Wait feature
-  */
-typedef enum {
-	EBI_NAND_WAIT_FEATURE_DISABLE = 0x0U,		/**< NAND wait feature disable */
-	EBI_NAND_WAIT_FEATURE_ENABLE  = (0x1U << 1),	/**< NAND wait feature enable */
-} ebi_nand_wait_feature_t;
-
-/** 
-  * @brief EBI NAND Data Width
-  */
-typedef enum {
-	EBI_NAND_MEM_BUS_WIDTH_8  = 0x0U,		/**< NAND mem bus width 8-bits */
-	EBI_NAND_MEM_BUS_WIDTH_16 = (0x3U << 4),	/**< NAND mem bus width 16-bits */
-} ebi_nand_mem_bus_width_t;
-
-/** 
-  * @brief EBI NAND ECC STATE
-  */
-typedef enum {
-	EBI_NAND_ECC_DISABLE = 0U,		/**< NAND ecc disable */
-	EBI_NAND_ECC_ENABLE  = (0x1U << 6),	/**< NAND ecc enable */
-} ebi_nand_ecc_t;
-
-/** 
-  * @brief EBI ECC Page Size
-  */
-typedef enum {
-	EBI_NAND_ECC_PAGE_SIZE_256BYTE  = 0U,		/**< NAND ecc page size 256 bytes */
-	EBI_NAND_ECC_PAGE_SIZE_512BYTE  = (0x1U << 17),	/**< NAND ecc page size 512 bytes */
-	EBI_NAND_ECC_PAGE_SIZE_1024BYTE = (0x2U << 17),	/**< NAND ecc page size 1024 bytes */
-	EBI_NAND_ECC_PAGE_SIZE_2048BYTE = (0x3U << 17),	/**< NAND ecc page size 2048 bytes */
-	EBI_NAND_ECC_PAGE_SIZE_4096BYTE = (0x4U << 17),	/**< NAND ecc page size 4096 bytes */
-	EBI_NAND_ECC_PAGE_SIZE_8192BYTE = (0x5U << 17),	/**< NAND ecc page size 8192 bytes */
-} ebi_md_ecc_page_size_t;
-
-/**
-  * @brief EBI NAND Configuration Structure definition
-  */
-typedef struct {
-	uint32_t bank;			/**< Specifies the NAND memory device that will be used */
-	ebi_nand_wait_feature_t wait;	/**< Enables or disables the Wait feature for the NAND Memory device */
-	ebi_nand_mem_bus_width_t width;	/**< Specifies the external memory device width */
-	ebi_nand_ecc_t ecc;		/**< Enables or disables the ECC computation */
-	ebi_md_ecc_page_size_t size;	/**< Defines the page size for the extended ECC */
-	uint32_t cle_time;		/**< Number of HCLK cycles between CLE low and RE low, the value between 0 and 255 */
-	uint32_t ale_time;		/**< Number of HCLK cycles between ALE low and RE low */
-} ald_ebi_nand_init_t;
-
-/**
-  * @brief EBI NAND Timing parameters structure definition
-  */
-typedef struct {
-	uint32_t time;		/**< Number of cycles to setup address, the value between 0 and 255 */
-	uint32_t wait_time;	/**< Number of HCLK cycles to assert the command ,the value between 0 and 255 */
-	uint32_t hold_time;	/**< Number of HCLK cycles to hold address or data, the value between 0 and 255 */
-	uint32_t hiz_time;	/**< Number of HCLK cycles data bus is kept in HiZ, the value between 0 and 255 */
-} ald_ebi_nand_timing_t;
-
-/** 
-  * @brief EBI Data Address Bus Multiplexing
-  */
-typedef enum {
-	EBI_DATA_ADDRESS_MUX_DISABLE = 0x0U,		/**< Data address mux disable */
-	EBI_DATA_ADDRESS_MUX_ENABLE  = (0x1U << 1),	/**< Data address mux enable */
-} ebi_data_address_mux_t;
-
-/** 
-  * @brief EBI NOR/SRAM Bank
-  */
-typedef enum {
-	EBI_NORSRAM_BANK1 = 0x0U,	/**< Norsram bank 1 */
-	EBI_NORSRAM_BANK2 = 0x2U,	/**< Norsram bank 2 */
-	EBI_NORSRAM_BANK3 = 0x4U,	/**< Norsram bank 3 */
-	EBI_NORSRAM_BANK4 = 0x6U,	/**< Norsram bank 4 */
-} ebi_norsram_bank_t;
-
-/** 
-  * @brief EBI Memory Type
-  */
-typedef enum {
-	EBI_MEMORY_TYPE_SRAM  = 0x0U,		/**< Memory tyepe SRAM */
-	EBI_MEMORY_TYPE_PSRAM = (0x1U << 2),	/**< Memory tyepe PSRAM */
-	EBI_MEMORY_TYPE_NOR   = (0x2U << 2),	/**< Memory tyepe NOR */
-} ebi_memory_type_t;
-
-/** 
-  * @brief EBI NOR/SRAM Data Width
-  */
-typedef enum {
-	EBI_NORSRAM_MEM_BUS_WIDTH_8  = 0x0U,		/**< Norsram Memory width 8-bits */
-	EBI_NORSRAM_MEM_BUS_WIDTH_16 = (0x1U << 4),	/**< Norsram Memory width 16-bits */
-	EBI_NORSRAM_MEM_BUS_WIDTH_32 = (0x2U << 4),	/**< Norsram Memory width 32-bits */
-} ebi_norsram_mem_bus_width_t;
-
-/** 
-  * @brief  EBI NOR/SRAM Flash Access
-  */
-typedef enum {
-	EBI_NORSRAM_FLASH_ACCESS_DISABLE = 0x0U,	/**< Norsram flash access disable */
-	EBI_NORSRAM_FLASH_ACCESS_ENABLE  = (0x1U << 6),	/**< Norsram flash access enable */
-} ebi_norsram_flash_access_t;
-
-/** 
-  * @brief EBI Burst Access Mode
-  */
-typedef enum {
-	EBI_BURST_ACCESS_MODE_DISABLE = 0x0U,		/**< Burst access disable */
-	EBI_BURST_ACCESS_MODE_ENABLE  = (0x1U << 8),	/**< Burst access enable */	
-} ebi_burst_access_mode_t;
-
-/** 
-  * @brief EBI Wait Signal Polarity
-  */
-typedef enum {
-	EBI_WAIT_SIGNAL_POLARITY_LOW  = 0x0U,		/**< Wait signal polarity low */
-	EBI_WAIT_SIGNAL_POLARITY_HIGH = (0x1U << 9),	/**< Wait signal polarity high */
-} ebi_wait_signal_polarity_t;
-
-/** 
-  * @brief EBI Wrap Mode
-  */
-typedef enum {
-	EBI_WRAP_MODE_DISABLE = 0x0U,		/**< Wrap mode disable */
-	EBI_WRAP_MODE_ENABLE  = (0x1U << 10),	/**< Wrap mode enable */
-} ebi_wrap_mode_t;
-
-/** 
-  * @brief EBI Wait Timing
-  */
-typedef enum {
-	EBI_WAIT_TIMING_BEFORE_WS = 0x0U,		/**< Wait timing before ws */
-	EBI_WAIT_TIMING_DURING_WS = (0x1U << 11),	/**< Wait timing during ws */
-} ebi_wait_timing_t;
-
-/** 
-  * @brief EBI Write Operation State
-  */
-typedef enum {
-	EBI_WRITE_OPERATION_DISABLE = 0x0U,		/**< Write operation disable */
-	EBI_WRITE_OPERATION_ENABLE  = (0x1U << 12),	/**< Write operation enable */
-} ebi_write_operation_t;
-
-/** 
-  * @brief EBI Wait Signal
-  */
-typedef enum {
-	EBI_WAIT_SIGNAL_DISABLE	= 0x0U,		/**< Wait signal disable */
-	EBI_WAIT_SIGNAL_ENABLE	= (0x1U << 13),	/**< Wait signal enable */
-} ebi_wait_signal_t;
-
-/** 
-  * @brief EBI Extended Mode
-  */
-typedef enum {
-	EBI_EXTENDED_MODE_DISABLE = 0x0U,		/**< EBI extended mode disable */
-	EBI_EXTENDED_MODE_ENABLE  = (0x1U << 14),	/**< EBI extended mode enable */
-} ebi_extended_mode_t;
-
-/** 
-  * @brief EBI Asynchronous Wait
-  */
-typedef enum {
-	EBI_ASYNCHRONOUS_WAIT_DISABLE = 0x0U,		/**< Asynchronous wait disable */
-	EBI_ASYNCHRONOUS_WAIT_ENABLE  = (0x1U << 15),	/**< Asynchronous wait enable */
-} ebi_asynchronous_wait_t;
-
-/** 
-  * @brief EBI Write Burst
-  */
-typedef enum {
-	EBI_WRITE_BURST_DISABLE = 0x0U,		/**<  Write burst disable */
-	EBI_WRITE_BURST_ENABLE  = (0x1U << 19),	/**<  Write burst enable */
-} ebi_write_burst_t;
-
-/** 
-  * @brief  EBI PCR Memory Type
-  */
-typedef enum {
-	EBI_PCTRLR_MEMORY_TYPE_None = 0x0U,		/**<  PCR memory type none */
-	EBI_PCTRLR_MEMORY_TYPE_NAND = (0x1U << 3),	/**<  PCR memory type nand */
-} ebi_pctrlr_memory_type_t;
-
-/** 
-  * @brief EBI Interrupt definition
-  */
-typedef enum {
-	EBI_IT_RISING_EDGE  = (1U << 3),	/**<  Rising edge trigger interrupt */
-	EBI_IT_LEVEL        = (1U << 4),	/**<  Level trigger interrupt */
-	EBI_IT_FALLING_EDGE = (1U << 5),	/**<  Falling edge trigger interrupt */
-} ebi_it_t;
-
-/** 
-  * @brief EBI Flag definition
-  */
-typedef enum {
-	EBI_FLAG_RISING_EDGE  = (1U << 0),	/**<  Rising edge flag */
-	EBI_FLAG_LEVEL        = (1U << 1),	/**<  Level flag */
-	EBI_FLAG_FALLING_EDGE = (1U << 2),	/**<  Falling edge flag */
-	EBI_FLAG_FEMPT        = (1U << 6),	/**<  Rising edge trigger interrupt */
-} ebi_flag_t;
-
-/** 
-  * @brief EBI LCD_Horizontal Synch Polarity definition 
-  */
-typedef enum {
-	EBI_LCD_HSYNCPOL_LOW  = 0x0U,		/**<  Horizontal synch polarity low */
-	EBI_LCD_HSYNCPOL_HIGH = (0x1U << 29),	/**<  Horizontal synch polarity high */
-} ebi_lcd_hsyncpol_t;
-
-/** 
-  * @brief EBI LCD Vertical Synch Polarity definition 
-  */
-typedef enum {
-	EBI_LCD_VSYNCPOL_LOW  = 0x0U,		/**<  Vertical synch polarity low */
-	EBI_LCD_VSYNCPOL_HIGH = (0x1U << 28),	/**<  Vertical synch polarity high */
-} ebi_lcd_vsyncpol_t;
-
-/** 
-  * @brief EBI LCD Data Enable Polarity definition 
-  */
-typedef enum {
-	EBI_LCD_DENPOL_LOW  = 0x0U,		/**<  LCD data enable polarity low */
-	EBI_LCD_DENPOL_HIGH = (0x1U << 27),	/**<  LCD data enable polarity high */
-} ebi_lcd_denpol_t;
-
-/** 
-  * @brief EBI LCD Enable definition
-  */
-typedef enum {
-	EBI_LCD_LCDEN_DISABLE = 0x0U,		/**<  LCD disable */
-	EBI_LCD_LCDEN_ENABLE  = (0x1U << 26),	/**<  LCD data enable polarity low */
-} ebi_lcd_lcden_t;
-
-/** 
-  * @brief EBI LCD Init Enable definition 
-  */
-typedef enum {
-	EBI_LCD_LCDINT_DISABLE = 0x0U,		/**<  LCD init disable */
-	EBI_LCD_LCDINT_ENABLE  = (0x1 << 25),	/**<  LCD init enable */
-} ebi_lcd_lcdint_t;
-
-/** 
-  * @brief EBI LCD Data Clock definition
-  */
-typedef enum {
-	EBI_LCD_DCLKPOL_FALLING = 0x0U,		/**<  LCD data clock falling edge */
-	EBI_LCD_DCLKPOL_RISING  = (0x1U << 24),	/**<  LCD data clock rising edge */
-} ebi_lcd_dclkpol_t;
-
-/**
-  * @brief EBI LCD parameters structure definition
-  */
-typedef struct {
-	uint8_t bank;			/**< Specifies the NORSRAM memory device */	
-	ebi_lcd_hsyncpol_t h_polarity;	/**< Horizontal sync polarity */
-	ebi_lcd_vsyncpol_t v_polarity;	/**< Vertical sync polarity */
-	ebi_lcd_denpol_t data_polarity;	/**< Data enable polarity */
-	ebi_lcd_lcden_t enable;		/**< LCD enable */
-	ebi_lcd_dclkpol_t clk_polarity;	/**< Data clock polarity */
-	ebi_lcd_lcdint_t reset;		/**< LCD Reset */
-	uint8_t setup;			/**< Data setup time */
-	uint8_t v_width;		/**< Vsync pulse width */
-	uint8_t h_width;		/**< Hsync puluse width */
-	uint16_t nr_line;		/**< Frame line number */
-	uint16_t nr_pixel;		/**< Frame pixel number */
-} ebi_lcd_init_t;
-
-/** 
-  * @brief  NOR LCD handle Structure definition  
-  */
-typedef struct {
-	EBI_LCD_TypeDef *inst;
-	ebi_lcd_init_t init;
-} ebi_lcd_handle_t;
-
-/**
-  * @brief EBI NORSRAM Configuration Structure definition
-  */
-typedef struct {
-	uint32_t bank;				/**< Specifies the NORSRAM memory device, the value can be one of 0 ~ 3 */
-	ebi_data_address_mux_t mux;		/**< Address and data values are multiplexed or not */
-	ebi_memory_type_t type;			/**< Specifies the type of external memory */ 
-	ebi_norsram_mem_bus_width_t width;	/**< Specifies the external memory device width */
-	ebi_burst_access_mode_t acc_mode;	/**< Enables or disables the burst access mode for Flash memory */
-	ebi_wait_signal_polarity_t polarity;	/**< Wait signal polarity, valid only in burst mode */
-	ebi_wrap_mode_t wrap_mode;		/**< Enables or disables the Wrapped burst access mode, only in burst mode */
-	ebi_wait_timing_t active;		/**< Specifies if the wait signal is asserted, only in burst mode */
-	ebi_write_operation_t write;		/**< Enables or disables the write operation */
-	ebi_wait_signal_t signal;		/**< Enables or disables the wait state insertion, only in burst mode */
-	ebi_extended_mode_t ext_mode;		/**< Enables or disables the extended mode */
-	ebi_asynchronous_wait_t wait;		/**< Enables or disables wait signal during asynchronous transfers */
-	ebi_write_burst_t burst;		/**< Enables or disables the write burst operation */
-} ald_ebi_nor_sram_init_t;
-
-/**
-  * @}
-  */
-
-/** @defgroup EBI_Private_Macros EBI Private Macros
-  * @{
-  */
-#define IS_EBI_NORSRAM_BANK(x)	(((x) == EBI_NORSRAM_BANK1) || \
-				((x) == EBI_NORSRAM_BANK2) || \
-				((x) == EBI_NORSRAM_BANK3) || \
-				((x) == EBI_NORSRAM_BANK4))
-#define IS_EBI_MUX(x)	(((x) == EBI_DATA_ADDRESS_MUX_DISABLE) || \
-			((x) == EBI_DATA_ADDRESS_MUX_ENABLE))
-#define IS_EBI_MEMORY(x)	(((x) == EBI_MEMORY_TYPE_SRAM) || \
-				((x) == EBI_MEMORY_TYPE_PSRAM) || \
-				((x) == EBI_MEMORY_TYPE_NOR))
-#define IS_EBI_NORSRAM_MEMORY_WIDTH(x)	(((x) == EBI_NORSRAM_MEM_BUS_WIDTH_8)  || \
-					((x) == EBI_NORSRAM_MEM_BUS_WIDTH_16) || \
-					((x) == EBI_NORSRAM_MEM_BUS_WIDTH_32))
-#define IS_EBI_WRITE_BURST(x)	(((x) == EBI_WRITE_BURST_DISABLE) || \
-				((x) == EBI_WRITE_BURST_ENABLE))
-#define IS_EBI_ACCESS_MODE(x)	(((x) == EBI_ACCESS_MODE_A) || \
-				((x) == EBI_ACCESS_MODE_B) || \
-				((x) == EBI_ACCESS_MODE_C) || \
-				((x) == EBI_ACCESS_MODE_D))
-#define IS_EBI_NAND_BANK(x)	(((x) == EBI_NAND_BANK2) || \
-				((x) == EBI_NAND_BANK3))
-#define IS_EBI_WAIT_FEATURE(x)	(((x) == EBI_NAND_WAIT_FEATURE_DISABLE) || \
-				((x) == EBI_NAND_WAIT_FEATURE_ENABLE))
-#define IS_EBI_NAND_MEMORY_WIDTH(x)	(((x) == EBI_NAND_MEM_BUS_WIDTH_8) || \
-					((x) == EBI_NAND_MEM_BUS_WIDTH_16))
-#define IS_EBI_ECC_STATE(x)		(((x) == EBI_NAND_ECC_DISABLE) || \
-					((x) == EBI_NAND_ECC_ENABLE))
-#define IS_EBI_ECCPAGE_SIZE(x)	(((x) == EBI_NAND_ECC_PAGE_SIZE_256BYTE)  || \
-				((x) == EBI_NAND_ECC_PAGE_SIZE_512BYTE)  || \
-				((x) == EBI_NAND_ECC_PAGE_SIZE_1024BYTE) || \
-				((x) == EBI_NAND_ECC_PAGE_SIZE_2048BYTE) || \
-				((x) == EBI_NAND_ECC_PAGE_SIZE_4096BYTE) || \
-				((x) == EBI_NAND_ECC_PAGE_SIZE_8192BYTE))
-#define IS_EBI_LCD_DEVICE(x)	((x) == EBI_LCD_DEVICE)
-#define IS_EBI_HORIZONTAL_SYNCH(x)	(((x) == EBI_LCD_HSYNCPOL_LOW) || \
-					((x) == EBI_LCD_HSYNCPOL_HIGH))
-#define IS_EBI_VERTICAL_SYNCH(x)	(((x) == EBI_LCD_VSYNCPOL_LOW) || \
-					((x) == EBI_LCD_VSYNCPOL_HIGH))
-#define IS_EBI_DATA_ENABLE(x)		(((x) == EBI_LCD_DENPOL_LOW) || \
-					((x) == EBI_LCD_DENPOL_HIGH))
-#define IS_EBI_LCD_ENABLE(x)		(((x) == EBI_LCD_LCDEN_DISABLE) || \
-					((x) == EBI_LCD_LCDEN_ENABLE))
-#define IS_EBI_LCD_RESET(x)		(((x) == EBI_LCD_LCDINT_DISABLE) || \
-					((x) == EBI_LCD_LCDINT_ENABLE))
-#define IS_EBI_DATA_CLOCK(x)		(((x) == EBI_LCD_DCLKPOL_FALLING) || \
-					((x) == EBI_LCD_DCLKPOL_RISING))
-#define IS_EBI_LCD_DATASETUP_TIME(x)	((x) < 255U)
-#define IS_EBI_HYSNC_PULSE_WIDTH(x)	((x) < 255U)
-#define IS_EBI_VSYNC_PULSE_WIDTH(x)	((x) < 255U)
-#define IS_EBI_FRAME_LINE_NUMBER(x)	(((x) >= 1U) && ((x) < 65535))
-#define IS_EBI_FRAME_PIXEL_NUMBER(x)	(((x) >= 1U) && ((x) < 65535))
-
-#define IS_EBI_TCLR_TIME(x)	((x) <= 255U)
-#define IS_EBI_TAR_TIME(x)	((x) <= 255U)
-#define IS_EBI_SETUP_TIME(x)	((x) <= 255U)
-#define IS_EBI_WAIT_TIME(x)	((x) <= 255U)
-#define IS_EBI_HOLD_TIME(x)	((x) <= 255U)
-#define IS_EBI_HIZ_TIME(x)	((x) <= 255U)
-#define IS_EBI_NORSRAM_DEVICE(x)	((x) == EBI_NOR_SRAM_DEVICE)
-#define IS_EBI_NORSRAM_EXTENDED_DEVICE(x)	((x) == EBI_NOR_SRAM_EXTENDED_DEVICE)
-#define IS_EBI_NAND_DEVICE(x)	((x) == EBI_NAND_DEVICE)
-#define IS_EBI_BURSTMODE(x)	(((x) == EBI_BURST_ACCESS_MODE_DISABLE) || \
-				((x) == EBI_BURST_ACCESS_MODE_ENABLE))
-#define IS_EBI_WAIT_POLARITY(x) (((x) == EBI_WAIT_SIGNAL_POLARITY_LOW) || \
-				((x) == EBI_WAIT_SIGNAL_POLARITY_HIGH))
-#define IS_EBI_WRAP_MODE(x)	(((x) == EBI_WRAP_MODE_DISABLE) || \
-				((x) == EBI_WRAP_MODE_ENABLE))
-#define IS_EBI_WAIT_SIGNAL_ACTIVE(x)	(((x) == EBI_WAIT_TIMING_BEFORE_WS) || \
-					((x) == EBI_WAIT_TIMING_DURING_WS))
-#define IS_EBI_WRITE_OPERATION(x)	(((x) == EBI_WRITE_OPERATION_DISABLE) || \
-					((x) == EBI_WRITE_OPERATION_ENABLE))
-#define IS_EBI_WAITE_SIGNAL(x)	(((x) == EBI_WAIT_SIGNAL_DISABLE) || \
-				((x) == EBI_WAIT_SIGNAL_ENABLE))
-#define IS_EBI_EXTENDED_MODE(x)	(((x) == EBI_EXTENDED_MODE_DISABLE) || \
-				((x) == EBI_EXTENDED_MODE_ENABLE))
-#define IS_EBI_ASYNWAIT(x)	(((x) == EBI_ASYNCHRONOUS_WAIT_DISABLE) || \
-				((x) == EBI_ASYNCHRONOUS_WAIT_ENABLE))
-#define IS_EBI_CLK_DIV(x)	(((x) >= 1U) && ((x) <= 16U))
-#define IS_EBI_DATA_LATENCY(x)	(((x) >= 1U) && ((x) <= 17U))
-#define IS_EBI_ADDRESS_SETUP_TIME(x)	((x) <= 15U)
-#define IS_EBI_ADDRESS_HOLD_TIME(x)	(((x) > 0U) && ((x) <= 15U))
-#define IS_EBI_DATASETUP_TIME(x)	(((x) > 0U) && ((x) <= 255U))
-#define IS_EBI_TURNAROUND_TIME(x)	((x) <= 15U)
-#define IS_EBI_BANK_NUMBER(x)	(((x) > 0U) && ((x) <= 4U))
-/**
-  * @}
-  */
-
-/** @addtogroup EBI_Public_Functions
-  * @{
-  */  
-
-/** @addtogroup EBI_Public_Functions_Group1
-  * @{
-  */
-/* NOR-FLASH SRAM initialize functions */    
-void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init);
-void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank);
-void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode);
-ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank);
-/**
-  * @}
-  */
-
-/** @addtogroup EBI_Public_Functions_Group2
-  * @{
-  */
-/* NOR/SRAM Control functions */
-void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank);
-void ald_ebi_nor_sram_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank);
-void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank);
-void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank);
-/**
-  * @}
-  */
-
-/** @addtogroup EBI_Public_Functions_Group3
-  * @{
-  */
-/* NAND-FLASH initialize functions */  
-void ald_ebi_nand_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init);
-void ald_ebi_nand_comm_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank);
-void ald_ebi_nand_attr_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank);
-void ald_ebi_nand_deinit(EBI_NAND_TypeDef *dev, uint32_t bank);
-/**
-  * @}
-  */
-
-/** @addtogroup EBI_Public_Functions_Group4
-  * @{
-  */
-/* NAND-FLASH control functions */    
-void ald_ebi_nand_enable(EBI_NAND_TypeDef *dev, uint32_t bank);
-void ald_ebi_nand_disable(EBI_NAND_TypeDef *dev, uint32_t bank);
-void ald_ebi_nand_enable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it);
-void ald_ebi_nand_disable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it);
-void ald_ebi_nand_ecc_enable(EBI_NAND_TypeDef *dev, uint32_t bank);
-void ald_ebi_nand_ecc_disable(EBI_NAND_TypeDef *dev, uint32_t bank);
-ald_status_t ald_ebi_nand_get_ecc(EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout);
-flag_status_t ald_ebi_nand_get_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag);
-void ald_ebi_nand_clear_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag);
-/**
-  * @}
-  */
-
-/** @addtogroup EBI_Public_Functions_Group5
-  * @{
-  */ 
-void ald_ebi_lcd_init(ebi_lcd_handle_t *hlcd);
-void ald_ebi_lcd_reset(ebi_lcd_handle_t *hlcd);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_EBI_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_flash.h

@@ -1,146 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_flash.h
-  * @brief   Header file of FLASH driver
-  *
-  * @version V1.0
-  * @date    17 Jun 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          17 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_FLASH_H__
-#define __ALD_FLASH_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */
-
-/**
-  * @defgroup FLASH_Private_Macros FLASH Private Macros
-  * @{
-  */
-#define FLASH_REG_UNLOCK()				\
-do {							\
-	if (op_cmd == OP_FLASH)	 {			\
-		WRITE_REG(MSC->FLASHKEY, 0x8ACE0246);	\
-		WRITE_REG(MSC->FLASHKEY, 0x9BDF1357);	\
-	}						\
-	else {						\
-		WRITE_REG(MSC->INFOKEY, 0x7153BFD9);	\
-		WRITE_REG(MSC->INFOKEY, 0x0642CEA8);	\
-	}						\
-} while (0)
-#define FLASH_REQ()			(SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
-#define FLASH_REQ_FIN()			(CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
-#define FLASH_IAP_ENABLE()		(SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
-#define FLASH_IAP_DISABLE()		(CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
-#define FLASH_BASE_ADDR			0x00000000
-#define	FLASH_PAGE_SIZE			1024UL
-#define FLASH_WORD_SIZE			8UL
-#define FLASH_TOTAL_SIZE		512UL
-#define FLASH_PAGE_MASK			(FLASH_PAGE_SIZE - 1)
-#define FLASH_WORD_MASK			(FLASH_WORD_SIZE - 1)
-#define IS_FLASH_ADDRESS(ADDR)		((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE))
-#define IS_4BYTES_ALIGN(ADDR)		(((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0)
-#define FLASH_PAGE_ADDR(ADDR)		((ADDR) & (~FLASH_PAGE_MASK))
-#define FLASH_PAGEEND_ADDR(ADDR)	((ADDR) | FLASH_PAGE_MASK)
-#define FLASH_WORD_ADDR(ADDR)		((ADDR) & (~FLASH_WORD_MASK))
-#define FLASH_WORDEND_ADDR(ADDR)	((ADDR) | FLASH_WORD_MASK)
-#define INFO_PAGE_SIZE			1024UL
-#define INFO_PAGE_MASK			(INFO_PAGE_SIZE - 1)
-#define INFO_PAGE_ADDR(ADDR)		((ADDR) & (~INFO_PAGE_MASK))
-
-#ifdef USE_FLASH_FIFO
-	#define	FLASH_FIFO 1
-#else
-	#define	FLASH_FIFO 0
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Private_Types FLASH Private Types
-  * @{
-  */
-typedef enum {
-	FLASH_CMD_AE          = 0x000051AEU,	/**< Program area erase all */
-	FLASH_CMD_PE          = 0x00005EA1U,	/**< Page erase  */
-	FLASH_CMD_WP          = 0x00005DA2U,	/**< Word program */
-	FLASH_CMD_WP_FAST     = 0x00005CA3U, 	/**< Flash quickly program */
-	FLASH_CMD_DATAPE      = 0x00005BA4U,	/**< Data flash page page erase */
-	FLASH_CMD_DATAWP      = 0x00005AA5U,	/**< Data flash word program */
-	FLASH_CMD_DATAWP_FAST = 0x000059A6U,	/**< Data flash quickly program */
-	FLASH_CMD_NP_AE       = 0x000050AFU,	/**< No-private area erase all */
-} flash_cmd_type;
-
-typedef enum {
-	OP_FLASH = 0U,	/**< Operate Pragram area */
-	OP_INFO  = 1U,	/**< Operate info area */
-} op_cmd_type;
-
-/**
-  * @}
-  */ 
-/** @addtogroup Flash_Private_Functions
-  * @{
-  */
-ald_status_t flash_page_erase(uint32_t addr);
-ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo);
-/**
-  * @}
-  */
-
-/** @addtogroup Flash_Public_Functions
-  * @{
-  */
-ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len);
-ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len);
-ald_status_t ald_flash_erase(uint32_t addr, uint16_t len);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_FLASH_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_gpio.h

@@ -1,339 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_gpio.h
-  * @brief   Header file of GPIO module driver
-  *
-  * @version V1.0
-  * @date    07 Nov 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          07 Nov 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_GPIO_H__
-#define __ALD_GPIO_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup GPIO
-  * @{
-  */
-
-/**
-  * @defgroup GPIO_Public_Macros GPIO Public Macros
-  * @{
-  */
-#define GPIO_PIN_0      (0x1U)
-#define GPIO_PIN_1      (0x2U)
-#define GPIO_PIN_2      (0x4U)
-#define GPIO_PIN_3      (0x8U)
-#define GPIO_PIN_4      (0x10U)
-#define GPIO_PIN_5      (0x20U)
-#define GPIO_PIN_6      (0x40U)
-#define GPIO_PIN_7      (0x80U)
-#define GPIO_PIN_8      (0x100U)
-#define GPIO_PIN_9      (0x200U)
-#define GPIO_PIN_10     (0x400U)
-#define GPIO_PIN_11     (0x800U)
-#define GPIO_PIN_12     (0x1000U)
-#define GPIO_PIN_13     (0x2000U)
-#define GPIO_PIN_14     (0x4000U)
-#define GPIO_PIN_15     (0x8000U)
-#define GPIO_PIN_ALL    (0xFFFF)
-
-/* Toggle IO */
-#define ALD_GPIOA_TOGGLE_PIN(x)    (GPIOA->BIR = (x))
-#define ALD_GPIOB_TOGGLE_PIN(x)    (GPIOB->BIR = (x))
-#define ALD_GPIOC_TOGGLE_PIN(x)    (GPIOC->BIR = (x))
-#define ALD_GPIOD_TOGGLE_PIN(x)    (GPIOD->BIR = (x))
-#define ALD_GPIOE_TOGGLE_PIN(x)    (GPIOE->BIR = (x))
-#define ALD_GPIOF_TOGGLE_PIN(x)    (GPIOF->BIR = (x))
-#define ALD_GPIOG_TOGGLE_PIN(x)    (GPIOG->BIR = (x))
-#define ALD_GPIOH_TOGGLE_PIN(x)    (GPIOH->BIR = (x))
-
-/* Read IO level */
-#define ALD_GPIOA_READ_PIN(x)      ((GPIOA->DIN & (x)) ? 1 : 0)
-#define ALD_GPIOB_READ_PIN(x)      ((GPIOB->DIN & (x)) ? 1 : 0)
-#define ALD_GPIOC_READ_PIN(x)      ((GPIOC->DIN & (x)) ? 1 : 0)
-#define ALD_GPIOD_READ_PIN(x)      ((GPIOD->DIN & (x)) ? 1 : 0)
-#define ALD_GPIOE_READ_PIN(x)      ((GPIOE->DIN & (x)) ? 1 : 0)
-#define ALD_GPIOF_READ_PIN(x)      ((GPIOF->DIN & (x)) ? 1 : 0)
-#define ALD_GPIOG_READ_PIN(x)      ((GPIOG->DIN & (x)) ? 1 : 0)
-#define ALD_GPIOH_READ_PIN(x)      ((GPIOH->DIN & (x)) ? 1 : 0)
-
-/* Set IO as high */
-#define ALD_GPIOA_SET_PIN(x)       (GPIOA->BSRR = (x))
-#define ALD_GPIOB_SET_PIN(x)       (GPIOB->BSRR = (x))
-#define ALD_GPIOC_SET_PIN(x)       (GPIOC->BSRR = (x))
-#define ALD_GPIOD_SET_PIN(x)       (GPIOD->BSRR = (x))
-#define ALD_GPIOE_SET_PIN(x)       (GPIOE->BSRR = (x))
-#define ALD_GPIOF_SET_PIN(x)       (GPIOF->BSRR = (x))
-#define ALD_GPIOG_SET_PIN(x)       (GPIOG->BSRR = (x))
-#define ALD_GPIOH_SET_PIN(x)       (GPIOH->BSRR = (x))
-
-/* Set IO as low */
-#define ALD_GPIOA_RESET_PIN(x)     (GPIOA->BSRR = ((x) << 16))
-#define ALD_GPIOB_RESET_PIN(x)     (GPIOB->BSRR = ((x) << 16))
-#define ALD_GPIOC_RESET_PIN(x)     (GPIOC->BSRR = ((x) << 16))
-#define ALD_GPIOD_RESET_PIN(x)     (GPIOD->BSRR = ((x) << 16))
-#define ALD_GPIOE_RESET_PIN(x)     (GPIOE->BSRR = ((x) << 16))
-#define ALD_GPIOF_RESET_PIN(x)     (GPIOF->BSRR = ((x) << 16))
-#define ALD_GPIOG_RESET_PIN(x)     (GPIOG->BSRR = ((x) << 16))
-#define ALD_GPIOH_RESET_PIN(x)     (GPIOH->BSRR = ((x) << 16))
-/**
-  * @}
-  */
-
-/**
-  * @defgroup GPIO_Public_Types GPIO Public Types
-  * @{
-  */
-
-/**
-  * @brief GPIO mode
-  */
-typedef enum {
-	GPIO_MODE_CLOSE  = 0x0U,	/**< Digital close  Analog open */
-	GPIO_MODE_INPUT  = 0x1U,	/**< Input */
-	GPIO_MODE_OUTPUT = 0x2U,	/**< Output */
-} gpio_mode_t;
-
-/**
-  * @brief GPIO open-drain or push-pull
-  */
-typedef enum {
-	GPIO_PUSH_PULL   = 0x0U,	/**< Push-Pull */
-	GPIO_OPEN_DRAIN  = 0x2U,	/**< Open-Drain. Can't output high level */
-	GPIO_OPEN_SOURCE = 0x3U,	/**< Open-Source. Can't output low level */
-} gpio_odos_t;
-
-/**
-  * @brief GPIO push-up or push-down
-  */
-typedef enum {
-	GPIO_FLOATING     = 0x0U,	/**< Floating */
-	GPIO_PUSH_UP      = 0x1U,	/**< Push-Up */
-	GPIO_PUSH_DOWN    = 0x2U,	/**< Push-Down */
-	GPIO_PUSH_UP_DOWN = 0x3U,	/**< Push-Up and Push-Down */
-} gpio_push_t;
-
-/**
-  * @brief GPIO output drive
-  */
-typedef enum {
-	GPIO_OUT_DRIVE_0_1 = 0x0U,	/**< 0.1mA */
-	GPIO_OUT_DRIVE_1   = 0x1U,	/**< 1mA */
-	GPIO_OUT_DRIVE_6   = 0x2U,	/**< 6mA */
-	GPIO_OUT_DRIVE_20  = 0x3U,	/**< 20mA */
-} gpio_out_drive_t;
-
-/**
-  * @brief GPIO filter
-  */
-typedef enum {
-	GPIO_FILTER_DISABLE = 0x0U,	/**< Disable filter */
-	GPIO_FILTER_ENABLE  = 0x1U,	/**< Enable filter */
-} gpio_filter_t;
-
-/**
-  * @brief GPIO type
-  */
-typedef enum {
-	GPIO_TYPE_CMOS = 0x0U,	/**< CMOS Type */
-	GPIO_TYPE_TTL  = 0x1U,	/**< TTL Type */
-} gpio_type_t;
-
-/**
-  * @brief GPIO functions
-  */
-typedef enum {
-	GPIO_FUNC_0 = 0U,	/**< function #0 */
-	GPIO_FUNC_1 = 1U,	/**< function #1 */
-	GPIO_FUNC_2 = 2U,	/**< function #2 */
-	GPIO_FUNC_3 = 3U,	/**< function #3 */
-	GPIO_FUNC_4 = 4U,	/**< function #4 */
-	GPIO_FUNC_5 = 5U,	/**< function #5 */
-	GPIO_FUNC_6 = 6U,	/**< function #6 */
-	GPIO_FUNC_7 = 7U,	/**< function #7 */
-} gpio_func_t;
-
-
-/**
-  * @brief GPIO Init Structure definition
-  */
-typedef struct {
-	gpio_mode_t mode;	/**< Specifies the operating mode for the selected pins.
-				     This parameter can be any value of @ref gpio_mode_t */
-	gpio_odos_t odos;	/**< Specifies the Open-Drain or Push-Pull for the selected pins.
-				     This parameter can be a value of @ref gpio_odos_t */
-	gpio_push_t pupd;	/**< Specifies the Pull-up or Pull-Down for the selected pins.
-				     This parameter can be a value of @ref gpio_push_t */
-	gpio_out_drive_t podrv;	/**< Specifies the output P-MOS driver for the selected pins.
-				     This parameter can be a value of @ref gpio_out_drive_t */
-	gpio_out_drive_t nodrv;	/**< Specifies the output N-MOS driver for the selected pins.
-				     This parameter can be a value of @ref gpio_out_drive_t */
-	gpio_filter_t flt;	/**< Specifies the input filter for the selected pins.
-				     This parameter can be a value of @ref gpio_filter_t */
-	gpio_type_t type;	/**< Specifies the type for the selected pins.
-				     This parameter can be a value of @ref gpio_type_t */
-	gpio_func_t func;	/**< Specifies the function for the selected pins.
-				     This parameter can be a value of @ref gpio_func_t */
-} gpio_init_t;
-
-/**
-  * @brief EXTI trigger style
-  */
-typedef enum {
-	EXTI_TRIGGER_RISING_EDGE   = 0U,	/**< Rising edge trigger */
-	EXTI_TRIGGER_TRAILING_EDGE = 1U,	/**< Trailing edge trigger */
-	EXTI_TRIGGER_BOTH_EDGE     = 2U,	/**< Rising and trailing edge trigger */
-} exti_trigger_style_t;
-
-/**
-  * @brief EXTI filter clock select
-  */
-typedef enum {
-	EXTI_FILTER_CLOCK_10K = 0U,	/**< cks = 10KHz */
-	EXTI_FILTER_CLOCK_32K = 1U,	/**< cks = 32KHz */
-} exti_filter_clock_t;
-
-/**
-  * @brief EXTI Init Structure definition
-  */
-typedef struct {
-	type_func_t filter;		/**< Enable filter. */
-	exti_filter_clock_t cks;	/**< Filter clock select. */
-	uint8_t filter_time;		/**< Filter duration */
-} exti_init_t;
-/**
-  * @}
-  */
-
-/**
-  * @defgroup GPIO_Private_Macros GPIO Private Macros
-  * @{
-  */
-#define PIN_MASK	0xFFFFU
-#define UNLOCK_KEY	0x55AAU
-
-#define IS_GPIO_PIN(x)	((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0))
-#define IS_GPIO_PORT(GPIOx)	((GPIOx == GPIOA) || \
-				 (GPIOx == GPIOB) || \
-				 (GPIOx == GPIOC) || \
-				 (GPIOx == GPIOD) || \
-				 (GPIOx == GPIOE) || \
-				 (GPIOx == GPIOF) || \
-				 (GPIOx == GPIOG) || \
-				 (GPIOx == GPIOH))
-#define IS_GPIO_MODE(x)		(((x) == GPIO_MODE_CLOSE) || \
-                                 ((x) == GPIO_MODE_INPUT) || \
-                                 ((x) == GPIO_MODE_OUTPUT))
-#define IS_GPIO_ODOS(x)		(((x) == GPIO_PUSH_PULL)  || \
-                                 ((x) == GPIO_OPEN_DRAIN) || \
-                                 ((x) == GPIO_OPEN_SOURCE))
-#define IS_GPIO_PUPD(x)		(((x) == GPIO_FLOATING)  || \
-                                 ((x) == GPIO_PUSH_UP)   || \
-                                 ((x) == GPIO_PUSH_DOWN) || \
-                                 ((x) == GPIO_PUSH_UP_DOWN))
-#define IS_GPIO_ODRV(x)		(((x) == GPIO_OUT_DRIVE_0_1) || \
-                                 ((x) == GPIO_OUT_DRIVE_1) || \
-                                 ((x) == GPIO_OUT_DRIVE_6) || \
-                                 ((x) == GPIO_OUT_DRIVE_20))
-#define IS_GPIO_FLT(x)		(((x) == GPIO_FILTER_DISABLE) || \
-                                 ((x) == GPIO_FILTER_ENABLE))
-#define IS_GPIO_TYPE(x)		(((x) == GPIO_TYPE_TTL) || \
-                                 ((x) == GPIO_TYPE_CMOS))
-#define IS_TRIGGER_STYLE(x)	(((x) == EXTI_TRIGGER_RISING_EDGE)   || \
-                                 ((x) == EXTI_TRIGGER_TRAILING_EDGE) || \
-                                 ((x) == EXTI_TRIGGER_BOTH_EDGE))
-#define IS_EXTI_FLTCKS_TYPE(x)	(((x) == EXTI_FILTER_CLOCK_10K) || \
-                                 ((x) == EXTI_FILTER_CLOCK_32K))
-#define IS_GPIO_FUNC(x)		((x) <= 7)
-/**
-  * @}
-  */
-
-/** @addtogroup GPIO_Public_Functions
-  * @{
-  */
-
-/** @addtogroup GPIO_Public_Functions_Group1
-  * @{
-  */
-void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init);
-void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin);
-void ald_gpio_func_default(GPIO_TypeDef *GPIOx);
-void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init);
-/**
-  * @}
-  */
-
-/** @addtogroup GPIO_Public_Functions_Group2
-  * @{
-  */
-uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
-void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val);
-void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
-void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin);
-void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
-uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx);
-void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val);
-/**
-  * @}
-  */
-
-/** @addtogroup GPIO_Public_Functions_Group3
-  * @{
-  */
-void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status);
-flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin);
-void ald_gpio_exti_clear_flag_status(uint16_t pin);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_GPIO_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_i2c.h

@@ -1,470 +0,0 @@
-/**
- *********************************************************************************
- *
- * @file    ald_i2c.h
- * @brief   Header file of I2C driver
- *
- * @version V1.0
- * @date    15 Nov 2019
- * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          30 Jun 2020     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
- */
-
-#ifndef __ALD_I2C_H__
-#define __ALD_I2C_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-#include "ald_cmu.h"
-#include <string.h>
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup I2C
-  * @{
-  */
-
-/** @defgroup I2C_Public_Types I2C Public Types
-  * @{
-  */
-/**
-  * @brief I2C Error Code
-  */
-typedef enum {
-	I2C_ERROR_NONE    = 0x0U,	/**< No error */
-	I2C_ERROR_BERR    = 0x1U,	/**< Berr error */
-	I2C_ERROR_ARLO    = 0x2U,	/**< Arlo error */
-	I2C_ERROR_RUD     = 0x4U,	/**< Rx underflow error */
-	I2C_ERROR_AF      = 0x8U,	/**< Af error */	
-	I2C_ERROR_ROV     = 0x10U,	/**< Rx overflow error */
-	I2C_ERROR_RF      = 0x20U,	/**< Rx full error */
-	I2C_ERROR_TUD     = 0x40U,	/**< Tx underflow error */
-	I2C_ERROR_TOV     = 0x80U,	/**< Tx overflow error */
-	I2C_ERROR_TE      = 0x100U,	/**< Tx empty error */
-	I2C_ERROR_DMA     = 0x200U,	/**< Dma error */
-	I2C_ERROR_TIMEOUT = 0x400U,	/**< Timeout error */
-} i2c_error_t;
-
-/**
-  * @brief I2C state structure definition
-  */
-typedef enum {
-	I2C_STATE_RESET   = 0x0U,	/**< Peripheral is not yet Initialized */
-	I2C_STATE_READY   = 0x20U,	/**< Peripheral Initialized and ready for use */
-	I2C_STATE_BUSY    = 0x24U,	/**< An internal process is ongoing */
-	I2C_STATE_BUSY_TX = 0x21U,	/**< Data Transmission process is ongoing */
-	I2C_STATE_BUSY_RX = 0x22U,	/**< Data Reception process is ongoing */
-	I2C_STATE_TIMEOUT = 0xA0U,	/**< timeout state */
-	I2C_STATE_ERROR   = 0xE0U,	/**< Error */
-} i2c_state_t;
-
-/**
-  * @brief I2C Addressing Mode
-  */
-typedef enum {
-	I2C_ADDR_7BIT  = 0x0U,	/**< 7 bit address */
-	I2C_ADDR_10BIT = 0x1U,	/**< 10 bit address */
-} i2c_addr_t;
-
-/**
-  * @brief I2C Dual Addressing Mode
-  */
-typedef enum {
-	I2C_DUALADDR_DISABLE = 0x0U,	/**< dual address is disable */
-	I2C_DUALADDR_ENABLE  = 0x1U,	/**< dual address is enable */
-} i2c_dual_addr_t;
-
-/**
-  * @brief I2C General Call Addressing mode
-  */
-typedef enum {
-	I2C_GENERALCALL_DISABLE = 0x0U,	/**< general call address is disable */
-	I2C_GENERALCALL_ENABLE  = 0x1U,	/**< general call address is enable */
-} i2c_general_addr_t;
-
-/**
-  * @brief I2C Nostretch Mode
-  */
-typedef enum {
-	I2C_NOSTRETCH_DISABLE = 0x0U,	/**< Nostretch disable */
-	I2C_NOSTRETCH_ENABLE  = 0x1U,	/**< Nostretch enable */
-} i2c_nostretch_t;
-
-/**
-  * @brief I2C Memory Address Size
-  */
-typedef enum {
-	I2C_MEMADD_SIZE_8BIT  = 0x8U,	/**< 8 bit memory address size */
-	I2C_MEMADD_SIZE_16BIT = 0x10U,	/**< 10 bit memory address size */
-} i2c_addr_size_t;
-
-/**
-  * @brief I2C mode structure definition
-  */
-typedef enum {
-	I2C_MODE_NONE   = 0x0U,		/**< No I2C communication on going */
-	I2C_MODE_MASTER = 0x10U,	/**< I2C communication is in Master mode */
-	I2C_MODE_SLAVE  = 0x20U,	/**< I2C communication is in Slave mode */
-	I2C_MODE_MEM    = 0x40U,	/**< I2C communication is in Memory mode */
-} i2c_mode_t;
-
-/**
-  * @brief I2C Clock
-  */
-typedef enum {
-	I2C_STANDARD_MODE_MAX_CLK     = 100000U,	/**< Standard mode clock */
-	I2C_FAST_MODE_MAX_CLK         = 400000U,	/**< Fast mode clock */
-	I2C_EXTREME_FAST_MODE_MAX_CLK = 1000000U,	/**< Extreme mode clock */
-} i2c_clock_t;
-
-/**
-  * @brief I2C OAR2 Register
-  */
-typedef enum {
-	I2C_OAR2_ENDUAL = (1U << 0), /**< ENDUAL BIT */
-	I2C_OAR2_ADD2   = (1U << 1)  /**< ADD2 BIT */
-} i2c_oar2_t;
-
-/**
-  * @brief I2C CON1 Register
-  */
-typedef enum {
-	I2C_CON1_PE        = (1U << 0),		/**< Peripheral enable BIT */
-	I2C_CON1_TXDMA     = (1U << 14),	/**< Transmit DMA BIT */
-	I2C_CON1_RXDMA     = (1U << 15),	/**< Receive DMA BIT */
-	I2C_CON1_SBC       = (1U << 16),	/**< Receive DMA BIT */
-	I2C_CON1_NOSTRETCH = (1U << 17),	/**< Slave bytes control BIT */
-	I2C_CON1_GCEN      = (1U << 19),	/**< General call BIT */
-	I2C_CON1_SMBHEN    = (1U << 20),	/**< SMBus slave device enable BIT */
-	I2C_CON1_SMBDEN    = (1U << 21),	/**< SMBus master device enable BIT */
-	I2C_CON1_ALERTEN   = (1U << 22),	/**< SMBus alert device enable BIT */
-	I2C_CON1_PECEN     = (1U << 23),	/**< PEC enable BIT */
-} i2c_con1_t;
-
-/**
-  * @brief I2C CON2 Register
-  */
-typedef enum {
-	I2C_CON2_RD_WRN    = (1U << 10),	/**< Master R/W control BIT */
-	I2C_CON2_ADD10     = (1U << 11),	/**< 10bit address control BIT */
-	I2C_CON2_HEAD10R   = (1U << 12),	/**< 10bit address master Receive control BIT */
-	I2C_CON2_START     = (1U << 13),	/**< Master start singal control BIT */
-	I2C_CON2_STOP      = (1U << 14),	/**< Master stop singal control BIT */
-	I2C_CON2_NACK      = (1U << 15),	/**< Master Nack control BIT */
-	I2C_CON2_RELOAD    = (1U << 24),	/**< Master communication reload control BIT */
-	I2C_CON2_AUTOEND   = (1U << 25),	/**< Master Autoend control BIT */
-	I2C_CON2_PECBYTE   = (1U << 26),	/**< PEC control BIT */
-	I2C_CON2_HOLDACK   = (1U << 28),	/**< Hold ack control BIT */
-} i2c_con2_t;
-
-/**
-  * @brief I2C ADDR1 Register
-  */
-typedef enum {
-	I2C_OA1MODE = (1U << 10),	/**< Addr1 bits choose BIT */
-	I2C_OA1EN   = (1U << 15),	/**< Addr1 enable BIT */
-} i2c_addr1_t;
-
-/**
-  * @brief I2C ADDR2 Register
-  */
-typedef enum {
-	I2C_OA2EN = (1U << 15),		/**< Addr2 enable BIT */
-} i2c_addr2_t;
-
-/**
-  * @brief I2C TIMEOUTR Register
-  */
-typedef enum {
-	I2C_TIMEOUTR_TIDLE     = (1U << 12),	/**< SCL idle check enable BIT */
-	I2C_TIMEOUTR_TIMEOUTEN = (1U << 15),	/**< Timeout enable BIT */
-} i2c_timoutr_t;
-
-/**
-  * @brief I2C peripherals module
-  */
-typedef enum {
-	I2C_MODULE_MASTER = (1U << 0),	/**< Master module */
-	I2C_MODULE_SLAVE  = (1U << 1)	/**< Slave module */
-} i2c_module_t;
-
-/**
-  * @brief I2C STAT Register 
-  */
-typedef enum {
-	I2C_STAT_TXE  = (1U << 0),	/**< Transmit FIFO empty flag */
-	I2C_STAT_TXF  = (1U << 1),	/**< Transmit FIFO full flag */
-	I2C_STAT_TXOV = (1U << 2),	/**< Transmit FIFO overrun flag */
-	I2C_STAT_TXUD = (1U << 3),	/**< Transmit FIFO underrun flag*/
-	I2C_STAT_THTH = (1U << 4),	/**< Transmit FIFO threshold flag */
-	I2C_STAT_RXE  = (1U << 5),	/**< Receive FIFO empty flag*/
-	I2C_STAT_RXF  = (1U << 6),	/**< Receive FIFO full flag*/
-	I2C_STAT_RXOV = (1U << 7),	/**< Receive FIFO overrun flag */
-	I2C_STAT_RXUD = (1U << 8),	/**< Receive FIFO underrun flag */
-	I2C_STAT_RXTH = (1U << 9),	/**< Receive FIFO threshold flag */
-	I2C_STAT_TC   = (1U << 10),	/**< Transmit completed flag */
-	I2C_STAT_TCR  = (1U << 11),	/**< Transmit and reload completed flag */
-	I2C_STAT_BUSY = (1U << 15),	/**< Bus status busy flag */
-	I2C_STAT_DIR  = (1U << 16),	/**< Slave R/W flag */
-} i2c_stat_t;
-
-/**
-  * @brief Interrupt Configuration Definition
-  */
-typedef enum {
-	I2C_IT_TXE   = (1U << 0), /**< Transmit FIFO empty interrupt */
-	I2C_IT_TXOV  = (1U << 2), /**< Transmit FIFO overrun interrupt */
-	I2C_IT_TXUD  = (1U << 3), /**< Transmit FIFO underrun interrupt*/
-	I2C_IT_TXTH  = (1U << 4), /**< Transmit FIFO threshold interrupt */
-	I2C_IT_RXF   = (1U << 6), /**< Receive FIFO full interrupt*/
-	I2C_IT_RXOV  = (1U << 7), /**< Receive FIFO overrun interrupt */
-	I2C_IT_RXUD  = (1U << 8), /**< Receive FIFO underrun interrupt */
-	I2C_IT_RXTH  = (1U << 9), /**< Receive FIFO threshold interrupt */
-	I2C_IT_TC    = (1U << 10), /**< Transmit completed interrupt */
-	I2C_IT_TCR   = (1U << 11), /**< Transmit and reload completed interrupt */
-	I2C_IT_ADDR  = (1U << 12), /**< Address matching interrupt */
-	I2C_IT_NACK  = (1U << 13), /**< NACK interrupt */
-	I2C_IT_STOP  = (1U << 14), /**< Stop detection interrupt */
-	I2C_IT_BERR  = (1U << 16), /**< Bus error interrupt */
-	I2C_IT_ARLO  = (1U << 17), /**< Arbitration loss interrupt */
-	I2C_IT_PECE  = (1U << 18), /**< PEC error interrupt */
-	I2C_IT_TOUT  = (1U << 19), /**< Timeout interrupt */
-	I2C_IT_ALERT = (1U << 20), /**< SMBus Alert interrupt */
-} i2c_interrupt_t;
-
-/**
-  * @brief I2C TRISE Register
-  */
-typedef enum {
-	I2C_TRISE_TRISE = 0x3FU, /**< TRISE BITS */
-} i2c_trise_t;
-
-/**
- * @brief I2C Configuration Structure definition
- */
-typedef struct {
-	i2c_module_t module;		/**< Specifies the communication module */
-	uint32_t clk_speed;		/**< Specifies the clock frequency */
-	uint32_t own_addr1;		/**< Specifies the first device own address */
-	i2c_addr_t addr_mode;		/**< Specifies addressing mode */
-	i2c_dual_addr_t dual_addr;	/**< Specifies if dual addressing mode is selected */
-	uint32_t own_addr2;		/**< Specifies the second device own address */
-	i2c_general_addr_t general_call;/**< Specifies if general call mode is selected */
-	i2c_nostretch_t no_stretch;	/**< Specifies if nostretch mode is selected */
-} i2c_init_t;
-
-/**
-  * @brief  I2C handle Structure definition
-  */
-typedef struct i2c_handle_s {
-	I2C_TypeDef *perh;        /**< I2C registers base address */
-	i2c_init_t init;          /**< I2C communication parameters */
-	uint8_t *p_buff;          /**< Pointer to I2C transfer buffer */
-	uint16_t xfer_size;       /**< I2C transfer size */
-	__IO uint16_t xfer_count; /**< I2C transfer counter */
-
-	dma_handle_t hdmatx;      /**< I2C Tx DMA handle parameters */
-	dma_handle_t hdmarx;      /**< I2C Rx DMA handle parameters */
-
-	lock_state_t lock;        /**< I2C locking object */
-	__IO i2c_state_t state;   /**< I2C communication state */
-	__IO i2c_mode_t mode;     /**< I2C communication mode */
-	__IO uint32_t error_code; /**< I2C Error code */
-
-	void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Tx completed callback */
-	void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Rx completed callback */
-	void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg);  /**< Slave Tx completed callback */
-	void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg);  /**< Slave Rx completed callback */
-	void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg);    /**< Tx to Memory completed callback */
-	void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg);    /**< Rx from Memory completed callback */
-	void (*error_callback)(struct i2c_handle_s *arg);     /**< Error callback */
-} i2c_handle_t;
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Public_Macro I2C Public Macros
-  * @{
-  */
-#define I2C_FLAG_MASK	(0xFFFFFFFFU)
-#define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET)
-#define I2C_ENABLE_IT(x, y)   (SET_BIT((x)->perh->IER, (y)))
-#define I2C_DISABLE_IT(x, y)  (SET_BIT((x)->perh->IDR, (y)))
-#define I2C_CLEAR_IT(x, y)  (SET_BIT((x)->perh->ICR, (y)))
-#define I2C_GET_IT_FLAG(x, y)  (READ_BIT((x)->perh->RIF, (y)))
-#define I2C_GET_IT_SOURCE(x, y) ((((x)->perh->IFM & (y))  == (y)) ? SET : RESET)
-#define I2C_GET_FLAG(x, y) ((((x)->perh->STAT) & ((y) & I2C_FLAG_MASK)) != RESET)
-#define I2C_MASTER_GET_DIR(x) (READ_BIT(((x)->perh->CON2), I2C_CON2_RD_WRN_MSK))
-#define I2C_SLAVE_GET_DIR(x) (READ_BIT(((x)->perh->STAT), I2C_STAT_DIR_MSK))
-#define I2C_ENABLE(x)  (SET_BIT((x)->perh->CON1, I2C_CON1_PE_MSK))
-#define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PE_MSK))
-#define I2C_RST_TXFIFO(x) (SET_BIT((x)->perh->FCON, I2C_FCON_TXFRST_MSK))
-#define I2C_RST_RXFIFO(x) (SET_BIT((x)->perh->FCON, I2C_FCON_RXFRST_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Private_Macro I2C Private Macros
-  * @{
-  */
-#define IS_I2C_TYPE(x)						(((x) == I2C0) || ((x) == I2C1))
-#define IS_I2C_MODULE(x)					(((x) == I2C_MODULE_MASTER) || ((x) == I2C_MODULE_SLAVE))
-#define IS_I2C_ADDRESSING_MODE(ADDRESS)				(((ADDRESS) == I2C_ADDR_7BIT) || \
-	((ADDRESS) == I2C_ADDR_10BIT))
-#define IS_I2C_DUAL_ADDRESS(ADDRESS)				(((ADDRESS) == I2C_DUALADDR_DISABLE) || \
-	((ADDRESS) == I2C_DUALADDR_ENABLE))
-#define IS_I2C_GENERAL_CALL(CALL)				(((CALL)    == I2C_GENERALCALL_DISABLE) || \
-	((CALL)    == I2C_GENERALCALL_ENABLE))
-#define IS_I2C_MEMADD_size(size)				(((size)    == I2C_MEMADD_SIZE_8BIT) || \
-	((size)    == I2C_MEMADD_SIZE_16BIT))
-#define IS_I2C_NO_STRETCH(STRETCH)				(((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
-	((STRETCH) == I2C_NOSTRETCH_ENABLE))
-#define IS_I2C_CLOCK_SPEED(SPEED)				(((SPEED) > 0) && ((SPEED) <= I2C_EXTREME_FAST_MODE_MAX_CLK) )
-#define I2C_FREQ_RANGE(__PCLK__)				((__PCLK__) / 1000000)
-#define I2C_MEM_ADD_MSB(__ADDRESS__)				((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) &\
-        (uint16_t)(0xFF00))) >> 8)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__)				((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-#define IS_I2C_IT(x)						(((x) == I2C_IT_TXE)	|| \
-                                                                 ((x) == I2C_IT_TXOV)	|| \
-                                                                 ((x) == I2C_IT_TXUD)	|| \
-                                                                 ((x) == I2C_IT_TXTH)	|| \
-                                                                 ((x) == I2C_IT_RXF)	|| \
-                                                                 ((x) == I2C_IT_RXOV)	|| \
-                                                                 ((x) == I2C_IT_RXUD)	|| \
-                                                                 ((x) == I2C_IT_RXTH)	|| \
-                                                                 ((x) == I2C_IT_TC)	|| \
-                                                                 ((x) == I2C_IT_TCR)	|| \
-                                                                 ((x) == I2C_IT_ADDR)	|| \
-                                                                 ((x) == I2C_IT_NACK)	|| \
-                                                                 ((x) == I2C_IT_STOP)	|| \
-                                                                 ((x) == I2C_IT_BERR)	|| \
-                                                                 ((x) == I2C_IT_ARLO)	|| \
-                                                                 ((x) == I2C_IT_PECE)	|| \
-								 ((x) == I2C_IT_TOUT)	|| \
-								 ((x) == I2C_IT_ALERT))
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Public_Functions
-  * @{
-  */
-
-/** @addtogroup I2C_Public_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-ald_status_t ald_i2c_init(i2c_handle_t *hperh);
-ald_status_t ald_i2c_reset(i2c_handle_t *hperh);
-
-/**
- * @}
- */
-
-/** @addtogroup I2C_Public_Functions_Group2 Input and Output operation functions
- * @{
- */
- /** Blocking mode: Polling */
-ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr,
-                                 uint8_t *buf, uint32_t size, uint32_t timeout);
-ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr,
-                                uint8_t *buf, uint32_t size, uint32_t timeout);
-ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout);
-ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout);
-ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                           i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout);
-ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                          i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout);
-
- /** Non-Blocking mode: Interrupt */
-ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size);
-ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size);
-ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size);
-ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size);
-ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                              i2c_addr_size_t add_size, uint8_t *buf, uint32_t size);
-ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                             i2c_addr_size_t add_size, uint8_t *buf, uint32_t size);
-
-
- /** Non-Blocking mode: DMA */
-ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr,
-                                     uint8_t *buf, uint8_t size, uint8_t channel);
-ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr,
-                                    uint8_t *buf, uint8_t size, uint8_t channel);
-ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel);
-ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel);
-ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size,
-                                 uint8_t *buf, uint8_t size, uint8_t channel);
-ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                                i2c_addr_size_t add_size, uint8_t *buf, uint8_t size, uint8_t channel);
-
-/**
- * @}
- */
-
-/** @addtogroup I2C_Public_Functions_Group3 Peripheral state and Errors functions
-  * @{
-  */
-i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh);
-uint32_t ald_i2c_get_error(i2c_handle_t *hperh);
-void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag);
-flag_status_t ald_i2c_get_mask_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag);
-flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag);
-it_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it);
-/**
- * @}
- */
-
-/** @addtogroup I2C_Public_Functions_Group4 IRQ Handler and Callbacks
- * @{
- */
-void ald_i2c_ev_irq_handler(i2c_handle_t *hperh);
-void ald_i2c_er_irq_handler(i2c_handle_t *hperh);
-void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
-  * @}
-  */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_I2C_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_i2s.h

@@ -1,391 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_i2s.c
-  * @brief   Header file of I2S module driver.
-  *
-  * @version V1.0
-  * @date    13 Nov 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          13 Nov 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_I2S_H__
-#define __ALD_I2S_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup I2S
-  * @{
-  */
-
-/** @defgroup I2S_Public_Types I2S Public Types
-  * @{
-  */
-
-/**
-  * @brief Channel length
-  */
-typedef enum {
-	I2S_WIDE_16 = 0x0U,	/**< Channel length is 16 */
-	I2S_WIDE_32 = 0x1U,	/**< Channel length is 32 */
-} i2s_chlen_t;
-
-/**
-  * @brief Data length 
-  */
-typedef enum {
-	I2S_LEN_16 = 0x0U,	/**< Data length is 16 */
-	I2S_LEN_24 = 0x1U,	/**< Data length is 24 */
-	I2S_LEN_32 = 0x2U,	/**< Data length is 32 */
-} i2s_datalen_t;
-
-/**
-  * @brief Inactive state clock polarity
-  */
-typedef enum {
-	I2S_INACTIVE_LOW  = 0x0U,	/**< Inactive state is low */
-	I2S_INACTIVE_HIGH = 0x1U,	/**< Inactive state is high */
-} i2s_cpol_t;
-
-/**
-  * @brief I2s standard
-  */
-typedef enum {
-	I2S_STD_PHI = 0x0U,	/**< Philips standard */
-	I2S_STD_MSB = 0x1U,	/**< MSB standard */
-	I2S_STD_LSB = 0x2U,	/**< LSB standard */
-	I2S_STD_PCM = 0x3U,	/**< PCM standard */
-} i2s_standard_t;
-
-/**
-  * @brief I2s configuration mode
-  */
-typedef enum {
-	I2S_MASTER_TRANSMIT = 0x2U,	/**< I2S master transmit mode */	
-	I2S_MASTER_RECEIVE  = 0x3U,	/**< I2S master receive mode */	
-} i2s_cfg_t;
-
-/**
-  * @brief Pcm frame synchronization
-  */
-typedef enum {
-	I2S_FRAME_SHORT = 0x0U,	/**< I2S PCM short frame */
-	I2S_FRAME_LONG  = 0x1U,	/**< I2S PCM long frame */
-} i2s_pcms_t;
-
-/**
-  * @brief I2S error status
-  */
-typedef enum {
-	I2S_ERROR_NONE = 0x0U,	/**< none */
-	I2S_ERROR_MODF = 0x1U,	/**< mode fault */
-	I2S_ERROR_DMA  = 0x2U,	/**< crc error */
-	I2S_ERROR_FRE  = 0x4U,	/**< frame error */ 
-	I2S_ERROR_RXOV = 0x8U,	/**< receive over error */
-	I2S_ERROR_TXOV = 0x10U,	/**< dma error  */
-	I2S_ERROR_FLAG = 0x20U,	/**< interrupt flag error */
-} i2s_error_t;
-
-/**
-  * @brief interrupt control
-  */
-typedef enum {
-	I2S_IT_TXE    = (1U << 0),	/**< Transmit fifo empty interrupt */
-	I2S_IT_TXOV   = (1U << 2),	/**< Transmit fifo overflow interrupt */
-	I2S_IT_TXUD   = (1U << 3),	/**< Transmit fifo underflow interrupt */
-	I2S_IT_RXF    = (1U << 9),	/**< Receive fifo full interrupt */
-	I2S_IT_RXOV   = (1U << 10),	/**< Receive fifo overflow interrupt */
-	I2S_IT_RXUD   = (1U << 11),	/**< Receive fifo underflow interrupt */
-	I2S_IT_RXTH   = (1U << 12),	/**< Receive fifo over threshold interrupt */
-	I2S_IT_CRCERR = (1U << 16),	/**< Crc error interrupt */
-	I2S_IT_MODF   = (1U << 17),	/**< Mode error interrupt */
-	I2S_IT_FRE    = (1U << 18),	/**< Frame error interrupt */
-} i2s_it_t;
-
-/**
-  * @brief I2S dma request definition
-  */
-typedef enum {
-	I2S_DMA_REQ_TX = 0U,	/**< TX dma request */
-	I2S_DMA_REQ_RX = 1U,	/**< RX dma request */
-} i2s_dma_req_t;
-
-/**
-  * @brief interrupt flag
-  */
-typedef enum {
-	I2S_IF_TXE  = (1U << 0),	/**< Transmit fifo empty interrupt flag */
-	I2S_IF_TXOV = (1U << 2),	/**< Transmit fifo overflow interrupt flag */
-	I2S_IF_TXUD = (1U << 3),	/**< Transmit fifo underflow interrupt flag */
-	I2S_IF_RXF  = (1U << 9),	/**< Receive fifo full interrupt flag */
-	I2S_IF_RXOV = (1U << 10),	/**< Receive fifo overflow interrupt flag */
-	I2S_IF_RXUD = (1U << 11),	/**< Receive fifo underflow interrupt flag */
-	I2S_IF_RXTH = (1U << 12),	/**< Receive fifo over threshold interrupt flag */
-	I2S_IF_FRE  = (1U << 18),	/**< Frame error interrupt flag */
-} i2s_flag_t;
-
-/**
-  * @brief I2S state structures definition
-  */
-typedef enum {
-	I2S_STATE_RESET      = 0x00U,	/**< Peripheral is not initialized */
-	I2S_STATE_READY      = 0x01U,	/**< Peripheral Initialized and ready for use */
-	I2S_STATE_BUSY       = 0x02U,	/**< an internal process is ongoing */
-	I2S_STATE_BUSY_TX    = 0x11U,	/**< transmit is ongoing */
-	I2S_STATE_BUSY_RX    = 0x21U,	/**< receive is ongoing */
-	I2S_STATE_BUSY_TX_RX = 0x31U,	/**< transmit and receive are ongoing */
-	I2S_STATE_TIMEOUT    = 0x03U,	/**< Timeout state */
-	I2S_STATE_ERROR      = 0x04U,	/**< Error */
-} i2s_state_t;
-
-/**
-  * @brief I2S status definition
-  */
-typedef enum {
-	I2S_STATUS_TXE    = (1U << 0),	/**< Transmit fifo empty status */
-	I2S_STATUS_TXF    = (1U << 1),	/**< Transmit fifo full status */
-	I2S_STATUS_TXOV   = (1U << 2),	/**< Transmit fifo overflow status */
-	I2S_STATUS_TXUD   = (1U << 3),  /**< Transmit fifo underflow status */
-	I2S_STATUS_RXE    = (1U << 8),  /**<  Receive fifo empty status */
-	I2S_STATUS_RXF    = (1U << 9),  /**< Receive fifo full status */
-	I2S_STATUS_RXOV   = (1U << 10), /**< Receive fifo overflow status */
-	I2S_STATUS_RXUD   = (1U << 11), /**< Receive fifo underflow status */
-	I2S_STATUS_CHSIDE = (1U << 14), /**< Sound channel status */
-	I2S_STATUS_BUSY   = (1U << 15), /**< BUSY status */
-} i2s_status_t;
-
-/**
-  * @brief Channel side
-  */
-typedef enum {
-	I2S_SIDE_LEFT  = 0U,	/**< Sound channel is left */
-	I2S_SIDE_RIGHT = 1U,	/**< Sound channel is right */
-} i2s_ch_side_t;
-
-/**
-  * @brief I2S TXE/RXNE status definition
-  */
-typedef enum {
-	I2S_SR_TXE      = 0U,	/**< STAT TXE set */
-	I2S_SR_RXNE     = 1U,	/**< STAT RXTH set */
-	I2S_SR_TXE_RXNE = 2U,	/**< STAT TXE and RXTH set */
-} i2s_sr_status_t;
-
-/**
-  * @brief I2S init structure definition
-  */
-typedef struct {
-	i2s_chlen_t ch_len;		/**< Channel length choose */
-	i2s_datalen_t data_len;		/**< Data length choose */
-	i2s_cpol_t polarity;		/**< Inactive clock polarity */
-	i2s_standard_t standard;	/**< Standard choose */
-	i2s_pcms_t pcm_frame;		/**< PCM frame synchronization */
-	type_func_t ext_clk_en;		/**< Choose external clock or APB1 clock */
-	uint32_t ext_clk;		/**< External clock, unit is Hz */
-	type_func_t mck_en;		/**< Main clock output function */
-	uint32_t sampling;		/**< Sampling rate. eg. 192*1024-192KHz, 96*1024-96KHz */
-} i2s_init_t;
-
-/**
-  * @brief  I2S handle structure definition
-  */
-typedef struct i2s_handle_s {
-	SPI_I2S_TypeDef *perh;	/**< I2S registers base address */
-	i2s_init_t init;	/**< I2S communication parameters */
-	uint16_t *tx_buf;	/**< Pointer to I2S Tx transfer buffer */
-	uint32_t tx_size;	/**< I2S Tx transfer size */
-	uint32_t tx_count;	/**< I2S Tx transfer counter */
-	uint16_t *rx_buf;	/**< Pointer to I2S Rx transfer buffer */
-	uint32_t rx_size;	/**< I2S Rx Transfer size */
-	uint32_t rx_count;	/**< I2S Rx Transfer Counter */
-
-	dma_handle_t hdmatx;	/**< I2S DMA handle parameters */
-	dma_handle_t hdmarx;	/**< I2S DMA handle parameters */
-
-	lock_state_t lock;	/**< Locking object */
-	i2s_state_t state;	/**< I2S communication state */
-	uint8_t side;		/**< I2S channel side */
-	uint32_t err_code;	/**< I2S error code */
-
-	void (*tx_cplt_cbk)(struct i2s_handle_s *arg);		/**< Tx completed callback */
-	void (*rx_cplt_cbk)(struct i2s_handle_s *arg);		/**< Rx completed callback */
-	void (*err_cbk)(struct i2s_handle_s *arg);		/**< error callback */
-} i2s_handle_t;
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Public_Macros I2S Public Macros
-  * @{
-  */
-#define I2S_RESET_HANDLE_STATE(x)	((x)->state = I2S_STATE_RESET)
-#define I2S_ENABLE(x)			(SET_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK))
-#define I2S_DISABLE(x)			(CLEAR_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Private_Macros   I2S Private Macros
-  * @{
-  */
-#define IS_I2S(x)		(((x) == I2S0) || \
-				 ((x) == I2S1) || \
-				 ((x) == I2S2))
-#define IS_I2S_CH_LEN(x)	(((x) == I2S_WIDE_16) || \
-				 ((x) == I2S_WIDE_32))
-#define IS_I2S_DATE_LEN(x)	(((x) == I2S_LEN_16) || \
-				 ((x) == I2S_LEN_24) || \
-				 ((x) == I2S_LEN_32))
-#define IS_I2S_CPOL(x)		(((x) == I2S_INACTIVE_LOW) || \
-				 ((x) == I2S_INACTIVE_HIGH))
-#define IS_I2S_STANDARD(x)	(((x) == I2S_STD_PHI) || \
-				 ((x) == I2S_STD_MSB) || \
-				 ((x) == I2S_STD_LSB) || \
-				 ((x) == I2S_STD_PCM))
-#define IS_I2S_PCMS(x)		(((x) == I2S_FRAME_SHORT) || \
-				 ((x) == I2S_FRAME_LONG))
-#define IS_I2S_IT(x)		(((x) == I2S_IT_TXE)    || \
-				 ((x) == I2S_IT_TXOV)   || \
-				 ((x) == I2S_IT_TXUD)   || \
-				 ((x) == I2S_IT_RXF)    || \
-				 ((x) == I2S_IT_RXOV)   || \
-				 ((x) == I2S_IT_RXUD)   || \
-				 ((x) == I2S_IT_RXTH)   || \
-				 ((x) == I2S_IT_CRCERR) || \
-				 ((x) == I2S_IT_MODF)   || \
-				 ((x) == I2S_IT_FRE))
-#define IS_I2S_IF(x)		(((x) == I2S_IF_TXE)    || \
-				 ((x) == I2S_IF_TXOV)   || \
-				 ((x) == I2S_IF_TXUD)   || \
-				 ((x) == I2S_IF_RXF)    || \
-				 ((x) == I2S_IF_RXOV)   || \
-				 ((x) == I2S_IF_RXUD)   || \
-				 ((x) == I2S_IF_RXTH)   || \
-				 ((x) == I2S_IF_FRE))
-#define IS_I2S_FLAG(x)		(((x) == I2S_FLAG_TXE)    || \
-				 ((x) == I2S_FLAG_TXF)    || \
-				 ((x) == I2S_FLAG_TXOV)   || \
-				 ((x) == I2S_FLAG_TXUD)   || \
-				 ((x) == I2S_FLAG_RXE)    || \
-				 ((x) == I2S_FLAG_RXF)    || \
-				 ((x) == I2S_FLAG_RXOV)   || \
-				 ((x) == I2S_FLAG_RXUD)   || \
-				 ((x) == I2S_FLAG_CHSIDE) || \
-				 ((x) == I2S_FLAG_BSY))
-#define IS_I2S_STATUS(x)	(((x) == I2S_STATUS_TXE)    || \
-				 ((x) == I2S_STATUS_TXF)    || \
-				 ((x) == I2S_STATUS_TXOV)   || \
-				 ((x) == I2S_STATUS_TXUD)   || \
-				 ((x) == I2S_STATUS_RXE)    || \
-				 ((x) == I2S_STATUS_RXF)    || \
-				 ((x) == I2S_STATUS_RXOV)   || \
-				 ((x) == I2S_STATUS_RXUD)   || \
-				 ((x) == I2S_STATUS_CHSIDE) || \
-				 ((x) == I2S_STATUS_BUSY))
-#define IS_I2S_DMA_REQ(x)	(((x) == I2S_DMA_REQ_TX) || \
-				 ((x) == I2S_DMA_REQ_RX))
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Public_Functions
-  * @{
-  */
-
-/** @addtogroup I2S_Public_Functions_Group1
-  * @{
-  */
-
-ald_status_t ald_i2s_init(i2s_handle_t *hperh);
-void ald_i2s_reset(i2s_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Public_Functions_Group2
-  * @{
-  */
-ald_status_t ald_i2s_master_send(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout);
-ald_status_t ald_i2s_master_recv(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout);
-ald_status_t ald_i2s_master_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size);
-ald_status_t ald_i2s_master_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size);
-
-ald_status_t ald_i2s_master_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel);
-ald_status_t ald_i2s_master_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch);
-ald_status_t ald_i2s_dma_pause(i2s_handle_t *hperh);
-ald_status_t ald_i2s_dma_resume(i2s_handle_t *hperh);
-ald_status_t ald_i2s_dma_stop(i2s_handle_t *hperh);
-
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Public_Functions_Group3
-  * @{
-  */
-void ald_i2s_irq_handler(i2s_handle_t *hperh);
-void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state);
-void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state);
-flag_status_t ald_i2s_get_status(i2s_handle_t *hperh, i2s_status_t status);
-it_status_t ald_i2s_get_it_status(i2s_handle_t *hperh, i2s_it_t it);
-flag_status_t ald_i2s_get_flag_status(i2s_handle_t *hperh, i2s_flag_t flag);
-flag_status_t ald_i2s_get_mask_flag_status(i2s_handle_t *hperh, i2s_flag_t flag);
-void ald_i2s_clear_flag_status(i2s_handle_t *hperh, i2s_flag_t flag);
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Public_Functions_Group4
-  * @{
-  */
-i2s_state_t ald_i2s_get_state(i2s_handle_t *hperh);
-uint32_t ald_i2s_get_error(i2s_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-#endif

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_iap.h

@@ -1,104 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_iap.h
-  * @brief   Header file of IAP module driver.
-  *
-  * @version V1.0
-  * @date    04 Dec 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          04 Dec 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_IAP_H__
-#define __ALD_IAP_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup IAP
-  * @{
-  */
-
-/**
-  * @defgroup IAP_Private_Macros IAP Private Macros
-  * @{
-  */
-#define IAP_WSP_ADDR	    0x10000000U
-#define IAP_PE_ADDR	    0x10000004U
-#define IAP_WP_ADDR	    0x10000008U
-#define IAP_DWP_ADDR	    0x1000000cU
-#define IAP_WordsProgram_DF 0x10000010U
-#define IAP_PageErase_DF    0x10000014U
-#define IAP_WordProgram_DF  0x10000018U
-#define IAP_DWordProgram_DF 0x1000001cU
-/**
-  * @}
-  */
-
-/** @defgroup IAP_Private_Types IAP Private Types
-  * @{
-  */
-typedef uint32_t (*IAP_PE)(uint32_t addr);
-typedef uint32_t (*IAP_WP)(uint32_t addr, uint32_t data);
-typedef uint32_t (*IAP_DWP)(uint32_t addr, uint32_t data_l, uint32_t data_h);
-typedef uint32_t (*IAP_WSP)(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase);
-/**
-  * @}
-  */
-
-/** @addtogroup IAP_Public_Functions
-  * @{
-  */
-uint32_t ald_iap_erase_page(uint32_t addr);
-uint32_t ald_iap_program_word(uint32_t addr, uint32_t data);
-uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h);
-uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase);
-uint32_t ald_iap_erase_page_df(uint32_t addr);
-uint32_t ald_iap_program_word_df(uint32_t addr, uint32_t data);
-uint32_t ald_iap_program_dword_df(uint32_t addr, uint32_t data_l, uint32_t data_h);
-uint32_t ald_iap_program_words_df(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_IAP_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_nand.h

@@ -1,222 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_nand.h
-  * @brief   Header file of EBI_NAND module driver
-  *
-  * @version V1.0
-  * @date    07 Dec 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          07 Dec 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_NAND_H_
-#define __ALD_NAND_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "ald_ebi.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup NAND 
-  * @{
-  */
-
-/** @defgroup NAND_Public_Types NAND Public Types
-  * @{
-  */
-
-/** 
-  * @brief NAND State structures definition
-  */
-typedef enum {
-	ALD_NAND_STATE_RESET = 0x00U,	/**< NAND not yet initialized or disabled */
-	ALD_NAND_STATE_READY = 0x01U,	/**< NAND initialized and ready for use */
-	ALD_NAND_STATE_BUSY  = 0x02U,	/**< NAND internal process is ongoing */
-	ALD_NAND_STATE_ERROR = 0x03U	/**< NAND error state */
-} ald_nand_state_t;
-
-/** 
-  * @brief  NAND Memory electronic signature Structure definition
-  */
-typedef struct {
-	uint8_t maker_id;	/**< Maker id */
-	uint8_t device_id;	/**< Device id */
-	uint8_t third_id;	/**< Third id */
-	uint8_t fourth_id;	/**< Fourth id */
-} nand_id_t;
-
-/** 
-  * @brief  NAND Memory address Structure definition
-  */
-typedef struct
-{
-	uint16_t page;	/**< NAND memory Page address */
-	uint16_t plane;	/**< NAND memory Plane address */	
-	uint16_t block;	/**< NAND memory Block address */
-} nand_address_t;
-
-/** 
-  * @brief  NAND Memory info Structure definition
-  */ 
-typedef struct
-{
-	uint32_t page_size;	/**< NAND memory page (without spare area) size measured in bytes */
-	uint32_t spare_size;	/**< NAND memory spare area size measured in bytes */
-	uint32_t block_size;	/**< NAND memory block size measured in number of pages */
-	uint32_t block_nbr;     /**< NAND memory number of total block */
-	uint32_t plane_nbr;	/**< NAND memory number of planes */	
-	uint32_t plane_size;	/**< NAND memory plane size measured in number of blocks */
-	type_func_t extra_cmd;	/**< NAND extra command needed for Page reading mode */                                        
-} nand_device_cfg_t;
-
-/** 
-  * @brief  NAND handle Structure definition
-  */   
-typedef struct
-{
-	EBI_NAND_TypeDef *instance;	/**< Register base address */
-	ald_ebi_nand_init_t init;	/**< NAND device control configuration parameters */
-	lock_state_t lock;		/**< NAND locking object */
-	__IO ald_nand_state_t state;	/**< NAND device access state */
-	nand_device_cfg_t config;	/**< NAND phusical characteristic information structure */	
-} nand_handle_t;
-
-/**
-  * @}
-  */
-
-/**
-  * @defgroup Nand_Private_Constants Nand Private Constants
-  * @{
-  */
-
-#define NAND_DEVICE1               EBI_BANK2
-#define NAND_DEVICE2               EBI_BANK3
-#define NAND_WRITE_TIMEOUT         1000U
-#define CMD_AREA                   (1U<<16U)	/* A16 = CLE high */
-#define ADDR_AREA                  (1U<<17U)	/* A17 = ALE high */
-#define NAND_CMD_AREA_A            ((uint8_t)0x00U)
-#define NAND_CMD_AREA_B            ((uint8_t)0x01U)
-#define NAND_CMD_AREA_C            ((uint8_t)0x50U)
-#define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30U)
-#define NAND_CMD_WRITE0            ((uint8_t)0x80U)
-#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10U)
-#define NAND_CMD_ERASE0            ((uint8_t)0x60U)
-#define NAND_CMD_ERASE1            ((uint8_t)0xD0U)
-#define NAND_CMD_READID            ((uint8_t)0x90U)
-#define NAND_CMD_STATUS            ((uint8_t)0x70U)
-#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7AU)
-#define NAND_CMD_RESET             ((uint8_t)0xFFU)
-/* NAND memory status */
-#define NAND_VALID_ADDRESS         0x00000100U
-#define NAND_INVALID_ADDRESS       0x00000200U
-#define NAND_TIMEOUT_ERROR         0x00000400U
-#define NAND_BUSY                  0x00000000U
-#define NAND_ERROR                 0x00000001U
-#define NAND_READY                 0x00000040U
-/**
-  * @}
-  */
-
-/** @defgroup Nand_Private_Macros Nand Private Macros
-  * @{
-  */
-#define ARRAY_ADDRESS(x , y)	((x)->page +   \
-		(((x)->block + (((x)->plane) * \
-		((y)->config.plane_size))) * ((y)->config.block_size)))
-#define COLUMN_ADDRESS( x)	((x)->config.page_size)
-#define ADDR_1ST_CYCLE(x)	(uint8_t)(x)		/* 1st addressing cycle */
-#define ADDR_2ND_CYCLE(x)	(uint8_t)((x) >> 8U)	/* 2nd addressing cycle */
-#define ADDR_3RD_CYCLE(x)	(uint8_t)((x) >> 16U)	/* 3rd addressing cycle */
-#define ADDR_4TH_CYCLE(x)	(uint8_t)((x) >> 24U)	/* 4th addressing cycle */
-#define COLUMN_1ST_CYCLE(x)	(uint8_t)(x)		/* 1st Column addressing cycle */
-#define COLUMN_2ND_CYCLE(x)	(uint8_t)((x) >> 8U)	/* 2nd Column addressing cycle */
-/**
-  * @}
-  */
-
-/** @addtogroup Nand_Public_Functions
- *  @{
- */
-/** @addtogroup Nand_Public_Functions_Group1
- *  @{
- */
-/* Initialization/de-initialization functions */
-ald_status_t ald_nand_init(nand_handle_t *hperh, ald_ebi_nand_timing_t *ctiming, ald_ebi_nand_timing_t *atiming);
-ald_status_t ald_nand_deinit(nand_handle_t *hperh);
-ald_status_t ald_nand_reset(nand_handle_t *hperh);
-void nand_config_device(nand_handle_t *hperh, nand_device_cfg_t *pdcfg);
-/**
-  * @}
-  */
-/** @addtogroup Nand_Public_Functions_Group2
- *  @{
- */
-/* IO operation functions */
-ald_status_t ald_nand_read_id(nand_handle_t *hperh, nand_id_t *id);
-ald_status_t ald_nand_read_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr);
-ald_status_t ald_nand_write_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr);
-ald_status_t ald_nand_read_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr);
-ald_status_t ald_nand_write_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr);
-ald_status_t ald_nand_read_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr);
-ald_status_t ald_nand_write_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr);
-ald_status_t ald_nand_read_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr);
-ald_status_t ald_nand_write_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr);
-ald_status_t ald_nand_erase_block(nand_handle_t *hperh, nand_address_t *addr);
-/**
-  * @}
-  */
-/** @addtogroup Nand_Public_Functions_Group3
- *  @{
- */
-/* NAND Control functions */
-void ald_nand_irq_handler(nand_handle_t *hperh);
-void ald_nand_irq_cbk(nand_handle_t *hperh);
-uint32_t ald_nand_address_inc(nand_handle_t *hperh, nand_address_t *addr);
-uint32_t ald_nand_read_status(nand_handle_t *hperh);
-ald_nand_state_t ald_nand_get_state(nand_handle_t *hperh);
-ald_status_t ald_nand_ecc_enable(nand_handle_t *hperh);
-ald_status_t ald_nand_ecc_disable(nand_handle_t *hperh);
-ald_status_t ald_nand_get_ecc(nand_handle_t *hperh, uint32_t *val, uint32_t timeout);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-#endif

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_nor_lcd.h

@@ -1,236 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_nor_lcd.h
-  * @brief   Header file of EBI_NOR_LCD module driver
-  *
-  * @version V1.0
-  * @date    07 Dec 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          07 Dec 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_NOR_LCD_H_
-#define __ALD_NOR_LCD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "ald_ebi.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup NOR_LCD
-  * @{
-  */ 
-
-/**
-  * @defgroup NOR_LCD_Private_Constants NOR LCD Private Constants
-  * @{
-  */
-
-/* NOR device IDs addresses */
-#define MC_ADDRESS               ((uint16_t)0x0000U)
-#define DEVICE_CODE1_ADDR        ((uint16_t)0x0001U)
-#define DEVICE_CODE2_ADDR        ((uint16_t)0x000EU)
-#define DEVICE_CODE3_ADDR        ((uint16_t)0x000FU)
-
-/* NOR CFI IDs addresses */
-#define CFI1_ADDRESS             ((uint16_t)0x10U)
-#define CFI2_ADDRESS             ((uint16_t)0x11U)
-#define CFI3_ADDRESS             ((uint16_t)0x12U)
-#define CFI4_ADDRESS             ((uint16_t)0x13U)
-
-/* NOR operation wait timeout */
-#define NOR_TMEOUT               ((uint16_t)0xFFFFU)
-
-/* NOR memory data width */
-#define NOR_MEMORY_8B            ((uint8_t)0x0U)
-#define NOR_MEMORY_16B           ((uint8_t)0x1U)
-
-/* NOR memory device read/write start address */
-#define NOR_MEMORY_ADRESS1       EBI_BANK1_1
-#define NOR_MEMORY_ADRESS2       EBI_BANK1_2
-#define NOR_MEMORY_ADRESS3       EBI_BANK1_3
-#define NOR_MEMORY_ADRESS4       EBI_BANK1_4
-
-#define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555U
-#define NOR_CMD_ADDRESS_FIRST_CFI             (uint16_t)0x0055U
-#define NOR_CMD_ADDRESS_SECOND                (uint16_t)0x02AAU
-#define NOR_CMD_ADDRESS_THIRD                 (uint16_t)0x0555U
-#define NOR_CMD_ADDRESS_FOURTH                (uint16_t)0x0555U
-#define NOR_CMD_ADDRESS_FIFTH                 (uint16_t)0x02AAU
-#define NOR_CMD_ADDRESS_SIXTH                 (uint16_t)0x0555U
-
-#define NOR_CMD_DATA_READ_RESET               (uint16_t)0x00F0U
-#define NOR_CMD_DATA_FIRST                    (uint16_t)0x00AAU
-#define NOR_CMD_DATA_SECOND                   (uint16_t)0x0055U
-#define NOR_CMD_DATA_AUTO_SELECT              (uint16_t)0x0090U
-#define NOR_CMD_DATA_PROGRAM                  (uint16_t)0x00A0U
-#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD   (uint16_t)0x0080U
-#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH  (uint16_t)0x00AAU
-#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH   (uint16_t)0x0055U
-#define NOR_CMD_DATA_CHIP_ERASE               (uint16_t)0x0010U
-#define NOR_CMD_DATA_CFI                      (uint16_t)0x0098U
-#define NOR_CMD_DATA_BUFFER_AND_PROG          (uint8_t)0x25U
-#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM  (uint8_t)0x29U
-#define NOR_CMD_DATA_BLOCK_ERASE              (uint8_t)0x30U
-#define NOR_MASK_STATUS_DQ5                   (uint16_t)0x0020U
-#define NOR_MASK_STATUS_DQ6                   (uint16_t)0x0040U
-/**
-  * @}
-  */
-
-/** @defgroup NOR_LCD_Private_Macros NOR_LCD Private Macros
-  * @{
-  */
-#define NOR_ADDR_SHIFT(NOR_ADDR, NOR_MEMORY_WIDTH_, ADDRESS)	\
-	((uint32_t)(((NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B) ? 	\
-	((uint32_t)((NOR_ADDR) + (2U * (ADDRESS)))):		\
-	((uint32_t)((NOR_ADDR) + (ADDRESS)))))
-#define NOR_WRITE(ADDR, DATA)  (*(__IO uint16_t *)((uint32_t)(ADDR)) = (DATA))
-/**
-  * @}
-  */
-
-/** @defgroup NOR_LCD_Public_Types NOR_LCD Public Types
-  * @{
-  */ 
-/** 
-  * @brief  ALD SRAM State structures definition  
-  */ 
-typedef enum {
-	ALD_NOR_STATE_RESET     = 0x00U,	/**< NOR not yet initialized or disabled */
-	ALD_NOR_STATE_READY     = 0x01U,	/**< NOR initialized and ready for use */
-	ALD_NOR_STATE_BUSY      = 0x02U,	/**< NOR internal processing is ongoing */
-	ALD_NOR_STATE_ERROR     = 0x03U,	/**< NOR error state */ 
-	ALD_NOR_STATE_PROTECTED = 0x04U		/**< NOR NORSRAM device write protected */
-} ald_nor_state_t;
-
-/**
-  * @brief  EBI NOR Status typedef
-  */
-typedef enum {
-	ALD_NOR_STATUS_SUCCESS = 0U,	/**< NOR status success */
-	ALD_NOR_STATUS_ONGOING,		/**< NOR status ongoing */
-	ALD_NOR_STATUS_ERROR,		/**< NOR status error */
-	ALD_NOR_STATUS_TIMEOUT,		/**< NOR status timeout */
-} nor_status_t;
-
-/**
-  * @brief  EBI NOR ID typedef
-  */
-typedef struct {
-	uint16_t m_code;	/**< Defines the device's manufacturer code used to identify the memory */
-	uint16_t device_code1;	/**< DEVICE_CODE1_ADDR code1 */
-	uint16_t device_code2;	/**< DEVICE_CODE1_ADDR code2 */
-	uint16_t device_code3;	/**< DEVICE_CODE1_ADDR code3 */
-} nor_id_t;
-
-/**
-  * @brief  EBI NOR CFI typedef
-  */
-typedef struct {
-	uint16_t cfi_1;  /**< NOR CFI 1 */
-	uint16_t cfi_2;  /**< NOR CFI 2 */
-	uint16_t cfi_3;  /**< NOR CFI 3 */
-	uint16_t cfi_4;  /**< NOR CFI 4 */
-} nor_cfi_t;
-
-/** 
-  * @brief  NOR handle Structure definition  
-  */ 
-typedef struct {
-	EBI_NOR_SRAM_TypeDef *instance;		/**< Register base address */ 
-	EBI_NOR_SRAM_EXTENDED_TypeDef *ext;	/**< Extended mode register base address */
-	ald_ebi_nor_sram_init_t init;		/**< NOR device control configuration parameters */
-	lock_state_t lock;			/**< NOR locking object */ 
-	__IO ald_nor_state_t state;		/**< NOR device access state */
-} nor_handle_t;
-/**
-  * @}
-  */
-
-/** @addtogroup NOR_Public_Functions
- *  @{
- */
-/** @addtogroup NOR_Public_Functions_Group1
- *  @{
- */
-/* Initialization/de-initialization functions */  
-ald_status_t ald_nor_init(nor_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing);
-ald_status_t ald_nor_deinit(nor_handle_t *hperh);
-/**
-  * @}
-  */
-/** @addtogroup NOR_LCD_Public_Functions_Group2
- *  @{
- */
-/* I/O operation functions */
-ald_status_t ald_nor_read_id(nor_handle_t *hperh, nor_id_t *id);
-ald_status_t ald_nor_return_readmode(nor_handle_t *hperh);
-ald_status_t ald_nor_read(nor_handle_t *hperh, uint32_t *addr, uint16_t *data);
-ald_status_t ald_nor_program(nor_handle_t *hperh, uint32_t *addr, uint16_t *data);
-ald_status_t ald_nor_read_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size);
-ald_status_t ald_nor_program_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size);
-ald_status_t ald_nor_erase_block(nor_handle_t *hperh, uint32_t blkaddr, uint32_t addr);
-ald_status_t ald_nor_erase_chip(nor_handle_t *hperh);
-ald_status_t ald_nor_read_cfi(nor_handle_t *hperh, nor_cfi_t *cfi);
-/**
-  * @}
-  */
-/** @addtogroup NOR_LCD_Public_Functions_Group3
- *  @{
- */
-/* Control functions */
-ald_status_t ald_nor_write_enable(nor_handle_t *hperh);
-ald_status_t ald_nor_write_disable(nor_handle_t *hperh);
-/**
-  * @}
-  */
-/** @addtogroup NOR_LCD_Public_Functions_Group4
- *  @{
- */
-/* State functions */
-ald_nor_state_t ald_nor_get_state(nor_handle_t *hperh);
-nor_status_t ald_nor_get_status(nor_handle_t *hperh, uint32_t addr, uint32_t timeout);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */ 
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_NOR_LCD_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_pis.h

@@ -1,727 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_pis.h
-  * @brief   Header file of PIS driver.
-  *
-  * @version V1.0
-  * @date    27 Nov 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          27 Nov 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_PIS_H__
-#define __ALD_PIS_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup PIS
-  * @{
-  */
-
-/** @defgroup PIS_Public_Types PIS Public Types
-  * @verbatim
-      In PIS module, for the convenience of code maintenance,
-      TIMERx is used to indicate the sequence of the timer peripheral.
-      Different product series TIMERx represent different meanings:
-      1. For ES32F36xx series:
-      TIMER0 ----> AD16C4T0
-      TIMER1 ----> AD16C4T1
-      TIMER2 ----> GP32C4T0
-      TIMER3 ----> GP32C4T1
-     
-      2. For ES32F393x/ES32F336x/ES32F392x series:
-      TIMER0 ----> GP16C4T0
-      TIMER1 ----> GP16C4T1
-      TIMER2 ----> GP32C4T0
-      TIMER3 ----> GP32C4T1
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief Producer entry
-  */
-typedef enum {
-	PIS_NON                 = 0x0U,		/**< No async */
-	PIS_GPIO_PIN0           = 0x10U,	/**< Pin0, level,support async */
-	PIS_GPIO_PIN1           = 0x11U,	/**< Pin1, level,support async */
-	PIS_GPIO_PIN2           = 0x12U,	/**< Pin2, level,support async */
-	PIS_GPIO_PIN3           = 0x13U,	/**< Pin3, level,support async */
-	PIS_GPIO_PIN4           = 0x14U,	/**< Pin4, level,support async */
-	PIS_GPIO_PIN5           = 0x15U,	/**< Pin5, level,support async */
-	PIS_GPIO_PIN6           = 0x16U,	/**< Pin6, level,support async */
-	PIS_GPIO_PIN7           = 0x17U,	/**< Pin7, level,support async */
-	PIS_GPIO_PIN8           = 0x18U,	/**< Pin8, level,support async */
-	PIS_GPIO_PIN9           = 0x19U,	/**< Pin9, level,support async */
-	PIS_GPIO_PIN10          = 0x1aU,	/**< Pin10, level,support async */
-	PIS_GPIO_PIN11          = 0x1bU,	/**< Pin11, level,support async */
-	PIS_GPIO_PIN12          = 0x1cU,	/**< Pin12, level,support async */
-	PIS_GPIO_PIN13          = 0x1dU,	/**< Pin13, level,support async */
-	PIS_GPIO_PIN14          = 0x1eU,	/**< Pin14, level,support async */
-	PIS_GPIO_PIN15          = 0x1fU,	/**< Pin15, level,support async */
-	PIS_ACMP_OUT0           = 0x30U,	/**< Acmp0 output, level,support async */
-	PIS_ACMP_OUT1           = 0x31U,	/**< Acmp1 output, level,support async */
-	PIS_DAC0_CH0            = 0x40U,	/**< Dac0 channel 0, pclk2 pulse,support async */
-	PIS_DAC0_CH1            = 0x41U,	/**< Dac0 channel 1, pclk2 pulse,support async */
-	PIS_ADC0_INSERT         = 0x60U,	/**< Adc0 insert, pclk2 pulse,support async */
-	PIS_ADC0_NORMAL         = 0x61U,	/**< Adc0 normal, pclk2 pulse,support async */
-	PIS_ADC0_RESERVE        = 0x62U,	/**< Adc0 reserve */
-	PIS_LVD                 = 0x70U,	/**< Lvd, level,support async */
-	PIS_UART0_RESERVE0      = 0x80U,	/**< Uart0 reserve bit 0 */
-	PIS_UART0_RESERVE1      = 0x81U,	/**< Uart0 reserve bit 1*/
-	PIS_UART0_IRDAOUT       = 0x82U,	/**< Uart0 irdaout, level,support async */
-	PIS_UART0_RTSOUT        = 0x83U,	/**< Uart0 rtsout, level,support async */
-	PIS_UART0_TXOUT         = 0x84U,	/**< Uart0 txout, level,support async */
-	PIS_UART0_SYN_SEND      = 0x85U,	/**< Uart0 syn send, pulse,support async */
-	PIS_UART0_SYN_RECV      = 0x86U,	/**< Uart0 syn recv, pulse,support async */
-	PIS_UART1_RESERVE0      = 0x90U,	/**< Uart1 reserve bit 0 */
-	PIS_UART1_RESERVE1      = 0x91U,	/**< Uart1 reserve bit 1*/
-	PIS_UART1_IRDA          = 0x92U,	/**< Uart1 irdaout, level,support async */
-	PIS_UART1_RTS           = 0x93U,	/**< Uart1 rtsout, level,support async */
-	PIS_UART1_TXOUT         = 0x94U,	/**< Uart1 txout, level,support async */
-	PIS_UART1_SYN_SEND      = 0x95U,	/**< Uart1 syn send, pulse,support async */
-	PIS_UART1_SYN_RECV      = 0x96U,	/**< Uart1 syn recv, pulse,support async */
-	PIS_UART2_RESERVE0      = 0xa0U,	/**< Uart2 reserve bit 0 */
-	PIS_UART2_RESERVE1      = 0xa1U,	/**< Uart2 reserve bit 1*/
-	PIS_UART2_IRDA          = 0xa2U,	/**< Uart2 irdaout, level,support async */
-	PIS_UART2_RTS           = 0xa3U,	/**< Uart2 rtsout, level,support async */
-	PIS_UART2_TXOUT         = 0xa4U,	/**< Uart2 txout, level,support async */
-	PIS_UART2_SYN_SEND      = 0xa5U,	/**< Uart2 syn send, pulse,support async */
-	PIS_UART2_SYN_RECV      = 0xa6U,	/**< Uart2 syn recv, pulse,support async */
-	PIS_UART3_RESERVE0      = 0xb1U,	/**< Uart3 reserve bit 0 */
-	PIS_UART3_RESERVE1      = 0xb2U,	/**< Uart3 reserve bit 1*/
-	PIS_UART3_IRDA          = 0xb3U,	/**< Uart3 irdaout, level,support async */
-	PIS_UART3_RTS           = 0xb4U,	/**< Uart3 rtsout, level,support async */
-	PIS_UART3_TXOUT         = 0xb5U,	/**< Uart3 txout, level,support async */
-	PIS_UART3_SYN_SEND      = 0xb6U,	/**< Uart3 syn send, pulse,support async */
-	PIS_UART3_SYN_RECV      = 0xb7U,	/**< Uart3 syn recv, pulse,support async */
-	PIS_UART4_RECV          = 0xc0U,	/**< uart4 recv, plck1 pulse */
-	PIS_UART4_SEND          = 0xc1U,	/**< uart4 send, plck1 pulse */
-	PIS_UART4_TXOUT         = 0xc2U,	/**< uart4 txout, plck1 level */
-	PIS_UART5_RECV          = 0xd0U,	/**< uart5 recv, plck1 pulse */
-	PIS_UART5_SEND          = 0xd1U,	/**< uart5 send, plck1 pulse */
-	PIS_UART5_TXOUT         = 0xd2U,	/**< uart5 txout, plck1 level */
-	PIS_SPI0_RECV           = 0xe0U,	/**< Spi0 recv, plck1 pulse */
-	PIS_SPI0_SEND           = 0xe1U,	/**< Spi0 send, plck1 pulse */
-	PIS_SPI0_NE             = 0xe2U,	/**< Spi0 ne, plck1 level */
-	PIS_SPI1_RECV           = 0xf0U,	/**< Spi1 recv, plck1 pulse */
-	PIS_SPI1_SEND           = 0xf1U,	/**< Spi1 send, plck1 pulse */
-	PIS_SPI1_NE             = 0xf2U,	/**< Spi1 ne, plck1 level */
-	PIS_I2C0_RECV           = 0x100U,	/**< I2c0 recv, plck1 level */
-	PIS_I2C0_SEND           = 0x101U,	/**< I2c0 send, plck1 level */
-	PIS_I2C1_RECV           = 0x110U,	/**< I2c1 recv, plck1 level */
-	PIS_I2C1_SEND           = 0x111U,	/**< I2c1 send, plck1 level */
-	PIS_TIMER0_UPDATA       = 0x120U,	/**< Timer0 updata, plck1 pulse */
-	PIS_TIMER0_TRIG         = 0x121U,	/**< Timer0 trig, plck1 pulse */
-	PIS_TIMER0_INPUT_1      = 0x122U,	/**< Timer0 chan1 input catch, plck1 pulse */
-	PIS_TIMER0_OUTPUT_1     = 0x123U,	/**< Timer0 chan1 output compare, plck1 pulse */
-	PIS_TIMER0_INPUT_2      = 0x124U,	/**< Timer0 chan2 input catch, plck1 pulse */
-	PIS_TIMER0_OUTPUT_2     = 0x125U,	/**< Timer0 chan2 output compare, plck1 pulse */
-	PIS_TIMER0_INPUT_3      = 0x126U,	/**< Timer0 chan3 input catch, plck1 pulse */
-	PIS_TIMER0_OUTPUT_3     = 0x127U,	/**< Timer0 chan3 output compare, plck1 pulse */
-	PIS_TIMER0_INPUT_4      = 0x128U,	/**< Timer0 chan4 input catch, plck1 pulse */
-	PIS_TIMER0_OUTPUT_4     = 0x129U,	/**< Timer0 chan4 output compare, plck1 pulse */
-	PIS_TIMER1_UPDATA       = 0x130U,	/**< Timer1 updata, plck1 pulse */
-	PIS_TIMER1_TRIG         = 0x131U,	/**< Timer1 trig, plck1 pulse */
-	PIS_TIMER1_INPUT_1      = 0x132U,	/**< Timer1 chan1 input catch, plck1 pulse */
-	PIS_TIMER1_OUTPUT_1     = 0x133U,	/**< Timer1 chan1 output compare, plck1 pulse */
-	PIS_TIMER1_INPUT_2      = 0x134U,	/**< Timer1 chan2 input catch, plck1 pulse */
-	PIS_TIMER1_OUTPUT_2     = 0x135U,	/**< Timer1 chan2 output compare, plck1 pulse */
-	PIS_TIMER1_INPUT_3      = 0x136U,	/**< Timer1 chan3 input catch, plck1 pulse */
-	PIS_TIMER1_OUTPUT_3     = 0x137U,	/**< Timer1 chan3 output compare, plck1 pulse */
-	PIS_TIMER1_INPUT_4      = 0x138U,	/**< Timer1 chan4 input catch, plck1 pulse */
-	PIS_TIMER1_OUTPUT_4     = 0x139U,	/**< Timer1 chan4 output compare, plck1 pulse */
-	PIS_TIMER2_UPDATA       = 0x140U,	/**< Timer2 updata, plck1 pulse */
-	PIS_TIMER2_TRIG         = 0x141U,	/**< Timer2 trig, plck1 pulse */
-	PIS_TIMER2_INPUT_1      = 0x142U,	/**< Timer2 chan1 input catch, plck1 pulse */
-	PIS_TIMER2_OUTPUT_1     = 0x143U,	/**< Timer2 chan1 output compare, plck1 pulse */
-	PIS_TIMER2_INPUT_2      = 0x144U,	/**< Timer2 chan2 input catch, plck1 pulse */
-	PIS_TIMER2_OUTPUT_2     = 0x145U,	/**< Timer2 chan2 output compare, plck1 pulse */
-	PIS_TIMER2_INPUT_3      = 0x146U,	/**< Timer2 chan3 input catch, plck1 pulse */
-	PIS_TIMER2_OUTPUT_3     = 0x147U,	/**< Timer2 chan3 output compare, plck1 pulse */
-	PIS_TIMER2_INPUT_4      = 0x148U,	/**< Timer2 chan4 input catch, plck1 pulse */
-	PIS_TIMER2_OUTPUT_4     = 0x149U,	/**< Timer2 chan4 output compare, plck1 pulse */
-	PIS_TIMER3_UPDATA       = 0x150U,	/**< Timer3 updata, plck1 pulse */
-	PIS_TIMER3_TRIG         = 0x151U,	/**< Timer3 trig, plck1 pulse */
-	PIS_TIMER3_INPUT_1      = 0x152U,	/**< Timer3 chan1 input catch, plck1 pulse */
-	PIS_TIMER3_OUTPUT_1     = 0x153U,	/**< Timer3 chan1 output compare, plck1 pulse */
-	PIS_TIMER3_INPUT_2      = 0x154U,	/**< Timer3 chan2 input catch, plck1 pulse */
-	PIS_TIMER3_OUTPUT_2     = 0x155U,	/**< Timer3 chan2 output compare, plck1 pulse */
-	PIS_TIMER3_INPUT_3      = 0x156U,	/**< Timer3 chan3 input catch, plck1 pulse */
-	PIS_TIMER3_OUTPUT_3     = 0x157U,	/**< Timer3 chan3 output compare, plck1 pulse */
-	PIS_TIMER3_INPUT_4      = 0x158U,	/**< Timer3 chan4 input catch, plck1 pulse */
-	PIS_TIMER3_OUTPUT_4     = 0x159U,	/**< Timer3 chan4 output compare, plck1 pulse */
-	PIS_RTC_CLOCK           = 0x160U,	/**< Rtc clock, pulse,support async */
-	PIS_RTC_ALARM           = 0x161U,	/**< Rtc alarm, pulse,support async */
-	PIS_LPTIMER0_SYN_UPDATA = 0x170U,	/**< Lptimer0 syn updata, pulse,support async */
-	PIS_LPTIMER0_ASY_UPDATA = 0x171U,	/**< Lptimer0 asy updata, pulse,support async */
-	PIS_LPUART0_ASY_RECV    = 0x180U,	/**< Lpuart0 asy recv, pulse,support async */
-	PIS_LPUART0_ASY_SEND    = 0x181U,	/**< Lpuart0 asy send, pulse,support async */
-	PIS_LPUART0_SYN_RECV    = 0x182U,	/**< Lpuart0 syn recv, pulse,support async */
-	PIS_LPUART0_SYN_SEND    = 0x183U,	/**< Lpuart0 syn recv, pulse,support async */
-	PIS_DMA                 = 0x190U,	/**< Dma, pulse,support async */
-	PIS_ADC1_INSERT         = 0x1a0U,	/**< Adc1 insert, pclk2 pulse,support async */
-	PIS_ADC1_NORMAL         = 0x1a1U,	/**< Adc1 normal, pclk2 pulse,support async */
-	PIS_ADC1_RESERVE        = 0x1a2U,	/**< Adc1 reserve */
-} pis_src_t;
-
-/**
-  * @brief Consumer entry
-  */
-typedef enum {
-	PIS_CH12_TIMER0_ITR0  = 0x003CU,	/** Tim0 internal input chan0 */
-	PIS_CH13_TIMER0_ITR1  = 0x003DU,	/** Tim0 internal input chan1 */
-	PIS_CH14_TIMER0_ITR2  = 0x003EU,	/** Tim0 internal input chan2 */
-	PIS_CH15_TIMER0_ITR3  = 0x003FU,	/** Tim0 internal input chan3 */
-	PIS_CH12_TIMER1_ITR0  = 0x003CU,	/** Tim1 internal input chan0 */
-	PIS_CH13_TIMER1_ITR1  = 0x003DU,	/** Tim1 internal input chan1 */
-	PIS_CH14_TIMER1_ITR2  = 0x003EU,	/** Tim1 internal input chan2 */
-	PIS_CH15_TIMER1_ITR3  = 0x003FU,	/** Tim1 internal input chan3 */
-	PIS_CH12_TIMER2_ITR0  = 0x003CU,	/** Tim2 internal input chan0 */
-	PIS_CH13_TIMER2_ITR1  = 0x003DU,	/** Tim2 internal input chan1 */
-	PIS_CH14_TIMER2_ITR2  = 0x003EU,	/** Tim2 internal input chan2 */
-	PIS_CH15_TIMER2_ITR3  = 0x003FU,	/** Tim2 internal input chan3 */
-	PIS_CH12_TIMER3_ITR0  = 0x003CU,	/** Tim3 internal input chan0 */
-	PIS_CH13_TIMER3_ITR1  = 0x003DU,	/** Tim3 internal input chan1 */
-	PIS_CH14_TIMER3_ITR2  = 0x003EU,	/** Tim3 internal input chan2 */
-	PIS_CH15_TIMER3_ITR3  = 0x003FU,	/** Tim3 internal input chan3 */
-	PIS_CH6_ADC0_NORMAL   = 0x0036U,	/** ADC0 normal transform */
-	PIS_CH7_ADC0_INSERT   = 0x0037U,	/** ADC0 insert transform */
-	PIS_CH0_ADC1_NORMAL   = 0x0030U,	/** ADC1 normal transform */
-	PIS_CH1_ADC1_INSERT   = 0x0031U,	/** ADC1 insert transform */
-	PIS_CH0_LPTIM0_EXT0   = 0x0030U,	/** Lptim0 external trigger 0 */
-	PIS_CH1_LPTIM0_EXT1   = 0x0031U,	/** Lptim0 external trigger 1 */
-	PIS_CH2_LPTIM0_EXT2   = 0x0032U,	/** Lptim0 external trigger 2 */
-	PIS_CH3_LPTIM0_EXT3   = 0x0033U,	/** Lptim0 external trigger 3 */
-	PIS_CH4_LPTIM0_EXT4   = 0x0034U,	/** Lptim0 external trigger 4 */
-	PIS_CH5_LPTIM0_EXT5   = 0x0035U,	/** Lptim0 external trigger 5 */
-	PIS_CH6_LPTIM0_EXT6   = 0x0036U,	/** Lptim0 external trigger 6 */
-	PIS_CH7_LPTIM0_EXT7   = 0x0037U,	/** Lptim0 external trigger 7 */
-	PIS_CH7_DMA_REQUEST   = 0x0037U,	/** DMA request 7 */
-	PIS_CH15_LPUART0_RXD  = 0x081FU,	/**< Lpuart Rx data */
-	PIS_CH14_UART5_RXD    = 0x071EU,	/**< Uart5 Rx data */
-	PIS_CH13_UART4_RXD    = 0x061DU,	/**< Uart4 Rx data */
-	PIS_CH12_UART3_RXD    = 0x031CU,	/**< Uart3 Rx data */
-	PIS_CH11_UART2_RXD    = 0x021BU,	/**< Uart2 Rx data */
-	PIS_CH10_UART1_RXD    = 0x011AU,	/**< Uart1 Rx data */
-	PIS_CH9_UART0_RXD     = 0x0019U,	/**< Uart0 Rx data  */
-	PIS_CH8_TIMER3_CH4IN  = 0x1B08U,	/**< Tim3 input chan4 */
-	PIS_CH8_TIMER2_CH4IN  = 0x1308U,	/**< Tim2 input chan4 */
-	PIS_CH8_SPI1_CLK      = 0x0F18U,	/**< Spi1 clk */
-	PIS_CH7_TIMER3_CH3IN  = 0x1A07U,	/**< Tim3 input chan3 */
-	PIS_CH7_TIMER2_CH3IN  = 0x1207U,	/**< Tim2 input chan3 */
-	PIS_CH7_SPI1_RX       = 0x0E17U,	/**< Spi1 rx */
-	PIS_CH6_TIMER3_CH2IN  = 0x1906U,	/**< Tim3 input chan2 */
-	PIS_CH6_TIMER2_CH2IN  = 0x1106U,	/**< Tim2 input chan2 */
-	PIS_CH6_SPI0_CLK      = 0x0D16U,	/**< SPI0 CLK */
-	PIS_CH5_TIMER3_CH1IN  = 0x1805U,	/**< Tim3 input chan1 */
-	PIS_CH5_TIMER2_CH1IN  = 0x1005U,	/**< Tim2 input chan1 */
-	PIS_CH5_SPI0_RX       = 0x0C15U,	/**< SPI0 RX */
-	PIS_CH4_TIMER1_CH4IN  = 0x0B04U,	/**< Tim1 input chan4 */
-	PIS_CH4_TIMER0_CH4IN  = 0x0304U,	/**< Tim0 input chan4 */
-	PIS_CH3_TIMER1_CH3IN  = 0x0A03U,	/**< Tim1 input chan3 */
-	PIS_CH3_TIMER0_CH3IN  = 0x0203U,	/**< Tim0 input chan3 */
-	PIS_CH2_TIMER1_CH2IN  = 0x0902U,	/**< Tim1 input chan2 */
-	PIS_CH2_TIMER0_CH2IN  = 0x0102U,	/**< Tim0 input chan2 */
-	PIS_CH1_TIMER1_CH1IN  = 0x0801U,	/**< Tim1 input chan1 */
-	PIS_CH0_TIMER0_CH1IN  = 0x0000U,	/**< Tim0 input chan1 */
-	PIS_CH0_TIMER0_BRKIN  = 0x0400U,	/**< Tim0 break in */
-	PIS_CH0_TIMER1_BRKIN  = 0x0C00U,	/**< Tim1 break in */
-	PIS_TRIG_RESERVE      = 0xFFFFU,	/**< Other Consumer */
-} pis_trig_t;
-
-/**
-  * @brief Clock select
-  */
-typedef enum {
-	PIS_CLK_PCLK1    = 0U,	/**< APB1 peripherals clock */
-	PIS_CLK_PCLK2    = 1U,	/**< APB2 peripherals clock */
-	PIS_CLK_SYS      = 2U,	/**< AHB peripherals clock */
-	PIS_CLK_RESERVE  = 3U,	/**< reserve clock */
-} pis_clock_t;
-
-/**
-  * @brief Level select
-  */
-typedef enum {
-	PIS_EDGE_NONE    = 0U,	/**< None edge */
-	PIS_EDGE_UP      = 1U,	/**< Up edge */
-	PIS_EDGE_DOWN    = 2U,	/**< Down edge */
-	PIS_EDGE_UP_DOWN = 3U,	/**< Up and down edge */
-} pis_edge_t;
-
-/**
-  * @brief Output style
-  */
-typedef enum {
-	PIS_OUT_LEVEL = 0U,	/**< Level */
-	PIS_OUT_PULSE = 1U,	/**< Pulse */
-} pis_output_t;
-/**
-  * @brief Sync select
-  */
-typedef enum {
-	PIS_SYN_DIRECT		= 0U,	/**< Direct */
-	PIS_SYN_LEVEL_ASY_APB1	= 1U,	/**< Producer level signal and Consumer in APB1 */
-	PIS_SYN_LEVEL_ASY_APB2	= 2U,	/**< Producer level signal and Consumer in APB2 */
-	PIS_SYN_LEVEL_ASY_AHB	= 3U,	/**< Producer level signal and Consumer in AHB */
-	PIS_SYN_PULSE_ASY_APB1	= 4U,	/**< Producer Pulse signal and Consumer in APB1 */
-	PIS_SYN_PULSE_ASY_APB2	= 5U,	/**< Producer Pulse signal and Consumer in APB2 */
-	PIS_SYN_PULSE_ASY_AHB	= 6U,	/**< Producer Pulse signal and Consumer in AHB */
-} pis_syncsel_t;
-
-/**
-  * @brief Pis channel
-  */
-typedef enum {
-	PIS_CH_0 = 0U,	/**< Channel 0 */
-	PIS_CH_1 = 1U,	/**< Channel 1 */
-	PIS_CH_2 = 2U,	/**< Channel 2 */
-	PIS_CH_3 = 3U,	/**< Channel 3 */
-	PIS_CH_4 = 4U,	/**< Channel 4 */
-	PIS_CH_5 = 5U,	/**< Channel 5 */
-	PIS_CH_6 = 6U,	/**< Channel 6 */
-	PIS_CH_7 = 7U,	/**< Channel 7 */
-	PIS_CH_8 = 8U,	/**< Channel 8 */
-	PIS_CH_9 = 9U,	/**< Channel 9 */
-	PIS_CH_10 = 10U,/**< Channel 10 */
-	PIS_CH_11 = 11U,/**< Channel 11 */
-	PIS_CH_12 = 12U,/**< Channel 12 */
-	PIS_CH_13 = 13U,/**< Channel 13 */
-	PIS_CH_14 = 14U,/**< Channel 14 */
-	PIS_CH_15 = 15U,/**< Channel 15 */
-} pis_ch_t;
-
-/**
-  * @brief Pis output channel
-  */
-typedef enum {
-	PIS_OUT_CH_0 = 0U,	/**< Channel 0 */
-	PIS_OUT_CH_1 = 1U,	/**< Channel 1 */
-	PIS_OUT_CH_2 = 2U,	/**< Channel 2 */
-	PIS_OUT_CH_3 = 3U,	/**< Channel 3 */
-} pis_out_ch_t;
-
-/**
-  * @brief Indirect value,no care of it.
-  */
-typedef enum {
-	PIS_CON_0    = 0U,	/**< Con 0 */
-	PIS_CON_1    = 1U,	/**< Con 1 */
-	PIS_CON_NONE = 2U,	/**< None */
-} pis_con_t;
-
-/**
-  * @brief PIS state structures definition
-  */
-typedef enum {
-	PIS_STATE_RESET   = 0x00U,	/**< Peripheral is not initialized */
-	PIS_STATE_READY   = 0x01U,	/**< Peripheral Initialized and ready for use */
-	PIS_STATE_BUSY    = 0x02U,	/**< An internal process is ongoing */
-	PIS_STATE_TIMEOUT = 0x03U,	/**< Timeout state */
-	PIS_STATE_ERROR   = 0x04U,	/**< Error */
-} pis_state_t;
-
-/**
-  * @brief PIS modulate target
-  */
-typedef enum {
-	PIS_UART0_TX   = 0U,	/**< Modulate uart0 tx */
-	PIS_UART1_TX   = 1U,	/**< Modulate uart1 tx */
-	PIS_UART2_TX   = 2U,	/**< Modulate uart2 tx */
-	PIS_UART3_TX   = 3U,	/**< Modulate uart3 tx */
-	PIS_LPUART0_TX = 4U,	/**< Modulate lpuart0 tx */
-} pis_modu_targ_t;
-
-/**
-  * @brief PIS modulate level
-  */
-typedef enum {
-	PIS_LOW_LEVEL  = 0U,	/**< Modulate low level */
-	PIS_HIGH_LEVEL = 1U,	/**< Modulate high level */
-} pis_modu_level_t;
-
-/**
-  * @brief PIS modulate source
-  */
-typedef enum {
-	PIS_SRC_NONE   = 0U,	/**< Stop modulate */
-	PIS_SRC_TIMER0 = 1U,	/**< Modulate source is TIMER0 */
-	PIS_SRC_TIMER1 = 2U,	/**< Modulate source is TIMER1 */
-	PIS_SRC_TIMER2 = 3U,	/**< Modulate source is TIMER2 */
-	PIS_SRC_TIMER3 = 4U,	/**< Modulate source is TIMER3 */
-	PIS_SRC_TIMER6 = 5U,	/**< Modulate source is TIMER6 */
-	PIS_SRC_TIMER7 = 6U,	/**< Modulate source is TIMER7 */
-	PIS_SRC_LPTIM0 = 7U,	/**< Modulate source is LPTIM0 */
-	PIS_SRC_BUZ    = 8U,	/**< Modulate source is buz */
-} pis_modu_src_t;
-
-/**
-  * @brief PIS modulate channel
-  */
-typedef enum {
-	PIS_TIMER_CH1 = 0U,	/**< Src is TIMERx and choose channel 1 */
-	PIS_TIMER_CH2 = 1U,	/**< Src is TIMERx and choose channel 2 */
-	PIS_TIMER_CH3 = 2U,	/**< Src is TIMERx and choose channel 3 */
-	PIS_TIMER_CH4 = 3U,	/**< Src is TIMERx and choose channel 4 */
-} pis_modu_channel_t;
-
-/**
-  * @brief PIS input channel chose
-  */
-typedef enum {
-	PIS_NONE_INPUT = 0U,	/**< Consumer input none */
-	PIS_PORT_INPUT = 1U,	/**< Consumer input choose external port */
-	PIS_CHAN_INPUT = 2U,	/**< Consumer input choose pis channel */
-} pis_input_sel_t;
-
-/**
-  * @brief PIS init structure definition
-  */
-typedef struct {
-	pis_src_t producer_src;			/**< Producer entry */
-	pis_output_t producer_signal;		/**< Producer signal mode */
-	pis_clock_t producer_clk;		/**< Producer module clock */
-	pis_edge_t producer_edge;		/**< Producer module pin output edge */
-	pis_trig_t consumer_trig;		/**< Consumer entry */
-	pis_clock_t consumer_clk;		/**< Consumer clock */
-	pis_input_sel_t input_chan;		/**< Consumer input channel */
-} pis_init_t;
-
-/**
-  * @brief PIS modulate config structure definition
-  */
-typedef struct {
-	pis_modu_targ_t target;		/**< Modulate target */
-	pis_modu_level_t level;		/**< Modulate level */
-	pis_modu_src_t src;		/**< Modulate src */
-	pis_modu_channel_t channel;	/**< Modulate channel */
-} pis_modulate_config_t;
-
-/**
-  * @brief  PIS Handle Structure definition
-  */
-typedef struct pis_handle_s {
-	PIS_TypeDef *perh;		/**< Register base address */
-	pis_init_t init;		/**< PIS required parameters */
-	pis_ch_t consumer_ch;		/**< Indirect value, no care of it */
-	pis_con_t consumer_con;		/**< Indirect value, no care of it */
-	uint8_t consumer_pos;	        /**< Indirect value, no care of it */
-	uint32_t check_info;		/**< When destroy a handle ,user need check whether is right that ready to destroy */
-	lock_state_t lock;		/**< Locking object */
-	pis_state_t state;		/**< PIS operation state */
-} pis_handle_t;
-/**
-  * @}
-  */
-
-
-/** @defgroup PIS_Private_Macros PIS Private Macros
-  * @{
-  */
-#define IS_PIS(x) 		(((x) == PIS))
-#define IS_PIS_SRC(x) 		(((x) == PIS_NON)		|| \
-				 ((x) == PIS_GPIO_PIN0)		|| \
-				 ((x) == PIS_GPIO_PIN1)		|| \
-				 ((x) == PIS_GPIO_PIN2)		|| \
-				 ((x) == PIS_GPIO_PIN3)		|| \
-				 ((x) == PIS_GPIO_PIN4)		|| \
-				 ((x) == PIS_GPIO_PIN5)		|| \
-				 ((x) == PIS_GPIO_PIN6)		|| \
-				 ((x) == PIS_GPIO_PIN7)		|| \
-				 ((x) == PIS_GPIO_PIN8)		|| \
-				 ((x) == PIS_GPIO_PIN9)		|| \
-				 ((x) == PIS_GPIO_PIN10)	|| \
-				 ((x) == PIS_GPIO_PIN11)	|| \
-				 ((x) == PIS_GPIO_PIN12)	|| \
-				 ((x) == PIS_GPIO_PIN13)	|| \
-				 ((x) == PIS_GPIO_PIN14)	|| \
-				 ((x) == PIS_GPIO_PIN15)	|| \
-				 ((x) == PIS_ACMP_OUT0)		|| \
-				 ((x) == PIS_ACMP_OUT1)		|| \
-				 ((x) == PIS_DAC0_CH0)		|| \
-				 ((x) == PIS_DAC0_CH1)		|| \
-				 ((x) == PIS_ADC0_INSERT)	|| \
-				 ((x) == PIS_ADC0_NORMAL)	|| \
-				 ((x) == PIS_ADC0_RESERVE)	|| \
-				 ((x) == PIS_LVD)		|| \
-				 ((x) == PIS_UART0_RESERVE0)	|| \
-				 ((x) == PIS_UART0_RESERVE1)	|| \
-				 ((x) == PIS_UART0_IRDAOUT)	|| \
-				 ((x) == PIS_UART0_RTSOUT)	|| \
-				 ((x) == PIS_UART0_TXOUT)	|| \
-				 ((x) == PIS_UART0_SYN_SEND)	|| \
-				 ((x) == PIS_UART0_SYN_RECV)	|| \
-				 ((x) == PIS_UART1_RESERVE0)	|| \
-				 ((x) == PIS_UART1_RESERVE1)	|| \
-				 ((x) == PIS_UART1_IRDA)	|| \
-				 ((x) == PIS_UART1_RTS)		|| \
-				 ((x) == PIS_UART1_TXOUT)	|| \
-				 ((x) == PIS_UART1_SYN_SEND)	|| \
-				 ((x) == PIS_UART1_SYN_RECV)	|| \
-				 ((x) == PIS_UART2_RESERVE0)	|| \
-				 ((x) == PIS_UART2_RESERVE1)	|| \
-				 ((x) == PIS_UART2_IRDA)	|| \
-				 ((x) == PIS_UART2_RTS)		|| \
-				 ((x) == PIS_UART2_TXOUT)	|| \
-				 ((x) == PIS_UART2_SYN_SEND)	|| \
-				 ((x) == PIS_UART2_SYN_RECV)	|| \
-				 ((x) == PIS_UART3_RESERVE0)	|| \
-				 ((x) == PIS_UART3_RESERVE1)	|| \
-				 ((x) == PIS_UART3_IRDA)	|| \
-				 ((x) == PIS_UART3_RTS)		|| \
-				 ((x) == PIS_UART3_TXOUT)	|| \
-				 ((x) == PIS_UART3_SYN_SEND)	|| \
-				 ((x) == PIS_UART3_SYN_RECV)	|| \
-				 ((x) == PIS_UART4_RECV)	|| \
-				 ((x) == PIS_UART4_SEND)	|| \
-				 ((x) == PIS_UART4_TXOUT)	|| \
-				 ((x) == PIS_UART5_RECV)	|| \
-				 ((x) == PIS_UART5_SEND)	|| \
-				 ((x) == PIS_UART5_TXOUT)	|| \
-				 ((x) == PIS_SPI0_RECV)		|| \
-				 ((x) == PIS_SPI0_SEND)		|| \
-				 ((x) == PIS_SPI0_NE)		|| \
-				 ((x) == PIS_SPI1_RECV)		|| \
-				 ((x) == PIS_SPI1_SEND)		|| \
-				 ((x) == PIS_SPI1_NE)		|| \
-				 ((x) == PIS_I2C0_RECV)		|| \
-				 ((x) == PIS_I2C0_SEND)		|| \
-				 ((x) == PIS_I2C1_RECV)		|| \
-				 ((x) == PIS_I2C1_SEND)		|| \
-				 ((x) == PIS_TIMER0_UPDATA)	|| \
-				 ((x) == PIS_TIMER0_TRIG)	|| \
-				 ((x) == PIS_TIMER0_INPUT_1)	|| \
-				 ((x) == PIS_TIMER0_OUTPUT_1)	|| \
-				 ((x) == PIS_TIMER0_INPUT_2)	|| \
-				 ((x) == PIS_TIMER0_OUTPUT_2)	|| \
-				 ((x) == PIS_TIMER0_INPUT_3)	|| \
-				 ((x) == PIS_TIMER0_OUTPUT_3)	|| \
-				 ((x) == PIS_TIMER0_INPUT_4)	|| \
-				 ((x) == PIS_TIMER0_OUTPUT_4)	|| \
-				 ((x) == PIS_TIMER1_UPDATA)	|| \
-				 ((x) == PIS_TIMER1_TRIG)	|| \
-				 ((x) == PIS_TIMER1_INPUT_1)	|| \
-				 ((x) == PIS_TIMER1_OUTPUT_1)	|| \
-				 ((x) == PIS_TIMER1_INPUT_2)	|| \
-				 ((x) == PIS_TIMER1_OUTPUT_2)	|| \
-				 ((x) == PIS_TIMER1_INPUT_3)	|| \
-				 ((x) == PIS_TIMER1_OUTPUT_3)	|| \
-				 ((x) == PIS_TIMER1_INPUT_4)	|| \
-				 ((x) == PIS_TIMER1_OUTPUT_4)	|| \
-				 ((x) == PIS_TIMER2_UPDATA)	|| \
-				 ((x) == PIS_TIMER2_TRIG)	|| \
-				 ((x) == PIS_TIMER2_INPUT_1)	|| \
-				 ((x) == PIS_TIMER2_OUTPUT_1)	|| \
-				 ((x) == PIS_TIMER2_INPUT_2)	|| \
-				 ((x) == PIS_TIMER2_OUTPUT_2)	|| \
-				 ((x) == PIS_TIMER2_INPUT_3)	|| \
-				 ((x) == PIS_TIMER2_OUTPUT_3)   || \
-				 ((x) == PIS_TIMER2_INPUT_4)    || \
-				 ((x) == PIS_TIMER2_OUTPUT_4)   || \
-				 ((x) == PIS_TIMER3_UPDATA)     || \
-				 ((x) == PIS_TIMER3_TRIG)       || \
-				 ((x) == PIS_TIMER3_INPUT_1)    || \
-				 ((x) == PIS_TIMER3_OUTPUT_1)   || \
-				 ((x) == PIS_TIMER3_INPUT_2)    || \
-				 ((x) == PIS_TIMER3_OUTPUT_2)   || \
-				 ((x) == PIS_TIMER3_INPUT_3)    || \
-				 ((x) == PIS_TIMER3_OUTPUT_3)   || \
-				 ((x) == PIS_TIMER3_INPUT_4)    || \
-				 ((x) == PIS_TIMER3_OUTPUT_4)   || \
-				 ((x) == PIS_RTC_CLOCK)         || \
-				 ((x) == PIS_RTC_ALARM)         || \
-				 ((x) == PIS_LPTIMER0_SYN_UPDATA) || \
-				 ((x) == PIS_LPTIMER0_ASY_UPDATA) || \
-				 ((x) == PIS_LPUART0_ASY_RECV)    || \
-				 ((x) == PIS_LPUART0_ASY_SEND)    || \
-				 ((x) == PIS_LPUART0_SYN_RECV)    || \
-				 ((x) == PIS_LPUART0_SYN_SEND)    || \
-				 ((x) == PIS_DMA)                 || \
-				 ((x) == PIS_ADC1_INSERT)         || \
-				 ((x) == PIS_ADC1_NORMAL)         || \
-				 ((x) == PIS_ADC1_RESERVE))
-#define IS_PIS_TRIG(x) 		(((x) == PIS_CH12_TIMER0_ITR0)  || \
-				 ((x) == PIS_CH13_TIMER0_ITR1)  || \
-				 ((x) == PIS_CH14_TIMER0_ITR2)  || \
-				 ((x) == PIS_CH15_TIMER0_ITR3)  || \
-				 ((x) == PIS_CH12_TIMER1_ITR0)  || \
-				 ((x) == PIS_CH13_TIMER1_ITR1)  || \
-				 ((x) == PIS_CH14_TIMER1_ITR2)  || \
-				 ((x) == PIS_CH15_TIMER1_ITR3)  || \
-				 ((x) == PIS_CH12_TIMER2_ITR0)  || \
-				 ((x) == PIS_CH13_TIMER2_ITR1)  || \
-				 ((x) == PIS_CH14_TIMER2_ITR2)  || \
-				 ((x) == PIS_CH15_TIMER2_ITR3)  || \
-				 ((x) == PIS_CH12_TIMER3_ITR0)  || \
-				 ((x) == PIS_CH13_TIMER3_ITR1)  || \
-				 ((x) == PIS_CH14_TIMER3_ITR2)  || \
-				 ((x) == PIS_CH15_TIMER3_ITR3)  || \
-				 ((x) == PIS_CH6_ADC0_NORMAL )  || \
-				 ((x) == PIS_CH7_ADC0_INSERT)   || \
-				 ((x) == PIS_CH0_ADC1_NORMAL)   || \
-				 ((x) == PIS_CH1_ADC1_INSERT)   || \
-				 ((x) == PIS_CH0_LPTIM0_EXT0) || \
-				 ((x) == PIS_CH1_LPTIM0_EXT1) || \
-				 ((x) == PIS_CH2_LPTIM0_EXT2) || \
-				 ((x) == PIS_CH3_LPTIM0_EXT3) || \
-				 ((x) == PIS_CH4_LPTIM0_EXT4) || \
-				 ((x) == PIS_CH5_LPTIM0_EXT5) || \
-				 ((x) == PIS_CH6_LPTIM0_EXT6) || \
-				 ((x) == PIS_CH7_LPTIM0_EXT7) || \
-				 ((x) == PIS_CH7_DMA_REQUEST)   || \
-				 ((x) == PIS_CH15_LPUART0_RXD)  || \
-				 ((x) == PIS_CH14_UART5_RXD)    || \
-				 ((x) == PIS_CH13_UART4_RXD)    || \
-				 ((x) == PIS_CH12_UART3_RXD)    || \
-				 ((x) == PIS_CH11_UART2_RXD)    || \
-				 ((x) == PIS_CH10_UART1_RXD)    || \
-				 ((x) == PIS_CH9_UART0_RXD)     || \
-				 ((x) == PIS_CH8_TIMER3_CH4IN)  || \
-				 ((x) == PIS_CH8_TIMER2_CH4IN)  || \
-				 ((x) == PIS_CH8_SPI1_CLK)      || \
-				 ((x) == PIS_CH7_TIMER3_CH3IN)  || \
-				 ((x) == PIS_CH7_TIMER2_CH3IN)  || \
-				 ((x) == PIS_CH7_SPI1_RX)       || \
-				 ((x) == PIS_CH6_TIMER3_CH2IN)  || \
-				 ((x) == PIS_CH6_TIMER2_CH2IN)  || \
-				 ((x) == PIS_CH6_SPI0_CLK)      || \
-				 ((x) == PIS_CH5_TIMER3_CH1IN)  || \
-				 ((x) == PIS_CH5_TIMER2_CH1IN)  || \
-				 ((x) == PIS_CH5_SPI0_RX)       || \
-				 ((x) == PIS_CH4_TIMER1_CH4IN)  || \
-				 ((x) == PIS_CH4_TIMER0_CH4IN)  || \
-				 ((x) == PIS_CH3_TIMER1_CH3IN)  || \
-				 ((x) == PIS_CH3_TIMER0_CH3IN)  || \
-				 ((x) == PIS_CH2_TIMER1_CH2IN)  || \
-				 ((x) == PIS_CH2_TIMER0_CH2IN)  || \
-				 ((x) == PIS_CH1_TIMER1_CH1IN)  || \
-				 ((x) == PIS_CH0_TIMER0_CH1IN)  || \
-				 ((x) == PIS_CH0_TIMER0_BRKIN)  || \
-				 ((x) == PIS_CH0_TIMER1_BRKIN)  || \
-				 ((x) == PIS_TRIG_RESERVE)      || \
-				 ((x) == PIS_CH8_SPI1_CLK))
-#define IS_PIS_CLOCK(x) 	(((x) == PIS_CLK_PCLK1)  || \
-				 ((x) == PIS_CLK_PCLK2)  || \
-				 ((x) == PIS_CLK_SYS))
-#define IS_PIS_SIGNAL_MODE(x) 	(((x) == PIS_OUT_LEVEL)  || \
-				 ((x) == PIS_OUT_PULSE))
-#define IS_PIS_EDGE(x) 		(((x) == PIS_EDGE_NONE) || \
-				 ((x) == PIS_EDGE_UP)   || \
-				 ((x) == PIS_EDGE_DOWN) || \
-				 ((x) == PIS_EDGE_UP_DOWN))
-#define IS_PIS_OUTPUT(x) 	(((x) == PIS_OUT_LEVEL) || \
-				 ((x) == PIS_OUT_PULSE))
-#define IS_PIS_OUPUT_CH(x)	(((x) == PIS_OUT_CH_0) || \
-				 ((x) == PIS_OUT_CH_1) || \
-				 ((x) == PIS_OUT_CH_2) || \
-				 ((x) == PIS_OUT_CH_3))
-#define IS_PIS_MODU_TARGET(x)	(((x) == PIS_UART0_TX) || \
-				 ((x) == PIS_UART1_TX) || \
-				 ((x) == PIS_UART2_TX) || \
-				 ((x) == PIS_UART3_TX) || \
-				 ((x) == PIS_LPUART0_TX))
-#define IS_PIS_MODU_LEVEL(x)	(((x) == PIS_LOW_LEVEL) || \
-				 ((x) == PIS_HIGH_LEVEL))
-#define IS_PIS_MODU_SRC(x)	(((x) == PIS_SRC_NONE)     || \
-				 ((x) == PIS_SRC_TIMER0)   || \
-				 ((x) == PIS_SRC_TIMER1)   || \
-				 ((x) == PIS_SRC_TIMER2)   || \
-				 ((x) == PIS_SRC_TIMER3)   || \
-				 ((x) == PIS_SRC_TIMER6)   || \
-				 ((x) == PIS_SRC_TIMER7)   || \
-				 ((x) == PIS_SRC_LPTIM0)   || \
-				 ((x) == PIS_SRC_BUZ))
-#define IS_PIS_MODU_CHANNEL(x)	(((x) == PIS_TIMER_CH1) || \
-				 ((x) == PIS_TIMER_CH2) || \
-				 ((x) == PIS_TIMER_CH3) || \
-				 ((x) == PIS_TIMER_CH4))
-/**
-  * @}
-  */
-
-/** @addtogroup PIS_Public_Functions
-  * @{
-  */
-
-/** @addtogroup PIS_Public_Functions_Group1
-  * @{
-  */
-ald_status_t ald_pis_create(pis_handle_t *hperh);
-ald_status_t ald_pis_destroy(pis_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup PIS_Public_Functions_Group2
-  * @{
-  */
-ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch);
-ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch);
-/**
-  * @}
-  */
-
-/** @addtogroup PIS_Public_Functions_Group3
-  * @{
-  */
-pis_state_t ald_pis_get_state(pis_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup PIS_Public_Functions_Group4
-  * @{
-  */
-ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_PIS_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_pmu.h

@@ -1,309 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_pmu.h
-  * @brief   Header file of PMU module driver.
-  *
-  * @version V1.0
-  * @date    04 Dec 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          04 Dec 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_PMU_H__
-#define __ALD_PMU_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_syscfg.h"
-#include "ald_bkpc.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup PMU
-  * @{
-  */
-
-/** @defgroup PMU_Public_Macros PMU Public Macros
-  * @{
-  */
-#define PMU_LPSTOP_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK);		\
-	SYSCFG_LOCK();					\
-} while (0)
-#define PMU_LPSTOP_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define PMU_FLASH_MODE_IDLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(PMU->CR0, PMU_CR0_SFPD_MSK);		\
-	SYSCFG_LOCK();					\
-} while (0)
-#define PMU_FLASH_MODE_WAIT()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(PMU->CR0, PMU_CR0_SFPD_MSK);		\
-	SYSCFG_LOCK();					\
-} while (0)
-#define PMU_MTSTOP_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);		\
-	SYSCFG_LOCK();					\
-} while (0)
-#define PMU_MTSTOP_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define PMU_VREF_ENABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	SET_BIT(PMU->VREFCR, PMU_VREFCR_VREFEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-#define PMU_VREF_DISABLE()				\
-do {							\
-	SYSCFG_UNLOCK();				\
-	CLEAR_BIT(PMU->VREFCR, PMU_VREFCR_VREFEN_MSK);	\
-	SYSCFG_LOCK();					\
-} while (0)
-
-#define PMU_GET_LVD_STATUS()	(READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS))
-/**
-  * @}
-  */
-
-
-/** @defgroup PMU_Public_Types PMU Public Types
-  * @{
-  */
-/**
-  * @brief Low power mode
-  */
-typedef enum {
-	PMU_LP_STOP1   = 0x0U,	/**< Stop1 */
-	PMU_LP_STOP2   = 0x1U,	/**< Stop2 */
-	PMU_LP_STANDBY = 0x2U,	/**< Standby */
-} pmu_lp_mode_t;
-
-/**
-  * @brief LDO_18 mode
-  */
-typedef enum {
-	PMU_LDO_18_DRV_HIGH = 0x0U, /**< High drive */
-	PMU_LDO_18_DRV_LOW  = 0x1U, /**< Low drive */
-	PMU_LDO_18_HOLD     = 0x2U, /**< Hold */
-	PMU_LDO_18_OFF      = 0x3U, /**< Turn off */
-} pmu_ldo_18_mode_t;
-
-typedef enum {
-	PMU_SR_WUF      = (1U << 0),	/**< WakeUp status */
-	PMU_SR_STANDBYF = (1U << 1),	/**< Standby status */
-	PMU_SR_USBRDY   = (1U << 2),	/**< USB Readby status */
-	PMU_SR_RSTAT    = (1U << 3),	/**< RUN/LPRUAN status */
-} pmu_status_t;
-
-/**
-  * @brief LVD voltage select
-  */
-typedef enum {
-	PMU_LVD_VOL_SEL_2_2 = 0x0U,	/**< 2.2V ~ 2.25V */
-	PMU_LVD_VOL_SEL_2_4 = 0x1U,	/**< 2.4V ~ 2.45V */
-	PMU_LVD_VOL_SEL_2_6 = 0x2U,	/**< 2.6V ~ 2.65V */
-	PMU_LVD_VOL_SEL_2_8 = 0x3U,	/**< 2.8V ~ 2.85V */
-	PMU_LVD_VOL_SEL_3_0 = 0x4U,	/**< 3.0V ~ 3.05V */
-	PMU_LVD_VOL_SEL_3_2 = 0x5U,	/**< 3.2V ~ 3.25V */
-	PMU_LVD_VOL_SEL_3_4 = 0x6U,	/**< 3.4V ~ 3.45V */
-	PMU_LVD_VOL_SEL_3_6 = 0x7U,	/**< 3.6V ~ 3.65V */
-	PMU_LVD_VOL_SEL_3_8 = 0x8U,	/**< 3.8V ~ 3.85V */
-	PMU_LVD_VOL_SEL_4_0 = 0x9U,	/**< 4.0V ~ 4.05V */
-	PMU_LVD_VOL_SEL_4_2 = 0xAU,	/**< 4.2V ~ 4.25V */
-	PMU_LVD_VOL_SEL_4_4 = 0xBU,	/**< 4.4V ~ 4.45V */
-	PMU_LVD_VOL_SEL_4_6 = 0xCU,	/**< 4.6V ~ 4.65V */
-	PMU_LVD_VOL_SEL_4_8 = 0xDU,	/**< 4.8V ~ 4.85V */
-	PMU_LVD_VOL_SEL_EXT = 0xFU,	/**< Select external input. It must be 1.2V */
-} pmu_lvd_voltage_sel_t;
-
-/**
-  * @brief LVD trigger mode
-  */
-typedef enum {
-	PMU_LVD_TRIGGER_RISING_EDGE    = 0x0U,	/**< Rising edge */
-	PMU_LVD_TRIGGER_FALLING_EDGE   = 0x1U,	/**< Falling edge */
-	PMU_LVD_TRIGGER_HIGH_LEVEL     = 0x2U,	/**< High level */
-	PMU_LVD_TRIGGER_LOW_LEVEL      = 0x3U,	/**< Low level */
-	PMU_LVD_TRIGGER_RISING_FALLING = 0x4U,	/**< Rising and falling edge */
-} pmu_lvd_trigger_mode_t;
-
-/**
-  * @brief LDO output voltage selest in low power mode
-  */
-typedef enum {
-	PMU_LDO_LPMODE_OUTPUT_0_9 = 0x0U,	/**< 0.9V */
-	PMU_LDO_LPMODE_OUTPUT_1_0 = 0x1U,	/**< 1.0V */
-	PMU_LDO_LPMODE_OUTPUT_1_1 = 0x2U,	/**< 1.1V */
-	PMU_LDO_LPMODE_OUTPUT_1_2 = 0x3U,	/**< 1.2V */
-} pmu_ldo_lpmode_output_t;
-
-typedef enum {
-	PMU_POWER_SRAM0 = 0x1U,		/**< SRAM0 */
-	PMU_POWER_SRAM1 = 0x2U,		/**< SRAM1 */
-	PMU_POWER_SRAM2 = 0x4U,		/**< SRAM2 */
-	PMU_POWER_SRAM3 = 0x8U,		/**< SRAM3 */
-	PMU_POWER_SRAM4 = 0x10U,	/**< SRAM4 */
-	PMU_POWER_SRAM5 = 0x20U,	/**< SRAM5 */
-	PMU_POWER_CAN   = 0x100U,	/**< CAN */
-	PMU_POWER_QSPI  = 0x400U,	/**< QSPI */
-	PMU_POWER_USB   = 0x800U,	/**< USB */
-	PMU_POWER_ROM   = 0x1000U,	/**< ROM */
-} pmu_perh_power_t;
-
-/**
-  * @}
-  */
-
-/**
-  * @defgroup PMU_Private_Macros PMU Private Macros
-  * @{
-  */
-#define IS_PMU_LP_MODE(x)		(((x) == PMU_LP_STOP1) || \
-                                         ((x) == PMU_LP_STOP2) || \
-                                         ((x) == PMU_LP_STANDBY))
-#define IS_PMU_LDO18_MODE(x)		(((x) == PMU_LDO_18_DRV_HIGH) || \
-                                         ((x) == PMU_LDO_18_DRV_LOW) || \
-                                         ((x) == PMU_LDO_18_HOLD) || \
-                                         ((x) == PMU_LDO_18_OFF))
-#define IS_PMU_STATUS(x)		(((x) == PMU_SR_WUF) || \
-                                         ((x) == PMU_SR_STANDBYF) || \
-                                         ((x) == PMU_SR_USBRDY) || \
-                                         ((x) == PMU_SR_RSTAT))
-#define IS_PMU_LVD_VOL_SEL(x)		(((x) == PMU_LVD_VOL_SEL_2_2) || \
-                                         ((x) == PMU_LVD_VOL_SEL_2_4) || \
-                                         ((x) == PMU_LVD_VOL_SEL_2_6) || \
-                                         ((x) == PMU_LVD_VOL_SEL_2_8) || \
-                                         ((x) == PMU_LVD_VOL_SEL_3_0) || \
-                                         ((x) == PMU_LVD_VOL_SEL_3_2) || \
-                                         ((x) == PMU_LVD_VOL_SEL_3_4) || \
-                                         ((x) == PMU_LVD_VOL_SEL_3_6) || \
-                                         ((x) == PMU_LVD_VOL_SEL_3_8) || \
-                                         ((x) == PMU_LVD_VOL_SEL_4_0) || \
-                                         ((x) == PMU_LVD_VOL_SEL_4_2) || \
-                                         ((x) == PMU_LVD_VOL_SEL_4_4) || \
-                                         ((x) == PMU_LVD_VOL_SEL_4_6) || \
-                                         ((x) == PMU_LVD_VOL_SEL_4_8) || \
-                                         ((x) == PMU_LVD_VOL_SEL_EXT))
-#define IS_PMU_LVD_TRIGGER_MODE(x)	(((x) == PMU_LVD_TRIGGER_RISING_EDGE)  || \
-                                         ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \
-                                         ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL)   || \
-                                         ((x) == PMU_LVD_TRIGGER_LOW_LEVEL)    || \
-                                         ((x) == PMU_LVD_TRIGGER_RISING_FALLING))
-#define IS_PMU_LDO_LPMODE_OUTPUT(x)	(((x) == PMU_LDO_LPMODE_OUTPUT_0_9) || \
-                                         ((x) == PMU_LDO_LPMODE_OUTPUT_1_0) || \
-                                         ((x) == PMU_LDO_LPMODE_OUTPUT_1_1) || \
-                                         ((x) == PMU_LDO_LPMODE_OUTPUT_1_2))
-#define IS_PMU_PERH_POWER(x)		(((x) == PMU_POWER_SRAM0) || \
-                                         ((x) == PMU_POWER_SRAM1) || \
-                                         ((x) == PMU_POWER_SRAM2) || \
-					 ((x) == PMU_POWER_SRAM3) || \
-					 ((x) == PMU_POWER_SRAM4) || \
-					 ((x) == PMU_POWER_SRAM5) || \
-					 ((x) == PMU_POWER_CAN)   || \
-					 ((x) == PMU_POWER_QSPI)  || \
-					 ((x) == PMU_POWER_USB)   || \
-                                         ((x) == PMU_POWER_ROM))
-
-/**
-  * @}
-  */
-
-/** @addtogroup PMU_Public_Functions
-  * @{
-  */
-/** @addtogroup PMU_Public_Functions_Group1
-  * @{
-  */
-/* Low power mode select */
-__STATIC_INLINE__ void ald_pmu_sleep()
-{
-	__WFI();
-}
-
-__STATIC_INLINE__ void ald_pmu_sleep_deep()
-{
-	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-	__WFI();
-}
-
-void ald_pmu_stop1_enter(void);
-void ald_pmu_stop2_enter(void);
-void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level);
-void ald_pmu_ldo_12_config(type_func_t state);
-void ald_pmu_ldo_18_config(pmu_ldo_18_mode_t mode);
-#ifdef ES32F336x  /* MCU Series: ES32F336x */
-void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state);
-#endif
-flag_status_t ald_pmu_get_status(pmu_status_t sr);
-void ald_pmu_clear_status(pmu_status_t sr);
-void ald_pmu_perh_power_config(pmu_perh_power_t perh, type_func_t state);
-/**
-  * @}
-  */
-/** @addtogroup PMU_Public_Functions_Group2
-  * @{
-  */
-/* LVD configure */
-void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state);
-void ald_lvd_irq_handler(void);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_PMU_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_qspi.h

@@ -1,557 +0,0 @@
-/***************************************************************************//**
- * @file    ald_qspi.h
- * @brief   Header file of QSPI module driver.
- * @version V1.0
- * @date    09 Nov 2019
- * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          09 Nov 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
- */
-
-#ifndef __ALD_QSPI_H_
-#define __ALD_QSPI_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup QSPI
-  * @{
-  */
-/** @defgroup QSPI_Public_Types QSPI Public Types
-  * @{
-  */
-/**
-  * @brief ALD QSPI state
-  */
-typedef enum {
-	QSPI_STATE_BUSY_TX = 0x11U,	/**< Data Transmission process is ongoing */
-	QSPI_STATE_BUSY_RX = 0x21U,	/**< Data Reception process is ongoing */
-} qspi_state_t;
-
-/**
-  * @brief QSPI Instruction Transfer Type
-  */
-typedef enum {
-	QSPI_XFER_SINGLE = 0x00U,	/**< Instruction shifted on DQ0 only*/
-	QSPI_XFER_DUAL   = 0x01U,	/**< Instruction,Address and data sent on DQ0 and DQ1*/
-	QSPI_XFER_QUAD   = 0x02U,	/**< Instruction,Address and data sent on DQ0,DQ1 and DQ2*/
-} qspi_xfer_t;
-
-/**
- * @brief QSPI Indirect Access SRAM fill level
- */	
-typedef enum {
-	QSPI_SRAM_RD = 0U,	/**< SRAM fill level(indirect write partition)in units of words(4bytes)*/
-	QSPI_SRAM_WR = 1U,	/**< SRAM fill level(indirect read partition)in units of words(4bytes)*/
-} qspi_sram_t;
-
-/** 
-  * @brief QSPI Clock Phase 
-  */
-typedef enum {
-	QSPI_CPHA_1E = 0U,	/**< First edge*/
-	QSPI_CPHA_2E = 1U,	/**< Second edge*/
-} qspi_cpha_t;
-
-/** 
-  * @brief QSPI_Clock_Polarity QSPI Clock Polarity
-  */
-typedef enum {
-	QSPI_CPOL_L = 0U,	/**< QSPI clock polarity low */
-	QSPI_CPOL_H = 1U,	/**< QSPI clock polarity high */
-} qspi_cpol_t;
-
-/** 
-  * @brief QSPI peripheral select decode
-  */
-typedef enum {
-	QSPI_SINGLE_CHIP = 0x0U,	/**< Only 1 of 4 selects n_ss_out[3:0] is active */
-	QSPI_MULTI_CHIP  = 0x1U,	/**< Allow external 4-to-16 decode */
-} qspi_nss_decode_t;
-
-/** 
-  * @brief QSPI_Baud_Rate_Clock_Prescaler QSPI Baud Rate Clock Prescaler
-  */
-typedef enum {
-	QSPI_DIV_2  = 0x0U,	/**< Master mode baud rate dibisor 2*/
-	QSPI_DIV_4  = 0x1U,	/**< Master mode baud rate dibisor 4*/
-	QSPI_DIV_6  = 0x2U,	/**< Master mode baud rate dibisor 6*/
-	QSPI_DIV_8  = 0x3U,	/**< Master mode baud rate dibisor 8*/
-	QSPI_DIV_10 = 0x4U,	/**< Master mode baud rate dibisor 10*/
-	QSPI_DIV_12 = 0x5U,	/**< Master mode baud rate dibisor 12*/
-	QSPI_DIV_14 = 0x6U,	/**< Master mode baud rate dibisor 14*/
-	QSPI_DIV_16 = 0x7U,	/**< Master mode baud rate dibisor 16*/
-	QSPI_DIV_18 = 0x8U,	/**< Master mode baud rate dibisor 18*/
-	QSPI_DIV_20 = 0x9U,	/**< Master mode baud rate dibisor 20*/
-	QSPI_DIV_22 = 0xAU,	/**< Master mode baud rate dibisor 22*/
-	QSPI_DIV_24 = 0xBU,	/**< Master mode baud rate dibisor 24*/
-	QSPI_DIV_26 = 0xCU,	/**< Master mode baud rate dibisor 26*/
-	QSPI_DIV_28 = 0xDU,	/**< Master mode baud rate dibisor 28*/
-	QSPI_DIV_30 = 0xEU,	/**< Master mode baud rate dibisor 30*/
-	QSPI_DIV_32 = 0xFU,	/**< Master mode baud rate dibisor 32*/
-} qspi_clk_div_t;
-
-/** 
-  * @brief QSPI Peripheral chip select decode
-  */
-typedef enum {
-	QSPI_CS_NSS0 = 0x0U,	/**< NSS0 active*/
-	QSPI_CS_NSS1 = 0x1U,	/**< NSS1 active*/ 
-	QSPI_CS_NSS2 = 0x3U,	/**< NSS2 active*/
-	QSPI_CS_NSS3 = 0x7U,	/**< NSS3 active*/
-} qspi_nss_t;
-
-/** 
-  *@brief Size of flash connected to CS[x](x = 0 ~ 3)pin
-  */
-typedef enum {
-	QSPI_NSS_512M = 0x0U,	/**< size of 512Mb*/
-        QSPI_NSS_1G   = 0x1U,	/**< size of 1Gb*/
-        QSPI_NSS_2G   = 0x2U,	/**< size of 2Gb*/
-        QSPI_NSS_4G   = 0x3U,	/**< size of 3Gb*/
-} qspi_nss_size_t;
-
-/** 
-  *@brief Qspi external flash device configuration
-  */
-typedef struct {
-	uint8_t addr;          /**< Peripheral address */
-	uint16_t page;         /**< Flash page size */
-	uint16_t blk;          /**< Flash block size */
-	qspi_nss_size_t cs0;   /**< NSS0 flash size */
-	qspi_nss_size_t cs1;   /**< NSS1 flash size */
-	qspi_nss_size_t cs2;   /**< NSS2 flash size */
-	qspi_nss_size_t cs3;   /**< NSS3 flash size */
-} qspi_device_size_t;
-
-/** 
-  * @brief QSPI Sample Edge Selection
-  */
-typedef enum {
-	QSPI_FALLING_E = 0x0U,	/**< Data outputs from flash are sampled on falling edge of the ref_clk*/
-	QSPI_RISING_E  = 0x1U,	/**< Data outputs from flash are sampled on rising edge of the ref_clk*/
-} qspi_data_sampled_t;
-
-/**
-  * @brief Flash write-protected blocks configuration.
-  */  
-typedef struct {
-	uint32_t lowblk;	/**< the lower block in the range of blocks that is to be locked from writing*/
-	uint32_t upblk;		/**< upper block in the range of blocks that is to be locked from writing*/
-} qspi_wr_protect_t;
-
-/**
-  * @brief  QSPI STIG Command Structure. 
-  */
-typedef struct {
-	uint32_t code;		/**< command op-code*/
-	uint32_t rd_len;	/**< Number of Read Data Bytes*/
-	uint32_t addr_len;	/**< Number of Address Bytes*/
-	uint32_t wr_len;	/**< Number of Write Data Bytes*/
-	uint32_t d_sycle;	/**< Number of dummy cycles*/
-	type_func_t mode_bit;	/**< Mode Bit Configuration register are sent following the address bytes*/
-	type_func_t op_addr;	/**< If opcde requires an address*/
-	uint32_t val;		/**< Mode bits,sent to device following the address*/
-	uint32_t addr;		/**< Flash opcde address*/
-	void *rd_buf;		/**< Buffer for read data*/
-	void *wr_buf;		/**< Buffer with data to write*/
-} qspi_stig_cmd_t;
-
-/**
-  * @brief QSPI base initialization structure. 
-  */
-typedef struct {
-	qspi_clk_div_t clkdiv;		/**< QSPI Baud Rate Clock Prescaler*/
-	type_func_t wrppin;		/**< QSPI Set Write Protect Pin*/
-	qspi_nss_decode_t nssdcode;	/**< QSPI Peripheral Select Decode*/
-	qspi_nss_t chipsel;		/**< QSPI Peripheral Select Line*/
-	qspi_cpol_t cpol;               /**< QSPI polarity */
-	qspi_cpha_t chpa;               /**< QSPI phase */
-} qspi_init_t;
-
-/**
-  * @brief QSPI legacy initialization structure.
-  */
-typedef struct {
-	uint8_t	tx_thrd; /**< Tx FIFO threshhold */
-	uint8_t	rx_thrd; /**< Rx FIFO threshhold */ 
-} qspi_legacy_cfg_t;
-
-/**
-  * @brief QSPI Device Read Instruction Configuration structure. 
-  */
-typedef struct {
-	uint8_t rdcde;		/**< Read opcode in non-xip mode*/		
-	uint8_t dcyles;		/**< Number of dummy read clock cycles*/
-	uint8_t mbitval;	/**< Mode bits,sent to device following the address bytes*/
-	type_func_t ddrbit;	/**< Opcode from bit 7 to 0 is compliant with DDR command*/
-	type_func_t modebit;	/**< Enable mode bit*/
-	qspi_xfer_t addxfer;	/**< Transfer type used for address*/
-	qspi_xfer_t datxfer;	/**< Transfer type used for data*/
-	qspi_xfer_t instxfer;	/**< Transfer type used for instruction*/
-} qspi_read_cfg_t;
-
-/**
-  * @brief QSPI Device Write Instruction Configuration structure. 
-  */
-typedef struct {
-	uint8_t wrcde;		/**< Write opcode*/
-	uint8_t dcyles;		/**< Number of dummy read clock cycles*/
-	qspi_xfer_t addxfer;	/**< Transfer type used for address*/
-	qspi_xfer_t datxfer;	/**< Transfer type used for data*/
-	qspi_xfer_t instxfer;	/**< Transfer type used for instruction*/	 
-	type_func_t autowel;	/**< Turn off automatic*/
-} qspi_write_cfg_t;
-
-/**
-  * @brief  QSPI Indirect Configuration structure.involatile parameters 
-  */
-typedef struct {
-	uint32_t saddr;		/**< Flash start address, commence write operation*/
-	uint32_t wrlen;		/**< Number of indirect write bytes*/
-} qspi_indac_wr_cfg_t;
-
-typedef struct {
-	uint32_t saddr;		/**< FLASH start address, commence read operation*/
-	uint32_t rdlen;		/**< Number of indirect read bytes*/ 
-} qspi_indac_rd_cfg_t;
-
-typedef struct {
-	uint32_t srampt;	/**< Defines the size of the indirect read partion in the SRAM*/
-	uint32_t trgaddr;	/**< Indirect trigger address which is used by AHB controller*/
-	uint32_t trgrng;	/**< The offset of indirect trigger address*/
-	uint32_t wrwmark;	/**< Maximum fill level of SRAM before a DMA, 0xFFFFFFFF disable the function*/
-	uint32_t rdwmark;	/**< Fill level passes watermark, an interrupt generated*/
-} qspi_indac_cfg_t;
-
-/**
-  * @brief QSPI DAC configuration.
-  */ 
-typedef struct {
-	type_func_t dtrprtcol;		/**< DTR protocol*/
-	type_func_t ahbdecoder;		/**< AHB decoder, direct access mode only*/
-	type_func_t xipimmed;		/**< QSPI Enter XIP Immediately*/
-	type_func_t xipnextrd;		/**< QSPI Enter XIP Next Read*/
-	type_func_t addrremap;		/**< Enable AHB address re-mapping*/ 
-	uint32_t remapaddr;		/**< Remap incoming AHB address to different address*/ 
-	type_func_t dmaperh;		/**< QSPI dma interface*/
-	qspi_read_cfg_t rdinit;		/**< QSPI read instruction configuration*/
-	qspi_write_cfg_t wrinit;	/**< QSPI write instruction configuration*/
-} qspi_dac_cfg_t;
-
-/** 
-  * @brief  QSPI Handle Structure definition  
-  */  
-typedef struct {
-	QSPI_TypeDef *perh;	/**< QSPI registers base address*/
-	qspi_init_t init;	/**< QSPI communication parameters*/
-	uint8_t *tx_buf;	/**< Pointer to QSPI transfer buffer */
-	uint16_t tx_size;       /**< QSPI transfer size */
-	uint16_t tx_cnt;        /**< QSPI transfer counter */
-	uint8_t *rx_buf;	/**< Pointer to QSPI receive buffer */
-	uint16_t rx_size;       /**< QSPI receive size */
-	uint16_t rx_cnt;        /**< QSPI receive counter */
-
-	dma_handle_t hdma;	/**< QSPI Rx/Tx DMA Handle parameters*/
-
-	qspi_state_t state;	/**< QSPI communication state */
-	__IO lock_state_t lock;	/**< Locking object*/
-} qspi_handle_t;
-
-/**
-  * @brief Defines command to be executed using STIG mechanism. 
-  */
-typedef struct {
-	uint32_t ccsot;		/**< range [0 ~ 255]*/
-	uint32_t cseot;		/**< range [0 ~ 255]*/
-	uint32_t csdads;	/**< range [0 ~ 255]*/
-	uint32_t csda;		/**< range [0 ~ 255]*/
-} qspi_dly_cfg_t;
-
-/**
-  * @brief QSPI Read Data Capture Configuration. 
-  */
-typedef struct {
-	uint32_t dlytd;			/**< Delay transmitted data [0 ~ 15]*/
-	uint32_t dlydcl;		/**< Delay the read data capturing logic [0 ~ 15]*/
-	qspi_data_sampled_t smpledge;	/**< Sample edge selection(of the flash data outputs) @ref qspi_data_sampled_t*/
-} qspi_data_capture_cfg_t;
-
-/**
-  * @brief QSPI Indirect Write Progress Status. 
-  */
-typedef enum {
-	QSPI_INDWR_PROGRESS = (1U << 2),	/**< Indirect write operation in progress*/
-	QSPI_INDWR_CPLT     = (1U << 5),	/**< Indirect write completion*/
-} qspi_indwr_status_t;
-
-/**
-  * @brief QSPI Indirect Read Progress Status. 
-  */
-typedef enum {
-	QSPI_INDRD_PROGRESS = (1U << 2),	/**< Indirect read operation in progress*/
-	QSPI_RD_CPLT        = (1U << 5),	/**< Indirect read completion*/
-} qspi_indrd_flag_t;
-
-/**
-  * @brief QSPI Auto Poll Configuration Struction. 
-  */
-typedef struct {
-	uint32_t opcode;	/**< Automatically poll operation code */
-	uint32_t indx;		/**< Polling bit index */
-	uint32_t polarity;	/**< Defines polling polarity */
-	uint32_t validcnt;	/**< Expect true result times */
-	uint32_t repdly;	/**< Defines additional delay for maintain de-assert during auto-polling phase */
-	uint32_t polexpcnt;	/**< Poll cycles,which polling expiration interrupt is generated*/
-} qspi_auto_poll_t;
-
-/**
-  *@brief QSPI_Interrupt_definition QSPI Interrupt Definition
-  */
-typedef enum {
-	QSPI_IT_POLLF   = (1U << 13),	/**< Programmed polls cycles expired flag */		  		  
-	QSPI_IT_INDRSFF = (1U << 12),	/**< Indirect read partition of SRAM is full flag */
-	QSPI_IT_SRFFF   = (1U << 11),	/**< Small rx FIFO full flag */
-	QSPI_IT_SRFNEF  = (1U << 10),	/**< Small rx FIFO not empty flag */
-	QSPI_IT_STFFF   = (1U << 9),	/**< Small tx FIFO full flag */
-	QSPI_IT_STFNFF  = (1U << 8),	/**< Small tx FIFO not full flag */
-	QSPI_IT_ROVF    = (1U << 7),	/**< Receive overflow flag */
-	QSPI_IT_INDTWF  = (1U << 6),	/**< Indirect transfer watermark level breached flag */
-	QSPI_IT_AHBAEF  = (1U << 5),	/**< Illegal AHB access detected flag */
-	QSPI_IT_WPAF    = (1U << 4),	/**< Write to protected area was rejected flag */
-	QSPI_IT_INDRRF  = (1U << 3),	/**< Indirect operation could not be accepted flag */
-	QSPI_IT_INDCF   = (1U << 2),	/**< Controller has completed last triggered indirect operation flag */
-	QSPI_IT_UDFF    = (1U << 1),	/**< Underflow detected flag */
-	QSPI_IT_MODFF   = (1U << 0),	/**< Mode fail M flag */
-} qspi_it_t;
-/**
-  * @brief QSPI_Flag_definition QSPI Flag Definition
-  */
-typedef enum {
-	QSPI_IF_POLLF   = (1U << 13),	/**< Programmed polls cycles expired flag */		  
-	QSPI_IF_INDRSFF = (1U << 12),	/**< Indirect read partition of SRAM is full flag */
-	QSPI_IF_SRFFF   = (1U << 11),	/**< Small rx FIFO full flag */
-	QSPI_IF_SRFNEF  = (1U << 10),	/**< Small rx FIFO not empty flag */
-	QSPI_IF_STFFF   = (1U << 9),	/**< Small tx FIFO full flag */
-	QSPI_IF_STFNFF  = (1U << 8),	/**< Small tx FIFO not full flag */
-	QSPI_IF_ROVF    = (1U << 7),	/**< Receive overflow flag */
-	QSPI_IF_INDTWF  = (1U << 6),	/**< Indirect transfer watermark level breached flag */
-	QSPI_IF_AHBAEF  = (1U << 5),	/**< Illegal AHB access detected flag */
-	QSPI_IF_WPAF    = (1U << 4),	/**< Write to protected area was rejected flag */
-	QSPI_IF_INDRRF  = (1U << 3),	/**< Indirect operation could not be accepted flag */
-	QSPI_IF_INDCF   = (1U << 2),	/**< Controller has completed last triggered indirect operation flag */
-	QSPI_IF_UDFF    = (1U << 1),	/**< Underflow detected flag */
-	QSPI_IF_MODFF   = (1U << 0),	/**< Mode fail M flag */
-} qspi_flag_t;
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_Private_Macros   QSPI Private Macros
-  * @{
-  */
-#define IS_QSPI_SRAM_PARTITION(x)	((x) < 255)
-#define IS_QSPI_INDIRECT_TRIGGER_RANGE(x)	(((x) < 16))
-#define IS_QSPI_INDIRECT_READ_WATERMARK(x)      ((x) < 512)
-#define IS_QSPI_INDIRECT_SRAM_FILL_TYPE(x)	(((x) == QSPI_SRAM_RD) || ((x) == QSPI_SRAM_WR))
-#define IS_QSPI_INDIRECT_READ_STATUS(x)		(((x) == QSPI_INDRD_PROGRESS) || ((x) == QSPI_RD_CPLT))
-#define IS_QSPI_INDIRECT_WRITE_STATUS(x)	(((x) == QSPI_INDWR_PROGRESS) || ((x) == QSPI_INDWR_CPLT))
-#define IS_QSPI_DEVICE_DELAY_CCSOT(x)	((x) < 256)
-#define IS_QSPI_DEVICE_DELAY_CSEOT(x)	((x) < 256)
-#define IS_QSPI_DEVICE_DELAY_CSDADS(x)	((x) < 256)
-#define IS_QSPI_DEVICE_DELAY_CSDA(x)	((x) < 256)
-
-#define IS_QSPI_READ_DATA_CAPTURE_DELAY_READ(x)		((x) < 16)
-#define IS_QSPI_READ_DATA_SAMPLE_EDGE(x)	(((x) == QSPI_FALLING_E) || \
-						((x) == QSPI_RISING_E))
-#define IS_QSPI_READ_DATA_DELAY_TRANSMIT(x)	((x) < 16)
-#define IS_QSPI_ALL(x)	((x) == QSPI)
-#define IS_QSPI_DCYLES(x)		((x) <= 31)
-
-#define IS_QSPI_ADDR_SIZE(x)	((x) <= 15)
-#define IS_QSPI_PAGE_SIZE(x)	((x) <= 0xfff)
-#define IS_QSPI_BLOCK_SIZE(x)	((x) <= 0x1f)
-#define IS_QSPI_NSS_SIZE(x)	((x) <= 3)
-
-#define IS_QSPI_XFER_TYPE(x)	(((x) == QSPI_XFER_SINGLE)  || \
-				((x) == QSPI_XFER_DUAL) || \
-				((x) == QSPI_XFER_QUAD))
-#define IS_QSPI_DDR_BIT_ENABLE(x)	(((x) == QSPI_READ_DDR_BIT_DISABLE) || \
-					((x) == QSPI_READ_DDR_BIT_ENABLE))
-#define IS_QSPI_MODE_BIT_ENABLE(x)	(((x) == QSPI_READ_INST_MODE_BIT_DISABLE) || \
-					((x) == QSPI_READ_INST_MODE_BIT_ENABLE))
-#define IS_QSPI_RD_OPCODE(x)		(((x) < 0xFF))
-#define IS_QSPI_WR_OPCODE(x)		(((x) < 0xFF))
-#define IS_QSPI_CLOCK_PRESCALER(x)	(((x) == QSPI_DIV_2)  || \
-					((x) == QSPI_DIV_4)  || \
-					((x) == QSPI_DIV_6)  || \
-					((x) == QSPI_DIV_8)  || \
-					((x) == QSPI_DIV_10) || \
-					((x) == QSPI_DIV_12) || \
-					((x) == QSPI_DIV_14) || \
-					((x) == QSPI_DIV_16) || \
-					((x) == QSPI_DIV_18) || \
-					((x) == QSPI_DIV_20) || \
-					((x) == QSPI_DIV_22) || \
-					((x) == QSPI_DIV_24) || \
-					((x) == QSPI_DIV_26) || \
-					((x) == QSPI_DIV_28) || \
-					((x) == QSPI_DIV_30) || \
-					((x) == QSPI_DIV_32))
-#define IS_QSPI_CLOCK_PHASE(x)		(((x) == QSPI_CPHA_1E)  || \
-					((x) == QSPI_CPHA_2E))
-#define IS_QSPI_CLOCK_POLARITY(x)	(((x) == QSPI_CPOL_L)  || \
-					((x) == QSPI_CPOL_H))
-#define IS_QSPI_IF(x)	(((x) == QSPI_IF_POLLF)		|| \
-			((x) == QSPI_IF_INDRSFF)	|| \
-			((x) == QSPI_IF_SRFFF)		|| \
-			((x) == QSPI_IF_SRFNEF)		|| \
-			((x) == QSPI_IF_STFFF)		|| \
-			((x) == QSPI_IF_STFNFF)		|| \
-			((x) == QSPI_IF_ROVF)		|| \
-			((x) == QSPI_IF_INDTWF)		|| \
-			((x) == QSPI_IF_AHBAEF)		|| \
-			((x) == QSPI_IF_WPAF)		|| \
-			((x) == QSPI_IF_INDRRF)		|| \
-			((x) == QSPI_IF_INDCF)		|| \
-			((x) == QSPI_IF_UDFF)		|| \
-			((x) == QSPI_IF_MODFF))
-#define IS_QSPI_IT(x)	(((x) == QSPI_IT_POLLF)		|| \
-			((x) == QSPI_IT_INDRSFF)	|| \
-			((x) == QSPI_IT_SRFFF)		|| \
-			((x) == QSPI_IT_SRFNEF)		|| \
-			((x) == QSPI_IT_STFFF)		|| \
-			((x) == QSPI_IT_STFNFF)		|| \
-			((x) == QSPI_IT_ROVF)		|| \
-			((x) == QSPI_IT_INDTWF)		|| \
-			((x) == QSPI_IT_AHBAEF)		|| \
-			((x) == QSPI_IT_WPAF)		|| \
-			((x) == QSPI_IT_INDRRF)		|| \
-			((x) == QSPI_IT_INDCF)		|| \
-			((x) == QSPI_IT_UDFF)		|| \
-			((x) == QSPI_IT_MODFF))
-
-/**
-  * @}
-  */
-
-/**
-  * @defgroup QSPI_Public_Macros QSPI Public Macros
-  * @{
-  */
-#define QSPI_MEMORY_ADDRESS			0x90000000U
-#define QSPI_SRAM_SIZE				255U
-#define QSPI_TIMEOUT_DEFAULT_VALUE		5000U /* 5s */	
-#define QSPI_SRAM_DEPTH 			0xFFU
-#define QSPI_DAC_ENABLE(hperh)			SET_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK)
-#define QSPI_DAC_DISABLE(hperh)			CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK)
-#define QSPI_LEGACY_SPI_ENABLE(hperh)		SET_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK)
-#define QSPI_LEGACY_SPI_DISABLE(hperh)		CLEAR_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK)
-#define QSPI_WRITE_PROTECT_ENABLE(hperh)	SET_BIT((hperh)->perh->WPCR, QSPI_WPCR_WPEN_MSK);
-#define QSPI_WRITE_PROTECT_DISABLE(hperh)	CLEAR_BIT((hperh)->perh->WPCR, QSPI_WPCR_WPEN_MSK);
-#define QSPI_ENABLE(hperh)			SET_BIT((hperh)->perh->CR, QSPI_CR_EN_MSK)
-#define QSPI_DISABLE(hperh)			CLEAR_BIT((hperh)->perh->CR, QSPI_CR_EN_MSK)
-#define QSPI_AUTO_POLL_ENABLE(hperh)		CLEAR_BIT((hperh)->perh->WCR, QSPI_WCR_PDIS_MSK)
-#define QSPI_AUTO_POLL_DISABLE(hperh)		SET_BIT((hperh)->perh->WCR, QSPI_WCR_PDIS_MSK)
-#define QSPI_DMA_ENABLE(hperh)			SET_BIT((hperh)->perh->CR, QSPI_CR_DMAEN_MSK)
-#define QSPI_DMA_DISABLE(hperh)			CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DMAEN_MSK)
-#define QSPI_CANCEL_INDIRECT_READ(hperh)	SET_BIT((hperh)->perh->IRTR, QSPI_IRTR_RDDIS_MSK)
-/**
-  * @}
-  */
-
-/** @addtogroup QSPI_Public_Functions
-  * @{
-  */
-
-/** @addtogroup QSPI_Public_Functions_Group1 
-  * @{
-  */
-/* QSPI basic execution functions */
-void ald_qspi_init(qspi_handle_t *hperh);
-uint32_t ald_qspi_dac_rd(uint32_t addr);
-void ald_qspi_dac_wr(uint32_t addr, uint32_t dat);
-ald_status_t ald_qspi_read_config(qspi_handle_t* hperh, const qspi_read_cfg_t * rdcfg);
-ald_status_t ald_qspi_write_config(qspi_handle_t* hperh, const qspi_write_cfg_t * wrcfg);
-ald_status_t ald_qspi_device_delay_config(qspi_handle_t * hperh, qspi_dly_cfg_t *dlycfg);
-ald_status_t ald_qspi_read_data_capture_config(qspi_handle_t * hperh, qspi_data_capture_cfg_t *dtcptcfg);
-ald_status_t ald_qspi_device_size_config(qspi_handle_t *hperh, qspi_device_size_t * devcfg);
-ald_status_t qspi_dac_config(qspi_handle_t * hperh, qspi_dac_cfg_t * dcfg);
-/**
-  * @}
-  */
-/** @addtogroup QSPI_Public_Functions_Group2
-  * @{
-  */
-/* QSPI indirect and stig access execution functions */
-ald_status_t ald_qspi_indac_config(qspi_handle_t * hperh, qspi_indac_cfg_t *indcfg);
-ald_status_t ald_qspi_indac_transmit_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc,  uint32_t size);
-ald_status_t ald_qspi_indac_transmit_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc,  uint32_t size);
-ald_status_t ald_qspi_indac_read_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size);
-ald_status_t ald_qspi_indac_read_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size);
-ald_status_t ald_qspi_execute_stig_cmd(qspi_handle_t* hperh, const qspi_stig_cmd_t * scmd);
-#ifdef ALD_DMA
-ald_status_t ald_qspi_indac_transmit_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *psrc, uint16_t size);
-ald_status_t ald_qspi_indac_read_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *pdbuf, uint16_t size);
-#endif
-/**
-  * @}
-  */
-/** @addtogroup QSPI_Public_Functions_Group3
-  * @{
-  */
-/* QSPI status functions */
-flag_status_t qspi_get_flag_status(qspi_handle_t *hperh, qspi_flag_t flag);
-void ald_qspi_clear_it_flag(qspi_handle_t *hperh, qspi_flag_t flag);
-uint16_t qspi_read_sram_fill_level(qspi_handle_t * hperh, qspi_sram_t srt);
-void ald_qspi_write_proect_config(qspi_handle_t * hperh, qspi_wr_protect_t* wpcfg);
-void ald_qspi_write_proect_inverse(qspi_handle_t * hperh, type_func_t state);
-ald_status_t ald_qspi_auto_poll(qspi_handle_t *hperh, qspi_auto_poll_t* apcfg);
-void ald_qspi_irq_handler(qspi_handle_t *hperh);
-void ald_qspi_interrupt_config(qspi_handle_t *hperh, qspi_it_t it, type_func_t state);
-void ald_qspi_legacy_config(qspi_handle_t* hperh, const qspi_legacy_cfg_t *config);
-flag_status_t qspi_indwr_get_status(qspi_handle_t *hperh, qspi_indwr_status_t status);
-ald_status_t qspi_indwr_wait_flag(qspi_handle_t *hperh, qspi_indwr_status_t flag, flag_status_t status, uint32_t timeout);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-#endif	/* __ALD_QSPI_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_rmu.h

@@ -1,314 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_rmu.h
-  * @brief   Header file of RMU module driver.
-  *
-  * @version V1.0
-  * @date    04 Dec 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          04 Dec 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_RMU_H__
-#define __ALD_RMU_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup RMU
-  * @{
-  */
-
-/** @defgroup RMU_Public_Types RMU Public Types
-  * @{
-  */
-/**
-  * @brief RMU BOR fliter
-  */
-typedef enum {
-	RMU_BORFLT_1 = 0x1U,	/**< 1 cycle  */
-	RMU_BORFLT_2 = 0x2U,	/**< 2 cycles */
-	RMU_BORFLT_3 = 0x3U,	/**< 3 cycles */
-	RMU_BORFLT_4 = 0x4U,	/**< 4 cycles */
-	RMU_BORFLT_5 = 0x5U,	/**< 5 cycles */
-	RMU_BORFLT_6 = 0x6U,	/**< 6 cycles */
-	RMU_BORFLT_7 = 0x7U,	/**< 7 cycles */
-} rmu_bor_filter_t;
-
-/**
-  * @brief RMU BOR voltage
-  */
-typedef enum {
-	RMU_VOL_NONE = 0x0U,	/**< Disable */
-	RMU_VOL_2_0  = 0x1U,	/**< 2.0V */
-	RMU_VOL_2_2  = 0x2U,	/**< 2.2V */
-	RMU_VOL_2_4  = 0x3U,	/**< 2.4V */
-	RMU_VOL_2_6  = 0x4U,	/**< 2.6V */
-	RMU_VOL_2_8  = 0x5U,	/**< 2.8V */
-	RMU_VOL_3_0  = 0x6U,	/**< 3.0V */
-	RMU_VOL_3_2  = 0x7U,	/**< 3.2V */
-	RMU_VOL_3_4  = 0x8U,	/**< 3.4V */
-	RMU_VOL_3_6  = 0x9U,	/**< 3.6V */
-	RMU_VOL_3_8  = 0xAU,	/**< 3.8V */
-	RMU_VOL_4_0  = 0xBU,	/**< 4.0V */
-	RMU_VOL_4_2  = 0xCU,	/**< 4.2V */
-	RMU_VOL_4_4  = 0xDU,	/**< 4.4V */
-	RMU_VOL_4_6  = 0xEU,	/**< 4.6V */
-	RMU_VOL_4_8  = 0xFU,	/**< 4.8V */
-} rmu_bor_vol_t;
-
-/**
-  * @brief RMU reset status
-  */
-typedef enum {
-	RMU_RST_POR    = (1U << 0),	/**< POR */
-	RMU_RST_WAKEUP = (1U << 1),	/**< WAKEUP */
-	RMU_RST_BOR    = (1U << 2),	/**< BOR */
-	RMU_RST_NMRST  = (1U << 3),	/**< NMRST */
-	RMU_RST_IWDT   = (1U << 4),	/**< IWDT */
-	RMU_RST_WWDT   = (1U << 5),	/**< WWDT */
-	RMU_RST_LOCKUP = (1U << 6),	/**< LOCKUP */
-	RMU_RST_CHIP   = (1U << 7),	/**< CHIP */
-	RMU_RST_MCU    = (1U << 8),	/**< MCU */
-	RMU_RST_CPU    = (1U << 9),	/**< CPU */
-	RMU_RST_CFG    = (1U << 10),	/**< CFG */
-	RMU_RST_CFGERR = (1U << 16),	/**< CFG Error */
-	RMU_RST_ALL    = (0xFFFFFU),	/**< ALL */
-} rmu_state_t;
-
-/**
-  * @brief RMU periperal select bit
-  * @verbatim
-      In this module, for the convenience of code maintenance,
-      TIMERx is used to indicate the sequence of the timer peripheral.
-      Different product series TIMERx represent different meanings:
-      1. For ES32F36xx series:
-      TIMER0 ----> AD16C4T0
-      TIMER1 ----> AD16C4T1
-      TIMER2 ----> GP32C4T0
-      TIMER3 ----> GP32C4T1
-      TIMER4 ----> BS16T0
-      TIMER5 ----> BS16T1
-      TIMER6 ----> GP16C4T0
-      TIMER7 ----> GP16C4T1
-     
-      2. For ES32F393x/ES32F336x/ES32F392x series:
-      TIMER0 ----> GP16C4T0
-      TIMER1 ----> GP16C4T1
-      TIMER2 ----> GP32C4T0
-      TIMER3 ----> GP32C4T1
-      TIMER4 ----> BS16T0
-      TIMER5 ----> BS16T1
-      TIMER6 ----> GP16C4T2
-      TIMER7 ----> GP16C4T3
-    @endverbatim
-  */
-typedef enum {
-	RMU_PERH_GPIO    = (1U << 0),			/**< AHB1: GPIO */
-	RMU_PERH_CRC     = (1U << 1),			/**< AHB1: CRC */
-	RMU_PERH_CALC    = (1U << 2),			/**< AHB1: CALC */
-	RMU_PERH_CRYPT   = (1U << 3),			/**< AHB1: CRYPT */
-	RMU_PERH_TRNG    = (1U << 4),			/**< AHB1: TRNG */
-	RMU_PERH_PIS     = (1U << 5),			/**< AHB1: PIS */
-	RMU_PERH_USB     = (1U << 10),			/**< AHB1: USB */
-	RMU_PERH_ECC     = (1U << 11),			/**< AHB1: ECC */
-	RMU_PERH_CHIP    = (1U << 0)  | (1U << 27),	/**< AHB2: CHIP */
-	RMU_PERH_CPU     = (1U << 1)  | (1U << 27),	/**< AHB2: CPU */
-	RMU_PERH_EBI     = (1U << 8)  | (1U << 27),	/**< AHB2: EBI */
-	RMU_PERH_TIMER0  = (1U << 0)  | (1U << 28),	/**< APB1: TIMER0 */
-	RMU_PERH_TIMER1  = (1U << 1)  | (1U << 28),	/**< APB1: TIMER1 */
-	RMU_PERH_TIMER2  = (1U << 2)  | (1U << 28),	/**< APB1: TIMER2 */
-	RMU_PERH_TIMER3  = (1U << 3)  | (1U << 28),	/**< APB1: TIMER3 */
-	RMU_PERH_TIMER4  = (1U << 4)  | (1U << 28),	/**< APB1: TIMER4 */
-	RMU_PERH_TIMER5  = (1U << 5)  | (1U << 28),	/**< APB1: TIMER5 */
-	RMU_PERH_TIMER6  = (1U << 6)  | (1U << 28),	/**< APB1: TIMER6 */
-	RMU_PERH_TIMER7  = (1U << 7)  | (1U << 28),	/**< APB1: TIMER7 */
-	RMU_PERH_UART0   = (1U << 8)  | (1U << 28),	/**< APB1: UART0 */
-	RMU_PERH_UART1   = (1U << 9)  | (1U << 28),	/**< APB1: UART1 */
-	RMU_PERH_UART2   = (1U << 10) | (1U << 28),	/**< APB1: UART2 */
-	RMU_PERH_UART3   = (1U << 11) | (1U << 28),	/**< APB1: UART3 */
-	RMU_PERH_UART4   = (1U << 12) | (1U << 28),	/**< APB1: UART4 */
-	RMU_PERH_UART5   = (1U << 13) | (1U << 28),	/**< APB1: UART5 */
-	RMU_PERH_SPI0    = (1U << 16) | (1U << 28),	/**< APB1: SPI0 */
-	RMU_PERH_SPI1    = (1U << 17) | (1U << 28),	/**< APB1: SPI1 */
-	RMU_PERH_SPI2    = (1U << 18) | (1U << 28),	/**< APB1: SPI2 */
-	RMU_PERH_I2C0    = (1U << 20) | (1U << 28),	/**< APB1: I2C0 */
-	RMU_PERH_I2C1    = (1U << 21) | (1U << 28),	/**< APB1: I2C1 */
-	RMU_PERH_CAN0    = (1U << 24) | (1U << 28),	/**< APB1: CAN0 */
-	RMU_PERH_QSPI    = (1U << 25) | (1U << 28),     /**< APB1: QSPI */
-	RMU_PERH_LPTIM0  = (1U << 0)  | (1U << 29),	/**< APB2: LPTIM0 */
-	RMU_PERH_LPUART0 = (1U << 2)  | (1U << 29),	/**< APB2: LPUART */
-	RMU_PERH_ADC0    = (1U << 4)  | (1U << 29),	/**< APB2: ADC0 */
-	RMU_PERH_ADC1    = (1U << 5)  | (1U << 29),	/**< APB2: ADC1 */
-	RMU_PERH_ACMP0   = (1U << 6)  | (1U << 29),	/**< APB2: ACMP0 */
-	RMU_PERH_ACMP1   = (1U << 7)  | (1U << 29),	/**< APB2: ACMP1 */
-	RMU_PERH_OPAMP   = (1U << 8)  | (1U << 29),	/**< APB2: OPAMP */
-	RMU_PERH_DAC0    = (1U << 9)  | (1U << 29),	/**< APB2: DAC0 */
-	RMU_PERH_ACMP2   = (1U << 11) | (1U << 29),	/**< APB2: WWDT */
-	RMU_PERH_WWDT    = (1U << 12) | (1U << 29),	/**< APB2: WWDT */
-	RMU_PERH_LCD     = (1U << 13) | (1U << 29),	/**< APB2: LCD */
-	RMU_PERH_IWDT    = (1U << 14) | (1U << 29),	/**< APB2: IWDT */
-	RMU_PERH_RTC     = (1U << 15) | (1U << 29),	/**< APB2: RTC */
-	RMU_PERH_TSENSE  = (1U << 16) | (1U << 29),	/**< APB2: TSENSE */
-	RMU_PERH_BKPC    = (1U << 17) | (1U << 29),	/**< APB2: BKPC */
-	RMU_PERH_BKPRAM  = (1U << 18) | (1U << 29),	/**< APB2: BKPRAM */
-} rmu_peripheral_t;
-/**
-  * @}
-  */
-
-/**
-  * @defgroup RMU_Private_Macros RMU Private Macros
-  * @{
-  */
-#define IS_RMU_BORFLT(x)	(((x) == RMU_BORFLT_1) || \
-                                 ((x) == RMU_BORFLT_2) || \
-                                 ((x) == RMU_BORFLT_3) || \
-                                 ((x) == RMU_BORFLT_4) || \
-                                 ((x) == RMU_BORFLT_5) || \
-                                 ((x) == RMU_BORFLT_6) || \
-                                 ((x) == RMU_BORFLT_7))
-#define IS_RMU_BORVOL(x)	(((x) == RMU_VOL_NONE) || \
-                                 ((x) == RMU_VOL_2_0) || \
-                                 ((x) == RMU_VOL_2_2) || \
-                                 ((x) == RMU_VOL_2_4) || \
-                                 ((x) == RMU_VOL_2_6) || \
-                                 ((x) == RMU_VOL_2_8) || \
-                                 ((x) == RMU_VOL_3_0) || \
-                                 ((x) == RMU_VOL_3_2) || \
-                                 ((x) == RMU_VOL_3_4) || \
-                                 ((x) == RMU_VOL_3_6) || \
-                                 ((x) == RMU_VOL_3_8) || \
-                                 ((x) == RMU_VOL_4_0) || \
-                                 ((x) == RMU_VOL_4_2) || \
-                                 ((x) == RMU_VOL_4_4) || \
-                                 ((x) == RMU_VOL_4_6) || \
-                                 ((x) == RMU_VOL_4_8))
-#define IS_RMU_STATE(x)		(((x) == RMU_RST_POR)    || \
-                                 ((x) == RMU_RST_WAKEUP) || \
-                                 ((x) == RMU_RST_BOR)    || \
-                                 ((x) == RMU_RST_NMRST)  || \
-                                 ((x) == RMU_RST_IWDT)   || \
-                                 ((x) == RMU_RST_WWDT)   || \
-                                 ((x) == RMU_RST_LOCKUP) || \
-                                 ((x) == RMU_RST_CHIP)   || \
-                                 ((x) == RMU_RST_MCU)    || \
-                                 ((x) == RMU_RST_CPU)    || \
-                                 ((x) == RMU_RST_CFG)    || \
-                                 ((x) == RMU_RST_CFGERR)    || \
-                                 ((x) == RMU_RST_ALL))
-#define IS_RMU_STATE_CLEAR(x)	(((x) == RMU_RST_POR)    || \
-                                 ((x) == RMU_RST_WAKEUP) || \
-                                 ((x) == RMU_RST_BOR)    || \
-                                 ((x) == RMU_RST_NMRST)  || \
-                                 ((x) == RMU_RST_IWDT)   || \
-                                 ((x) == RMU_RST_WWDT)   || \
-                                 ((x) == RMU_RST_LOCKUP) || \
-                                 ((x) == RMU_RST_CHIP)   || \
-                                 ((x) == RMU_RST_MCU)    || \
-                                 ((x) == RMU_RST_CPU)    || \
-                                 ((x) == RMU_RST_CFG)    || \
-                                 ((x) == RMU_RST_ALL))
-#define IS_RMU_PERH(x)		(((x) == RMU_PERH_GPIO)    || \
-                                 ((x) == RMU_PERH_CRC)     || \
-                                 ((x) == RMU_PERH_CALC)    || \
-                                 ((x) == RMU_PERH_CRYPT)   || \
-                                 ((x) == RMU_PERH_TRNG)    || \
-                                 ((x) == RMU_PERH_PIS)     || \
-                                 ((x) == RMU_PERH_USB)     || \
-                                 ((x) == RMU_PERH_ECC)     || \
-                                 ((x) == RMU_PERH_CHIP)    || \
-                                 ((x) == RMU_PERH_CPU)     || \
-                                 ((x) == RMU_PERH_EBI)     || \
-                                 ((x) == RMU_PERH_TIMER0)  || \
-                                 ((x) == RMU_PERH_TIMER1)  || \
-                                 ((x) == RMU_PERH_TIMER2)  || \
-                                 ((x) == RMU_PERH_TIMER3)  || \
-                                 ((x) == RMU_PERH_TIMER4)  || \
-                                 ((x) == RMU_PERH_TIMER5)  || \
-                                 ((x) == RMU_PERH_TIMER6)  || \
-                                 ((x) == RMU_PERH_TIMER7)  || \
-                                 ((x) == RMU_PERH_UART0)   || \
-                                 ((x) == RMU_PERH_UART1)   || \
-                                 ((x) == RMU_PERH_UART2)   || \
-                                 ((x) == RMU_PERH_UART3)   || \
-                                 ((x) == RMU_PERH_UART4)   || \
-                                 ((x) == RMU_PERH_UART5)   || \
-                                 ((x) == RMU_PERH_SPI0)    || \
-                                 ((x) == RMU_PERH_SPI1)    || \
-                                 ((x) == RMU_PERH_SPI2)    || \
-                                 ((x) == RMU_PERH_I2C0)    || \
-                                 ((x) == RMU_PERH_I2C1)    || \
-                                 ((x) == RMU_PERH_CAN0)    || \
-                                 ((x) == RMU_PERH_QSPI)    || \
-                                 ((x) == RMU_PERH_LPTIM0)  || \
-                                 ((x) == RMU_PERH_LPUART0) || \
-                                 ((x) == RMU_PERH_ADC0)    || \
-                                 ((x) == RMU_PERH_ADC1)    || \
-                                 ((x) == RMU_PERH_ACMP0)   || \
-                                 ((x) == RMU_PERH_ACMP1)   || \
-                                 ((x) == RMU_PERH_OPAMP)   || \
-                                 ((x) == RMU_PERH_DAC0)    || \
-                                 ((x) == RMU_PERH_ACMP2)    || \
-                                 ((x) == RMU_PERH_WWDT)    || \
-                                 ((x) == RMU_PERH_LCD)     || \
-                                 ((x) == RMU_PERH_IWDT)    || \
-                                 ((x) == RMU_PERH_RTC)     || \
-                                 ((x) == RMU_PERH_TSENSE)  || \
-                                 ((x) == RMU_PERH_BKPC)    || \
-                                 ((x) == RMU_PERH_BKPRAM))
-/**
-  * @}
-  */
-
-/** @addtogroup RMU_Public_Functions
-  * @{
-  */
-void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state);
-uint32_t ald_rmu_get_reset_status(rmu_state_t state);
-void ald_rmu_clear_reset_status(rmu_state_t state);
-void ald_rmu_reset_periperal(rmu_peripheral_t perh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_RMU_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_rtc.h

@@ -1,685 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ald_rtc.h
-  * @brief   Header file of RTC Module driver.
-  *
-  * @version V1.0
-  * @date    16 Nov 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          16 Nov 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_RTC_H__
-#define __ALD_RTC_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup RTC
-  * @{
-  */
-
-/** @defgroup RTC_Public_Types RTC Public Types
-  * @{
-  */
-
-/**
-  * @brief Hours format
-  */
-typedef enum {
-	RTC_HOUR_FORMAT_24 = 0x0U,	/**< 24-hours format */
-	RTC_HOUR_FORMAT_12 = 0x1U,	/**< 12-hours format */
-} rtc_hour_format_t;
-
-/**
-  * @brief Output mode
-  */
-typedef enum {
-	RTC_OUTPUT_DISABLE = 0x0U,	/**< Disable output */
-	RTC_OUTPUT_ALARM_A = 0x1U,	/**< Output alarm_a signal */
-	RTC_OUTPUT_ALARM_B = 0x2U,	/**< Output alarm_b signal */
-	RTC_OUTPUT_WAKEUP  = 0x3U,	/**< Output wakeup signal */
-} rtc_output_select_t;
-
-/**
-  * @brief Output polarity
-  */
-typedef enum {
-	RTC_OUTPUT_POLARITY_HIGH = 0x0U,	/**< Polarity is high */
-	RTC_OUTPUT_POLARITY_LOW  = 0x1U,	/**< Polarity is low */
-} rtc_output_polarity_t;
-
-/**
-  * @brief Initialization structure
-  */
-typedef struct {
-	rtc_hour_format_t hour_format;		/**< Hours format */
-	uint32_t asynch_pre_div;		/**< Asynchronous predivider value */
-	uint32_t synch_pre_div;			/**< Synchronous predivider value */
-	rtc_output_select_t output;		/**< Output signal type */
-	rtc_output_polarity_t output_polarity;	/**< Output polarity */
-} rtc_init_t;
-
-/**
-  * @brief Source select
-  */
-typedef enum {
-	RTC_SOURCE_LOSC        = 0x0U,	/**< LOSC */
-	RTC_SOURCE_LRC         = 0x1U,	/**< LRC */
-	RTC_SOURCE_HRC_DIV_1M  = 0x2U,	/**< HRC divide to 1MHz */
-	RTC_SOURCE_HOSC_DIV_1M = 0x3U,	/**< HOSC divide to 1MHz */
-} rtc_source_sel_t;
-
-/**
-  * @brief Time structure
-  */
-typedef struct {
-	uint8_t hour;		/**< Hours */
-	uint8_t minute;		/**< Minutes */
-	uint8_t second;		/**< Seconds */
-	uint16_t sub_sec;	/**< Sub-seconds */
-} rtc_time_t;
-
-/**
-  * @brief Date structure
-  */
-typedef struct {
-	uint8_t week;	/**< Weeks */
-	uint8_t day;	/**< days */
-	uint8_t month;	/**< months */
-	uint8_t year;	/**< years */
-} rtc_date_t;
-
-/**
-  * @brief Data format
-  */
-typedef enum {
-	RTC_FORMAT_DEC = 0U,	/**< Decimal */
-	RTC_FORMAT_BCD = 1U,	/**< BSD */
-} rtc_format_t;
-
-/**
-  * @brief Index of alarm
-  */
-typedef enum {
-	RTC_ALARM_A = 0x0U,	/**< Alarm-A */
-	RTC_ALARM_B = 0x1U,	/**< Alarm-B */
-} rtc_alarm_idx_t;
-
-/**
-  * @brief Alarm mask
-  */
-typedef enum {
-	RTC_ALARM_MASK_NONE     = 0x0U,		/**< Mask is disable */
-	RTC_ALARM_MASK_WEEK_DAY = (1U << 30),	/**< Mask week or day */
-	RTC_ALARM_MASK_HOUR     = (1U << 23),	/**< Mask hour */
-	RTC_ALARM_MASK_MINUTE   = (1U << 15),	/**< Mask minute */
-	RTC_ALARM_MASK_SECOND   = (1U << 7),	/**< Mask second */
-	RTC_ALARM_MASK_ALL      = 0x40808080U,	/**< Mask all */
-} rtc_alarm_mask_t;
-
-/**
-  * @brief Alarm sub-second mask
-  */
-typedef enum {
-	RTC_ALARM_SS_MASK_NONE  = 0xFU,	/**< Mask is disable */
-	RTC_ALARM_SS_MASK_14_1  = 0x1U,	/**< Mask bit(1-14) */
-	RTC_ALARM_SS_MASK_14_2  = 0x2U,	/**< Mask bit(2-14) */
-	RTC_ALARM_SS_MASK_14_3  = 0x3U,	/**< Mask bit(3-14) */
-	RTC_ALARM_SS_MASK_14_4  = 0x4U,	/**< Mask bit(4-14) */
-	RTC_ALARM_SS_MASK_14_5  = 0x5U,	/**< Mask bit(5-14) */
-	RTC_ALARM_SS_MASK_14_6  = 0x6U,	/**< Mask bit(6-14) */
-	RTC_ALARM_SS_MASK_14_7  = 0x7U,	/**< Mask bit(7-14) */
-	RTC_ALARM_SS_MASK_14_8  = 0x8U,	/**< Mask bit(8-14) */
-	RTC_ALARM_SS_MASK_14_9  = 0x9U,	/**< Mask bit(9-14) */
-	RTC_ALARM_SS_MASK_14_10 = 0xAU,	/**< Mask bit(10-14) */
-	RTC_ALARM_SS_MASK_14_11 = 0xBU,	/**< Mask bit(11-14) */
-	RTC_ALARM_SS_MASK_14_12 = 0xCU,	/**< Mask bit(12-14) */
-	RTC_ALARM_SS_MASK_14_13 = 0xDU,	/**< Mask bit(13-14) */
-	RTC_ALARM_SS_MASK_14    = 0xEU,	/**< Mask bit14 */
-	RTC_ALARM_SS_MASK_ALL   = 0x0U,	/**< Mask bit(0-14) */
-} rtc_sub_second_mask_t;
-
-/**
-  * @brief Alarm select week or day */
-typedef enum {
-	RTC_SELECT_DAY  = 0x0U,	/**< Alarm select day */
-	RTC_SELECT_WEEK = 0x1U,	/**< Alarm select week */
-} rtc_week_day_sel_t;
-
-/**
-  * @brief Alarm structure
-  */
-typedef struct {
-	rtc_alarm_idx_t idx;		/**< Index of alarm */
-	rtc_time_t time;		/**< Time structure */
-	uint32_t mask;			/**< Alarm mask */
-	rtc_sub_second_mask_t ss_mask;	/**< Alarm sub-second mask */
-	rtc_week_day_sel_t sel;		/**< Select week or day */
-
-	union {
-		uint8_t week;		/**< Alarm select week */
-		uint8_t day;		/**< Alarm select day */
-	};
-} rtc_alarm_t;
-
-/**
-  * @brief Time stamp signel select
-  */
-typedef enum {
-	RTC_TS_SIGNAL_SEL_TAMPER0 = 0U,	/**< Select tamper0 */
-	RTC_TS_SIGNAL_SEL_TAMPER1 = 1U,	/**< Select tamper1 */
-} rtc_ts_signal_sel_t;
-
-/**
-  * @brief Time stamp trigger style
-  */
-typedef enum {
-	RTC_TS_RISING_EDGE  = 0U,	/**< Rising edge */
-	RTC_TS_FALLING_EDGE = 1U,	/**< Falling edge */
-} rtc_ts_trigger_style_t;
-
-/**
-  * @brief Index of tamper
-  */
-typedef enum {
-	RTC_TAMPER_0 = 0U,	/**< Tamper0 */
-	RTC_TAMPER_1 = 1U,	/**< Tamper1 */
-} rtc_tamper_idx_t;
-
-/**
-  * @brief Tamper trigger type
-  */
-typedef enum {
-	RTC_TAMPER_TRIGGER_LOW  = 0U,	/**< High trigger */
-	RTC_TAMPER_TRIGGER_HIGH = 1U,	/**< Low trigger */
-} rtc_tamper_trigger_t;
-
-/**
-  * @brief Tamper sampling frequency
-  */
-typedef enum {
-	RTC_TAMPER_SAMPLING_FREQ_32768 = 0U,	/**< RTCCLK / 32768 */
-	RTC_TAMPER_SAMPLING_FREQ_16384 = 1U,	/**< RTCCLK / 16384 */
-	RTC_TAMPER_SAMPLING_FREQ_8192  = 2U,	/**< RTCCLK / 8192 */
-	RTC_TAMPER_SAMPLING_FREQ_4096  = 3U,	/**< RTCCLK / 4096 */
-	RTC_TAMPER_SAMPLING_FREQ_2048  = 4U,	/**< RTCCLK / 2048 */
-	RTC_TAMPER_SAMPLING_FREQ_1024  = 5U,	/**< RTCCLK / 1024 */
-	RTC_TAMPER_SAMPLING_FREQ_512   = 6U,	/**< RTCCLK / 512 */
-	RTC_TAMPER_SAMPLING_FREQ_256   = 7U,	/**< RTCCLK / 256 */
-} rtc_tamper_sampling_freq_t;
-
-/**
-  * @brief Tamper filter time
-  */
-typedef enum {
-	RTC_TAMPER_DURATION_1 = 0U,	/**< Duration 1 sampling */
-	RTC_TAMPER_DURATION_2 = 1U,	/**< Duration 2 sampling */
-	RTC_TAMPER_DURATION_4 = 2U,	/**< Duration 4 sampling */
-	RTC_TAMPER_DURATION_8 = 3U,	/**< Duration 8 sampling */
-} rtc_tamper_duration_t;
-
-/**
-  * @brief Tamper structure
-  */
-typedef struct {
-	rtc_tamper_idx_t idx;			/**< Index of tamper */
-	rtc_tamper_trigger_t trig;		/**< Trigger type */
-	rtc_tamper_sampling_freq_t freq;	/**< Sampling frequency */
-	rtc_tamper_duration_t dur;		/**< Filter time */
-	type_func_t ts;				/**< Enable/Disable trigger time stamp event */
-} rtc_tamper_t;
-
-/**
-  * @brief Wake-up clock
-  */
-typedef enum {
-	RTC_WAKEUP_CLOCK_DIV_16   = 0U,	/**< RTCCLK / 16 */
-	RTC_WAKEUP_CLOCK_DIV_8    = 1U,	/**< RTCCLK / 8 */
-	RTC_WAKEUP_CLOCK_DIV_4    = 2U,	/**< RTCCLK / 4 */
-	RTC_WAKEUP_CLOCK_DIV_2    = 3U,	/**< RTCCLK / 2 */
-	RTC_WAKEUP_CLOCK_1HZ      = 4U,	/**< 1Hz */
-	RTC_WAKEUP_CLOCK_1HZ_PULS = 6U,	/**< 1Hz and WUT + 65536 */
-} rtc_wakeup_clock_t;
-
-/**
-  * @brief RTC clock output type
-  */
-typedef enum {
-	RTC_CLOCK_OUTPUT_32768 = 0U,	/**< 32768Hz */
-	RTC_CLOCK_OUTPUT_1024  = 1U,	/**< 1024Hz */
-	RTC_CLOCK_OUTPUT_32    = 2U,	/**< 32Hz */
-	RTC_CLOCK_OUTPUT_1     = 3U,	/**< 1Hz */
-	RTC_CLOCK_OUTPUT_CAL_1 = 4U,	/**< 1Hz after calibration */
-	RTC_CLOCK_OUTPUT_EXA_1 = 5U,	/**< Exact 1Hz */
-} rtc_clock_output_t;
-
-/**
-  * @ Calibration frequency
-  */
-typedef enum {
-	RTC_CALI_FREQ_10_SEC = 0U,	/**< Calibrate every 10 seconds */
-	RTC_CALI_FREQ_20_SEC = 1U,	/**< Calibrate every 20 seconds */
-	RTC_CALI_FREQ_1_MIN  = 2U,	/**< Calibrate every 1 minute */
-	RTC_CALI_FREQ_2_MIN  = 3U,	/**< Calibrate every 2 minutes */
-	RTC_CALI_FREQ_5_MIN  = 4U,	/**< Calibrate every 5 minutes */
-	RTC_CALI_FREQ_10_MIN = 5U,	/**< Calibrate every 10 minutes */
-	RTC_CALI_FREQ_20_MIN = 6U,	/**< Calibrate every 20 minutes */
-	RTC_CALI_FREQ_1_SEC  = 7U,	/**< Calibrate every 1 second */
-} rtc_cali_freq_t;
-
-/**
-  * @brief Temperature compensate type
-  */
-typedef enum {
-	RTC_CALI_TC_NONE          = 0U,	/**< Temperature compensate disable */
-	RTC_CALI_TC_AUTO_BY_HW    = 1U,	/**< Temperature compensate by hardware */
-	RTC_CALI_TC_AUTO_BY_SF    = 2U,	/**< Temperature compensate by software */
-	RTC_CALI_TC_AUTO_BY_HW_SF = 3U,	/**< Temperature compensate by hardware, trigger by software */
-} rtc_cali_tc_t;
-
-/**
-  * @ Calculate frequency
-  */
-typedef enum {
-	RTC_CALI_CALC_FREQ_10_SEC = 0U,	/**< Calculate every 10 seconds */
-	RTC_CALI_CALC_FREQ_20_SEC = 1U,	/**< Calculate every 20 seconds */
-	RTC_CALI_CALC_FREQ_1_MIN  = 2U,	/**< Calculate every 1 minute */
-	RTC_CALI_CALC_FREQ_2_MIN  = 3U,	/**< Calculate every 2 minutes */
-	RTC_CALI_CALC_FREQ_5_MIN  = 4U,	/**< Calculate every 5 minutes */
-	RTC_CALI_CALC_FREQ_10_MIN = 5U,	/**< Calculate every 10 minutes */
-	RTC_CALI_CALC_FREQ_20_MIN = 6U,	/**< Calculate every 20 minutes */
-	RTC_CALI_CALC_FREQ_1_HOUR = 7U,	/**< Calculate every 1 hour */
-} rtc_cali_calc_freq_t;
-
-/**
-  * @brief Calibration algorithm
-  */
-typedef enum {
-	RTC_CALI_CALC_4 = 0U,	/**< 4-polynomial */
-	RTC_CALI_CALC_2 = 1U,	/**< 2-parabola */
-} rtc_cali_calc_t;
-
-/**
-  * @brief Calibration structure
-  */
-typedef struct {
-	rtc_cali_freq_t cali_freq;	/**< calibrate frequency */
-	rtc_cali_tc_t tc;		/**< Temperature compensate type */
-	rtc_cali_calc_freq_t calc_freq;	/**< Calculate frequency */
-	rtc_cali_calc_t calc;		/**< algorithm */
-	type_func_t acc;		/**< Enable/Disable decimal accumulate */
-} rtc_cali_t;
-
-/**
-  * @brief Interrupt type
-  */
-typedef enum {
-	RTC_IT_SEC  = (1U << 0),	/**< Second */
-	RTC_IT_MIN  = (1U << 1),	/**< Minute */
-	RTC_IT_HR   = (1U << 2),	/**< Hour */
-	RTC_IT_DAY  = (1U << 3),	/**< Day */
-	RTC_IT_MON  = (1U << 4),	/**< Month */
-	RTC_IT_YR   = (1U << 5),	/**< Year */
-	RTC_IT_ALMA = (1U << 8),	/**< Alarm-A */
-	RTC_IT_ALMB = (1U << 9),	/**< Alarm-B */
-	RTC_IT_TS   = (1U << 10),	/**< Time stamp */
-	RTC_IT_TSOV = (1U << 11),	/**< Time stamp overflow */
-	RTC_IT_TP0  = (1U << 12),	/**< Tamper-0 */
-	RTC_IT_TP1  = (1U << 13),	/**< Tamper-1 */
-	RTC_IT_RSC  = (1U << 16),	/**< Synchronous complete */
-	RTC_IT_SFC  = (1U << 17),	/**< Shift complete */
-	RTC_IT_WU   = (1U << 18),	/**< Wake-up */
-	RTC_IT_TCC  = (1U << 24),	/**< Temperature compensate complete */
-	RTC_IT_TCE  = (1U << 25),	/**< Temperature compensate error */
-} rtc_it_t;
-
-/**
-  * @brief Interrupt flag
-  */
-typedef enum {
-	RTC_IF_SEC  = (1U << 0),	/**< Second */
-	RTC_IF_MIN  = (1U << 1),	/**< Minute */
-	RTC_IF_HR   = (1U << 2),	/**< Hour */
-	RTC_IF_DAY  = (1U << 3),	/**< Day */
-	RTC_IF_MON  = (1U << 4),	/**< Month */
-	RTC_IF_YR   = (1U << 5),	/**< Year */
-	RTC_IF_ALMA = (1U << 8),	/**< Alarm-A */
-	RTC_IF_ALMB = (1U << 9),	/**< Alarm-B */
-	RTC_IF_TS   = (1U << 10),	/**< Time stamp */
-	RTC_IF_TSOV = (1U << 11),	/**< Time stamp overflow */
-	RTC_IF_TP0  = (1U << 12),	/**< Tamper-0 */
-	RTC_IF_TP1  = (1U << 13),	/**< Tamper-1 */
-	RTC_IF_RSC  = (1U << 16),	/**< Synchronous complete */
-	RTC_IF_SFC  = (1U << 17),	/**< Shift complete */
-	RTC_IF_WU   = (1U << 18),	/**< Wake-up */
-	RTC_IF_TCC  = (1U << 24),	/**< Temperature compensate complete */
-	RTC_IF_TCE  = (1U << 25),	/**< Temperature compensate error */
-} rtc_flag_t;
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Public_Macro RTC Public Macros
-  * @{
-  */
-#define RTC_UNLOCK()		(WRITE_REG(RTC->WPR, 0x55AAAA55U))
-#define RTC_LOCK()		(WRITE_REG(RTC->WPR, 0x0U))
-#define RTC_BY_PASS_ENABLE()			\
-do {						\
-	RTC_UNLOCK();				\
-	SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK);	\
-	RTC_LOCK();				\
-} while (0)
-#define RTC_BY_PASS_DISABLE()			\
-do {						\
-	RTC_UNLOCK();				\
-	CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK);	\
-	RTC_LOCK();				\
-} while (0)
-#define RTC_SUMMER_TIME_ENABLE()		\
-do {						\
-	RTC_UNLOCK();				\
-	SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK);	\
-	RTC_LOCK();				\
-} while (0)
-#define RTC_SUMMER_TIME_DISABLE()		\
-do {						\
-	RTC_UNLOCK();				\
-	CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK);	\
-	RTC_LOCK();				\
-} while (0)
-#define RTC_WINTER_TIME_ENABLE()		\
-do {						\
-	RTC_UNLOCK();				\
-	SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK);	\
-	RTC_LOCK();				\
-} while (0)
-#define RTC_WINTER_TIME_DISABLE()		\
-do {						\
-	RTC_UNLOCK();				\
-	CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK);	\
-	RTC_LOCK();				\
-} while (0)
-/**
- * @}
- */
-
-/** @defgroup CAN_Private_Macros CAN Private Macros
-  * @{
-  */
-#define RTC_CALI_UNLOCK()	(WRITE_REG(RTC->CALWPR, 0x699655AAU))
-#define RTC_CALI_LOCK()		(WRITE_REG(RTC->CALWPR, 0x0U))
-#define ALARM_MASK_ALL		0x40808080
-#define RTC_TIMEOUT_VALUE	100
-
-#define IS_SHIFT_SUB_SS(x)	((x) < (1U << 15))
-#define IS_RTC_HOUR_FORMAT(x)	(((x) == RTC_HOUR_FORMAT_24) || \
-                                 ((x) == RTC_HOUR_FORMAT_12))
-#define IS_RTC_OUTPUT_SEL(x)	(((x) == RTC_OUTPUT_DISABLE) || \
-                                 ((x) == RTC_OUTPUT_ALARM_A) || \
-                                 ((x) == RTC_OUTPUT_ALARM_B) || \
-                                 ((x) == RTC_OUTPUT_WAKEUP))
-#define IS_RTC_OUTPUT_POLARITY(x)	(((x) == RTC_OUTPUT_POLARITY_HIGH) || \
-                                         ((x) == RTC_OUTPUT_POLARITY_LOW))
-#define IS_RTC_SOURCE_SEL(x)	(((x) == RTC_SOURCE_LOSC)        || \
-                                 ((x) == RTC_SOURCE_LRC)         || \
-                                 ((x) == RTC_SOURCE_HRC_DIV_1M ) || \
-                                 ((x) == RTC_SOURCE_HOSC_DIV_1M))
-#define IS_RTC_ALARM(x)		(((x) == RTC_ALARM_A) || \
-                                 ((x) == RTC_ALARM_B))
-#define IS_RTC_ALARM_SEL(x)	(((x) == RTC_SELECT_DAY) || \
-                                 ((x) == RTC_SELECT_WEEK))
-#define IS_RTC_ALARM_MASK(x)	(((x) == RTC_ALARM_MASK_NONE)     || \
-                                 ((x) == RTC_ALARM_MASK_WEEK_DAY) || \
-                                 ((x) == RTC_ALARM_MASK_HOUR)     || \
-                                 ((x) == RTC_ALARM_MASK_MINUTE)   || \
-                                 ((x) == RTC_ALARM_MASK_SECOND)   || \
-                                 ((x) == RTC_ALARM_MASK_ALL))
-#define IS_RTC_ALARM_SS_MASK(x)	(((x) == RTC_ALARM_SS_MASK_NONE)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_1)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_2)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_3)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_4)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_5)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_6)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_7)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_8)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_9)  || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_10) || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_11) || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_12) || \
-                                 ((x) == RTC_ALARM_SS_MASK_14_13) || \
-                                 ((x) == RTC_ALARM_SS_MASK_14)    || \
-                                 ((x) == RTC_ALARM_SS_MASK_ALL))
-#define IS_RTC_TS_SIGNAL(x)	(((x) == RTC_TS_SIGNAL_SEL_TAMPER0) || \
-                                 ((x) == RTC_TS_SIGNAL_SEL_TAMPER1))
-#define IS_RTC_TS_STYLE(x)	(((x) == RTC_TS_RISING_EDGE) || \
-                                 ((x) == RTC_TS_FALLING_EDGE))
-#define IS_RTC_FORMAT(x)	(((x) == RTC_FORMAT_DEC) || \
-                                 ((x) == RTC_FORMAT_BCD))
-#define IS_RTC_TAMPER(x)	(((x) == RTC_TAMPER_0) || \
-                                 ((x) == RTC_TAMPER_1))
-#define IS_RTC_TAMPER_TRIGGER(x)	(((x) == RTC_TAMPER_TRIGGER_LOW) || \
-                                         ((x) == RTC_TAMPER_TRIGGER_HIGH))
-#define IS_RTC_TAMPER_SAMPLING_FREQ(x)	(((x) == RTC_TAMPER_SAMPLING_FREQ_32768) || \
-                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \
-                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_8192)  || \
-                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_4096)  || \
-                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_2048)  || \
-                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_1024)  || \
-                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_512)   || \
-                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_256))
-#define IS_RTC_TAMPER_DURATION(x)	(((x) == RTC_TAMPER_DURATION_1) || \
-                                         ((x) == RTC_TAMPER_DURATION_2) || \
-                                         ((x) == RTC_TAMPER_DURATION_4) || \
-                                         ((x) == RTC_TAMPER_DURATION_8))
-#define IS_RTC_WAKEUP_CLOCK(x)	(((x) == RTC_WAKEUP_CLOCK_DIV_16) || \
-                                 ((x) == RTC_WAKEUP_CLOCK_DIV_8)  || \
-                                 ((x) == RTC_WAKEUP_CLOCK_DIV_4)  || \
-                                 ((x) == RTC_WAKEUP_CLOCK_DIV_2)  || \
-                                 ((x) == RTC_WAKEUP_CLOCK_1HZ)    || \
-                                 ((x) == RTC_WAKEUP_CLOCK_1HZ_PULS))
-#define IS_RTC_CLOCK_OUTPUT(x)	(((x) == RTC_CLOCK_OUTPUT_32768) || \
-                                 ((x) == RTC_CLOCK_OUTPUT_1024)  || \
-                                 ((x) == RTC_CLOCK_OUTPUT_32)    || \
-                                 ((x) == RTC_CLOCK_OUTPUT_1)     || \
-                                 ((x) == RTC_CLOCK_OUTPUT_CAL_1) || \
-                                 ((x) == RTC_CLOCK_OUTPUT_EXA_1))
-#define IS_RTC_CALI_FREQ(x)	(((x) == RTC_CALI_FREQ_10_SEC) || \
-                                 ((x) == RTC_CALI_FREQ_20_SEC) || \
-                                 ((x) == RTC_CALI_FREQ_1_MIN)  || \
-                                 ((x) == RTC_CALI_FREQ_2_MIN)  || \
-                                 ((x) == RTC_CALI_FREQ_5_MIN)  || \
-                                 ((x) == RTC_CALI_FREQ_10_MIN) || \
-                                 ((x) == RTC_CALI_FREQ_20_MIN) || \
-                                 ((x) == RTC_CALI_FREQ_1_SEC))
-#define IS_RTC_CALI_TC(x)	(((x) == RTC_CALI_TC_NONE)       || \
-                                 ((x) == RTC_CALI_TC_AUTO_BY_HW) || \
-                                 ((x) == RTC_CALI_TC_AUTO_BY_SF) || \
-                                 ((x) == RTC_CALI_TC_AUTO_BY_HW_SF))
-#define IS_RTC_CALC_FREQ(x)	(((x) == RTC_CALI_CALC_FREQ_10_SEC) || \
-                                 ((x) == RTC_CALI_CALC_FREQ_20_SEC) || \
-                                 ((x) == RTC_CALI_CALC_FREQ_1_MIN)  || \
-                                 ((x) == RTC_CALI_CALC_FREQ_2_MIN)  || \
-                                 ((x) == RTC_CALI_CALC_FREQ_5_MIN)  || \
-                                 ((x) == RTC_CALI_CALC_FREQ_10_MIN) || \
-                                 ((x) == RTC_CALI_CALC_FREQ_20_MIN) || \
-                                 ((x) == RTC_CALI_CALC_FREQ_1_HOUR))
-#define IS_RTC_CALI_CALC(x)	(((x) == RTC_CALI_CALC_4) || \
-                                 ((x) == RTC_CALI_CALC_2))
-#define IS_RTC_IT(x)		(((x) == RTC_IT_SEC)  || \
-                                 ((x) == RTC_IT_MIN)  || \
-                                 ((x) == RTC_IT_HR)   || \
-                                 ((x) == RTC_IT_DAY)  || \
-                                 ((x) == RTC_IT_MON)  || \
-                                 ((x) == RTC_IT_YR)   || \
-                                 ((x) == RTC_IT_ALMA) || \
-                                 ((x) == RTC_IT_ALMB) || \
-                                 ((x) == RTC_IT_TS)   || \
-                                 ((x) == RTC_IT_TSOV) || \
-                                 ((x) == RTC_IT_TP0)  || \
-                                 ((x) == RTC_IT_TP1)  || \
-                                 ((x) == RTC_IT_RSC)  || \
-                                 ((x) == RTC_IT_SFC)  || \
-                                 ((x) == RTC_IT_WU)   || \
-                                 ((x) == RTC_IT_TCC)  || \
-                                 ((x) == RTC_IT_TCE))
-#define IS_RTC_IF(x)		(((x) == RTC_IF_SEC)  || \
-                                 ((x) == RTC_IF_MIN)  || \
-                                 ((x) == RTC_IF_HR)   || \
-                                 ((x) == RTC_IF_DAY)  || \
-                                 ((x) == RTC_IF_MON)  || \
-                                 ((x) == RTC_IF_YR)   || \
-                                 ((x) == RTC_IF_ALMA) || \
-                                 ((x) == RTC_IF_ALMB) || \
-                                 ((x) == RTC_IF_TS)   || \
-                                 ((x) == RTC_IF_TSOV) || \
-                                 ((x) == RTC_IF_TP0)  || \
-                                 ((x) == RTC_IF_TP1)  || \
-                                 ((x) == RTC_IF_RSC)  || \
-                                 ((x) == RTC_IF_SFC)  || \
-                                 ((x) == RTC_IF_WU)   || \
-                                 ((x) == RTC_IF_TCC)  || \
-                                 ((x) == RTC_IF_TCE))
-#define IS_RTC_SECOND(x)	((x) < 60)
-#define IS_RTC_MINUTE(x)	((x) < 60)
-#define IS_RTC_HOUR(x)		((x) < 24)
-#define IS_RTC_DAY(x)		(((x) > 0) && ((x) < 32))
-#define IS_RTC_MONTH(x)		(((x) > 0) && ((x) < 13))
-#define IS_RTC_YEAR(x)		((x) < 100)
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Public_Functions
-  * @{
-  */
-
-/** @addtogroup RTC_Public_Functions_Group1
-  *  @{
-  */
-/* Initialization functions */
-void ald_rtc_reset(void);
-void ald_rtc_init(rtc_init_t *init);
-void ald_rtc_source_select(rtc_source_sel_t sel);
-/**
-  * @}
-  */
-/** @addtogroup RTC_Public_Functions_Group2
-  * @{
-  */
-/* Time and date operation functions */
-ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format);
-ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format);
-void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format);
-void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format);
-int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format);
-/**
-  * @}
-  */
-/** @addtogroup RTC_Public_Functions_Group3
-  * @{
-  */
-/* Alarm functions */
-void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format);
-void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format);
-/**
-  * @}
-  */
-/** @addtogroup RTC_Public_Functions_Group4
-  * @{
-  */
-/* Time stamp functions */
-void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style);
-void ald_rtc_cancel_time_stamp(void);
-void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format);
-/**
-  * @}
-  */
-/** @addtogroup RTC_Public_Functions_Group5
-  * @{
-  */
-/* Tamper functions */
-void ald_rtc_set_tamper(rtc_tamper_t *tamper);
-void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx);
-/**
-  * @}
-  */
-/** @addtogroup RTC_Public_Functions_Group6
-  * @{
-  */
-/* Wakeup functions */
-void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value);
-void ald_rtc_cancel_wakeup(void);
-uint16_t ald_rtc_get_wakeup_timer_value(void);
-/**
-  * @}
-  */
-/** @addtogroup RTC_Public_Functions_Group7
-  * @{
-  */
-/* Clock output functions */
-ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock);
-void ald_rtc_cancel_clock_output(void);
-/**
-  * @}
-  */
-/** @addtogroup RTC_Public_Functions_Group8
-  * @{
-  */
-/* Control functions */
-void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state);
-void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state);
-ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss);
-void ald_rtc_set_cali(rtc_cali_t *config);
-void ald_rtc_cancel_cali(void);
-ald_status_t ald_rtc_get_cali_status(void);
-void ald_rtc_write_temp(uint16_t temp);
-it_status_t ald_rtc_get_it_status(rtc_it_t it);
-flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag);
-void ald_rtc_clear_flag_status(rtc_flag_t flag);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-#endif

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_rtchw.h

@@ -1,160 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ald_rtchw.h
-  * @brief   Header file of RTCHW Module driver.
-  *
-  * @version V1.0
-  * @date    16 Nov 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          16 Nov 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_RTCHW_H__
-#define __ALD_RTCHW_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup RTCHW
-  * @{
-  */
-
-/** @defgroup RTCHW_Public_Types RTCHW Public Types
-  * @{
-  */
-/**
-  * @brief Hardware calibration algorithm
-  */
-typedef enum {
-	RTC_CALI_MODE_NORMAL = 0U,	/**< Normal mode */
-	RTC_CALI_MODE_SLEEP  = 1U,	/**< Low power mode */
-} rtc_hw_cali_mode_t;
-
-/**
-  * @brief the parameters table of rtc calibration
-  */
-typedef  struct {
-	uint32_t  MODE_CALI;		/**< Calibration Mode */
-	uint32_t  RTC_CALCR;		/**< CALCR */
-	uint32_t  RTC_TEMPBDR;		/**< TEMPBDR */
-	uint32_t  TEMP_TBDR;		/**< TBDR */
-	uint32_t  RTC_LTAXR;		/**< LTAXR */
-	uint32_t  RTC_HTAXR;		/**< HTAXR */
-	uint32_t  RTC_LTCAR;		/**< LTCAR */
-	uint32_t  RTC_LTCBR;		/**< LTCBR */
-	uint32_t  RTC_LTCCR;		/**< LTCCR */
-	uint32_t  RTC_LTCDR;		/**< LTCDR */
-	uint32_t  RTC_HTCAR;		/**< HTCAR */
-	uint32_t  RTC_HTCBR;		/**< HTCBR */
-	uint32_t  RTC_HTCCR;		/**< HTCCR */
-	uint32_t  RTC_HTCDR;		/**< HTCDR */
-	uint32_t  TEMP_LTGR;		/**< LTGR */
-	uint32_t  TEMP_HTGR;		/**< HTGR */
-	uint32_t  TEMP_CR;		/**< CR */
-	uint32_t  rsv0;			/**< Reserved */
-	uint32_t  RTC_LTCER;		/**< LTCER */
-	uint32_t  RTC_HTCER;		/**< HTCER */
-	uint32_t  TEMP_PEAK;		/**< PEAK */
-	uint32_t  FREQ_PEAK;		/**< PEAK */
-	uint32_t  TEMP_CALI;		/**< CALI */
-	uint32_t  TEMP_CALI_AFTER;	/**< AFTER */
-	uint32_t  TEMP_TCALBDR;		/**< TCALBDR */
-	uint32_t  TEMP_TCALBDR_MINUS;	/**< TCALBDR_MINUS */
-	uint32_t  rsv1[4];		/**< Reserved */
-	uint32_t  SUM;			/**< SUM */
-	uint32_t  SUM_MINUS;		/**< SUM_MINUS */
-} RTCINFO_TypeDef;
-
-/**
-  * @brief Hardware calibration structure
-  */
-typedef struct {
-	int16_t  offset_rtc_bdr;	/**< offset:0x00 */
-	int16_t  offset_temp_bdr;	/**< offset:0x02 */
-	int16_t  offset_ltaxr;		/**< offset:0x04 */
-	int16_t  offset_htaxr;		/**< offset:0x06 */
-	int16_t  offset_ltcar;		/**< offset:0x08 */
-	int16_t  offset_ltcbr;		/**< offset:0x0A */
-	int16_t  offset_ltccr;		/**< offset:0x0C */
-	int16_t  offset_ltcdr;		/**< offset:0x0E */
-	int16_t  offset_htcar;		/**< offset:0x10 */
-	int16_t  offset_htcbr;		/**< offset:0x12 */
-	int16_t  offset_htccr;		/**< offset:0x14 */
-	int16_t  offset_htcdr;		/**< offset:0x16 */
-	int16_t  offset_ltgr;		/**< offset:0x18 */
-	int16_t  offset_htgr;		/**< offset:0x1A */
-	int16_t  offset_ltcer;		/**< offset:0x1C */
-	int16_t  offset_htcer;		/**< offset:0x1E */
-	int16_t  offset_temp_peak;	/**< offset:0x20 */
-	int16_t  offset_freq_peak;	/**< offset:0x22 */
-	int16_t  offset_tcalbdr;	/**< offset:0x24 */
-	int16_t  crc;			/**< offset:0x26 */
-	int16_t  rsv[8];
-} rtc_hw_cali_offset_t;
-/**
-  * @}
-  */
-/** @defgroup RTCHW_Private_Macros RTCHW Private Macros
-  * @{
-  */
-#ifndef RTC_LOCK
-#define RTC_LOCK()	(WRITE_REG(RTC->WPR, 0x0U))
-#define RTC_UNLOCK()	(WRITE_REG(RTC->WPR, 0x55AAAA55U))
-#endif
-
-#ifndef TSENSE_LOCK
-#define TSENSE_LOCK()	(WRITE_REG(TSENSE->WPR, 0x0U))
-#define TSENSE_UNLOCK()	(WRITE_REG(TSENSE->WPR, 0xA55A9669U))
-#endif
-
-#define RTCINFO	((RTCINFO_TypeDef *)0x81000U)
-/**
-  * @}
-  */
-
-/** @addtogroup RTCHW_Public_Functions
-  * @{
-  */
-/* Calibration functions */
-void ald_rtc_hw_auto_cali(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-#endif

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_spi.h

@@ -1,450 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_spi.c
-  * @brief   Header file of SPI module driver.
-  *
-  * @version V1.0
-  * @date    13 Nov 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          13 Nov 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_SPI_H__
-#define __ALD_SPI_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup SPI
-  * @{
-  */
-
-/** @defgroup SPI_Public_Types SPI Public Types
-  * @{
-  */
-
-/**
-  * @brief clock phase
-  */
-typedef enum {
-	SPI_CPHA_FIRST  = 0U,	/**< Transiting data in the first edge */
-	SPI_CPHA_SECOND = 1U,	/**< Transiting data in the seconde edge */
-} spi_cpha_t;
-
-/**
-  * @brief clock polarity
-  */
-typedef enum {
-	SPI_CPOL_LOW  = 0U,	/**< Polarity hold low when spi-bus is idle */
-	SPI_CPOL_HIGH = 1U,	/**< Polarity hold high when spi-bus is idle */
-} spi_cpol_t;
-
-/**
-  * @brief master selection
-  */
-typedef enum {
-	SPI_MODE_SLAVER = 0U,	/**< Slave mode */
-	SPI_MODE_MASTER = 1U,	/**< Master mode */
-} spi_mode_t;
-
-/**
-  * @brief baud rate control
-  */
-typedef enum {
-	SPI_BAUD_2   = 0U,	/**< fpclk/2 */
-	SPI_BAUD_4   = 1U,	/**< fpclk/4 */
-	SPI_BAUD_8   = 2U,	/**< fpclk/8 */
-	SPI_BAUD_16  = 3U,	/**< fpclk/16 */
-	SPI_BAUD_32  = 4U,	/**< fpclk/32 */
-	SPI_BAUD_64  = 5U,	/**< fpclk/64 */
-	SPI_BAUD_128 = 6U,	/**< fpclk/128 */
-	SPI_BAUD_256 = 7U,	/**< fpclk/256 */
-} spi_baud_t;
-
-/**
-  * @brief frame format
-  */
-typedef enum {
-	SPI_FIRSTBIT_MSB = 0U,	/**< MSB transmitted first */
-	SPI_FIRSTBIT_LSB = 1U,	/**< LSB transmitted first */
-} spi_firstbit_t;
-
-/**
-  * @brief data frame format
-  */
-typedef enum {
-	SPI_DATA_SIZE_8  = 0U,	/**< 8-bit data frame format is selected for transmission/reception */
-	SPI_DATA_SIZE_16 = 1U,	/**< 16-bit data frame format is selected for transmission/reception */
-} spi_datasize_t;
-
-/**
-  * @brief SPI error status
-  */
-typedef enum {
-	SPI_ERROR_NONE = 0U,	/**< none */
-	SPI_ERROR_MODF = 1U,	/**< mode fault */
-	SPI_ERROR_CRC  = 2U,	/**< crc error */
-	SPI_ERROR_FRE  = 4U,	/**< frame error */ 
-	SPI_ERROR_RXOV = 8U,	/**< receive over error */
-	SPI_ERROR_TXOV = 0x10U,	/**< dma error  */
-	SPI_ERROR_FLAG = 0x20U,	/**< interrupt flag error */
-} spi_error_t;
-
-/**
-  * @brief interrupt control
-  */
-typedef enum {
-	SPI_IT_TXE    = (1U << 0),	/**< Transmit fifo empty interrupt */
-	SPI_IT_TXOV   = (1U << 2),	/**< Transmit fifo overflow interrupt */
-	SPI_IT_TXUD   = (1U << 3),	/**< Transmit fifo underflow interrupt */
-	SPI_IT_TXTH   = (1U << 4),	/**< Transmit fifo under threshold interrupt */
-	SPI_IT_RXF    = (1U << 9),	/**< Receive fifo full interrupt */
-	SPI_IT_RXOV   = (1U << 10),	/**< Receive fifo overflow interrupt */
-	SPI_IT_RXUD   = (1U << 11),	/**< Receive fifo underflow interrupt */
-	SPI_IT_RXTH   = (1U << 12),	/**< Receive fifo over threshold interrupt */
-	SPI_IT_CRCERR = (1U << 16),	/**< Crc error interrupt */
-	SPI_IT_MODF   = (1U << 17),	/**< Mode error interrupt */
-	SPI_IT_FRE    = (1U << 18),	/**< Frame error interrupt */
-} spi_it_t;
-
-/**
-  * @brief interrupt flag
-  */
-typedef enum {
-	SPI_IF_TXE    = (1U << 0),	/**< Transmit fifo empty interrupt flag */
-	SPI_IF_TXOV   = (1U << 2),	/**< Transmit fifo overflow interrupt flag */
-	SPI_IF_TXUD   = (1U << 3),	/**< Transmit fifo underflow interrupt flag */
-	SPI_IF_TXTH   = (1U << 4),	/**< Transmit fifo under threshold interrupt flag */
-	SPI_IF_RXF    = (1U << 9),	/**< Receive fifo full interrupt flag */
-	SPI_IF_RXOV   = (1U << 10),	/**< Receive fifo overflow interrupt flag */
-	SPI_IF_RXUD   = (1U << 11),	/**< Receive fifo underflow interrupt flag */
-	SPI_IF_RXTH   = (1U << 12),	/**< Receive fifo over threshold interrupt flag */
-	SPI_IF_CRCERR = (1U << 16),	/**< Crc error interrupt flag */
-	SPI_IF_MODF   = (1U << 17),	/**< Mode error interrupt flag */
-	SPI_IF_FRE    = (1U << 18),	/**< Frame error interrupt flag */
-} spi_flag_t;
-
-/**
-  * @brief SPI state structures definition
-  */
-typedef enum {
-	SPI_STATE_RESET      = 0x00U,	/**< Peripheral is not initialized */
-	SPI_STATE_READY      = 0x01U,	/**< Peripheral Initialized and ready for use */
-	SPI_STATE_BUSY       = 0x02U,	/**< an internal process is ongoing */
-	SPI_STATE_BUSY_TX    = 0x11U,	/**< transmit is ongoing */
-	SPI_STATE_BUSY_RX    = 0x21U,	/**< receive is ongoing */
-	SPI_STATE_BUSY_TX_RX = 0x31U,	/**< transmit and receive are ongoing */
-	SPI_STATE_TIMEOUT    = 0x03U,	/**< Timeout state */
-	SPI_STATE_ERROR      = 0x04U,	/**< Error */
-} spi_state_t;
-
-
-/**
-  * @brief SPI direction definition
-  */
-typedef enum {
-	SPI_DIRECTION_2LINES        = 0U,	/**< 2 lines */
-	SPI_DIRECTION_2LINES_RXONLY = 1U,	/**< 2 lines only rx */
-	SPI_DIRECTION_1LINE         = 2U,	/**< 1 line */
-	SPI_DIRECTION_1LINE_RX      = 3U,	/**< 1 line only rx */
-} spi_direction_t;
-
-/**
-  * @brief SPI dma request definition
-  */
-typedef enum {
-	SPI_DMA_REQ_TX = 0U,	/**< TX dma request */
-	SPI_DMA_REQ_RX = 1U,	/**< RX dma request */
-} spi_dma_req_t;
-
-/**
-  * @brief SPI crc length definition
-  */
-typedef enum {
-	SPI_FRAME_MOTOROLA = 0U,	/**< SPI motorola mode */
-	SPI_FRAME_TI       = 1U,	/**< SPI TI mode */
-} spi_frame_t;
-
-/**
-  * @brief SPI status definition
-  */
-typedef enum {
-	SPI_STATUS_TXE  = (1U << 0),	/**< Transmit fifo empty status */
-	SPI_STATUS_TXF  = (1U << 1),	/**< Transmit fifo full status */
-	SPI_STATUS_TXOV = (1U << 2),	/**< Transmit fifo overflow status */
-	SPI_STATUS_TXUD = (1U << 3),    /**< Transmit fifo underflow status */
-	SPI_STATUS_TXTH = (1U << 4),    /**< Transmit fifo under threshold status */
-	SPI_STATUS_RXE  = (1U << 8),    /**< Receive fifo empty status */
-	SPI_STATUS_RXF  = (1U << 9),    /**< Receive fifo full status */
-	SPI_STATUS_RXOV = (1U << 10),   /**< Receive fifo overflow status */
-	SPI_STATUS_RXUD = (1U << 11),   /**< Receive fifo underflow status */
-	SPI_STATUS_RXTH = (1U << 12),   /**< Receive fifo under threshold status */
-	SPI_STATUS_BUSY = (1U << 15),   /**< BUSY status */
-} spi_status_t;
-
-/**
-  * @brief SPI TXE/RXNE status definition
-  */
-typedef enum {
-	SPI_SR_TXE      = 0U,	/**< SR.TXE set */
-	SPI_SR_RXNE     = 1U,	/**< SR.RXTH set */
-	SPI_SR_TXE_RXNE = 2U,	/**< SR.TXE and SR.RXNE set */
-} spi_sr_status_t;
-
-
-/**
-  * @brief SPI init structure definition
-  */
-typedef struct {
-	spi_mode_t mode;		/**< SPI mode */
-	spi_direction_t dir;		/**< SPI direction */
-	spi_datasize_t data_size;	/**< SPI data size */
-	spi_baud_t baud;		/**< SPI baudrate prescaler */
-	spi_cpha_t phase;		/**< SPI clock phase */
-	spi_cpol_t polarity;		/**< SPI clock polarity */
-	spi_firstbit_t first_bit;	/**< SPI first bit */
-	type_func_t ss_en;		/**< SPI ssm enable or disable */
-	type_func_t crc_calc;		/**< SPI crc calculation */
-	spi_frame_t frame;              /**< SPI frame format */
-	uint16_t crc_poly;		/**< SPI crc polynomial */
-} spi_init_t;
-
-/**
-  * @brief  SPI handle structure definition
-  */
-typedef struct spi_handle_s {
-	SPI_I2S_TypeDef *perh;	/**< SPI registers base address */
-	spi_init_t init;	/**< SPI communication parameters */
-	uint8_t *tx_buf;	/**< Pointer to SPI Tx transfer buffer */
-	uint16_t tx_size;	/**< SPI Tx transfer size */
-	uint16_t tx_count;	/**< SPI Tx transfer counter */
-	uint8_t *rx_buf;	/**< Pointer to SPI Rx transfer buffer */
-	uint16_t rx_size;	/**< SPI Rx Transfer size */
-	uint16_t rx_count;	/**< SPI Rx Transfer Counter */
-
-	dma_handle_t hdmatx;	/**< SPI Tx DMA handle parameters */
-	dma_handle_t hdmarx;	/**< SPI Rx DMA handle parameters */
-
-	lock_state_t lock;	/**< Locking object */
-	spi_state_t state;	/**< SPI communication state */
-	uint32_t err_code;	/**< SPI error code */
-
-	void (*tx_cplt_cbk)(struct spi_handle_s *arg);		/**< Tx completed callback */
-	void (*rx_cplt_cbk)(struct spi_handle_s *arg);		/**< Rx completed callback */
-	void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg);	/**< Tx & Rx completed callback */
-	void (*err_cbk)(struct spi_handle_s *arg);		/**< error callback */
-} spi_handle_t;
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Public_Macros SPI Public Macros
-  * @{
-  */
-#define SPI_RESET_HANDLE_STATE(x)	((x)->state = SPI_STATE_RESET)
-#define SPI_ENABLE(x)			((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS))
-#define SPI_DISABLE(x)			((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS))
-#define SPI_CRC_RESET(x)					\
-do {								\
-	CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK);		\
-	SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK);		\
-} while (0)
-#define SPI_CRCNEXT_ENABLE(x)	(SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
-#define SPI_CRCNEXT_DISABLE(x)	(CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
-#define SPI_RXONLY_ENABLE(x)	(SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
-#define SPI_RXONLY_DISABLE(x)	(CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
-#define SPI_1LINE_TX(x)		(SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
-#define SPI_1LINE_RX(x)		(CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
-#define SPI_SSI_HIGH(x)		(SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
-#define SPI_SSI_LOW(x)		(CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
-#define SPI_SSOE_ENABLE(x)	(SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
-#define SPI_SSOE_DISABLE(x)	(CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Private_Macros   SPI Private Macros
-  * @{
-  */
-#define IS_SPI(x)	(((x) == SPI0) || \
-                         ((x) == SPI1) || \
-                         ((x) == SPI2))
-#define IS_SPI_CPHA(x)	(((x) == SPI_CPHA_FIRST) || \
-                         ((x) == SPI_CPHA_SECOND))
-#define IS_SPI_CPOL(x)	(((x) == SPI_CPOL_LOW) || \
-                         ((x) == SPI_CPOL_HIGH))
-#define IS_SPI_MODE(x)	(((x) == SPI_MODE_SLAVER) || \
-                         ((x) == SPI_MODE_MASTER))
-#define IS_SPI_FIRBIT(x) (((x) == SPI_FIRSTBIT_MSB) || \
-                          ((x) == SPI_FIRSTBIT_LSB))
-#define IS_SPI_BAUD(x)	(((x) == SPI_BAUD_2)   || \
-                         ((x) == SPI_BAUD_4)   || \
-                         ((x) == SPI_BAUD_8)   || \
-                         ((x) == SPI_BAUD_16)  || \
-                         ((x) == SPI_BAUD_32)  || \
-                         ((x) == SPI_BAUD_64)  || \
-                         ((x) == SPI_BAUD_128) || \
-                         ((x) == SPI_BAUD_256))
-#define IS_SPI_DATASIZE(x)	(((x) == SPI_DATA_SIZE_8) || \
-                                 ((x) == SPI_DATA_SIZE_16))
-#define IS_SPI_BIDOE(x)		(((x) == SPI_BID_RX) || \
-                                 ((x) == SPI_BID_TX))
-#define IS_SPI_BIDMODE(x)	(((x) == SPI_BIDMODE_DUAL) || \
-                                 ((x) == SPI_BIDMODE_SOLE))
-#define IS_SPI_DIRECTION(x)	(((x) == SPI_DIRECTION_2LINES)         || \
-                                 ((x) == SPI_DIRECTION_2LINES_RXONLY)  || \
-                                 ((x) == SPI_DIRECTION_1LINE)          || \
-				 ((x) == SPI_DIRECTION_1LINE_RX))
-#define IS_SPI_DMA_REQ(x)	(((x) == SPI_DMA_REQ_TX) || \
-                                 ((x) == SPI_DMA_REQ_RX))
-#define IS_SPI_STATUS(x)	(((x) == SPI_STATUS_TXE)    || \
-				 ((x) == SPI_STATUS_TXF)    || \
-				 ((x) == SPI_STATUS_TXOV)   || \
-				 ((x) == SPI_STATUS_TXUD)   || \
-				 ((x) == SPI_STATUS_TXTH)   || \
-				 ((x) == SPI_STATUS_RXE)    || \
-				 ((x) == SPI_STATUS_RXF)    || \
-				 ((x) == SPI_STATUS_RXOV)   || \
-				 ((x) == SPI_STATUS_RXUD)   || \
-				 ((x) == SPI_STATUS_RXTH)   || \
-				 ((x) == SPI_STATUS_BUSY))
-#define IS_SPI_IT(x)		(((x) == SPI_IT_TXE)    || \
-				 ((x) == SPI_IT_TXOV)   || \
-				 ((x) == SPI_IT_TXUD)   || \
-				 ((x) == SPI_IT_TXTH)   || \
-				 ((x) == SPI_IT_RXF)    || \
-				 ((x) == SPI_IT_RXOV)   || \
-				 ((x) == SPI_IT_RXUD)   || \
-				 ((x) == SPI_IT_RXTH)   || \
-				 ((x) == SPI_IT_CRCERR) || \
-				 ((x) == SPI_IT_MODF)   || \
-				 ((x) == SPI_IT_FRE))
-#define IS_SPI_IF(x)		(((x) == SPI_IF_TXE)    || \
-				 ((x) == SPI_IF_TXOV)   || \
-				 ((x) == SPI_IF_TXUD)   || \
-				 ((x) == SPI_IF_TXTH)   || \
-				 ((x) == SPI_IF_RXF)    || \
-				 ((x) == SPI_IF_RXOV)   || \
-				 ((x) == SPI_IF_RXUD)   || \
-				 ((x) == SPI_IF_RXTH)   || \
-				 ((x) == SPI_IF_CRCERR) || \
-				 ((x) == SPI_IF_MODF)   || \
-				 ((x) == SPI_IF_FRE))
-#define IS_SPI_FRAME(x)		(((x) == SPI_FRAME_MOTOROLA) || \
-				 ((x) == SPI_FRAME_TI) )
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Public_Functions
-  * @{
-  */
-
-/** @addtogroup SPI_Public_Functions_Group1
-  * @{
-  */
-
-ald_status_t ald_spi_init(spi_handle_t *hperh);
-void ald_spi_reset(spi_handle_t *hperh);
-/**
-  * @}
-  */
-/** @addtogroup SPI_Public_Functions_Group2
-  * @{
-  */
-int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data);
-int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data);
-uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh, int *status);
-ald_status_t ald_spi_send_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout);
-ald_status_t ald_spi_master_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size);
-ald_status_t ald_spi_slave_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout);
-ald_status_t ald_spi_send_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout);
-ald_status_t ald_spi_master_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size);
-ald_status_t ald_spi_slave_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout);
-/**
-  * @}
-  */
-/** @addtogroup SPI_Public_Functions_Group3
-  * @{
-  */
-ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout);
-ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size);
-ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size);
-ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size);
-
-ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel);
-ald_status_t ald_spi_dma_pause(spi_handle_t *hperh);
-ald_status_t ald_spi_dma_resume(spi_handle_t *hperh);
-ald_status_t ald_spi_dma_stop(spi_handle_t *hperh);
-
-/**
-  * @}
-  */
-/** @addtogroup SPI_Public_Functions_Group4
-  * @{
-  */
-void ald_spi_irq_handler(spi_handle_t *hperh);
-void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state);
-void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed);
-void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state);
-it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it);
-flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status);
-flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag);
-void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag);
-/**
-  * @}
-  */
-/** @addtogroup SPI_Public_Functions_Group5
-  * @{
-  */
-spi_state_t ald_spi_get_state(spi_handle_t *hperh);
-uint32_t ald_spi_get_error(spi_handle_t *hperh);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-#endif

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_sram.h

@@ -1,142 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_sram.h
-  * @brief   Header file of EBI_SRAM driver
-  *
-  * @version V1.0
-  * @date    07 Dec 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          07 Dec 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_SRAM_H__
-#define __ALD_SRAM_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "ald_ebi.h"
-#include "ald_dma.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup SRAM
-  * @{
-  */
-
-/** @defgroup SRAM_Public_Types SRAM Public Types
-  * @{
-  */
-
-/** 
-  * @brief  ALD SRAM State structures definition  
-  */ 
-typedef enum {
-	ALD_SRAM_STATE_RESET     = 0x00U,	/**< SRAM not yet initialized or disabled */
-	ALD_SRAM_STATE_READY     = 0x01U,	/**< SRAM initialized and ready for use */
-	ALD_SRAM_STATE_BUSY      = 0x02U,	/**< SRAM internal process is ongoing */
-	ALD_SRAM_STATE_ERROR     = 0x03U,	/**< SRAM error state */
-	ALD_SRAM_STATE_PROTECTED = 0x04U	/**< SRAM peripheral NORSRAM device write protected */
-} ald_sram_state_t;
-
-/** 
-  * @brief  SRAM handle Structure definition  
-  */ 
-typedef struct {
-	EBI_NOR_SRAM_TypeDef *instance;		/**< Register base address */ 
-	EBI_NOR_SRAM_EXTENDED_TypeDef *ext;	/**< Extended mode register base address */
-	ald_ebi_nor_sram_init_t init;		/**< SRAM device control configuration parameters */
-	lock_state_t lock;			/**< SRAM locking object */ 
-	__IO ald_sram_state_t state;		/**< SRAM device access state */
-
-	dma_handle_t hdma;			/**< SRAM DMA Handle parameters */
-	void(*cplt_cbk)(void *arg);             /**< DMA transmit completely callback function */
-
-} sram_handle_t;
-/**
-  * @}
-  */
-
-/** @addtogroup SRAM_Public_Functions
-  * @{
-  */
-/** @addtogroup SRAM_Public_Functions_Group1
-  * @{
-  */
-/* Initialization functions */  
-ald_status_t ald_sram_init(sram_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing);
-ald_status_t  ald_sram_deinit(sram_handle_t *hperh);
-/**
-  * @}
-  */
-/** @addtogroup SRAM_Public_Functions_Group2
-  * @{
-  */
-/* I/O operation functions */
-ald_status_t ald_sram_read_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size);
-ald_status_t ald_sram_write_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size);
-ald_status_t ald_sram_read_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size);
-ald_status_t ald_sram_write_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size);
-ald_status_t ald_sram_read_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size);
-ald_status_t ald_sram_write_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size);
-#ifdef ALD_DMA
-ald_status_t ald_sram_read_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch);
-ald_status_t ald_sram_write_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch);
-#endif
-/**
-  * @}
-  */
-/** @addtogroup SRAM_Public_Functions_Group3
-  * @{
-  */
-/* Control functions */
-ald_status_t ald_sram_write_enable(sram_handle_t *hperh);
-ald_status_t ald_sram_write_disable(sram_handle_t *hperh);
-/**
-  * @}
-  */
-/** @addtogroup SRAM_Public_Functions_Group4
-  * @{
-  */
-/* State functions */
-ald_sram_state_t ald_sram_get_state(sram_handle_t *hperh);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */ 
-#ifdef __cplusplus
-}
-#endif
-#endif  /* __ALD_SRAM_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_syscfg.h

@@ -1,93 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_syscfg.h
-  * @brief   SYSCFG module driver.
-  *
-  * @version V1.0
-  * @date    04 Jun 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          04 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_SYSCFG_H__
-#define __ALD_SYSCFG_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup SYSCFG SYSCFG
-  * @brief SYSCFG module driver
-  * @{
-  */
-
-/** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros
-  * @{
-  */
-#define SYSCFG_LOCK()  		WRITE_REG(SYSCFG->PROT, 0x0U)
-#define SYSCFG_UNLOCK()		WRITE_REG(SYSCFG->PROT, 0x55AA6996U)
-#define GET_SYSCFG_LOCK()	READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK)
-
-#define SYSCFG_BOOTFLASH_MAPPING_ENABLE()	SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK)
-#define SYSCFG_BOOTFLASH_MAPPING_DISABLE()	CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK)
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_Public_Functions SYSCFG Public Functions
-  * @{
-  */
-/**
-  * @brief  Set the offset of the interrup vector map
-  * @param  offset: Offset of the interrup vector map
-  * @param  status: ENABLE/DISABLE
-  * @retval None
-  */
-__STATIC_INLINE__ void ald_vtor_config(uint32_t offset, type_func_t status)
-{
-	SCB->VTOR = status ? (offset & ~0x3FU) : 0;
-	return;
-}
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_trng.h

@@ -1,217 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_trng.h
-  * @brief   Header file of TRNG module driver.
-  *
-  * @version V1.0
-  * @date    26 Jun 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          26 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_TRNG_H__
-#define __ALD_TRNG_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup TRNG
-  * @{
-  */
-
-/** @defgroup TRNG_Public_Types TRNG Public Types
-  * @{
-  */
-/**
-  * @brief Data width
-  */
-typedef enum {
-	TRNG_DSEL_1B  = 0x0U,	/**< 1-bit */
-	TRNG_DSEL_8B  = 0x1U,	/**< 8-bits */
-	TRNG_DSEL_16B = 0x2U,	/**< 16-bits */
-	TRNG_DSEL_32B = 0x3U,	/**< 32-bits */
-} trng_data_width_t;
-
-/**
-  * @brief seed type
-  */
-typedef enum {
-	TRNG_SEED_TYPE_0    = 0x0U,	/**< Using 0 as seed */
-	TRNG_SEED_TYPE_1    = 0x1U,	/**< Using 1 as seed */
-	TRNG_SEED_TYPE_LAST = 0x2U,	/**< Using last seed */
-	TRNG_SEED_TYPE_SEED = 0x3U,	/**< Using value of register */
-} trng_seed_type_t;
-
-/**
-  * @brief TRNG init structure definition
-  */
-typedef struct {
-	trng_data_width_t data_width;	/**< The width of data */
-	trng_seed_type_t seed_type;	/**< The seed type */
-	uint32_t seed;			/**< The value of seed */
-	uint16_t t_start;		/**< T(start) = T(trng) * 2 ^ (t_start + 1), T(start) > 1ms */
-	uint8_t adjc;			/**< Adjust parameter */
-	type_func_t posten;		/**< Data back handle function  */
-} trng_init_t;
-
-/**
-  * @brief TRNG state structures definition
-  */
-typedef enum {
-	TRNG_STATE_RESET = 0x0U,	/**< Peripheral is not initialized */
-	TRNG_STATE_READY = 0x1U,	/**< Peripheral Initialized and ready for use */
-	TRNG_STATE_BUSY  = 0x2U,	/**< An internal process is ongoing */
-	TRNG_STATE_ERROR = 0x4U,	/**< Error */
-} trng_state_t;
-
-/**
-  * @brief State type
-  */
-typedef enum {
-	TRNG_STATUS_START = (1U << 0),	/**< Start state */
-	TRNG_STATUS_DAVLD = (1U << 1),	/**< Data valid state */
-	TRNG_STATUS_SERR  = (1U << 2),	/**< Error state */
-} trng_status_t;
-
-/**
-  * @brief Interrupt type
-  */
-typedef enum {
-	TRNG_IT_START = (1U << 0),	/**< Start */
-	TRNG_IT_DAVLD = (1U << 1),	/**< Data valid */
-	TRNG_IT_SERR  = (1U << 2),	/**< Error */
-} trng_it_t;
-
-/**
-  * @brief Interrupt flag type
-  */
-typedef enum {
-	TRNG_IF_START = (1U << 0),	/**< Start */
-	TRNG_IF_DAVLD = (1U << 1),	/**< Data valid */
-	TRNG_IF_SERR  = (1U << 2),	/**< Error */
-} trng_flag_t;
-
-/**
-  * @brief  TRNG Handle Structure definition
-  */
-typedef struct trng_handle_s {
-	TRNG_TypeDef *perh;	/**< Register base address */
-	trng_init_t init;	/**< TRNG required parameters */
-	uint32_t data;		/**< result data */
-	lock_state_t lock; 	/**< Locking object */
-	trng_state_t state;	/**< TRNG operation state */
-
-	void (*trng_cplt_cbk)(struct trng_handle_s *arg); /**< Trng completed callback */
-	void (*err_cplt_cbk)(struct trng_handle_s *arg);  /**< Trng error callback */
-	void (*init_cplt_cbk)(struct trng_handle_s *arg); /**< Trng init completed callback */
-} trng_handle_t;
-/**
-  * @}
-  */
-
-/** @defgroup TRNG_Public_Macros TRNG Public Macros
-  * @{
-  */
-#define TRNG_ENABLE()		(SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
-#define TRNG_DISABLE()		(CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
-#define TRNG_ADJM_ENABLE()	(SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
-#define TRNG_ADJM_DISABLE()	(CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
-/**
-  * @}
-  */
-
-/**
-  * @defgroup TRNG_Private_Macros TRNG Private Macros
-  * @{
-  */
-#define IS_TRNG_DATA_WIDTH(x)	(((x) == TRNG_DSEL_1B)  || \
-                                 ((x) == TRNG_DSEL_8B)  || \
-                                 ((x) == TRNG_DSEL_16B) || \
-                                 ((x) == TRNG_DSEL_32B))
-#define IS_TRNG_SEED_TYPE(x)	(((x) == TRNG_SEED_TYPE_0)    || \
-                                 ((x) == TRNG_SEED_TYPE_1)    || \
-                                 ((x) == TRNG_SEED_TYPE_LAST) || \
-                                 ((x) == TRNG_SEED_TYPE_SEED))
-#define IS_TRNG_STATUS(x)	(((x) == TRNG_STATUS_START)  || \
-                                 ((x) == TRNG_STATUS_DAVLD)  || \
-                                 ((x) == TRNG_STATUS_SERR))
-#define IS_TRNG_IT(x)		(((x) == TRNG_IT_START)  || \
-                                 ((x) == TRNG_IT_DAVLD)  || \
-                                 ((x) == TRNG_IT_SERR))
-#define IS_TRNG_FLAG(x)		(((x) == TRNG_IF_START)  || \
-                                 ((x) == TRNG_IF_DAVLD)  || \
-                                 ((x) == TRNG_IF_SERR))
-#define IS_TRNG_ADJC(x)		((x) < 4)
-#define IS_TRNG_T_START(x)	((x) < 8)
-/**
-  * @}
-  */
-
-/** @addtogroup TRNG_Public_Functions
-  * @{
-  */
-/** @addtogroup TRNG_Public_Functions_Group1
-  * @{
-  */
-/* Initialization functions */
-extern ald_status_t ald_trng_init(trng_handle_t *hperh);
-/**
-  * @}
-  */
-/** @addtogroup TRNG_Public_Functions_Group2
-  * @{
-  */
-/* Control functions */
-extern uint32_t ald_trng_get_result(trng_handle_t *hperh);
-extern void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state);
-extern flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status);
-extern it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it);
-extern flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag);
-extern void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag);
-extern void ald_trng_irq_handler(trng_handle_t *hperh);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_TRNG_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_tsense.h

@@ -1,215 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_tsense.h
-  * @brief   Header file of TSENSE module driver.
-  *
-  * @version V1.0
-  * @date    26 Jun 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          26 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_TSENSE_H__
-#define __ALD_TSENSE_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup TSENSE
-  * @{
-  */
-
-/** @defgroup TSENSE_Public_Macros TSENSE Public Macros
-  * @{
-  */
-#define TSENSE_LOCK()		(WRITE_REG(TSENSE->WPR, 0x0U))
-#define TSENSE_UNLOCK()		(WRITE_REG(TSENSE->WPR, 0xA55A9669U))
-#define TSENSE_ENABLE()					\
-do {							\
-	TSENSE_UNLOCK();				\
-	SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);		\
-	TSENSE_LOCK();					\
-} while (0)
-#define TSENSE_DISABLE()				\
-do {							\
-	TSENSE_UNLOCK();				\
-	CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);	\
-	TSENSE_LOCK();					\
-} while (0)
-#define TSENSE_REQ_ENABLE()				\
-do {							\
-	TSENSE_UNLOCK();				\
-	SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK);	\
-	TSENSE_LOCK();					\
-} while (0)
-#define TSENSE_REQ_DISABLE()				\
-do {							\
-	TSENSE_UNLOCK();				\
-	CLEAR_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK);	\
-	TSENSE_LOCK();					\
-} while (0)
-#define TSENSE_CTN_ENABLE()				\
-do {							\
-	TSENSE_UNLOCK();				\
-	SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK);		\
-	TSENSE_LOCK();					\
-} while (0)
-#define TSENSE_CTN_DISABLE()				\
-do {							\
-	TSENSE_UNLOCK();				\
-	CLEAR_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK);	\
-	TSENSE_LOCK();					\
-} while (0)
-#define TSENSE_RESET()					\
-do {							\
-	TSENSE_UNLOCK();				\
-	SET_BIT(TSENSE->CR, TSENSE_CR_RST_MSK);		\
-	TSENSE_LOCK();					\
-} while (0)
-#define	TSENSE_LTGR_WR(data)				\
-do {							\
-	TSENSE_UNLOCK();				\
-	WRITE_REG(TSENSE->LTGR, (data));		\
-	TSENSE_LOCK();					\
-} while (0)
-#define	TSENSE_HTGR_WR(data)				\
-do {							\
-	TSENSE_UNLOCK();				\
-	WRITE_REG(TSENSE->HTGR, (data));		\
-	TSENSE_LOCK();					\
-} while (0)
-#define	TSENSE_TBDR_WR(data)				\
-do {							\
-	TSENSE_UNLOCK();				\
-	WRITE_REG(TSENSE->TBDR, (data));		\
-	TSENSE_LOCK();					\
-} while (0)
-#define	TSENSE_TCALBDR_WR(data)				\
-do {							\
-	TSENSE_UNLOCK();				\
-	WRITE_REG(TSENSE->TCALBDR, (data));		\
-	TSENSE_LOCK();					\
-} while (0)
-/**
-  * @}
-  */
-
-/** @defgroup TSENSE_Public_Types TSENSE Public Types
-  * @{
-  */
-/**
-  * @brief Temperature update time
-  */
-typedef enum {
-	TSENSE_UPDATE_CYCLE_3 = 0x3U,	/**< 3 Cycles */
-	TSENSE_UPDATE_CYCLE_4 = 0x4U,	/**< 4 Cycles */
-	TSENSE_UPDATE_CYCLE_5 = 0x5U,	/**< 5 Cycles */
-	TSENSE_UPDATE_CYCLE_6 = 0x6U,	/**< 6 Cycles */
-	TSENSE_UPDATE_CYCLE_7 = 0x7U,	/**< 7 Cycles */
-} tsense_update_cycle_t;
-
-/**
-  * @brief Temperature output mode
-  */
-typedef enum {
-	TSENSE_OUTPUT_MODE_200  = 0x0U,	/**< 200 cycles update one temperature */
-	TSENSE_OUTPUT_MODE_400  = 0x1U,	/**< 400 cycles update one temperature */
-	TSENSE_OUTPUT_MODE_800  = 0x2U,	/**< 800 cycles update one temperature */
-	TSENSE_OUTPUT_MODE_1600 = 0x3U,	/**< 1600 cycles update one temperature */
-	TSENSE_OUTPUT_MODE_3200 = 0x4U,	/**< 3200 cycles update one temperature */
-} tsense_output_mode_t;
-
-/**
-  * @brief Source select
-  */
-typedef enum {
-	TSENSE_SOURCE_LOSC        = 0x0U,	/**< LOSC */
-	TSENSE_SOURCE_LRC         = 0x1U,	/**< LRC */
-} tsense_source_sel_t;
-
-
-/**
-  * @brief Define callback function type
-  */
-typedef void (*tsense_cbk)(uint16_t value, ald_status_t status);
-/**
-  * @}
-  */
-
-/**
-  * @defgroup TSENSE_Private_Macros TSENSE Private Macros
-  * @{
-  */
-#define IS_TSENSE_SOURCE_SEL(x)	(((x) == TSENSE_SOURCE_LOSC) || \
-                                 ((x) == TSENSE_SOURCE_LRC))
-/**
-  * @}
-  */
-
-/** @addtogroup TSENSE_Public_Functions
-  * @{
-  */
-/** @addtogroup TSENSE_Public_Functions_Group1
-  * @{
-  */
-/* Initialization functions */
-extern void ald_tsense_init(void);
-extern void ald_tsense_source_select(tsense_source_sel_t sel);
-/**
-  * @}
-  */
-/** @addtogroup TSENSE_Public_Functions_Group2
-  * @{
-  */
-/* Control functions */
-extern ald_status_t ald_tsense_get_value(uint16_t *tsense);
-extern void ald_tsense_get_value_by_it(tsense_cbk cbk);
-extern void ald_tsense_irq_handler(void);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_TSENSE_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_uart.h

@@ -1,551 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_uart.h
-  * @brief   Header file of UART module library.
-  *
-  * @version V1.0
-  * @date    21 Nov 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          21 Nov 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_UART_H__
-#define __ALD_UART_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-#include "ald_dma.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup UART
-  * @{
-  */
-
-/**
-  * @defgroup UART_Public_Macros UART Public Macros
-  * @{
-  */
-#define UART_RX_ENABLE(hperh)		(SET_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK))
-#define UART_RX_DISABLE(hperh)		(CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK))
-#define UART_TX_ENABLE(hperh)		(SET_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK))
-#define UART_TX_DISABLE(hperh)		(CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK))
-#define UART_RX_TIMEOUT_ENABLE(hperh)	(SET_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK))
-#define UART_RX_TIMEOUT_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK))
-#define UART_MSB_FIRST_ENABLE(hperh)	(SET_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK))
-#define UART_MSB_FIRST_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK))
-#define UART_DATA_INV_ENABLE(hperh)	(SET_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK))
-#define UART_DATA_INV_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK))
-#define UART_RX_INV_ENABLE(hperh)	(SET_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK))
-#define UART_RX_INV_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK))
-#define UART_TX_INV_ENABLE(hperh)	(SET_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK))
-#define UART_TX_INV_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK))
-#define UART_TX_RX_SWAP_ENABLE(hperh)	(SET_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK))
-#define UART_TX_RX_SWAP_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK))
-#define UART_HDSEL_ENABLE(hperh)	(SET_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK))
-#define UART_HDSEL_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK))
-#define UART_FIFO_TX_RESET(hperh)	(SET_BIT((hperh)->perh->FCON, UART_FCON_TFRST_MSK))
-#define UART_FIFO_RX_RESET(hperh)	(SET_BIT((hperh)->perh->FCON, UART_FCON_RFRST_MSK))
-#define UART_LPBMOD_ENABLE(hperh)	(SET_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK))
-#define UART_LPBMOD_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK))
-#define UART_AUTOBR_ENABLE(hperh)	(SET_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK))
-#define UART_AUTOBR_DISABLE(hperh)	(CLEAR_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK))
-#define UART_AUTOBR_REPT(hperh)		(SET_BIT((hperh)->perh->MCON, UART_MCON_ABRREPT_MSK))
-#define UART_GET_BRR_VALUE(hperh)	(READ_REG((hperh)->perh->BRR))
-#define UART_SET_TIMEOUT_VALUE(x, y)	(MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS))
-#define UART_ENABLE_SCARD_CLK(hperh)    (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK))
-#define UART_DISABLE_SCARD_CLK(hperh)   (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK))
-#define UART_ENABLE_SCARD_NACK(hperh)   (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK))
-#define UART_DISABLE_SCARD_NACK(hperh)  (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK))
-#define UART_SCARD_ENABLE(hperh)        (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK))
-#define UART_SCARD_DISABLE(hperh)       (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK))
-/**
-  * @}
-  */
-
-/** @defgroup UART_Public_Types UART Public Types
-  * @{
-  */
-/**
-  * @brief UART word length
-  */
-typedef enum {
-	UART_WORD_LENGTH_8B = 0x0U,	/**< 8-bits */
-	UART_WORD_LENGTH_7B = 0x1U,	/**< 7-bits */
-	UART_WORD_LENGTH_6B = 0x2U,	/**< 6-bits */
-	UART_WORD_LENGTH_5B = 0x3U,	/**< 5-bits */
-} uart_word_length_t;
-
-/**
-  * @brief UART stop bits
-  */
-typedef enum {
-	UART_STOP_BITS_1   = 0x0U,	/**< 1-bits */
-	UART_STOP_BITS_2   = 0x1U,	/**< 2-bits */
-	UART_STOP_BITS_0_5 = 0x0U,	/**< 0.5-bits, using smartcard mode */
-	UART_STOP_BITS_1_5 = 0x1U,	/**< 1.5-bits, using smartcard mode */
-} uart_stop_bits_t;
-
-/**
-  * @brief UART parity
-  */
-typedef enum {
-	UART_PARITY_NONE = 0x0U,	/**< Not parity */
-	UART_PARITY_ODD  = 0x1U,	/**< Odd parity */
-	UART_PARITY_EVEN = 0x3U,	/**< Even parity */
-} uart_parity_t;
-
-/**
-  * @brief UART mode
-  */
-typedef enum {
-	UART_MODE_UART  = 0x0U,	/**< UART */
-	UART_MODE_LIN   = 0x1U,	/**< LIN */
-	UART_MODE_IrDA  = 0x2U,	/**< IrDA */
-	UART_MODE_RS485 = 0x3U,	/**< RS485 */
-	UART_MODE_HDSEL = 0x4U,	/**< Single-wire half-duplex */
-	UART_MODE_SCARD = 0x5U,	/**< Smart card */
-} uart_mode_t;
-
-/**
-  * @brief UART hardware flow control
-  */
-typedef enum {
-	UART_HW_FLOW_CTL_DISABLE = 0x0U,	/**< Auto-flow-control disable */
-	UART_HW_FLOW_CTL_ENABLE  = 0x1U,	/**< Auto-flow-control enable */
-} uart_hw_flow_ctl_t;
-
-/**
-  * @brief ALD UART state
-  */
-typedef enum {
-	UART_STATE_RESET      = 0x00U,	/**< Peripheral is not initialized */
-	UART_STATE_READY      = 0x01U,	/**< Peripheral Initialized and ready for use */
-	UART_STATE_BUSY       = 0x02U,	/**< an internal process is ongoing */
-	UART_STATE_BUSY_TX    = 0x11U,	/**< Data Transmission process is ongoing */
-	UART_STATE_BUSY_RX    = 0x21U,	/**< Data Reception process is ongoing */
-	UART_STATE_BUSY_TX_RX = 0x31U,	/**< Data Transmission Reception process is ongoing */
-	UART_STATE_TIMEOUT    = 0x03U,	/**< Timeout state */
-	UART_STATE_ERROR      = 0x04U,	/**< Error */
-} uart_state_t;
-
-/**
-  * @brief UART error codes
-  */
-typedef enum {
-	UART_ERROR_NONE = ((uint32_t)0x00U),	/**< No error */
-	UART_ERROR_PE   = ((uint32_t)0x01U),	/**< Parity error */
-	UART_ERROR_NE   = ((uint32_t)0x02U),	/**< Noise error */
-	UART_ERROR_FE   = ((uint32_t)0x04U),	/**< frame error */
-	UART_ERROR_ORE  = ((uint32_t)0x08U),	/**< Overrun error */
-	UART_ERROR_DMA  = ((uint32_t)0x10U),	/**< DMA transfer error */
-} uart_error_t;
-
-/**
-  * @brief UART init structure definition
-  */
-typedef struct {
-	uint32_t baud;			/**< Specifies the uart communication baud rate */
-	uart_word_length_t word_length;	/**< Specifies the number of data bits transmitted or received in a frame */
-	uart_stop_bits_t stop_bits;	/**< Specifies the number of stop bits transmitted */
-	uart_parity_t parity;		/**< Specifies the parity mode */
-	uart_mode_t mode;		/**< Specifies uart mode */
-	uart_hw_flow_ctl_t fctl;	/**< Specifies wether the hardware flow control mode is enabled or disabled */
-} uart_init_t;
-
-/**
-  * @brief  UART handle structure definition
-  */
-typedef struct uart_handle_s {
-	UART_TypeDef *perh;	/**< UART registers base address */
-	uart_init_t init;	/**< UART communication parameters */
-	uint8_t *tx_buf;	/**< Pointer to UART Tx transfer Buffer */
-	uint16_t tx_size;	/**< UART Tx Transfer size */
-	uint16_t tx_count;	/**< UART Tx Transfer Counter */
-	uint8_t *rx_buf;	/**< Pointer to UART Rx transfer Buffer */
-	uint16_t rx_size;	/**< UART Rx Transfer size */
-	uint16_t rx_count;	/**< UART Rx Transfer Counter */
-
-	dma_handle_t hdmatx;	/**< UART Tx DMA Handle parameters */
-	dma_handle_t hdmarx;	/**< UART Rx DMA Handle parameters */
-
-	lock_state_t lock;	/**< Locking object */
-	uart_state_t state;	/**< UART communication state */
-	uart_error_t err_code;	/**< UART Error code */
-
-	void (*tx_cplt_cbk)(struct uart_handle_s *arg);	/**< Tx completed callback */
-	void (*rx_cplt_cbk)(struct uart_handle_s *arg);	/**< Rx completed callback */
-	void (*error_cbk)(struct uart_handle_s *arg);	/**< error callback */
-} uart_handle_t;
-
-/**
-  * @brief UART RS485 configure structure definition
-  */
-typedef struct {
-	type_func_t normal;	/**< Normal mode */
-	type_func_t dir;	/**< Auto-direction mode */
-	type_func_t invert;	/**< Address detection invert */
-	uint8_t addr;		/**< Address for compare */
-} uart_rs485_config_t;
-
-/**
-  * @brief Smart_card Rx/Tx handle retry time
-  */
-typedef enum {
-	SCARD_RETRY_CNT0 = 0x0U,	/**< retry time 0 */
-	SCARD_RETRY_CNT1 = 0x1U,	/**< retry time 1 */
-	SCARD_RETRY_CNT2 = 0x2U,	/**< retry time 2 */
-	SCARD_RETRY_CNT3 = 0x3U,	/**< retry time 3 */
-	SCARD_RETRY_CNT4 = 0x4U,	/**< retry time 4 */
-	SCARD_RETRY_CNT5 = 0x5U,	/**< retry time 5 */
-	SCARD_RETRY_CNT6 = 0x6U,	/**< retry time 6 */
-	SCARD_RETRY_CNT7 = 0x7U,	/**< retry time 7 */
-} scard_retry_t;
-
-/**
-  * @brief UART Smart card configure structure definition
-  */
-typedef struct {
-	uint8_t block_len;       /**< Specifies the data block length.*/
-	uint8_t pt;	         /**< Specifies the protect time*/
-	scard_retry_t retry;	 /**< Specifies retry time.*/
-	uint8_t clk_div;         /**< Specifies the clock division.*/
-	type_func_t clk_out;     /**< Specifies the clock out */
-} uart_scard_config_t;
-
-/**
-  * @brief LIN detection break length
-  */
-typedef enum {
-	LIN_BREAK_LEN_10B = 0x0U,	/**< 10-bit break */
-	LIN_BREAK_LEN_11B = 0x1U,	/**< 11-bit break */
-} uart_lin_break_len_t;
-
-/**
-  * @brief UART TXFIFO size
-  */
-typedef enum {
-	UART_TXFIFO_EMPTY = 0x0U,	/**< Empty */
-	UART_TXFIFO_2BYTE = 0x1U,	/**< 2-Bytes */
-	UART_TXFIFO_4BYTE = 0x2U,	/**< 4-Bytes */
-	UART_TXFIFO_8BYTE = 0x3U,	/**< 8-Bytes */
-} uart_txfifo_t;
-
-/**
-  * @brief UART RXFIFO size
-  */
-typedef enum {
-	UART_RXFIFO_1BYTE  = 0x0U,	/**< 1-Byte */
-	UART_RXFIFO_4BYTE  = 0x1U,	/**< 4-Bytes */
-	UART_RXFIFO_8BYTE  = 0x2U,	/**< 8-Bytes */
-	UART_RXFIFO_14BYTE = 0x3U,	/**< 14-Bytes */
-} uart_rxfifo_t;
-
-/**
-  * @brief UART auto-baud mode
-  */
-typedef enum {
-	UART_ABRMOD_1_TO_0 = 0x0U,	/**< Detect bit0:1, bit1:0 */
-	UART_ABRMOD_1      = 0x1U,	/**< Detect bit0:1 */
-	UART_ABRMOD_0_TO_1 = 0x2U,	/**< Detect bit0:0, bit1:1 */
-} uart_auto_baud_mode_t;
-
-/**
-  * @brief UART DMA Requests
-  */
-typedef enum {
-	UART_DMA_REQ_TX = 0x0U,	/**< TX dma */
-	UART_DMA_REQ_RX = 0x1U,	/**< RX dma */
-} uart_dma_req_t;
-
-/**
-  * @brief UART status types
-  */
-typedef enum {
-	UART_STATUS_PERR    = (1U << 0),	/**< Parity error */
-	UART_STATUS_FERR    = (1U << 1),	/**< Framing error */
-	UART_STATUS_BKERR   = (1U << 2),	/**< Break error */
-	UART_STATUS_CTSSTA  = (1U << 3),	/**< Clear to send status */
-	UART_STATUS_RSBUSY  = (1U << 8),	/**< Receive shif register busy */
-	UART_STATUS_RFTH    = (1U << 9),	/**< Receive FIFO trigger threshold */
-	UART_STATUS_RFEMPTY = (1U << 10),	/**< Receive FIFO empty */
-	UART_STATUS_RFFULL  = (1U << 11),	/**< Receive FIFO full */
-	UART_STATUS_RFOERR  = (1U << 12),	/**< Reveive FIFO overrun error */
-	UART_STATUS_RFUERR  = (1U << 13),	/**< Receive FIFO underrun error */
-	UART_STATUS_TSBUSY  = (1U << 14),	/**< Transmit shit register busy */
-	UART_STATUS_TFTH    = (1U << 15),	/**< Transmit FIFO trigger threshold */
-	UART_STATUS_TFEMPTY = (1U << 16),	/**< Transmit FIFO empty */
-	UART_STATUS_TFFULL  = (1U << 17),	/**< Transmit FIFO full */
-	UART_STATUS_TFOERR  = (1U << 18),	/**< Transmit FIFO overrun error */
-} uart_status_t;
-
-/**
-  * @brief UART interrupt types
-  */
-typedef enum {
-	UART_IT_RXBERR  = (1U << 0),	/**< Receiver byte error */
-	UART_IT_ABEND   = (1U << 1),	/**< Auto-Baud rate detection end */
-	UART_IT_ABTO    = (1U << 2),	/**< Auto-Baud rate detection timeout */
-	UART_IT_DCTS    = (1U << 3),	/**< Delta CTS status */
-	UART_IT_RXTO    = (1U << 4),	/**< Receiver timeout */
-	UART_IT_ADDRM   = (1U << 5),	/**< Addredd match */
-	UART_IT_LINBK   = (1U << 6),	/**< Lin break detection */
-	UART_IT_EOB     = (1U << 7),	/**< End of block */
-	UART_IT_NOISE   = (1U << 8),	/**< Start bit noise detection */
-	UART_IT_RFTH    = (1U << 9),	/**< Receive FIFO trigger threshold */
-	UART_IT_RFFULL  = (1U << 11),	/**< Receive FIFO full */
-	UART_IT_RFOERR  = (1U << 12),	/**< Receive FIFO overrun */
-	UART_IT_RFUERR  = (1U << 13),	/**< Reveive FIFO underrun */
-	UART_IT_TBC     = (1U << 14),	/**< Transmit shift register empty */
-	UART_IT_TFTH    = (1U << 15),	/**< Transmit FIFO trigger threshold */
-	UART_IT_TFEMPTY = (1U << 16),	/**< Transmit FIFO empty */
-	UART_IT_TFOVER  = (1U << 18),	/**< Transmit FIFO overrun */
-} uart_it_t;
-
-/**
-  * @brief UART flags types
-  */
-typedef enum {
-	UART_IF_RXBERR  = (1U << 0),	/**< Receiver byte error */
-	UART_IF_ABEND   = (1U << 1),	/**< Auto-Baud rate detection end */
-	UART_IF_ABTO    = (1U << 2),	/**< Auto-Baud rate detection timeout */
-	UART_IF_DCTS    = (1U << 3),	/**< Delta CTS status */
-	UART_IF_RXTO    = (1U << 4),	/**< Receiver timeout */
-	UART_IF_ADDRM   = (1U << 5),	/**< Addredd match */
-	UART_IF_LINBK   = (1U << 6),	/**< Lin break detection */
-	UART_IF_EOB     = (1U << 7),	/**< End of block */
-	UART_IF_NOISE   = (1U << 8),	/**< Start bit noise detection */
-	UART_IF_RFTH    = (1U << 9),	/**< Receive FIFO trigger threshold */
-	UART_IF_RFFULL  = (1U << 11),	/**< Receive FIFO full */
-	UART_IF_RFOERR  = (1U << 12),	/**< Receive FIFO overrun */
-	UART_IF_RFUERR  = (1U << 13),	/**< Reveive FIFO underrun */
-	UART_IF_TBC     = (1U << 14),	/**< Transmit shift register empty */
-	UART_IF_TFTH    = (1U << 15),	/**< Transmit FIFO trigger threshold */
-	UART_IF_TFEMPTY = (1U << 16),	/**< Transmit FIFO empty */
-	UART_IF_TFOVER  = (1U << 18),	/**< Transmit FIFO overrun */
-} uart_flag_t;
-/**
-  * @}
-  */
-
-/** @defgroup UART_Private_Macros   UART Private Macros
-  * @{
-  */
-#define IS_UART_SCARD(x)(((x) == UART4) || \
-                         ((x) == UART5))
-#define IS_UART_ALL(x)	(((x) == UART0) || \
-                         ((x) == UART1) || \
-                         ((x) == UART2) || \
-                         ((x) == UART3) || \
-                         ((x) == UART4) || \
-                         ((x) == UART5))
-#define IS_UART_WORD_LENGTH(x)	(((x) == UART_WORD_LENGTH_5B) || \
-                                 ((x) == UART_WORD_LENGTH_6B) || \
-                                 ((x) == UART_WORD_LENGTH_7B) || \
-                                 ((x) == UART_WORD_LENGTH_8B))
-#define IS_UART_STOPBITS(x)	(((x) == UART_STOP_BITS_1)   || \
-                                 ((x) == UART_STOP_BITS_2)   || \
-                                 ((x) == UART_STOP_BITS_0_5) || \
-                                 ((x) == UART_STOP_BITS_1_5))
-#define IS_UART_PARITY(x)	(((x) == UART_PARITY_NONE)  || \
-                                 ((x) == UART_PARITY_ODD) || \
-                                 ((x) == UART_PARITY_EVEN))
-#define IS_UART_MODE(x)		(((x) == UART_MODE_UART) || \
-                                 ((x) == UART_MODE_LIN)  || \
-                                 ((x) == UART_MODE_IrDA) || \
-                                 ((x) == UART_MODE_HDSEL) || \
-                                 ((x) == UART_MODE_SCARD) || \
-                                 ((x) == UART_MODE_RS485))
-#define IS_UART_HARDWARE_FLOW_CONTROL(x) \
-                                (((x) == UART_HW_FLOW_CTL_DISABLE) || \
-                                 ((x) == UART_HW_FLOW_CTL_ENABLE))
-#define IS_UART_LIN_BREAK_LEN(x)	(((x) == LIN_BREAK_LEN_10B) || \
-                                         ((x) == LIN_BREAK_LEN_11B))
-#define IS_UART_TXFIFO_TYPE(x)	(((x) == UART_TXFIFO_EMPTY) || \
-                                 ((x) == UART_TXFIFO_2BYTE) || \
-                                 ((x) == UART_TXFIFO_4BYTE) || \
-                                 ((x) == UART_TXFIFO_8BYTE))
-#define IS_UART_RXFIFO_TYPE(x)	(((x) == UART_RXFIFO_1BYTE) || \
-                                 ((x) == UART_RXFIFO_4BYTE) || \
-                                 ((x) == UART_RXFIFO_8BYTE) || \
-                                 ((x) == UART_RXFIFO_14BYTE))
-#define IS_UART_AUTO_BAUD_MODE(x)	(((x) == UART_ABRMOD_1_TO_0) || \
-                                         ((x) == UART_ABRMOD_1)      || \
-                                         ((x) == UART_ABRMOD_0_TO_1))
-#define IS_UART_DMA_REQ(x)	(((x) == UART_DMA_REQ_TX) || \
-                                 ((x) == UART_DMA_REQ_RX))
-#define IS_UART_STATUS(x)	(((x) == UART_STATUS_PERR)    || \
-                                 ((x) == UART_STATUS_FERR)    || \
-                                 ((x) == UART_STATUS_BKERR)   || \
-                                 ((x) == UART_STATUS_CTSSTA)  || \
-                                 ((x) == UART_STATUS_RSBUSY)  || \
-                                 ((x) == UART_STATUS_RFEMPTY) || \
-                                 ((x) == UART_STATUS_RFFULL)  || \
-                                 ((x) == UART_STATUS_RFOERR)  || \
-                                 ((x) == UART_STATUS_RFUERR)  || \
-                                 ((x) == UART_STATUS_TSBUSY)  || \
-                                 ((x) == UART_STATUS_RFTH)    || \
-                                 ((x) == UART_STATUS_TFTH)    || \
-                                 ((x) == UART_STATUS_TFEMPTY) || \
-                                 ((x) == UART_STATUS_TFFULL)  || \
-                                 ((x) == UART_STATUS_TFOERR))
-#define IS_UART_IT(x)		(((x) == UART_IT_RXBERR)  || \
-                                 ((x) == UART_IT_ABEND)   || \
-                                 ((x) == UART_IT_ABTO)    || \
-                                 ((x) == UART_IT_DCTS)    || \
-                                 ((x) == UART_IT_RXTO)    || \
-                                 ((x) == UART_IT_ADDRM)   || \
-                                 ((x) == UART_IT_LINBK)   || \
-                                 ((x) == UART_IT_EOB)     || \
-                                 ((x) == UART_IT_NOISE)   || \
-                                 ((x) == UART_IT_RFTH)    || \
-                                 ((x) == UART_IT_RFFULL)  || \
-                                 ((x) == UART_IT_RFOERR)  || \
-                                 ((x) == UART_IT_RFUERR)  || \
-                                 ((x) == UART_IT_TBC) || \
-                                 ((x) == UART_IT_TFTH)    || \
-                                 ((x) == UART_IT_TFEMPTY) || \
-                                 ((x) == UART_IT_TFOVER))
-#define IS_UART_IF(x)		(((x) == UART_IF_RXBERR)  || \
-                                 ((x) == UART_IF_ABEND)   || \
-                                 ((x) == UART_IF_ABTO)    || \
-                                 ((x) == UART_IF_DCTS)    || \
-                                 ((x) == UART_IF_RXTO)    || \
-                                 ((x) == UART_IF_ADDRM)   || \
-                                 ((x) == UART_IF_LINBK)   || \
-                                 ((x) == UART_IF_EOB)     || \
-                                 ((x) == UART_IF_NOISE)   || \
-                                 ((x) == UART_IF_RFTH)    || \
-                                 ((x) == UART_IF_RFFULL)  || \
-                                 ((x) == UART_IF_RFOERR)  || \
-                                 ((x) == UART_IF_RFUERR)  || \
-                                 ((x) == UART_IF_TBC) || \
-                                 ((x) == UART_IF_TFTH)    || \
-                                 ((x) == UART_IF_TFEMPTY) || \
-                                 ((x) == UART_IF_TFOVER))
-#define IS_UART_SCARD_CLK(x) (((x) <= 0x1F))
-#define IS_UART_BAUDRATE(x)	(((x) > 0) && ((x) < 0x44AA21))
-#define IS_UART_DATA(x)		((x) <= 0x1FF)
-
-#define UART_STATE_TX_MASK	(1U << 4)
-#define UART_STATE_RX_MASK	(1U << 5)
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Public_Functions
-  * @{
-  */
-
-/** @addtogroup UART_Public_Functions_Group1
-  * @{
-  */
-/* Initialization functions */
-void ald_uart_init(uart_handle_t *hperh);
-void ald_uart_reset(uart_handle_t *hperh);
-void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config);
-void ald_uart_scard_config(uart_handle_t *hperh, uart_scard_config_t *config);
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Public_Functions_Group2
-  * @{
-  */
-/* IO operation functions */
-ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t ald_uart_send_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t ald_uart_recv_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
-ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size);
-ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size);
-ald_status_t ald_uart_recv_frame_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out);
-
-ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
-ald_status_t ald_uart_dma_pause(uart_handle_t *hperh);
-ald_status_t ald_uart_dma_resume(uart_handle_t *hperh);
-ald_status_t ald_uart_dma_stop(uart_handle_t *hperh);
-
-void ald_uart_irq_handler(uart_handle_t *hperh);
-void ald_uart_irq_handler_fast(uart_handle_t *hperh);
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Public_Functions_Group3
-  * @{
-  */
-/* Peripheral Control functions */
-void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state);
-void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state);
-void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config);
-void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config);
-void uart_lin_break_detect_irq(uart_handle_t *hperh, type_func_t status);
-void ald_uart_lin_send_break(uart_handle_t *hperh);
-void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len);
-void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode);
-ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout);
-it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it);
-flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status);
-flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag);
-flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag);
-void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag);
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Public_Functions_Group4
-  * @{
-  */
-/* Peripheral State and Errors functions */
-uart_state_t ald_uart_get_state(uart_handle_t *hperh);
-uint32_t ald_uart_get_error(uart_handle_t *hperh);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_UART_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_usb.h

@@ -1,618 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_usb.h
-  * @brief   Header file of USB module driver.
-  *
-  * @version V1.0
-  * @date    25 Dec 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          25 Dec 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __ALD_USB_H__
-#define __ALD_USB_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdbool.h>
-#include "utils.h"
-#include "ald_rmu.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup USB
-  * @{
-  */
-
-/** @defgroup USB_Public_Macros USB Public Macros
-  * @{
-  */
-
-#define USB_POWER_ISOUP         0x00000080U
-#define USB_POWER_SOFTCONN      0x00000040U
-#define USB_POWER_HS_EN		0x00000020U
-#define USB_POWER_HS_M		0x00000010U
-#define USB_POWER_RESET         0x00000008U
-#define USB_POWER_RESUME        0x00000004U
-#define USB_POWER_SUSPEND       0x00000002U
-#define USB_POWER_PWRDNPHY      0x00000001U
-
-#define USB_DEVCTL_DEV          0x00000080U
-#define USB_DEVCTL_FSDEV        0x00000040U
-#define USB_DEVCTL_LSDEV        0x00000020U
-#define USB_DEVCTL_VBUS_M       0x00000018U
-#define USB_DEVCTL_VBUS_NONE    0x00000000U
-#define USB_DEVCTL_VBUS_SEND    0x00000008U
-#define USB_DEVCTL_VBUS_AVALID  0x00000010U
-#define USB_DEVCTL_VBUS_VALID   0x00000018U
-#define USB_DEVCTL_HOST         0x00000004U
-#define USB_DEVCTL_HOSTREQ      0x00000002U
-#define USB_DEVCTL_SESSION      0x00000001U
-
-#define USB_RXCSRH1_AUTOCL      0x00000080U
-#define USB_RXCSRH1_AUTORQ      0x00000040U
-#define USB_RXCSRH1_ISO         0x00000040U
-#define USB_RXCSRH1_DMAEN       0x00000020U
-#define USB_RXCSRH1_DISNYET     0x00000010U
-#define USB_RXCSRH1_PIDERR      0x00000010U
-#define USB_RXCSRH1_DMAMOD      0x00000008U
-#define USB_RXCSRH1_DTWE        0x00000004U
-#define USB_RXCSRH1_DT          0x00000002U
-#define USB_RXCSRH1_INCOMPRX    0x00000001U
-
-#define USB_CSRH0_DISPING       0x00000008U
-#define USB_CSRH0_DTWE          0x00000004U
-#define USB_CSRH0_DT            0x00000002U
-#define USB_CSRH0_FLUSH         0x00000001U
-
-#define USB_TXCSRH1_AUTOSET     0x00000080U
-#define USB_TXCSRH1_ISO         0x00000040U
-#define USB_TXCSRH1_MODE        0x00000020U
-#define USB_TXCSRH1_DMAEN       0x00000010U
-#define USB_TXCSRH1_FDT         0x00000008U
-#define USB_TXCSRH1_DMAMOD      0x00000004U
-#define USB_TXCSRH1_DTWE        0x00000002U
-#define USB_TXCSRH1_DT          0x00000001U
-
-#define USB_TXCSRL1_NAKTO       0x00000080U
-#define USB_TXCSRL1_CLRDT       0x00000040U
-#define USB_TXCSRL1_STALLED     0x00000020U
-#define USB_TXCSRL1_STALL       0x00000010U
-#define USB_TXCSRL1_SETUP       0x00000010U
-#define USB_TXCSRL1_FLUSH       0x00000008U
-#define USB_TXCSRL1_ERROR       0x00000004U
-#define USB_TXCSRL1_UNDRN       0x00000004U
-#define USB_TXCSRL1_FIFONE      0x00000002U
-#define USB_TXCSRL1_TXRDY       0x00000001U
-
-#define USB_RXCSRL1_CLRDT       0x00000080U
-#define USB_RXCSRL1_STALLED     0x00000040U
-#define USB_RXCSRL1_STALL       0x00000020U
-#define USB_RXCSRL1_REQPKT      0x00000020U
-#define USB_RXCSRL1_FLUSH       0x00000010U
-#define USB_RXCSRL1_DATAERR     0x00000008U
-#define USB_RXCSRL1_NAKTO       0x00000008U
-#define USB_RXCSRL1_OVER        0x00000004U
-#define USB_RXCSRL1_ERROR       0x00000004U
-#define USB_RXCSRL1_FULL        0x00000002U
-#define USB_RXCSRL1_RXRDY       0x00000001U
-
-#define USB_CSRL0_NAKTO         0x00000080U
-#define USB_CSRL0_SETENDC       0x00000080U
-#define USB_CSRL0_STATUS        0x00000040U
-#define USB_CSRL0_RXRDYC        0x00000040U
-#define USB_CSRL0_REQPKT        0x00000020U
-#define USB_CSRL0_STALL         0x00000020U
-#define USB_CSRL0_SETEND        0x00000010U
-#define USB_CSRL0_ERROR         0x00000010U
-#define USB_CSRL0_DATAEND       0x00000008U
-#define USB_CSRL0_SETUP         0x00000008U
-#define USB_CSRL0_STALLED       0x00000004U
-#define USB_CSRL0_TXRDY         0x00000002U
-#define USB_CSRL0_RXRDY         0x00000001U
-
-#define USB_TYPE0_SPEED_M       0x000000C0U
-#define USB_TYPE0_SPEED_HIGH    0x00000040U
-#define USB_TYPE0_SPEED_FULL    0x00000080U
-#define USB_TYPE0_SPEED_LOW     0x000000C0U
-
-#define USB_TXTYPE1_SPEED_M     0x000000C0U
-#define USB_TXTYPE1_SPEED_DFLT  0x00000000U
-#define USB_TXTYPE1_SPEED_HIGH  0x00000040U
-#define USB_TXTYPE1_SPEED_FULL  0x00000080U
-#define USB_TXTYPE1_SPEED_LOW   0x000000C0U
-#define USB_TXTYPE1_PROTO_M     0x00000030U
-#define USB_TXTYPE1_PROTO_CTRL  0x00000000U
-#define USB_TXTYPE1_PROTO_ISOC  0x00000010U
-#define USB_TXTYPE1_PROTO_BULK  0x00000020U
-#define USB_TXTYPE1_PROTO_INT   0x00000030U
-#define USB_TXTYPE1_TEP_M       0x0000000FU
-#define USB_TXTYPE1_TEP_S       0U
-
-#define USB_LPMATTR_ENDPT_M     0x0000F000U
-#define USB_LPMATTR_RMTWAK      0x00000100U
-#define USB_LPMATTR_HIRD_M      0x000000F0U
-#define USB_LPMATTR_LS_M        0x0000000FU
-#define USB_LPMATTR_LS_L1       0x00000001U
-#define USB_LPMATTR_ENDPT_S     12U
-#define USB_LPMATTR_HIRD_S      4U
-
-#define USB_LPMCNTRL_LPMRES	0x00000002U
-#define USB_LPMCNTRL_LPMXMT	0x00000001U
-#define USB_LPMCNTRL_ENABLE	0x00000006U
-#define USB_LPMCNTRL_DISABLE	0x00000000U
-
-#define USB_INTCTRL_ALL         0x000003FFU
-#define USB_INTCTRL_STATUS      0x000000FFU
-#define USB_INTCTRL_VBUS_ERR    0x00000080U
-#define USB_INTCTRL_SESSION     0x00000040U
-#define USB_INTCTRL_SESSION_END 0x00000040U
-#define USB_INTCTRL_DISCONNECT  0x00000020U
-#define USB_INTCTRL_CONNECT     0x00000010U
-#define USB_INTCTRL_SOF         0x00000008U
-#define USB_INTCTRL_BABBLE      0x00000004U
-#define USB_INTCTRL_RESET       0x00000004U
-#define USB_INTCTRL_RESUME      0x00000002U
-#define USB_INTCTRL_SUSPEND     0x00000001U
-#define USB_INTCTRL_MODE_DETECT 0x00000200U
-#define USB_INTCTRL_POWER_FAULT 0x00000100U
-
-#define USB_INTEP_ALL           0xFFFFFFFFU
-#define USB_INTEP_HOST_IN       0xFFFE0000U
-#define USB_INTEP_HOST_IN_15    0x80000000U
-#define USB_INTEP_HOST_IN_14    0x40000000U
-#define USB_INTEP_HOST_IN_13    0x20000000U
-#define USB_INTEP_HOST_IN_12    0x10000000U
-#define USB_INTEP_HOST_IN_11    0x08000000U
-#define USB_INTEP_HOST_IN_10    0x04000000U
-#define USB_INTEP_HOST_IN_9     0x02000000U
-#define USB_INTEP_HOST_IN_8     0x01000000U
-#define USB_INTEP_HOST_IN_7     0x00800000U
-#define USB_INTEP_HOST_IN_6     0x00400000U
-#define USB_INTEP_HOST_IN_5     0x00200000U
-#define USB_INTEP_HOST_IN_4     0x00100000U
-#define USB_INTEP_HOST_IN_3     0x00080000U
-#define USB_INTEP_HOST_IN_2     0x00040000U
-#define USB_INTEP_HOST_IN_1     0x00020000U
-
-#define USB_INTEP_DEV_OUT       0xFFFE0000U
-#define USB_INTEP_DEV_OUT_15    0x80000000U
-#define USB_INTEP_DEV_OUT_14    0x40000000U
-#define USB_INTEP_DEV_OUT_13    0x20000000U
-#define USB_INTEP_DEV_OUT_12    0x10000000U
-#define USB_INTEP_DEV_OUT_11    0x08000000U
-#define USB_INTEP_DEV_OUT_10    0x04000000U
-#define USB_INTEP_DEV_OUT_9     0x02000000U
-#define USB_INTEP_DEV_OUT_8     0x01000000U
-#define USB_INTEP_DEV_OUT_7     0x00800000U
-#define USB_INTEP_DEV_OUT_6     0x00400000U
-#define USB_INTEP_DEV_OUT_5     0x00200000U
-#define USB_INTEP_DEV_OUT_4     0x00100000U
-#define USB_INTEP_DEV_OUT_3     0x00080000U
-#define USB_INTEP_DEV_OUT_2     0x00040000U
-#define USB_INTEP_DEV_OUT_1     0x00020000U
-
-#define USB_INTEP_HOST_OUT      0x0000FFFEU
-#define USB_INTEP_HOST_OUT_15   0x00008000U
-#define USB_INTEP_HOST_OUT_14   0x00004000U
-#define USB_INTEP_HOST_OUT_13   0x00002000U
-#define USB_INTEP_HOST_OUT_12   0x00001000U
-#define USB_INTEP_HOST_OUT_11   0x00000800U
-#define USB_INTEP_HOST_OUT_10   0x00000400U
-#define USB_INTEP_HOST_OUT_9    0x00000200U
-#define USB_INTEP_HOST_OUT_8    0x00000100U
-#define USB_INTEP_HOST_OUT_7    0x00000080U
-#define USB_INTEP_HOST_OUT_6    0x00000040U
-#define USB_INTEP_HOST_OUT_5    0x00000020U
-#define USB_INTEP_HOST_OUT_4    0x00000010U
-#define USB_INTEP_HOST_OUT_3    0x00000008U
-#define USB_INTEP_HOST_OUT_2    0x00000004U
-#define USB_INTEP_HOST_OUT_1    0x00000002U
-
-#define USB_INTEP_DEV_IN        0x0000FFFEU
-#define USB_INTEP_DEV_IN_15     0x00008000U
-#define USB_INTEP_DEV_IN_14     0x00004000U
-#define USB_INTEP_DEV_IN_13     0x00002000U
-#define USB_INTEP_DEV_IN_12     0x00001000U
-#define USB_INTEP_DEV_IN_11     0x00000800U
-#define USB_INTEP_DEV_IN_10     0x00000400U
-#define USB_INTEP_DEV_IN_9      0x00000200U
-#define USB_INTEP_DEV_IN_8      0x00000100U
-#define USB_INTEP_DEV_IN_7      0x00000080U
-#define USB_INTEP_DEV_IN_6      0x00000040U
-#define USB_INTEP_DEV_IN_5      0x00000020U
-#define USB_INTEP_DEV_IN_4      0x00000010U
-#define USB_INTEP_DEV_IN_3      0x00000008U
-#define USB_INTEP_DEV_IN_2      0x00000004U
-#define USB_INTEP_DEV_IN_1      0x00000002U
-
-#define USB_INTEP_0             0x00000001U
-
-#define USB_UNDEF_SPEED         0x80000000U
-#define USB_HIGH_SPEED          0x00000002U
-#define USB_FULL_SPEED          0x00000001U
-#define USB_LOW_SPEED           0x00000000U
-
-#define USB_HOST_IN_STATUS      0x114F0000U
-#define USB_HOST_IN_PID_ERROR   0x10000000U
-#define USB_HOST_IN_NOT_COMP    0x01000000U
-#define USB_HOST_IN_STALL       0x00400000U
-#define USB_HOST_IN_DATA_ERROR  0x00080000U
-
-#define USB_HOST_IN_NAK_TO      0x00080000U
-
-#define USB_HOST_IN_ERROR       0x00040000U
-
-#define USB_HOST_IN_FIFO_FULL   0x00020000U
-#define USB_HOST_IN_PKTRDY      0x00010000U
-#define USB_HOST_OUT_STATUS     0x000000A7U
-#define USB_HOST_OUT_NAK_TO     0x00000080U
-
-#define USB_HOST_OUT_NOT_COMP   0x00000080U
-
-#define USB_HOST_OUT_STALL      0x00000020U
-#define USB_HOST_OUT_ERROR      0x00000004U
-
-#define USB_HOST_OUT_FIFO_NE    0x00000002U
-#define USB_HOST_OUT_PKTPEND    0x00000001U
-#define USB_HOST_EP0_NAK_TO     0x00000080U
-
-#define USB_HOST_EP0_STATUS     0x00000040U
-#define USB_HOST_EP0_ERROR      0x00000010U
-
-#define USB_HOST_EP0_RX_STALL   0x00000004U
-#define USB_HOST_EP0_RXPKTRDY   0x00000001U
-#define USB_DEV_RX_PID_ERROR    0x01000000U
-
-#define USB_DEV_RX_SENT_STALL   0x00400000U
-#define USB_DEV_RX_DATA_ERROR   0x00080000U
-#define USB_DEV_RX_OVERRUN      0x00040000U
-
-#define USB_DEV_RX_FIFO_FULL    0x00020000U
-#define USB_DEV_RX_PKT_RDY      0x00010000U
-#define USB_DEV_TX_NOT_COMP     0x00000080U
-
-#define USB_DEV_TX_SENT_STALL   0x00000020U
-#define USB_DEV_TX_UNDERRUN     0x00000004U
-#define USB_DEV_TX_FIFO_NE      0x00000002U
-#define USB_DEV_TX_TXPKTRDY     0x00000001U
-#define USB_DEV_EP0_SETUP_END   0x00000010U
-
-#define USB_DEV_EP0_SENT_STALL  0x00000004U
-#define USB_DEV_EP0_IN_PKTPEND  0x00000002U
-#define USB_DEV_EP0_OUT_PKTRDY  0x00000001U
-
-#define USB_EP_AUTO_SET         0x00000001U
-#define USB_EP_AUTO_REQUEST     0x00000002U
-#define USB_EP_AUTO_CLEAR       0x00000004U
-#define USB_EP_DMA_MODE_0       0x00000008U
-#define USB_EP_DMA_MODE_1       0x00000010U
-#define USB_EP_DIS_NYET         0x00000020U
-
-
-#define USB_EP_MODE_ISOC        0x00000000U
-#define USB_EP_MODE_BULK        0x00000100U
-#define USB_EP_MODE_INT         0x00000200U
-#define USB_EP_MODE_CTRL        0x00000300U
-#define USB_EP_MODE_MASK        0x00000300U
-#define USB_EP_SPEED_LOW        0x00000000U
-#define USB_EP_SPEED_FULL       0x00001000U
-#define USB_EP_SPEED_HIGH       0x00004000U
-#define USB_EP_HOST_IN          0x00000000U
-#define USB_EP_HOST_OUT         0x00002000U
-#define USB_EP_DEV_IN           0x00002000U
-#define USB_EP_DEV_OUT          0x00000000U
-
-#define USB_HOST_PWRFLT_LOW     0x00000010U
-#define USB_HOST_PWRFLT_HIGH    0x00000030U
-#define USB_HOST_PWRFLT_EP_NONE 0x00000000U
-#define USB_HOST_PWRFLT_EP_TRI  0x00000140U
-#define USB_HOST_PWRFLT_EP_LOW  0x00000240U
-#define USB_HOST_PWRFLT_EP_HIGH 0x00000340U
-#define USB_HOST_PWREN_MAN_LOW  0x00000000U
-#define USB_HOST_PWREN_MAN_HIGH 0x00000001U
-#define USB_HOST_PWREN_AUTOLOW  0x00000002U
-#define USB_HOST_PWREN_AUTOHIGH 0x00000003U
-#define USB_HOST_PWREN_FILTER   0x00010000U
-
-#define USB_HOST_LPM_RMTWAKE    0x00000100U
-#define USB_HOST_LPM_L1         0x00000001U
-#define USB_DEV_LPM_NAK         0x00000010U
-#define USB_DEV_LPM_NONE        0x00000000U
-#define USB_DEV_LPM_EN          0x0000000cU
-#define USB_DEV_LPM_EXTONLY     0x00000004U
-#define USB_DEV_LPM_LS_RMTWAKE  0x00000100U
-#define USB_DEV_LPM_LS_L1       0x00000001U
-#define USB_INTLPM_ERROR        0x00000020U
-#define USB_INTLPM_RESUME       0x00000010U
-#define USB_INTLPM_INCOMPLETE   0x00000008U
-#define USB_INTLPM_ACK          0x00000004U
-#define USB_INTLPM_NYET         0x00000002U
-#define USB_INTLPM_STALL        0x00000001U
-
-#define MAX_NAK_LIMIT           31U
-#define DISABLE_NAK_LIMIT       0U
-
-#define MAX_PACKET_SIZE_EP0     64U
-#define USB_EP_0                0U
-#define USB_EP_1                1U
-#define USB_EP_2                2U
-#define USB_EP_3                3U
-#define USB_EP_4                4U
-#define USB_EP_5                5U
-#define NUM_USB_EP              6U
-#define IndexToUSBEP(x)         ((x))
-#define USBEPToIndex(x)         ((x))
-
-#define USB_FIFO_SZ_8           0x00000000U
-#define USB_FIFO_SZ_16          0x00000001U
-#define USB_FIFO_SZ_32          0x00000002U
-#define USB_FIFO_SZ_64          0x00000003U
-#define USB_FIFO_SZ_128         0x00000004U
-#define USB_FIFO_SZ_256         0x00000005U
-#define USB_FIFO_SZ_512         0x00000006U
-#define USB_FIFO_SZ_1024        0x00000007U
-#define USB_FIFO_SZ_2048        0x00000008U
-#define USBFIFOSizeToBytes(x)   (8 << (x))
-
-#define USB_TRANS_OUT           0x00000102U
-#define USB_TRANS_IN            0x00000102U
-#define USB_TRANS_IN_LAST       0x0000010aU
-#define USB_TRANS_SETUP         0x0000110aU
-#define USB_TRANS_STATUS        0x00000142U
-
-#define USB_DUAL_MODE_HOST      0x00000001U
-#define USB_DUAL_MODE_DEVICE    0x00000081U
-#define USB_DUAL_MODE_NONE      0x00000080U
-#define USB_OTG_MODE_ASIDE_HOST 0x0000001dU
-#define USB_OTG_MODE_ASIDE_NPWR 0x00000001U
-#define USB_OTG_MODE_ASIDE_SESS 0x00000009U
-#define USB_OTG_MODE_ASIDE_AVAL 0x00000011U
-#define USB_OTG_MODE_ASIDE_DEV  0x00000019U
-#define USB_OTG_MODE_BSIDE_HOST 0x0000009dU
-#define USB_OTG_MODE_BSIDE_DEV  0x00000099U
-#define USB_OTG_MODE_BSIDE_NPWR 0x00000081U
-#define USB_OTG_MODE_NONE       0x00000080U
-
-#define USB_DMA_INT_CH8         0x00000080U
-#define USB_DMA_INT_CH7         0x00000040U
-#define USB_DMA_INT_CH6         0x00000020U
-#define USB_DMA_INT_CH5         0x00000010U
-#define USB_DMA_INT_CH4         0x00000008U
-#define USB_DMA_INT_CH3         0x00000004U
-#define USB_DMA_INT_CH2         0x00000002U
-#define USB_DMA_INT_CH1         0x00000001U
-#define USB_DMA_EP_CFG_TX	0x00000001U
-#define USB_DMA_EP_CFG_RX_DEV	0x00000002U
-#define USB_DMA_EP_CFG_RX_HOST	0x00000004U
-#define USB_DMA_EP_TX_MSK	0x94U
-#define USB_DMA_EP_RX_DEV_MSK	0xA8U
-#define USB_DMA_EP_RX_HOST_MSK	0xE8U
-#define USB_DMA_STATUS_ERROR    0x00000100U
-
-#define USB_MODE_HOST_VBUS      0x00000004U
-#define USB_MODE_HOST           0x00000002U
-#define USB_MODE_DEV_VBUS       0x00000005U
-#define USB_MODE_DEV            0x00000003U
-#define USB_MODE_OTG            0x00000000U
-
-#define USB_RX_EPSTATUS_SHIFT   16U
-#define USB_INTEP_RX_SHIFT      16U
-
-#define USB_DMA_CFG_START	0x00000001U
-#define USB_DMA_CFG_START_NO	0x00000000U
-#define USB_DMA_CFG_DIR_WR	0x00000000U
-#define USB_DMA_CFG_DIR_RD	0x00000002U
-#define USB_DMA_CFG_MODE_0	0x00000000U
-#define USB_DMA_CFG_MODE_1	0x00000004U
-#define USB_DMA_CFG_IE_DIS	0x00000000U
-#define USB_DMA_CFG_IE_EN	0x00000008U
-#define USB_DMA_CFG_EP_1	0x00000010U
-#define USB_DMA_CFG_EP_2	0x00000020U
-#define USB_DMA_CFG_EP_3	0x00000030U
-#define USB_DMA_CFG_EP_4	0x00000040U
-#define USB_DMA_CFG_EP_5	0x00000050U
-#define USB_DMA_CFG_BURST_NONE	0x00000000U
-#define USB_DMA_CFG_BURST_4	0x00000200U
-#define USB_DMA_CFG_BURST_8	0x00000400U
-#define USB_DMA_CFG_BURST_16	0x00000600U
-#define USB_DMA_CFG_MODE_MSK	0x00000004U
-#define USB_DMA_CFG_EP_POS	0x00000004U
-#define USB_DMA_CFG_EP_MSK	0x000000F0U
-#define USB_DMA_CH_ERR_MSK	0x100U
-/**
-  * @}
-  */
-
-/** @addtogroup USB_Public_Functions
-  * @{
-  */
-
-/** @addtogroup USB_Public_Functions_Group1
-  * @{
-  */
-/* Base functions */
-extern uint32_t ald_usb_frame_number_get(void);
-extern void ald_usb_otg_session_request(bool start);
-extern uint32_t ald_usb_mode_get(void);
-extern void ald_usb_high_speed_enable(bool enable);
-extern uint32_t ald_usb_device_speed_get(void);
-extern uint32_t ald_usb_num_ep_get( void);
-extern void ald_usb_control_reset(void);
-extern void ald_usb_clock_output(void);
-extern int ald_usb_eye_diagram_start(uint8_t *buf, uint16_t len);
-/**
-  * @}
-  */
-
-/** @addtogroup USB_Public_Functions_Group2
-  * @{
-  */
-/* Device functions */
-extern uint8_t ald_usb_dev_get_addr(void);
-extern void ald_usb_dev_set_addr(uint8_t addr);
-extern void ald_usb_dev_connect(void);
-extern void ald_usb_dev_disconnect(void);
-extern void ald_usb_dev_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t flags);
-extern void ald_usb_dev_ep_get_config(uint32_t ep_idx, uint32_t *p_max, uint32_t *flags);
-extern void ald_usb_dev_ep_data_ack(uint32_t ep_idx, bool last);
-extern void ald_usb_dev_ep_stall(uint32_t ep_idx, uint32_t flags);
-extern void ald_usb_dev_ep_stall_clear(uint32_t ep_idx, uint32_t flags);
-extern void ald_usb_dev_ep_status_clear(uint32_t ep_idx, uint32_t flags);
-/**
-  * @}
-  */
-
-/** @addtogroup USB_Public_Functions_Group3
-  * @{
-  */
-/* Host functions */
-extern uint32_t ald_usb_host_addr_get(uint32_t ep_idx, uint32_t flags);
-extern void ald_usb_host_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags);
-extern void ald_usb_host_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags);
-extern void ald_usb_host_ep_data_ack(uint32_t ep_idx);
-extern void ald_usb_host_ep_data_toggle(uint32_t ep_idx, bool toggle, uint32_t flags);
-extern void ald_usb_host_ep_status_clear(uint32_t ep_idx, uint32_t flags);
-extern uint32_t ald_usb_host_hub_addr_get(uint32_t ep_idx, uint32_t flags);
-extern void ald_usb_host_hub_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags);
-extern void ald_usb_host_pwr_disable(void);
-extern void ald_usb_host_pwr_enable(void);
-extern void ald_usb_host_pwr_config(uint32_t flags);
-extern void ald_usb_host_pwr_fault_disable(void);
-extern void ald_usb_host_pwr_fault_enable(void);
-extern void ald_usb_host_request_in(uint32_t ep_idx);
-extern void ald_usb_host_request_in_clear(uint32_t ep_idx);
-extern void ald_usb_host_request_status(void);
-extern void ald_usb_host_reset(bool start);
-extern void ald_usb_host_resume(bool start);
-extern void ald_usb_host_suspend(void);
-extern uint32_t ald_usb_host_speed_get(void);
-extern void ald_usb_host_ep_speed_set(uint32_t ep_idx, uint32_t flags);
-extern void ald_usb_host_ep_ping(uint32_t ep_idx, bool enable);
-/**
-  * @}
-  */
-
-/** @addtogroup USB_Public_Functions_Group4
-  * @{
-  */
-/* Endpoint functions */
-extern uint32_t ald_usb_ep_data_avail(uint32_t ep_idx);
-extern int32_t ald_usb_ep_data_get(uint32_t ep_idx, uint8_t *data, uint32_t *size);
-extern int32_t ald_usb_ep_data_put(uint32_t ep_idx, uint8_t *data, uint32_t size);
-extern int32_t ald_usb_ep_data_send(uint32_t ep_idx, uint32_t tx_type);
-extern void ald_usb_ep_data_toggle_clear(uint32_t ep_idx, uint32_t flags);
-extern void ald_usb_ep_req_packet_count(uint32_t ep_idx, uint32_t count);
-extern uint32_t ald_usb_ep_status(uint32_t ep_idx);
-extern void ald_usb_ep_dma_config(uint32_t ep_idx, uint32_t flag, type_func_t en);
-/**
-  * @}
-  */
-
-/** @addtogroup USB_Public_Functions_Group5
-  * @{
-  */
-/* FIFO functions */
-extern uint32_t ald_usb_fifo_addr_get(uint32_t ep_idx);
-extern void ald_usb_fifo_config_get(uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags);
-extern void ald_usb_fifo_config_set(uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags);
-extern void ald_usb_fifo_flush(uint32_t ep_idx, uint32_t flags);
-/**
-  * @}
-  */
-
-/** @addtogroup USB_Public_Functions_Group6
-  * @{
-  */
-/* Interrupt functions */
-extern void ald_usb_int_disable(uint32_t flags);
-extern void ald_usb_int_enable(uint32_t flags);
-extern uint32_t ald_usb_int_status_get(void);
-extern void ald_usb_int_disable_ep(uint32_t flags);
-extern void ald_usb_int_enable_ep(uint32_t flags);
-extern uint32_t ald_usb_int_status_ep_get(void);
-extern void ald_usb_int_register(void);
-extern void ald_usb_int_unregister(void);
-extern uint32_t ald_usb_int_num_get(void);
-/**
-  * @}
-  */
-
-/** @addtogroup USB_Public_Functions_Group7
-  * @{
-  */
-/* DMA functions */
-extern void ald_usb_dma_channel_config(uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl);
-extern void ald_usb_dma_mult_recv_start(uint32_t ep_idx);
-extern void ald_usb_dma_channel_start(uint8_t ch);
-extern void ald_usb_dma_channel_stop(uint8_t ch);
-extern uint32_t ald_usb_dma_get_interrupt_flag(void);
-extern uint32_t ald_usb_dma_get_channel_error(uint8_t ch);
-extern void ald_usb_dma_clear_channel_error(uint8_t ch);
-/**
-  * @}
-  */
-
-/** @addtogroup USB_Public_Functions_Group8
-  * @{
-  */
-/* LPM functions */
-extern void ald_usb_host_lpm_send(uint32_t addr, uint32_t ep_idx);
-extern void ald_usb_host_lpm_config(uint32_t resume_time, uint32_t config);
-extern uint32_t ald_usb_lpm_remote_wake_is_enable(void);
-extern void ald_usb_host_lpm_resume(void);
-extern void ald_usb_dev_lpm_remote_wake(void);
-extern void ald_usb_dev_lpm_config(uint32_t config);
-extern void ald_usb_dev_lpm_enable(void);
-extern void ald_usb_dev_lpm_disable(void);
-extern uint32_t ald_usb_lpm_link_status_get(void);
-extern uint32_t ald_usb_lpm_ep_get(void);
-extern uint32_t ald_usb_lpm_int_status_get(void);
-extern void ald_usb_lpm_int_disable(uint32_t ints);
-extern void ald_usb_lpm_int_enable(uint32_t ints);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-#endif

demo/es32/Drivers/ALD/ES32F36xx/Include/ald_wdt.h

@@ -1,132 +0,0 @@
-/**
- *********************************************************************************
- *
- * @file    ald_wdt.h
- * @brief   Header file of WDT module driver.
- *
- * @version V1.0
- * @date    18 Dec 2019
- * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          18 Dec 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
- */
-
-#ifndef __ALD_WDT_H__
-#define __ALD_WDT_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "utils.h"
-
-/** @addtogroup ES32FXXX_ALD
- * @{
- */
-
-/** @addtogroup WDT
- * @{
- */
-
-/** @defgroup WDT_Public_Types WDT Public Types
- * @{
- */
-
-/**
-  * @brief Wwdt no dog window
-  */
-typedef enum {
-	WWDT_WIN_25 = 0x0U,	/**< No dog window size: 25% */
-	WWDT_WIN_50 = 0x1U,	/**< No dog window size: 50% */
-	WWDT_WIN_75 = 0x2U,	/**< No dog window size: 75% */
-	WWDT_WIN_00 = 0x3U,	/**< No dog window size: 0% */
-} wwdt_win_t;
-
-/**
- * @}
- */
-
-/**
- * @defgroup WDT_Private_Macros WDT Private Macros
- * @{
- */
-#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);}
-#define WWDT_LOCK()   {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);}
-#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);}
-#define IWDT_LOCK()   {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);}
-
-/**
- * @}
- */
-
-/**
- * @addtogroup WDT_Private_Macros WDT Private Macros
- * @{
- */
-#define IS_WWDT_WIN_TYPE(x)     ((x == WWDT_WIN_25) || \
-                                 (x == WWDT_WIN_50) || \
-                                 (x == WWDT_WIN_75) || \
-                                 (x == WWDT_WIN_00))
-#define IS_FUNC_STATE(x)	(((x) == DISABLE) || \
-				 ((x) == ENABLE))
-/**
- * @}
- */
-
-/** @addtogroup WWDT_Public_Functions
- * @{
- */
-void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt);
-void ald_wwdt_start(void);
-uint32_t ald_wwdt_get_value(void);
-it_status_t ald_wwdt_get_flag_status(void);
-void ald_wwdt_clear_flag_status(void);
-void ald_wwdt_feed_dog(void);
-/**
- * @}
- */
-
-/** @addtogroup IWDT_Public_Functions
- * @{
- */
-void ald_iwdt_init(uint32_t load, type_func_t interrupt);
-void ald_iwdt_start(void);
-uint32_t ald_iwdt_get_value(void);
-it_status_t ald_iwdt_get_flag_status(void);
-void ald_iwdt_clear_flag_status(void);
-void ald_iwdt_feed_dog(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALD_WDT_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/type.h

@@ -1,138 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    type.h
-  * @brief   define type
-  *
-  * @version V1.0
-  * @date    17 Apr 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          17 Apr 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __TYPE_H__
-#define __TYPE_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-
-#if defined (__CC_ARM)
-#define __INLINE__		__inline
-#define __STATIC_INLINE__	static __inline
-#else
-#define __INLINE__		inline
-#define __STATIC_INLINE__	static inline
-#endif
-
-#define __isr__
-
-typedef enum {
-	RESET = 0x0U,
-	SET   = 0x1U,
-} flag_status_t, it_status_t;
-
-typedef enum {
-	BIT_RESET = 0x0U,
-	BIT_SET   = 0x1U,
-} bit_status_t;
-
-typedef enum {
-	DISABLE = 0x0U,
-	ENABLE  = 0x1U,
-} type_func_t;
-#define IS_FUNC_STATE(x)	(((x) == DISABLE) || ((x) == ENABLE))
-
-typedef enum {
-	FALSE = 0x0U,
-	TRUE  = 0x1U,
-} type_bool_t;
-
-typedef enum {
-	UNLOCK = 0x0U,
-	LOCK   = 0x1U,
-} lock_state_t;
-#define IS_LOCK_STATE(x)	(((x) == UNLOCK) || ((x) == LOCK))
-
-
-#define BIT(x)			((1U << (x)))
-#define BITS(s, e)		((0xffffffffU << (s)) & (0xffffffffU >> (31 - (e))))
-#define SET_BIT(reg, bit)	((reg) |= (bit))
-#define CLEAR_BIT(reg, bit)	((reg) &= ~(bit))
-#define READ_BIT(reg, bit)	((reg) & (bit))
-#define READ_BITS(reg, msk, s)	(((reg) & (msk)) >> (s))
-#define CLEAR_REG(reg)		((reg) = (0x0))
-#define WRITE_REG(reg, val)	((reg) = (val))
-#define READ_REG(reg)		((reg))
-#define MODIFY_REG(reg, clearmask, setmask)	\
-	WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask)))
-#define UNUSED(x)	((void)(x))
-
-#ifdef USE_ASSERT
-#define assert_param(x)			\
-do {					\
-	if (!(x)) {			\
-		__disable_irq();	\
-		while (1)		\
-			;		\
-	}				\
-} while (0)
-#else
-#define assert_param(x)
-#endif
-
-
-#define PER_MEM_BASE         ((uint32_t) 0x40000000UL)	/* PER base address  */
-#define RAM_MEM_BASE         ((uint32_t) 0x20000000UL)	/* RAM base address  */
-#define BITBAND_PER_BASE     ((uint32_t) 0x42000000UL)	/* Peripheral Address Space bit-band area */
-#define BITBAND_RAM_BASE     ((uint32_t) 0x22000000UL)	/* SRAM Address Space bit-band area */
-
-__STATIC_INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val)
-{
-	uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2);
-	*((volatile uint32_t *)tmp) = (uint32_t)val;
-}
-
-__STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val)
-{
-	uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2);
-	*((volatile uint32_t *)tmp) = (uint32_t)val;
-}
-
-#if defined ( __GNUC__ )
-	#ifndef __weak
-		#define __weak   __attribute__((weak))
-	#endif	/* __weak */
-	#ifndef __packed
-		#define __packed __attribute__((__packed__))
-	#endif	/* __packed */
-#endif /* __GNUC__ */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __TYPE_H__ */

demo/es32/Drivers/ALD/ES32F36xx/Include/utils.h

@@ -1,208 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    utils.h
-  * @brief   This file contains the Utilities functions/types for the driver.
-  *
-  * @version V1.0
-  * @date    07 Nov 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          07 Nov 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#ifndef __UTILS_H__
-#define __UTILS_H__
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include <stdlib.h>
-#include "type.h"
-#ifdef ES32F36xx
-#include "es32f36xx.h"
-#elif ES32F39xx
-#include "es32f39xx.h"
-#elif ES32F336x
-#include "es32f336x.h"
-#endif
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup UTILS
-  * @{
-  */
-
-/** @defgroup ALD_Public_Types Public Types
-  * @{
-  */
-/**
-  * @brief  SysTick interval
-  */
-extern uint32_t __systick_interval;
-
-/**
-  * @brief  ALD Status structures definition
-  */
-typedef enum {
-	OK      = 0x0U,	/**< OK */
-	ERROR   = 0x1U,	/**< ERROR */
-	BUSY    = 0x2U,	/**< BUSY */
-	TIMEOUT = 0x3U,	/**< TIMEOUT */
-} ald_status_t;
-
-/**
-  * @brief NVIC Preemption Priority Group
-  */
-typedef enum {
-	NVIC_PRIORITY_GROUP_0 = 0x7U,	/**< 0-bits for pre-emption priority 4-bits for subpriority */
-	NVIC_PRIORITY_GROUP_1 = 0x6U,	/**< 1-bits for pre-emption priority 3-bits for subpriority */
-	NVIC_PRIORITY_GROUP_2 = 0x5U,	/**< 2-bits for pre-emption priority 2-bits for subpriority */
-	NVIC_PRIORITY_GROUP_3 = 0x4U,	/**< 3-bits for pre-emption priority 1-bits for subpriority */
-	NVIC_PRIORITY_GROUP_4 = 0x3U,	/**< 4-bits for pre-emption priority 0-bits for subpriority */
-} nvic_priority_group_t;
-
-/**
-  * @brief  SysTick interval definition
-  */
-typedef enum {
-	SYSTICK_INTERVAL_1MS    = 1000U,	/**< Interval is 1ms */
-	SYSTICK_INTERVAL_10MS   = 100U,		/**< Interval is 10ms */
-	SYSTICK_INTERVAL_100MS  = 10U,		/**< Interval is 100ms */
-	SYSTICK_INTERVAL_1000MS = 1U,		/**< Interval is 1s */
-} systick_interval_t;
-/**
-  * @}
-  */
-
-/** @defgroup ALD_Public_Macros Public Macros
-  * @{
-  */
-#define ALD_MAX_DELAY	0xFFFFFFFFU
-#define IS_BIT_SET(reg, bit)	(((reg) & (bit)) != RESET)
-#define IS_BIT_CLR(reg, bit)	(((reg) & (bit)) == RESET)
-#define RESET_HANDLE_STATE(x)	((x)->state = 0)
-#define __LOCK(x)			\
-do {					\
-	if ((x)->lock == LOCK) {	\
-		return BUSY;		\
-	}				\
-	else {				\
-		(x)->lock = LOCK;	\
-	}				\
-} while (0)
-#define __UNLOCK(x)			\
-do {					\
-	(x)->lock = UNLOCK;		\
-} while (0)
-#define ALD_PANIC() 	\
-do {			\
-	while (1)	\
-		;	\
-} while (0)
-/**
-  * @}
-  */
-
-/** @defgroup ALD_Private_Macros Private Macros
-  * @{
-  */
-#define MCU_UID0_ADDR	0x000803E0U
-#define MCU_UID1_ADDR	0x000803E8U
-#define MCU_UID2_ADDR	0x000803ECU
-#define MCU_CHIPID_ADDR	0x000803F8U
-#define DWT_CR		*(uint32_t *)0xE0001000U
-#define DWT_CYCCNT	*(volatile uint32_t *)0xE0001004U
-#define DEM_CR		*(uint32_t *)0xE000EDFCU
-#define DEM_CR_TRCENA	(1U << 24)
-#define DWT_CR_CYCCNTEA	(1U << 0)
-#define IS_PREEMPT_PRIO(x)	((x) < 16)
-#define IS_SUB_PRIO(x)		((x) < 16)
-#define IS_SYSTICK_INTERVAL(x)	(((x) == SYSTICK_INTERVAL_1MS)   || \
-                                 ((x) == SYSTICK_INTERVAL_10MS)  || \
-                                 ((x) == SYSTICK_INTERVAL_100MS) || \
-                                 ((x) == SYSTICK_INTERVAL_1000MS))
-/**
-  * @}
-  */
-
-/** @addtogroup ALD_Public_Functions
-  * @{
-  */
-
-/** @addtogroup ALD_Public_Functions_Group1
-  * @{
-  */
-
-/* Initialization functions */
-void ald_cmu_init(void);
-void ald_tick_init(uint32_t prio);
-void ald_systick_interval_select(systick_interval_t value);
-
-/**
-  * @}
-  */
-
-/** @addtogroup ALD_Public_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions */
-void ald_inc_tick(void);
-void ald_systick_irq_cbk(void);      
-void ald_delay_ms(__IO uint32_t delay);
-void ald_delay_us(__IO uint32_t delay);
-uint32_t ald_get_tick(void);
-void ald_suspend_tick(void);
-void ald_resume_tick(void);
-uint32_t ald_get_ald_version(void);
-void ald_flash_wait_config(uint8_t cycle);
-ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout);
-void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status);
-void ald_mcu_timestamp_init(void);
-uint32_t ald_mcu_get_timestamp(void);
-uint32_t ald_mcu_get_cpu_id(void);
-void ald_mcu_get_uid(uint8_t *buf);
-uint32_t ald_mcu_get_chipid(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __UTILS_H__ */

demo/es32/Drivers/ALD/ES32F36xx/ReleaseNote.html

@@ -1,50 +0,0 @@
-<!doctype html>
-<html>
-<head>
-<meta charset='UTF-8'><meta name='viewport' content='width=device-width initial-scale=1'>
-<title>ReleaseNote</title></head>
-<body><h1>ES32F36xx ALD Release Note</h1>
-<h2>V1.00 2019-12-16</h2>
-<ol start='' >
-<li>First release</li>
-
-</ol>
-<h2>V1.01 2020-05-07</h2>
-<ol start='' >
-<li>Delete invalid member variables in can_filter_t-&gt;bank_number</li>
-<li>Support FIFO0/FIFO1 receiving in CAN module</li>
-<li>Add parameter check in ald_trng_init()</li>
-<li>Add ping-pong, scatter-gather modes in DMA module</li>
-<li>Add automatic control function of flash read waiting cycle</li>
-
-</ol>
-<h2>V1.02 2020-05-20</h2>
-<ol start='' >
-<li>Modify the ADC module structure member variables</li>
-<li>Update ADC module driver</li>
-<li>Support ADC1 in PIS module</li>
-<li>Add get_hclk2_clock() API in ald_cmu.h</li>
-
-</ol>
-<h2>V1.03 2020-08-24</h2>
-<ol start='' >
-<li>Add API: ald_cmu_current_clock_source_get()</li>
-<li>Add &quot;Set/Read HCLK2 Bus Frequency Division&quot; interface</li>
-<li>Modify the API related to DMA in the TIMER module</li>
-<li>Optimize the control logic of the discontinuous-scan-mode in ADC module</li>
-<li>Optimize FIFO function in UART module</li>
-<li>Add API: ald_dma_descriptor_cplt_get() in DMA module</li>
-<li>Optimize ald_dma_config_sg_per() in DMA module</li>
-<li>Fixed bug in md_usart_set_smartcard_psc()</li>
-<li>Add API to get UID/CHIPID in utils.h</li>
-<li>Add LDO12/LDO18 configure function in PMU module</li>
-<li>Delete the operation of writing SSEC register in RTC module</li>
-<li>Make the code comply with &quot;C-STAT(STDCHECKS)&quot; specification</li>
-<li>Fixed a bug in ald_can.c</li>
-<li>Fixed a bug in ald_uart.c</li>
-<li>Optimize I2S module library functions</li>
-
-</ol>
-<p>&nbsp;</p>
-</body>
-</html>

demo/es32/Drivers/ALD/ES32F36xx/ReleaseNote.md

@@ -1,39 +0,0 @@
-# ES32F36xx ALD Release Note
-
-## V1.00 2019-12-16
-
-1. First release
-
-## V1.01 2020-05-07
-
-1. Delete invalid member variables in can_filter_t->bank_number
-2. Support FIFO0/FIFO1 receiving in CAN module
-3. Add parameter check in ald_trng_init()
-4. Add ping-pong, scatter-gather modes in DMA module
-5. Add automatic control function of flash read waiting cycle
-
-## V1.02 2020-05-20
-
-1. Modify the ADC module structure member variables
-2. Update ADC module driver
-3. Support ADC1 in PIS module
-4. Add get_hclk2_clock() API in ald_cmu.h
-
-## V1.03 2020-08-24
-
-1. Add API: ald_cmu_current_clock_source_get()
-2. Add "Set/Read HCLK2 Bus Frequency Division" interface
-3. Modify the API related to DMA in the TIMER module
-4. Optimize the control logic of the discontinuous-scan-mode in ADC module
-5. Optimize FIFO function in UART module
-6. Add API: ald_dma_descriptor_cplt_get() in DMA module
-7. Optimize ald_dma_config_sg_per() in DMA module
-8. Fixed bug in md_usart_set_smartcard_psc()
-9. Add API to get UID/CHIPID in utils.h
-10. Add LDO12/LDO18 configure function in PMU module
-11. Delete the operation of writing SSEC register in RTC module
-12. Make the code comply with "C-STAT(STDCHECKS)" specification
-13. Fixed a bug in ald_can.c
-14. Fixed a bug in ald_uart.c
-15. Optimize I2S module library functions
-

demo/es32/Drivers/ALD/ES32F36xx/SConscript

@@ -1,34 +0,0 @@
-Import('ES32_SDK_ROOT')
-from building import *
-Import('esconfig')
-
-#目的1：首先生成group_ald（对应project里面的ald）
-cwd = GetCurrentDir()
-src =[]
-
-#获取Source中.c文件后将其转换成字符串
-clist=Glob('Source/*.c')
-cstr=""
-for i in clist:
-	cstr=cstr.__add__(str(i))
-	
-
-#判断conf内的.h文件在Source中有没有对应的.c文件，有.c则添加，没有.c则不添加
-if esconfig.ald_lib_src:
-    for i in set(esconfig.ald_lib_src):
-		if i in cstr:
-			src.append('Source/' + i)
-else:
-    src = Glob('Source/*.c')
-	
-#将md_.c添加进md中，将所有md_.h都include在魔法棒c/c++里面的include paths里，将USE_ASSERT加入到魔法棒c/c++里面的define中
-include_path = [cwd + '/Include']
-group_ald = DefineGroup('ald', src, depend = [''], CPPPATH = include_path,CPPDEFINES = ['USE_ASSERT','ES32F36xx'])
-
-
-#2.生成group_bsp（对应project里面的bsp）
-srcb=[]
-group_bsp = DefineGroup('bsp', srcb, depend = [''])
-
-#返回group_bsp，group_ald
-Return('group_ald','group_bsp')

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_acmp.c

@@ -1,336 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_acmp.c
-  * @brief   ACMP module driver.
-  *
-  * @version V1.0
-  * @date    26 Jun 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          26 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#include "ald_conf.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup ACMP ACMP
-  * @brief ACMP module driver
-  * @{
-  */
-#ifdef ALD_ACMP
-
-/** @defgroup ACMP_Public_Functions ACMP Public Functions
-  * @{
-  */
-
-/** @defgroup ACMP_Public_Functions_Group1 Initialization functions
-  * @brief Initialization and Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  Initializes the ACMP mode according to the specified parameters in
-  *         the acmp_init_t and create the associated handle.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_acmp_init(acmp_handle_t *hperh)
-{
-	uint32_t tmp = 0;
-
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-	assert_param(IS_ACMP_MODE_TYPE(hperh->init.mode));
-	assert_param(IS_ACMP_WARM_UP_TIME_TYPE(hperh->init.warm_time));
-	assert_param(IS_ACMP_HYSTSEL_TYPE(hperh->init.hystsel));
-	assert_param(IS_ACMP_POS_INPUT_TYPE(hperh->init.p_port));
-	assert_param(IS_ACMP_NEG_INPUT_TYPE(hperh->init.n_port));
-	assert_param(IS_ACMP_INACTVAL_TYPE(hperh->init.inactval));
-	assert_param(IS_FUNC_STATE(hperh->init.out_inv));
-	assert_param(IS_ACMP_EDGE_TYPE(hperh->init.edge));
-	assert_param(hperh->init.vdd_level < 64);
-
-	__LOCK(hperh);
-	tmp = ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) |
-		(hperh->init.inactval << ACMP_CON_INACTV_POS) | (hperh->init.hystsel << ACMP_CON_HYSTSEL_POSS));
-
-	hperh->perh->CON = tmp;
-
-	tmp |= ((hperh->init.p_port << ACMP_INPUTSEL_PSEL_POSS) | (hperh->init.n_port << ACMP_INPUTSEL_NSEL_POSS) |
-		(hperh->init.vdd_level << ACMP_INPUTSEL_VDDLVL_POSS));
-	hperh->perh->INPUTSEL = tmp;
-
-	if (hperh->init.out_inv)
-		SET_BIT(hperh->perh->CON, ACMP_CON_OUTINV_MSK);
-	else
-		CLEAR_BIT(hperh->perh->CON, ACMP_CON_OUTINV_MSK);
-
-	switch (hperh->init.edge) {
-	case ACMP_EDGE_NONE:
-		CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
-		CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
-		break;
-
-	case ACMP_EDGE_FALL:
-		SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
-		CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
-		break;
-
-	case ACMP_EDGE_RISE:
-		CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
-		SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
-		break;
-
-	case ACMP_EDGE_ALL:
-		SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
-		SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
-		break;
-
-	default:
-		break;
-	}
-
-	SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK);
-
-	tmp = 0;
-	while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0) {
-		if (tmp++ >= 600000) {
-			__UNLOCK(hperh);
-			return ERROR;
-		}
-	}
-
-	__UNLOCK(hperh);
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup ACMP_Public_Functions_Group2 Interrupt operation functions
-  * @brief ACMP Interrupt operation functions
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified ACMP interrupts.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @param  it: Specifies the ACMP interrupt sources to be enabled or disabled.
-  *         This parameter can be one of the @ref acmp_it_t.
-  * @param  state: New status
-  *           - ENABLE
-  *           - DISABLE
-  * @retval None
-  */
-void ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state)
-{
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-	assert_param(IS_ACMP_IT_TYPE(it));
-	assert_param(IS_FUNC_STATE(state));
-
-	if (state)
-		hperh->perh->IES = it;
-	else
-		hperh->perh->IEC = it;
-
-	return;
-}
-
-/**
-  * @brief  Checks whether the specified ACMP interrupt has set or not.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @param  it: Specifies the ACMP interrupt sources to be enabled or disabled.
-  *         This parameter can be one of the @ref acmp_it_t.
-  * @retval it_status_t
-  *           - SET
-  *           - RESET
-  */
-it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it)
-{
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-	assert_param(IS_ACMP_IT_TYPE(it));
-
-	if (hperh->perh->IEV & it)
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Checks whether the specified ACMP interrupt has occurred or not.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @param  flag: Specifies the ACMP interrupt source to check.
-  *         This parameter can be one of the @ref acmp_flag_t.
-  * @retval flag_status_t
-  *           - SET
-  *           - RESET
-  */
-flag_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
-{
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-	assert_param(IS_ACMP_FLAG_TYPE(flag));
-
-	if (hperh->perh->RIF & flag)
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Get the status of interrupt flag and interupt source.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *               the configuration information for the specified ACMP.
-  * @param  flag: Specifies the ACMP interrupt flag.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-flag_status_t ald_acmp_get_mask_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
-{
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-	assert_param(IS_ACMP_FLAG_TYPE(flag));
-
-	if (hperh->perh->IFM & flag)
-		return SET;
-
-	return RESET;
-}
-
-/** @brief  Clear the specified ACMP it flags.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @param  flag: specifies the it flag.
-  *         This parameter can be one of the @ref acmp_flag_t.
-  * @retval None
-  */
-void ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
-{
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-	assert_param(IS_ACMP_FLAG_TYPE(flag));
-
-	hperh->perh->IFC = flag;
-	return;
-}
-/**
-  * @}
-  */
-/** @defgroup ACMP_Public_Functions_Group3 Output value functions
-  * @brief ACMP Output value functions
-  * @{
-  */
-/**
-  * @brief  This function handles ACMP interrupt request.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @retval None
-  */
-void ald_acmp_irq_handler(acmp_handle_t *hperh)
-{
-	if ((ald_acmp_get_mask_flag_status(hperh, ACMP_FLAG_WARMUP)) == SET) {
-		ald_acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP);
-
-		if (hperh->acmp_warmup_cplt_cbk)
-			hperh->acmp_warmup_cplt_cbk(hperh);
-	}
-
-	if ((ald_acmp_get_mask_flag_status(hperh, ACMP_FLAG_EDGE)) == SET) {
-		ald_acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE);
-
-		if (hperh->acmp_edge_cplt_cbk)
-			hperh->acmp_edge_cplt_cbk(hperh);
-	}
-
-	return;
-}
-
-/**
-  * @brief  This function config acmp output.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @param  state: ENABLE/DISABLE.
-  * @retval None
-  */
-void ald_acmp_out_config(acmp_handle_t *hperh, type_func_t state)
-{
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-	assert_param(IS_FUNC_STATE(state));
-
-	if (state)
-		SET_BIT(hperh->perh->PORT, ACMP_PORT_PEN_MSK);
-	else
-		CLEAR_BIT(hperh->perh->PORT, ACMP_PORT_PEN_MSK);
-
-	return;
-}
-
-/**
-  * @brief  This function output acmp result.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @retval output value.
-  */
-uint8_t ald_acmp_out_result(acmp_handle_t *hperh)
-{
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-
-	return (READ_BIT(hperh->perh->STAT, ACMP_STAT_OUT_MSK) >> ACMP_STAT_OUT_POS);
-}
-
-/** @brief  Check whether the specified ACMP flag is set or not.
-  * @param  hperh: Pointer to a acmp_handle_t structure that contains
-  *         the configuration information for the specified ACMP module.
-  * @param  status: specifies the status to check.
-  *         This parameter can be one of the @ref acmp_status_t.
-  * @retval flag_status_t
-  *           - SET
-  *           - RESET
-  */
-flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status)
-{
-	assert_param(IS_ACMP_TYPE(hperh->perh));
-	assert_param(IS_ACMP_STATUS_TYPE(status));
-
-	if (hperh->perh->STAT & status)
-		return SET;
-
-	return RESET;
-}
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#endif /* ALD_ACMP */
-/**
-  * @}
-  */
-/**
-  * @}
-  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_bkpc.c

@@ -1,185 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_bkpc.c
-  * @brief   BKPC module driver.
-  *
-  * @version V1.0
-  * @date    15 Dec 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          15 Dec 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#include "ald_conf.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup BKPC BKPC
-  * @brief BKPC module driver
-  * @{
-  */
-#ifdef ALD_BKPC
-
-/** @defgroup BKPC_Public_Functions BKPC Public Functions
-  * @{
-  */
-
-/** @addtogroup BKPC_Public_Functions_Group1 Peripheral Control functions
-  * @brief Peripheral Control functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### Peripheral Control functions #####
-  ==============================================================================
-  [..]  This section provides functions allowing to:
-    (+) ald_bkpc_standby_wakeup_config() API can configure STANDBY wakeup.
-    (+) ald_bkpc_rtc_clock_config() API can configure RTC clock.
-    (+) ald_bkpc_tsense_clock_config() API can configure Tsense clock.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure standby wakeup in backup field
-  * @param  port: Wakeup port
-  * @param  level: HIGH/LOW.
-  * @retval None
-  */
-void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
-{
-	assert_param(IS_BKPC_WAKEUP_PORT(port));
-	assert_param(IS_BKPC_WAKEUP_LEVEL(level));
-
-	if (port == PMU_STANDBY_PORT_SEL_NONE) {
-		BKPC_UNLOCK();
-		CLEAR_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK);
-		SET_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK);
-		BKPC_LOCK();
-		return;
-	}
-
-	BKPC_UNLOCK();
-	SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK | BKPC_CR_MRST_WKPEN_MSK);
-	MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS);
-	MODIFY_REG(BKPC->CR, BKPC_CR_WKPOL_MSK, level << BKPC_CR_WKPOL_POS);
-	BKPC_LOCK();
-
-	return;
-}
-
-/**
-  * @brief  Configure rtc clock in backup field
-  * @param  clock: Clock
-  * @retval None
-  */
-void ald_bkpc_rtc_clock_config(bkpc_preh_clk_t clock)
-{
-	assert_param(IS_BKPC_PREH_CLOCK(clock));
-
-	BKPC_UNLOCK();
-	MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, clock << BKPC_PCCR_RTCCS_POSS);
-	BKPC_LOCK();
-
-	return;
-}
-
-/**
-  * @brief  Configure tsense clock in backup field
-  * @param  clock: Clock
-  * @retval None
-  */
-void ald_bkpc_tsense_clock_config(bkpc_preh_clk_t clock)
-{
-	assert_param(IS_BKPC_PREH_CLOCK(clock));
-
-	BKPC_UNLOCK();
-	MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, clock << BKPC_PCCR_TSENSECS_POSS);
-	BKPC_LOCK();
-
-	return;
-}
-/**
-  * @}
-  */
-
-/** @addtogroup BKPC_Public_Functions_Group2 IO operation functions
-  * @brief IO operation functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### IO operation functions #####
-  ==============================================================================
-  [..]  This section provides functions allowing to:
-    (+) ald_bkpc_write_ram() API can write data in backup ram.
-    (+) ald_bkpc_read_ram() API can read data from backup ram.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Write data into backup ram.
-  * @param  idx: Index of backup word.
-  * @param  value: Value which will be written to backup ram.
-  * @retval None
-  */
-void ald_bkpc_write_ram(uint8_t idx, uint32_t value)
-{
-	assert_param(IS_BKPC_RAM_IDX(idx));
-
-	RTC_UNLOCK();
-	WRITE_REG(RTC->BKPR[idx], value);
-	RTC_LOCK();
-
-	return;
-}
-
-/**
-  * @brief  Read data from backup ram.
-  * @param  idx: Index of backup word.
-  * @retval The data.
-  */
-uint32_t ald_bkpc_read_ram(uint8_t idx)
-{
-	assert_param(IS_BKPC_RAM_IDX(idx));
-
-	return READ_REG(RTC->BKPR[idx]);
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* ALD_BKPC */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_calc.c

@@ -1,81 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_calc.c
-  * @brief   CALC module driver.
-  *
-  * @version V1.0
-  * @date    26 Jun 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          26 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#include "ald_conf.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup CALC CALC
-  * @brief CALC module driver
-  * @{
-  */
-#ifdef ALD_CALC
-
-/** @defgroup CALC_Public_Functions CALC Public Functions
-  * @brief    Accelerating calculate functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### Accelerating calculate functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Square root operation.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Square root operation.
-  * @param  data: The  radicand.
-  * @retval The value of square root.
-  */
-uint32_t ald_calc_sqrt(uint32_t data)
-{
-	WRITE_REG(CALC->RDCND, data);
-	while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK));
-
-	return READ_REG(CALC->SQRTRES);
-}
-/**
-  * @}
-  */
-#endif /* ALD_CALC */
-/**
-  * @}
-  */
-/**
-  * @}
-  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_crc.c

@@ -1,535 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_crc.c
-  * @brief   CRC module driver.
-  *
-  * @version V1.0
-  * @date    18 Jun 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          18 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#include "ald_conf.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup CRC CRC
-  * @brief CRC module driver
-  * @{
-  */
-#ifdef ALD_CRC
-
-/** @addtogroup CRC_Private_Functions   CRC Private Functions
-  * @{
-  */
-void ald_crc_reset(crc_handle_t *hperh);
-#ifdef ALD_DMA
-static void crc_dma_calculate_cplt(void *arg);
-static void crc_dma_error(void *arg);
-#endif
-/**
-  * @}
-  */
-
-
-/** @defgroup CRC_Public_Functions CRC Public Functions
-  * @{
-  */
-
-/** @defgroup CRC_Public_Functions_Group1 Initialization functions
-  * @brief Initialization and Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  Initializes the CRC mode according to the specified parameters in
-  *         the crc_handle_t and create the associated handle.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_crc_init(crc_handle_t *hperh)
-{
-	uint32_t tmp = 0;
-
-	if (hperh == NULL)
-		return ERROR;
-
-	assert_param(IS_CRC(hperh->perh));
-	assert_param(IS_CRC_MODE(hperh->init.mode));
-	assert_param(IS_FUNC_STATE(hperh->init.chs_rev));
-	assert_param(IS_FUNC_STATE(hperh->init.data_inv));
-	assert_param(IS_FUNC_STATE(hperh->init.data_rev));
-	assert_param(IS_FUNC_STATE(hperh->init.chs_inv));
-
-	ald_crc_reset(hperh);
-	__LOCK(hperh);
-
-	CRC_ENABLE(hperh);
-
-	tmp = hperh->perh->CR;
-
-	tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATINV_POS) |
-		(hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) |
-		(CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) |
-		(0 << CRC_CR_BYTORD_POS));
-
-	hperh->perh->CR = tmp;
-	hperh->perh->SEED = hperh->init.seed;
-	CRC_RESET(hperh);
-
-	hperh->state = CRC_STATE_READY;
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Public_Functions_Group2 Calculate functions
-  * @brief Calculate functions
-  * @{
-  */
-
-/**
-  * @brief  Calculate the crc value of data by byte.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: The size of data to be calculate
-  * @retval result, the result of a amount data
-  */
-uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size)
-{
-	uint32_t i;
-	uint32_t ret;
-
-	assert_param(IS_CRC(hperh->perh));
-
-	if (buf == NULL || size == 0)
-		return 0;
-
-	__LOCK(hperh);
-	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS);
-	hperh->state = CRC_STATE_BUSY;
-
-	for (i = 0; i < size; i++)
-		*((volatile uint8_t *)&(hperh->perh->DATA)) = buf[i];
-
-	ret          = CRC->CHECKSUM;
-	hperh->state = CRC_STATE_READY;
-	__UNLOCK(hperh);
-
-	return ret;
-}
-
-/**
-  * @brief  Calculate the crc value of data by halfword.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: The size of data to be calculate,width is 2 bytes.
-  * @retval result, the result of a amount data
-  */
-uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size)
-{
-	uint32_t i;
-	uint32_t ret;
-
-	assert_param(IS_CRC(hperh->perh));
-
-	if (buf == NULL || size == 0)
-		return 0;
-
-	__LOCK(hperh);
-	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS);
-	hperh->state = CRC_STATE_BUSY;
-
-	for (i = 0; i < size; i++)
-		*((volatile uint16_t *)&(hperh->perh->DATA)) = buf[i];
-
-	ret          = CRC->CHECKSUM;
-	hperh->state = CRC_STATE_READY;
-	__UNLOCK(hperh);
-
-	return ret;
-}
-
-/**
-  * @brief  Calculate the crc value of data by word.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @param  buf: Pointer to data buffer
-  * @param  size: The size of data to be calculate,width is 4 bytes
-  * @retval result, the result of a amount data
-  */
-uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size)
-{
-	uint32_t i;
-	uint32_t ret;
-
-	assert_param(IS_CRC(hperh->perh));
-
-	if (buf == NULL || size == 0)
-		return 0;
-
-	__LOCK(hperh);
-	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS);
-	hperh->state = CRC_STATE_BUSY;
-
-	for (i = 0; i < size; i++)
- 		CRC->DATA = buf[i];
-
-	for (i = 0; i < 3; i++);
-
-	ret          = CRC->CHECKSUM;
-	hperh->state = CRC_STATE_READY;
-	__UNLOCK(hperh);
-
-	return ret;
-}
-
-/**
-  * @}
-  */
-
-#ifdef ALD_DMA
-/** @defgroup CRC_Public_Functions_Group3 DMA operation functions
-  * @brief DMA operation functions
-  * @{
-  */
-
-/**
-  * @brief  Calculate an amount of data used dma channel
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @param  buf: Pointer to data buffer
-  * @param  res: Pointer to result
-  * @param  size: Amount of data to be Calculate
-  * @param  channel: DMA channel as CRC transmit
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
-{
-	if (hperh->state != CRC_STATE_READY)
-		return BUSY;
-
-	if (buf == NULL || size == 0)
-		return ERROR;
-
-	__LOCK(hperh);
-	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS);
-
-	hperh->state = CRC_STATE_BUSY;
-
-	hperh->cal_buf = buf;
-	hperh->cal_res = res;
-
-	if (hperh->hdma.perh == NULL)
-		hperh->hdma.perh = DMA0;
-
-	hperh->hdma.cplt_arg = (void *)hperh;
-	hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
-	hperh->hdma.err_arg  = (void *)hperh;
-	hperh->hdma.err_cbk  = &crc_dma_error;
-
-	ald_dma_config_struct(&(hperh->hdma.config));
-	hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE;
-	hperh->hdma.config.src        = (void *)buf;
-	hperh->hdma.config.dst        = (void *)&hperh->perh->DATA;
-	hperh->hdma.config.size       = size;
-	hperh->hdma.config.src_inc    = DMA_DATA_INC_BYTE;
-	hperh->hdma.config.dst_inc    = DMA_DATA_INC_NONE;
-	hperh->hdma.config.msel       = DMA_MSEL_CRC;
-	hperh->hdma.config.msigsel    = DMA_MSIGSEL_NONE;
-	hperh->hdma.config.channel    = channel;
-	hperh->hdma.config.burst      = ENABLE;
-	ald_dma_config_basic(&(hperh->hdma));
-
-	__UNLOCK(hperh);
-	CRC_DMA_ENABLE(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Calculate an amount of data used dma channel,data width is half-word.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @param  buf: Pointer to half_word data buffer
-  * @param  res: Pointer to result
-  * @param  size: Amount of half_word data to be Calculate
-  * @param  channel: DMA channel as CRC transmit
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
-{
-	if (hperh->state != CRC_STATE_READY)
-		return BUSY;
-
-	if (buf == NULL || size == 0)
-		return ERROR;
-
-	__LOCK(hperh);
-	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS);
-
-	hperh->state = CRC_STATE_BUSY;
-
-	hperh->cal_buf = (uint8_t *)buf;
-	hperh->cal_res = res;
-
-	if (hperh->hdma.perh == NULL)
-		hperh->hdma.perh = DMA0;
-
-	hperh->hdma.cplt_arg = (void *)hperh;
-	hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
-	hperh->hdma.err_arg  = (void *)hperh;
-	hperh->hdma.err_cbk  = &crc_dma_error;
-
-	ald_dma_config_struct(&(hperh->hdma.config));
-	hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD;
-	hperh->hdma.config.src        = (void *)buf;
-	hperh->hdma.config.dst        = (void *)&hperh->perh->DATA;
-	hperh->hdma.config.size       = size;
-	hperh->hdma.config.src_inc    = DMA_DATA_INC_HALFWORD;
-	hperh->hdma.config.dst_inc    = DMA_DATA_INC_NONE;
-	hperh->hdma.config.msel       = DMA_MSEL_CRC;
-	hperh->hdma.config.msigsel    = DMA_MSIGSEL_NONE;
-	hperh->hdma.config.channel    = channel;
-	hperh->hdma.config.burst      = ENABLE;
-	ald_dma_config_basic(&(hperh->hdma));
-
-	__UNLOCK(hperh);
-	CRC_DMA_ENABLE(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Calculate an amount of data used dma channel,data width is word.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @param  buf: Pointer to word data buffer
-  * @param  res: Pointer to result
-  * @param  size: Amount of word data to be Calculate
-  * @param  channel: DMA channel as CRC transmit
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
-{
-	if (hperh->state != CRC_STATE_READY)
-		return BUSY;
-
-	if (buf == NULL || size == 0)
-		return ERROR;
-
-	__LOCK(hperh);
-	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS);
-
-	hperh->state = CRC_STATE_BUSY;
-
-	hperh->cal_buf = (uint8_t *)buf;
-	hperh->cal_res = res;
-
-	if (hperh->hdma.perh == NULL)
-		hperh->hdma.perh = DMA0;
-
-	hperh->hdma.cplt_arg = (void *)hperh;
-	hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
-	hperh->hdma.err_arg  = (void *)hperh;
-	hperh->hdma.err_cbk  = &crc_dma_error;
-
-	ald_dma_config_struct(&(hperh->hdma.config));
-	hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD;
-	hperh->hdma.config.src        = (void *)buf;
-	hperh->hdma.config.dst        = (void *)&hperh->perh->DATA;
-	hperh->hdma.config.size       = size;
-	hperh->hdma.config.src_inc    = DMA_DATA_INC_WORD;
-	hperh->hdma.config.dst_inc    = DMA_DATA_INC_NONE;
-	hperh->hdma.config.msel       = DMA_MSEL_CRC;
-	hperh->hdma.config.msigsel    = DMA_MSIGSEL_NONE;
-	hperh->hdma.config.channel    = channel;
-	hperh->hdma.config.burst      = ENABLE;
-	ald_dma_config_basic(&(hperh->hdma));
-
-	__UNLOCK(hperh);
-	CRC_DMA_ENABLE(hperh);
-
-	return OK;
-}
-
-
-/**
-  * @brief  Pauses the DMA Transfer.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_crc_dma_pause(crc_handle_t *hperh)
-{
-	__LOCK(hperh);
-	CRC_DMA_DISABLE(hperh);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Resumes the DMA Transfer.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_crc_dma_resume(crc_handle_t *hperh)
-{
-	__LOCK(hperh);
-	CRC_DMA_ENABLE(hperh);
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Stops the DMA Transfer.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_crc_dma_stop(crc_handle_t *hperh)
-{
-	__LOCK(hperh);
-	CRC_DMA_DISABLE(hperh);
-	__UNLOCK(hperh);
-
-	hperh->state = CRC_STATE_READY;
-	return OK;
-}
-
-/**
-  * @}
-  */
-#endif
-
-/** @defgroup CRC_Public_Functions_Group4 Peripheral State and Errors functions
-  * @brief    CRC State and Errors functions
-  * @{
-  */
-
-/**
-  * @brief  Returns the CRC state.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @retval CRC state
-  */
-crc_state_t ald_crc_get_state(crc_handle_t *hperh)
-{
-	assert_param(IS_CRC(hperh->perh));
-
-	return hperh->state;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Private_Functions   CRC Private Functions
-  *  @brief   CRC Private functions
-  * @{
-  */
-
-/**
-  * @brief  Reset the CRC peripheral.
-  * @param  hperh: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @retval None
-  */
-void ald_crc_reset(crc_handle_t *hperh)
-{
-	hperh->perh->DATA = 0x0;
-	hperh->perh->CR   = 0x2;
-	hperh->perh->SEED = 0xFFFFFFFF;
-
-	hperh->state = CRC_STATE_READY;
-	__UNLOCK(hperh);
-	return;
-}
-
-#ifdef ALD_DMA
-/**
-  * @brief  DMA CRC calculate process complete callback.
-  * @param  arg: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @retval None
-  */
-static void crc_dma_calculate_cplt(void *arg)
-{
-	crc_handle_t *hperh = (crc_handle_t *)arg;
-
-	*(hperh->cal_res) = CRC->CHECKSUM;
-	CRC_DMA_DISABLE(hperh);
-
-	hperh->state = CRC_STATE_READY;
-
-	if (hperh->cal_cplt_cbk)
-		hperh->cal_cplt_cbk(hperh);
-}
-
-/**
-  * @brief  DMA CRC communication error callback.
-  * @param  arg: Pointer to a crc_handle_t structure that contains
-  *         the configuration information for the specified CRC module.
-  * @retval None
-  */
-static void crc_dma_error(void *arg)
-{
-	crc_handle_t *hperh = (crc_handle_t *)arg;
-
-	CRC_CLEAR_ERROR_FLAG(hperh);
-	CRC_DMA_DISABLE(hperh);
-
-	hperh->state = CRC_STATE_READY;
-
-	if (hperh->err_cplt_cbk)
-		hperh->err_cplt_cbk(hperh);
-}
-#endif
-/**
-  * @}
-  */
-#endif /* ALD_CRC */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_dac.c

@@ -1,349 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ald_dac.c
-  * @brief   DAC module driver.
-  *
-  * @version V1.0
-  * @date    28 Jun 2019
-  * @author  AE Team.
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          28 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#include "ald_conf.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup DAC DAC
-  * @brief DAC module driver
-  * @{
-  */
-#ifdef ALD_DAC
-
-/** @defgroup DAC_Public_Functions DAC Public Functions
-  * @{
-  */
-/**
-  * @brief  Reset the dac mode.
-  * @param  hperh: Pointer to a dac_handle_t structure that contains
-  *         the configuration information for the specified DAC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_dac_reset(dac_handle_t *hperh)
-{
-	assert_param(IS_DAC_TYPE(hperh->perh));
-
-	hperh->perh->CON      = 0;
-	hperh->perh->CH0CTRL  = 0;
-	hperh->perh->CH1CTRL  = 0;
-	hperh->perh->IES      = 0;
-	hperh->perh->IEC      = 0xFF;
-	hperh->perh->IFC      = 0xFF;
-	hperh->perh->CAL      = 0;
-
-	return OK;
-}
-
-/**
-  * @brief  Initializes the DAC peripheral.
-  * @param  hperh: Pointer to a dac_handle_t structure that contains
-  *         the configuration information for the specified DAC module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_dac_init(dac_handle_t *hperh)
-{
-	uint32_t tmp;
-
-	assert_param(IS_DAC_TYPE(hperh->perh));
-	assert_param(IS_DAC_CONVERT_TYPE(hperh->init.conv_mode));
-	assert_param(IS_DAC_OUTPUT_TYPE(hperh->init.out_mode));
-	assert_param(IS_DAC_NEG_REFRESH_TYPE(hperh->init.n_ref));
-	assert_param(IS_DAC_POS_REFRESH_TYPE(hperh->init.p_ref));
-	assert_param(IS_DAC_REFRESH_TYPE(hperh->init.refresh));
-	assert_param(IS_DAC_PRESCALE_TYPE(hperh->init.div));
-	assert_param(IS_FUNC_STATE(hperh->init.ch0_reset));
-	assert_param(IS_FUNC_STATE(hperh->init.o_ctrl_pis));
-	assert_param(IS_FUNC_STATE(hperh->init.sine));
-	assert_param(IS_FUNC_STATE(hperh->init.diff));
-
-	__LOCK(hperh);
-	ald_dac_reset(hperh);
-	DAC_CH0_DISABLE();
-	DAC_CH1_DISABLE();
-
-	MODIFY_REG(ADC0->CCR, ADC_CCR_VREFEN_MSK, 1 << ADC_CCR_VREFEN_POS);
-
-	if (hperh->init.p_ref == DAC_POS_REF_VREEFP_BUF || hperh->init.p_ref == DAC_POS_REF_2V)
-		SET_BIT(ADC0->CCR, (ADC_CCR_IREFEN_MSK | ADC_CCR_VRBUFEN_MSK | ADC_CCR_VCMBUFEN_MSK));
-
-	MODIFY_REG(ADC0->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS);
-	MODIFY_REG(ADC0->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS);
-
-	tmp = ((hperh->init.refresh << DAC_CON_RCYCLSEL_POSS) | (hperh->init.div << DAC_CON_PRES_POSS) |
-	       (hperh->init.ch0_reset << DAC_CON_CH0PRESRST_POS) | ( hperh->init.o_ctrl_pis << DAC_CON_OUTENPIS_POS) |
-	       (hperh->init.out_mode << DAC_CON_OUTMD_POSS) | (hperh->init.conv_mode << DAC_CON_CONVMD_POSS) |
-	       (hperh->init.sine << DAC_CON_SINEMD_POS) | (hperh->init.diff << DAC_CON_DIFEN_POS));
-	hperh->perh->CON = tmp;
-
-	/* Automatic calibration */
-	SET_BIT(hperh->perh->CAL, DAC_CAL_SELF_CALEN_MSK);
-	for (tmp = 0; tmp < 1000; ++tmp);
-	CLEAR_BIT(hperh->perh->CAL, DAC_CAL_SELF_CALEN_MSK);
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Configure dac channel.
-  * @param  hperh: Pointer to a dac_handle_t structure that contains
-  *         the configuration information for the specified DAC module.
-  * @param  config: Pointer to a dac_channel_config_t structure that contains
-  *         the configutation information for dac channel.
-  * @param  ch: Specifies which dac channel to be config.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_dac_channel_config(dac_handle_t *hperh, dac_channel_config_t *config, dac_channel_t ch)
-{
-	uint32_t tmp;
-
-	if ((hperh == NULL) || (config == NULL))
-		return ERROR;
-
-	assert_param(IS_DAC_TYPE(hperh->perh));
-	assert_param(IS_FUNC_STATE(config->enable));
-	assert_param(IS_DAC_TRIGGER_TYPE(config->trigger));
-	assert_param(IS_FUNC_STATE(config->refresh_en));
-	assert_param(IS_DAC_PISSEL_CH_TYPE(config->pis_ch));
-
-	__LOCK(hperh);
-	tmp = ((config->pis_ch << DAC_CH0CTRL_PISSEL_POSS) | (config->trigger << DAC_CH0CTRL_PISEN_POS) |
-	       (config->refresh_en << DAC_CH0CTRL_RCYCLEN_POS) | (config->enable << DAC_CH0CTRL_EN_POS));
-
-	switch (ch) {
-	case DAC_CHANNEL_0:
-		hperh->perh->CH0CTRL = tmp;
-		break;
-
-	case DAC_CHANNEL_1:
-		hperh->perh->CH1CTRL = tmp;
-		break;
-
-	default:
-		break;
-	}
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Set dac channel output value.
-  * @param  hperh: Pointer to a dac_handle_t structure that contains
-  *         the configuration information for the specified DAC module.
-  * @param  ch: Specifies which dac channel to be set.
-  * @param  value: The value be converted,and the valid value is low 12 bit.
-  * @retval None
-  */
-void ald_dac_output_set(dac_handle_t *hperh, dac_channel_t ch, uint32_t value)
-{
-	assert_param(IS_DAC_TYPE(hperh->perh));
-	assert_param(IS_DAC_CHANNEL_TYPE(ch));
-
-	switch (ch) {
-	case DAC_CHANNEL_0:
-		hperh->perh->CH0DATA = value;
-		break;
-
-	case DAC_CHANNEL_1:
-		hperh->perh->CH1DATA = value;
-		break;
-
-	case DAC_CHANNEL_COMB:
-		hperh->perh->COMBDATA = value;
-		break;
-
-	default:
-		break;
-	}
-
-	return;
-}
-
-/**
-  * @brief  Checks whether the specified DAC flag is set or not.
-  * @param  hperh: Pointer to a dac_handle_t structure that contains
-  *               the configuration information for the specified dac.
-  * @param  status: Specifies the flag to check.
-  * @retval The new state.
-  */
-flag_status_t ald_dac_get_status(dac_handle_t *hperh, dac_status_t status)
-{
-	assert_param(IS_DAC_TYPE(hperh->perh));
-	assert_param(IS_DAC_STATUS_TYPE(status));
-
-	return hperh->perh->STAT & status ? SET : RESET;
-}
-
-/**
-  * @brief Enable or disable the specified interrupt
-  * @param hperh: Pointer to a dac_handle_t structure that contains
-  *               the configuration information for the specified DAC.
-  * @param it: Specifies the interrupt type to be enabled or disabled
-  *        @arg @ref DAC_IT_CH0 Channel 0 conversion complete interrupt
-  *        @arg @ref DAC_IT_CH1 Channel 1 conversion complete interrupt
-  *        @arg @ref DAC_IT_CH0_UF Channel 0 data underflow interrupt
-  *        @arg @ref DAC_IT_CH1_UF Channel 1 data underflow interrupt
-  * @param state: New state of the specified interrupt.
-  *        This parameter can be: ENABLE or DISABLE
-  * @retval Status, see @ref ald_status_t.
-  */
-void ald_dac_interrupt_config(dac_handle_t *hperh, dac_it_t it, type_func_t state)
-{
-	assert_param(IS_DAC_TYPE(hperh->perh));
-	assert_param(IS_DAC_INTERRUPT_TYPE(it));
-	assert_param(IS_FUNC_STATE(state));
-
-	if (state)
-		hperh->perh->IES |= it;
-	else
-		hperh->perh->IEC = it;
-
-	return;
-}
-
-/**
-  * @brief  Get the status of DAC interrupt source.
-  * @param  hperh: Pointer to a dac_handle_t structure that contains
-  *               the configuration information for the specified DAC.
-  * @param  it: Specifies the DAC interrupt source.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-it_status_t ald_dac_get_it_status(dac_handle_t *hperh, dac_it_t it)
-{
-	assert_param(IS_DAC_TYPE(hperh->perh));
-	assert_param(IS_DAC_INTERRUPT_TYPE(it));
-
-	return hperh->perh->IEV & it ? SET : RESET;
-}
-
-/**
-  * @brief Checks whether the specified interrupt has occurred or not.
-  * @param hperh: Pointer to a dac_handle_t structure that contains
-  *               the configuration information for the specified DAC.
-  * @param flag: Specifies the interrupt type to check.
-  * @retval The new state.
-  */
-flag_status_t ald_dac_get_flag_status(dac_handle_t *hperh, dac_flag_t flag)
-{
-	assert_param(IS_DAC_TYPE(hperh->perh));
-	assert_param(IS_DAC_FLAG_TYPE(flag));
-
-	return hperh->perh->RIF & flag ? SET : RESET;
-}
-
-/**
-  * @brief  Get the status of interrupt flag and interupt source.
-  * @param  hperh: Pointer to a dac_handle_t structure that contains
-  *               the configuration information for the specified DAC.
-  * @param  flag: Specifies the DAC interrupt flag.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-flag_status_t ald_dac_get_mask_flag_status(dac_handle_t *hperh, dac_flag_t flag)
-{
-	assert_param(IS_DAC_TYPE(hperh->perh));
-	assert_param(IS_DAC_FLAG_TYPE(flag));
-
-	return hperh->perh->IFM & flag ? SET : RESET;
-}
-
-/**
-  * @brief  Clear interrupt state flag
-  * @param  hperh: Pointer to a dac_handle_t structure that contains
-  *               the configuration information for the specified DAC.
-  * @param  flag: Specifies the interrupt type to clear
-  * @retval None
-  */
-void ald_dac_clear_flag_status(dac_handle_t *hperh, dac_flag_t flag)
-{
-	assert_param(IS_DAC_TYPE(hperh->perh));
-	assert_param(IS_DAC_FLAG_TYPE(flag));
-
-	hperh->perh->IFC = flag;
-	return;
-}
-
-/**
-  * @brief  This function handles DAC event interrupt request.
-  * @param hperh: Pointer to a dac_handle_t structure that contains
-  *               the configuration information for the specified DAC.
-  * @retval None
-  */
-void ald_dac_irq_handler(dac_handle_t *hperh)
-{
-	if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH0)) {
-		ald_dac_clear_flag_status(hperh, DAC_FLAG_CH0);
-
-		if (hperh->cbk)
-			hperh->cbk(hperh, DAC_EVENT_CH0_CPLT);
-	}
-
-	if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH1)) {
-		ald_dac_clear_flag_status(hperh, DAC_FLAG_CH1);
-
-		if (hperh->cbk)
-			hperh->cbk(hperh, DAC_EVENT_CH1_CPLT);
-	}
-
-	if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH0_UF)) {
-		ald_dac_clear_flag_status(hperh, DAC_FLAG_CH0_UF);
-
-		if (hperh->cbk)
-			hperh->cbk(hperh, DAC_EVENT_CH0_UF);
-	}
-
-	if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH1_UF)) {
-		ald_dac_clear_flag_status(hperh, DAC_FLAG_CH1_UF);
-
-		if (hperh->cbk)
-			hperh->cbk(hperh, DAC_EVENT_CH1_UF);
-	}
-
-	return;
-}
-/**
-  *@}
-  */
-#endif /* ALD_DAC */
-/**
-  *@}
-  */
-/**
-  *@}
-  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_ebi.c

@@ -1,693 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_ebi.c
-  * @brief   EBI module driver.
-  *
-  * @version V1.0
-  * @date    20 Jan 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          20 Jan 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#include "ald_conf.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup EBI EBI
-  * @brief EBI module driver
-  * @{
-  */  
-#ifdef ALD_EBI
-
-/** @defgroup EBI_Public_Functions EBI Public Functions
-  * @{
-  */
-
-/** @defgroup EBI_Public_Functions_Group1 NOR-FLASH SRAM initialize functions
-  * @brief NOR-FLASH SRAM initialize functions
-  * @{
-  */  
-/**
-  * @brief  Initialize the EBI_NOR_SRAM device according to the specified
-  *         control parameters in the EBI_NOR_SRAM_InitTypeDef
-  * @param  dev: Pointer to NOR_SRAM device instance
-  * @param  init: Pointer to NOR_SRAM Initialization structure
-  * @retval None
-  */
-void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init)
-{
-	assert_param(IS_EBI_NORSRAM_DEVICE(dev));
-	assert_param(IS_EBI_NORSRAM_BANK(init->bank));
-	assert_param(IS_EBI_MUX(init->mux));
-	assert_param(IS_EBI_MEMORY(init->type));
-	assert_param(IS_EBI_NORSRAM_MEMORY_WIDTH(init->width));
-	assert_param(IS_EBI_BURSTMODE(init->acc_mode));
-	assert_param(IS_EBI_WAIT_POLARITY(init->polarity));
-	assert_param(IS_EBI_WRAP_MODE(init->wrap_mode));
-	assert_param(IS_EBI_WAIT_SIGNAL_ACTIVE(init->active));
-	assert_param(IS_EBI_WRITE_OPERATION(init->write));
-	assert_param(IS_EBI_WAITE_SIGNAL(init->signal));
-	assert_param(IS_EBI_EXTENDED_MODE(init->ext_mode));
-	assert_param(IS_EBI_ASYNWAIT(init->wait));
-	assert_param(IS_EBI_WRITE_BURST(init->burst));
-
-	/* Disable NORSRAM device */
-	ald_ebi_nor_sram_disable(dev, init->bank);
-
-	/* Set NORSRAM device control parameters */
-	if (init->type == EBI_MEMORY_TYPE_NOR) {
-		MODIFY_REG(dev->BTCR[init->bank], BCTRLR_CLEAR_MASK, (uint32_t)((uint32_t)EBI_NORSRAM_FLASH_ACCESS_ENABLE
-		       | (uint32_t)init->mux
-		       | (uint32_t)init->type
-		       | (uint32_t)init->width
-		       | (uint32_t)init->acc_mode
-		       | (uint32_t)init->polarity
-		       | (uint32_t)init->wrap_mode
-		       | (uint32_t)init->active
-		       | (uint32_t)init->write
-		       | (uint32_t)init->signal
-		       | (uint32_t)init->ext_mode
-		       | (uint32_t)init->wait
-		       | (uint32_t)init->burst));
-	}
-	else {
-		MODIFY_REG(dev->BTCR[init->bank], BCTRLR_CLEAR_MASK, (uint32_t)(EBI_NORSRAM_FLASH_ACCESS_DISABLE
-		       | (uint32_t)init->mux
-		       | (uint32_t)init->type
-		       | (uint32_t)init->width
-		       | (uint32_t)init->acc_mode
-		       | (uint32_t)init->polarity
-		       | (uint32_t)init->wrap_mode
-		       | (uint32_t)init->active
-		       | (uint32_t)init->write
-		       | (uint32_t)init->signal
-		       | (uint32_t)init->ext_mode
-		       | (uint32_t)init->wait
-		       | (uint32_t)init->burst));
-	}
-}
-
-/**
-  * @brief  Initialize the EBI_NOR_SRAM Timing according to the specified
-  *         parameters in the EBI_NOR_SRAM_TimingTypeDef
-  * @param  dev: Pointer to NOR_SRAM device instance
-  * @param  timing: Pointer to NOR_SRAM Timing structure
-  * @param  bank: NOR_SRAM bank number
-  * @retval None
-  */
-void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank)
-{
-	assert_param(IS_EBI_NORSRAM_DEVICE(dev));
-	assert_param(IS_EBI_ADDRESS_SETUP_TIME(timing->addr_setup));
-	assert_param(IS_EBI_ADDRESS_HOLD_TIME(timing->addr_hold));
-	assert_param(IS_EBI_DATASETUP_TIME(timing->data_setup));
-	assert_param(IS_EBI_TURNAROUND_TIME(timing->bus_dur));
-	assert_param(IS_EBI_DATA_LATENCY(timing->latency));
-	assert_param(IS_EBI_ACCESS_MODE(timing->mode));
-	assert_param(IS_EBI_NORSRAM_BANK(bank));
-
-	/* Set EBI_NORSRAM device timing parameters */
-	MODIFY_REG(dev->BTCR[bank + 1U], BTR_CLEAR_MASK,                       \
-		(uint32_t)(timing->addr_setup                                | \
-			((timing->addr_hold)      << EBI_BTRx_ADDHOLD_POSS)  | \
-			((timing->data_setup)     << EBI_BTRx_DATAHOLD_POSS) | \
-			((timing->bus_dur)	  << EBI_BTRx_BUSTURN_POSS)  | \
-			(((timing->div) - 1U)     << EBI_BTRx_CLKDIV_POSS)   | \
-			(((timing->latency) - 1U) << EBI_BTRx_DATALAT_POSS)  | \
-			(timing->mode)));
-}
-
-/**
-  * @brief  Initialize the EBI_NOR_SRAM Extended mode Timing according to the specified
-  *         parameters in the EBI_NOR_SRAM_TimingTypeDef
-  * @param  dev: Pointer to NOR_SRAM device instance
-  * @param  timing: Pointer to NOR_SRAM Timing structure
-  * @param  bank: NOR_SRAM bank number
-  * @param  mode EBI Extended Mode
-  *         This parameter can be one of the following values:
-  *            @arg EBI_EXTENDED_MODE_DISABLE
-  *            @arg EBI_EXTENDED_MODE_ENABLE
-  * @retval None
-  */
-void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode)
-{
-	assert_param(IS_EBI_EXTENDED_MODE(mode));
-
-	/* Set NORSRAM device timing register for write configuration, if extended mode is used */
-	if (mode == EBI_EXTENDED_MODE_ENABLE) {
-		assert_param(IS_EBI_NORSRAM_EXTENDED_DEVICE(dev));
-		assert_param(IS_EBI_ADDRESS_SETUP_TIME(timing->addr_setup));
-		assert_param(IS_EBI_ADDRESS_HOLD_TIME(timing->addr_hold));
-		assert_param(IS_EBI_DATASETUP_TIME(timing->data_setup));
-		assert_param(IS_EBI_TURNAROUND_TIME(timing->bus_dur));
-		assert_param(IS_EBI_ACCESS_MODE(timing->mode));
-		assert_param(IS_EBI_NORSRAM_BANK(bank));
-
-		/* Set NORSRAM device timing register for write configuration, if extended mode is used */
-		MODIFY_REG(dev->BWTR[bank], BWTR_CLEAR_MASK,                              \
-		       (uint32_t)(timing->addr_setup                                    | \
-				  ((timing->addr_hold)  << EBI_BWRTRx_ADDHOLD_POSS)	 | \
-				  ((timing->data_setup) << EBI_BWRTRx_DATAHOLD_POSS)	 | \
-				  timing->mode                                          | \
-				  ((timing->bus_dur)    << EBI_BWRTRx_BUSTURN_POSS)));
-	}
-	else {
-		dev->BWTR[bank] = 0x0FFFFFFFU;
-	}
-}
-
-/**
-  * @brief  DeInitialize the EBI_NOR_SRAM peripheral 
-  * @param  dev: Pointer to NOR_SRAM device instance
-  * @param  e_dev: Pointer to NOR_SRAM extended mode device instance
-  * @param  bank: NOR_SRAM bank number  
-  * @retval ald status
-  */
-ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank)
-{
-	assert_param(IS_EBI_NORSRAM_DEVICE(dev));
-	assert_param(IS_EBI_NORSRAM_EXTENDED_DEVICE(e_dev));
-	assert_param(IS_EBI_NORSRAM_BANK(bank));
-
-	/* Disable the EBI_NOR/SRAM device */
-	ald_ebi_nor_sram_disable(dev, bank);
-
-	/* De-initialize the EBI_NOR/SRAM device */
-	if (bank == EBI_NORSRAM_BANK1)
-		dev->BTCR[bank] = 0x000030DBU;
-	else
-		dev->BTCR[bank] = 0x000030D2U;
-
-	dev->BTCR[bank + 1U] = 0x0FFFFFFFU;
-	e_dev->BWTR[bank]    = 0x0FFFFFFFU;
-
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup EBI_Public_Functions_Group2 NOR-FLASH SRAM control functions
-  * @brief NOR-FLASH SRAM control functions
-  * @{
-  */
-/**
-  * @brief  Enable the NOR/SRAM device access.
-  * @param  dev: NOR/SRAM Instance
-  * @param  bank: NOR/SRAM Bank
-  * @retval none
-  */
-void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
-{
-	assert_param(IS_EBI_NORSRAM_DEVICE(dev));
-	assert_param(IS_EBI_NORSRAM_BANK(bank));
-
-	SET_BIT(dev->BTCR[bank], EBI_BCTRLRx_MEMBKEN_MSK);
-}
-
-/**
-  * @brief  Disable the NORSRAM device access.
-  * @param  dev: EBI_NORSRAM Instance
-  * @param  bank: EBI_NORSRAM Bank
-  * @retval none
-  */
-void ald_ebi_nor_sram_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
-{
-	assert_param(IS_EBI_NORSRAM_DEVICE(dev));
-	assert_param(IS_EBI_NORSRAM_BANK(bank));
-
-	CLEAR_BIT(dev->BTCR[bank], EBI_BCTRLRx_MEMBKEN_MSK);
-}
-
-/**
-  * @brief  Enables dynamically NOR-FLASH/SRAM write operation.
-  * @param  dev: Pointer to NOR/SRAM device instance
-  * @param  bank: NOR/SRAM bank number
-  * @retval void
-  */
-void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
-{
-	assert_param(IS_EBI_NORSRAM_DEVICE(dev));
-	assert_param(IS_EBI_NORSRAM_BANK(bank));
-
-	/* Enable write operation */
-	SET_BIT(dev->BTCR[bank], EBI_WRITE_OPERATION_ENABLE);
-}
-
-/**
-  * @brief  Disables dynamically EBI_NORSRAM write operation.
-  * @param  dev: Pointer to NORSRAM device instance
-  * @param  bank: NORSRAM bank number
-  * @retval None
-  */
-void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
-{
-	assert_param(IS_EBI_NORSRAM_DEVICE(dev));
-	assert_param(IS_EBI_NORSRAM_BANK(bank));
-
-	/* Disable write operation */
-	CLEAR_BIT(dev->BTCR[bank], EBI_WRITE_OPERATION_ENABLE);
-}
-/**
-  * @}
-  */
-
-/** @defgroup EBI_Public_Functions_Group3 NAND-FLASH initialize functions
-  * @brief NAND-FLASH initialize functions
-  * @{
-  */
-/**
-  * @brief  Initializes the EBI_NAND device according to the specified
-  *         control parameters in the EBI_NAND_HandleTypeDef
-  * @param  dev: Pointer to NAND device instance
-  * @param  init: Pointer to NAND Initialization structure
-  * @retval None
-  */
-void ald_ebi_nand_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init)
-{
-	assert_param(IS_EBI_NAND_DEVICE(dev));
-	assert_param(IS_EBI_NAND_BANK(init->bank));
-	assert_param(IS_EBI_WAIT_FEATURE(init->wait));
-	assert_param(IS_EBI_NAND_MEMORY_WIDTH(init->width));
-	assert_param(IS_EBI_ECC_STATE(init->ecc));
-	assert_param(IS_EBI_ECCPAGE_SIZE(init->size));
-	assert_param(IS_EBI_TCLR_TIME(init->cle_time));
-	assert_param(IS_EBI_TAR_TIME(init->ale_time));
-
-	/* Set NAND device control parameters */
-	if (init->bank == EBI_NAND_BANK2) {
-		MODIFY_REG(dev->PCTRLR2, PCTRLR_CLEAR_MASK, ((uint32_t)init->wait      |
-				(uint32_t)EBI_PCTRLR_MEMORY_TYPE_NAND                  |
-				(uint32_t)init->width                                  |
-				(uint32_t)init->ecc                                    |
-				(uint32_t)init->size                                   |
-				(uint32_t)((init->cle_time) << EBI_PCTRLRx_CRDLY_POSS) |
-				(uint32_t)((init->ale_time) << EBI_PCTRLRx_ARDLY_POSS)));
-	}
-	else {
-		MODIFY_REG(dev->PCTRLR3, PCTRLR_CLEAR_MASK, ((uint32_t)init->wait      |
-				(uint32_t)EBI_PCTRLR_MEMORY_TYPE_NAND                  |
-				(uint32_t)init->width                                  |
-				(uint32_t)init->ecc                                    |
-				(uint32_t)init->size                                   |
-				(uint32_t)((init->cle_time) << EBI_PCTRLRx_CRDLY_POSS) |
-				(uint32_t)((init->ale_time) << EBI_PCTRLRx_ARDLY_POSS)));
-	}
-}
-
-/**
-  * @brief  Initializes the EBI_NAND Common space Timing according to the specified
-  *         parameters in the EBI_NAND_TimingTypeDef
-  * @param  dev: Pointer to NAND device instance
-  * @param  timing: Pointer to NAND timing structure
-  * @param  bank: NAND bank number
-  * @retval None
-  */
-void ald_ebi_nand_comm_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
-{
-	assert_param(IS_EBI_NAND_DEVICE(dev));
-	assert_param(IS_EBI_SETUP_TIME(timing->time));
-	assert_param(IS_EBI_WAIT_TIME(timing->wait_time));
-	assert_param(IS_EBI_HOLD_TIME(timing->hold_time));
-	assert_param(IS_EBI_HIZ_TIME(timing->hiz_time));
-	assert_param(IS_EBI_NAND_BANK(bank));
-
-	/* Set EBI_NAND device timing parameters */
-	if (bank == EBI_NAND_BANK2) {
-		MODIFY_REG(dev->PMEMR2, PMEMR_CLEAR_MASK, (timing->time          | \
-				((timing->wait_time) << EBI_PMEMRx_MEMWAIT_POSS) | \
-				((timing->hold_time) << EBI_PMEMRx_MEMHOLD_POSS) | \
-				((timing->hiz_time)  << EBI_PMEMRx_MEMHIZT_POSS)));
-	}
-	else {
-		MODIFY_REG(dev->PMEMR3, PMEMR_CLEAR_MASK, (timing->time          | \
-				((timing->wait_time) << EBI_PMEMRx_MEMWAIT_POSS) | \
-				((timing->hold_time) << EBI_PMEMRx_MEMHOLD_POSS) | \
-				((timing->hiz_time)  << EBI_PMEMRx_MEMHIZT_POSS)));
-	}
-}
-
-/**
-  * @brief  Initializes the EBI_NAND Attribute space Timing according to the specified
-  *         parameters in the EBI_NAND_TimingTypeDef
-  * @param  dev: Pointer to NAND device instance
-  * @param  timing: Pointer to NAND timing structure
-  * @param  bank: NAND bank number
-  * @retval None
-  */
-void ald_ebi_nand_attr_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
-{
-	assert_param(IS_EBI_NAND_DEVICE(dev));
-	assert_param(IS_EBI_SETUP_TIME(timing->time));
-	assert_param(IS_EBI_WAIT_TIME(timing->wait_time));
-	assert_param(IS_EBI_HOLD_TIME(timing->hold_time));
-	assert_param(IS_EBI_HIZ_TIME(timing->hiz_time));
-	assert_param(IS_EBI_NAND_BANK(bank));
-
-	/* Set FMC_NAND device timing parameters */
-	if (bank == EBI_NAND_BANK2) {
-		MODIFY_REG(dev->PATTR2, PATTR_CLEAR_MASK, (timing->time       | \
-				((timing->wait_time) << EBI_PATTRx_ATTWAIT_POSS) | \
-				((timing->hold_time) << EBI_PATTRx_ATTHOLD_POSS) | \
-				((timing->hiz_time)  << EBI_PATTRx_ATTHIZT_POSS)));
-	}
-	else {
-		MODIFY_REG(dev->PATTR3, PATTR_CLEAR_MASK, (timing->time       | \
-				((timing->wait_time) << EBI_PATTRx_ATTWAIT_POSS) | \
-				((timing->hold_time) << EBI_PATTRx_ATTHOLD_POSS) | \
-				((timing->hiz_time)  << EBI_PATTRx_ATTHIZT_POSS)));
-	}
-}
-
-/**
-  * @brief  DeInitializes the EBI_NAND device 
-  * @param  dev: Pointer to NAND device instance
-  * @param  bank: NAND bank number
-  * @retval None
-  */
-void ald_ebi_nand_deinit(EBI_NAND_TypeDef *dev, uint32_t bank)
-{
-	assert_param(IS_EBI_NAND_DEVICE(dev));
-	assert_param(IS_EBI_NAND_BANK(bank));
-
-	/* Disable the NAND Bank */
-	ald_ebi_nand_disable(dev, bank);
-
-	/* De-initialize the NAND Bank */
-	if (bank == EBI_NAND_BANK2) {
-		/* Set the EBI_NAND_BANK2 registers to their reset values */
-		WRITE_REG(dev->PCTRLR2,  0x00000018U);
-		WRITE_REG(dev->STAR2,    0x00000040U);
-		WRITE_REG(dev->PMEMR2,   0xFCFCFCFCU);
-		WRITE_REG(dev->PATTR2,   0xFCFCFCFCU);
-	}
-	/* EBI_Bank3_NAND */
-	else {
-		/* Set the EBI_NAND_BANK3 registers to their reset values */
-		WRITE_REG(dev->PCTRLR3, 0x00000018U);
-		WRITE_REG(dev->STAR3,   0x00000040U);
-		WRITE_REG(dev->PMEMR3,  0xFCFCFCFCU);
-		WRITE_REG(dev->PATTR3,  0xFCFCFCFCU);
-	}
-}
-/**
-  * @}
-  */
-
-/** @defgroup EBI_Public_Functions_Group4 NAND-FLASH control functions
-  * @brief NAND-FLASH control functions
-  * @{
-  */ 
-/**
-  * @brief  Enable the NAND device access
-  * @param  dev: EBI_NAND Instance
-  * @param  bank: EBI_NAND Bank
-  * @retval None
-  */
-void ald_ebi_nand_enable(EBI_NAND_TypeDef *dev, uint32_t bank)
-{
-	assert_param(IS_EBI_NAND_DEVICE(dev));
-	assert_param(IS_EBI_NAND_BANK(bank));
-
-	if (bank == EBI_NAND_BANK2)
-		SET_BIT(dev->PCTRLR2, EBI_PCTRLRx_MEMBKEN_MSK);
-	else
-		SET_BIT(dev->PCTRLR3, EBI_PCTRLRx_MEMBKEN_MSK);
-}
-
-/**
-  * @brief  Disable the NAND device access.
-  * @param  dev: EBI_NAND Instance
-  * @param  bank: EBI_NAND Bank
-  * @retval None
-  */
-void ald_ebi_nand_disable(EBI_NAND_TypeDef *dev, uint32_t bank)
-{
-	assert_param(IS_EBI_NAND_DEVICE(dev));
-	assert_param(IS_EBI_NAND_BANK(bank));
-
-	if (bank == EBI_NAND_BANK2)
-		CLEAR_BIT(dev->PCTRLR2, EBI_PCTRLRx_MEMBKEN_MSK);
-	else
-		CLEAR_BIT(dev->PCTRLR3, EBI_PCTRLRx_MEMBKEN_MSK);
-}
-
-/**
-  * @brief  Enable the NAND device interrupt.
-  * @param  dev: EBI_NAND Instance
-  * @param  bank: EBI_NAND Bank
-  * @param  it: EBI_NAND interrupt
-  *         This parameter can be any combination of the following values:
-  *            @arg EBI_IT_RISING_EDGE: Interrupt rising edge.
-  *            @arg EBI_IT_LEVEL: Interrupt level.
-  *            @arg EBI_IT_FALLING_EDGE: Interrupt falling edge.
-  * @retval None
-  */
-void ald_ebi_nand_enable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
-{
-	assert_param(IS_EBI_NAND_DEVICE(dev));
-	assert_param(IS_EBI_NAND_BANK(bank));
-
-	if (bank == EBI_NAND_BANK2)
-		SET_BIT(dev->STAR2, it);
-	else
-		SET_BIT(dev->STAR3, it);
-}
-
-/**
-  * @brief  Disable the NAND device interrupt.
-  * @param  dev: EBI_NAND Instance
-  * @param  bank: EBI_NAND Bank
-  * @param  it: EBI_NAND interrupt
-  *         This parameter can be any combination of the following values:
-  *            @arg EBI_IT_RISING_EDGE: Interrupt rising edge.
-  *            @arg EBI_IT_LEVEL: Interrupt level.
-  *            @arg EBI_IT_FALLING_EDGE: Interrupt falling edge.
-  * @retval None
-  */
-void ald_ebi_nand_disable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
-{
-	assert_param(IS_EBI_NAND_DEVICE(dev));
-	assert_param(IS_EBI_NAND_BANK(bank));
-
-	if (bank == EBI_NAND_BANK2)
-		CLEAR_BIT(dev->STAR2, it);
-	else
-		CLEAR_BIT(dev->STAR3, it);
-}
-
-/**
-  * @brief  Enables dynamically EBI_NAND ECC feature.
-  * @param  dev: Pointer to NAND device instance
-  * @param  bank: NAND bank number
-  * @retval None
-  */
-void ald_ebi_nand_ecc_enable(EBI_NAND_TypeDef *dev, uint32_t bank)
-{
-	assert_param(IS_EBI_NAND_DEVICE(dev));
-	assert_param(IS_EBI_NAND_BANK(bank));
-
-	/* Enable ECC feature */
-	if (bank == EBI_NAND_BANK2)
-		SET_BIT(dev->PCTRLR2, EBI_PCTRLRx_ECCEN_MSK);
-	else
-		SET_BIT(dev->PCTRLR3, EBI_PCTRLRx_ECCEN_MSK);
-}
-
-/**
-  * @brief  Disables dynamically EBI_NAND ECC feature.
-  * @param  dev: Pointer to NAND device instance
-  * @param  bank: NAND bank number
-  * @retval None
-  */
-void ald_ebi_nand_ecc_disable(EBI_NAND_TypeDef *dev, uint32_t bank)
-{
-	assert_param(IS_EBI_NAND_DEVICE(dev));
-	assert_param(IS_EBI_NAND_BANK(bank));
-
-	/* Disable ECC feature */
-	if (bank == EBI_NAND_BANK2)
-		CLEAR_BIT(dev->PCTRLR2, EBI_PCTRLRx_ECCEN_MSK);
-	else
-		CLEAR_BIT(dev->PCTRLR3, EBI_PCTRLRx_ECCEN_MSK);
-}
-
-/**
-  * @brief  Disables dynamically EBI_NAND ECC feature.
-  * @param  dev: Pointer to NAND device instance
-  * @param  val: Pointer to ECC value
-  * @param  bank: NAND bank number
-  * @param  timeout: Timeout wait value  
-  * @retval ALD status
-  */
-ald_status_t ald_ebi_nand_get_ecc(EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout)
-{
-	uint32_t tick;
-
-	assert_param(IS_EBI_NAND_DEVICE(dev));
-	assert_param(IS_EBI_NAND_BANK(bank));
-
-	tick = ald_get_tick();
-
-	/* Wait until FIFO is empty */
-	while (ald_ebi_nand_get_flag(dev, bank, EBI_FLAG_FEMPT) == RESET) {
-		if (timeout != ALD_MAX_DELAY) {
-			if ((timeout == 0U) || ((ald_get_tick() - tick) > timeout))
-				return TIMEOUT;
-		}
-	}
-
-	if (bank == EBI_NAND_BANK2)
-		*val = (uint32_t)dev->ECCRESULT2;
-	else
-		*val = (uint32_t)dev->ECCRESULT3;
-
-	return OK;
-}
-
-/**
-  * @brief  Get flag status of the NAND device.
-  * @param  dev: EBI_NAND Instance
-  * @param  bank  : EBI_NAND Bank
-  * @param  flag  : EBI_NAND flag
-  *         This parameter can be any combination of the following values:
-  *            @arg EBI_FLAG_RISING_EDGE: Interrupt rising edge flag.
-  *            @arg EBI_FLAG_LEVEL: Interrupt level edge flag.
-  *            @arg EBI_FLAG_FALLING_EDGE: Interrupt falling edge flag.
-  *            @arg EBI_FLAG_FEMPT: FIFO empty flag.
-  * @retval Status:
-  *           - 0: RESET
-  *           - 1: SET
-  */
-flag_status_t ald_ebi_nand_get_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
-{
-	assert_param(IS_EBI_NAND_DEVICE(dev));
-	assert_param(IS_EBI_NAND_BANK(bank));
-
-	if (bank == EBI_NAND_BANK2) {
-		if (dev->STAR2 & flag)
-			return SET;
-	} else {
-		if (dev->STAR3 & flag)
-			return SET;
-	}
-
-	return RESET;
-}
-
-/**
-  * @brief  Clear flag status of the NAND device.
-  * @param  dev: EBI_NAND Instance
-  * @param  bank: EBI_NAND Bank
-  * @param  flag: EBI_NAND flag
-  *         This parameter can be any combination of the following values:
-  *            @arg EBI_FLAG_RISING_EDGE: Interrupt rising edge flag.
-  *            @arg EBI_FLAG_LEVEL: Interrupt level edge flag.
-  *            @arg EBI_FLAG_FALLING_EDGE: Interrupt falling edge flag.
-  *            @arg EBI_FLAG_FEMPT: FIFO empty flag.
-  * @retval None
-  */
-void ald_ebi_nand_clear_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
-{
-	assert_param(IS_EBI_NAND_DEVICE(dev));
-	assert_param(IS_EBI_NAND_BANK(bank));
-
-	/* Enable ECC feature */
-	if (bank == EBI_NAND_BANK2)
-		CLEAR_BIT(dev->STAR2, flag);
-	else
-		CLEAR_BIT(dev->STAR3, flag);
-}
-/**
-  * @}
-  */
-
-/** @defgroup EBI_Public_Functions_Group5 LCD initialize functions
-  * @brief LCD initialize functions
-  * @{
-  */ 
-/**
-  * @brief  Initializes the EBI_LCD device according to the specified
-  *         control parameters in the nor_lcd_handle_t
-  * @param  hlcd: Pointer to LCD device instance
-  * @retval None
-  */
-void ald_ebi_lcd_init(ebi_lcd_handle_t *hlcd)
-{
-	assert_param(IS_EBI_LCD_DEVICE(hlcd->inst));
-	assert_param(IS_EBI_BANK_NUMBER(hlcd->init.bank));
-	assert_param(IS_EBI_HORIZONTAL_SYNCH(hlcd->init.h_polarity));
-	assert_param(IS_EBI_VERTICAL_SYNCH(hlcd->init.v_polarity));
-	assert_param(IS_EBI_DATA_ENABLE(hlcd->init.data_polarity));
-	assert_param(IS_EBI_LCD_ENABLE(hlcd->init.enable));
-	assert_param(IS_EBI_DATA_CLOCK(hlcd->init.clk_polarity));
-	assert_param(IS_EBI_LCD_DATASETUP_TIME(hlcd->init.setup));
-	assert_param(IS_EBI_HYSNC_PULSE_WIDTH(hlcd->init.h_width));
-	assert_param(IS_EBI_VSYNC_PULSE_WIDTH(hlcd->init.v_width));
-	assert_param(IS_EBI_FRAME_LINE_NUMBER(hlcd->init.nr_line));
-	assert_param(IS_EBI_FRAME_PIXEL_NUMBER(hlcd->init.nr_pixel));
-
-	MODIFY_REG(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4], LCDCTRL_CLEAR_MASK,
-				((uint32_t)hlcd->init.h_polarity                  |
-				(uint32_t)hlcd->init.v_polarity                   |
-				hlcd->init.data_polarity                          |
-				hlcd->init.enable                                 |
-				hlcd->init.clk_polarity                           |
-				hlcd->init.setup   << EBI_LCDCTRLx_DATASETUP_POSS |
-				hlcd->init.h_width << EBI_LCDCTRLx_VSYNCWID_POSS  |
-				hlcd->init.v_width << EBI_LCDCTRLx_HSYNCWID_POSS));
-
-	WRITE_REG(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4 + 1],
-						 (hlcd->init.nr_line  << EBI_LCDSTx_LINECNT_POSS |
-						  hlcd->init.nr_pixel << EBI_LCDSTx_PXLCNT_POSS));
-}
-
-/**
-  * @brief  Reset the EBI_LCD 
-  * @param  hlcd: Pointer to LCD device instance
-  * @retval None
-  */
-void ald_ebi_lcd_reset(ebi_lcd_handle_t *hlcd)
-{
-	assert_param(IS_EBI_LCD_RESET(hlcd->init.reset));
-	assert_param(IS_EBI_BANK_NUMBER(hlcd->init.bank));
-
-	SET_BIT(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4], hlcd->init.reset);
-}
-
-/**
-  * @}
-  */
-/**
-  * @}
-  */												    
-#endif
-/**
- * @}
- */
-/**
- * @}
- */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_flash.c

@@ -1,243 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_flash.c
-  * @brief   FLASH module driver.
-  *
-  * @version V1.0
-  * @date    17 Jun 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          17 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  * @verbatim
-  ==============================================================================
-                    ##### FLASH Peripheral features #####
-  ==============================================================================
-  [..]
-  Base address is 0x00000000
-
-  [..]
-  FLASH have just one programme mode , word programme.
-  word programme can programme 8 bytes once ;
-
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-  This driver provide private functions for ald_flash_ext.c to use
-  @endverbatim
-  */
-
-#include "ald_conf.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup FLASH FLASH
-  * @brief FLASH module driver
-  * @{
-  */
-
-#ifdef ALD_FLASH
-
-#if defined ( __ICCARM__ )
-#define __RAMFUNC       __ramfunc
-#else
-#define __RAMFUNC
-#endif
-
-/** @defgroup Flash_Private_Variables Flash Private Variables
-  * @{
-  */
-/* global variable*/
-static op_cmd_type OP_CMD = OP_FLASH;
-/**
-  * @}
-  */
-
-/** @defgroup Flash_Private_Functions Flash Private Functions
-  *  @brief   Flash Private functions
-  * @{
-  */
-/**
-  * @brief  Unlock the flash.
-  * @retval Status, see @ref ald_status_t.
-  */
-__RAMFUNC static ald_status_t flash_unlock(void)
-{
-	uint16_t i;
-	uint16_t op_cmd = OP_CMD;
-
-	if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
-		return ERROR;
-
-	FLASH_REG_UNLOCK();
-	FLASH_IAP_ENABLE();
-	FLASH_REQ();
-
-	for (i = 0; i < 0xFFFF; i++) {
-		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))
-			break;
-	}
-
-	return i == 0xFFFF ? ERROR : OK;
-}
-
-/**
-  * @brief  Lock the flash.
-  * @retval Status, see @ref ald_status_t.
-  */
-__RAMFUNC static ald_status_t flash_lock(void)
-{
-	uint16_t i;
-	uint16_t op_cmd = OP_CMD;
-
-	FLASH_REG_UNLOCK();
-	WRITE_REG(MSC->FLASHCR, 0x0);
-
-	for (i = 0; i < 0xFFFF; i++) {
-		if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)))
-			break;
-	}
-
-	return i == 0xFFFF ? ERROR : OK;
-}
-
-/**
-  * @brief  Erase one page.
-  * @param  addr: The erased page's address
-  * @retval Status, see @ref ald_status_t.
-  */
-__RAMFUNC ald_status_t flash_page_erase(uint32_t addr)
-{
-	uint32_t i;
-	uint16_t op_cmd = OP_CMD;
-
-	if (flash_unlock() != OK)
-		goto end;
-
-	if (op_cmd == OP_FLASH) {
-		CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
-		MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS);
-	}
-	else {
-		SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
-		MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS);
-	}
-
-	WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE);
-
-	for (i = 0; i < 0xFFFF; i++) {
-		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
-			continue;
-		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK))
-			goto end;
-		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK))
-			goto end;
-		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK))
-			break;
-	}
-
-	if (i == 0xFFFF)
-		goto end;
-
-	if (flash_lock() == ERROR)
-		goto end;
-
-	return OK;
-end:
-	flash_lock();
-	return ERROR;
-}
-
-/**
-  * @brief  Programme a word.
-  * @param  addr: The word's address, it is must word align.
-  * @param  data: The 8 bytes data be write.
-  * @param  len: The number of data be write.
-  * @param  fifo: Choose if use fifo.
-  * @retval Status, see @ref ald_status_t.
-  */
-__RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo)
-{
-	uint16_t i = 0;
-	uint16_t prog_len;
-	uint32_t *p_data = data;
-	uint16_t op_cmd = OP_CMD;
-
-	if (flash_unlock() != OK)
-		goto end;
-
-	if (op_cmd == OP_FLASH)
-		CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
-	else
-		SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
-
-	MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS);
-	MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS);
-
-	for (prog_len = 0; prog_len < len; prog_len++) {
-		if (fifo) {
-			WRITE_REG(MSC->FLASHFIFO, p_data[0]);
-			WRITE_REG(MSC->FLASHFIFO, p_data[1]);
-		}
-		else {
-			WRITE_REG(MSC->FLASHDL, p_data[0]);
-			WRITE_REG(MSC->FLASHDH, p_data[1]);
-			WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP);
-		}
-
-		p_data += 2;
-
-		for (i = 0; i < 0xFFFF; i++) {
-			if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
-				continue;
-			if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK))
-				break;
-		}
-	}
-	if (i == 0xFFFF)
-		goto end;
-
-	if (flash_lock() == ERROR)
-		goto end;
-
-	return OK;
-end:
-	flash_lock();
-	return ERROR;
-}
-/**
-  * @}
-  */
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_flash_ext.c

@@ -1,343 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_flash_ext.c
-  * @brief   FLASH extra module driver.
-  *
-  * @version V1.0
-  * @date    17 Jun 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          17 Jun 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  * @verbatim
-  ==============================================================================
-                    ##### FLASH Peripheral features #####
-  ==============================================================================
-  [..]
-  Base address is 0x00000000
-
-  [..]
-  FLASH have just one programme mode , word programme.
-  word programme can programme 8 bytes once ;
-
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-   (#) programme flash using ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
-       (++) call the function and supply all the three paraments is needs, addr means
-            the first address to write in this operation, buf is a pointer to the data which
-	    need writing to flash.
-
-   (#) erase flash using ald_flash_erase(uint32_t addr, uint16_t len)
-       (++) call the function and supply two paraments, addr is the first address to erase,
-            len is the length to erase
-
-   (#) read flash using ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len)
-       (++) read the flash and save to a buffer, ram_addr is the buffer's first address,
-            addr is the start reading address in flash, len is the length need read
-
-    @endverbatim
-  */
-
-
-#include "ald_conf.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */
-
-#ifdef ALD_FLASH
-
-/** @addtogroup Flash_Private_Variables
-  * @{
-  */
-/* opration buffer*/
-static uint8_t write_buf[FLASH_PAGE_SIZE];
-/**
-  * @}
-  */
-
-/** @addtogroup Flash_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Check whether the flash between the given address section
-  *         have been writen, if it have been writen, return TRUE, else
-  *         return FALSE.
-  * @param  begin_addr: The begin address.
-  * @param  end_addr: The end address.
-  * @retval The check result
-  *         - TRUE
-  *         - FALSE
-  */
-static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr)
-{
-	uint8_t* addr_to_read;
-	uint8_t value;
-	uint32_t index;
-
-	/* Check the parameters */
-	assert_param(IS_FLASH_ADDRESS(begin_addr));
-	assert_param(IS_FLASH_ADDRESS(end_addr));
-
-	addr_to_read = (uint8_t *)begin_addr;
-	index        = begin_addr;
-	value        = 0xFF;
-
-	if (begin_addr > end_addr)
-		return FALSE;
-
-	while (index++ <= end_addr) {
-		value = *addr_to_read++;
-
-		if (value != 0xFF)
-			break;
-	}
-
-	return value == 0xFF ? FALSE : TRUE;
-}
-/**
-  * @}
-  */
-
-/** @defgroup Flash_Public_Functions Flash Public Functions
-  * @verbatim
- ===============================================================================
-              ##### Flash operation functions #####
- ===============================================================================
-  [..]
-    This section provides functions allowing to operate flash, such as read and write.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  read the specified length bytes from flash, and store to the specified area.
-  * @param  ram_addr: the specified area to store the reading bytes.
-  * @param  addr: the start address.
-  * @param  len: the length to read.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len)
-{
-	uint32_t i;
-	uint32_t temp;
-
-	assert_param(IS_4BYTES_ALIGN(ram_addr));
-	assert_param(IS_FLASH_ADDRESS(addr));
-	assert_param(IS_FLASH_ADDRESS(addr + len - 1));
-
-	temp = (uint32_t)ram_addr;
-
-	if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0))
-		return ERROR;
-
-	for (i = 0; i < len; i++)
-		ram_addr[i] = ((uint32_t *)addr)[i];
-
-	return OK;
-}
-
-/**
-  * @brief  Write the give bytes to the given address section.
-  * @param  addr: The start address to write.
-  * @param  buf: The bytes' address.
-  * @param  len: The length to write,and multiple of 2.
-  * @retval Status, see @ref ald_status_t.
-  */
-
-ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
-{
-	uint32_t index = 0;
-	uint32_t para = 0;
-	uint32_t index2 = 0;
-	uint32_t start_write_addr;
-	uint32_t end_write_addr;
-	uint32_t start_word_addr;
-	uint32_t end_word_addr;
-	uint16_t len_to_write;
-	uint32_t len_index;
-	type_bool_t need_erase_page;
-
-	assert_param(IS_FLASH_ADDRESS(addr));
-	assert_param(IS_FLASH_ADDRESS(addr + len - 1));
-
-	len_to_write = len;
-
-	__disable_irq();
-	while (len_to_write > 0) {
-		need_erase_page = FALSE;
-
-		for (index = 0; index < FLASH_PAGE_SIZE; index++)
-			write_buf[index] = 0xFF;
-
-		start_write_addr = addr + (len - len_to_write);
-		end_write_addr   = addr + len - 1;
-		end_write_addr   = FLASH_PAGE_ADDR(start_write_addr) == FLASH_PAGE_ADDR(end_write_addr)
-		                   ? end_write_addr : FLASH_PAGEEND_ADDR(start_write_addr);
-		need_erase_page  = page_have_writen(FLASH_WORD_ADDR(start_write_addr),
-		                                    FLASH_WORDEND_ADDR(end_write_addr));
-
-		if (need_erase_page) {
-			if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr),
-                                 		  FLASH_PAGE_SIZE >> 2)) {
-				__enable_irq();
-				return ERROR;
-			}
-
-			if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr))) {
-				__enable_irq();
-				return ERROR;
-			}
-
-			para   = end_write_addr & (FLASH_PAGE_SIZE - 1);
-			index  = start_write_addr & (FLASH_PAGE_SIZE - 1);
-			index2 = len - len_to_write;
-
-			while (index <= para)
-				write_buf[index++] = buf[index2++];
-
-			index2     = 0;
-			index      = FLASH_PAGE_ADDR(start_write_addr);
-			len_index  = FLASH_PAGE_SIZE;
-		}
-		else {
-			para   = end_write_addr & (FLASH_PAGE_SIZE - 1);
-			index  = start_write_addr & (FLASH_PAGE_SIZE - 1);
-			index2 = len - len_to_write;
-
-			while (index <= para)
-				write_buf[index++] = buf[index2++];
-
-			start_word_addr = FLASH_WORD_ADDR(start_write_addr);
-			end_word_addr   = FLASH_WORDEND_ADDR(end_write_addr);
-			index2          = (FLASH_WORD_ADDR(start_word_addr) - FLASH_PAGE_ADDR(start_word_addr));
-			index           = start_word_addr;
-			len_index       = end_word_addr - start_word_addr + 1;
-		}
-
-		if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO)) {
-			__enable_irq();
-			return ERROR;
-		}
-
-		len_to_write = len_to_write - (end_write_addr - start_write_addr + 1);
-	}
-
-	__enable_irq();
-	return OK;
-}
-
-/**
-  * @brief  erase The flash between the given address section.
-  * @param  addr: The start address to erase.
-  * @param  len: The length to erase.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_flash_erase(uint32_t addr, uint16_t len)
-{
-	uint32_t index;
-	int32_t para;
-	int32_t start_erase_addr;
-	int32_t end_erase_addr;
-	uint16_t len_not_erase;
-	uint32_t len_index;
-	type_bool_t page_need_save;
-
-	assert_param(IS_FLASH_ADDRESS(addr));
-	assert_param(IS_FLASH_ADDRESS(addr + len - 1));
-
-	len_not_erase = len;
-
-	__disable_irq();
-	while (len_not_erase > 0) {
-		page_need_save = FALSE;
-
-		start_erase_addr = addr + len - len_not_erase;
-		end_erase_addr   = addr + len - 1;
-		end_erase_addr   = (FLASH_PAGE_ADDR(start_erase_addr) == FLASH_PAGE_ADDR(end_erase_addr))
-		                    ? end_erase_addr : FLASH_PAGEEND_ADDR(start_erase_addr);
-
-		if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr)) {
-			if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1)))
-				page_need_save = TRUE;
-		}
-		if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) {
-			if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr)))
-				page_need_save = TRUE;
-		}
-
-		if (page_need_save) {
-			if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr),
-			                                                     FLASH_PAGE_SIZE >> 2)) {
-				__enable_irq();
-				return ERROR;
-			}
-		}
-
-		if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr))) {
-			__enable_irq();
-			return ERROR;
-		}
-
-		if (page_need_save) {
-			para  = end_erase_addr & (FLASH_PAGE_SIZE - 1);
-			index = start_erase_addr & (FLASH_PAGE_SIZE - 1);
-
-			while (index <= para)
-				write_buf[index++] = 0xFF;
-
-			index     = FLASH_PAGE_ADDR(start_erase_addr);
-			len_index = FLASH_PAGE_SIZE;
-			if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) {
-				__enable_irq();
-				return ERROR;
-			}
-		}
-		len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1);
-	}
-
-	__enable_irq();
-	return OK;
-}
-/**
-  * @}
-  */
-
-
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_gpio.c

@@ -1,644 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_gpio.c
-  * @brief   GPIO module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
-  *           + Initialization functions
-  *           + IO operation functions
-  *           + Control functions
-  *
-  * @version V1.0
-  * @date    07 Nov 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          07 Nov 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  * @verbatim
-  ==============================================================================
-                    ##### GPIO Peripheral features #####
-  ==============================================================================
-  [..]
-  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
-  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
-  in several modes:
-  (+) Input mode
-  (+) Analog mode
-  (+) Output mode
-  (+) External interrupt/event lines
-
-  [..]
-  During and just after reset, the external interrupt lines are not active and
-  the I/O ports are configured Analog mode.
-
-  [..]
-  All GPIO pins have weak internal pull-up and pull-down resistors, which can be
-  activated or not.
-
-  [..]
-  In Output mode, each IO can be configured on open-drain or push-pull
-  type and the Output driver can be selected depending on ODRV register.
-
-  [..]
-  In Input mode, each IO can select filter function.
-
-  [..]
-  Each IO can select TTL or SMIT type.
-
-  [..]
-  Each IO have up to eight functions, user can configure the functions depend
-  on the user's environment.
-
-  [..]
-  Each IO can be locked. Once locked, uesr can only change the output data.
-  Only when the CPU reset to unlock the GPIO port.
-
-  [..]
-  All ports have external interrupt/event capability. To use external interrupt
-  lines, the port must be configured in input mode. All available GPIO pins are
-  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
-
-  [..]
-  Each input line can be independently configured to select the type (event or interrupt) and
-  the corresponding trigger event (rising or falling). Each line can also masked
-  independently. A pending register maintains the status line of the interrupt requests.
-
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-   (#) Enable the GPIO clock.
-
-   (#) Configure the GPIO pin(s) using ald_gpio_init().
-       (++) Configure the IO mode using "mode" member from gpio_init_t structure
-       (++) Activate Pull-up, Pull-down resistor using "pupd" member from gpio_init_t
-            structure.
-       (++) In Output mode, configured on open-drain or push-pull using "odos"
-            member from gpio_init_t structure.
-       (++) In Output mode, configured output driver using "odrv" member
-            from gpio_init_t structure.
-       (++) In Input mode, configured filter function using "flt" member
-            from gpio_init_t structure.
-       (++) Configured type using "type" member from gpio_init_t structure.
-       (++) Configured functions using "func" member from gpio_init_t structure.
-       (++) Analog mode is required when a pin is to be used as ADC channel
-            or DAC output.
-
-   (#) Configure the GPIO pin(s) using ald_gpio_init_default().
-       (++) Configure GPIO pin using default param:
-            init.mode  = GPIO_MODE_OUTPUT;
-            init.odos  = GPIO_PUSH_PULL;
-            init.pupd  = GPIO_PUSH_UP;
-            init.podrv = GPIO_OUT_DRIVE_6;
-            init.nodrv = GPIO_OUT_DRIVE_6;
-            init.flt   = GPIO_FILTER_DISABLE;
-            init.type  = GPIO_TYPE_CMOS;
-            init.func  = GPIO_FUNC_1;
-
-   (#) In case of external interrupt/event mode selection, user need invoke
-       ald_gpio_exti_init() to configure some param. And then invoke
-       ald_gpio_exti_interrupt_config() to enable/disable external interrupt/event.
-
-   (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
-       mapped to the EXTI line using NVIC_SetPriority() and enable it using
-       NVIC_EnableIRQ().
-
-   (#) To get the level of a pin configured in input mode use GPIO_read_pin().
-
-   (#) To set/reset the level of a pin configured in output mode use
-       ald_gpio_write_pin()/ald_gpio_toggle_pin().
-
-   (#) To lock pin configuration until next reset use ald_gpio_lock_pin().
-
-   (#) Configure external interrupt mode and enable/disable using
-       ald_gpio_exti_interrupt_config().
-
-   (#) Get external interrupt flag status using ald_gpio_exti_get_flag_status().
-
-   (#) Clear pending external interrupt flag status using
-       ald_gpio_exti_clear_flag_status().
-
-    @endverbatim
-  */
-
-#include "ald_conf.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup GPIO GPIO
-  * @brief GPIO module driver
-  * @{
-  */
-
-#ifdef ALD_GPIO
-
-/** @defgroup GPIO_Public_Functions GPIO Public Functions
-  * @{
-  */
-
-/** @defgroup GPIO_Public_Functions_Group1 Initialization functions
-  * @brief    Initialization and Configuration functions
-  *
-    @verbatim
- ===============================================================================
-              ##### Initialization functions #####
- ===============================================================================
-  [..]
-    This section provides functions allowing to initialize the GPIOs or external
-    interrupt to be ready for use.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initialize the GPIOx peripheral according to the specified
-  *         parameters in the gpio_init_t.
-  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
-  * @param  pin: The pin which need to initialize.
-  * @param  init: Pointer to a gpio_init_t structure that can contains
-  *         the configuration information for the specified parameters.
-  * @retval None
-  */
-void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init)
-{
-	uint32_t i, pos, mask, tmp;
-
-	assert_param(IS_GPIO_PORT(GPIOx));
-	assert_param(IS_GPIO_PIN(pin));
-	assert_param(IS_GPIO_MODE(init->mode));
-	assert_param(IS_GPIO_ODOS(init->odos));
-	assert_param(IS_GPIO_PUPD(init->pupd));
-	assert_param(IS_GPIO_ODRV(init->podrv));
-	assert_param(IS_GPIO_ODRV(init->nodrv));
-	assert_param(IS_GPIO_FLT(init->flt));
-	assert_param(IS_GPIO_TYPE(init->type));
-	assert_param(IS_GPIO_FUNC(init->func));
-
-	for (i = 0; i < 16; ++i) {
-		if (((pin >> i) & 0x1) == 0)
-			continue;
-
-		/* Get position and 2-bits mask */
-		pos  = i << 1;
-		mask = 0x3 << pos;
-
-		/* Set PIN mode */
-		tmp  = READ_REG(GPIOx->MODE);
-		tmp &= ~mask;
-		tmp |= (init->mode << pos);
-		WRITE_REG(GPIOx->MODE, tmp);
-
-		/* Set PIN open-drain or push-pull */
-		tmp  = READ_REG(GPIOx->ODOS);
-		tmp &= ~mask;
-		tmp |= (init->odos << pos);
-		WRITE_REG(GPIOx->ODOS, tmp);
-
-		/* Set PIN push-up or/and push-down */
-		tmp  = READ_REG(GPIOx->PUPD);
-		tmp &= ~mask;
-		tmp |= (init->pupd << pos);
-		WRITE_REG(GPIOx->PUPD, tmp);
-
-		/* Set PIN output P-MOS driver */
-		tmp  = READ_REG(GPIOx->PODRV);
-		tmp &= ~mask;
-		tmp |= (init->podrv << pos);
-		WRITE_REG(GPIOx->PODRV, tmp);
-
-		/* Set PIN output N-MOS driver */
-		tmp  = READ_REG(GPIOx->NODRV);
-		tmp &= ~mask;
-		tmp |= (init->nodrv << pos);
-		WRITE_REG(GPIOx->NODRV, tmp);
-
-		/* Get position and 1-bit mask */
-		pos  = i;
-		mask = 0x1 << pos;
-
-		/* Set PIN filter enable or disable */
-		tmp  = READ_REG(GPIOx->FLT);
-		tmp &= ~mask;
-		tmp |= (init->flt << pos);
-		WRITE_REG(GPIOx->FLT, tmp);
-
-		/* Set PIN type ttl or smit */
-		tmp  = READ_REG(GPIOx->TYPE);
-		tmp &= ~mask;
-		tmp |= (init->type << pos);
-		WRITE_REG(GPIOx->TYPE, tmp);
-
-		/* Configure PIN function */
-		pos  = i < 8 ? (i << 2) : ((i - 8) << 2);
-		mask = 0xF << pos;
-		tmp  = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1);
-		tmp &= ~mask;
-		tmp |= (init->func << pos);
-		i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp);
-	}
-
-	return;
-}
-
-/**
-  * @brief  Initialize the GPIOx peripheral using the default parameters.
-  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
-  * @param  pin: The pin which need to initialize.
-  * @retval None
-  */
-void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin)
-{
-	gpio_init_t init;
-
-	/* Fill GPIO_init_t structure with default parameter */
-	init.mode  = GPIO_MODE_OUTPUT;
-	init.odos  = GPIO_PUSH_PULL;
-	init.pupd  = GPIO_PUSH_UP;
-	init.podrv = GPIO_OUT_DRIVE_6;
-	init.nodrv = GPIO_OUT_DRIVE_6;
-	init.flt   = GPIO_FILTER_DISABLE;
-	init.type  = GPIO_TYPE_CMOS;
-	init.func  = GPIO_FUNC_1;
-
-	ald_gpio_init(GPIOx, pin, &init);
-	return;
-}
-
-/**
-  * @brief  Sets GPIO function to default(func0).
-  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
-  * @retval None
-  */
-void ald_gpio_func_default(GPIO_TypeDef *GPIOx)
-{
-	WRITE_REG(GPIOx->FUNC0, 0x00);
-	WRITE_REG(GPIOx->FUNC1, 0x00);
-
-	return;
-}
-
-/**
-  * @brief  Initialize the external interrupt according to the specified
-  *         parameters in the exti_init_t.
-  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
-  * @param  pin: The pin which need to initialize.
-  * @param  init: Pointer to a exti_init_t structure that can contains
-  *         the configuration information for the specified parameters.
-  * @retval None
-  */
-void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init)
-{
-	uint8_t i;
-	uint8_t port;
-
-	assert_param(IS_GPIO_PORT(GPIOx));
-	assert_param(IS_GPIO_PIN(pin));
-	assert_param(IS_FUNC_STATE(init->filter));
-	assert_param(IS_EXTI_FLTCKS_TYPE(init->cks));
-
-	/* Get GPIO port */
-	if (GPIOx == GPIOA)
-		port = 0x0;
-	else if (GPIOx == GPIOB)
-		port = 0x1;
-	else if (GPIOx == GPIOC)
-		port = 2;
-	else if (GPIOx == GPIOD)
-		port = 3;
-	else if (GPIOx == GPIOE)
-		port = 4;
-	else if (GPIOx == GPIOF)
-		port = 5;
-	else if (GPIOx == GPIOG)
-		port = 6;
-	else if (GPIOx == GPIOH)
-		port = 7;
-	else
-		port = 0;
-
-	/* Get Pin index */
-	for (i = 0; i < 16; ++i) {
-		if (((pin >> i) & 0x1) == 0x1)
-			break;
-	}
-
-	/* Select external interrupt line */
-	if (i <= 7) {
-		EXTI->EXTIPSR0 &= ~(0x7U << (i * 4));
-		EXTI->EXTIPSR0 |= (port << (i * 4));
-	}
-	else {
-		i -= 8;
-		EXTI->EXTIPSR1 &= ~(0x7U << (i * 4));
-		EXTI->EXTIPSR1 |= (port << (i * 4));
-	}
-
-	/* Configure filter parameter */
-	if (init->filter == ENABLE) {
-		SET_BIT(EXTI->EXTIFLTCR, pin);
-		MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTCKS_MSK, init->cks << GPIO_EXTIFLTCR_FLTCKS_POSS);
-		MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS);
-	}
-	else {
-		CLEAR_BIT(EXTI->EXTIFLTCR, pin);
-	}
-
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Public_Functions_Group2 IO operation functions
-  * @brief   GPIO Read and Write
-  *
-    @verbatim
- ===============================================================================
-                       ##### IO operation functions #####
- ===============================================================================
-  [..]
-    This subsection provides a set of functions allowing to manage the GPIOs.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Read the specified input port pin.
-  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
-  * @param  pin: Specifies the pin to read.
-  * @retval The input pin value
-  */
-uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
-{
-	assert_param(IS_GPIO_PORT(GPIOx));
-	assert_param(IS_GPIO_PIN(pin));
-
-	if (READ_BIT(GPIOx->DIN, pin))
-		return 1;
-	else
-		return 0;
-}
-
-/**
-  * @brief  Set or clear the select Pin data.
-  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
-  * @param  pin: The specified pin to be written.
-  * @param  val: The specifies value to be written.
-  * @retval None
-  */
-void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val)
-{
-	assert_param(IS_GPIO_PORT(GPIOx));
-	assert_param(IS_GPIO_PIN(pin));
-
-	if ((val & (0x01)) == 0x00)
-		GPIOx->BSRR = pin << 16U;
-	else
-		GPIOx->BSRR = pin;
-
-	return;
-}
-
-/**
-  * @brief  Turn over the select data.
-  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
-  * @param  pin: Specifies the pin to turn over.
-  * @retval None
-  */
-void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
-{
-	assert_param(IS_GPIO_PORT(GPIOx));
-	assert_param(IS_GPIO_PIN(pin));
-
-	WRITE_REG(GPIOx->BIR, pin);
-	return;
-}
-
-/**
-  * @brief  Turn over the direction.
-  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
-  * @param  pin: Specifies the pin to turn over.
-  * @retval None
-  */
-void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin)
-{
-	uint32_t i, pos, mask, tmp, value;
-
-	assert_param(IS_GPIO_PORT(GPIOx));
-	assert_param(IS_GPIO_PIN(pin));
-
-	for (i = 0; i < 16; ++i) {
-		if (((pin >> i) & 0x1) == 0)
-			continue;
-
-		/* Get position and 2-bits mask */
-		pos  = i << 1;
-		mask = 0x3 << pos;
-
-		/* Get the new direction */
-		tmp = READ_REG(GPIOx->MODE);
-		value = (tmp >> pos) & 0x3;
-
-		if ((value == 2) || (value == 3))
-			value = 1;
-		else if (value == 1) {
-			value = 2;
-		}
-		else {
-			continue; /* do nothing */
-		}
-
-		/* Set PIN mode */
-		tmp &= ~mask;
-		tmp |= (value << pos);
-		WRITE_REG(GPIOx->MODE, tmp);
-	}
-
-	return;
-}
-
-/**
-  * @brief  Lock the GPIO prot. Once locked, can
-  *         only change the output data. Only when the CPU
-  *         reset to unlock the GPIO port.
-  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
-  * @param  pin: The specified Pin to be written.
-  * @retval None
-  */
-void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
-{
-	assert_param(IS_GPIO_PORT(GPIOx));
-	assert_param(IS_GPIO_PIN(pin));
-
-	MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, UNLOCK_KEY << GPIO_LOCK_KEY_POSS);
-	WRITE_REG(GPIOx->LOCK, pin);
-
-	return;
-}
-
-/**
-  * @brief  Read the specified input port pin.
-  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
-  * @retval The value;
-  */
-uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx)
-{
-	assert_param(IS_GPIO_PORT(GPIOx));
-
-	return READ_REG(GPIOx->DIN);
-}
-
-/**
-  * @brief  Set or clear the select Pin data.
-  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
-  * @param  val: The specifies value to be written.
-  * @retval None
-  */
-void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val)
-{
-	assert_param(IS_GPIO_PORT(GPIOx));
-
-	WRITE_REG(GPIOx->DOUT, val);
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Public_Functions_Group3 Control functions
-  * @brief EXTI Control functions
-  *
-    @verbatim
- ===============================================================================
-                       ##### Control functions #####
- ===============================================================================
-  [..]
-    This subsection provides a set of functions allowing to
-    control external interrupt.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure the interrupt according to the specified parameter.
-  * @param  pin: The Pin which need to configure.
-  * @param  style: External interrupt trigger style.
-  * @param  status:
-  *           @arg ENABLE
-  *           @arg DISABLE
-  * @retval None
-  */
-void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status)
-{
-	assert_param(IS_GPIO_PIN(pin));
-	assert_param(IS_TRIGGER_STYLE(style));
-	assert_param(IS_FUNC_STATE(status));
-
-	if (status == ENABLE) {
-		if (style == EXTI_TRIGGER_RISING_EDGE) {
-			SET_BIT(EXTI->EXTIRER, pin);
-		}
-		else if (style == EXTI_TRIGGER_TRAILING_EDGE) {
-			SET_BIT(EXTI->EXTIFER, pin);
-		}
-		else if (style == EXTI_TRIGGER_BOTH_EDGE) {
-			SET_BIT(EXTI->EXTIRER, pin);
-			SET_BIT(EXTI->EXTIFER, pin);
-		}
-		else {
-			; /* do nothing */
-		}
-
-		WRITE_REG(EXTI->EXTICFR, 0xffff);
-		SET_BIT(EXTI->EXTIEN, pin);
-	}
-	else {
-		if (style == EXTI_TRIGGER_RISING_EDGE) {
-			CLEAR_BIT(EXTI->EXTIRER, pin);
-		}
-		else if (style == EXTI_TRIGGER_TRAILING_EDGE) {
-			CLEAR_BIT(EXTI->EXTIFER, pin);
-		}
-		else if (style == EXTI_TRIGGER_BOTH_EDGE) {
-			CLEAR_BIT(EXTI->EXTIRER, pin);
-			CLEAR_BIT(EXTI->EXTIFER, pin);
-		}
-		else {
-			; /* do nothing */
-		}
-
-		CLEAR_BIT(EXTI->EXTIEN, pin);
-	}
-
-	return;
-}
-
-/**
-  * @brief  Get the Flag about external interrupt.
-  * @param  pin: The pin which belong to external interrupt.
-  * @retval Flag status
-  *         - SET
-  *         - RESET
-  */
-flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin)
-{
-	assert_param(IS_GPIO_PIN(pin));
-
-	if (READ_BIT(EXTI->EXTIFLAG, pin))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Clear the external interrupt flag.
-  * @param  pin: The pin which belong to external interrupt.
-  * @retval None
-  */
-void ald_gpio_exti_clear_flag_status(uint16_t pin)
-{
-	assert_param(IS_GPIO_PIN(pin));
-
-	WRITE_REG(EXTI->EXTICFR, pin);
-	return;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* ALD_GPIO */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_iap.c

@@ -1,259 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_iap.c
-  * @brief   IAP module driver.
-  *
-  * @version V1.0
-  * @date    04 Dec 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          04 Dec 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#include "ald_conf.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup IAP IAP
-  * @brief IAP module driver
-  * @{
-  */
-#ifdef ALD_IAP
-
-
-/** @defgroup IAP_Public_Functions IAP Public Functions
-  *
-  * @verbatim
-  ==============================================================================
-              #####  Erase and Program flash functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Erase flash.
-      (+) Program flash.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Erases a specified page.
-  * @param  addr: The beginning address of the page to be erased.
-  * @retval The result:
-  *           - 0: SUCCESS
-  *           - 1: ERROR
-  */
-uint32_t ald_iap_erase_page(uint32_t addr)
-{
-	uint32_t status;
-	IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR);
-
-	__disable_irq();
-	status = (*iap_pe)(addr);
-	__enable_irq();
-
-	return !status;
-}
-
-/**
-  * @brief  Programs a word at a specified address.
-  * @param  addr: Specifies the address to be programmed.
-  *         Bit0-1 must be zero.
-  * @param  data: Specifies the data to be programmed.
-  * @retval The result:
-  *           - 0: SUCCESS
-  *           - 1: ERROR
-  */
-uint32_t ald_iap_program_word(uint32_t addr, uint32_t data)
-{
-	uint32_t status;
-	IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR);
-
-	if (addr & 0x3)
-		return 1;
-
-	__disable_irq();
-	status = (*iap_wp)(addr, data);
-	__enable_irq();
-
-	return !status;
-}
-
-/**
-  * @brief  Programs double words at a specified address.
-  * @param  addr: Specifies the address to be programmed.
-  *         Bit0-1 must be zero.
-  * @param  data_l: Specifies the LSB data to be programmed.
-  * @param  data_h: Specifies the MSB data to be programmed.
-  * @retval The result:
-  *           - 0: SUCCESS
-  *           - 1: ERROR
-  */
-uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h)
-{
-	uint32_t status;
-	IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR);
-
-	if (addr & 0x3)
-		return 1;
-
-	__disable_irq();
-	status = (*iap_dwp)(addr, data_l, data_h);
-	__enable_irq();
-
-	return !status;
-}
-
-/**
-  * @brief  Programs datas at a specified address.
-  * @param  addr: Specifies the address to be programmed.
-  *         Bit0-1 must be zero.
-  * @param  data: Specifies the data to be programmed.
-  * @param  len: Specifies the data length to be programmed.
-  *         Bit0-1 must be zero.
-  * @param  erase: Erase page flag before programming.
-  * @retval The result:
-  *           - 0: SUCCESS
-  *           - 1: ERROR
-  */
-uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)
-{
-	uint32_t status;
-	IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR);
-
-	if ((addr & 0x3) || (len & 0x3))
-		return 1;
-
-	__disable_irq();
-	status = (*iap_wsp)(addr, data, len, erase);
-	__enable_irq();
-
-	return !status;
-}
-
-/**
-  * @brief  Erases a specified page of dataflash.
-  * @param  addr: The beginning address of the page to be erased.
-  * @retval The result:
-  *           - 0: SUCCESS
-  *           - 1: ERROR
-  */
-uint32_t ald_iap_erase_page_df(uint32_t addr)
-{
-	uint32_t status;
-	IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PageErase_DF);
-
-	__disable_irq();
-	status = (*iap_pe)(addr);
-	__enable_irq();
-
-	return !status;
-}
-
-/**
-  * @brief  Programs a word at a specified address of dataflash.
-  * @param  addr: Specifies the address to be programmed.
-  *         Bit0-1 must be zero.
-  * @param  data: Specifies the data to be programmed.
-  * @retval The result:
-  *           - 0: SUCCESS
-  *           - 1: ERROR
-  */
-uint32_t ald_iap_program_word_df(uint32_t addr, uint32_t data)
-{
-	uint32_t status;
-	IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WordProgram_DF);
-
-	if (addr & 0x3)
-		return 1;
-
-	__disable_irq();
-	status = (*iap_wp)(addr, data);
-	__enable_irq();
-
-	return !status;
-}
-
-/**
-  * @brief  Programs double words at a specified address of dataflash.
-  * @param  addr: Specifies the address to be programmed.
-  *         Bit0-1 must be zero.
-  * @param  data_l: Specifies the LSB data to be programmed.
-  * @param  data_h: Specifies the MSB data to be programmed.
-  * @retval The result:
-  *           - 0: SUCCESS
-  *           - 1: ERROR
-  */
-uint32_t ald_iap_program_dword_df(uint32_t addr, uint32_t data_l, uint32_t data_h)
-{
-	uint32_t status;
-	IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWordProgram_DF);
-
-	if (addr & 0x3)
-		return 1;
-
-	__disable_irq();
-	status = (*iap_dwp)(addr, data_l, data_h);
-	__enable_irq();
-
-	return !status;
-}
-
-/**
-  * @brief  Programs datas at a specified address of dataflash.
-  * @param  addr: Specifies the address to be programmed.
-  *         Bit0-1 must be zero.
-  * @param  data: Specifies the data to be programmed.
-  * @param  len: Specifies the data length to be programmed.
-  *         Bit0-1 must be zero.
-  * @param  erase: Erase page flag before programming.
-  * @retval The result:
-  *           - 0: SUCCESS
-  *           - 1: ERROR
-  */
-uint32_t ald_iap_program_words_df(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)
-{
-	uint32_t status;
-	IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WordsProgram_DF);
-
-	if ((addr & 0x3) || (len & 0x3))
-		return 1;
-
-	__disable_irq();
-	status = (*iap_wsp)(addr, data, len, erase);
-	__enable_irq();
-
-	return !status;
-}
-/**
-  * @}
-  */
-#endif /* ALD_IAP */
-/**
-  * @}
-  */
-/**
-  * @}
-  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_nor_lcd.c

@@ -1,610 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_nor_lcd.c
-  * @brief   EBI_NOR_LCD module driver.
-  *
-  * @version V1.0
-  * @date    25 Dec 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          25 Dec 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#include "ald_conf.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup NOR_LCD NOR_LCD
-  * @brief NOR_LCD driver modules
-  * @{
-  */
-#ifdef ALD_NOR
-
-/** @defgroup NOR_LCD_Private_Variables NOR_LCD Private Variables
-  * @{
-  */
-static uint32_t NORMEMDATWIDTH = NOR_MEMORY_8B;
-/**
-  * @}
-  */
-
-/** @defgroup NOR_LCD_Public_Functions NOR_LCD Public Functions
-  * @brief NOR_LCD public functions
-  * @{
-  */
-/** @defgroup NOR_LCD_Public_Functions_Group1 Initialization functions
-  * @brief NOR_LCD Initialization functions 
-  * @{
- */
-/**
-  * @brief  Perform the NOR memory Initialization sequence
-  * @param  hperh: pointer to a nor_handle_t structure 
-  * @param  timing: pointer to NOR control timing structure 
-  * @param  ext_timing: pointer to NOR extended mode timing structure    
-  * @retval ald status 
-  */
-ald_status_t ald_nor_init(nor_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing)
-{
-	if (hperh == NULL)
-		return ERROR;
-	if (hperh->state == ALD_NOR_STATE_RESET)
-		hperh->lock = UNLOCK;
-
-	/* Initialize NOR control Interface */
-	ald_ebi_nor_sram_init(hperh->instance, &(hperh->init));
-	/* Initialize NOR timing Interface */
-	ald_ebi_nor_sram_timing_init(hperh->instance, timing, hperh->init.bank);
-	/* Initialize NOR extended mode timing Interface */
-	ald_ebi_nor_sram_ext_timing_init(hperh->ext, ext_timing, hperh->init.bank, hperh->init.ext_mode);
-	/* Enable the NORSRAM device */
-	ald_ebi_nor_sram_enable(hperh->instance, hperh->init.bank);
-
-	/* Initialize NOR Memory Data Width*/
-	if (hperh->init.width == EBI_NORSRAM_MEM_BUS_WIDTH_8)
-		NORMEMDATWIDTH = NOR_MEMORY_8B;
-	else
-		NORMEMDATWIDTH = NOR_MEMORY_16B;
-
-	hperh->state = ALD_NOR_STATE_READY;
-	return OK;
-}
-
-/**
-  * @brief  Perform NOR memory De-Initialization sequence
-  * @param  hperh: pointer to a nor_handle_t structure 
-  * @retval ald status
-  */
-ald_status_t ald_nor_deinit(nor_handle_t *hperh)
-{
-	ald_ebi_nor_sram_deinit(hperh->instance, hperh->ext, hperh->init.bank);
-	hperh->state = ALD_NOR_STATE_RESET;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup NOR_LCD_Public_Functions_Group2 I/O operation functions
-  * @brief NOR_LCD I/O operation functions
-  * @{
-  */
-/**
-  * @brief  Read NOR flash IDs
-  * @param  hperh: pointer to a nor_handle_t structure
-  * @param  id : pointer to NOR ID structure
-  * @retval ald status
-  */
-ald_status_t ald_nor_read_id(nor_handle_t *hperh, nor_id_t *id)
-{
-	uint32_t devaddr = 0;
-
-	__LOCK(hperh);
-
-	if (hperh->state == ALD_NOR_STATE_BUSY)
-		return BUSY;
-
-	/* Select the NOR device address */
-	if (hperh->init.bank == EBI_NORSRAM_BANK1)
-		devaddr = NOR_MEMORY_ADRESS1;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
-		devaddr = NOR_MEMORY_ADRESS2;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
-		devaddr = NOR_MEMORY_ADRESS3;
-	else
-		devaddr = NOR_MEMORY_ADRESS4;
-
-	hperh->state = ALD_NOR_STATE_BUSY;
-
-	/* Send read ID command */
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
-
-	/* Read the NOR IDs */
-	id->m_code       = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, MC_ADDRESS);
-	id->device_code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE1_ADDR);
-	id->device_code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE2_ADDR);
-	id->device_code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE3_ADDR);
-
-	hperh->state = ALD_NOR_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Returns the NOR memory to Read mode.
-  * @param  hperh: pointer to a nor_handle_t structure 
-  * @retval ald status
-  */
-ald_status_t ald_nor_return_readmode(nor_handle_t *hperh)
-{
-	uint32_t devaddr = 0;
-
-	__LOCK(hperh);
-
-	if (hperh->state == ALD_NOR_STATE_BUSY)
-		return BUSY;
-
-	/* Select the NOR device address */
-	if (hperh->init.bank == EBI_NORSRAM_BANK1)
-		devaddr = NOR_MEMORY_ADRESS1;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
-		devaddr = NOR_MEMORY_ADRESS2;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
-		devaddr = NOR_MEMORY_ADRESS3;
-	else
-		devaddr = NOR_MEMORY_ADRESS4;
-
-	NOR_WRITE(devaddr, NOR_CMD_DATA_READ_RESET);
-	hperh->state = ALD_NOR_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Read data from NOR memory 
-  * @param  hperh: pointer to a nor_handle_t structure
-  * @param  addr: pointer to Device address
-  * @param  data: pointer to read data  
-  * @retval ald status
-  */
-ald_status_t ald_nor_read(nor_handle_t *hperh, uint32_t *addr, uint16_t *data)
-{
-	uint32_t devaddr = 0;
-
-	__LOCK(hperh);
-
-	if (hperh->state == ALD_NOR_STATE_BUSY)
-		return BUSY;
-
-	if (hperh->init.bank == EBI_NORSRAM_BANK1)
-		devaddr = NOR_MEMORY_ADRESS1;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
-		devaddr = NOR_MEMORY_ADRESS2;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
-		devaddr = NOR_MEMORY_ADRESS3;
-	else
-		devaddr = NOR_MEMORY_ADRESS4;
-
-	hperh->state = ALD_NOR_STATE_BUSY;
-
-	/* Send read data command */
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-	NOR_WRITE((uint32_t)addr, NOR_CMD_DATA_READ_RESET);
-
-	*data = *(__IO uint32_t *)(uint32_t)addr;
-	hperh->state = ALD_NOR_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Program data to NOR memory 
-  * @param  hperh: pointer to a nor_handle_t structure 
-  * @param  addr: device address
-  * @param  data: pointer to the data to write   
-  * @retval ald status
-  */
-ald_status_t ald_nor_program(nor_handle_t *hperh, uint32_t *addr, uint16_t *data)
-{
-	uint32_t devaddr = 0;
-
-	__LOCK(hperh);
-
-	if (hperh->state == ALD_NOR_STATE_BUSY)
-		return BUSY;
-
-	/* Select the NOR device address */
-	if (hperh->init.bank == EBI_NORSRAM_BANK1)
-		devaddr = NOR_MEMORY_ADRESS1;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
-		devaddr = NOR_MEMORY_ADRESS2;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
-		devaddr = NOR_MEMORY_ADRESS3;
-	else /* EBI_NORSRAM_BANK4 */
-		devaddr = NOR_MEMORY_ADRESS4;
-
-	hperh->state = ALD_NOR_STATE_BUSY;
-
-	/* Send program data command */
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
-
-	/* Write the data */
-	NOR_WRITE(addr, *data);
-	hperh->state = ALD_NOR_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Reads a block of data from the EBI NOR memory
-  * @param  hperh: pointer to a nor_handle_t structure 
-  * @param  addr: nor memory internal address to read from
-  * @param  data: pointer to the buffer that receives the data read from the 
-  *         NOR memory
-  * @param  size : number of Half word to read
-  * @retval ald status
-  */
-ald_status_t ald_nor_read_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size)
-{
-	uint32_t devaddr = 0;
-
-	/* Process Locked */
-	__LOCK(hperh);
-
-	if (hperh->state == ALD_NOR_STATE_BUSY)
-		return BUSY;
-
-	if (hperh->init.bank == EBI_NORSRAM_BANK1)
-		devaddr = NOR_MEMORY_ADRESS1;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
-		devaddr = NOR_MEMORY_ADRESS2;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
-		devaddr = NOR_MEMORY_ADRESS3;
-	else
-		devaddr = NOR_MEMORY_ADRESS4;
-
-	hperh->state = ALD_NOR_STATE_BUSY;
-
-	/* Send read data command */
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-	NOR_WRITE(addr, NOR_CMD_DATA_READ_RESET);
-
-	/* Read buffer */
-	while (size > 0) {
-		*data++ = *(__IO uint16_t *)addr;
-		addr += 2U;
-		size--;
-	}
-
-	hperh->state = ALD_NOR_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Writes a half-word buffer to the EBI NOR memory
-  * @param  hperh: pointer to a nor_handle_t structure
-  * @param  addr: nor memory internal address from which the data 
-  * @param  data: pointer to source data buffer 
-  * @param  size: number of Half words to write  
-  * @retval ald status
-  */ 
-ald_status_t ald_nor_program_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size)
-{
-	uint16_t * p_currentaddr = (uint16_t *)NULL;
-	uint16_t * p_endaddr = (uint16_t *)NULL;
-	uint32_t lastloadedaddr = 0, devaddr = 0;
-
-	__LOCK(hperh);
-
-	if (hperh->state == ALD_NOR_STATE_BUSY)
-		return BUSY;
-
-	if (hperh->init.bank == EBI_NORSRAM_BANK1)
-		devaddr = NOR_MEMORY_ADRESS1;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
-		devaddr = NOR_MEMORY_ADRESS2;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
-		devaddr = NOR_MEMORY_ADRESS3;
-	else
-		devaddr = NOR_MEMORY_ADRESS4;
-
-	hperh->state = ALD_NOR_STATE_BUSY;
-
-	/* Initialize variables */
-	p_currentaddr  = (uint16_t*)((uint32_t)(addr));
-	p_endaddr      = p_currentaddr + (size - 1U);
-	lastloadedaddr = (uint32_t)(addr);
-
-	/* Issue unlock command sequence */
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-	/* Write Buffer Load Command */
-	NOR_WRITE((uint32_t)(p_currentaddr), NOR_CMD_DATA_BUFFER_AND_PROG);
-	NOR_WRITE((uint32_t)(p_currentaddr), (size - 1U));
-
-	/* Load Data into NOR Buffer */
-	while (p_currentaddr <= p_endaddr) {
-		lastloadedaddr = (uint32_t)p_currentaddr;
-		NOR_WRITE(p_currentaddr, *data++);
-		p_currentaddr++;
-	}
-
-	NOR_WRITE((uint32_t)(lastloadedaddr), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
-	hperh->state = ALD_NOR_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Erase the specified block of the NOR memory 
-  * @param  hperh: pointer to a nor_handle_t structure 
-  * @param  blkaddr : block to erase address 
-  * @param  addr: device address
-  * @retval ald status
-  */
-ald_status_t ald_nor_erase_block(nor_handle_t *hperh, uint32_t blkaddr, uint32_t addr)
-{
-	uint32_t devaddr = 0;
-
-	__LOCK(hperh);
-
-	if (hperh->state == ALD_NOR_STATE_BUSY)
-		return BUSY;
-
-	if (hperh->init.bank == EBI_NORSRAM_BANK1)
-		devaddr = NOR_MEMORY_ADRESS1;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
-		devaddr = NOR_MEMORY_ADRESS2;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
-		devaddr = NOR_MEMORY_ADRESS3;
-	else
-		devaddr = NOR_MEMORY_ADRESS4;
-
-	hperh->state = ALD_NOR_STATE_BUSY;
-
-	/* Send block erase command sequence */
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
-	NOR_WRITE((uint32_t)(blkaddr + addr), NOR_CMD_DATA_BLOCK_ERASE);
-
-	hperh->state = ALD_NOR_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-
-}
-
-/**
-  * @brief  Erase the entire NOR chip.
-  * @param  hperh: pointer to a nor_handle_t structure
-  * @retval ald status
-  */
-ald_status_t ald_nor_erase_chip(nor_handle_t *hperh)
-{
-	uint32_t devaddr = 0;
-
-	__LOCK(hperh);
-
-	if (hperh->state == ALD_NOR_STATE_BUSY)
-		return BUSY;
-
-	/* Select the NOR device address */
-	if (hperh->init.bank == EBI_NORSRAM_BANK1)
-		devaddr = NOR_MEMORY_ADRESS1;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
-		devaddr = NOR_MEMORY_ADRESS2;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
-		devaddr = NOR_MEMORY_ADRESS3;
-	else
-		devaddr = NOR_MEMORY_ADRESS4;
-
-	hperh->state = ALD_NOR_STATE_BUSY;
-
-	/* Send NOR chip erase command sequence */
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
-
-	hperh->state = ALD_NOR_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Read NOR flash CFI IDs
-  * @param  hperh: pointer to a nor_handle_t structure
-  * @param  cfi: pointer to NOR CFI IDs structure  
-  * @retval ald status
-  */
-ald_status_t ald_nor_read_cfi(nor_handle_t *hperh, nor_cfi_t *cfi)
-{
-	uint32_t devaddr = 0;
-
-	__LOCK(hperh);
-
-	if (hperh->state == ALD_NOR_STATE_BUSY)
-		return BUSY;
-
-	/* Select the NOR device address */
-	if (hperh->init.bank == EBI_NORSRAM_BANK1)
-		devaddr = NOR_MEMORY_ADRESS1;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
-		devaddr = NOR_MEMORY_ADRESS2;
-	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
-		devaddr = NOR_MEMORY_ADRESS3;
-	else
-		devaddr = NOR_MEMORY_ADRESS4;
-
-	hperh->state = ALD_NOR_STATE_BUSY;
-	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
-
-	cfi->cfi_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI1_ADDRESS);
-	cfi->cfi_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI2_ADDRESS);
-	cfi->cfi_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI3_ADDRESS);
-	cfi->cfi_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI4_ADDRESS);
-
-	hperh->state = ALD_NOR_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup NOR_LCD_Public_Functions_Group3 Control functions
-  * @brief NOR_LCD Control functions
-  * @{
-  */
-/**
-  * @brief  Enables dynamically NOR write operation.
-  * @param  hperh: pointer to a nor_handle_t structure
-  * @retval ald status
-  */
-ald_status_t ald_nor_write_enable(nor_handle_t *hperh)
-{
-	__LOCK(hperh);
-	/* Enable write operation */
-	ald_ebi_nor_sram_write_enable(hperh->instance, hperh->init.bank);
-	hperh->state = ALD_NOR_STATE_READY;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Disables dynamically NOR write operation.
-  * @param  hperh: pointer to a nor_handle_t structure
-  * @retval ald status
-  */
-ald_status_t ald_nor_write_disable(nor_handle_t *hperh)
-{
-	__LOCK(hperh);
-	hperh->state = ALD_NOR_STATE_BUSY;
-	/* Disable write operation */
-	ald_ebi_nor_sram_write_disable(hperh->instance, hperh->init.bank);
-	hperh->state = ALD_NOR_STATE_PROTECTED;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup NOR_LCD_Public_Functions_Group4 State functions
-  * @brief NOR_LCD State functions
-  * @{
-  */
-/**
-  * @brief  return the NOR controller state
-  * @param  hperh: pointer to a nor_handle_t structure 
-  * @retval nor controller state
-  */
-ald_nor_state_t ald_nor_get_state(nor_handle_t *hperh)
-{
-	return hperh->state;
-}
-
-/**
-  * @brief  Returns the NOR operation status.
-  * @param  hperh: pointer to a nor_handle_t structure    
-  * @param  addr: device address
-  * @param  timeout: nor progamming timeout
-  * @retval nor status
-  */
-nor_status_t ald_nor_get_status(nor_handle_t *hperh, uint32_t addr, uint32_t timeout)
-{
-	nor_status_t status = ALD_NOR_STATUS_ONGOING;
-	uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
-	uint32_t tickstart = 0;
-
-	/* Get tick */
-	tickstart = ald_get_tick();
-	while ((status != ALD_NOR_STATUS_SUCCESS) && (status != ALD_NOR_STATUS_TIMEOUT)) {
-		/* Check for the Timeout */
-		if (timeout != ALD_MAX_DELAY) {
-			if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout))
-				status = ALD_NOR_STATUS_TIMEOUT;
-		}
-
-		/* Read NOR status register (DQ6 and DQ5) */
-		tmp_sr1 = *(__IO uint16_t *)addr;
-		tmp_sr2 = *(__IO uint16_t *)addr;
-
-		/* If DQ6 did not toggle between the two reads then return NOR_Success */
-		if ((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
-			return ALD_NOR_STATUS_SUCCESS;
-
-		if ((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
-			status = ALD_NOR_STATUS_ONGOING;
-
-		tmp_sr1 = *(__IO uint16_t *)addr;
-		tmp_sr2 = *(__IO uint16_t *)addr;
-
-		/* If DQ6 did not toggle between the two reads then return NOR_Success */
-		if ((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
-			return ALD_NOR_STATUS_SUCCESS;
-		else if ((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
-			return ALD_NOR_STATUS_ERROR;
-	}
-
-	return status;
-}
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#endif
-/**
-  * @}
-  */
-/**
-  * @}		
-  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_pis.c

@@ -1,323 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_pis.c
-  * @brief   PIS module driver.
-  *
-  * @version V1.0
-  * @date    27 Nov 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          27 Nov 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#include "ald_conf.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup PIS PIS
-  * @brief PIS module driver
-  * @{
-  */
-#ifdef ALD_PIS
-
-/** @defgroup PIS_Public_Functions PIS Public Functions
-  * @{
-  */
-
-/** @defgroup PIS_Public_Functions_Group1 Initialization functions
-  * @brief Initialization and Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  Create the PIS mode according to the specified parameters in
-  *         the pis_handle_t and create the associated handle.
-  * @param  hperh: Pointer to a pis_handle_t structure that contains
-  *         the configuration information for the specified PIS module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_pis_create(pis_handle_t *hperh)
-{
-	if (hperh == NULL)
-		return ERROR;
-
-	assert_param(IS_PIS_SRC(hperh->init.producer_src));
-	assert_param(IS_PIS_TRIG(hperh->init.consumer_trig));
-	assert_param(IS_PIS_CLOCK(hperh->init.producer_clk));
-	assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk));
-	assert_param(IS_PIS_EDGE(hperh->init.producer_edge));
-	assert_param(IS_PIS_SIGNAL_MODE(hperh->init.producer_signal));
-
-	__LOCK(hperh);
-	hperh->perh = PIS;
-
-	/* get location of consumer in channel and position of con0/con1
-	 * accord to comsumer_trig information */
-	hperh->consumer_ch  = (pis_ch_t)(hperh->init.consumer_trig & 0x0F);
-	hperh->consumer_con = (pis_con_t)((hperh->init.consumer_trig >> 4) & 0x0F);
-	hperh->consumer_pos = (1U << (uint32_t)((hperh->init.consumer_trig >> 8) & 0xFF));
-
-	if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) {
-		__UNLOCK(hperh);
-		return BUSY;
-	}
-
-	MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS);
-	MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS);
-
-	if (hperh->init.producer_clk == hperh->init.consumer_clk) {
-		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_DIRECT << PIS_CH0_CON_SYNCSEL_POSS);
-		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, (hperh->init.consumer_clk) << PIS_CH0_CON_PULCK_POSS);
-	}
-	else {
-		if (hperh->init.producer_signal == PIS_OUT_LEVEL) {
-			if (hperh->init.consumer_clk == PIS_CLK_PCLK1)
-				MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_APB1 << PIS_CH0_CON_SYNCSEL_POSS);
-			if (hperh->init.consumer_clk == PIS_CLK_PCLK2)
-				MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_APB2 << PIS_CH0_CON_SYNCSEL_POSS);
-			if (hperh->init.consumer_clk == PIS_CLK_SYS)
-				MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS);
-		}
-
-		if (hperh->init.producer_signal == PIS_OUT_PULSE) {
-			if (hperh->init.consumer_clk == PIS_CLK_PCLK1)
-				MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_APB1 << PIS_CH0_CON_SYNCSEL_POSS);
-			if (hperh->init.consumer_clk == PIS_CLK_PCLK2)
-				MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_APB2 << PIS_CH0_CON_SYNCSEL_POSS);
-			if (hperh->init.consumer_clk == PIS_CLK_SYS)
-				MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS);
-		}
-	}
-
-	MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS);
-	MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS);
-	hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch];
-
-	/* enable consumer bit, switch pin of consumer */
-	if (hperh->init.input_chan == PIS_CHAN_INPUT) {
-		switch (hperh->consumer_con) {
-		case PIS_CON_0:
-			PIS->TAR_CON0 |= hperh->consumer_pos;
-			break;
-		case PIS_CON_1:
-			PIS->TAR_CON1 |= hperh->consumer_pos;
-			break;
-		default:
-			break;
-		}
-	}
-
-	__UNLOCK(hperh);
-	return OK;
-}
-
-/**
-  * @brief  Destroy the PIS mode according to the specified parameters in
-  *         the pis_init_t and create the associated handle.
-  * @param  hperh: Pointer to a pis_handle_t structure that contains
-  *         the configuration information for the specified PIS module.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_pis_destroy(pis_handle_t *hperh)
-{
-	assert_param(IS_PIS(hperh->perh));
-
-	if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch])
-		return ERROR;
-
-	__LOCK(hperh);
-
-	CLEAR_BIT(PIS->CH_OER, (1U << (uint32_t)hperh->consumer_ch));
-	WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0);
-
-	switch (hperh->consumer_con) {
-	case PIS_CON_0:
-		PIS->TAR_CON0 &= ~(hperh->consumer_pos);
-		break;
-	case PIS_CON_1:
-		PIS->TAR_CON1 &= ~(hperh->consumer_pos);
-		break;
-	default:
-		break;
-	}
-
-	hperh->state = PIS_STATE_RESET;
-	__UNLOCK(hperh);
-
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup PIS_Public_Functions_Group2 Operation functions
-  * @brief PIS output enable or disable functions
-  * @{
-  */
-
-/**
-  * @brief  Start the PIS output function.
-  * @param  hperh: Pointer to a pis_handle_t structure that contains
-  *         the configuration information for the specified PIS module.
-  * @param  ch: The PIS channel enable output
-  *	    This parameter can be one of the following values:
-  *		@arg PIS_OUT_CH_0
-  *		@arg PIS_OUT_CH_1
-  *		@arg PIS_OUT_CH_2
-  *		@arg PIS_OUT_CH_3
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch)
-{
-	assert_param(IS_PIS(hperh->perh));
-	assert_param(IS_PIS_OUPUT_CH(ch));
-	__LOCK(hperh);
-	SET_BIT(PIS->CH_OER, (1 << (uint32_t)ch));
-	__UNLOCK(hperh);
-
-	return OK;
-}
-
-/**
-  * @brief  Stop the PIS output function.
-  * @param  hperh: Pointer to a pis_handle_t structure that contains
-  *         the configuration information for the specified PIS module.
-  * @param  ch: The PIS channel disable output
-  *	    This parameter can be one of the following values:
-  *		@arg PIS_OUT_CH_0
-  *		@arg PIS_OUT_CH_1
-  *		@arg PIS_OUT_CH_2
-  *		@arg PIS_OUT_CH_3
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch)
-{
-	assert_param(IS_PIS(hperh->perh));
-	assert_param(IS_PIS_OUPUT_CH(ch));
-	__LOCK(hperh);
-	CLEAR_BIT(PIS->CH_OER, (1 << (uint32_t)ch));
-	__UNLOCK(hperh);
-
-	return OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup PIS_Public_Functions_Group3 Peripheral State and Errors functions
-  *  @brief   PIS State and Errors functions
-  * @{
-  */
-
-/**
-  * @brief  Returns the PIS state.
-  * @param  hperh: Pointer to a pis_handle_t structure that contains
-  *         the configuration information for the specified PIS module.
-  * @retval ALD state
-  */
-pis_state_t ald_pis_get_state(pis_handle_t *hperh)
-{
-	assert_param(IS_PIS(hperh->perh));
-	return hperh->state;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PIS_Public_Functions_Group4 modulate output functions
-  *  @brief   PIS modulate output signal functions
-  * @{
-  */
-
-/**
-  * @brief  Config the PIS modulate signal function
-  * @param  hperh: Pointer to a pis_handle_t structure that contains
-  *         the configuration information for the specified PIS module.
-  * @param  config: Pointer to a pis_modulate_config_t structure that
-  *         contains the selected target (UART0,UART1,UART2,UART3 or
-  *         LPUART0) how to modulate the target output signal.
-  * @retval Status, see @ref ald_status_t.
-  */
-ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config)
-{
-	assert_param(IS_PIS(hperh->perh));
-	assert_param(IS_PIS_MODU_TARGET(config->target));
-	assert_param(IS_PIS_MODU_LEVEL(config->level));
-	assert_param(IS_PIS_MODU_SRC(config->src));
-	assert_param(IS_PIS_MODU_CHANNEL(config->channel));
-	__LOCK(hperh);
-
-	switch (config->target) {
-	case PIS_UART0_TX:
-		MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMLVLS_MSK, config->level << PIS_UART0_TXMCR_TXMLVLS_POS);
-		MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMSS_MSK, config->src << PIS_UART0_TXMCR_TXMSS_POSS);
-		MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXSIGS_MSK, config->channel << PIS_UART0_TXMCR_TXSIGS_POSS);
-		break;
-
-	case PIS_UART1_TX:
-		MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMLVLS_MSK, config->level << PIS_UART1_TXMCR_TXMLVLS_POS);
-		MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMSS_MSK, config->src << PIS_UART1_TXMCR_TXMSS_POSS);
-		MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXSIGS_MSK, config->channel << PIS_UART1_TXMCR_TXSIGS_POSS);
-		break;
-
-	case PIS_UART2_TX:
-		MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMLVLS_MSK, config->level << PIS_UART2_TXMCR_TXMLVLS_POS);
-		MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMSS_MSK, config->src << PIS_UART2_TXMCR_TXMSS_POSS);
-		MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXSIGS_MSK, config->channel << PIS_UART2_TXMCR_TXSIGS_POSS);
-		break;
-
-	case PIS_UART3_TX:
-		MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMLVLS_MSK, config->level << PIS_UART3_TXMCR_TXMLVLS_POS);
-		MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMSS_MSK, config->src << PIS_UART3_TXMCR_TXMSS_POSS);
-		MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXSIGS_MSK, config->channel << PIS_UART3_TXMCR_TXSIGS_POSS);
-		break;
-
-	case PIS_LPUART0_TX:
-		MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXMLVLS_MSK, config->level << PIS_LPUART0_TXMCR_TXMLVLS_POS);
-		MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXMSS_MSK, config->src << PIS_LPUART0_TXMCR_TXMSS_POSS);
-		MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXSIGS_MSK, config->channel << PIS_LPUART0_TXMCR_TXSIGS_POSS);
-		break;
-
-	default:
-		break;
-	}
-
-	__UNLOCK(hperh);
-	return OK;
-}
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-#endif /* ALD_PIS */
-/**
-  * @}
-  */
-/**
-  * @}
-  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_pmu.c

@@ -1,356 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_pmu.c
-  * @brief   PMU module driver.
-  *
-  * @version V1.0
-  * @date    04 Dec 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          04 Dec 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#include "ald_conf.h"
-
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup PMU PMU
-  * @brief PMU module driver
-  * @{
-  */
-#ifdef ALD_PMU
-
-
-/** @defgroup PMU_Private_Functions PMU Private Functions
-  * @{
-  */
-
-/**
-  * @brief  PMU module interrupt handler
-  * @retval None
-  */
-void ald_lvd_irq_handler(void)
-{
-	SYSCFG_UNLOCK();
-	SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
-	SYSCFG_LOCK();
-
-	return;
-}
-/**
-  * @}
-  */
-
-/** @defgroup PMU_Public_Functions PMU Public Functions
-  * @{
-  */
-
-/** @addtogroup PMU_Public_Functions_Group1 Low Power Mode
-  * @brief Low power mode select functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### Low power mode select functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Enter stop1 mode.
-      (+) Enter stop2 mode.
-      (+) Enter standby mode.
-      (+) Get wakeup status.
-      (+) Clear wakeup status.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enter stop1 mode
-  * @retval None
-  */
-void ald_pmu_stop1_enter(void)
-{
-	int cnt = 4000;
-
-	SYSCFG_UNLOCK();
-	
-	CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);
-#ifdef ES32F336x  /* MCU Series: ES32F336x */
-	SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK);
-#endif
-	MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, PMU_LDO_18_HOLD << PMU_CR1_LDO18MOD_POSS);
-	MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STOP1 << PMU_CR0_LPM_POSS);
-	SYSCFG_LOCK();
-
-	while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--));
-
-	SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
-	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-	__WFI();
-	SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
-
-	return;
-}
-
-/**
-  * @brief  Enter stop2 mode
-  * @retval None
-  */
-void ald_pmu_stop2_enter(void)
-{
-	int cnt = 4000;
-
-	SYSCFG_UNLOCK();
-
-	SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);
-#ifdef ES32F336x  /* MCU Series: ES32F336x */
-	SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK);
-#endif
-	MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, PMU_LDO_18_HOLD << PMU_CR1_LDO18MOD_POSS);
-	MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STOP2 << PMU_CR0_LPM_POSS);
-	SYSCFG_LOCK();
-
-	while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--));
-
-	SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
-	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-	__WFI();
-	SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
-
-	return;
-}
-
-/**
-  * @brief  Enter standby mode
-  * @param  port: The port whick wake up the standby mode.
-  * @param  level: Wakeup level.
-  * @retval None
-  */
-void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
-{
-	ald_bkpc_standby_wakeup_config(port, level);
-
-	SYSCFG_UNLOCK();
-	MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STANDBY << PMU_CR0_LPM_POSS);
-	SYSCFG_LOCK();
-
-	SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
-	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-	__WFI();
-	SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
-
-	return;
-}
-
-/**
-  * @brief  Enable/Disable LDO(1.2V) hold mode. It must be disabled in STOP1.
-  * @param  state: Enable/Disable
-  * @retval None
-  */
-void ald_pmu_ldo_12_config(type_func_t state)
-{
-	assert_param(IS_FUNC_STATE(state));
-	SYSCFG_UNLOCK();
-
-	if (state)
-		SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);
-	else
-		CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);
-
-	SYSCFG_LOCK();
-	return;
-}
-
-/**
-  * @brief  Configure LDO(1.8V) mode
-  * @param  mode: Mode of the LDO(1.8V)
-  * @retval None
-  */
-void ald_pmu_ldo_18_config(pmu_ldo_18_mode_t mode)
-{
-	uint32_t cnt = 4000;
-
-	assert_param(IS_PMU_LDO18_MODE(mode));
-
-	SYSCFG_UNLOCK();
-	MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, mode << PMU_CR1_LDO18MOD_POSS);
-	SYSCFG_LOCK();
-
-	while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--));
-	return;
-}
-
-#ifdef ES32F336x  /* MCU Series: ES32F336x */
-
-/**
-  * @brief  Configures low power mode. The system clock must
-  *         be less than 2MHz. Such as: LOSC or LRC.
-  * @param  vol: LDO output voltage select in low power mode.
-  * @param  state: New state, ENABLE/DISABLE;
-  * @retval None
-  */
-void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state)
-{
-	assert_param(IS_FUNC_STATE(state));
-	SYSCFG_UNLOCK();
-
-	if (state) {
-		assert_param(IS_PMU_LDO_LPMODE_OUTPUT(vol));
-
-		MODIFY_REG(PMU->CR0, PMU_CR0_LPVS_MSK, vol << PMU_CR0_LPVS_POSS);
-		SET_BIT(PMU->CR0, PMU_CR0_LPRUN_MSK);
-	}
-	else {
-		CLEAR_BIT(PMU->CR0, PMU_CR0_LPRUN_MSK);
-	}
-
-	SYSCFG_LOCK();
-	return;
-}
-#endif
-
-/**
-  * @brief  Get wakup status.
-  * @param  sr: Status bit.
-  * @retval Status.
-  */
-flag_status_t ald_pmu_get_status(pmu_status_t sr)
-{
-	assert_param(IS_PMU_STATUS(sr));
-
-	if (READ_BIT(PMU->SR, sr))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Clear wakup status.
-  * @param  sr: Status bit.
-  * @retval None
-  */
-void ald_pmu_clear_status(pmu_status_t sr)
-{
-	assert_param(IS_PMU_STATUS(sr));
-	SYSCFG_UNLOCK();
-
-	if (sr == PMU_SR_WUF)
-		SET_BIT(PMU->CR0, PMU_CR0_CWUF_MSK);
-	else if (sr == PMU_SR_STANDBYF)
-		SET_BIT(PMU->CR0, PMU_CR0_CSTANDBYF_MSK);
-	else
-		;/* do nothing */
-
-	SYSCFG_LOCK();
-	return;
-}
-
-/**
-  * @brief  Configure peripheral power
-  * @param  perh: The peripheral
-  * @param  state: ENABLE/DISABLE
-  * @retval None
-  */
-void ald_pmu_perh_power_config(pmu_perh_power_t perh, type_func_t state)
-{
-	assert_param(IS_PMU_PERH_POWER(perh));
-	assert_param(IS_FUNC_STATE(state));
-
-	SYSCFG_UNLOCK();
-
-	if (state)
-		SET_BIT(PMU->PWRCR, perh);
-	else
-		CLEAR_BIT(PMU->PWRCR, perh);
-
-	SYSCFG_LOCK();
-	return;
-}
-/**
-  * @}
-  */
-
-/** @addtogroup PMU_Public_Functions_Group2 LVD Configure
-  * @brief LVD configure functions
-  *
-  * @verbatim
-  ==============================================================================
-              ##### LVD configure functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure lvd parameters.
-
-    @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configure lvd using specified parameters.
-  * @param  sel: LVD threshold voltage.
-  * @param  mode: LVD trigger mode.
-  * @param  state: New state, ENABLE/DISABLE;
-  * @retval None
-  */
-void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state)
-{
-	assert_param(IS_FUNC_STATE(state));
-	SYSCFG_UNLOCK();
-
-	if (state) {
-		assert_param(IS_PMU_LVD_VOL_SEL(sel));
-		assert_param(IS_PMU_LVD_TRIGGER_MODE(mode));
-
-		MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS);
-		MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS);
-		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK);
-		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
-		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
-		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
-	}
-	else {
-		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
-		CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
-		CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
-	}
-
-	SYSCFG_LOCK();
-	return;
-}
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-#endif /* ALD_PMU */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_rmu.c

@@ -1,161 +0,0 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_rmu.c
-  * @brief   RMU module driver.
-  *
-  * @version V1.0
-  * @date    04 Dec 2019
-  * @author  AE Team
-  * @note
-  *          Change Logs:
-  *          Date            Author          Notes
-  *          04 Dec 2019     AE Team         The first version
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  * SPDX-License-Identifier: Apache-2.0
-  *
-  * Licensed under the Apache License, Version 2.0 (the License); you may
-  * not use this file except in compliance with the License.
-  * You may obtain a copy of the License at
-  *
-  * www.apache.org/licenses/LICENSE-2.0
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  **********************************************************************************
-  */
-
-#include "ald_conf.h"
-
-/** @addtogroup ES32FXXX_ALD
-  * @{
-  */
-
-/** @defgroup RMU RMU
-  * @brief RMU module driver
-  * @{
-  */
-#ifdef ALD_RMU
-
-/** @defgroup RMU_Public_Functions RMU Public Functions
-  * @{
-  */
-
-/**
-  * @brief  Configure BOR parameters.
-  * @param  flt: filter time.
-  * @param  vol: The voltage.
-  * @param  state: The new status: ENABLE/DISABLE.
-  * @retval None
-  */
-void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state)
-{
-	assert_param(IS_FUNC_STATE(state));
-
-	SYSCFG_UNLOCK();
-
-	if (state) {
-		assert_param(IS_RMU_BORFLT(flt));
-		assert_param(IS_RMU_BORVOL(vol));
-
-		MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS);
-		MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS);
-		SET_BIT(RMU->CR, RMU_CR_BOREN_MSK);
-	}
-	else {
-		CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK);
-	}
-
-	SYSCFG_LOCK();
-	return;
-}
-
-/**
-  * @brief  Get specified reset status
-  * @param  state: Speicifies the type of the reset,
-  * @retval The status.
-  */
-uint32_t ald_rmu_get_reset_status(rmu_state_t state)
-{
-	assert_param(IS_RMU_STATE(state));
-
-	if (state == RMU_RST_ALL)
-		return RMU->RSTSR;
-
-	if (READ_BIT(RMU->RSTSR, state))
-		return SET;
-
-	return RESET;
-}
-
-/**
-  * @brief  Clear the specified reset status
-  * @param  state: Specifies the type of the reset,
-  * @retval None
-  */
-void ald_rmu_clear_reset_status(rmu_state_t state)
-{
-	assert_param(IS_RMU_STATE_CLEAR(state));
-
-	SYSCFG_UNLOCK();
-	WRITE_REG(RMU->CRSTSR, state);
-	SYSCFG_LOCK();
-
-	return;
-}
-/**
-  * @brief  Reset peripheral device
-  * @param  perh: The peripheral device,
-  * @retval None
-  */
-void ald_rmu_reset_periperal(rmu_peripheral_t perh)
-{
-	uint32_t idx, pos;
-
-	assert_param(IS_RMU_PERH(perh));
-
-	idx = ((uint32_t)perh >> 27) & 0x7;
-	pos = perh & ~(0x7 << 27);
-	SYSCFG_UNLOCK();
-
-	switch (idx) {
-	case 0:
-		WRITE_REG(RMU->AHB1RSTR, pos);
-		break;
-
-	case 1:
-		WRITE_REG(RMU->AHB2RSTR, pos);
-		break;
-
-	case 2:
-		WRITE_REG(RMU->APB1RSTR, pos);
-		break;
-
-	case 4:
-		WRITE_REG(RMU->APB2RSTR, pos);
-		break;
-
-	default:
-		break;
-	}
-
-	SYSCFG_LOCK();
-	return;
-}
-
-/**
-  * @}
-  */
-#endif /* ALD_RMU */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */