@@ -41,7 +41,11 @@ void usb_dc_low_level_init(uint8_t busid)
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||||
usb_phy_config_t phy_config = {
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||||
.controller = USB_PHY_CTRL_OTG,
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.otg_mode = USB_OTG_MODE_DEVICE,
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#if CONFIG_IDF_TARGET_ESP32P4 // ESP32-P4 has 2 USB-DWC peripherals, each with its dedicated PHY. We support HS+UTMI only ATM.
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.target = USB_PHY_TARGET_UTMI,
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#else
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.target = USB_PHY_TARGET_INT,
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#endif
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};
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||||
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||||
esp_err_t ret = usb_new_phy(&phy_config, &s_phy_handle);
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||||
@@ -87,7 +91,11 @@ void usb_hc_low_level_init(struct usbh_bus *bus)
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// Host Library defaults to internal PHY
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||||
usb_phy_config_t phy_config = {
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||||
.controller = USB_PHY_CTRL_OTG,
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||||
#if CONFIG_IDF_TARGET_ESP32P4 // ESP32-P4 has 2 USB-DWC peripherals, each with its dedicated PHY. We support HS+UTMI only ATM.
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||||
.target = USB_PHY_TARGET_UTMI,
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||||
#else
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||||
.target = USB_PHY_TARGET_INT,
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||||
#endif
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||||
.otg_mode = USB_OTG_MODE_HOST,
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||||
.otg_speed = USB_PHY_SPEED_UNDEFINED, // In Host mode, the speed is determined by the connected device
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||||
.ext_io_conf = NULL,
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||||
@@ -136,16 +144,25 @@ void usbd_dwc2_delay_ms(uint8_t ms)
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void usb_dcache_clean(uintptr_t addr, size_t size)
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{
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||||
if (size == 0)
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||||
return;
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||||
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||||
esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M);
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}
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||||
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||||
void usb_dcache_invalidate(uintptr_t addr, size_t size)
|
||||
{
|
||||
if (size == 0)
|
||||
return;
|
||||
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||||
esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_M2C);
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||||
}
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||||
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||||
void usb_dcache_flush(uintptr_t addr, size_t size)
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||||
{
|
||||
if (size == 0)
|
||||
return;
|
||||
|
||||
esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_DIR_M2C);
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user