From f0d93dcdc18c9a341a87cc1af7d3dc898bcf01c2 Mon Sep 17 00:00:00 2001 From: HalfSweet Date: Mon, 11 Aug 2025 13:15:59 +0800 Subject: [PATCH] feat: Add MUSB IP without multipoint feature support --- cherryusb_config_template.h | 1 + port/musb/usb_hc_musb.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/cherryusb_config_template.h b/cherryusb_config_template.h index 1e8aab74..2f788eb0 100644 --- a/cherryusb_config_template.h +++ b/cherryusb_config_template.h @@ -301,6 +301,7 @@ /* ---------------- MUSB Configuration ---------------- */ #define CONFIG_USB_MUSB_PIPE_NUM 8 // #define CONFIG_USB_MUSB_SUNXI +// #define CONFIG_USB_MUSB_WITHOUT_MULTIPOINT /* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, * the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. diff --git a/port/musb/usb_hc_musb.c b/port/musb/usb_hc_musb.c index eea625cc..cb2002dd 100644 --- a/port/musb/usb_hc_musb.c +++ b/port/musb/usb_hc_musb.c @@ -328,10 +328,16 @@ void musb_control_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb speed = USB_TYPE0_SPEED_LOW; } +#ifdef CONFIG_USB_MUSB_WITHOUT_MULTIPOINT + /* Without multipoint, use FADDR for host target addressing and do not access Hub/FuncAddr regs */ + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = (urb->hport->dev_addr & 0x7F); + HWREGB(USB_TXTYPE_BASE(chidx)) = speed; +#else HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; HWREGB(USB_TXTYPE_BASE(chidx)) = speed; HWREGB(USB_TXHUBADDR_BASE(chidx)) = 0; HWREGB(USB_TXHUBPORT_BASE(chidx)) = 0; +#endif musb_write_packet(bus, chidx, (uint8_t *)setup, 8); HWREGB(USB_TXCSRL_BASE(chidx)) = USB_CSRL0_TXRDY | USB_CSRL0_SETUP; @@ -360,12 +366,19 @@ int musb_bulk_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb return -USB_ERR_RANGE; } +#ifdef CONFIG_USB_MUSB_WITHOUT_MULTIPOINT + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = (urb->hport->dev_addr & 0x7F); + HWREGB(USB_RXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; + HWREGH(USB_RXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + HWREGB(USB_RXINTERVAL_BASE(chidx)) = 0; +#else HWREGB(USB_RXADDR_BASE(chidx)) = urb->hport->dev_addr; HWREGB(USB_RXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; HWREGH(USB_RXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); HWREGB(USB_RXINTERVAL_BASE(chidx)) = 0; HWREGB(USB_RXHUBADDR_BASE(chidx)) = 0; HWREGB(USB_RXHUBPORT_BASE(chidx)) = 0; +#endif HWREGB(USB_TXCSRH_BASE(chidx)) &= ~USB_TXCSRH1_MODE; HWREGB(USB_RXCSRL_BASE(chidx)) = USB_RXCSRL1_REQPKT; @@ -376,12 +389,19 @@ int musb_bulk_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb return -USB_ERR_RANGE; } +#ifdef CONFIG_USB_MUSB_WITHOUT_MULTIPOINT + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = (urb->hport->dev_addr & 0x7F); + HWREGB(USB_TXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; + HWREGH(USB_TXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + HWREGB(USB_TXINTERVAL_BASE(chidx)) = 0; +#else HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; HWREGB(USB_TXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; HWREGH(USB_TXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); HWREGB(USB_TXINTERVAL_BASE(chidx)) = 0; HWREGB(USB_TXHUBADDR_BASE(chidx)) = 0; HWREGB(USB_TXHUBPORT_BASE(chidx)) = 0; +#endif if (buflen > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { buflen = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); @@ -419,12 +439,19 @@ int musb_intr_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb return -USB_ERR_RANGE; } +#ifdef CONFIG_USB_MUSB_WITHOUT_MULTIPOINT + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = (urb->hport->dev_addr & 0x7F); + HWREGB(USB_RXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; + HWREGH(USB_RXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + HWREGB(USB_RXINTERVAL_BASE(chidx)) = urb->ep->bInterval; +#else HWREGB(USB_RXADDR_BASE(chidx)) = urb->hport->dev_addr; HWREGB(USB_RXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; HWREGH(USB_RXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); HWREGB(USB_RXINTERVAL_BASE(chidx)) = urb->ep->bInterval; HWREGB(USB_RXHUBADDR_BASE(chidx)) = 0; HWREGB(USB_RXHUBPORT_BASE(chidx)) = 0; +#endif HWREGB(USB_TXCSRH_BASE(chidx)) &= ~USB_TXCSRH1_MODE; HWREGB(USB_RXCSRL_BASE(chidx)) = USB_RXCSRL1_REQPKT; @@ -435,12 +462,19 @@ int musb_intr_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb return -USB_ERR_RANGE; } +#ifdef CONFIG_USB_MUSB_WITHOUT_MULTIPOINT + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = (urb->hport->dev_addr & 0x7F); + HWREGB(USB_TXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; + HWREGH(USB_TXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + HWREGB(USB_TXINTERVAL_BASE(chidx)) = urb->ep->bInterval; +#else HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; HWREGB(USB_TXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; HWREGH(USB_TXMAP_BASE(chidx)) = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); HWREGB(USB_TXINTERVAL_BASE(chidx)) = urb->ep->bInterval; HWREGB(USB_TXHUBADDR_BASE(chidx)) = 0; HWREGB(USB_TXHUBPORT_BASE(chidx)) = 0; +#endif if (buflen > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { buflen = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize);