add ehci power config
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@@ -87,10 +87,10 @@ struct usb_ehci_qh_s {
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struct usb_ehci_epinfo_s *epinfo; /* Endpoint used for the transfer */
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uint32_t fqp; /* First qTD in the list (physical address) */
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#if (__riscv_xlen == 64)
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uint8_t pad[4]; /* Padding to assure 32-byte alignment */
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#if (CONFIG_DCACHE_LINE_SIZE == 64)
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uint8_t pad[4]; /* Padding to assure 64-byte alignment */
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#else
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uint8_t pad[8]; /* Padding to assure 32-byte alignment */
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uint8_t pad[8]; /* Padding to assure 32-byte alignment */
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#endif
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};
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@@ -2168,7 +2168,13 @@ int usb_hc_hw_init(void)
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if (ret < 0) {
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return -2;
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}
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#ifdef CONFIG_USB_EHCI_PORT_POWER
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for (uint8_t port = 1; i <= CONFIG_USBHOST_RHPORTS; port++) {
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regval = usb_ehci_getreg(&HCOR->portsc[port - 1]);
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regval |= EHCI_PORTSC_PP;
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usb_ehci_putreg(regval, &HCOR->portsc[port - 1]);
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}
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#endif
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/* Enable EHCI interrupts. Interrupts are still disabled at the level of
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* the interrupt controller.
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*/
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@@ -2228,11 +2234,11 @@ int usbh_reset_port(const uint8_t port)
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return 0;
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}
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__WEAK uint8_t usbh_get_port_speed(const uint8_t port)
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{
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/* Defined by individual manufacturers */
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return 0;
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}
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// __WEAK uint8_t usbh_get_port_speed(const uint8_t port)
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// {
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// /* Defined by individual manufacturers */
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// return 0;
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// }
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int usbh_ep0_reconfigure(usbh_epinfo_t ep, uint8_t dev_addr, uint8_t ep_mps, uint8_t speed)
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{
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@@ -123,6 +123,7 @@
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#define CONFIG_USB_EHCI_QTD_NUM (10)
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// #define CONFIG_USB_EHCI_INFO_ENABLE
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// #define CONFIG_USB_ECHI_HCOR_RESERVED_DISABLE
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#define CONFIG_USB_EHCI_CONFIGFLAG
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// #define CONFIG_USB_EHCI_CONFIGFLAG
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// #define CONFIG_USB_EHCI_PORT_POWER
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#endif
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