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Add FS support for ESP32-P4

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This commit is contained in:
LiPeng
2025-07-14 19:59:11 +08:00
committed by sakumisu
parent f3b5025b64
commit d58037e3d4
3 changed files with 63 additions and 35 deletions
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7
osal/idf/usb_config.h
View File

@@ -247,9 +247,16 @@
#endif
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#define ESP_USB_FS0_BASE 0x60080000
#define ESP_USBD_BASE ESP_USB_FS0_BASE
#define ESP_USBH_BASE ESP_USB_FS0_BASE
#define CONFIG_USBDEV_MAX_BUS 1
#define CONFIG_USBHOST_MAX_BUS 1
#elif CONFIG_IDF_TARGET_ESP32P4
#define ESP_USB_HS0_BASE 0x50000000
#define ESP_USB_FS0_BASE 0x50040000
#define ESP_USBD_BASE ESP_USB_HS0_BASE
#define ESP_USBH_BASE ESP_USB_HS0_BASE
#define CONFIG_USBDEV_MAX_BUS 2
#define CONFIG_USBHOST_MAX_BUS 2
#define CONFIG_USB_HS

12
port/dwc2/usb_dc_dwc2.c
View File

@@ -1017,7 +1017,9 @@ void USBD_IRQHandler(uint8_t busid)
}
g_dwc2_udc[busid].out_ep[ep_idx].xfer_len = 0;
usb_dcache_invalidate((uintptr_t)g_dwc2_udc[busid].out_ep[ep_idx].xfer_buf, USB_ALIGN_UP(g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len, CONFIG_USB_ALIGN_SIZE));
if (g_dwc2_udc[busid].user_params.device_dma_enable) {
usb_dcache_invalidate((uintptr_t)g_dwc2_udc[busid].out_ep[ep_idx].xfer_buf, USB_ALIGN_UP(g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len, CONFIG_USB_ALIGN_SIZE));
}
usbd_event_ep_out_complete_handler(busid, 0x00, g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len);
if (usbd_get_ep0_next_state(busid) == USBD_EP0_STATE_SETUP) {
@@ -1027,7 +1029,9 @@ void USBD_IRQHandler(uint8_t busid)
} else {
g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len = g_dwc2_udc[busid].out_ep[ep_idx].xfer_len - ((USB_OTG_OUTEP(ep_idx)->DOEPTSIZ) & USB_OTG_DOEPTSIZ_XFRSIZ);
g_dwc2_udc[busid].out_ep[ep_idx].xfer_len = 0;
usb_dcache_invalidate((uintptr_t)g_dwc2_udc[busid].out_ep[ep_idx].xfer_buf, USB_ALIGN_UP(g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len, CONFIG_USB_ALIGN_SIZE));
if (g_dwc2_udc[busid].user_params.device_dma_enable) {
usb_dcache_invalidate((uintptr_t)g_dwc2_udc[busid].out_ep[ep_idx].xfer_buf, USB_ALIGN_UP(g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len, CONFIG_USB_ALIGN_SIZE));
}
usbd_event_ep_out_complete_handler(busid, ep_idx, g_dwc2_udc[busid].out_ep[ep_idx].actual_xfer_len);
}
}
@@ -1035,7 +1039,9 @@ void USBD_IRQHandler(uint8_t busid)
process_setup:
// clang-format on
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) {
usb_dcache_invalidate((uintptr_t)&g_dwc2_udc[busid].setup, USB_ALIGN_UP(8, CONFIG_USB_ALIGN_SIZE));
if (g_dwc2_udc[busid].user_params.device_dma_enable) {
usb_dcache_invalidate((uintptr_t)&g_dwc2_udc[busid].setup, USB_ALIGN_UP(8, CONFIG_USB_ALIGN_SIZE));
}
usbd_event_ep0_setup_complete_handler(busid, (uint8_t *)&g_dwc2_udc[busid].setup);
}
}

79
port/dwc2/usb_glue_esp.c
View File

@@ -14,6 +14,10 @@
#include "usbh_core.h"
#include "usb_dwc2_param.h"
#define GET_USB_INDEX(reg_base) 0
#define GET_USB_INTR_SOURCE(reg_base) ETS_USB_INTR_SOURCE
#define GET_USB_PHY_TARGET(reg_base) USB_PHY_TARGET_INT
#define GET_USB_PHY_SPEED(reg_base) USB_PHY_SPEED_UNDEFINED
#ifdef CONFIG_IDF_TARGET_ESP32S2
#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ
#define DEFAULT_USB_INTR_SOURCE ETS_USB_INTR_SOURCE
@@ -21,15 +25,24 @@
#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ
#define DEFAULT_USB_INTR_SOURCE ETS_USB_INTR_SOURCE
#elif CONFIG_IDF_TARGET_ESP32P4
#undef GET_USB_INDEX
#define GET_USB_INDEX(reg_base) ((reg_base) == (void*)ESP_USB_HS0_BASE ? 0 : 1)
#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
#define DEFAULT_USB_INTR_SOURCE ETS_USB_OTG_INTR_SOURCE
#define USB_FS_INTR_SOURCE ETS_USB_OTG11_CH0_INTR_SOURCE
#undef GET_USB_INTR_SOURCE
#define GET_USB_INTR_SOURCE(reg_base) ((reg_base) == (void*)ESP_USB_HS0_BASE ? DEFAULT_USB_INTR_SOURCE : USB_FS_INTR_SOURCE)
#undef GET_USB_PHY_TARGET
#define GET_USB_PHY_TARGET(reg_base) ((reg_base) == (void*)ESP_USB_HS0_BASE ? USB_PHY_TARGET_UTMI : USB_PHY_TARGET_INT)
#undef GET_USB_PHY_SPEED
#define GET_USB_PHY_SPEED(reg_base) ((reg_base) == (void*)ESP_USB_HS0_BASE ? USB_PHY_SPEED_HIGH : USB_PHY_SPEED_FULL)
#else
#define DEFAULT_CPU_FREQ_MHZ 160
#endif
uint32_t SystemCoreClock = (DEFAULT_CPU_FREQ_MHZ * 1000 * 1000);
static usb_phy_handle_t s_phy_handle = NULL;
static intr_handle_t s_interrupt_handle = NULL;
static usb_phy_handle_t s_phy_handle[SOC_USB_OTG_PERIPH_NUM] = {NULL};
static intr_handle_t s_interrupt_handle[SOC_USB_OTG_PERIPH_NUM] = {NULL};
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
const struct dwc2_user_params param_fs = {
@@ -123,29 +136,30 @@ const struct dwc2_user_params param_hs = {
static void usb_dc_interrupt_cb(void *arg_pv)
{
extern void USBD_IRQHandler(uint8_t busid);
USBD_IRQHandler(0);
uint8_t busid = (uintptr_t)arg_pv;
USBD_IRQHandler(busid);
}
void usb_dc_low_level_init(uint8_t busid)
{
esp_err_t ret;
void *reg_base = (void*)g_usbdev_bus[busid].reg_base;
usb_phy_config_t phy_config = {
.controller = USB_PHY_CTRL_OTG,
.otg_mode = USB_OTG_MODE_DEVICE,
#if CONFIG_IDF_TARGET_ESP32P4 // ESP32-P4 has 2 USB-DWC peripherals, each with its dedicated PHY. We support HS+UTMI only ATM.
.target = USB_PHY_TARGET_UTMI,
#else
.target = USB_PHY_TARGET_INT,
#endif
};
esp_err_t ret = usb_new_phy(&phy_config, &s_phy_handle);
phy_config.target = GET_USB_PHY_TARGET(reg_base);
phy_config.otg_speed = GET_USB_PHY_SPEED(reg_base);
ret = usb_new_phy(&phy_config, &s_phy_handle[GET_USB_INDEX(reg_base)]);
if (ret != ESP_OK) {
USB_LOG_ERR("USB Phy Init Failed!\r\n");
return;
}
uintptr_t arg = busid;
// TODO: Check when to enable interrupt
ret = esp_intr_alloc(DEFAULT_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, usb_dc_interrupt_cb, 0, &s_interrupt_handle);
ret = esp_intr_alloc(GET_USB_INTR_SOURCE(reg_base), ESP_INTR_FLAG_LOWMED, usb_dc_interrupt_cb, (void *)arg, &s_interrupt_handle[GET_USB_INDEX(reg_base)]);
if (ret != ESP_OK) {
USB_LOG_ERR("USB Interrupt Init Failed!\r\n");
return;
@@ -155,46 +169,46 @@ void usb_dc_low_level_init(uint8_t busid)
void usb_dc_low_level_deinit(uint8_t busid)
{
if (s_interrupt_handle) {
esp_intr_free(s_interrupt_handle);
s_interrupt_handle = NULL;
void *reg_base = (void*)g_usbdev_bus[busid].reg_base;
if (s_interrupt_handle[GET_USB_INDEX(reg_base)]) {
esp_intr_free(s_interrupt_handle[GET_USB_INDEX(reg_base)]);
s_interrupt_handle[GET_USB_INDEX(reg_base)] = NULL;
}
if (s_phy_handle) {
usb_del_phy(s_phy_handle);
s_phy_handle = NULL;
if (s_phy_handle[GET_USB_INDEX(reg_base)]) {
usb_del_phy(s_phy_handle[GET_USB_INDEX(reg_base)]);
s_phy_handle[GET_USB_INDEX(reg_base)] = NULL;
}
}
static void usb_hc_interrupt_cb(void *arg_pv)
{
extern void USBH_IRQHandler(uint8_t busid);
USBH_IRQHandler(0);
uint8_t busid = (uintptr_t)arg_pv;
USBH_IRQHandler(busid);
}
void usb_hc_low_level_init(struct usbh_bus *bus)
{
void *reg_base = (void*)bus->hcd.reg_base;
// Host Library defaults to internal PHY
usb_phy_config_t phy_config = {
.controller = USB_PHY_CTRL_OTG,
#if CONFIG_IDF_TARGET_ESP32P4 // ESP32-P4 has 2 USB-DWC peripherals, each with its dedicated PHY. We support HS+UTMI only ATM.
.target = USB_PHY_TARGET_UTMI,
#else
.target = USB_PHY_TARGET_INT,
#endif
.otg_mode = USB_OTG_MODE_HOST,
.otg_speed = USB_PHY_SPEED_UNDEFINED, // In Host mode, the speed is determined by the connected device
.ext_io_conf = NULL,
.otg_io_conf = NULL,
};
phy_config.target = GET_USB_PHY_TARGET(reg_base);
esp_err_t ret = usb_new_phy(&phy_config, &s_phy_handle);
esp_err_t ret = usb_new_phy(&phy_config, &s_phy_handle[GET_USB_INDEX(reg_base)]);
if (ret != ESP_OK) {
USB_LOG_ERR("USB Phy Init Failed!\r\n");
return;
}
uintptr_t arg = bus->busid;
// TODO: Check when to enable interrupt
ret = esp_intr_alloc(DEFAULT_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, usb_hc_interrupt_cb, 0, &s_interrupt_handle);
ret = esp_intr_alloc(GET_USB_INTR_SOURCE(reg_base), ESP_INTR_FLAG_LOWMED, usb_hc_interrupt_cb, (void*)(arg), &s_interrupt_handle[GET_USB_INDEX(reg_base)]);
if (ret != ESP_OK) {
USB_LOG_ERR("USB Interrupt Init Failed!\r\n");
return;
@@ -204,13 +218,14 @@ void usb_hc_low_level_init(struct usbh_bus *bus)
void usb_hc_low_level_deinit(struct usbh_bus *bus)
{
if (s_interrupt_handle) {
esp_intr_free(s_interrupt_handle);
s_interrupt_handle = NULL;
void *reg_base = (void*)bus->hcd.reg_base;
if (s_interrupt_handle[GET_USB_INDEX(reg_base)]) {
esp_intr_free(s_interrupt_handle[GET_USB_INDEX(reg_base)]);
s_interrupt_handle[GET_USB_INDEX(reg_base)] = NULL;
}
if (s_phy_handle) {
usb_del_phy(s_phy_handle);
s_phy_handle = NULL;
if (s_phy_handle[GET_USB_INDEX(reg_base)]) {
usb_del_phy(s_phy_handle[GET_USB_INDEX(reg_base)]);
s_phy_handle[GET_USB_INDEX(reg_base)] = NULL;
}
}
@@ -219,7 +234,7 @@ void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params)
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
memcpy(params, &param_fs, sizeof(struct dwc2_user_params));
#elif CONFIG_IDF_TARGET_ESP32P4
if (reg_base == 0x50000000UL) {
if (reg_base == ESP_USB_HS0_BASE) {
memcpy(params, &param_hs, sizeof(struct dwc2_user_params));
} else {
memcpy(params, &param_fs, sizeof(struct dwc2_user_params));