diff --git a/port/ehci/usb_glue_aic.c b/port/ehci/usb_glue_aic.c
index bb188b05..e986f9f4 100644
--- a/port/ehci/usb_glue_aic.c
+++ b/port/ehci/usb_glue_aic.c
@@ -14,64 +14,100 @@ extern void USBH_IRQHandler(uint8_t busid);
 
 static void aic_ehci_isr(void *arg)
 {
-    uint8_t busid = (uint8_t)arg;
+    struct usbh_bus *bus = (struct usbh_bus *)arg;
     extern void USBH_IRQHandler(uint8_t busid);
-    USBH_IRQHandler(busid);
+    USBH_IRQHandler(bus->hcd.hcd_id);
 }
 
-const uint8_t aic_irq_table[] = {
-    USB_HOST0_EHCI_IRQn,
-#ifdef HPM_USB1_BASE
-    USB_HOST1_EHCI_IRQn
+typedef struct aic_ehci_config {
+    uint32_t base_addr;
+    uint32_t clk_id;
+    uint32_t rst_id;
+    uint32_t phy_clk_id;
+    uint32_t phy_rst_id;
+    uint32_t irq_num;
+}aic_ehci_config_t;
+
+aic_ehci_config_t config[] = {
+#ifdef AIC_USING_USB0_HOST
+    {
+        USB_HOST0_BASE,
+        CLK_USBH0,
+        RESET_USBH0,
+        CLK_USB_PHY0,
+        RESET_USBPHY0,
+        USB_HOST0_EHCI_IRQn
+    },
+#else
+    {
+        0xFFFFFFFF,
+        0xFFFFFFFF,
+        0xFFFFFFFF,
+        0xFFFFFFFF,
+        0xFFFFFFFF,
+        0xFFFFFFFF
+    },
+#endif
+#ifdef AIC_USING_USB1_HOST
+    {
+        USB_HOST1_BASE,
+        CLK_USBH1,
+        RESET_USBH1,
+        CLK_USB_PHY1,
+        RESET_USBPHY1,
+        USB_HOST1_EHCI_IRQn
+    }
 #endif
 };
 
 void usb_hc_low_level_init(struct usbh_bus *bus)
 {
     uint32_t val;
+    int i = 0;
+
+    for (i=0; i<sizeof(config)/sizeof(aic_ehci_config_t); i++) {
+        if (bus->hcd.reg_base == config[i].base_addr)
+            break;
+    }
+
+    if (i == sizeof(config)/sizeof(aic_ehci_config_t))
+        return;
 
     /* set usb0 phy switch: Host/Device */
-#ifdef AIC_USING_USB0_HOST
-    syscfg_usb_phy0_sw_host(1);
-#endif
+    if (i == 0)
+        syscfg_usb_phy0_sw_host(1);
+
+    /* enable clock */
+    hal_clk_enable(config[i].phy_clk_id);
+    hal_clk_enable(config[i].clk_id);
+    aicos_udelay(300);
+    hal_reset_assert(config[i].phy_rst_id);
+    hal_reset_assert(config[i].rst_id);
+    aicos_udelay(300);
+    hal_reset_deassert(config[i].phy_rst_id);
+    hal_reset_deassert(config[i].rst_id);
+    aicos_udelay(300);
 
     /* set phy type: UTMI/ULPI */
-    val = readl((volatile void *)(unsigned long)(bus->hcd.reg_base+0x800));
+    val = readl((volatile void *)(unsigned long)(config[i].base_addr+0x800));
 #ifdef FPGA_BOARD_ARTINCHIP
     /* fpga phy type = ULPI */
-    writel((val  & ~0x1U), (volatile void *)(unsigned long)(bus->hcd.reg_base+0x800));
+    writel((val  & ~0x1U), (volatile void *)(unsigned long)(config[i].base_addr+0x800));
 #else
     /* board phy type = UTMI */
-    writel((val | 0x1), (volatile void *)(unsigned long)(bus->hcd.reg_base+0x800));
+    writel((val | 0x1), (volatile void *)(unsigned long)(config[i].base_addr+0x800));
 #endif
 
-#if 0
     /* Set AHB2STBUS_INSREG01
         Set EHCI packet buffer IN/OUT threshold (in DWORDs)
         Must increase the OUT threshold to avoid underrun. (FIFO size - 4)
     */
-#ifdef FPGA_BOARD_ARTINCHIP
-    writel((32 | (127 << 16)), (volatile void *)(unsigned long)(bus->hcd.reg_base+0x94));
-#else
-    writel((32 | (32 << 16)), (volatile void *)(unsigned long)(bus->hcd.reg_base+0x94));
-#endif
-#endif
-
-    /* enable clock */
-    hal_clk_enable(CONFIG_USB_EHCI_PHY_CLK);
-    hal_clk_enable(CONFIG_USB_EHCI_CLK);
-    aicos_udelay(300);
-    hal_reset_assert(CONFIG_USB_EHCI_PHY_RESET);
-    hal_reset_assert(CONFIG_USB_EHCI_RESET);
-    aicos_udelay(300);
-    hal_reset_deassert(CONFIG_USB_EHCI_PHY_RESET);
-    hal_reset_deassert(CONFIG_USB_EHCI_RESET);
-    aicos_udelay(300);
+    writel((32 | (127 << 16)), (volatile void *)(unsigned long)(config[i].base_addr+0x94));
 
     /* register interrupt callback */
-    aicos_request_irq(aic_irq_table[bus->hcd.hcd_id], (irq_handler_t)aic_ehci_isr,
-                      0, "usb_host_ehci", (void *)bus->hcd.hcd_id);
-    aicos_irq_enable(aic_irq_table[bus->hcd.hcd_id]);
+    aicos_request_irq(config[i].irq_num, (irq_handler_t)aic_ehci_isr,
+                      0, "usb_host_ehci", bus);
+    aicos_irq_enable(config[i].irq_num);
 }
 
 uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port)