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add nocache ram config when enable dcache

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This commit is contained in:
sakumisu
2022-07-31 15:57:59 +08:00
parent 7dd7285e3a
commit b835c9ccd2
25 changed files with 108 additions and 84 deletions
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8
CMakeLists.txt
View File

@@ -11,8 +11,8 @@ sdk_inc(class/video)
if(CONFIG_CHERRYUSB_DEVICE)
sdk_src(core/usbd_core.c)
sdk_src(port/hpm/usb_dc_hpm.c)
sdk_compile_definitions(-DCONFIG_USB_ALIGN32 -DCONFIG_USB_HS)
sdk_compile_definitions(-DCONFIG_DCACHE_LINE_SIZE=64 -DCONFIG_USB_DCACHE_ENABLE)
sdk_compile_definitions(-DCONFIG_USB_HS -DCONFIG_USB_ALIGN_SIZE=64)
#sdk_compile_definitions(-DCONFIG_USB_DCACHE_ENABLE)
if(CONFIG_CHERRYUSB_DEVICE_CDC)
sdk_src(class/cdc/usbd_cdc.c)
endif()
@@ -33,6 +33,10 @@ if(CONFIG_CHERRYUSB_DEVICE_DEMO_CDC)
sdk_src(demo/cdc_acm_template.c)
endif()
if(CONFIG_CHERRYUSB_DEVICE_DEMO_CDC_MSC)
sdk_src(demo/cdc_acm_msc_template.c)
endif()
endif()

2
class/hub/usbh_hub.c
View File

@@ -29,7 +29,7 @@ static uint32_t g_devinuse = 0;
usb_slist_t hub_class_head = USB_SLIST_OBJECT_INIT(hub_class_head);
USB_MEM_ALIGN32 uint8_t int_buffer[6][USBH_HUB_INTIN_BUFSIZE];
USB_MEM_ALIGNX uint8_t int_buffer[6][USBH_HUB_INTIN_BUFSIZE];
extern void usbh_external_hport_connect(struct usbh_hubport *hport);
extern void usbh_external_hport_disconnect(struct usbh_hubport *hport);
extern void usbh_hport_activate(struct usbh_hubport *hport);

20
class/msc/usbd_msc.c
View File

@@ -34,6 +34,10 @@
#define MASS_STORAGE_BULK_EP_MPS 512
#endif
#ifndef CONFIG_USBDEV_MSC_BLOCK_SIZE
#define CONFIG_USBDEV_MSC_BLOCK_SIZE 512
#endif
#define MSC_THREAD_OP_READ_MEM 1
#define MSC_THREAD_OP_WRITE_MEM 2
#define MSC_THREAD_OP_WRITE_DONE 3
@@ -54,11 +58,11 @@ enum Stage {
};
/* Device data structure */
struct usbd_msc_cfg_priv {
USB_NOCACHE_RAM_SECTION struct usbd_msc_cfg_priv {
/* state of the bulk-only state machine */
enum Stage stage;
USB_MEM_ALIGN32 struct CBW cbw;
USB_MEM_ALIGN32 struct CSW csw;
USB_MEM_ALIGNX struct CBW cbw;
USB_MEM_ALIGNX struct CSW csw;
uint8_t sKey; /* Sense key */
uint8_t ASC; /* Additional Sense Code */
@@ -69,8 +73,7 @@ struct usbd_msc_cfg_priv {
uint32_t scsi_blk_addr;
uint32_t scsi_blk_len;
uint8_t *block_buffer;
uint8_t block_buffer[CONFIG_USBDEV_MSC_BLOCK_SIZE];
} usbd_msc_cfg;
/*memory OK (after a usbd_msc_memory_verify)*/
@@ -995,10 +998,11 @@ void usbd_msc_class_init(uint8_t out_ep, uint8_t in_ep)
memset((uint8_t *)&usbd_msc_cfg, 0, sizeof(struct usbd_msc_cfg_priv));
usbd_msc_get_cap(0, &usbd_msc_cfg.scsi_blk_nbr, &usbd_msc_cfg.scsi_blk_size);
if (usbd_msc_cfg.block_buffer == NULL) {
usbd_msc_cfg.block_buffer = usb_iomalloc(usbd_msc_cfg.scsi_blk_size * sizeof(uint8_t));
}
if (usbd_msc_cfg.scsi_blk_size > CONFIG_USBDEV_MSC_BLOCK_SIZE) {
USB_LOG_ERR("no enough block buffer\r\n");
return;
}
#ifdef CONFIG_USBDEV_MSC_THREAD
msc_sem = usb_osal_sem_create(1);
msc_thread = usb_osal_thread_create("usbd_msc", CONFIG_USBDEV_MSC_STACKSIZE, CONFIG_USBDEV_MSC_PRIO, usbd_msc_thread, NULL);

2
class/mtp/usbd_mtp.c
View File

@@ -25,7 +25,7 @@
/* Device data structure */
struct mtp_cfg_priv {
USB_MEM_ALIGN32 uint8_t device_status;
uint8_t device_status;
} usbd_mtp_cfg;
/* max USB packet size */

35
common/usb_mem.h
View File

@@ -23,24 +23,18 @@
#ifndef _USB_MEM_H
#define _USB_MEM_H
#ifndef CONFIG_DCACHE_LINE_SIZE
#define CONFIG_DCACHE_LINE_SIZE 32
#endif
#if defined(CONFIG_USB_DCACHE_ENABLE)
#define USB_NOCACHE_RAM_SECTION __attribute__((section(".nocache_ram")))
#define USB_MEM_ALIGN32 __attribute__((aligned(CONFIG_DCACHE_LINE_SIZE)))
#elif defined(CONFIG_USB_ALIGN32)
#define USB_NOCACHE_RAM_SECTION
#define USB_MEM_ALIGN32 __attribute__((aligned(32)))
#else
#define USB_NOCACHE_RAM_SECTION
#define USB_MEM_ALIGN32
#endif
#define usb_malloc(size) malloc(size)
#define usb_free(ptr) free(ptr)
#ifndef CONFIG_USB_ALIGN_SIZE
#define CONFIG_USB_ALIGN_SIZE 4
#endif
#ifndef USB_NOCACHE_RAM_SECTION
#define USB_NOCACHE_RAM_SECTION
#endif
#define USB_MEM_ALIGNX __attribute__((aligned(CONFIG_USB_ALIGN_SIZE)))
#ifdef CONFIG_USB_DCACHE_ENABLE
static inline void *usb_iomalloc(size_t size)
{
@@ -48,7 +42,7 @@ static inline void *usb_iomalloc(size_t size)
void *align_ptr;
int uintptr_size;
size_t align_size;
uint32_t align = CONFIG_DCACHE_LINE_SIZE;
uint32_t align = CONFIG_USB_ALIGN_SIZE;
/* sizeof pointer */
uintptr_size = sizeof(void *);
@@ -85,9 +79,18 @@ static inline void usb_iofree(void *ptr)
real_ptr = (void *)*(unsigned long *)((unsigned long)ptr - sizeof(void *));
usb_free(real_ptr);
}
void usb_dcache_clean(uintptr_t addr, uint32_t len);
void usb_dcache_invalidate(uintptr_t addr, uint32_t len);
void usb_dcache_clean_invalidate(uintptr_t addr, uint32_t len);
#else
#define usb_iomalloc(size) usb_malloc(size)
#define usb_iofree(ptr) usb_free(ptr)
#define usb_dcache_clean(addr, len)
#define usb_dcache_invalidate(addr, len)
#define usb_dcache_clean_invalidate(addr, len)
#endif
#endif

14
core/usbd_core.c
View File

@@ -38,9 +38,9 @@
#define USB_EP_OUT_NUM 8
#define USB_EP_IN_NUM 8
struct usbd_core_cfg_priv {
USB_NOCACHE_RAM_SECTION struct usbd_core_cfg_priv {
/** Setup packet */
USB_MEM_ALIGN32 struct usb_setup_packet setup;
USB_MEM_ALIGNX struct usb_setup_packet setup;
/** Pointer to data buffer */
uint8_t *ep0_data_buf;
/** Remaining bytes in buffer */
@@ -52,7 +52,7 @@ struct usbd_core_cfg_priv {
/** Pointer to registered descriptors */
const uint8_t *descriptors;
/* Buffer used for storing standard, class and vendor request data */
USB_MEM_ALIGN32 uint8_t req_data[CONFIG_USBDEV_REQUEST_BUFFER_LEN];
USB_MEM_ALIGNX uint8_t req_data[CONFIG_USBDEV_REQUEST_BUFFER_LEN];
usbd_endpoint_callback in_ep_cb[USB_EP_IN_NUM];
usbd_endpoint_callback out_ep_cb[USB_EP_OUT_NUM];
@@ -1009,12 +1009,14 @@ void usbd_event_ep0_setup_complete_handler(uint8_t *psetup)
usbd_core_cfg.ep0_data_buf_residue = MIN(usbd_core_cfg.ep0_data_buf_len,
setup->wLength);
#if defined(CONFIG_USB_DCACHE_ENABLE) || defined(CONFIG_USB_ALIGN32)
/* check if the data buf addr uses usbd_core_cfg.req_data */
if (((unsigned long)usbd_core_cfg.ep0_data_buf) != ((unsigned long)usbd_core_cfg.req_data)) {
/* check if the data buf addr matches align size,if not, copy into align buf */
#ifndef CONFIG_USBDEV_ALIGN_CHECK_DISABLE
if (((unsigned long)usbd_core_cfg.ep0_data_buf) & (CONFIG_USB_ALIGN_SIZE - 1)) {
#endif
/*copy data buf from misalign32 addr to align32 addr*/
memcpy(usbd_core_cfg.req_data, usbd_core_cfg.ep0_data_buf, usbd_core_cfg.ep0_data_buf_residue);
usbd_core_cfg.ep0_data_buf = usbd_core_cfg.req_data;
#ifndef CONFIG_USBDEV_ALIGN_CHECK_DISABLE
}
#endif
/*Send data or status to host*/

2
demo/audio_v1_mic_speaker_multichan_template.c
View File

@@ -165,7 +165,7 @@ static usbd_interface_t audio_stream_intf2;
#define AUDIO_OUT_EP_MPS 64
#endif
USB_MEM_ALIGN32 uint8_t out_buffer[AUDIO_OUT_EP_MPS];
USB_MEM_ALIGNX uint8_t out_buffer[AUDIO_OUT_EP_MPS];
uint32_t actual_read_length = 0;
void usbd_audio_out_callback(uint8_t ep)

4
demo/cdc_acm_hid_msc_template.c
View File

@@ -262,8 +262,8 @@ usbd_interface_t cdc_cmd_intf;
/*!< interface two */
usbd_interface_t cdc_data_intf;
uint8_t read_buffer[2048];
uint8_t write_buffer[2048] = { 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30 };
USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[2048];
USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[2048] = { 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30 };
volatile bool ep_tx_busy_flag = false;

4
demo/cdc_acm_msc_template.c
View File

@@ -105,8 +105,8 @@ usbd_interface_t cdc_cmd_intf;
/*!< interface two */
usbd_interface_t cdc_data_intf;
uint8_t read_buffer[2048];
uint8_t write_buffer[2048] = { 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30 };
USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[2048];
USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[2048] = { 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30 };
volatile bool ep_tx_busy_flag = false;

4
demo/cdc_acm_multi_template.c
View File

@@ -115,8 +115,8 @@ usbd_interface_t cdc_cmd_intf;
/*!< interface two */
usbd_interface_t cdc_data_intf;
uint8_t read_buffer[4][2048];
uint8_t write_buffer[4][2048] = { 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30 };
USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[4][2048];
USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[4][2048] = { 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30 };
volatile bool ep_tx_busy_flag = false;

4
demo/cdc_acm_template.c
View File

@@ -120,6 +120,10 @@ void usbd_cdc_acm_setup(void)
void usbd_cdc_acm_bulk_out(uint8_t ep, uint32_t nbytes)
{
USB_LOG_RAW("actual out len:%d\r\n", nbytes);
// for (int i = 0; i < 100; i++) {
// printf("%02x ", read_buffer[i]);
// }
// printf("\r\n");
/* setup next out ep read transfer */
usbd_ep_start_read(CDC_OUT_EP, read_buffer, 2048);
}

2
demo/hid_mouse_template.c
View File

@@ -198,7 +198,7 @@ static usbd_interface_t hid_intf;
static struct hid_mouse mouse_cfg;
/*!< hid state ! Data can be sent only when state is idle */
uint8_t hid_state = HID_STATE_IDLE;
static uint8_t hid_state = HID_STATE_IDLE;
/* function ------------------------------------------------------------------*/
static void usbd_hid_int_callback(uint8_t ep, uint32_t nbytes)

1
demo/hpm/usb_device/src/usb_config.h
View File

@@ -12,6 +12,7 @@
#define CONFIG_USB_PRINTF_COLOR_ENABLE
#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable")))
/* USB DEVICE Configuration */
/* core */
#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN

2
demo/stm32/usb_device/stm32f429igt6/MDK-ARM/stm32f429igt6.uvoptx
View File

@@ -521,7 +521,7 @@
<Group>
<GroupName>CherryUSB</GroupName>
<tvExp>1</tvExp>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>

2
demo/stm32/usb_device/stm32f429igt6/MDK-ARM/stm32f429igt6.uvprojx
View File

@@ -338,7 +338,7 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>USE_HAL_DRIVER,STM32F429xx,CONFIG_USB_DWC2_PORT=HS_PORT,CONFIG_USB_ALIGN32</Define>
<Define>USE_HAL_DRIVER,STM32F429xx,CONFIG_USB_DWC2_PORT=HS_PORT</Define>
<Undefine></Undefine>
<IncludePath>../Core/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include;..\..\..\..\..\class\cdc;..\..\..\..\..\core;..\..\..\..\..\common;..\..\..\..\..\class\video;..\..\..\..\..\class\msc;..\..\..\..\..\class\audio</IncludePath>
</VariousControls>

4
demo/stm32/usb_host/stm32h743xih6/Core/Src/main.c
View File

@@ -225,12 +225,12 @@ void cpu_mpu_config(uint8_t Region, uint8_t Mode, uint32_t Address, uint32_t Siz
}
void usb_dwc2_dcache_clean(uintptr_t addr, uint32_t len)
void usb_dcache_clean(uintptr_t addr, uint32_t len)
{
SCB_CleanDCache_by_Addr((uint32_t*)addr,len);
}
void usb_dwc2_dcache_invalidate(uintptr_t addr, uint32_t len)
void usb_dcache_invalidate(uintptr_t addr, uint32_t len)
{
SCB_InvalidateDCache_by_Addr((uint32_t*)addr,len);
}

6
demo/stm32/usb_host/stm32h743xih6/MDK-ARM/stm32h743xih6.uvprojx
View File

@@ -17,8 +17,8 @@
<TargetCommonOption>
<Device>STM32H743XIHx</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32H7xx_DFP.2.5.0</PackID>
<PackURL>https://www.keil.com/pack/</PackURL>
<PackID>Keil.STM32H7xx_DFP.2.8.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000-0x2001FFFF) IRAM2(0x24000000-0x2407FFFF) IROM(0x8000000-0x81FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE TZ</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@@ -338,7 +338,7 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>USE_HAL_DRIVER,STM32H743xx,STM32H7,CONFIG_USBHOST_HIGH_WORKQ,CONFIG_USB_DCACHE_ENABLE</Define>
<Define>USE_HAL_DRIVER,STM32H743xx,STM32H7,CONFIG_USBHOST_HIGH_WORKQ,CONFIG_USB_DCACHE_ENABLE,CONFIG_USB_ALIGN_SIZE=32</Define>
<Undefine></Undefine>
<IncludePath>../Core/Inc;../Drivers/STM32H7xx_HAL_Driver/Inc;../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32H7xx/Include;../Drivers/CMSIS/Include;..\..\..\..\..\core;..\..\..\..\..\common;..\..\..\..\..\osal;..\..\..\..\..\class\cdc;..\..\..\..\..\class\hid;..\..\..\..\..\class\msc;..\..\..\..\..\class\hub;..\..\..\..\..\third_party\FreeRTOS-10.4\include;..\..\..\..\..\third_party\FreeRTOS-10.4\portable\GCC\ARM_CM7\r0p1</IncludePath>
</VariousControls>

6
demo/usb_host.c
View File

@@ -3,7 +3,7 @@
#include "usbh_hid.h"
#include "usbh_msc.h"
USB_MEM_ALIGN32 uint8_t cdc_buffer[512];
USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t cdc_buffer[512];
void usbh_cdc_acm_callback(void *arg, int nbytes)
{
@@ -73,7 +73,7 @@ int cdc_acm_test(void)
#include "ff.h"
#endif
USB_MEM_ALIGN32 uint8_t partition_table[512];
USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t partition_table[512];
int msc_test(void)
{
@@ -143,7 +143,7 @@ int msc_test(void)
return ret;
}
USB_MEM_ALIGN32 uint8_t hid_buffer[128];
USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t hid_buffer[128];
void usbh_hid_callback(void *arg, int nbytes)
{

2
demo/video_static_mjpeg_template.c
View File

@@ -182,7 +182,7 @@ void video_init()
usbd_initialize();
}
uint8_t packet_buffer[10 * 1024];
USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t packet_buffer[10 * 1024];
void video_test()
{

4
port/ch32/usb_dc_usbfs.c
View File

@@ -4,8 +4,8 @@
#ifdef CONFIG_USB_HS
#error "usb fs do not support hs"
#endif
#ifndef CONFIG_USB_ALIGN32
#error "usb hs dma must be align4"
#ifndef CONFIG_USBDEV_ALIGN_CHECK_DISABLE
#error "ch32 ip must disable align check"
#endif
#ifndef USBD_IRQHandler

4
port/ch32/usb_dc_usbhs.c
View File

@@ -1,8 +1,8 @@
#include "usbd_core.h"
#include "usb_ch32_usbhs_reg.h"
#ifndef CONFIG_USB_ALIGN32
#error "usb hs dma must be align4"
#ifndef CONFIG_USBDEV_ALIGN_CHECK_DISABLE
#error "ch32 ip must disable align check"
#endif
#ifndef USBD_IRQHandler

7
port/dwc2/usb_dc_dwc2.c
View File

@@ -75,13 +75,14 @@
#if defined(STM32F7) || defined(STM32H7)
#ifndef CONFIG_USB_DCACHE_ENABLE
#warning "if you enable dcache,please enable this macro"
#endif
#else
#ifndef CONFIG_USB_ALIGN32
#error "dwc2 hs with dma, must enable align32"
#if CONFIG_USB_ALIGN_SIZE != 32
#error "dwc2 hs with dma and cache, must enable align32"
#endif
#endif
#endif
#endif
/*FIFO sizes in bytes (total available memory for FIFOs is 4KB )*/
#ifndef CONFIG_USB_DWC2_RX_FIFO_SIZE
#define CONFIG_USB_DWC2_RX_FIFO_SIZE (1024)

34
port/dwc2/usb_hc_dwc2.c
View File

@@ -5,6 +5,16 @@
#error "dwc2 host must use high workq"
#endif
#if defined(STM32F7) || defined(STM32H7)
#ifndef CONFIG_USB_DCACHE_ENABLE
#warning "if you enable dcache,please enable this macro"
#else
#if CONFIG_USB_ALIGN_SIZE != 32
#error "dwc2 hs with dma and cache, must enable align32"
#endif
#endif
#endif
#ifndef USBH_IRQHandler
#define USBH_IRQHandler OTG_HS_IRQHandler
#endif
@@ -59,14 +69,6 @@ struct dwc2_hcd {
struct dwc2_pipe chan[CONFIG_USB_DWC2_PIPE_NUM];
} g_dwc2_hcd;
#ifdef CONFIG_USB_DCACHE_ENABLE
void usb_dwc2_dcache_clean(uintptr_t addr, uint32_t len);
void usb_dwc2_dcache_invalidate(uintptr_t addr, uint32_t len);
#else
#define usb_dwc2_dcache_clean(addr, len)
#define usb_dwc2_dcache_invalidate(addr, len)
#endif
static inline int dwc2_reset(void)
{
uint32_t count = 0U;
@@ -821,7 +823,7 @@ int usbh_control_transfer(usbh_epinfo_t ep, struct usb_setup_packet *setup, uint
chan->waiter = true;
chan->result = -EBUSY;
chan->num_packets = dwc2_calculate_packet_num(8, chan->ep_addr, chan->ep_mps, &chan->xferlen);
usb_dwc2_dcache_clean((uintptr_t)setup, 8);
usb_dcache_clean((uintptr_t)setup, 8);
dwc2_pipe_init(chidx, chan->dev_addr, 0x00, 0x00, chan->ep_mps, chan->speed);
dwc2_pipe_transfer(chidx, 0x00, (uint32_t *)setup, chan->xferlen, chan->num_packets, HC_PID_SETUP);
ret = dwc2_pipe_wait(chan, CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT);
@@ -840,7 +842,7 @@ int usbh_control_transfer(usbh_epinfo_t ep, struct usb_setup_packet *setup, uint
if (ret < 0) {
goto error_out;
}
usb_dwc2_dcache_invalidate((uintptr_t)buffer, setup->wLength);
usb_dcache_invalidate((uintptr_t)buffer, setup->wLength);
chan->waiter = true;
chan->result = -EBUSY;
chan->num_packets = dwc2_calculate_packet_num(0, 0x00, chan->ep_mps, &chan->xferlen);
@@ -854,7 +856,7 @@ int usbh_control_transfer(usbh_epinfo_t ep, struct usb_setup_packet *setup, uint
chan->waiter = true;
chan->result = -EBUSY;
chan->num_packets = dwc2_calculate_packet_num(setup->wLength, 0x00, chan->ep_mps, &chan->xferlen);
usb_dwc2_dcache_clean((uintptr_t)buffer, setup->wLength);
usb_dcache_clean((uintptr_t)buffer, setup->wLength);
dwc2_pipe_init(chidx, chan->dev_addr, 0x00, 0x00, chan->ep_mps, chan->speed);
dwc2_pipe_transfer(chidx, 0x00, (uint32_t *)buffer, chan->xferlen, chan->num_packets, HC_PID_DATA1);
ret = dwc2_pipe_wait(chan, CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT);
@@ -921,7 +923,7 @@ int usbh_ep_bulk_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t buflen, ui
chan->num_packets = dwc2_calculate_packet_num(buflen, chan->ep_addr, chan->ep_mps, &chan->xferlen);
#ifdef CONFIG_USB_DCACHE_ENABLE
if ((chan->ep_addr & 0x80) == 0x00) {
usb_dwc2_dcache_clean((uintptr_t)buffer, buflen);
usb_dcache_clean((uintptr_t)buffer, buflen);
}
#endif
dwc2_pipe_transfer(chidx, chan->ep_addr, (uint32_t *)buffer, chan->xferlen, chan->num_packets, chan->data_pid);
@@ -931,7 +933,7 @@ int usbh_ep_bulk_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t buflen, ui
}
#ifdef CONFIG_USB_DCACHE_ENABLE
if ((chan->ep_addr & 0x80) == 0x80) {
usb_dwc2_dcache_invalidate((uintptr_t)buffer, buflen);
usb_dcache_invalidate((uintptr_t)buffer, buflen);
}
#endif
usb_osal_mutex_give(chan->exclsem);
@@ -974,7 +976,7 @@ int usbh_ep_intr_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t buflen, ui
chan->num_packets = dwc2_calculate_packet_num(buflen, chan->ep_addr, chan->ep_mps, &chan->xferlen);
#ifdef CONFIG_USB_DCACHE_ENABLE
if ((chan->ep_addr & 0x80) == 0x00) {
usb_dwc2_dcache_clean((uintptr_t)buffer, buflen);
usb_dcache_clean((uintptr_t)buffer, buflen);
}
#endif
while (1) {
@@ -996,7 +998,7 @@ int usbh_ep_intr_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t buflen, ui
}
#ifdef CONFIG_USB_DCACHE_ENABLE
if ((chan->ep_addr & 0x80) == 0x80) {
usb_dwc2_dcache_invalidate((uintptr_t)buffer, buflen);
usb_dcache_invalidate((uintptr_t)buffer, buflen);
}
#endif
usb_osal_mutex_give(chan->exclsem);
@@ -1038,7 +1040,7 @@ int usbh_ep_bulk_async_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t bufl
chan->num_packets = dwc2_calculate_packet_num(buflen, chan->ep_addr, chan->ep_mps, &chan->xferlen);
#ifdef CONFIG_USB_DCACHE_ENABLE
if ((chan->ep_addr & 0x80) == 0x00) {
usb_dwc2_dcache_clean((uintptr_t)buffer, buflen);
usb_dcache_clean((uintptr_t)buffer, buflen);
}
#endif
dwc2_pipe_transfer(chidx, chan->ep_addr, (uint32_t *)buffer, chan->xferlen, chan->num_packets, chan->data_pid);

10
port/ehci/usb_ehci.c
View File

@@ -87,10 +87,12 @@ struct usb_ehci_qh_s {
struct usb_ehci_epinfo_s *epinfo; /* Endpoint used for the transfer */
uint32_t fqp; /* First qTD in the list (physical address) */
#if (CONFIG_DCACHE_LINE_SIZE == 64)
#if (CONFIG_USB_ALIGN_SIZE == 64)
uint8_t pad[4]; /* Padding to assure 64-byte alignment */
#else
#elif (CONFIG_USB_ALIGN_SIZE == 32)
uint8_t pad[8]; /* Padding to assure 32-byte alignment */
#else
#error "ehci align size must be 32 or 64"
#endif
};
@@ -151,8 +153,8 @@ struct usb_ehci_epinfo_s {
struct ehci_hcd {
struct usb_ehci_list_s *qhfree; /* List of free Queue Head (QH) structures */
struct usb_ehci_list_s *qtdfree; /* List of free Queue Element Transfer Descriptor (qTD) */
__attribute__((aligned(32))) struct usb_ehci_qh_s qhpool[CONFIG_USB_EHCI_QH_NUM]; /* Queue Head (QH) pool */
__attribute__((aligned(32))) struct usb_ehci_qtd_s qtdpool[CONFIG_USB_EHCI_QTD_NUM]; /* Queue Element Transfer Descriptor (qTD) pool */
USB_MEM_ALIGNX struct usb_ehci_qh_s qhpool[CONFIG_USB_EHCI_QH_NUM]; /* Queue Head (QH) pool */
USB_MEM_ALIGNX struct usb_ehci_qtd_s qtdpool[CONFIG_USB_EHCI_QTD_NUM]; /* Queue Element Transfer Descriptor (qTD) pool */
struct usb_ehci_epinfo_s chan[CONFIG_USBHOST_PIPE_NUM];
};

1
usb_config.h
View File

@@ -10,6 +10,7 @@
#define CONFIG_USB_PRINTF printf
#endif
//#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable")))
#define CONFIG_USB_PRINTF_COLOR_ENABLE
/* USB DEVICE Configuration */