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add ep_enable param to check if ep is enable when transfer

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This commit is contained in:
sakumisu
2022-08-20 20:28:11 +08:00
parent b139f8c133
commit b72e794ea7
6 changed files with 87 additions and 44 deletions
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40
port/dwc2/usb_dc_dwc2.c
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@@ -140,6 +140,7 @@ struct dwc2_ep_state {
uint16_t ep_mps; /* Endpoint max packet size */
uint8_t ep_type; /* Endpoint type */
uint8_t ep_stalled; /* Endpoint stall flag */
uint8_t ep_enable; /* Endpoint enable */
uint8_t *xfer_buf;
uint32_t xfer_len;
uint32_t actual_xfer_len;
@@ -679,6 +680,7 @@ int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
if (USB_EP_DIR_IS_OUT(ep_cfg->ep_addr)) {
g_dwc2_udc.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
g_dwc2_udc.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
g_dwc2_udc.out_ep[ep_idx].ep_enable = true;
USB_OTG_DEV->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & (uint32_t)(1UL << (16 + ep_idx));
@@ -709,6 +711,7 @@ int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
} else {
g_dwc2_udc.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
g_dwc2_udc.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
g_dwc2_udc.in_ep[ep_idx].ep_enable = true;
USB_OTG_DEV->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << ep_idx);
@@ -786,24 +789,26 @@ int usbd_ep_start_write(const uint8_t ep, const uint8_t *data, uint32_t data_len
if (!data && data_len) {
return -1;
}
if (!g_dwc2_udc.in_ep[ep_idx].ep_enable) {
return -2;
}
#ifdef CONFIG_USB_DWC2_DMA_ENABLE
if ((uint32_t)data & 0x03) {
return -2;
return -3;
}
#endif
#ifdef CONFIG_USB_DCACHE_ENABLE
if ((data && (((uint32_t)data) & 0x1f))) {
return -2;
return -4;
}
#if defined(STM32F7) || defined(STM32H7)
if (data && (((uint32_t)data) & 0x24000000) != 0x24000000))
{
return -2;
}
if ((((uint32_t)data) & 0x24000000) != 0x24000000) {
return -5;
}
#endif
#endif
if (USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) {
return -3;
return -6;
}
g_dwc2_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data;
@@ -855,24 +860,26 @@ int usbd_ep_start_read(const uint8_t ep, uint8_t *data, uint32_t data_len)
if (!data && data_len) {
return -1;
}
#ifdef CONFIG_USB_DWC2_DMA_ENABLE
if ((uint32_t)data & 0x03) {
if (!g_dwc2_udc.out_ep[ep_idx].ep_enable) {
return -2;
}
#ifdef CONFIG_USB_DWC2_DMA_ENABLE
if (((uint32_t)data) & 0x03) {
return -3;
}
#endif
#ifdef CONFIG_USB_DCACHE_ENABLE
if ((data && (((uint32_t)data) & 0x1f))) {
return -2;
if (((uint32_t)data) & 0x1f) {
return -4;
}
#if defined(STM32F7) || defined(STM32H7)
if (data && (((uint32_t)data) & 0x24000000) != 0x24000000))
{
return -2;
}
if ((((uint32_t)data) & 0x24000000) != 0x24000000) {
return -5;
}
#endif
#endif
if (USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) {
return -3;
return -6;
}
g_dwc2_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data;
@@ -1052,6 +1059,7 @@ void USBD_IRQHandler(void)
USB_OTG_DEV->DIEPMSK = USB_OTG_DIEPMSK_XFRCM;
memset(&g_dwc2_udc, 0, sizeof(struct dwc2_udc));
usbd_event_reset_handler();
/* Start reading setup */
dwc2_ep0_start_read_setup((uint8_t *)&g_dwc2_udc.setup);