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feat(port/dwc2): add dcache api for esp & st

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Signed-off-by: sakumisu <1203593632@qq.com>
This commit is contained in:
sakumisu
2025-06-03 22:46:48 +08:00
parent b6650bdbc6
commit ac4e4c569d
3 changed files with 54 additions and 7 deletions
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11
osal/idf/usb_config.h
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@@ -334,4 +334,15 @@
#define CONFIG_USB_HS #define CONFIG_USB_HS
#else #else
#error "Unsupported SoC" #error "Unsupported SoC"
#endif
#if CONFIG_IDF_TARGET_ESP32P4
#define CONFIG_USB_DCACHE_ENABLE
#undef CONFIG_USB_ALIGN_SIZE
#define CONFIG_USB_ALIGN_SIZE 32
void usb_dcache_clean(uintptr_t addr, uint32_t size);
void usb_dcache_invalidate(uintptr_t addr, uint32_t size);
void usb_dcache_flush(uintptr_t addr, uint32_t size);
#endif #endif

31
port/dwc2/usb_glue_esp.c
View File

@@ -14,13 +14,13 @@
#include "usbh_core.h" #include "usbh_core.h"
#ifdef CONFIG_IDF_TARGET_ESP32S2 #ifdef CONFIG_IDF_TARGET_ESP32S2
#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ #define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ
#define DEFAULT_USB_INTR_SOURCE ETS_USB_INTR_SOURCE #define DEFAULT_USB_INTR_SOURCE ETS_USB_INTR_SOURCE
#elif CONFIG_IDF_TARGET_ESP32S3 #elif CONFIG_IDF_TARGET_ESP32S3
#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ #define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ
#define DEFAULT_USB_INTR_SOURCE ETS_USB_INTR_SOURCE #define DEFAULT_USB_INTR_SOURCE ETS_USB_INTR_SOURCE
#elif CONFIG_IDF_TARGET_ESP32P4 #elif CONFIG_IDF_TARGET_ESP32P4
#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ #define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
#define DEFAULT_USB_INTR_SOURCE ETS_USB_OTG_INTR_SOURCE #define DEFAULT_USB_INTR_SOURCE ETS_USB_OTG_INTR_SOURCE
#else #else
#define DEFAULT_CPU_FREQ_MHZ 160 #define DEFAULT_CPU_FREQ_MHZ 160
@@ -56,7 +56,7 @@ void usb_dc_low_level_init(uint8_t busid)
USB_LOG_ERR("USB Interrupt Init Failed!\r\n"); USB_LOG_ERR("USB Interrupt Init Failed!\r\n");
return; return;
} }
USB_LOG_INFO("cherryusb, version: "CHERRYUSB_VERSION_STR"\r\n"); USB_LOG_INFO("cherryusb, version: " CHERRYUSB_VERSION_STR "\r\n");
} }
void usb_dc_low_level_deinit(uint8_t busid) void usb_dc_low_level_deinit(uint8_t busid)
@@ -106,7 +106,7 @@ void usb_hc_low_level_init(struct usbh_bus *bus)
USB_LOG_ERR("USB Interrupt Init Failed!\r\n"); USB_LOG_ERR("USB Interrupt Init Failed!\r\n");
return; return;
} }
USB_LOG_INFO("cherryusb, version: "CHERRYUSB_VERSION_STR"\r\n"); USB_LOG_INFO("cherryusb, version: " CHERRYUSB_VERSION_STR "\r\n");
} }
void usb_hc_low_level_deinit(struct usbh_bus *bus) void usb_hc_low_level_deinit(struct usbh_bus *bus)
@@ -129,4 +129,23 @@ uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base)
void usbd_dwc2_delay_ms(uint8_t ms) void usbd_dwc2_delay_ms(uint8_t ms)
{ {
vTaskDelay(pdMS_TO_TICKS(ms)); vTaskDelay(pdMS_TO_TICKS(ms));
} }
#ifdef CONFIG_USB_DCACHE_ENABLE
#include "esp_cache.h"
void usb_dcache_clean(uintptr_t addr, size_t size)
{
esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M);
}
void usb_dcache_invalidate(uintptr_t addr, size_t size)
{
esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_M2C);
}
void usb_dcache_flush(uintptr_t addr, size_t size)
{
esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_DIR_M2C);
}
#endif

19
port/dwc2/usb_glue_st.c
View File

@@ -235,4 +235,21 @@ void OTG_FS_IRQHandler(void)
void OTG_HS_IRQHandler(void) void OTG_HS_IRQHandler(void)
{ {
g_usb_dwc2_irq[1](g_usb_dwc2_busid[1]); g_usb_dwc2_irq[1](g_usb_dwc2_busid[1]);
} }
#ifdef CONFIG_USB_DCACHE_ENABLE
void usb_dcache_clean(uintptr_t addr, size_t size)
{
SCB_CleanDCache_by_Addr((void *)addr, size);
}
void usb_dcache_invalidate(uintptr_t addr, size_t size)
{
SCB_InvalidateDCache_by_Addr((void *)addr, size);
}
void usb_dcache_flush(uintptr_t addr, size_t size)
{
SCB_CleanInvalidateDCache_by_Addr((void *)addr, size);
}
#endif