complete fsdev and synopsys usb otg ip dcd portinng
This commit is contained in:
sakumisu
@@ -67,6 +67,16 @@ int fputc(int ch, FILE *f)
|
||||
USART1->DR = ch;
|
||||
return ch;
|
||||
}
|
||||
|
||||
void usb_dc_low_level_init(void)
|
||||
{
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_USB_CLK_ENABLE();
|
||||
/* USB interrupt Init */
|
||||
HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
|
||||
|
||||
}
|
||||
extern void usb_dc_init(void);
|
||||
/* USER CODE END 0 */
|
||||
|
||||
|
||||
@@ -125,7 +125,7 @@
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ST-LINKIII-KEIL_SWO</Key>
|
||||
<Name>-U38FF6E065254313254222343 -O2254 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(1BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103C8$Flash\STM32F10x_128.FLM)</Name>
|
||||
<Name>-U066EFF555453774987091527 -O2287 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("") -D00(00000000) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103C8$Flash\STM32F10x_128.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
@@ -575,20 +575,8 @@
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\port\stm32\usb_dc_nohal.c</PathWithFileName>
|
||||
<FilenameWithoutPath>usb_dc_nohal.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>5</GroupNumber>
|
||||
<FileNumber>28</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\port\stm32\usb_dc_hal.c</PathWithFileName>
|
||||
<FilenameWithoutPath>usb_dc_hal.c</FilenameWithoutPath>
|
||||
<PathWithFileName>..\..\..\..\port\fsdev\usb_dc_fsdev.c</PathWithFileName>
|
||||
<FilenameWithoutPath>usb_dc_fsdev.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
@@ -602,7 +590,7 @@
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>29</FileNumber>
|
||||
<FileNumber>28</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
@@ -614,7 +602,7 @@
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>30</FileNumber>
|
||||
<FileNumber>29</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
@@ -626,7 +614,7 @@
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>31</FileNumber>
|
||||
<FileNumber>30</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
@@ -638,7 +626,7 @@
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>32</FileNumber>
|
||||
<FileNumber>31</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
@@ -650,7 +638,7 @@
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>6</GroupNumber>
|
||||
<FileNumber>33</FileNumber>
|
||||
<FileNumber>32</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
|
||||
@@ -338,7 +338,7 @@
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define>USE_HAL_DRIVER,STM32F103xB,STM32F1</Define>
|
||||
<Define>USE_HAL_DRIVER,STM32F103xB</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>../Core/Inc;../Drivers/STM32F1xx_HAL_Driver/Inc;../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F1xx/Include;../Drivers/CMSIS/Include;..\..\..\..\common;..\..\..\..\core;..\..\..\..\class\cdc;..\..\..\..\class\msc;..\..\..\..\class\hid;..\example</IncludePath>
|
||||
</VariousControls>
|
||||
@@ -535,65 +535,9 @@
|
||||
<FilePath>..\..\..\..\core\usbd_core.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>usb_dc_nohal.c</FileName>
|
||||
<FileName>usb_dc_fsdev.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\port\stm32\usb_dc_nohal.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>usb_dc_hal.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\port\stm32\usb_dc_hal.c</FilePath>
|
||||
<FileOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>2</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>0</IncludeInBuild>
|
||||
<AlwaysBuild>2</AlwaysBuild>
|
||||
<GenerateAssemblyFile>2</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>2</AssembleAssemblyFile>
|
||||
<PublicsOnly>2</PublicsOnly>
|
||||
<StopOnExitCode>11</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<FileArmAds>
|
||||
<Cads>
|
||||
<interw>2</interw>
|
||||
<Optim>0</Optim>
|
||||
<oTime>2</oTime>
|
||||
<SplitLS>2</SplitLS>
|
||||
<OneElfS>2</OneElfS>
|
||||
<Strict>2</Strict>
|
||||
<EnumInt>2</EnumInt>
|
||||
<PlainCh>2</PlainCh>
|
||||
<Ropi>2</Ropi>
|
||||
<Rwpi>2</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>2</uThumb>
|
||||
<uSurpInc>2</uSurpInc>
|
||||
<uC99>2</uC99>
|
||||
<uGnu>2</uGnu>
|
||||
<useXO>2</useXO>
|
||||
<v6Lang>0</v6Lang>
|
||||
<v6LangP>0</v6LangP>
|
||||
<vShortEn>2</vShortEn>
|
||||
<vShortWch>2</vShortWch>
|
||||
<v6Lto>2</v6Lto>
|
||||
<v6WtE>2</v6WtE>
|
||||
<v6Rtti>2</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
</FileArmAds>
|
||||
</FileOption>
|
||||
<FilePath>..\..\..\..\port\fsdev\usb_dc_fsdev.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
|
||||
@@ -9,17 +9,17 @@ CDefines=USE_HAL_DRIVER;STM32H750xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
|
||||
[PreviousGenFiles]
|
||||
AdvancedFolderStructure=true
|
||||
HeaderFileListSize=3
|
||||
HeaderFiles#0=C:/Users/lvjiazhen/Desktop/usb_stack/demo/stm32/stm32h743vbt6/Core/Inc/stm32h7xx_it.h
|
||||
HeaderFiles#1=C:/Users/lvjiazhen/Desktop/usb_stack/demo/stm32/stm32h743vbt6/Core/Inc/stm32h7xx_hal_conf.h
|
||||
HeaderFiles#2=C:/Users/lvjiazhen/Desktop/usb_stack/demo/stm32/stm32h743vbt6/Core/Inc/main.h
|
||||
HeaderFiles#0=C:/Users/lvjiazhen/Desktop/usb_stack/demo/stm32/stm32h743vbt7/Core/Inc/stm32h7xx_it.h
|
||||
HeaderFiles#1=C:/Users/lvjiazhen/Desktop/usb_stack/demo/stm32/stm32h743vbt7/Core/Inc/stm32h7xx_hal_conf.h
|
||||
HeaderFiles#2=C:/Users/lvjiazhen/Desktop/usb_stack/demo/stm32/stm32h743vbt7/Core/Inc/main.h
|
||||
HeaderFolderListSize=1
|
||||
HeaderPath#0=C:/Users/lvjiazhen/Desktop/usb_stack/demo/stm32/stm32h743vbt6/Core/Inc
|
||||
HeaderPath#0=C:/Users/lvjiazhen/Desktop/usb_stack/demo/stm32/stm32h743vbt7/Core/Inc
|
||||
HeaderFiles=;
|
||||
SourceFileListSize=3
|
||||
SourceFiles#0=C:/Users/lvjiazhen/Desktop/usb_stack/demo/stm32/stm32h743vbt6/Core/Src/stm32h7xx_it.c
|
||||
SourceFiles#1=C:/Users/lvjiazhen/Desktop/usb_stack/demo/stm32/stm32h743vbt6/Core/Src/stm32h7xx_hal_msp.c
|
||||
SourceFiles#2=C:/Users/lvjiazhen/Desktop/usb_stack/demo/stm32/stm32h743vbt6/Core/Src/main.c
|
||||
SourceFiles#0=C:/Users/lvjiazhen/Desktop/usb_stack/demo/stm32/stm32h743vbt7/Core/Src/stm32h7xx_it.c
|
||||
SourceFiles#1=C:/Users/lvjiazhen/Desktop/usb_stack/demo/stm32/stm32h743vbt7/Core/Src/stm32h7xx_hal_msp.c
|
||||
SourceFiles#2=C:/Users/lvjiazhen/Desktop/usb_stack/demo/stm32/stm32h743vbt7/Core/Src/main.c
|
||||
SourceFolderListSize=1
|
||||
SourcePath#0=C:/Users/lvjiazhen/Desktop/usb_stack/demo/stm32/stm32h743vbt6/Core/Src
|
||||
SourcePath#0=C:/Users/lvjiazhen/Desktop/usb_stack/demo/stm32/stm32h743vbt7/Core/Src
|
||||
SourceFiles=;
|
||||
|
||||
|
||||
@@ -56,9 +56,7 @@ void SVC_Handler(void);
|
||||
void DebugMon_Handler(void);
|
||||
void PendSV_Handler(void);
|
||||
void SysTick_Handler(void);
|
||||
void OTG_HS_EP1_OUT_IRQHandler(void);
|
||||
void OTG_HS_EP1_IN_IRQHandler(void);
|
||||
void OTG_HS_IRQHandler(void);
|
||||
void OTG_FS_IRQHandler(void);
|
||||
/* USER CODE BEGIN EFP */
|
||||
|
||||
/* USER CODE END EFP */
|
||||
|
||||
@@ -44,7 +44,7 @@
|
||||
|
||||
UART_HandleTypeDef huart1;
|
||||
|
||||
PCD_HandleTypeDef hpcd_USB_OTG_HS;
|
||||
PCD_HandleTypeDef hpcd_USB_OTG_FS;
|
||||
|
||||
/* USER CODE BEGIN PV */
|
||||
|
||||
@@ -53,8 +53,8 @@ PCD_HandleTypeDef hpcd_USB_OTG_HS;
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
void SystemClock_Config(void);
|
||||
static void MX_GPIO_Init(void);
|
||||
static void MX_USB_OTG_HS_PCD_Init(void);
|
||||
static void MX_USART1_UART_Init(void);
|
||||
static void MX_USB_OTG_FS_PCD_Init(void);
|
||||
/* USER CODE BEGIN PFP */
|
||||
|
||||
/* USER CODE END PFP */
|
||||
@@ -70,7 +70,7 @@ int fputc(int ch, FILE *f)
|
||||
|
||||
#define CDC_IN_EP 0x81
|
||||
#define CDC_OUT_EP 0x01
|
||||
#define CDC_INT_EP 0x82
|
||||
#define CDC_INT_EP 0x83
|
||||
|
||||
#define USBD_VID 0xFFFF
|
||||
#define USBD_PID 0xFFFF
|
||||
@@ -184,7 +184,50 @@ usbd_endpoint_t cdc_in_ep = {
|
||||
.ep_cb = usbd_cdc_acm_in
|
||||
};
|
||||
|
||||
void usb_dc_low_level_init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
/* USER CODE BEGIN USB_OTG_FS_MspInit 0 */
|
||||
|
||||
/* USER CODE END USB_OTG_FS_MspInit 0 */
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/** Enable USB Voltage detector
|
||||
*/
|
||||
HAL_PWREx_EnableUSBVoltageDetector();
|
||||
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
/**USB_OTG_FS GPIO Configuration
|
||||
PA11 ------> USB_OTG_FS_DM
|
||||
PA12 ------> USB_OTG_FS_DP
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
|
||||
/* USB_OTG_FS interrupt Init */
|
||||
HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
|
||||
/* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
|
||||
|
||||
/* USER CODE END USB_OTG_FS_MspInit 1 */
|
||||
|
||||
}
|
||||
extern void usb_dc_init(void);
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
/**
|
||||
@@ -215,17 +258,19 @@ int main(void)
|
||||
|
||||
/* Initialize all configured peripherals */
|
||||
MX_GPIO_Init();
|
||||
MX_USB_OTG_HS_PCD_Init();
|
||||
MX_USART1_UART_Init();
|
||||
//MX_USB_OTG_FS_PCD_Init();
|
||||
/* USER CODE BEGIN 2 */
|
||||
usbd_desc_register(cdc_descriptor);
|
||||
usbd_cdc_add_acm_interface(&cdc_class, &cdc_cmd_intf);
|
||||
usbd_cdc_add_acm_interface(&cdc_class, &cdc_data_intf);
|
||||
usbd_interface_add_endpoint(&cdc_data_intf, &cdc_out_ep);
|
||||
usbd_interface_add_endpoint(&cdc_data_intf, &cdc_in_ep);
|
||||
|
||||
|
||||
usb_dc_init();
|
||||
|
||||
|
||||
while(!usb_device_is_configured())
|
||||
{}
|
||||
/* USER CODE END 2 */
|
||||
|
||||
/* Infinite loop */
|
||||
@@ -235,6 +280,11 @@ int main(void)
|
||||
/* USER CODE END WHILE */
|
||||
|
||||
/* USER CODE BEGIN 3 */
|
||||
uint8_t data_buffer[10] = { 0x31, 0x32, 0x33, 0x34, 0x35, 0x31, 0x32, 0x33, 0x34, 0x35 };
|
||||
usbd_ep_write(CDC_IN_EP, data_buffer, 10, NULL);
|
||||
printf("start\r\n");
|
||||
HAL_Delay(500);
|
||||
printf("end\r\n");
|
||||
}
|
||||
/* USER CODE END 3 */
|
||||
}
|
||||
@@ -344,39 +394,38 @@ static void MX_USART1_UART_Init(void)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_HS Initialization Function
|
||||
* @brief USB_OTG_FS Initialization Function
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void MX_USB_OTG_HS_PCD_Init(void)
|
||||
static void MX_USB_OTG_FS_PCD_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN USB_OTG_HS_Init 0 */
|
||||
/* USER CODE BEGIN USB_OTG_FS_Init 0 */
|
||||
|
||||
/* USER CODE END USB_OTG_HS_Init 0 */
|
||||
/* USER CODE END USB_OTG_FS_Init 0 */
|
||||
|
||||
/* USER CODE BEGIN USB_OTG_HS_Init 1 */
|
||||
/* USER CODE BEGIN USB_OTG_FS_Init 1 */
|
||||
|
||||
/* USER CODE END USB_OTG_HS_Init 1 */
|
||||
hpcd_USB_OTG_HS.Instance = USB_OTG_HS;
|
||||
hpcd_USB_OTG_HS.Init.dev_endpoints = 9;
|
||||
hpcd_USB_OTG_HS.Init.speed = PCD_SPEED_FULL;
|
||||
hpcd_USB_OTG_HS.Init.dma_enable = DISABLE;
|
||||
hpcd_USB_OTG_HS.Init.phy_itface = USB_OTG_EMBEDDED_PHY;
|
||||
hpcd_USB_OTG_HS.Init.Sof_enable = DISABLE;
|
||||
hpcd_USB_OTG_HS.Init.low_power_enable = DISABLE;
|
||||
hpcd_USB_OTG_HS.Init.lpm_enable = DISABLE;
|
||||
hpcd_USB_OTG_HS.Init.battery_charging_enable = ENABLE;
|
||||
hpcd_USB_OTG_HS.Init.vbus_sensing_enable = DISABLE;
|
||||
hpcd_USB_OTG_HS.Init.use_dedicated_ep1 = DISABLE;
|
||||
hpcd_USB_OTG_HS.Init.use_external_vbus = DISABLE;
|
||||
if (HAL_PCD_Init(&hpcd_USB_OTG_HS) != HAL_OK)
|
||||
/* USER CODE END USB_OTG_FS_Init 1 */
|
||||
hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
|
||||
hpcd_USB_OTG_FS.Init.dev_endpoints = 9;
|
||||
hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
|
||||
hpcd_USB_OTG_FS.Init.dma_enable = DISABLE;
|
||||
hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
|
||||
hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
|
||||
hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
|
||||
hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
|
||||
hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE;
|
||||
hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
|
||||
hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
|
||||
if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN USB_OTG_HS_Init 2 */
|
||||
/* USER CODE BEGIN USB_OTG_FS_Init 2 */
|
||||
|
||||
/* USER CODE END USB_OTG_HS_Init 2 */
|
||||
/* USER CODE END USB_OTG_FS_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
@@ -390,7 +439,6 @@ static void MX_GPIO_Init(void)
|
||||
|
||||
/* GPIO Ports Clock Enable */
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
|
||||
}
|
||||
|
||||
@@ -161,11 +161,11 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
if(hpcd->Instance==USB_OTG_HS)
|
||||
if(hpcd->Instance==USB_OTG_FS)
|
||||
{
|
||||
/* USER CODE BEGIN USB_OTG_HS_MspInit 0 */
|
||||
/* USER CODE BEGIN USB_OTG_FS_MspInit 0 */
|
||||
|
||||
/* USER CODE END USB_OTG_HS_MspInit 0 */
|
||||
/* USER CODE END USB_OTG_FS_MspInit 0 */
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
@@ -178,30 +178,26 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
|
||||
*/
|
||||
HAL_PWREx_EnableUSBVoltageDetector();
|
||||
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
/**USB_OTG_HS GPIO Configuration
|
||||
PB14 ------> USB_OTG_HS_DM
|
||||
PB15 ------> USB_OTG_HS_DP
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
/**USB_OTG_FS GPIO Configuration
|
||||
PA11 ------> USB_OTG_FS_DM
|
||||
PA12 ------> USB_OTG_FS_DP
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF12_OTG2_FS;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
|
||||
/* USB_OTG_HS interrupt Init */
|
||||
HAL_NVIC_SetPriority(OTG_HS_EP1_OUT_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(OTG_HS_EP1_OUT_IRQn);
|
||||
HAL_NVIC_SetPriority(OTG_HS_EP1_IN_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(OTG_HS_EP1_IN_IRQn);
|
||||
HAL_NVIC_SetPriority(OTG_HS_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(OTG_HS_IRQn);
|
||||
/* USER CODE BEGIN USB_OTG_HS_MspInit 1 */
|
||||
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
|
||||
/* USB_OTG_FS interrupt Init */
|
||||
HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
|
||||
/* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
|
||||
|
||||
/* USER CODE END USB_OTG_HS_MspInit 1 */
|
||||
/* USER CODE END USB_OTG_FS_MspInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
@@ -214,27 +210,25 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
|
||||
*/
|
||||
void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd)
|
||||
{
|
||||
if(hpcd->Instance==USB_OTG_HS)
|
||||
if(hpcd->Instance==USB_OTG_FS)
|
||||
{
|
||||
/* USER CODE BEGIN USB_OTG_HS_MspDeInit 0 */
|
||||
/* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END USB_OTG_HS_MspDeInit 0 */
|
||||
/* USER CODE END USB_OTG_FS_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_USB_OTG_HS_CLK_DISABLE();
|
||||
__HAL_RCC_USB_OTG_FS_CLK_DISABLE();
|
||||
|
||||
/**USB_OTG_HS GPIO Configuration
|
||||
PB14 ------> USB_OTG_HS_DM
|
||||
PB15 ------> USB_OTG_HS_DP
|
||||
/**USB_OTG_FS GPIO Configuration
|
||||
PA11 ------> USB_OTG_FS_DM
|
||||
PA12 ------> USB_OTG_FS_DP
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_14|GPIO_PIN_15);
|
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);
|
||||
|
||||
/* USB_OTG_HS interrupt DeInit */
|
||||
HAL_NVIC_DisableIRQ(OTG_HS_EP1_OUT_IRQn);
|
||||
HAL_NVIC_DisableIRQ(OTG_HS_EP1_IN_IRQn);
|
||||
HAL_NVIC_DisableIRQ(OTG_HS_IRQn);
|
||||
/* USER CODE BEGIN USB_OTG_HS_MspDeInit 1 */
|
||||
/* USB_OTG_FS interrupt DeInit */
|
||||
HAL_NVIC_DisableIRQ(OTG_FS_IRQn);
|
||||
/* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END USB_OTG_HS_MspDeInit 1 */
|
||||
/* USER CODE END USB_OTG_FS_MspDeInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
@@ -56,7 +56,7 @@
|
||||
/* USER CODE END 0 */
|
||||
|
||||
/* External variables --------------------------------------------------------*/
|
||||
extern PCD_HandleTypeDef hpcd_USB_OTG_HS;
|
||||
extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
|
||||
/* USER CODE BEGIN EV */
|
||||
|
||||
/* USER CODE END EV */
|
||||
@@ -73,9 +73,8 @@ void NMI_Handler(void)
|
||||
|
||||
/* USER CODE END NonMaskableInt_IRQn 0 */
|
||||
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
while (1) {
|
||||
}
|
||||
/* USER CODE END NonMaskableInt_IRQn 1 */
|
||||
}
|
||||
|
||||
@@ -200,46 +199,18 @@ void SysTick_Handler(void)
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This function handles USB On The Go HS End Point 1 Out global interrupt.
|
||||
* @brief This function handles USB On The Go FS global interrupt.
|
||||
*/
|
||||
void OTG_HS_EP1_OUT_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN OTG_HS_EP1_OUT_IRQn 0 */
|
||||
//void OTG_FS_IRQHandler(void)
|
||||
//{
|
||||
// /* USER CODE BEGIN OTG_FS_IRQn 0 */
|
||||
|
||||
/* USER CODE END OTG_HS_EP1_OUT_IRQn 0 */
|
||||
HAL_PCD_IRQHandler(&hpcd_USB_OTG_HS);
|
||||
/* USER CODE BEGIN OTG_HS_EP1_OUT_IRQn 1 */
|
||||
// /* USER CODE END OTG_FS_IRQn 0 */
|
||||
// HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);
|
||||
// /* USER CODE BEGIN OTG_FS_IRQn 1 */
|
||||
|
||||
/* USER CODE END OTG_HS_EP1_OUT_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles USB On The Go HS End Point 1 In global interrupt.
|
||||
*/
|
||||
void OTG_HS_EP1_IN_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN OTG_HS_EP1_IN_IRQn 0 */
|
||||
|
||||
/* USER CODE END OTG_HS_EP1_IN_IRQn 0 */
|
||||
HAL_PCD_IRQHandler(&hpcd_USB_OTG_HS);
|
||||
/* USER CODE BEGIN OTG_HS_EP1_IN_IRQn 1 */
|
||||
|
||||
/* USER CODE END OTG_HS_EP1_IN_IRQn 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles USB On The Go HS global interrupt.
|
||||
*/
|
||||
void OTG_HS_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN OTG_HS_IRQn 0 */
|
||||
|
||||
/* USER CODE END OTG_HS_IRQn 0 */
|
||||
HAL_PCD_IRQHandler(&hpcd_USB_OTG_HS);
|
||||
/* USER CODE BEGIN OTG_HS_IRQn 1 */
|
||||
|
||||
/* USER CODE END OTG_HS_IRQn 1 */
|
||||
}
|
||||
// /* USER CODE END OTG_FS_IRQn 1 */
|
||||
//}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
|
||||
@@ -117,6 +117,26 @@
|
||||
<pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMRTXEVENTFLAGS</Key>
|
||||
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGTARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGUARM</Key>
|
||||
<Name>(105=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
@@ -125,10 +145,27 @@
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ST-LINKIII-KEIL_SWO</Key>
|
||||
<Name>-U-O142 -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32H7x_128k.FLM -FS08000000 -FL020000 -FP0($$Device:STM32H750VBTx$CMSIS\Flash\STM32H7x_128k.FLM)</Name>
|
||||
<Name>-U066EFF555453774987091527 -O2287 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(6BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32H7x_128k.FLM -FS08000000 -FL020000 -FP0($$Device:STM32H750VBTx$CMSIS\Flash\STM32H7x_128k.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Breakpoint>
|
||||
<Bp>
|
||||
<Number>0</Number>
|
||||
<Type>0</Type>
|
||||
<LineNumber>415</LineNumber>
|
||||
<EnabledFlag>1</EnabledFlag>
|
||||
<Address>134218740</Address>
|
||||
<ByteObject>0</ByteObject>
|
||||
<HtxType>0</HtxType>
|
||||
<ManyObjects>0</ManyObjects>
|
||||
<SizeOfObject>0</SizeOfObject>
|
||||
<BreakByAccess>0</BreakByAccess>
|
||||
<BreakIfRCount>1</BreakIfRCount>
|
||||
<Filename>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c</Filename>
|
||||
<ExecCommand></ExecCommand>
|
||||
<Expression>\\stm32h743vbt6\../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c\415</Expression>
|
||||
</Bp>
|
||||
</Breakpoint>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
@@ -173,7 +210,7 @@
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
<DebugDescription>
|
||||
<Enable>1</Enable>
|
||||
<EnableFlashSeq>1</EnableFlashSeq>
|
||||
<EnableFlashSeq>0</EnableFlashSeq>
|
||||
<EnableLog>0</EnableLog>
|
||||
<Protocol>2</Protocol>
|
||||
<DbgClock>10000000</DbgClock>
|
||||
@@ -247,7 +284,7 @@
|
||||
|
||||
<Group>
|
||||
<GroupName>Drivers/STM32H7xx_HAL_Driver</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
@@ -255,7 +292,7 @@
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>5</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c</PathWithFileName>
|
||||
@@ -586,8 +623,8 @@
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\port\stm32\usb_dc_hal.c</PathWithFileName>
|
||||
<FilenameWithoutPath>usb_dc_hal.c</FilenameWithoutPath>
|
||||
<PathWithFileName>..\..\..\..\port\synopsys\usb_dc_synopsys.c</PathWithFileName>
|
||||
<FilenameWithoutPath>usb_dc_synopsys.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
|
||||
@@ -190,7 +190,7 @@
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
@@ -338,9 +338,9 @@
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define>USE_HAL_DRIVER,STM32H750xx,STM32H7,CONFIG_USB_HS</Define>
|
||||
<Define>USE_HAL_DRIVER,STM32H750xx,STM32H7</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>../Core/Inc; ../Drivers/STM32H7xx_HAL_Driver/Inc; ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy; ../Drivers/CMSIS/Device/ST/STM32H7xx/Include; ../Drivers/CMSIS/Include; ..\..\..\..\class\cdc; ..\..\..\..\common; ..\..\..\..\core; ..\..\..\..\class\winusb</IncludePath>
|
||||
<IncludePath>../Core/Inc; ../Drivers/STM32H7xx_HAL_Driver/Inc; ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy; ../Drivers/CMSIS/Device/ST/STM32H7xx/Include; ../Drivers/CMSIS/Include; ..\..\..\..\class\cdc; ..\..\..\..\common; ..\..\..\..\core; ..\..\..\..\class\winusb</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
@@ -657,9 +657,9 @@
|
||||
<FilePath>..\..\..\..\core\usbd_core.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>usb_dc_hal.c</FileName>
|
||||
<FileName>usb_dc_synopsys.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\port\stm32\usb_dc_hal.c</FilePath>
|
||||
<FilePath>..\..\..\..\port\synopsys\usb_dc_synopsys.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
|
||||
@@ -8,16 +8,16 @@ Mcu.IP1=NVIC
|
||||
Mcu.IP2=RCC
|
||||
Mcu.IP3=SYS
|
||||
Mcu.IP4=USART1
|
||||
Mcu.IP5=USB_OTG_HS
|
||||
Mcu.IP5=USB_OTG_FS
|
||||
Mcu.IPNb=6
|
||||
Mcu.Name=STM32H750VBTx
|
||||
Mcu.Package=LQFP100
|
||||
Mcu.Pin0=PH0-OSC_IN (PH0)
|
||||
Mcu.Pin1=PH1-OSC_OUT (PH1)
|
||||
Mcu.Pin2=PB14
|
||||
Mcu.Pin3=PB15
|
||||
Mcu.Pin4=PA9
|
||||
Mcu.Pin5=PA10
|
||||
Mcu.Pin2=PA9
|
||||
Mcu.Pin3=PA10
|
||||
Mcu.Pin4=PA11
|
||||
Mcu.Pin5=PA12
|
||||
Mcu.Pin6=VP_SYS_VS_Systick
|
||||
Mcu.PinsNb=7
|
||||
Mcu.ThirdPartyNb=0
|
||||
@@ -31,9 +31,7 @@ NVIC.ForceEnableDMAVector=true
|
||||
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||
NVIC.OTG_HS_EP1_IN_IRQn=true\:0\:0\:false\:false\:true\:true\:true
|
||||
NVIC.OTG_HS_EP1_OUT_IRQn=true\:0\:0\:false\:false\:true\:true\:true
|
||||
NVIC.OTG_HS_IRQn=true\:0\:0\:false\:false\:true\:true\:true
|
||||
NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true
|
||||
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
|
||||
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||
@@ -41,12 +39,12 @@ NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
|
||||
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||
PA10.Mode=Asynchronous
|
||||
PA10.Signal=USART1_RX
|
||||
PA11.Mode=Device_Only
|
||||
PA11.Signal=USB_OTG_FS_DM
|
||||
PA12.Mode=Device_Only
|
||||
PA12.Signal=USB_OTG_FS_DP
|
||||
PA9.Mode=Asynchronous
|
||||
PA9.Signal=USART1_TX
|
||||
PB14.Mode=Device_Only_FS
|
||||
PB14.Signal=USB_OTG_HS_DM
|
||||
PB15.Mode=Device_Only_FS
|
||||
PB15.Signal=USB_OTG_HS_DP
|
||||
PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
|
||||
PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
|
||||
PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
|
||||
@@ -79,7 +77,7 @@ ProjectManager.StackSize=0x400
|
||||
ProjectManager.TargetToolchain=MDK-ARM V5.27
|
||||
ProjectManager.ToolChainLocation=
|
||||
ProjectManager.UnderRoot=false
|
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
|
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
|
||||
RCC.ADCFreq_Value=400000000
|
||||
RCC.AHB12Freq_Value=200000000
|
||||
RCC.AHB4Freq_Value=200000000
|
||||
@@ -162,8 +160,8 @@ RCC.VCOInput2Freq_Value=5000000
|
||||
RCC.VCOInput3Freq_Value=5000000
|
||||
USART1.IPParameters=VirtualMode-Asynchronous
|
||||
USART1.VirtualMode-Asynchronous=VM_ASYNC
|
||||
USB_OTG_HS.IPParameters=VirtualMode-Device_Only_FS
|
||||
USB_OTG_HS.VirtualMode-Device_Only_FS=Device_Only_FS
|
||||
USB_OTG_FS.IPParameters=VirtualMode
|
||||
USB_OTG_FS.VirtualMode=Device_Only
|
||||
VP_SYS_VS_Systick.Mode=SysTick
|
||||
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
|
||||
board=custom
|
||||
|
||||
@@ -1,2 +1,31 @@
|
||||
# Note
|
||||
与 STM32 USB IP 同系列的使用该 port
|
||||
# Support Chip List
|
||||
|
||||
## STM32
|
||||
|
||||
- STM32F042x6、STM32F048xx、STM32F070x6、STM32F070xb、STM32F072xb、STM32F078xx
|
||||
- STM32F102x6、STM32F102xb、STM32F103x6、STM32F103xb、STM32F103xe、STM32F103xg
|
||||
- STM32F302x8、STM32F302xc、STM32F302xe、STM32F373xc
|
||||
- STM32g431xx、STM32g441xx、STM32g471xx、STM32g483xx、STM32g484xx、STM32gbk1cb
|
||||
- STM32l052xx、STM32l053xx、STM32l062xx、STM32l063xx、STM32l072xx、STM32l073xx、STM32l082xx、STM32l083xx
|
||||
- STM32l100xb、STM32l100xba、STM32l100xc、STM32l151xb、STM32l151xba、STM32l151xc、STM32l151xca、STM32l151xd、STM32l151xdx、STM32l151xe、STM32l152xb、STM32l152xba、STM32l152xc、STM32l152xa、STM32l152xd、STM32l152xdx、STM32l152xe、STM32l162xc、STM32l162xca、STM32l162xd、STM32l162xdx、STM32l162xe
|
||||
- STM32l412xx、STM32l422xx、STM32l432xx、STM32l433xx、STM32l442xx、STM32l452xx、STM32l462xx
|
||||
- STM32wb5mxx、STM32wb35xx、STM32wb55xx
|
||||
|
||||
## AT32
|
||||
|
||||
- AT32F403xx、AT32F407xx、AT32F413xx
|
||||
|
||||
## APM32
|
||||
|
||||
- APM32f10x
|
||||
|
||||
## GD32
|
||||
|
||||
- GD32F10X_MD、GD32F10X_HD、GD32F10X_XD
|
||||
- GD32F30X_HD、GD32F30X_XD
|
||||
- GD32F350
|
||||
- GD32F407
|
||||
|
||||
## CH32
|
||||
|
||||
- CH32F10x、CH32V10x
|
||||
@@ -13,6 +13,12 @@
|
||||
#define USB_RAM_SIZE 512
|
||||
#endif
|
||||
|
||||
/* USB device FS */
|
||||
#define USB_BASE (0x40005C00UL) /*!< USB_IP Peripheral Registers base address */
|
||||
#define USB_PMAADDR (0x40006000UL) /*!< USB_IP Packet Memory Area base address */
|
||||
|
||||
#define USB ((USB_TypeDef *)USB_BASE)
|
||||
|
||||
#define USB_BTABLE_SIZE (8 * USB_NUM_BIDIR_ENDPOINTS)
|
||||
|
||||
static void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
@@ -40,6 +46,14 @@ struct usb_dc_config_priv {
|
||||
uint32_t pma_offset;
|
||||
} usb_dc_cfg;
|
||||
|
||||
__WEAK void usb_dc_low_level_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
__WEAK void usb_dc_low_level_deinit(void)
|
||||
{
|
||||
}
|
||||
|
||||
int usb_dc_init(void)
|
||||
{
|
||||
memset(&usb_dc_cfg, 0, sizeof(struct usb_dc_config_priv));
|
||||
@@ -49,7 +63,7 @@ int usb_dc_init(void)
|
||||
|
||||
USB_TypeDef *USBx = usb_dc_cfg.Instance;
|
||||
|
||||
HAL_PCD_MspInit(&usb_dc_cfg);
|
||||
usb_dc_low_level_init();
|
||||
|
||||
/* Init Device */
|
||||
/* CNTR_FRES = 1 */
|
||||
@@ -90,7 +104,7 @@ void usb_dc_deinit(void)
|
||||
/* switch-off device */
|
||||
USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
|
||||
|
||||
HAL_PCD_MspDeInit(&usb_dc_cfg);
|
||||
usb_dc_low_level_deinit();
|
||||
}
|
||||
|
||||
int usbd_set_address(const uint8_t addr)
|
||||
|
||||
@@ -36,14 +36,6 @@ typedef struct
|
||||
__IO uint16_t RESERVEDC; /*!< Reserved */
|
||||
} USB_TypeDef;
|
||||
|
||||
#define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */
|
||||
#define APB1PERIPH_BASE PERIPH_BASE
|
||||
/* USB device FS */
|
||||
#define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
|
||||
#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
|
||||
|
||||
#define USB ((USB_TypeDef *)USB_BASE)
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* USB Device FS */
|
||||
@@ -2212,7 +2204,6 @@ typedef struct
|
||||
* @{
|
||||
*/
|
||||
#define USBD_FS_SPEED 2U
|
||||
#define PCD_SPEED_FULL USBD_FS_SPEED
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -5,3 +5,6 @@
|
||||
- 如果使用的是 usb_dc_hal.c 则上条不需要
|
||||
- 推荐使用 nohal 版本，极简代码
|
||||
|
||||
|
||||
## 该目录下porting可以不再使用，选择 fsdev 或者 synopsys下的porting接口
|
||||
|
||||
|
||||
@@ -26,10 +26,10 @@ extern PCD_HandleTypeDef hpcd_USB_OTG_HS;
|
||||
#ifndef USB_RAM_SIZE
|
||||
#define USB_RAM_SIZE 1280
|
||||
#endif
|
||||
extern PCD_HandleTypeDef hpcd_USB_OTG_HS;
|
||||
#define PCD_HANDLE &hpcd_USB_OTG_HS
|
||||
//extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
|
||||
//#define PCD_HANDLE &hpcd_USB_OTG_FS
|
||||
//extern PCD_HandleTypeDef hpcd_USB_OTG_HS;
|
||||
//#define PCD_HANDLE &hpcd_USB_OTG_HS
|
||||
extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
|
||||
#define PCD_HANDLE &hpcd_USB_OTG_FS
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
@@ -1,3 +1,25 @@
|
||||
# Note
|
||||
# Support Chip List
|
||||
|
||||
使用 DesignWare USB OTG IP 的使用该 port
|
||||
## STM32
|
||||
|
||||
- STM32F105xc、STM32F107xc
|
||||
- STM32F205xx、STM32F207xx、STM32F215xx、STM32F217xx
|
||||
- STM32F401xc、STM32F401xe、STM32F405xx、STM32F407xx、STM32F411xe、STM32F412cx、STM32F412rx、STM32F412vx、STM32F412zx、STM32F413xx、STM32F415xx、STM32F417xx、STM32F423xx、STM32F423xx、STM32F429xx、STM32F437xx、STM32F439xx、STM32F446xx、STM32F469xx、STM32F479xx
|
||||
- STM32F7xx
|
||||
- STM32H7xx
|
||||
- STM32L4xx
|
||||
- STM32MPxx
|
||||
|
||||
## AT32
|
||||
|
||||
- AT32F415xx
|
||||
|
||||
## GD32
|
||||
|
||||
- GD32F30X_CL
|
||||
- GD32F405、GD32F407
|
||||
- GD32F450
|
||||
|
||||
## HC32
|
||||
|
||||
- HC32F4A0
|
||||
709
port/synopsys/usb_dc_synopsys.c
Normal file
709
port/synopsys/usb_dc_synopsys.c
Normal file
@@ -0,0 +1,709 @@
|
||||
#include "usbd_core.h"
|
||||
#include "usb_synopsys_regs.h"
|
||||
|
||||
/*!< USB registers base address */
|
||||
#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
|
||||
#ifndef STM32H7
|
||||
#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
|
||||
#else
|
||||
#define USB_OTG_FS_PERIPH_BASE 0x40080000UL
|
||||
#endif
|
||||
|
||||
#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *)USB_OTG_FS_PERIPH_BASE)
|
||||
#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *)USB_OTG_HS_PERIPH_BASE)
|
||||
|
||||
#if defined(CONFIG_USB_HS) || defined(CONFIG_USB_HS_IN_FULL)
|
||||
#ifndef USBD_IRQHandler
|
||||
#define USBD_IRQHandler OTG_HS_IRQHandler
|
||||
#endif
|
||||
|
||||
#ifndef USB_RAM_SIZE
|
||||
#define USB_RAM_SIZE 4096
|
||||
#endif
|
||||
|
||||
#define USB_INSTANCE USB_OTG_HS
|
||||
#else
|
||||
#ifndef USBD_IRQHandler
|
||||
#define USBD_IRQHandler OTG_FS_IRQHandler
|
||||
#endif
|
||||
|
||||
#ifndef USB_RAM_SIZE
|
||||
#define USB_RAM_SIZE 1280
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef USB_NUM_BIDIR_ENDPOINTS
|
||||
#define USB_NUM_BIDIR_ENDPOINTS 6
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_USB_HS) || defined(CONFIG_USB_HS_IN_FULL)
|
||||
/*FIFO sizes in bytes (total available memory for FIFOs is 4 kB)*/
|
||||
#ifndef CONFIG_USB_RX_FIFO_SIZE
|
||||
#define CONFIG_USB_RX_FIFO_SIZE (1024U)
|
||||
#endif
|
||||
#ifndef CONFIG_USB_TX0_FIFO_SIZE
|
||||
#define CONFIG_USB_TX0_FIFO_SIZE (64U)
|
||||
#endif
|
||||
#ifndef CONFIG_USB_TX1_FIFO_SIZE
|
||||
#define CONFIG_USB_TX1_FIFO_SIZE (1024U)
|
||||
#endif
|
||||
#ifndef CONFIG_USB_TX2_FIFO_SIZE
|
||||
#define CONFIG_USB_TX2_FIFO_SIZE (512U)
|
||||
#endif
|
||||
#ifndef CONFIG_USB_TX3_FIFO_SIZE
|
||||
#define CONFIG_USB_TX3_FIFO_SIZE (256U)
|
||||
#endif
|
||||
#ifndef CONFIG_USB_TX4_FIFO_SIZE
|
||||
#define CONFIG_USB_TX4_FIFO_SIZE (256U)
|
||||
#endif
|
||||
#ifndef CONFIG_USB_TX5_FIFO_SIZE
|
||||
#define CONFIG_USB_TX5_FIFO_SIZE (256U)
|
||||
#endif
|
||||
#ifndef CONFIG_USB_TX6_FIFO_SIZE
|
||||
#define CONFIG_USB_TX6_FIFO_SIZE (256U)
|
||||
#endif
|
||||
#ifndef CONFIG_USB_TX7_FIFO_SIZE
|
||||
#define CONFIG_USB_TX7_FIFO_SIZE (256U)
|
||||
#endif
|
||||
#ifndef CONFIG_USB_TX8_FIFO_SIZE
|
||||
#define CONFIG_USB_TX8_FIFO_SIZE (192U)
|
||||
#endif
|
||||
#else
|
||||
/*FIFO sizes in bytes (total available memory for FIFOs is 1.25kB)*/
|
||||
#ifndef CONFIG_USB_RX_FIFO_SIZE
|
||||
#define CONFIG_USB_RX_FIFO_SIZE (640U)
|
||||
#endif
|
||||
#ifndef CONFIG_USB_TX0_FIFO_SIZE
|
||||
#define CONFIG_USB_TX0_FIFO_SIZE (160U)
|
||||
#endif
|
||||
#ifndef CONFIG_USB_TX1_FIFO_SIZE
|
||||
#define CONFIG_USB_TX1_FIFO_SIZE (160U)
|
||||
#endif
|
||||
#ifndef CONFIG_USB_TX2_FIFO_SIZE
|
||||
#define CONFIG_USB_TX2_FIFO_SIZE (160U)
|
||||
#endif
|
||||
#ifndef CONFIG_USB_TX3_FIFO_SIZE
|
||||
#define CONFIG_USB_TX3_FIFO_SIZE (160U)
|
||||
#endif
|
||||
#ifndef CONFIG_USB_TX4_FIFO_SIZE
|
||||
#define CONFIG_USB_TX4_FIFO_SIZE (160U)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_USB_TURNAROUND_TIME
|
||||
#define CONFIG_USB_TURNAROUND_TIME 9
|
||||
#endif
|
||||
|
||||
/* Endpoint state */
|
||||
struct usb_dc_ep_state {
|
||||
/** Endpoint max packet size */
|
||||
uint16_t ep_mps;
|
||||
/** Endpoint Transfer Type.
|
||||
* May be Bulk, Interrupt, Control or Isochronous
|
||||
*/
|
||||
uint8_t ep_type;
|
||||
uint8_t ep_stalled; /** Endpoint stall flag */
|
||||
};
|
||||
|
||||
/* Driver state */
|
||||
struct usb_dc_config_priv {
|
||||
USB_OTG_GlobalTypeDef *Instance; /*!< Register base address */
|
||||
struct usb_dc_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/
|
||||
struct usb_dc_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
|
||||
volatile uint32_t grxstsp;
|
||||
} usb_dc_cfg;
|
||||
|
||||
static int usb_flush_rxfifo(USB_OTG_GlobalTypeDef *USBx);
|
||||
static int usb_flush_txfifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
|
||||
static void usb_set_txfifo(USB_OTG_GlobalTypeDef *USBx, uint8_t fifo, uint16_t size);
|
||||
|
||||
__WEAK void usb_dc_low_level_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
__WEAK void usb_dc_low_level_deinit(void)
|
||||
{
|
||||
}
|
||||
|
||||
int usb_dc_init(void)
|
||||
{
|
||||
uint32_t USBx_BASE;
|
||||
uint32_t count = 0U;
|
||||
|
||||
memset(&usb_dc_cfg, 0, sizeof(struct usb_dc_config_priv));
|
||||
|
||||
#if defined(CONFIG_USB_HS) || defined(CONFIG_USB_HS_IN_FULL)
|
||||
usb_dc_cfg.Instance = USB_OTG_HS;
|
||||
#else
|
||||
usb_dc_cfg.Instance = USB_OTG_FS;
|
||||
#endif
|
||||
USB_OTG_GlobalTypeDef *USBx = usb_dc_cfg.Instance;
|
||||
|
||||
usb_dc_low_level_init();
|
||||
|
||||
USBx_BASE = (uint32_t)USBx;
|
||||
|
||||
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
|
||||
|
||||
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
|
||||
#if defined(CONFIG_USB_HS)
|
||||
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
||||
|
||||
/* Init The ULPI Interface */
|
||||
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
|
||||
|
||||
/* Select vbus source */
|
||||
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
|
||||
|
||||
//USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
|
||||
|
||||
#else
|
||||
/* Select FS Embedded PHY */
|
||||
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
|
||||
// if (cfg.battery_charging_enable == 0U)
|
||||
// {
|
||||
/* Activate the USB Transceiver */
|
||||
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// /* Deactivate the USB Transceiver */
|
||||
// USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
||||
// }
|
||||
#endif
|
||||
|
||||
/* Reset after a PHY select and set Host mode */
|
||||
/* Wait for AHB master IDLE state. */
|
||||
do {
|
||||
if (++count > 200000U) {
|
||||
return -1;
|
||||
}
|
||||
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
||||
|
||||
/* Core Soft Reset */
|
||||
count = 0U;
|
||||
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
|
||||
|
||||
do {
|
||||
if (++count > 200000U) {
|
||||
return -1;
|
||||
}
|
||||
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
|
||||
|
||||
/* Force Device Mode*/
|
||||
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
|
||||
|
||||
USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
|
||||
USBx->GUSBCFG |= (uint32_t)((CONFIG_USB_TURNAROUND_TIME << 10) & USB_OTG_GUSBCFG_TRDT);
|
||||
|
||||
for (uint8_t i = 0U; i < 15U; i++) {
|
||||
USBx->DIEPTXF[i] = 0U;
|
||||
}
|
||||
|
||||
/* VBUS Sensing setup */
|
||||
// if (cfg.vbus_sensing_enable == 0U)
|
||||
// {
|
||||
/* Deactivate VBUS Sensing B */
|
||||
USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
|
||||
|
||||
/* B-peripheral session valid override enable */
|
||||
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
|
||||
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// /* Enable HW VBUS sensing */
|
||||
// USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
|
||||
// }
|
||||
//
|
||||
|
||||
/* Restart the Phy Clock */
|
||||
USBx_PCGCCTL = 0U;
|
||||
|
||||
/* Device mode configuration */
|
||||
USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
|
||||
#if defined(CONFIG_USB_HS)
|
||||
/* Set Core speed to High speed mode */
|
||||
USBx_DEVICE->DCFG |= USB_OTG_SPEED_HIGH;
|
||||
#else
|
||||
USBx_DEVICE->DCFG |= USB_OTG_SPEED_FULL;
|
||||
#endif
|
||||
|
||||
usb_flush_txfifo(USBx, 0x10U);
|
||||
usb_flush_rxfifo(USBx);
|
||||
|
||||
/* Clear all pending Device Interrupts */
|
||||
USBx_DEVICE->DIEPMSK = 0U;
|
||||
USBx_DEVICE->DOEPMSK = 0U;
|
||||
USBx_DEVICE->DAINTMSK = 0U;
|
||||
|
||||
for (uint8_t i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
|
||||
if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) {
|
||||
if (i == 0U) {
|
||||
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;
|
||||
} else {
|
||||
USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;
|
||||
}
|
||||
} else {
|
||||
USBx_INEP(i)->DIEPCTL = 0U;
|
||||
}
|
||||
|
||||
USBx_INEP(i)->DIEPTSIZ = 0U;
|
||||
USBx_INEP(i)->DIEPINT = 0xFB7FU;
|
||||
}
|
||||
for (uint8_t i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
|
||||
if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) {
|
||||
if (i == 0U) {
|
||||
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;
|
||||
} else {
|
||||
USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;
|
||||
}
|
||||
} else {
|
||||
USBx_OUTEP(i)->DOEPCTL = 0U;
|
||||
}
|
||||
|
||||
USBx_OUTEP(i)->DOEPTSIZ = 0U;
|
||||
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
|
||||
}
|
||||
|
||||
/* Disable all interrupts. */
|
||||
USBx->GINTMSK = 0U;
|
||||
|
||||
/* Clear any pending interrupts */
|
||||
USBx->GINTSTS = 0xBFFFFFFFU;
|
||||
|
||||
/* Enable interrupts matching to the Device mode ONLY */
|
||||
USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM |
|
||||
USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_RXFLVLM |
|
||||
USB_OTG_GINTMSK_WUIM;
|
||||
|
||||
USBx->GRXFSIZ = (CONFIG_USB_RX_FIFO_SIZE / 4);
|
||||
|
||||
usb_set_txfifo(USBx, 0, CONFIG_USB_TX0_FIFO_SIZE / 4);
|
||||
usb_set_txfifo(USBx, 1, CONFIG_USB_TX1_FIFO_SIZE / 4);
|
||||
usb_set_txfifo(USBx, 2, CONFIG_USB_TX2_FIFO_SIZE / 4);
|
||||
usb_set_txfifo(USBx, 3, CONFIG_USB_TX3_FIFO_SIZE / 4);
|
||||
usb_set_txfifo(USBx, 4, CONFIG_USB_TX4_FIFO_SIZE / 4);
|
||||
|
||||
USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
|
||||
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void usb_dc_deinit(void)
|
||||
{
|
||||
USB_OTG_GlobalTypeDef *USBx = usb_dc_cfg.Instance;
|
||||
uint32_t USBx_BASE = (uint32_t)USBx;
|
||||
|
||||
usb_dc_low_level_deinit();
|
||||
}
|
||||
|
||||
int usbd_set_address(const uint8_t addr)
|
||||
{
|
||||
USB_OTG_GlobalTypeDef *USBx = usb_dc_cfg.Instance;
|
||||
uint32_t USBx_BASE = (uint32_t)USBx;
|
||||
USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);
|
||||
USBx_DEVICE->DCFG |= ((uint32_t)addr << 4) & USB_OTG_DCFG_DAD;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
|
||||
{
|
||||
USB_OTG_GlobalTypeDef *USBx = usb_dc_cfg.Instance;
|
||||
uint32_t USBx_BASE = (uint32_t)USBx;
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep_cfg->ep_addr);
|
||||
|
||||
if (!ep_cfg) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (USB_EP_DIR_IS_OUT(ep_cfg->ep_addr)) {
|
||||
usb_dc_cfg.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
|
||||
usb_dc_cfg.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
|
||||
|
||||
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & (uint32_t)(1UL << (16 + ep_idx));
|
||||
|
||||
USBx_OUTEP(ep_idx)->DOEPCTL |= (ep_cfg->ep_mps & USB_OTG_DOEPCTL_MPSIZ) |
|
||||
((uint32_t)ep_cfg->ep_type << 18) |
|
||||
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
|
||||
USB_OTG_DOEPCTL_USBAEP;
|
||||
/* EP enable */
|
||||
USBx_OUTEP(ep_idx)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
|
||||
} else {
|
||||
usb_dc_cfg.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
|
||||
usb_dc_cfg.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
|
||||
|
||||
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << ep_idx);
|
||||
|
||||
USBx_INEP(ep_idx)->DIEPCTL |= (ep_cfg->ep_mps & USB_OTG_DIEPCTL_MPSIZ) |
|
||||
((uint32_t)ep_cfg->ep_type << 18) | (ep_idx << 22) |
|
||||
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
|
||||
USB_OTG_DIEPCTL_USBAEP;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
int usbd_ep_close(const uint8_t ep)
|
||||
{
|
||||
USB_OTG_GlobalTypeDef *USBx = usb_dc_cfg.Instance;
|
||||
uint32_t USBx_BASE = (uint32_t)USBx;
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep);
|
||||
|
||||
if (USB_EP_DIR_IS_OUT(ep)) {
|
||||
} else {
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
int usbd_ep_set_stall(const uint8_t ep)
|
||||
{
|
||||
USB_OTG_GlobalTypeDef *USBx = usb_dc_cfg.Instance;
|
||||
uint32_t USBx_BASE = (uint32_t)USBx;
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep);
|
||||
|
||||
if (USB_EP_DIR_IS_OUT(ep)) {
|
||||
USBx_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
|
||||
} else {
|
||||
USBx_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
int usbd_ep_clear_stall(const uint8_t ep)
|
||||
{
|
||||
USB_OTG_GlobalTypeDef *USBx = usb_dc_cfg.Instance;
|
||||
uint32_t USBx_BASE = (uint32_t)USBx;
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep);
|
||||
|
||||
if (USB_EP_DIR_IS_OUT(ep)) {
|
||||
USBx_OUTEP(ep_idx)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
|
||||
} else {
|
||||
USBx_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
|
||||
{
|
||||
if (USB_EP_DIR_IS_OUT(ep)) {
|
||||
} else {
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes)
|
||||
{
|
||||
USB_OTG_GlobalTypeDef *USBx = usb_dc_cfg.Instance;
|
||||
uint32_t USBx_BASE = (uint32_t)USBx;
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep);
|
||||
uint32_t len32b;
|
||||
|
||||
if (!data && data_len) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (!data_len) {
|
||||
USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
|
||||
USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
|
||||
USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
|
||||
/* EP enable, IN data in FIFO */
|
||||
USBx_INEP(ep_idx)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (data_len > usb_dc_cfg.in_ep[ep_idx].ep_mps) {
|
||||
data_len = usb_dc_cfg.in_ep[ep_idx].ep_mps;
|
||||
}
|
||||
|
||||
/* Program the transfer size and packet count
|
||||
* as follows: xfersize = N * maxpacket +
|
||||
* short_packet pktcnt = N + (short_packet
|
||||
* exist ? 1 : 0)
|
||||
*/
|
||||
USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
|
||||
USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
|
||||
USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
|
||||
//USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((data_len + usb_dc_cfg.in_ep[ep_idx].ep_mps - 1U) / usb_dc_cfg.in_ep[ep_idx].ep_mps) << 19));
|
||||
USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & data_len);
|
||||
/* EP enable, IN data in FIFO */
|
||||
USBx_INEP(ep_idx)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
|
||||
|
||||
if (usb_dc_cfg.in_ep[ep_idx].ep_type == EP_TYPE_ISOC) {
|
||||
USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
|
||||
USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
|
||||
|
||||
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) {
|
||||
USBx_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
|
||||
} else {
|
||||
USBx_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
|
||||
}
|
||||
}
|
||||
|
||||
len32b = (data_len + 3U) / 4U;
|
||||
|
||||
while (USBx_INEP(ep_idx)->DTXFSTS < len32b) {
|
||||
}
|
||||
for (uint8_t i = 0U; i < len32b; i++) {
|
||||
USBx_DFIFO(ep_idx) = ((uint32_t *)data)[i];
|
||||
}
|
||||
|
||||
if (ret_bytes) {
|
||||
*ret_bytes = data_len;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_t *read_bytes)
|
||||
{
|
||||
USB_OTG_GlobalTypeDef *USBx = usb_dc_cfg.Instance;
|
||||
uint32_t USBx_BASE = (uint32_t)USBx;
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep);
|
||||
uint32_t *pdest = (uint32_t *)data;
|
||||
uint32_t len32b;
|
||||
uint32_t read_count;
|
||||
uint32_t pktcnt;
|
||||
if (!data && max_data_len) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (!max_data_len) {
|
||||
if (ep_idx != 0) {
|
||||
/* Program the transfer size and packet count as follows:
|
||||
* pktcnt = N
|
||||
* xfersize = N * maxpacket
|
||||
*/
|
||||
pktcnt = (uint16_t)((max_data_len + usb_dc_cfg.out_ep[ep_idx].ep_mps - 1U) / usb_dc_cfg.out_ep[ep_idx].ep_mps);
|
||||
USBx_OUTEP(ep_idx)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
|
||||
USBx_OUTEP(ep_idx)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
|
||||
USBx_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19));
|
||||
USBx_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & usb_dc_cfg.out_ep[ep_idx].ep_mps * pktcnt);
|
||||
/* EP enable */
|
||||
USBx_OUTEP(ep_idx)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (max_data_len > usb_dc_cfg.out_ep[ep_idx].ep_mps) {
|
||||
max_data_len = usb_dc_cfg.out_ep[ep_idx].ep_mps;
|
||||
}
|
||||
|
||||
read_count = (usb_dc_cfg.grxstsp & USB_OTG_GRXSTSP_BCNT) >> 4;
|
||||
read_count = MIN(read_count, max_data_len);
|
||||
|
||||
len32b = ((uint32_t)read_count + 3U) / 4U;
|
||||
|
||||
for (uint8_t i = 0U; i < len32b; i++) {
|
||||
*pdest = USBx_DFIFO(0U);
|
||||
pdest++;
|
||||
}
|
||||
|
||||
if (read_bytes) {
|
||||
*read_bytes = read_count;
|
||||
}
|
||||
|
||||
usb_dc_cfg.grxstsp = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles PCD interrupt request.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
void USBD_IRQHandler(void)
|
||||
{
|
||||
USB_OTG_GlobalTypeDef *USBx = usb_dc_cfg.Instance;
|
||||
uint32_t gint_status, temp, epnum, ep_intr, epint;
|
||||
uint32_t USBx_BASE = (uint32_t)USBx;
|
||||
gint_status = USBx->GINTSTS;
|
||||
|
||||
if ((gint_status & 0x1U) == USB_OTG_MODE_DEVICE) {
|
||||
if (gint_status == 0) {
|
||||
return;
|
||||
}
|
||||
/* Handle RxQLevel Interrupt */
|
||||
if (gint_status & USB_OTG_GINTSTS_RXFLVL) {
|
||||
USB_MASK_INTERRUPT(USBx, USB_OTG_GINTSTS_RXFLVL);
|
||||
temp = USBx->GRXSTSP;
|
||||
usb_dc_cfg.grxstsp = temp;
|
||||
epnum = temp & USB_OTG_GRXSTSP_EPNUM;
|
||||
if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> USB_OTG_GRXSTSP_PKTSTS_Pos) == STS_DATA_UPDT) {
|
||||
if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) {
|
||||
if (epnum == 0) {
|
||||
usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
|
||||
} else {
|
||||
usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(epnum | USB_EP_DIR_OUT));
|
||||
}
|
||||
}
|
||||
} else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> USB_OTG_GRXSTSP_PKTSTS_Pos) == STS_SETUP_UPDT) {
|
||||
uint8_t len = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
|
||||
usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
|
||||
} else {
|
||||
/* ... */
|
||||
}
|
||||
USB_UNMASK_INTERRUPT(USBx, USB_OTG_GINTSTS_RXFLVL);
|
||||
}
|
||||
|
||||
if (gint_status & USB_OTG_GINTSTS_OEPINT) {
|
||||
epnum = 0;
|
||||
/* Read in the device interrupt bits */
|
||||
ep_intr = USBx_DEVICE->DAINT;
|
||||
ep_intr &= USBx_DEVICE->DAINTMSK;
|
||||
ep_intr >>= 16;
|
||||
|
||||
while (ep_intr != 0U) {
|
||||
if ((ep_intr & 0x1U) != 0U) {
|
||||
epint = USBx_OUTEP((uint32_t)epnum)->DOEPINT;
|
||||
|
||||
epint &= USBx_DEVICE->DOEPMSK;
|
||||
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) {
|
||||
USBx_OUTEP(epnum)->DOEPINT = (USB_OTG_DOEPINT_STUP);
|
||||
|
||||
USBx_OUTEP(epnum)->DOEPTSIZ = 1U << USB_OTG_DOEPTSIZ_PKTCNT_Pos |
|
||||
(USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_MPSIZ) << USB_OTG_DOEPTSIZ_XFRSIZ_Pos;
|
||||
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;
|
||||
}
|
||||
if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) {
|
||||
USBx_OUTEP(epnum)->DOEPINT = (USB_OTG_DOEPINT_XFRC);
|
||||
|
||||
if (epnum == 0) {
|
||||
USBx_OUTEP(epnum)->DOEPTSIZ = 1U << USB_OTG_DOEPTSIZ_PKTCNT_Pos |
|
||||
(USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_MPSIZ) << USB_OTG_DOEPTSIZ_XFRSIZ_Pos;
|
||||
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;
|
||||
}
|
||||
}
|
||||
}
|
||||
ep_intr >>= 1U;
|
||||
epnum++;
|
||||
}
|
||||
}
|
||||
if (gint_status & USB_OTG_GINTSTS_IEPINT) {
|
||||
epnum = 0U;
|
||||
ep_intr = USBx_DEVICE->DAINT & 0xFFFF;
|
||||
ep_intr &= USBx_DEVICE->DAINTMSK;
|
||||
while (ep_intr != 0U) {
|
||||
if ((ep_intr & 0x1U) != 0U) {
|
||||
epint = USBx_INEP((uint32_t)epnum)->DIEPINT;
|
||||
epint &= USBx_DEVICE->DIEPMSK;
|
||||
|
||||
if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) {
|
||||
USBx_INEP(epnum)->DIEPINT = USB_OTG_DIEPINT_XFRC;
|
||||
if (epnum == 0) {
|
||||
usbd_event_notify_handler(USBD_EVENT_EP0_IN_NOTIFY, NULL);
|
||||
} else {
|
||||
usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(epnum | USB_EP_DIR_IN));
|
||||
}
|
||||
}
|
||||
}
|
||||
ep_intr >>= 1U;
|
||||
epnum++;
|
||||
}
|
||||
}
|
||||
if (gint_status & USB_OTG_GINTSTS_USBRST) {
|
||||
USBx->GINTSTS |= USB_OTG_GINTSTS_USBRST;
|
||||
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
|
||||
|
||||
usb_flush_txfifo(USBx, 0x10U);
|
||||
usb_flush_rxfifo(USBx);
|
||||
for (uint8_t i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
|
||||
USBx_INEP(i)->DIEPINT = 0xFB7FU;
|
||||
USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
|
||||
USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
|
||||
USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
|
||||
USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
|
||||
USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
|
||||
}
|
||||
USBx_DEVICE->DAINTMSK |= 0x10001U;
|
||||
|
||||
USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
|
||||
USB_OTG_DOEPMSK_XFRCM;
|
||||
|
||||
USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
|
||||
USB_OTG_DIEPMSK_XFRCM;
|
||||
|
||||
USBx_OUTEP(0U)->DOEPTSIZ = 0U;
|
||||
USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
|
||||
USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
|
||||
USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
|
||||
USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;
|
||||
|
||||
usbd_event_notify_handler(USBD_EVENT_RESET, NULL);
|
||||
}
|
||||
if (gint_status & USB_OTG_GINTSTS_ENUMDNE) {
|
||||
USBx->GINTSTS |= USB_OTG_GINTSTS_ENUMDNE;
|
||||
//uint8_t speed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;
|
||||
/* Set the MPS of the IN EP0 to 64 bytes */
|
||||
USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
|
||||
|
||||
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
|
||||
}
|
||||
if (gint_status & USB_OTG_GINTSTS_SOF) {
|
||||
USBx->GINTSTS |= USB_OTG_GINTSTS_SOF;
|
||||
}
|
||||
if (gint_status & USB_OTG_GINTSTS_USBSUSP) {
|
||||
USBx->GINTSTS |= USB_OTG_GINTSTS_USBSUSP;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int usb_flush_rxfifo(USB_OTG_GlobalTypeDef *USBx)
|
||||
{
|
||||
uint32_t count = 0;
|
||||
|
||||
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
|
||||
|
||||
do {
|
||||
if (++count > 200000U) {
|
||||
return -1;
|
||||
}
|
||||
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int usb_flush_txfifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
|
||||
{
|
||||
uint32_t count = 0U;
|
||||
|
||||
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
|
||||
|
||||
do {
|
||||
if (++count > 200000U) {
|
||||
return -1;
|
||||
}
|
||||
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void usb_set_txfifo(USB_OTG_GlobalTypeDef *USBx, uint8_t fifo, uint16_t size)
|
||||
{
|
||||
uint8_t i;
|
||||
uint32_t Tx_Offset;
|
||||
|
||||
/* TXn min size = 16 words. (n : Transmit FIFO index)
|
||||
When a TxFIFO is not used, the Configuration should be as follows:
|
||||
case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
|
||||
--> Txm can use the space allocated for Txn.
|
||||
case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
|
||||
--> Txn should be configured with the minimum space of 16 words
|
||||
The FIFO is used optimally when used TxFIFOs are allocated in the top
|
||||
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
|
||||
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
|
||||
|
||||
Tx_Offset = USBx->GRXFSIZ;
|
||||
|
||||
if (fifo == 0U) {
|
||||
USBx->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;
|
||||
} else {
|
||||
Tx_Offset += (USBx->DIEPTXF0_HNPTXFSIZ) >> 16;
|
||||
for (i = 0U; i < (fifo - 1U); i++) {
|
||||
Tx_Offset += (USBx->DIEPTXF[i] >> 16);
|
||||
}
|
||||
|
||||
/* Multiply Tx_Size by 2 to get higher performance */
|
||||
USBx->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;
|
||||
}
|
||||
}
|
||||
@@ -7,7 +7,7 @@
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
|
||||
__IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
|
||||
__IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
|
||||
__IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
|
||||
__IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
|
||||
@@ -22,9 +22,18 @@ typedef struct
|
||||
uint32_t Reserved30[2]; /*!< Reserved 030h */
|
||||
__IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
|
||||
__IO uint32_t CID; /*!< User ID Register 03Ch */
|
||||
uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
|
||||
__IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
|
||||
__IO uint32_t GHWCFG1; /* User HW config1 044h*/
|
||||
__IO uint32_t GHWCFG2; /* User HW config2 048h*/
|
||||
__IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
|
||||
uint32_t Reserved6; /*!< Reserved 050h */
|
||||
__IO uint32_t GLPMCFG; /*!< LPM Register 054h */
|
||||
__IO uint32_t GPWRDN; /*!< Power Down Register 058h */
|
||||
__IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
|
||||
__IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
|
||||
uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
|
||||
__IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
|
||||
__IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
|
||||
__IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
|
||||
} USB_OTG_GlobalTypeDef;
|
||||
|
||||
/**
|
||||
@@ -111,12 +120,18 @@ typedef struct
|
||||
uint32_t Reserved[2]; /*!< Reserved */
|
||||
} USB_OTG_HostChannelTypeDef;
|
||||
|
||||
/*!< USB registers base address */
|
||||
#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
|
||||
#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
|
||||
|
||||
#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
|
||||
#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
|
||||
#define USB_OTG_GLOBAL_BASE 0x000UL
|
||||
#define USB_OTG_DEVICE_BASE 0x800UL
|
||||
#define USB_OTG_IN_ENDPOINT_BASE 0x900UL
|
||||
#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
|
||||
#define USB_OTG_EP_REG_SIZE 0x20UL
|
||||
#define USB_OTG_HOST_BASE 0x400UL
|
||||
#define USB_OTG_HOST_PORT_BASE 0x440UL
|
||||
#define USB_OTG_HOST_CHANNEL_BASE 0x500UL
|
||||
#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
|
||||
#define USB_OTG_PCGCCTL_BASE 0xE00UL
|
||||
#define USB_OTG_FIFO_BASE 0x1000UL
|
||||
#define USB_OTG_FIFO_SIZE 0x1000UL
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@@ -130,6 +145,24 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
|
||||
#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
|
||||
#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
|
||||
#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
|
||||
#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
|
||||
#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
|
||||
#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
|
||||
#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
|
||||
#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
|
||||
#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
|
||||
#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
|
||||
#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
|
||||
#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
|
||||
#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
|
||||
#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
|
||||
#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
|
||||
#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
|
||||
#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
|
||||
#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
|
||||
#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
|
||||
#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
|
||||
@@ -142,6 +175,9 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
|
||||
#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
|
||||
#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
|
||||
#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
|
||||
#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
|
||||
#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
|
||||
#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
|
||||
#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
|
||||
@@ -151,9 +187,12 @@ typedef struct
|
||||
#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
|
||||
#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
|
||||
#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
|
||||
#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
|
||||
#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
|
||||
#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
|
||||
#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
|
||||
#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
|
||||
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
|
||||
|
||||
@@ -578,6 +617,9 @@ typedef struct
|
||||
#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
|
||||
#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
|
||||
#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
|
||||
#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
|
||||
#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
|
||||
#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
|
||||
#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
|
||||
#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
|
||||
@@ -587,6 +629,9 @@ typedef struct
|
||||
#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
|
||||
#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
|
||||
#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
|
||||
#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
|
||||
#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
|
||||
#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
|
||||
#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
|
||||
#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
|
||||
#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
|
||||
@@ -658,6 +703,9 @@ typedef struct
|
||||
#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
|
||||
#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
|
||||
#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
|
||||
#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
|
||||
#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
|
||||
#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
|
||||
#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
|
||||
#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
|
||||
@@ -667,6 +715,9 @@ typedef struct
|
||||
#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
|
||||
#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
|
||||
#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
|
||||
#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
|
||||
#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
|
||||
#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
|
||||
#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
|
||||
#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
|
||||
#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
|
||||
@@ -688,6 +739,48 @@ typedef struct
|
||||
#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
|
||||
#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
|
||||
|
||||
/******************** Bit definition for OTG register ********************/
|
||||
#define USB_OTG_CHNUM_Pos (0U)
|
||||
#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
|
||||
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
|
||||
#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
|
||||
#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
|
||||
#define USB_OTG_BCNT_Pos (4U)
|
||||
#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
|
||||
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
|
||||
|
||||
#define USB_OTG_DPID_Pos (15U)
|
||||
#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
|
||||
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
|
||||
#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
|
||||
|
||||
#define USB_OTG_PKTSTS_Pos (17U)
|
||||
#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
|
||||
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
|
||||
#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
|
||||
#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
|
||||
|
||||
#define USB_OTG_EPNUM_Pos (0U)
|
||||
#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
|
||||
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
|
||||
#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
|
||||
#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
|
||||
|
||||
#define USB_OTG_FRMNUM_Pos (21U)
|
||||
#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
|
||||
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
|
||||
#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
|
||||
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
|
||||
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
|
||||
|
||||
/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
|
||||
#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
|
||||
#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
|
||||
@@ -826,9 +919,37 @@ typedef struct
|
||||
#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
|
||||
|
||||
/******************** Bit definition for USB_OTG_GCCFG register ********************/
|
||||
#define USB_OTG_GCCFG_DCDET_Pos (0U)
|
||||
#define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
|
||||
#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
|
||||
#define USB_OTG_GCCFG_PDET_Pos (1U)
|
||||
#define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
|
||||
#define USB_OTG_GCCFG_SDET_Pos (2U)
|
||||
#define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
|
||||
#define USB_OTG_GCCFG_PS2DET_Pos (3U)
|
||||
#define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
|
||||
#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
|
||||
#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
|
||||
#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
|
||||
#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
|
||||
#define USB_OTG_GCCFG_BCDEN_Pos (17U)
|
||||
#define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
|
||||
#define USB_OTG_GCCFG_DCDEN_Pos (18U)
|
||||
#define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
|
||||
#define USB_OTG_GCCFG_PDEN_Pos (19U)
|
||||
#define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
|
||||
#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
|
||||
#define USB_OTG_GCCFG_SDEN_Pos (20U)
|
||||
#define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
|
||||
#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
|
||||
#define USB_OTG_GCCFG_VBDEN_Pos (21U)
|
||||
#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
|
||||
|
||||
#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
|
||||
#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
|
||||
@@ -845,6 +966,14 @@ typedef struct
|
||||
#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
|
||||
#define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
|
||||
#define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
|
||||
#define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */
|
||||
#define USB_OTG_GPWRDN_ADPIF_Pos (23U)
|
||||
#define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
|
||||
#define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
|
||||
#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
|
||||
#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
|
||||
@@ -858,6 +987,53 @@ typedef struct
|
||||
#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
|
||||
#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
|
||||
|
||||
/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
|
||||
#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
|
||||
#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
|
||||
#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
|
||||
#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
|
||||
#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
|
||||
#define USB_OTG_GLPMCFG_BESL_Pos (2U)
|
||||
#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
|
||||
#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
|
||||
#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
|
||||
#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
|
||||
#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
|
||||
#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
|
||||
#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
|
||||
#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
|
||||
#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
|
||||
#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
|
||||
#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
|
||||
#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
|
||||
#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
|
||||
#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
|
||||
#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
|
||||
#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
|
||||
#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
|
||||
#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
|
||||
#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
|
||||
#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
|
||||
#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
|
||||
#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
|
||||
#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
|
||||
#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
|
||||
#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
|
||||
#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
|
||||
#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
|
||||
#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
|
||||
#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
|
||||
#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
|
||||
#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
|
||||
#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
|
||||
#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
|
||||
#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
|
||||
#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
|
||||
#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
|
||||
|
||||
/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
|
||||
#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
|
||||
#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
|
||||
@@ -1345,6 +1521,9 @@ typedef struct
|
||||
#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
|
||||
#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
|
||||
#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */
|
||||
#define USB_OTG_DOEPINT_BERR_Pos (12U)
|
||||
#define USB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
|
||||
#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */
|
||||
#define USB_OTG_DOEPINT_NAK_Pos (13U)
|
||||
#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
|
||||
#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */
|
||||
@@ -1380,51 +1559,6 @@ typedef struct
|
||||
#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
|
||||
#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
|
||||
|
||||
/* Legacy define */
|
||||
/******************** Bit definition for OTG register ********************/
|
||||
#define USB_OTG_CHNUM_Pos (0U)
|
||||
#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
|
||||
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
|
||||
#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
|
||||
#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
|
||||
#define USB_OTG_BCNT_Pos (4U)
|
||||
#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
|
||||
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
|
||||
|
||||
#define USB_OTG_DPID_Pos (15U)
|
||||
#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
|
||||
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
|
||||
#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
|
||||
|
||||
#define USB_OTG_PKTSTS_Pos (17U)
|
||||
#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
|
||||
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
|
||||
#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
|
||||
#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
|
||||
|
||||
#define USB_OTG_EPNUM_Pos (0U)
|
||||
#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
|
||||
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
|
||||
#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
|
||||
#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
|
||||
#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
|
||||
#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
|
||||
|
||||
#define USB_OTG_FRMNUM_Pos (21U)
|
||||
#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
|
||||
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
|
||||
#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
|
||||
#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
|
||||
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
|
||||
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
|
||||
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_CORE VERSION ID
|
||||
* @{
|
||||
*/
|
||||
|
||||
Reference in New Issue
Block a user