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delete repeatable file

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This commit is contained in:
sakumisu
2022-01-26 21:59:15 +08:00
parent 43005a1b89
commit a8a9a9b41f
6 changed files with 17 additions and 2339 deletions
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33
port/fsdev/usb_dc_fsdev.c
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@@ -352,26 +352,27 @@ void USBD_IRQHandler(void)
USBx->DADDR = ((uint16_t)usb_dc_cfg.USB_Address | USB_DADDR_EF);
usb_dc_cfg.USB_Address = 0U;
}
}
/* DIR = 1 */
} else {
/* DIR = 1 */
/* DIR = 1 & CTR_RX => SETUP or OUT int */
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
/* DIR = 1 & CTR_RX => SETUP or OUT int */
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
wEPVal = PCD_GET_ENDPOINT(USBx, 0);
wEPVal = PCD_GET_ENDPOINT(USBx, 0);
if ((wEPVal & USB_EP_SETUP) != 0U) {
/* SETUP bit kept frozen while CTR_RX = 1 */
PCD_CLEAR_RX_EP_CTR(USBx, 0);
if ((wEPVal & USB_EP_SETUP) != 0U) {
/* SETUP bit kept frozen while CTR_RX = 1 */
PCD_CLEAR_RX_EP_CTR(USBx, 0);
/* Process SETUP Packet*/
usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
PCD_SET_EP_RX_STATUS(USBx, 0, USB_EP_RX_VALID);
} else if ((wEPVal & USB_EP_CTR_RX) != 0U) {
PCD_CLEAR_RX_EP_CTR(USBx, 0);
/* Process Control Data OUT Packet */
usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
PCD_SET_EP_RX_STATUS(USBx, 0, USB_EP_RX_VALID);
/* Process SETUP Packet*/
usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
PCD_SET_EP_RX_STATUS(USBx, 0, USB_EP_RX_VALID);
} else if ((wEPVal & USB_EP_CTR_RX) != 0U) {
PCD_CLEAR_RX_EP_CTR(USBx, 0);
/* Process Control Data OUT Packet */
usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
PCD_SET_EP_RX_STATUS(USBx, 0, USB_EP_RX_VALID);
}
}
} else {
/* Decode and service non control endpoints interrupt */

1070
port/fsdev/usb_fsdev_reg.h
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File diff suppressed because it is too large Load Diff

10
port/stm32/README.md
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@@ -1,10 +0,0 @@
# 基本工程生成
- 首先使用 stm32cubemx 使能系统时钟、USB时钟、USB引脚，勾选 USB外设、使能 USB 中断，然后产生基本工程。
- 如果使用的是 usb_dc_nohal.c，需要注释掉 MX_USB_PCD_Init 函数，USB 中断中调用 USBD_IRQHandler 替代 HAL_PCD_IRQHandler 函数，HAL_PCD_MspInit 函数保留
- 如果使用的是 usb_dc_hal.c 则上条不需要
- 推荐使用 nohal 版本，极简代码
## 该目录下porting可以不再使用，选择 fsdev 或者 synopsys下的porting接口

441
port/stm32/usb_dc_hal.c
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@@ -1,441 +0,0 @@
#include "usbd_core.h"
#include "usbd_config.h"
#ifndef USB_NUM_BIDIR_ENDPOINTS
#define USB_NUM_BIDIR_ENDPOINTS 6
#endif
#ifdef USB
#ifndef USB_RAM_SIZE
#define USB_RAM_SIZE 512
#endif
extern PCD_HandleTypeDef hpcd_USB_FS;
#define PCD_HANDLE &hpcd_USB_FS
#else
#ifdef CONFIG_USB_HS
#ifndef USB_RAM_SIZE
#define USB_RAM_SIZE 4096
#endif
extern PCD_HandleTypeDef hpcd_USB_OTG_HS;
#define PCD_HANDLE &hpcd_USB_OTG_HS
#else
#ifndef USB_RAM_SIZE
#define USB_RAM_SIZE 1280
#endif
//extern PCD_HandleTypeDef hpcd_USB_OTG_HS;
//#define PCD_HANDLE &hpcd_USB_OTG_HS
extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
#define PCD_HANDLE &hpcd_USB_OTG_FS
#endif
#endif
#ifdef USB
#define EP0_MPS 64U
#define EP_MPS 64U
/*
* USB BTABLE is stored in the PMA. The size of BTABLE is 4 bytes
* per endpoint.
*
*/
#define USB_BTABLE_SIZE (8 * USB_NUM_BIDIR_ENDPOINTS)
#else /* USB_OTG_FS */
#define EP0_MPS USB_OTG_MAX_EP0_SIZE
#ifdef CONFIG_USB_HS
#define EP_MPS USB_OTG_HS_MAX_PACKET_SIZE
#else
#define EP_MPS USB_OTG_FS_MAX_PACKET_SIZE
#endif
#define CONTROL_EP_NUM 1
/*this should user make config*/
#define OUT_EP_NUM 2
#define OUT_EP_MPS 1024
#define EP_RX_FIFO_WORDS ((4 * CONTROL_EP_NUM + 6) + ((OUT_EP_MPS / 4) + 1) + 2 * OUT_EP_NUM + 1)
#define EP_TX_FIFO_WORDS 0x40
#endif /* USB */
/* Endpoint state */
struct usb_dc_ep_state {
uint16_t ep_mps; /** Endpoint max packet size */
#ifdef USB
uint16_t ep_pma_buf_len; /** Previously allocated buffer size */
#endif
uint8_t ep_type; /** Endpoint type (STM32 HAL enum) */
uint8_t ep_stalled; /** Endpoint stall flag */
uint32_t read_count; /** Number of bytes in read buffer */
uint32_t read_offset; /** Current offset in read buffer */
};
/* Driver state */
struct usb_dc_pcd_state {
struct usb_dc_ep_state out_ep_state[USB_NUM_BIDIR_ENDPOINTS];
struct usb_dc_ep_state in_ep_state[USB_NUM_BIDIR_ENDPOINTS];
uint8_t ep_buf[USB_NUM_BIDIR_ENDPOINTS][EP_MPS];
#ifdef USB
uint32_t pma_offset;
#endif /* USB */
};
static struct usb_dc_pcd_state usb_dc_pcd_state;
/* Internal functions */
static struct usb_dc_ep_state *usb_dc_stm32_get_ep_state(uint8_t ep)
{
struct usb_dc_ep_state *ep_state_base;
if (USB_EP_GET_IDX(ep) >= USB_NUM_BIDIR_ENDPOINTS) {
return NULL;
}
if (USB_EP_DIR_IS_OUT(ep)) {
ep_state_base = usb_dc_pcd_state.out_ep_state;
} else {
ep_state_base = usb_dc_pcd_state.in_ep_state;
}
return ep_state_base + USB_EP_GET_IDX(ep);
}
int usb_dc_init(void)
{
HAL_StatusTypeDef status;
unsigned int i;
/*pcd has init*/
status = HAL_PCD_Start(PCD_HANDLE);
if (status != HAL_OK) {
return -2;
}
usb_dc_pcd_state.out_ep_state[0].ep_mps = EP0_MPS;
usb_dc_pcd_state.out_ep_state[0].ep_type = EP_TYPE_CTRL;
usb_dc_pcd_state.in_ep_state[0].ep_mps = EP0_MPS;
usb_dc_pcd_state.in_ep_state[0].ep_type = EP_TYPE_CTRL;
#ifdef USB
/* Start PMA configuration for the endpoints after the BTABLE. */
usb_dc_pcd_state.pma_offset = USB_BTABLE_SIZE;
#else /* USB_OTG_FS */
/* TODO: make this dynamic (depending usage) */
HAL_PCDEx_SetRxFiFo(PCD_HANDLE, EP_RX_FIFO_WORDS);
for (i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
HAL_PCDEx_SetTxFiFo(PCD_HANDLE, i,
EP_TX_FIFO_WORDS);
}
#endif /* USB */
return 0;
}
void usb_dc_deinit(void)
{
}
int usbd_set_address(const uint8_t addr)
{
HAL_StatusTypeDef status;
status = HAL_PCD_SetAddress(PCD_HANDLE, addr);
if (status != HAL_OK) {
return -2;
}
return 0;
}
int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
{
HAL_StatusTypeDef status;
uint8_t ep = ep_cfg->ep_addr;
struct usb_dc_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
if (!ep_state) {
return -1;
}
#ifdef USB
if (ep_cfg->ep_mps > ep_state->ep_pma_buf_len) {
if (USB_RAM_SIZE <=
(usb_dc_pcd_state.pma_offset + ep_cfg->ep_mps)) {
return -1;
}
HAL_PCDEx_PMAConfig(&hpcd_USB_FS, ep, PCD_SNG_BUF,
usb_dc_pcd_state.pma_offset);
ep_state->ep_pma_buf_len = ep_cfg->ep_mps;
usb_dc_pcd_state.pma_offset += ep_cfg->ep_mps;
}
#endif
ep_state->ep_mps = ep_cfg->ep_mps;
switch (ep_cfg->ep_type) {
case USBD_EP_TYPE_CTRL:
ep_state->ep_type = EP_TYPE_CTRL;
break;
case USBD_EP_TYPE_ISOC:
ep_state->ep_type = EP_TYPE_ISOC;
break;
case USBD_EP_TYPE_BULK:
ep_state->ep_type = EP_TYPE_BULK;
break;
case USBD_EP_TYPE_INTR:
ep_state->ep_type = EP_TYPE_INTR;
break;
default:
return -1;
}
status = HAL_PCD_EP_Open(PCD_HANDLE, ep,
ep_state->ep_mps, ep_state->ep_type);
if (status != HAL_OK) {
return -1;
}
if (USB_EP_DIR_IS_OUT(ep) && ep != USB_CONTROL_OUT_EP0) {
return HAL_PCD_EP_Receive(PCD_HANDLE, ep,
usb_dc_pcd_state.ep_buf[USB_EP_GET_IDX(ep)],
EP_MPS);
}
return 0;
}
int usbd_ep_close(const uint8_t ep)
{
struct usb_dc_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
HAL_StatusTypeDef status;
if (!ep_state) {
return -1;
}
status = HAL_PCD_EP_Close(PCD_HANDLE, ep);
if (status != HAL_OK) {
return -2;
}
return 0;
}
int usbd_ep_set_stall(const uint8_t ep)
{
struct usb_dc_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
HAL_StatusTypeDef status;
if (!ep_state) {
return -1;
}
status = HAL_PCD_EP_SetStall(PCD_HANDLE, ep);
if (status != HAL_OK) {
return -2;
}
ep_state->ep_stalled = 1U;
return 0;
}
int usbd_ep_clear_stall(const uint8_t ep)
{
struct usb_dc_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
HAL_StatusTypeDef status;
if (!ep_state) {
return -1;
}
status = HAL_PCD_EP_ClrStall(PCD_HANDLE, ep);
if (status != HAL_OK) {
return -2;
}
ep_state->ep_stalled = 0U;
ep_state->read_count = 0U;
return 0;
}
int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
{
struct usb_dc_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
if (!ep_state || !stalled) {
return -1;
}
*stalled = ep_state->ep_stalled;
return 0;
}
int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes)
{
struct usb_dc_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
HAL_StatusTypeDef status;
int ret = 0;
if (!ep_state || !USB_EP_DIR_IS_IN(ep)) {
return -1;
}
if (ep == USB_CONTROL_IN_EP0 && data_len > 64) {
data_len = 64;
}
status = HAL_PCD_EP_Transmit(PCD_HANDLE, ep,
(void *)data, data_len);
if (status != HAL_OK) {
ret = -2;
}
if (!ret && ep == USB_CONTROL_IN_EP0 && data_len > 0) {
/* Wait for an empty package as from the host.
* This also flushes the TX FIFO to the host.
*/
status = HAL_PCD_EP_Receive(PCD_HANDLE, ep,
usb_dc_pcd_state.ep_buf[USB_EP_GET_IDX(ep)],
0);
if (status != HAL_OK) {
return -2;
}
}
if (!ret && ret_bytes) {
*ret_bytes = data_len;
}
return ret;
}
int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_t *read_bytes)
{
struct usb_dc_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
uint32_t read_count;
HAL_StatusTypeDef status;
if (!ep_state) {
return -1;
}
if (!USB_EP_DIR_IS_OUT(ep)) { /* check if OUT ep */
return -1;
}
if (!data && max_data_len) {
return -1;
}
if (max_data_len == 0) {
/* If no more data in the buffer, start a new read transaction.
* DataOutStageCallback will called on transaction complete.
*/
if (!ep_state->read_count) {
status = HAL_PCD_EP_Receive(PCD_HANDLE, ep,
usb_dc_pcd_state.ep_buf[USB_EP_GET_IDX(ep)],
EP_MPS);
if (status != HAL_OK) {
return -2;
}
}
return 0;
}
ep_state->read_count = HAL_PCD_EP_GetRxCount(PCD_HANDLE, ep);
ep_state->read_offset = 0U;
read_count = ep_state->read_count;
/* When both buffer and max data to read are zero, just ingore reading
* and return available data in buffer. Otherwise, return data
* previously stored in the buffer.
*/
if (data) {
read_count = MIN(read_count, max_data_len);
memcpy(data, usb_dc_pcd_state.ep_buf[USB_EP_GET_IDX(ep)] + ep_state->read_offset, read_count);
ep_state->read_count -= read_count;
ep_state->read_offset += read_count;
}
/* If no more data in the buffer, start a new read transaction.
* DataOutStageCallback will called on transaction complete.
*/
#if 0
if (!ep_state->read_count) {
status = HAL_PCD_EP_Receive(PCD_HANDLE, ep,
usb_dc_pcd_state.ep_buf[USB_EP_GET_IDX(ep)],
EP_MPS);
if (status != HAL_OK) {
return -2;
}
}
#endif
if (read_bytes) {
*read_bytes = read_count;
}
return 0;
}
/* Callbacks from the STM32 Cube HAL code */
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
}
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
{
usbd_event_notify_handler(USBD_EVENT_RESET, NULL);
}
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
{
}
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
{
}
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
{
}
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
{
}
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
{
struct usb_setup_packet *setup = (void *)hpcd->Setup;
memcpy(&usb_dc_pcd_state.ep_buf[0],
hpcd->Setup, 8);
usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
if (!(setup->wLength == 0U) &&
!(REQTYPE_GET_DIR(setup->bmRequestType) ==
USB_REQUEST_DIR_IN)) {
HAL_PCD_EP_Receive(PCD_HANDLE, 0x00,
usb_dc_pcd_state.ep_buf[0],
setup->wLength);
}
}
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
if (epnum == 0) {
usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
} else {
usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(epnum | USB_EP_DIR_OUT));
}
}
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
if (epnum == 0) {
usbd_event_notify_handler(USBD_EVENT_EP0_IN_NOTIFY, NULL);
} else {
usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(epnum | USB_EP_DIR_IN));
}
}

773
port/stm32/usb_dc_nohal.c
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@@ -1,773 +0,0 @@
#include "usbd_core.h"
#include "usbd_config.h"
#ifndef USB_NUM_BIDIR_ENDPOINTS
#define USB_NUM_BIDIR_ENDPOINTS 8
#endif
#ifdef USB
#ifndef USB_RAM_SIZE
#define USB_RAM_SIZE 512
#endif
#define USB_BTABLE_SIZE (8 * USB_NUM_BIDIR_ENDPOINTS)
#else
#ifdef CONFIG_USB_HS
#ifndef USB_RAM_SIZE
#define USB_RAM_SIZE 4096
#endif
#else
#ifndef USB_RAM_SIZE
#define USB_RAM_SIZE 1280
#endif
#endif
#endif
/* Endpoint state */
struct usb_dc_ep_state {
/** Endpoint max packet size */
uint16_t ep_mps;
/** Endpoint Transfer Type.
* May be Bulk, Interrupt, Control or Isochronous
*/
uint8_t ep_type;
uint8_t ep_stalled; /** Endpoint stall flag */
#ifdef USB
uint16_t ep_pma_buf_len; /** Previously allocated buffer size */
uint16_t ep_pma_addr; /**ep pmd allocated addr*/
#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
#endif
};
/* Driver state */
struct usb_dc_config_priv {
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address */
struct usb_dc_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/
struct usb_dc_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
#ifdef USB
uint32_t pma_offset;
#endif
} usb_dc_cfg;
int usb_dc_init(void)
{
memset(&usb_dc_cfg, 0, sizeof(struct usb_dc_config_priv));
#ifdef USB
usb_dc_cfg.Instance = USB;
usb_dc_cfg.pma_offset = USB_BTABLE_SIZE;
usb_dc_cfg.Init.speed = PCD_SPEED_FULL;
#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
#ifdef CONFIG_USB_HS
usb_dc_cfg.Instance = USB_OTG_HS;
usb_dc_cfg.Init.speed = PCD_SPEED_FULL;
usb_dc_cfg.Init.dma_enable = DISABLE;
usb_dc_cfg.Init.phy_itface = USB_OTG_ULPI_PHY;
usb_dc_cfg.Init.vbus_sensing_enable = DISABLE;
usb_dc_cfg.Init.use_dedicated_ep1 = DISABLE;
usb_dc_cfg.Init.use_external_vbus = DISABLE;
#else
//usb_dc_cfg.Instance = USB_OTG_HS; //run in full speed
usb_dc_cfg.Instance = USB_OTG_FS;
usb_dc_cfg.Init.speed = PCD_SPEED_FULL;
usb_dc_cfg.Init.dma_enable = DISABLE;
usb_dc_cfg.Init.phy_itface = USB_OTG_EMBEDDED_PHY;
usb_dc_cfg.Init.vbus_sensing_enable = DISABLE;
usb_dc_cfg.Init.use_dedicated_ep1 = DISABLE;
usb_dc_cfg.Init.use_external_vbus = DISABLE;
#endif
#endif
PCD_TypeDef *USBx = usb_dc_cfg.Instance;
usb_dc_cfg.Init.dev_endpoints = USB_NUM_BIDIR_ENDPOINTS;
usb_dc_cfg.Init.Sof_enable = DISABLE;
usb_dc_cfg.Init.low_power_enable = DISABLE;
usb_dc_cfg.Init.lpm_enable = DISABLE;
HAL_PCD_MspInit((PCD_HandleTypeDef *)&usb_dc_cfg);
#ifdef USB
USB_DisableGlobalInt(USBx);
USB_DevInit(USBx, usb_dc_cfg.Init);
USB_EnableGlobalInt(USBx);
#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
/* Disable DMA mode for FS instance */
#ifndef CONFIG_USB_HS
if ((USBx->CID & (0x1U << 8)) == 0U) {
usb_dc_cfg.Init.dma_enable = 0U;
}
#endif
/* Disable the Interrupts */
USB_DisableGlobalInt(USBx);
/*Init the Core (common init.) */
if (USB_CoreInit(usb_dc_cfg.Instance, usb_dc_cfg.Init) != HAL_OK) {
return -1;
}
/* Force Device Mode*/
(void)USB_SetCurrentMode(USBx, USB_DEVICE_MODE);
/* Init Device */
if (USB_DevInit(USBx, usb_dc_cfg.Init) != HAL_OK) {
return -1;
}
USB_DevDisconnect(USBx);
if ((usb_dc_cfg.Init.battery_charging_enable == 1U) &&
(usb_dc_cfg.Init.phy_itface != USB_OTG_ULPI_PHY)) {
/* Enable USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
}
(void)USB_DevConnect(USBx);
/* Enable the Interrupts */
USB_EnableGlobalInt(USBx);
#endif
return 0;
}
void usb_dc_deinit(void)
{
PCD_TypeDef *USBx = usb_dc_cfg.Instance;
USB_StopDevice(USBx);
HAL_PCD_MspDeInit((PCD_HandleTypeDef *)&usb_dc_cfg);
}
int usbd_set_address(const uint8_t addr)
{
PCD_TypeDef *USBx = usb_dc_cfg.Instance;
USB_SetDevAddress(USBx, addr);
usb_dc_cfg.USB_Address = addr;
return 0;
}
int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
{
PCD_TypeDef *USBx = usb_dc_cfg.Instance;
uint8_t ep_idx = USB_EP_GET_IDX(ep_cfg->ep_addr);
#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
uint32_t USBx_BASE = (uint32_t)USBx;
#endif
if (!ep_cfg) {
return -1;
}
#ifdef USB
uint16_t wEpRegVal;
wEpRegVal = PCD_GET_ENDPOINT(USBx, ep_idx) & USB_EP_T_MASK;
/* initialize Endpoint */
switch (ep_cfg->ep_type) {
case EP_TYPE_CTRL:
wEpRegVal |= USB_EP_CONTROL;
break;
case EP_TYPE_BULK:
wEpRegVal |= USB_EP_BULK;
break;
case EP_TYPE_INTR:
wEpRegVal |= USB_EP_INTERRUPT;
break;
case EP_TYPE_ISOC:
wEpRegVal |= USB_EP_ISOCHRONOUS;
break;
default:
break;
}
PCD_SET_ENDPOINT(USBx, ep_idx, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
PCD_SET_EP_ADDRESS(USBx, ep_idx, ep_idx);
if (USB_EP_DIR_IS_OUT(ep_cfg->ep_addr)) {
usb_dc_cfg.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
usb_dc_cfg.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
if (usb_dc_cfg.out_ep[ep_idx].ep_mps > usb_dc_cfg.out_ep[ep_idx].ep_pma_buf_len) {
if (usb_dc_cfg.pma_offset + usb_dc_cfg.out_ep[ep_idx].ep_mps >= 512) {
return -1;
}
usb_dc_cfg.out_ep[ep_idx].ep_pma_buf_len = ep_cfg->ep_mps;
usb_dc_cfg.out_ep[ep_idx].ep_pma_addr = usb_dc_cfg.pma_offset;
/*Set the endpoint Receive buffer address */
PCD_SET_EP_RX_ADDRESS(USBx, ep_idx, usb_dc_cfg.pma_offset);
usb_dc_cfg.pma_offset += ep_cfg->ep_mps;
}
/*Set the endpoint Receive buffer counter*/
PCD_SET_EP_RX_CNT(USBx, ep_idx, ep_cfg->ep_mps);
PCD_CLEAR_RX_DTOG(USBx, ep_idx);
/* Configure VALID status for the Endpoint*/
PCD_SET_EP_RX_STATUS(USBx, ep_idx, USB_EP_RX_VALID);
} else {
usb_dc_cfg.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
usb_dc_cfg.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
if (usb_dc_cfg.in_ep[ep_idx].ep_mps > usb_dc_cfg.in_ep[ep_idx].ep_pma_buf_len) {
if (usb_dc_cfg.pma_offset + usb_dc_cfg.in_ep[ep_idx].ep_mps >= USB_RAM_SIZE) {
return -1;
}
usb_dc_cfg.in_ep[ep_idx].ep_pma_buf_len = ep_cfg->ep_mps;
usb_dc_cfg.in_ep[ep_idx].ep_pma_addr = usb_dc_cfg.pma_offset;
/*Set the endpoint Transmit buffer address */
PCD_SET_EP_TX_ADDRESS(USBx, ep_idx, usb_dc_cfg.pma_offset);
usb_dc_cfg.pma_offset += ep_cfg->ep_mps;
}
PCD_CLEAR_TX_DTOG(USBx, ep_idx);
if (ep_cfg->ep_type != EP_TYPE_ISOC) {
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_NAK);
} else {
/* Configure TX Endpoint to disabled state */
PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_DIS);
}
}
#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
if (USB_EP_DIR_IS_OUT(ep_cfg->ep_addr)) {
usb_dc_cfg.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
usb_dc_cfg.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep_idx & EP_ADDR_MSK)) << 16);
if (((USBx_OUTEP(ep_idx)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) {
USBx_OUTEP(ep_idx)->DOEPCTL |= (ep_cfg->ep_mps & USB_OTG_DOEPCTL_MPSIZ) |
((uint32_t)ep_cfg->ep_type << 18) |
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
USB_OTG_DOEPCTL_USBAEP;
}
} else {
usb_dc_cfg.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
usb_dc_cfg.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep_idx & EP_ADDR_MSK));
if ((USBx_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) {
USBx_INEP(ep_idx)->DIEPCTL |= (ep_cfg->ep_mps & USB_OTG_DIEPCTL_MPSIZ) |
((uint32_t)ep_cfg->ep_type << 18) | (ep_idx << 22) |
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
USB_OTG_DIEPCTL_USBAEP;
}
}
#endif
return 0;
}
int usbd_ep_close(const uint8_t ep)
{
PCD_TypeDef *USBx = usb_dc_cfg.Instance;
uint8_t ep_idx = USB_EP_GET_IDX(ep);
#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
uint32_t USBx_BASE = (uint32_t)USBx;
#endif
if (USB_EP_DIR_IS_OUT(ep)) {
#ifdef USB
PCD_CLEAR_RX_DTOG(USBx, ep_idx);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_RX_STATUS(USBx, ep_idx, USB_EP_RX_DIS);
#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
if (((USBx_OUTEP(ep_idx)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) {
USBx_OUTEP(ep_idx)->DOEPCTL |= (usb_dc_cfg.out_ep[ep_idx].ep_mps & USB_OTG_DOEPCTL_MPSIZ) |
((uint32_t)usb_dc_cfg.out_ep[ep_idx].ep_type << 18) | (ep_idx << 22) |
USB_OTG_DOEPCTL_USBAEP;
}
USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep_idx & EP_ADDR_MSK)) << 16);
#endif
} else {
#ifdef USB
PCD_CLEAR_TX_DTOG(USBx, ep_idx);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_DIS);
#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
if (((USBx_INEP(ep_idx)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) {
USBx_INEP(ep_idx)->DIEPCTL |= (usb_dc_cfg.in_ep[ep_idx].ep_mps & USB_OTG_DIEPCTL_MPSIZ) |
((uint32_t)usb_dc_cfg.in_ep[ep_idx].ep_type << 18) | (ep_idx << 22) |
USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
USB_OTG_DIEPCTL_USBAEP;
}
USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep_idx & EP_ADDR_MSK));
#endif
}
return 0;
}
int usbd_ep_set_stall(const uint8_t ep)
{
PCD_TypeDef *USBx = usb_dc_cfg.Instance;
uint8_t ep_idx = USB_EP_GET_IDX(ep);
#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
uint32_t USBx_BASE = (uint32_t)USBx;
#endif
if (USB_EP_DIR_IS_OUT(ep)) {
#ifdef USB
PCD_SET_EP_RX_STATUS(USBx, ep_idx, USB_EP_RX_STALL);
#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
if (((USBx_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (ep_idx != 0U)) {
USBx_OUTEP(ep_idx)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
}
USBx_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
#endif
} else {
#ifdef USB
PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_STALL);
#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
if (((USBx_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (ep_idx != 0U)) {
USBx_INEP(ep_idx)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
}
USBx_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
#endif
}
return 0;
}
int usbd_ep_clear_stall(const uint8_t ep)
{
PCD_TypeDef *USBx = usb_dc_cfg.Instance;
uint8_t ep_idx = USB_EP_GET_IDX(ep);
#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
uint32_t USBx_BASE = (uint32_t)USBx;
#endif
if (USB_EP_DIR_IS_OUT(ep)) {
#ifdef USB
PCD_CLEAR_TX_DTOG(USBx, ep_idx);
if (usb_dc_cfg.in_ep[ep_idx].ep_type != EP_TYPE_ISOC) {
/* Configure NAK status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_NAK);
}
#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
USBx_OUTEP(ep_idx)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
if ((usb_dc_cfg.out_ep[ep_idx].ep_type == EP_TYPE_INTR) || (usb_dc_cfg.out_ep[ep_idx].ep_type == EP_TYPE_BULK)) {
USBx_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
}
#endif
} else {
#ifdef USB
PCD_CLEAR_RX_DTOG(USBx, ep_idx);
/* Configure VALID status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep_idx, USB_EP_RX_VALID);
#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
USBx_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
if ((usb_dc_cfg.in_ep[ep_idx].ep_type == EP_TYPE_INTR) || (usb_dc_cfg.in_ep[ep_idx].ep_type == EP_TYPE_BULK)) {
USBx_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
}
#endif
}
return 0;
}
int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
{
PCD_TypeDef *USBx = usb_dc_cfg.Instance;
uint8_t ep_idx = USB_EP_GET_IDX(ep);
#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
uint32_t USBx_BASE = (uint32_t)USBx;
#endif
if (USB_EP_DIR_IS_OUT(ep)) {
} else {
}
return 0;
}
int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes)
{
PCD_TypeDef *USBx = usb_dc_cfg.Instance;
uint8_t ep_idx = USB_EP_GET_IDX(ep);
#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
uint32_t USBx_BASE = (uint32_t)USBx;
#endif
if (!data && data_len) {
return -1;
}
if (!data_len) {
#ifdef USB
PCD_SET_EP_TX_CNT(USBx, ep_idx, (uint16_t)0);
PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_VALID);
#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
/* EP enable, IN data in FIFO */
USBx_INEP(ep_idx)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
#endif
return 0;
}
if (data_len > usb_dc_cfg.in_ep[ep_idx].ep_mps) {
data_len = usb_dc_cfg.in_ep[ep_idx].ep_mps;
}
#ifdef USB
USB_WritePMA(USBx, (uint8_t *)data, usb_dc_cfg.in_ep[ep_idx].ep_pma_addr, (uint16_t)data_len);
PCD_SET_EP_TX_CNT(USBx, ep_idx, (uint16_t)data_len);
PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_VALID);
#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
if (ep_idx == 0x00) {
/* Program the transfer size and packet count
* as follows: xfersize = N * maxpacket +
* short_packet pktcnt = N + (short_packet
* exist ? 1 : 0)
*/
USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & data_len);
/* EP enable, IN data in FIFO */
USBx_INEP(ep_idx)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
/* Enable the Tx FIFO Empty Interrupt for this EP */
USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep_idx & EP_ADDR_MSK);
} else {
/* Program the transfer size and packet count
* as follows: xfersize = N * maxpacket +
* short_packet pktcnt = N + (short_packet
* exist ? 1 : 0)
*/
uint32_t len32b = (data_len + 3) / 4;
while ((USBx_INEP(ep_idx)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) {
}
USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((data_len + usb_dc_cfg.in_ep[ep_idx].ep_mps - 1U) / usb_dc_cfg.in_ep[ep_idx].ep_mps) << 19));
USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & data_len);
if (usb_dc_cfg.in_ep[ep_idx].ep_type == EP_TYPE_ISOC) {
USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
}
(void)USB_WritePacket(USBx, (uint8_t *)data, ep_idx, (uint16_t)data_len, 0);
/* EP enable, IN data in FIFO */
USBx_INEP(ep_idx)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
if (usb_dc_cfg.in_ep[ep_idx].ep_type != EP_TYPE_ISOC) {
/* Enable the Tx FIFO Empty Interrupt for this EP */
//USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep_idx & EP_ADDR_MSK);
} else {
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) {
USBx_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
} else {
USBx_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
}
}
}
#endif
if (ret_bytes) {
*ret_bytes = data_len;
}
return 0;
}
int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_t *read_bytes)
{
PCD_TypeDef *USBx = usb_dc_cfg.Instance;
uint8_t ep_idx = USB_EP_GET_IDX(ep);
#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
uint32_t USBx_BASE = (uint32_t)USBx;
#endif
uint32_t read_count;
if (!data && max_data_len) {
return -1;
}
if (!max_data_len) {
#ifdef USB
if (ep_idx != 0x00)
PCD_SET_EP_RX_STATUS(USBx, ep_idx, USB_EP_RX_VALID);
#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
/* Program the transfer size and packet count as follows:
* pktcnt = N
* xfersize = N * maxpacket
*/
USBx_OUTEP(ep_idx)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
USBx_OUTEP(ep_idx)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
USBx_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
USBx_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (usb_dc_cfg.out_ep[ep_idx].ep_mps));
if (usb_dc_cfg.out_ep[ep_idx].ep_type == EP_TYPE_ISOC) {
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) {
USBx_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
} else {
USBx_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
}
}
/* EP enable */
USBx_OUTEP(ep_idx)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
#endif
return 0;
}
#ifdef USB
read_count = PCD_GET_EP_RX_CNT(USBx, ep_idx);
read_count = MIN(read_count, max_data_len);
USB_ReadPMA(USBx, (uint8_t *)data,
usb_dc_cfg.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
read_count = (USBx->GRXSTSP & USB_OTG_GRXSTSP_BCNT) >> 4;
read_count = MIN(read_count, max_data_len);
(void)USB_ReadPacket(USBx, data, read_count);
USBx_OUTEP(ep_idx)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
USBx_OUTEP(ep_idx)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
USBx_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
USBx_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (usb_dc_cfg.out_ep[ep_idx].ep_mps));
if (usb_dc_cfg.out_ep[ep_idx].ep_type == EP_TYPE_ISOC) {
if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) {
USBx_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
} else {
USBx_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
}
}
/* EP enable */
USBx_OUTEP(ep_idx)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
#endif
if (read_bytes) {
*read_bytes = read_count;
}
return 0;
}
/**
* @brief This function handles PCD interrupt request.
* @param hpcd PCD handle
* @retval HAL status
*/
void USBD_IRQHandler(void)
{
PCD_TypeDef *USBx = usb_dc_cfg.Instance;
#ifdef USB
uint16_t wIstr, wEPVal;
uint8_t epindex;
wIstr = USBx->ISTR;
uint16_t store_ep[8];
if (wIstr & USB_ISTR_CTR) {
while ((USBx->ISTR & USB_ISTR_CTR) != 0U) {
wIstr = USBx->ISTR;
/* extract highest priority endpoint number */
epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
if (epindex == 0U) {
/* Decode and service control endpoint interrupt */
/* DIR bit = origin of the interrupt */
if ((wIstr & USB_ISTR_DIR) == 0U) {
/* DIR = 0 */
/* DIR = 0 => IN int */
/* DIR = 0 implies that (EP_CTR_TX = 1) always */
PCD_CLEAR_TX_EP_CTR(USBx, PCD_ENDP0);
usbd_event_notify_handler(USBD_EVENT_EP0_IN_NOTIFY, NULL);
if ((usb_dc_cfg.USB_Address > 0U) && (PCD_GET_EP_TX_CNT(USBx, PCD_ENDP0) == 0U)) {
USBx->DADDR = ((uint16_t)usb_dc_cfg.USB_Address | USB_DADDR_EF);
usb_dc_cfg.USB_Address = 0U;
}
}
/* DIR = 1 */
/* DIR = 1 & CTR_RX => SETUP or OUT int */
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
wEPVal = PCD_GET_ENDPOINT(USBx, PCD_ENDP0);
if ((wEPVal & USB_EP_SETUP) != 0U) {
/* SETUP bit kept frozen while CTR_RX = 1 */
PCD_CLEAR_RX_EP_CTR(USBx, PCD_ENDP0);
/* Process SETUP Packet*/
usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
PCD_SET_EP_RX_STATUS(USBx, 0, USB_EP_RX_VALID);
} else if ((wEPVal & USB_EP_CTR_RX) != 0U) {
PCD_CLEAR_RX_EP_CTR(USBx, PCD_ENDP0);
/* Process Control Data OUT Packet */
usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
PCD_SET_EP_RX_STATUS(USBx, 0, USB_EP_RX_VALID);
}
} else {
/* Decode and service non control endpoints interrupt */
/* process related endpoint register */
wEPVal = PCD_GET_ENDPOINT(USBx, epindex);
if ((wEPVal & USB_EP_CTR_RX) != 0U) {
/* clear int flag */
PCD_CLEAR_RX_EP_CTR(USBx, epindex);
usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(epindex & 0x7f));
}
if ((wEPVal & USB_EP_CTR_TX) != 0U) {
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(USBx, epindex);
usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(epindex | 0x80));
}
}
}
}
if (wIstr & USB_ISTR_RESET) {
usbd_event_notify_handler(USBD_EVENT_RESET, NULL);
USBx->ISTR &= (uint16_t)(~USB_ISTR_RESET);
}
if (wIstr & USB_ISTR_PMAOVR) {
USBx->ISTR &= (uint16_t)(~USB_ISTR_PMAOVR);
}
if (wIstr & USB_ISTR_ERR) {
USBx->ISTR &= (uint16_t)(~USB_ISTR_ERR);
}
if (wIstr & USB_ISTR_WKUP) {
USBx->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE);
USBx->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
USBx->ISTR &= (uint16_t)(~USB_ISTR_WKUP);
}
if (wIstr & USB_ISTR_SUSP) {
/* WA: To Clear Wakeup flag if raised with suspend signal */
/* Store Endpoint register */
for (uint8_t i = 0U; i < 8U; i++) {
store_ep[i] = PCD_GET_ENDPOINT(USBx, i);
}
/* FORCE RESET */
USBx->CNTR |= (uint16_t)(USB_CNTR_FRES);
/* CLEAR RESET */
USBx->CNTR &= (uint16_t)(~USB_CNTR_FRES);
/* wait for reset flag in ISTR */
while ((USBx->ISTR & USB_ISTR_RESET) == 0U) {
}
/* Clear Reset Flag */
USBx->ISTR &= (uint16_t)(~USB_ISTR_RESET);
/* Restore Registre */
for (uint8_t i = 0U; i < 8U; i++) {
PCD_SET_ENDPOINT(USBx, i, store_ep[i]);
}
/* Force low-power mode in the macrocell */
USBx->CNTR |= (uint16_t)USB_CNTR_FSUSP;
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
USBx->ISTR &= (uint16_t)(~USB_ISTR_SUSP);
USBx->CNTR |= (uint16_t)USB_CNTR_LP_MODE;
}
if (wIstr & USB_ISTR_SOF) {
USBx->ISTR &= (uint16_t)(~USB_ISTR_SOF);
}
if (wIstr & USB_ISTR_ESOF) {
USBx->ISTR &= (uint16_t)(~USB_ISTR_ESOF);
}
#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t int_status;
uint32_t temp, epindex, ep_intr, ep_int_status;
/* ensure that we are in device mode */
if (USB_GetMode(USBx) == USB_OTG_MODE_DEVICE) {
while (int_status == USB_ReadInterrupts(USBx)) {
if (int_status & USB_OTG_GINTSTS_USBRST) {
usbd_event_notify_handler(USBD_EVENT_RESET, NULL);
USBx->GINTSTS &= USB_OTG_GINTSTS_USBRST;
}
if (int_status & USB_OTG_GINTSTS_ENUMDNE) {
USBx->GINTSTS &= USB_OTG_GINTSTS_ENUMDNE;
}
if (int_status & USB_OTG_GINTSTS_RXFLVL) {
USB_MASK_INTERRUPT(USBx, USB_OTG_GINTSTS_RXFLVL);
temp = USBx->GRXSTSP;
epindex = temp & USB_OTG_GRXSTSP_EPNUM;
if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) {
if (epindex == 0)
usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
else {
usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(epindex & 0x7f));
}
} else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) {
usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
} else {
/* ... */
}
USB_UNMASK_INTERRUPT(USBx, USB_OTG_GINTSTS_RXFLVL);
}
if (int_status & USB_OTG_GINTSTS_IEPINT) {
epindex = 0U;
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllInEpInterrupt(USBx);
while (ep_intr != 0U) {
if ((ep_intr & 0x1U) != 0U) {
/* Read IN EP interrupt status */
ep_int_status = USB_ReadDevInEPInterrupt(USBx, (uint8_t)epindex);
/* Clear IN EP interrupts */
CLEAR_IN_EP_INTR(epindex, ep_int_status);
if (ep_int_status & USB_OTG_DIEPINT_XFRC) {
usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(epindex | 0x80));
}
}
epindex++;
ep_intr >>= 1U;
}
}
if (int_status & USB_OTG_GINTSTS_OEPINT) {
epindex = 0;
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllOutEpInterrupt(USBx);
while (ep_intr != 0U) {
if ((ep_intr & 0x1U) != 0U) {
/* Read OUT EP interrupt status */
ep_int_status = USB_ReadDevOutEPInterrupt(USBx, (uint8_t)epindex);
/* Clear OUT EP interrupts */
CLEAR_OUT_EP_INTR(epindex, ep_int_status);
}
epindex++;
ep_intr >>= 1U;
}
}
if (int_status & USB_OTG_GINTSTS_MMIS) {
USBx->GINTSTS &= USB_OTG_GINTSTS_MMIS;
}
if (int_status & USB_OTG_GINTSTS_WKUINT) {
USBx->GINTSTS &= USB_OTG_GINTSTS_WKUINT;
}
if (int_status & USB_OTG_GINTSTS_USBSUSP) {
USBx->GINTSTS &= USB_OTG_GINTSTS_USBSUSP;
}
// if (int_status & USB_OTG_GINTSTS_LPMINT) {
// USBx->GINTSTS &= USB_OTG_GINTSTS_LPMINT;
// }
if (int_status & USB_OTG_GINTSTS_SOF) {
USBx->GINTSTS &= USB_OTG_GINTSTS_SOF;
}
if (int_status & USB_OTG_GINTSTS_SRQINT) {
USBx->GINTSTS &= USB_OTG_GINTSTS_SRQINT;
}
if (int_status & USB_OTG_GINTSTS_OTGINT) {
USBx->GINTSTS &= USB_OTG_GINTSTS_OTGINT;
}
}
}
#endif
}

29
port/stm32/usbd_config.h
View File

@@ -1,29 +0,0 @@
#ifndef __USBD_CONFIG_H__
#define __USBD_CONFIG_H__
#if defined(STM32F0)
#include "stm32f0xx.h"
#elif defined(STM32F1)
#include "stm32f1xx.h"
#elif STM32F3
#include "stm32f3xx.h"
#elif defined(STM32F4)
#include "stm32f4xx.h"
#elif defined(STM32H7)
#include "stm32h7xx.h"
#endif
/*other do not process，users need to modify byself*/
#if defined(STM32F0)
#define USBD_IRQHandler USB_IRQHandler
#elif defined(STM32F1) || defined(STM32F3)
#define USBD_IRQHandler USB_LP_CAN1_RX0_IRQHandler
#else
#ifdef CONFIG_USB_HS
#define USBD_IRQHandler OTG_HS_IRQHandler
#else
#define USBD_IRQHandler OTG_FS_IRQHandler
#endif
#endif
#endif