From 90de3354b5f67550135bebbedb7f566ada429d29 Mon Sep 17 00:00:00 2001 From: sakumisu <1203593632@qq.com> Date: Mon, 28 Jul 2025 20:20:16 +0800 Subject: [PATCH] update(port/musb): If ep control register group exists, do not use epidx register Signed-off-by: sakumisu <1203593632@qq.com> --- port/musb/usb_dc_musb.c | 187 +++++++++++++++++++++++++++------------- port/musb/usb_hc_musb.c | 140 ++++++++++++++++++------------ 2 files changed, 213 insertions(+), 114 deletions(-) diff --git a/port/musb/usb_dc_musb.c b/port/musb/usb_dc_musb.c index 000ef778..a6485143 100644 --- a/port/musb/usb_dc_musb.c +++ b/port/musb/usb_dc_musb.c @@ -26,13 +26,17 @@ #define MUSB_IE_OFFSET 0x50 #define MUSB_EPIDX_OFFSET 0x42 -#define MUSB_IND_TXMAP_OFFSET 0x80 -#define MUSB_IND_TXCSRL_OFFSET 0x82 -#define MUSB_IND_TXCSRH_OFFSET 0x83 -#define MUSB_IND_RXMAP_OFFSET 0x84 -#define MUSB_IND_RXCSRL_OFFSET 0x86 -#define MUSB_IND_RXCSRH_OFFSET 0x87 -#define MUSB_IND_RXCOUNT_OFFSET 0x88 +#define MUSB_IND_TXMAP_OFFSET 0x80 +#define MUSB_IND_TXCSRL_OFFSET 0x82 +#define MUSB_IND_TXCSRH_OFFSET 0x83 +#define MUSB_IND_RXMAP_OFFSET 0x84 +#define MUSB_IND_RXCSRL_OFFSET 0x86 +#define MUSB_IND_RXCSRH_OFFSET 0x87 +#define MUSB_IND_RXCOUNT_OFFSET 0x88 +#define MUSB_IND_TXTYPE_OFFSET 0x8C +#define MUSB_IND_TXINTERVAL_OFFSET 0x8D +#define MUSB_IND_RXTYPE_OFFSET 0x8E +#define MUSB_IND_RXINTERVAL_OFFSET 0x8F #define MUSB_FIFO_OFFSET 0x00 @@ -43,6 +47,35 @@ #define MUSB_TXFIFOADD_OFFSET 0x92 #define MUSB_RXFIFOADD_OFFSET 0x96 +#define MUSB_TXFUNCADDR0_OFFSET 0x98 +#define MUSB_TXHUBADDR0_OFFSET 0x9A +#define MUSB_TXHUBPORT0_OFFSET 0x9B +#define MUSB_TXFUNCADDRx_OFFSET 0x98 +#define MUSB_TXHUBADDRx_OFFSET 0x9A +#define MUSB_TXHUBPORTx_OFFSET 0x9B +#define MUSB_RXFUNCADDRx_OFFSET 0x9C +#define MUSB_RXHUBADDRx_OFFSET 0x9E +#define MUSB_RXHUBPORTx_OFFSET 0x9F + +#define USB_TXMAP_BASE(ep_idx) (USB_BASE + MUSB_IND_TXMAP_OFFSET) +#define USB_TXCSRL_BASE(ep_idx) (USB_BASE + MUSB_IND_TXCSRL_OFFSET) +#define USB_TXCSRH_BASE(ep_idx) (USB_BASE + MUSB_IND_TXCSRH_OFFSET) +#define USB_RXMAP_BASE(ep_idx) (USB_BASE + MUSB_IND_RXMAP_OFFSET) +#define USB_RXCSRL_BASE(ep_idx) (USB_BASE + MUSB_IND_RXCSRL_OFFSET) +#define USB_RXCSRH_BASE(ep_idx) (USB_BASE + MUSB_IND_RXCSRH_OFFSET) +#define USB_RXCOUNT_BASE(ep_idx) (USB_BASE + MUSB_IND_RXCOUNT_OFFSET) +#define USB_TXTYPE_BASE(ep_idx) (USB_BASE + MUSB_IND_TXTYPE_OFFSET) +#define USB_TXINTERVAL_BASE(ep_idx) (USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) +#define USB_RXTYPE_BASE(ep_idx) (USB_BASE + MUSB_IND_RXTYPE_OFFSET) +#define USB_RXINTERVAL_BASE(ep_idx) (USB_BASE + MUSB_IND_RXINTERVAL_OFFSET) + +#define USB_TXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDRx_OFFSET) +#define USB_TXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXHUBADDRx_OFFSET) +#define USB_TXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXHUBPORTx_OFFSET) +#define USB_RXADDR_BASE(ep_idx) (USB_BASE + MUSB_RXFUNCADDRx_OFFSET) +#define USB_RXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_RXHUBADDRx_OFFSET) +#define USB_RXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_RXHUBPORTx_OFFSET) + #elif defined(CONFIG_USB_MUSB_CUSTOM) #include "musb_custom.h" #else @@ -57,13 +90,17 @@ #define MUSB_EPIDX_OFFSET 0x0E -#define MUSB_IND_TXMAP_OFFSET 0x10 -#define MUSB_IND_TXCSRL_OFFSET 0x12 -#define MUSB_IND_TXCSRH_OFFSET 0x13 -#define MUSB_IND_RXMAP_OFFSET 0x14 -#define MUSB_IND_RXCSRL_OFFSET 0x16 -#define MUSB_IND_RXCSRH_OFFSET 0x17 -#define MUSB_IND_RXCOUNT_OFFSET 0x18 +#define MUSB_IND_TXMAP_OFFSET 0x10 +#define MUSB_IND_TXCSRL_OFFSET 0x12 +#define MUSB_IND_TXCSRH_OFFSET 0x13 +#define MUSB_IND_RXMAP_OFFSET 0x14 +#define MUSB_IND_RXCSRL_OFFSET 0x16 +#define MUSB_IND_RXCSRH_OFFSET 0x17 +#define MUSB_IND_RXCOUNT_OFFSET 0x18 +#define MUSB_IND_TXTYPE_OFFSET 0x1A +#define MUSB_IND_TXINTERVAL_OFFSET 0x1B +#define MUSB_IND_RXTYPE_OFFSET 0x1C +#define MUSB_IND_RXINTERVAL_OFFSET 0x1D #define MUSB_FIFO_OFFSET 0x20 @@ -74,7 +111,38 @@ #define MUSB_TXFIFOADD_OFFSET 0x64 #define MUSB_RXFIFOADD_OFFSET 0x66 -#endif // CONFIG_USB_MUSB_SUNXI +#define MUSB_TXFUNCADDR0_OFFSET 0x80 +#define MUSB_TXHUBADDR0_OFFSET 0x82 +#define MUSB_TXHUBPORT0_OFFSET 0x83 +#define MUSB_TXFUNCADDRx_OFFSET 0x88 +#define MUSB_TXHUBADDRx_OFFSET 0x8A +#define MUSB_TXHUBPORTx_OFFSET 0x8B +#define MUSB_RXFUNCADDRx_OFFSET 0x8C +#define MUSB_RXHUBADDRx_OFFSET 0x8E +#define MUSB_RXHUBPORTx_OFFSET 0x8F + +#define MUSB_TXMAP0_OFFSET 0x100 + +// do not use EPIDX +#define USB_TXMAP_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx) +#define USB_TXCSRL_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 2) +#define USB_TXCSRH_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 3) +#define USB_RXMAP_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 4) +#define USB_RXCSRL_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 6) +#define USB_RXCSRH_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 7) +#define USB_RXCOUNT_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 8) +#define USB_TXTYPE_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 0x0A) +#define USB_TXINTERVAL_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 0x0B) +#define USB_RXTYPE_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 0x0C) +#define USB_RXINTERVAL_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 0x0D) + +#define USB_TXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx) +#define USB_TXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 2) +#define USB_TXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 3) +#define USB_RXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 4) +#define USB_RXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 6) +#define USB_RXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 7) +#endif #define USB_FIFO_BASE(ep_idx) (USB_BASE + MUSB_FIFO_OFFSET + 0x4 * ep_idx) @@ -357,7 +425,7 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) "Ep %02x fifo is overflow", ep->bEndpointAddress); #endif - HWREGH(USB_BASE + MUSB_IND_RXMAP_OFFSET) = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + HWREGH(USB_RXMAP_BASE(ep_idx)) = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); // // Allow auto clearing of RxPktRdy when packet of size max packet @@ -389,15 +457,15 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) ui32Register |= USB_RXCSRH1_ISO; } - HWREGB(USB_BASE + MUSB_IND_RXCSRH_OFFSET) = ui32Register; + HWREGB(USB_RXCSRH_BASE(ep_idx)) = ui32Register; // Reset the Data toggle to zero. - if (HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_RXRDY) - HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = (USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH); + if (HWREGB(USB_RXCSRL_BASE(ep_idx)) & USB_RXCSRL1_RXRDY) + HWREGB(USB_RXCSRL_BASE(ep_idx)) = (USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH); else - HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = USB_RXCSRL1_CLRDT; + HWREGB(USB_RXCSRL_BASE(ep_idx)) = USB_RXCSRL1_CLRDT; - HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) &= ~USB_TXCSRH1_MODE; + HWREGB(USB_TXCSRH_BASE(ep_idx)) &= ~USB_TXCSRH1_MODE; } else { g_musb_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); g_musb_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); @@ -408,7 +476,7 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) "Ep %02x fifo is overflow", ep->bEndpointAddress); #endif - HWREGH(USB_BASE + MUSB_IND_TXMAP_OFFSET) = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + HWREGH(USB_TXMAP_BASE(ep_idx)) = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); // // Allow auto setting of TxPktRdy when max packet size has been loaded @@ -434,13 +502,13 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) ui32Register |= USB_TXCSRH1_ISO; } - HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) = ui32Register | USB_TXCSRH1_MODE; + HWREGB(USB_TXCSRH_BASE(ep_idx)) = ui32Register | USB_TXCSRH1_MODE; // Reset the Data toggle to zero. - if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_TXRDY) - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH); + if (HWREGB(USB_TXCSRL_BASE(ep_idx)) & USB_TXCSRL1_TXRDY) + HWREGB(USB_TXCSRL_BASE(ep_idx)) = (USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH); else - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_CLRDT; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_TXCSRL1_CLRDT; } musb_set_active_ep(old_ep_idx); @@ -464,16 +532,16 @@ int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) if (USB_EP_DIR_IS_OUT(ep)) { if (ep_idx == 0x00) { usb_ep0_state = USB_EP0_STATE_STALL; - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC); + HWREGB(USB_TXCSRL_BASE(ep_idx)) |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC); } else { - HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) |= USB_RXCSRL1_STALL; + HWREGB(USB_RXCSRL_BASE(ep_idx)) |= USB_RXCSRL1_STALL; } } else { if (ep_idx == 0x00) { usb_ep0_state = USB_EP0_STATE_STALL; - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC); + HWREGB(USB_TXCSRL_BASE(ep_idx)) |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC); } else { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= USB_TXCSRL1_STALL; + HWREGB(USB_TXCSRL_BASE(ep_idx)) |= USB_TXCSRL1_STALL; } } @@ -491,21 +559,21 @@ int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) if (USB_EP_DIR_IS_OUT(ep)) { if (ep_idx == 0x00) { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_STALLED; + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_CSRL0_STALLED; } else { // Clear the stall on an OUT endpoint. - HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + HWREGB(USB_RXCSRL_BASE(ep_idx)) &= ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); // Reset the data toggle. - HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) |= USB_RXCSRL1_CLRDT; + HWREGB(USB_RXCSRL_BASE(ep_idx)) |= USB_RXCSRL1_CLRDT; } } else { if (ep_idx == 0x00) { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_STALLED; + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_CSRL0_STALLED; } else { // Clear the stall on an IN endpoint. - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); // Reset the data toggle. - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= USB_TXCSRL1_CLRDT; + HWREGB(USB_TXCSRL_BASE(ep_idx)) |= USB_TXCSRL1_CLRDT; } } @@ -522,13 +590,13 @@ int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) musb_set_active_ep(ep_idx); if (USB_EP_DIR_IS_OUT(ep)) { - if (HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_STALL) { + if (HWREGB(USB_RXCSRL_BASE(ep_idx)) & USB_RXCSRL1_STALL) { *stalled = 1; } else { *stalled = 0; } } else { - if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_STALL) { + if (HWREGB(USB_TXCSRL_BASE(ep_idx)) & USB_TXCSRL1_STALL) { *stalled = 1; } else { *stalled = 0; @@ -553,7 +621,7 @@ int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, ui old_ep_idx = musb_get_active_ep(); musb_set_active_ep(ep_idx); - if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_TXRDY) { + if (HWREGB(USB_TXCSRL_BASE(ep_idx)) & USB_TXCSRL1_TXRDY) { musb_set_active_ep(old_ep_idx); return -3; } @@ -569,9 +637,9 @@ int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, ui } else { usb_ep0_state = USB_EP0_STATE_IN_ZLP; } - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_TXRDY | USB_CSRL0_DATAEND); + HWREGB(USB_TXCSRL_BASE(ep_idx)) = (USB_CSRL0_TXRDY | USB_CSRL0_DATAEND); } else { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_TXCSRL1_TXRDY; HWREGH(USB_BASE + MUSB_TXIE_OFFSET) |= (1 << ep_idx); } musb_set_active_ep(old_ep_idx); @@ -585,12 +653,12 @@ int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, ui if (ep_idx == 0x00) { usb_ep0_state = USB_EP0_STATE_IN_DATA; if (data_len < g_musb_udc.in_ep[ep_idx].ep_mps) { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_TXRDY | USB_CSRL0_DATAEND); + HWREGB(USB_TXCSRL_BASE(ep_idx)) = (USB_CSRL0_TXRDY | USB_CSRL0_DATAEND); } else { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_TXRDY; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_CSRL0_TXRDY; } } else { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_TXCSRL1_TXRDY; } musb_set_active_ep(old_ep_idx); @@ -634,17 +702,18 @@ int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t static void handle_ep0(void) { - uint8_t ep0_status = HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET); + uint8_t ep_idx = 0; // EP0 index is always 0 + uint8_t ep0_status = HWREGB(USB_TXCSRL_BASE(ep_idx)); uint16_t read_count; if (ep0_status & USB_CSRL0_STALLED) { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_STALLED; + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_CSRL0_STALLED; usb_ep0_state = USB_EP0_STATE_SETUP; return; } if (ep0_status & USB_CSRL0_SETEND) { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_SETENDC; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_CSRL0_SETENDC; } if (g_musb_udc.dev_addr > 0) { @@ -655,7 +724,7 @@ static void handle_ep0(void) switch (usb_ep0_state) { case USB_EP0_STATE_SETUP: if (ep0_status & USB_CSRL0_RXRDY) { - read_count = HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET); + read_count = HWREGH(USB_RXCOUNT_BASE(ep_idx)); if (read_count != 8) { return; @@ -663,9 +732,9 @@ static void handle_ep0(void) musb_read_packet(0, (uint8_t *)&g_musb_udc.setup, 8); if (g_musb_udc.setup.wLength) { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_RXRDYC; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_CSRL0_RXRDYC; } else { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND); + HWREGB(USB_TXCSRL_BASE(ep_idx)) = (USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND); } usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_musb_udc.setup); @@ -686,7 +755,7 @@ static void handle_ep0(void) break; case USB_EP0_STATE_OUT_DATA: if (ep0_status & USB_CSRL0_RXRDY) { - read_count = HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET); + read_count = HWREGH(USB_RXCOUNT_BASE(ep_idx)); musb_read_packet(0, g_musb_udc.out_ep[0].xfer_buf, read_count); g_musb_udc.out_ep[0].xfer_buf += read_count; @@ -694,10 +763,10 @@ static void handle_ep0(void) if (read_count < g_musb_udc.out_ep[0].ep_mps) { usbd_event_ep_out_complete_handler(0, 0x00, g_musb_udc.out_ep[0].actual_xfer_len); - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND); + HWREGB(USB_TXCSRL_BASE(ep_idx)) = (USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND); usb_ep0_state = USB_EP0_STATE_IN_STATUS; } else { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_RXRDYC; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_CSRL0_RXRDYC; } } break; @@ -764,8 +833,8 @@ void USBD_IRQHandler(uint8_t busid) if (txis & (1 << ep_idx)) { musb_set_active_ep(ep_idx); HWREGH(USB_BASE + MUSB_TXIS_OFFSET) = (1 << ep_idx); - if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_UNDRN) { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_TXCSRL1_UNDRN; + if (HWREGB(USB_TXCSRL_BASE(ep_idx)) & USB_TXCSRL1_UNDRN) { + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_TXCSRL1_UNDRN; } if (g_musb_udc.in_ep[ep_idx].xfer_len > g_musb_udc.in_ep[ep_idx].ep_mps) { @@ -785,7 +854,7 @@ void USBD_IRQHandler(uint8_t busid) write_count = MIN(g_musb_udc.in_ep[ep_idx].xfer_len, g_musb_udc.in_ep[ep_idx].ep_mps); musb_write_packet(ep_idx, g_musb_udc.in_ep[ep_idx].xfer_buf, write_count); - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_TXCSRL1_TXRDY; } txis &= ~(1 << ep_idx); @@ -799,11 +868,11 @@ void USBD_IRQHandler(uint8_t busid) if (rxis & (1 << ep_idx)) { musb_set_active_ep(ep_idx); HWREGH(USB_BASE + MUSB_RXIS_OFFSET) = (1 << ep_idx); - if (HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_RXRDY) { - read_count = HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET); + if (HWREGB(USB_RXCSRL_BASE(ep_idx)) & USB_RXCSRL1_RXRDY) { + read_count = HWREGH(USB_RXCOUNT_BASE(ep_idx)); musb_read_packet(ep_idx, g_musb_udc.out_ep[ep_idx].xfer_buf, read_count); - HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~(USB_RXCSRL1_RXRDY); + HWREGB(USB_RXCSRL_BASE(ep_idx)) &= ~(USB_RXCSRL1_RXRDY); g_musb_udc.out_ep[ep_idx].xfer_buf += read_count; g_musb_udc.out_ep[ep_idx].actual_xfer_len += read_count; diff --git a/port/musb/usb_hc_musb.c b/port/musb/usb_hc_musb.c index 49da88e9..c2ac9bb9 100644 --- a/port/musb/usb_hc_musb.c +++ b/port/musb/usb_hc_musb.c @@ -16,7 +16,7 @@ #define USB_BASE (bus->hcd.reg_base) -#ifdef CONFIG_USB_MUSB_SUNXI +#if defined(CONFIG_USB_MUSB_SUNXI) #define MUSB_FADDR_OFFSET 0x98 #define MUSB_POWER_OFFSET 0x40 #define MUSB_TXIS_OFFSET 0x44 @@ -58,6 +58,18 @@ #define MUSB_RXHUBADDRx_OFFSET 0x9E #define MUSB_RXHUBPORTx_OFFSET 0x9F +#define USB_TXMAP_BASE(ep_idx) (USB_BASE + MUSB_IND_TXMAP_OFFSET) +#define USB_TXCSRL_BASE(ep_idx) (USB_BASE + MUSB_IND_TXCSRL_OFFSET) +#define USB_TXCSRH_BASE(ep_idx) (USB_BASE + MUSB_IND_TXCSRH_OFFSET) +#define USB_RXMAP_BASE(ep_idx) (USB_BASE + MUSB_IND_RXMAP_OFFSET) +#define USB_RXCSRL_BASE(ep_idx) (USB_BASE + MUSB_IND_RXCSRL_OFFSET) +#define USB_RXCSRH_BASE(ep_idx) (USB_BASE + MUSB_IND_RXCSRH_OFFSET) +#define USB_RXCOUNT_BASE(ep_idx) (USB_BASE + MUSB_IND_RXCOUNT_OFFSET) +#define USB_TXTYPE_BASE(ep_idx) (USB_BASE + MUSB_IND_TXTYPE_OFFSET) +#define USB_TXINTERVAL_BASE(ep_idx) (USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) +#define USB_RXTYPE_BASE(ep_idx) (USB_BASE + MUSB_IND_RXTYPE_OFFSET) +#define USB_RXINTERVAL_BASE(ep_idx) (USB_BASE + MUSB_IND_RXINTERVAL_OFFSET) + #define USB_TXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDRx_OFFSET) #define USB_TXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXHUBADDRx_OFFSET) #define USB_TXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXHUBPORTx_OFFSET) @@ -110,6 +122,21 @@ #define MUSB_RXHUBADDRx_OFFSET 0x8E #define MUSB_RXHUBPORTx_OFFSET 0x8F +#define MUSB_TXMAP0_OFFSET 0x100 + +// do not use EPIDX +#define USB_TXMAP_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx) +#define USB_TXCSRL_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 2) +#define USB_TXCSRH_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 3) +#define USB_RXMAP_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 4) +#define USB_RXCSRL_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 6) +#define USB_RXCSRH_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 7) +#define USB_RXCOUNT_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 8) +#define USB_TXTYPE_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 0x0A) +#define USB_TXINTERVAL_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 0x0B) +#define USB_RXTYPE_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 0x0C) +#define USB_RXINTERVAL_BASE(ep_idx) (USB_BASE + MUSB_TXMAP0_OFFSET + 0x10 * ep_idx + 0x0D) + #define USB_TXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx) #define USB_TXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 2) #define USB_TXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 3) @@ -160,15 +187,15 @@ static void musb_fifo_flush(struct usbh_bus *bus, uint8_t ep) { uint8_t ep_idx = ep & 0x7f; if (ep_idx == 0) { - if ((HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0) - HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) |= USB_CSRH0_FLUSH; + if ((HWREGB(USB_TXCSRL_BASE(ep_idx)) & (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0) + HWREGB(USB_RXCSRL_BASE(ep_idx)) |= USB_CSRH0_FLUSH; } else { if (ep & 0x80) { - if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_TXRDY) - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= USB_TXCSRL1_FLUSH; + if (HWREGB(USB_TXCSRL_BASE(ep_idx)) & USB_TXCSRL1_TXRDY) + HWREGB(USB_TXCSRL_BASE(ep_idx)) |= USB_TXCSRL1_FLUSH; } else { - if (HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_RXRDY) - HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) |= USB_RXCSRL1_FLUSH; + if (HWREGB(USB_RXCSRL_BASE(ep_idx)) & USB_RXCSRL1_RXRDY) + HWREGB(USB_RXCSRL_BASE(ep_idx)) |= USB_RXCSRL1_FLUSH; } } } @@ -302,12 +329,12 @@ void musb_control_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb } HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; - HWREGB(USB_BASE + MUSB_IND_TXTYPE_OFFSET) = speed; + HWREGB(USB_TXTYPE_BASE(chidx)) = speed; HWREGB(USB_TXHUBADDR_BASE(chidx)) = 0; HWREGB(USB_TXHUBPORT_BASE(chidx)) = 0; musb_write_packet(bus, chidx, (uint8_t *)setup, 8); - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_TXRDY | USB_CSRL0_SETUP; + HWREGB(USB_TXCSRL_BASE(chidx)) = USB_CSRL0_TXRDY | USB_CSRL0_SETUP; musb_set_active_ep(bus, old_ep_index); } @@ -334,12 +361,12 @@ int musb_bulk_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb } HWREGB(USB_RXADDR_BASE(chidx)) = urb->hport->dev_addr; - HWREGB(USB_BASE + MUSB_IND_RXTYPE_OFFSET) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; - HWREGB(USB_BASE + MUSB_IND_RXINTERVAL_OFFSET) = 0; + HWREGB(USB_RXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; + HWREGB(USB_RXINTERVAL_BASE(chidx)) = 0; HWREGB(USB_RXHUBADDR_BASE(chidx)) = 0; HWREGB(USB_RXHUBPORT_BASE(chidx)) = 0; - HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) &= ~USB_TXCSRH1_MODE; - HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = USB_RXCSRL1_REQPKT; + HWREGB(USB_TXCSRH_BASE(chidx)) &= ~USB_TXCSRH1_MODE; + HWREGB(USB_RXCSRL_BASE(chidx)) = USB_RXCSRL1_REQPKT; HWREGH(USB_BASE + MUSB_RXIE_OFFSET) |= (1 << chidx); } else { @@ -349,8 +376,8 @@ int musb_bulk_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb } HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; - HWREGB(USB_BASE + MUSB_IND_TXTYPE_OFFSET) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; - HWREGB(USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) = 0; + HWREGB(USB_TXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; + HWREGB(USB_TXINTERVAL_BASE(chidx)) = 0; HWREGB(USB_TXHUBADDR_BASE(chidx)) = 0; HWREGB(USB_TXHUBPORT_BASE(chidx)) = 0; @@ -359,8 +386,8 @@ int musb_bulk_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb } musb_write_packet(bus, chidx, buffer, buflen); - HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) |= USB_TXCSRH1_MODE; - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY; + HWREGB(USB_TXCSRH_BASE(chidx)) |= USB_TXCSRH1_MODE; + HWREGB(USB_TXCSRL_BASE(chidx)) = USB_TXCSRL1_TXRDY; HWREGH(USB_BASE + MUSB_TXIE_OFFSET) |= (1 << chidx); } @@ -391,12 +418,12 @@ int musb_intr_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb } HWREGB(USB_RXADDR_BASE(chidx)) = urb->hport->dev_addr; - HWREGB(USB_BASE + MUSB_IND_RXTYPE_OFFSET) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; - HWREGB(USB_BASE + MUSB_IND_RXINTERVAL_OFFSET) = urb->ep->bInterval; + HWREGB(USB_RXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; + HWREGB(USB_RXINTERVAL_BASE(chidx)) = urb->ep->bInterval; HWREGB(USB_RXHUBADDR_BASE(chidx)) = 0; HWREGB(USB_RXHUBPORT_BASE(chidx)) = 0; - HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) &= ~USB_TXCSRH1_MODE; - HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = USB_RXCSRL1_REQPKT; + HWREGB(USB_TXCSRH_BASE(chidx)) &= ~USB_TXCSRH1_MODE; + HWREGB(USB_RXCSRL_BASE(chidx)) = USB_RXCSRL1_REQPKT; HWREGH(USB_BASE + MUSB_RXIE_OFFSET) |= (1 << chidx); } else { @@ -406,8 +433,8 @@ int musb_intr_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb } HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; - HWREGB(USB_BASE + MUSB_IND_TXTYPE_OFFSET) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; - HWREGB(USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) = urb->ep->bInterval; + HWREGB(USB_TXTYPE_BASE(chidx)) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; + HWREGB(USB_TXINTERVAL_BASE(chidx)) = urb->ep->bInterval; HWREGB(USB_TXHUBADDR_BASE(chidx)) = 0; HWREGB(USB_TXHUBPORT_BASE(chidx)) = 0; @@ -416,8 +443,8 @@ int musb_intr_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb } musb_write_packet(bus, chidx, buffer, buflen); - HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) |= USB_TXCSRH1_MODE; - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY; + HWREGB(USB_TXCSRH_BASE(chidx)) |= USB_TXCSRH1_MODE; + HWREGB(USB_TXCSRL_BASE(chidx)) = USB_TXCSRL1_TXRDY; HWREGH(USB_BASE + MUSB_TXIE_OFFSET) |= (1 << chidx); } @@ -505,14 +532,14 @@ int usb_hc_init(struct usbh_bus *bus) uint8_t cfg_num; struct musb_fifo_cfg *cfg; + usb_hc_low_level_init(bus); + memset(&g_musb_hcd[bus->hcd.hcd_id], 0, sizeof(struct musb_hcd)); for (uint8_t i = 0; i < CONFIG_USB_MUSB_PIPE_NUM; i++) { g_musb_hcd[bus->hcd.hcd_id].pipe_pool[i].waitsem = usb_osal_sem_create(0); } - usb_hc_low_level_init(bus); - cfg_num = usbh_get_musb_fifo_cfg(&cfg); for (uint8_t i = 0; i < cfg_num; i++) { @@ -536,7 +563,7 @@ int usb_hc_init(struct usbh_bus *bus) #ifdef CONFIG_USB_MUSB_SUNXI musb_set_active_ep(bus, 0); - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_TXRDY; + HWREGB(USB_TXCSRL_BASE(0)) = USB_CSRL0_TXRDY; #endif return 0; } @@ -804,6 +831,8 @@ static void musb_urb_waitup(struct usbh_urb *urb) struct musb_pipe *pipe; pipe = (struct musb_pipe *)urb->hcpriv; + pipe->urb = NULL; + urb->hcpriv = NULL; if (urb->timeout) { usb_osal_sem_give(pipe->waitsem); @@ -822,6 +851,7 @@ static void musb_urb_waitup(struct usbh_urb *urb) void handle_ep0(struct usbh_bus *bus) { + uint8_t ep_idx = 0; uint8_t ep0_status; struct musb_pipe *pipe; struct usbh_urb *urb; @@ -834,16 +864,16 @@ void handle_ep0(struct usbh_bus *bus) } musb_set_active_ep(bus, 0); - ep0_status = HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET); + ep0_status = HWREGB(USB_TXCSRL_BASE(ep_idx)); if (ep0_status & USB_CSRL0_STALLED) { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_STALLED; + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_CSRL0_STALLED; pipe->ep0_state = USB_EP0_STATE_SETUP; urb->errorcode = -USB_ERR_STALL; musb_urb_waitup(urb); return; } if (ep0_status & USB_CSRL0_ERROR) { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_ERROR; + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_CSRL0_ERROR; musb_fifo_flush(bus, 0); pipe->ep0_state = USB_EP0_STATE_SETUP; urb->errorcode = -USB_ERR_IO; @@ -851,7 +881,7 @@ void handle_ep0(struct usbh_bus *bus) return; } if (ep0_status & USB_CSRL0_STALL) { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_STALL; + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_CSRL0_STALL; pipe->ep0_state = USB_EP0_STATE_SETUP; urb->errorcode = -USB_ERR_STALL; musb_urb_waitup(urb); @@ -864,7 +894,7 @@ void handle_ep0(struct usbh_bus *bus) if (urb->transfer_buffer_length) { if (urb->setup->bmRequestType & 0x80) { pipe->ep0_state = USB_EP0_STATE_IN_DATA; - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_REQPKT; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_CSRL0_REQPKT; } else { pipe->ep0_state = USB_EP0_STATE_OUT_DATA; size = urb->transfer_buffer_length; @@ -873,7 +903,7 @@ void handle_ep0(struct usbh_bus *bus) } musb_write_packet(bus, 0, urb->transfer_buffer, size); - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_TXRDY; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_CSRL0_TXRDY; urb->transfer_buffer += size; urb->transfer_buffer_length -= size; @@ -881,23 +911,23 @@ void handle_ep0(struct usbh_bus *bus) } } else { pipe->ep0_state = USB_EP0_STATE_IN_STATUS; - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_REQPKT | USB_CSRL0_STATUS); + HWREGB(USB_TXCSRL_BASE(ep_idx)) = (USB_CSRL0_REQPKT | USB_CSRL0_STATUS); } break; case USB_EP0_STATE_IN_DATA: if (ep0_status & USB_CSRL0_RXRDY) { - size = HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET); + size = HWREGH(USB_RXCOUNT_BASE(ep_idx)); musb_read_packet(bus, 0, urb->transfer_buffer, size); - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_RXRDY; + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_CSRL0_RXRDY; urb->transfer_buffer += size; urb->transfer_buffer_length -= size; urb->actual_length += size; if ((size < USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) || (urb->transfer_buffer_length == 0)) { pipe->ep0_state = USB_EP0_STATE_OUT_STATUS; - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_TXRDY | USB_CSRL0_STATUS); + HWREGB(USB_TXCSRL_BASE(ep_idx)) = (USB_CSRL0_TXRDY | USB_CSRL0_STATUS); } else { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_REQPKT; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_CSRL0_REQPKT; } } break; @@ -909,14 +939,14 @@ void handle_ep0(struct usbh_bus *bus) } musb_write_packet(bus, 0, urb->transfer_buffer, size); - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_TXRDY; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_CSRL0_TXRDY; urb->transfer_buffer += size; urb->transfer_buffer_length -= size; urb->actual_length += size; } else { pipe->ep0_state = USB_EP0_STATE_IN_STATUS; - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_REQPKT | USB_CSRL0_STATUS); + HWREGB(USB_TXCSRL_BASE(ep_idx)) = (USB_CSRL0_REQPKT | USB_CSRL0_STATUS); } break; case USB_EP0_STATE_OUT_STATUS: @@ -925,7 +955,7 @@ void handle_ep0(struct usbh_bus *bus) break; case USB_EP0_STATE_IN_STATUS: if (ep0_status & (USB_CSRL0_RXRDY | USB_CSRL0_STATUS)) { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~(USB_CSRL0_RXRDY | USB_CSRL0_STATUS); + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~(USB_CSRL0_RXRDY | USB_CSRL0_STATUS); urb->errorcode = 0; musb_urb_waitup(urb); } @@ -1007,18 +1037,18 @@ void USBH_IRQHandler(uint8_t busid) urb = pipe->urb; musb_set_active_ep(bus, ep_idx); - ep_csrl_status = HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET); + ep_csrl_status = HWREGB(USB_TXCSRL_BASE(ep_idx)); if (ep_csrl_status & USB_TXCSRL1_ERROR) { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_TXCSRL1_ERROR; + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_TXCSRL1_ERROR; urb->errorcode = -USB_ERR_IO; musb_urb_waitup(urb); } else if (ep_csrl_status & USB_TXCSRL1_NAKTO) { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_TXCSRL1_NAKTO; + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_TXCSRL1_NAKTO; urb->errorcode = -USB_ERR_NAK; musb_urb_waitup(urb); } else if (ep_csrl_status & USB_TXCSRL1_STALL) { - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_TXCSRL1_STALL; + HWREGB(USB_TXCSRL_BASE(ep_idx)) &= ~USB_TXCSRL1_STALL; urb->errorcode = -USB_ERR_STALL; musb_urb_waitup(urb); } else { @@ -1038,7 +1068,7 @@ void USBH_IRQHandler(uint8_t busid) musb_urb_waitup(urb); } else { musb_write_packet(bus, ep_idx, urb->transfer_buffer, MIN(urb->transfer_buffer_length, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize))); - HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY; + HWREGB(USB_TXCSRL_BASE(ep_idx)) = USB_TXCSRL1_TXRDY; } } } @@ -1053,27 +1083,27 @@ void USBH_IRQHandler(uint8_t busid) urb = pipe->urb; musb_set_active_ep(bus, ep_idx); - ep_csrl_status = HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET); - //ep_csrh_status = HWREGB(USB_BASE + MUSB_IND_RXCSRH_OFFSET); // todo:for iso transfer + ep_csrl_status = HWREGB(USB_RXCSRL_BASE(ep_idx)); + //ep_csrh_status = HWREGB(USB_BASE + USB_RXCSRH_BASE(ep_idx)); // todo:for iso transfer if (ep_csrl_status & USB_RXCSRL1_ERROR) { - HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~USB_RXCSRL1_ERROR; + HWREGB(USB_RXCSRL_BASE(ep_idx)) &= ~USB_RXCSRL1_ERROR; urb->errorcode = -USB_ERR_IO; musb_urb_waitup(urb); } else if (ep_csrl_status & USB_RXCSRL1_NAKTO) { - HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~USB_RXCSRL1_NAKTO; + HWREGB(USB_RXCSRL_BASE(ep_idx)) &= ~USB_RXCSRL1_NAKTO; urb->errorcode = -USB_ERR_NAK; musb_urb_waitup(urb); } else if (ep_csrl_status & USB_RXCSRL1_STALL) { - HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~USB_RXCSRL1_STALL; + HWREGB(USB_RXCSRL_BASE(ep_idx)) &= ~USB_RXCSRL1_STALL; urb->errorcode = -USB_ERR_STALL; musb_urb_waitup(urb); } else if (ep_csrl_status & USB_RXCSRL1_RXRDY) { - size = HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET); + size = HWREGH(USB_RXCOUNT_BASE(ep_idx)); musb_read_packet(bus, ep_idx, urb->transfer_buffer, size); - HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~USB_RXCSRL1_RXRDY; + HWREGB(USB_RXCSRL_BASE(ep_idx)) &= ~USB_RXCSRL1_RXRDY; urb->transfer_buffer += size; urb->transfer_buffer_length -= size; @@ -1084,7 +1114,7 @@ void USBH_IRQHandler(uint8_t busid) urb->errorcode = 0; musb_urb_waitup(urb); } else { - HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = USB_RXCSRL1_REQPKT; + HWREGB(USB_RXCSRL_BASE(ep_idx)) = USB_RXCSRL1_REQPKT; } } }