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update(port): remove all ips CONFIG_USBDEV_EP_NUM & CONFIG_USBHOST_PIPE_NUM

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Signed-off-by: sakumisu <1203593632@qq.com>
This commit is contained in:
sakumisu
2025-07-28 19:06:37 +08:00
parent 3b04facd09
commit 81d8f22e05
9 changed files with 43 additions and 50 deletions
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29
cherryusb_config_template.h
View File

@@ -253,20 +253,8 @@
#define CONFIG_USBDEV_MAX_BUS 1
#endif
/* only useful for musb/ch32/chipidea */
#ifndef CONFIG_USBDEV_EP_NUM
#define CONFIG_USBDEV_EP_NUM 8
#endif
// #define CONFIG_USBDEV_SOF_ENABLE
/* When your chip hardware supports high-speed and wants to initialize it in high-speed mode,
* the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS.
*
* in xxx32 chips, only pb14/pb15 can support hs mode, pa11/pa12 is not supported(only a few supports, but we ignore them).
*/
// #define CONFIG_USB_HS
/* ---------------- FSDEV Configuration ---------------- */
//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference
@@ -277,6 +265,7 @@
// #define CONFIG_USB_DWC2_DMA_ENABLE
/* ---------------- MUSB Configuration ---------------- */
#define CONFIG_USB_MUSB_EP_NUM 8
// #define CONFIG_USB_MUSB_SUNXI
/* ================ USB Host Port Configuration ==================*/
@@ -284,11 +273,6 @@
#define CONFIG_USBHOST_MAX_BUS 1
#endif
/* only useful for musb */
#ifndef CONFIG_USBHOST_PIPE_NUM
#define CONFIG_USBHOST_PIPE_NUM 10
#endif
/* ---------------- EHCI Configuration ---------------- */
#define CONFIG_USB_EHCI_HCCR_OFFSET (0x0)
@@ -311,9 +295,20 @@
/* ---------------- XHCI Configuration ---------------- */
#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0)
/* ---------------- DWC2 Configuration ---------------- */
// nothing to define
/* ---------------- MUSB Configuration ---------------- */
#define CONFIG_USB_MUSB_PIPE_NUM 8
// #define CONFIG_USB_MUSB_SUNXI
/* When your chip hardware supports high-speed and wants to initialize it in high-speed mode,
* the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS.
*
* in xxx32 chips, only pb14/pb15 can support hs mode, pa11/pa12 is not supported(only a few supports, but we ignore them).
*/
// #define CONFIG_USB_HS
#ifndef usb_phyaddr2ramaddr
#define usb_phyaddr2ramaddr(addr) (addr)
#endif

4
port/chipidea/usb_dc_chipidea.c
View File

@@ -17,6 +17,10 @@
#define CHIPIDEA_BITSMASK(val, offset) ((uint32_t)(val) << (offset))
#define QTD_COUNT_EACH_ENDPOINT (8U)
#ifndef CONFIG_USBDEV_EP_NUM
#define CONFIG_USBDEV_EP_NUM 8
#endif
/* ENDPTCTRL */
enum {
ENDPTCTRL_STALL = CHIPIDEA_BITSMASK(1, 0),

6
port/musb/usb_dc_musb.c
View File

@@ -103,8 +103,8 @@ struct musb_ep_state {
struct musb_udc {
volatile uint8_t dev_addr;
__attribute__((aligned(32))) struct usb_setup_packet setup;
struct musb_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/
struct musb_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */
struct musb_ep_state in_ep[CONFIG_USB_MUSB_EP_NUM]; /*!< IN endpoint parameters*/
struct musb_ep_state out_ep[CONFIG_USB_MUSB_EP_NUM]; /*!< OUT endpoint parameters */
} g_musb_udc;
static volatile uint8_t usb_ep0_state = USB_EP0_STATE_SETUP;
@@ -342,7 +342,7 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep)
return 0;
}
USB_ASSERT_MSG(ep_idx < CONFIG_USBDEV_EP_NUM, "Ep addr %02x overflow", ep->bEndpointAddress);
USB_ASSERT_MSG(ep_idx < CONFIG_USB_MUSB_EP_NUM, "Ep addr %02x overflow", ep->bEndpointAddress);
old_ep_idx = musb_get_active_ep();
musb_set_active_ep(ep_idx);

4
port/musb/usb_glue_bk.c
View File

@@ -94,11 +94,11 @@
#define NANENG_PHY_FC_REG1E (0x1E * 4)
#define NANENG_PHY_FC_REG1F (0x1F * 4)
#if CONFIG_USBDEV_EP_NUM != 8
#if CONFIG_USB_MUSB_EP_NUM != 8
#error beken chips only support 8 endpoints
#endif
#if CONFIG_USBHOST_PIPE_NUM != 8
#if CONFIG_USB_MUSB_PIPE_NUM != 8
#error beken chips only support 8 pipes
#endif

4
port/musb/usb_glue_es.c
View File

@@ -7,11 +7,11 @@
#include "stdint.h"
#include "usb_musb_reg.h"
#if CONFIG_USBDEV_EP_NUM != 6
#if CONFIG_USB_MUSB_EP_NUM != 6
#error es32 chips only support 6 endpoints
#endif
#if CONFIG_USBHOST_PIPE_NUM != 6
#if CONFIG_USB_MUSB_PIPE_NUM != 6
#error es32 chips only support 6 pipes
#endif

4
port/musb/usb_glue_sunxi.c
View File

@@ -11,11 +11,11 @@
#error must define CONFIG_USB_MUSB_SUNXI when use sunxi chips
#endif
#if CONFIG_USBDEV_EP_NUM != 4
#if CONFIG_USB_MUSB_EP_NUM != 4
#error sunxi chips only support 4 endpoints
#endif
#if CONFIG_USBHOST_PIPE_NUM != 4
#if CONFIG_USB_MUSB_PIPE_NUM != 4
#error sunxi chips only support 4 pipes
#endif

14
port/musb/usb_hc_musb.c
View File

@@ -141,7 +141,7 @@ struct musb_hcd {
volatile bool port_csc;
volatile bool port_pec;
volatile bool port_pe;
struct musb_pipe pipe_pool[CONFIG_USBHOST_PIPE_NUM];
struct musb_pipe pipe_pool[CONFIG_USB_MUSB_PIPE_NUM];
} g_musb_hcd[CONFIG_USBHOST_MAX_BUS];
/* get current active ep */
@@ -464,7 +464,7 @@ static int musb_pipe_alloc(void)
{
int chidx;
for (chidx = 1; chidx < CONFIG_USBHOST_PIPE_NUM; chidx++) {
for (chidx = 1; chidx < CONFIG_USB_MUSB_PIPE_NUM; chidx++) {
if (!g_musb_hcd[bus->hcd.hcd_id].pipe_pool[chidx].inuse) {
g_musb_hcd[bus->hcd.hcd_id].pipe_pool[chidx].inuse = true;
return chidx;
@@ -507,7 +507,7 @@ int usb_hc_init(struct usbh_bus *bus)
memset(&g_musb_hcd[bus->hcd.hcd_id], 0, sizeof(struct musb_hcd));
for (uint8_t i = 0; i < CONFIG_USBHOST_PIPE_NUM; i++) {
for (uint8_t i = 0; i < CONFIG_USB_MUSB_PIPE_NUM; i++) {
g_musb_hcd[bus->hcd.hcd_id].pipe_pool[i].waitsem = usb_osal_sem_create(0);
}
@@ -550,7 +550,7 @@ int usb_hc_deinit(struct usbh_bus *bus)
HWREGB(USB_BASE + MUSB_POWER_OFFSET) &= ~USB_POWER_HSENAB;
HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) &= ~USB_DEVCTL_SESSION;
for (uint8_t i = 0; i < CONFIG_USBHOST_PIPE_NUM; i++) {
for (uint8_t i = 0; i < CONFIG_USB_MUSB_PIPE_NUM; i++) {
usb_osal_sem_delete(g_musb_hcd[bus->hcd.hcd_id].pipe_pool[i].waitsem);
}
@@ -703,7 +703,7 @@ int usbh_submit_urb(struct usbh_urb *urb)
} else {
chidx = (urb->ep->bEndpointAddress & 0x0f);
if (chidx > (CONFIG_USBHOST_PIPE_NUM - 1)) {
if (chidx > (CONFIG_USB_MUSB_PIPE_NUM - 1)) {
return -USB_ERR_RANGE;
}
}
@@ -999,7 +999,7 @@ void USBH_IRQHandler(uint8_t busid)
handle_ep0(bus);
}
for (ep_idx = 1; ep_idx < CONFIG_USBHOST_PIPE_NUM; ep_idx++) {
for (ep_idx = 1; ep_idx < CONFIG_USB_MUSB_PIPE_NUM; ep_idx++) {
if (txis & (1 << ep_idx)) {
HWREGH(USB_BASE + MUSB_TXIS_OFFSET) = (1 << ep_idx);
@@ -1045,7 +1045,7 @@ void USBH_IRQHandler(uint8_t busid)
}
rxis &= HWREGH(USB_BASE + MUSB_RXIE_OFFSET);
for (ep_idx = 1; ep_idx < CONFIG_USBHOST_PIPE_NUM; ep_idx++) {
for (ep_idx = 1; ep_idx < CONFIG_USB_MUSB_PIPE_NUM; ep_idx++) {
if (rxis & (1 << ep_idx)) {
HWREGH(USB_BASE + MUSB_RXIS_OFFSET) = (1 << ep_idx); // clear isr flag

13
port/rp2040/usb_dc_rp2040.c
View File

@@ -12,9 +12,6 @@
#include "pico/fix/rp2040_usb_device_enumeration.h"
#endif
#undef CONFIG_USBDEV_EP_NUM
#define CONFIG_USBDEV_EP_NUM USB_NUM_ENDPOINTS
#define usb_hw_set hw_set_alias(usb_hw)
#define usb_hw_clear hw_clear_alias(usb_hw)
@@ -42,8 +39,8 @@ struct rp2040_ep_state {
/* Driver state */
struct rp2040_udc {
volatile uint8_t dev_addr;
struct rp2040_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/
struct rp2040_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */
struct rp2040_ep_state in_ep[USB_NUM_ENDPOINTS]; /*!< IN endpoint parameters*/
struct rp2040_ep_state out_ep[USB_NUM_ENDPOINTS]; /*!< OUT endpoint parameters */
struct usb_setup_packet setup; /*!< Setup package that may be used in interrupt processing (outside the protocol stack) */
} g_rp2040_udc;
@@ -124,7 +121,7 @@ int usb_dc_init(uint8_t busid)
g_rp2040_udc.out_ep[0].endpoint_control = NULL;
g_rp2040_udc.out_ep[0].data_buffer = &usb_dpram->ep0_buf_a[0];
for (uint32_t i = 0; i < CONFIG_USBDEV_EP_NUM; i++) {
for (uint32_t i = 0; i < USB_NUM_ENDPOINTS; i++) {
g_rp2040_udc.in_ep[i].buffer_control = &usb_dpram->ep_buf_ctrl[i].in;
g_rp2040_udc.out_ep[i].buffer_control = &usb_dpram->ep_buf_ctrl[i].out;
@@ -136,7 +133,7 @@ int usb_dc_init(uint8_t busid)
next_buffer_ptr = &usb_dpram->epx_data[0];
for (uint32_t i = 1; i < CONFIG_USBDEV_EP_NUM; i++) {
for (uint32_t i = 1; i < USB_NUM_ENDPOINTS; i++) {
g_rp2040_udc.in_ep[i].data_buffer = next_buffer_ptr;
if (i == 1) {
next_buffer_ptr += 1024; /* for iso video */
@@ -540,7 +537,7 @@ void USBD_IRQHandler(uint8_t busid)
usb_hw->dev_addr_ctrl = 0;
for (uint8_t i = 0; i < CONFIG_USBDEV_EP_NUM - 1; i++) {
for (uint8_t i = 0; i < USB_NUM_ENDPOINTS - 1; i++) {
/*!< Start at ep1 */
usb_dpram->ep_ctrl[i].in = 0;
usb_dpram->ep_ctrl[i].out = 0;

15
port/rp2040/usb_hc_rp2040.c
View File

@@ -9,9 +9,6 @@
#include "hardware/irq.h"
#include "hardware/structs/usb.h"
#undef CONFIG_USBHOST_PIPE_NUM
#define CONFIG_USBHOST_PIPE_NUM USB_HOST_INTERRUPT_ENDPOINTS
#define usb_hw_set hw_set_alias(usb_hw)
#define usb_hw_clear hw_clear_alias(usb_hw)
@@ -45,7 +42,7 @@ struct rp2040_hcd {
volatile bool port_pec;
volatile bool port_pe;
usb_osal_mutex_t ep0_mutex;
struct rp2040_pipe pipe_pool[1 + CONFIG_USBHOST_PIPE_NUM];
struct rp2040_pipe pipe_pool[1 + USB_HOST_INTERRUPT_ENDPOINTS];
} g_rp2040_hcd[CONFIG_USBHOST_MAX_BUS];
void rp2040_usbh_irq(void);
@@ -56,7 +53,7 @@ static int rp2040_pipe_alloc(struct usbh_bus *bus)
int chidx;
flags = usb_osal_enter_critical_section();
for (chidx = 1; chidx <= CONFIG_USBHOST_PIPE_NUM; chidx++) {
for (chidx = 1; chidx <= USB_HOST_INTERRUPT_ENDPOINTS; chidx++) {
if (!g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[chidx].inuse) {
g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[chidx].inuse = true;
usb_osal_leave_critical_section(flags);
@@ -295,7 +292,7 @@ int usb_hc_init(struct usbh_bus *bus)
memset(&g_rp2040_hcd[bus->hcd.hcd_id], 0, sizeof(struct rp2040_hcd));
for (uint8_t i = 0; i <= CONFIG_USBHOST_PIPE_NUM; i++) {
for (uint8_t i = 0; i <= USB_HOST_INTERRUPT_ENDPOINTS; i++) {
g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[i].waitsem = usb_osal_sem_create(0);
if (g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[i].waitsem == NULL) {
USB_LOG_ERR("Failed to create waitsem\r\n");
@@ -316,7 +313,7 @@ int usb_hc_init(struct usbh_bus *bus)
next_buffer_ptr = &usb_dpram->epx_data[64 * 2];
for (uint8_t i = 1; i <= CONFIG_USBHOST_PIPE_NUM; i++) {
for (uint8_t i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS; i++) {
g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[i].chidx = i;
g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[i].endpoint_control = &usbh_dpram->int_ep_ctrl[i - 1].ctrl;
g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[i].buffer_control = &usbh_dpram->int_ep_buffer_ctrl[i - 1].ctrl;
@@ -368,7 +365,7 @@ int usb_hc_deinit(struct usbh_bus *bus)
// Remove shared irq if it was previously added so as not to fill up shared irq slots
irq_remove_handler(USBCTRL_IRQ, rp2040_usbh_irq);
for (uint8_t i = 0; i <= CONFIG_USBHOST_PIPE_NUM; i++) {
for (uint8_t i = 0; i <= USB_HOST_INTERRUPT_ENDPOINTS; i++) {
usb_osal_sem_delete(g_rp2040_hcd[bus->hcd.hcd_id].pipe_pool[i].waitsem);
}
@@ -703,7 +700,7 @@ static void rp2040_handle_buffer_status(struct usbh_bus *bus)
}
}
for (uint8_t i = 1; remaining_buffers && i <= CONFIG_USBHOST_PIPE_NUM; i++) {
for (uint8_t i = 1; remaining_buffers && i <= USB_HOST_INTERRUPT_ENDPOINTS; i++) {
for (uint8_t j = 0; j < 2; j++) {
bit = 1 << (i * 2 + j);
if (remaining_buffers & bit) {