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use offset to operate register instead of usb struct

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This commit is contained in:
sakumisu
2022-05-27 22:12:36 +08:00
parent fea07e0079
commit 77d6de89f6
2 changed files with 335 additions and 260 deletions
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239
port/musb/usb_dc_musb.c
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@@ -1,12 +1,17 @@
#include "usbd_core.h"
#include "usb_musb_reg.h"
#ifdef CONFIG_USB_MUSB_SUNXI
#define HWREG(x) \
(*((volatile uint32_t *)(x)))
#define HWREGH(x) \
(*((volatile uint16_t *)(x)))
#define HWREGB(x) \
(*((volatile uint8_t *)(x)))
#define SUNXI_USB0_BASE 0x01c13000
#if defined(CONFIG_USB_MUSB_SUNXI)
#ifndef USB_BASE
#define USB_BASE (SUNXI_USB0_BASE)
#define USB_BASE (0x01c13000)
#endif
#ifndef USBD_IRQHandler
@@ -15,6 +20,16 @@
void USBD_IRQHandler(int, void *);
#endif
#define MUSB_FADDR_OFFSET 0x98
#define MUSB_POWER_OFFSET 0x40
#define MUSB_TXIS_OFFSET 0x44
#define MUSB_RXIS_OFFSET 0x46
#define MUSB_TXIE_OFFSET 0x48
#define MUSB_RXIE_OFFSET 0x4A
#define MUSB_IS_OFFSET 0x4C
#define MUSB_IE_OFFSET 0x50
#define MUSB_EPIDX_OFFSET 0x42
#define MUSB_IND_TXMAP_OFFSET 0x80
#define MUSB_IND_TXCSRL_OFFSET 0x82
#define MUSB_IND_TXCSRH_OFFSET 0x83
@@ -22,7 +37,17 @@ void USBD_IRQHandler(int, void *);
#define MUSB_IND_RXCSRL_OFFSET 0x86
#define MUSB_IND_RXCSRH_OFFSET 0x87
#define MUSB_IND_RXCOUNT_OFFSET 0x88
#define MUSB_FIFO_OFFSET 0x00
#define MUSB_FIFO_OFFSET 0x00
#define MUSB_DEVCTL_OFFSET 0x41
#define MUSB_TXFIFOSZ_OFFSET 0x90
#define MUSB_RXFIFOSZ_OFFSET 0x94
#define MUSB_TXFIFOADD_OFFSET 0x92
#define MUSB_RXFIFOADD_OFFSET 0x96
#elif defined(CONFIG_USB_MUSB_CUSTOM)
#else
@@ -34,6 +59,17 @@ void USBD_IRQHandler(int, void *);
#define USB_BASE (0x40086400UL)
#endif
#define MUSB_FADDR_OFFSET 0x00
#define MUSB_POWER_OFFSET 0x01
#define MUSB_TXIS_OFFSET 0x02
#define MUSB_RXIS_OFFSET 0x04
#define MUSB_TXIE_OFFSET 0x06
#define MUSB_RXIE_OFFSET 0x08
#define MUSB_IS_OFFSET 0x0A
#define MUSB_IE_OFFSET 0x0B
#define MUSB_EPIDX_OFFSET 0x0E
#define MUSB_IND_TXMAP_OFFSET 0x10
#define MUSB_IND_TXCSRL_OFFSET 0x12
#define MUSB_IND_TXCSRH_OFFSET 0x13
@@ -41,32 +77,24 @@ void USBD_IRQHandler(int, void *);
#define MUSB_IND_RXCSRL_OFFSET 0x16
#define MUSB_IND_RXCSRH_OFFSET 0x17
#define MUSB_IND_RXCOUNT_OFFSET 0x18
#define MUSB_FIFO_OFFSET 0x20
#define MUSB_FIFO_OFFSET 0x20
#define MUSB_DEVCTL_OFFSET 0x60
#define MUSB_TXFIFOSZ_OFFSET 0x62
#define MUSB_RXFIFOSZ_OFFSET 0x63
#define MUSB_TXFIFOADD_OFFSET 0x64
#define MUSB_RXFIFOADD_OFFSET 0x66
#endif // CONFIG_USB_MUSB_SUNXI
#define USB_FIFO_BASE(ep_idx) (USB_BASE + MUSB_FIFO_OFFSET + 0x4 * ep_idx)
#ifndef USB_NUM_BIDIR_ENDPOINTS
#define USB_NUM_BIDIR_ENDPOINTS 8
#endif
#define USB_TXMAPx_BASE (USB_BASE + MUSB_IND_TXMAP_OFFSET)
#define USB_RXMAPx_BASE (USB_BASE + MUSB_IND_RXMAP_OFFSET)
#define USB_TXCSRLx_BASE (USB_BASE + MUSB_IND_TXCSRL_OFFSET)
#define USB_RXCSRLx_BASE (USB_BASE + MUSB_IND_RXCSRL_OFFSET)
#define USB_TXCSRHx_BASE (USB_BASE + MUSB_IND_TXCSRH_OFFSET)
#define USB_RXCSRHx_BASE (USB_BASE + MUSB_IND_RXCSRH_OFFSET)
#define USB_RXCOUNTx_BASE (USB_BASE + MUSB_IND_RXCOUNT_OFFSET)
#define USB_FIFO_BASE(ep_idx) (USB_BASE + MUSB_FIFO_OFFSET + 0x4 * ep_idx)
#define USB ((volatile USB0_Type *)USB_BASE)
#define HWREG(x) \
(*((volatile uint32_t *)(x)))
#define HWREGH(x) \
(*((volatile uint16_t *)(x)))
#define HWREGB(x) \
(*((volatile uint8_t *)(x)))
typedef enum {
USB_EP0_STATE_SETUP = 0x0, /**< SETUP DATA */
USB_EP0_STATE_IN_DATA = 0x1, /**< IN DATA */
@@ -102,13 +130,13 @@ volatile uint16_t ep0_last_size = 0;
/* get current active ep */
static uint8_t USBC_GetActiveEp(void)
{
return USB->EPIDX;
return HWREGB(USB_BASE + MUSB_EPIDX_OFFSET);
}
/* set the active ep */
static void USBC_SelectActiveEp(uint8_t ep_index)
{
USB->EPIDX = ep_index;
HWREGB(USB_BASE + MUSB_EPIDX_OFFSET) = ep_index;
}
static void usb_musb_write_packet(uint8_t ep_idx, uint8_t *buffer, uint16_t len)
@@ -119,7 +147,7 @@ static void usb_musb_write_packet(uint8_t ep_idx, uint8_t *buffer, uint16_t len)
uint32_t count8;
int i;
if ((size_t)buffer & 0x03) {
if ((uint32_t)buffer & 0x03) {
buf8 = buffer;
for (i = 0; i < len; i++) {
HWREGB(USB_FIFO_BASE(ep_idx)) = *buf8++;
@@ -150,7 +178,7 @@ static void usb_musb_read_packet(uint8_t ep_idx, uint8_t *buffer, uint16_t len)
uint32_t count8;
int i;
if ((size_t)buffer & 0x03) {
if ((uint32_t)buffer & 0x03) {
buf8 = buffer;
for (i = 0; i < len; i++) {
*buf8++ = HWREGB(USB_FIFO_BASE(ep_idx));
@@ -210,22 +238,22 @@ int usb_dc_init(void)
usb_dc_low_level_init();
#ifdef CONFIG_USB_HS
USB->POWER |= USB_POWER_HSENAB;
HWREGB(USB_BASE + MUSB_POWER_OFFSET) |= USB_POWER_HSENAB;
#else
USB->POWER &= ~USB_POWER_HSENAB;
HWREGB(USB_BASE + MUSB_POWER_OFFSET) &= ~USB_POWER_HSENAB;
#endif
USB->EPIDX = 0;
USB->FADDR = 0;
USBC_SelectActiveEp(0);
HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = 0;
USB->DEVCTL |= USB_DEVCTL_SESSION;
HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) |= USB_DEVCTL_SESSION;
/* Enable USB interrupts */
USB->IE = USB_IE_RESET;
USB->TXIE = USB_TXIE_EP0;
USB->RXIE = 0;
HWREGB(USB_BASE + MUSB_IE_OFFSET) = USB_IE_RESET;
HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = USB_TXIE_EP0;
HWREGH(USB_BASE + MUSB_RXIE_OFFSET) = 0;
USB->POWER |= USB_POWER_SOFTCONN;
HWREGB(USB_BASE + MUSB_POWER_OFFSET) |= USB_POWER_SOFTCONN;
return 0;
}
@@ -237,7 +265,7 @@ int usb_dc_deinit(void)
int usbd_set_address(const uint8_t addr)
{
if (addr == 0) {
USB->FADDR = 0;
HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = 0;
}
usb_dc_cfg.dev_addr = addr;
@@ -264,9 +292,9 @@ int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
usb_dc_cfg.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
usb_dc_cfg.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
USB->RXIE |= (1 << ep_idx);
HWREGH(USB_BASE + MUSB_RXIE_OFFSET) |= (1 << ep_idx);
HWREGH(USB_RXMAPx_BASE) = ep_cfg->ep_mps;
HWREGH(USB_BASE + MUSB_IND_RXMAP_OFFSET) = ep_cfg->ep_mps;
//
// Allow auto clearing of RxPktRdy when packet of size max packet
@@ -298,27 +326,27 @@ int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
ui32Register |= USB_RXCSRH1_ISO;
}
HWREGB(USB_RXCSRHx_BASE) = ui32Register;
HWREGB(USB_BASE + MUSB_IND_RXCSRH_OFFSET) = ui32Register;
// Reset the Data toggle to zero.
if (HWREGB(USB_RXCSRLx_BASE) & USB_RXCSRL1_RXRDY)
HWREGB(USB_RXCSRLx_BASE) = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
if (HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_RXRDY)
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = (USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH);
else
HWREGB(USB_RXCSRLx_BASE) = USB_RXCSRL1_CLRDT;
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = USB_RXCSRL1_CLRDT;
fifo_size = usb_musb_get_fifo_size(ep_cfg->ep_mps, &used);
USB->RXFIFOSZ = fifo_size & 0x0f;
USB->RXFIFOADD = (usb_dc_cfg.fifo_size_offset >> 3);
HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = fifo_size & 0x0f;
HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = (usb_dc_cfg.fifo_size_offset >> 3);
usb_dc_cfg.fifo_size_offset += used;
} else {
usb_dc_cfg.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
usb_dc_cfg.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
USB->TXIE |= (1 << ep_idx);
HWREGH(USB_BASE + MUSB_TXIE_OFFSET) |= (1 << ep_idx);
HWREGH(USB_TXMAPx_BASE) = ep_cfg->ep_mps;
HWREGH(USB_BASE + MUSB_IND_TXMAP_OFFSET) = ep_cfg->ep_mps;
//
// Allow auto setting of TxPktRdy when max packet size has been loaded
@@ -344,17 +372,18 @@ int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
ui32Register |= USB_TXCSRH1_ISO;
}
HWREGB(USB_TXCSRHx_BASE) = ui32Register;
HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) = ui32Register;
// Reset the Data toggle to zero.
if (HWREGB(USB_TXCSRLx_BASE) & USB_TXCSRL1_TXRDY)
HWREGB(USB_TXCSRLx_BASE) = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_TXRDY)
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH);
else
HWREGB(USB_TXCSRLx_BASE) = USB_TXCSRL1_CLRDT;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_CLRDT;
fifo_size = usb_musb_get_fifo_size(ep_cfg->ep_mps, &used);
USB->TXFIFOSZ = fifo_size & 0x0f;
USB->TXFIFOADD = (usb_dc_cfg.fifo_size_offset >> 3);
HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = fifo_size & 0x0f;
HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = (usb_dc_cfg.fifo_size_offset >> 3);
usb_dc_cfg.fifo_size_offset += used;
}
@@ -380,16 +409,16 @@ int usbd_ep_set_stall(const uint8_t ep)
if (USB_EP_DIR_IS_OUT(ep)) {
if (ep_idx == 0x00) {
usb_ep0_state = USB_EP0_STATE_STALL;
HWREGB(USB_TXCSRLx_BASE) |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC);
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC);
} else {
HWREGB(USB_RXCSRLx_BASE) |= USB_RXCSRL1_STALL;
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) |= USB_RXCSRL1_STALL;
}
} else {
if (ep_idx == 0x00) {
usb_ep0_state = USB_EP0_STATE_STALL;
HWREGB(USB_TXCSRLx_BASE) |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC);
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC);
} else {
HWREGB(USB_TXCSRLx_BASE) |= USB_TXCSRL1_STALL;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= USB_TXCSRL1_STALL;
}
}
@@ -407,21 +436,21 @@ int usbd_ep_clear_stall(const uint8_t ep)
if (USB_EP_DIR_IS_OUT(ep)) {
if (ep_idx == 0x00) {
HWREGB(USB_TXCSRLx_BASE) &= ~USB_CSRL0_STALLED;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_STALLED;
} else {
// Clear the stall on an OUT endpoint.
HWREGB(USB_RXCSRLx_BASE) &= ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED);
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED);
// Reset the data toggle.
HWREGB(USB_RXCSRLx_BASE) |= USB_RXCSRL1_CLRDT;
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) |= USB_RXCSRL1_CLRDT;
}
} else {
if (ep_idx == 0x00) {
HWREGB(USB_TXCSRLx_BASE) &= ~USB_CSRL0_STALLED;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_STALLED;
} else {
// Clear the stall on an IN endpoint.
HWREGB(USB_TXCSRLx_BASE) &= ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED);
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED);
// Reset the data toggle.
HWREGB(USB_TXCSRLx_BASE) |= USB_TXCSRL1_CLRDT;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= USB_TXCSRL1_CLRDT;
}
}
@@ -449,8 +478,8 @@ int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint
}
if (ep_idx == 0x00) {
while (HWREGB(USB_TXCSRLx_BASE) & USB_CSRL0_TXRDY) {
if (HWREGB(USB_TXCSRLx_BASE) & USB_CSRL0_ERROR) {
while (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_CSRL0_TXRDY) {
if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_CSRL0_ERROR) {
ret = -2;
goto _RET;
}
@@ -460,8 +489,8 @@ int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint
}
}
} else {
while (HWREGB(USB_TXCSRLx_BASE) & USB_TXCSRL1_TXRDY) {
if ((HWREGB(USB_TXCSRLx_BASE) & USB_TXCSRL1_ERROR) || (HWREGB(USB_TXCSRLx_BASE) & USB_TXCSRL1_UNDRN)) {
while (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_TXRDY) {
if ((HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_ERROR) || (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_UNDRN)) {
ret = -2;
goto _RET;
}
@@ -486,7 +515,7 @@ int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint
usb_musb_write_packet(ep_idx, (uint8_t *)data, data_len);
if (ep_idx != 0) {
HWREGB(USB_TXCSRLx_BASE) = USB_TXCSRL1_TXRDY;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY;
}
if (ret_bytes) {
*ret_bytes = data_len;
@@ -513,7 +542,7 @@ int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_
if (!max_data_len) {
if (ep_idx != 0x00) {
HWREGB(USB_RXCSRLx_BASE) &= ~(USB_RXCSRL1_RXRDY);
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~(USB_RXCSRL1_RXRDY);
}
ret = 0;
goto _RET;
@@ -523,12 +552,12 @@ int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_
if (usb_ep0_state == USB_EP0_STATE_SETUP) {
memcpy(data, (uint8_t *)&usb_dc_cfg.setup, 8);
} else {
read_count = HWREGH(USB_RXCOUNTx_BASE);
read_count = HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET);
read_count = MIN(read_count, max_data_len);
usb_musb_read_packet(0, data, read_count);
}
} else {
read_count = HWREGH(USB_RXCOUNTx_BASE);
read_count = HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET);
read_count = MIN(read_count, max_data_len);
usb_musb_read_packet(ep_idx, data, read_count);
}
@@ -544,27 +573,27 @@ _RET:
static void handle_ep0(void)
{
uint8_t ep0_status = USB->CSRL0;
uint8_t ep0_status = HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET);
if (ep0_status & USB_CSRL0_STALLED) {
USB->CSRL0 &= ~USB_CSRL0_STALLED;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_STALLED;
usb_ep0_state = USB_EP0_STATE_SETUP;
return;
}
if (ep0_status & USB_CSRL0_SETEND) {
USB->CSRL0 = USB_CSRL0_SETENDC;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_SETENDC;
}
if (usb_dc_cfg.dev_addr > 0) {
USB->FADDR = usb_dc_cfg.dev_addr;
HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = usb_dc_cfg.dev_addr;
usb_dc_cfg.dev_addr = 0;
}
switch (usb_ep0_state) {
case USB_EP0_STATE_SETUP:
if (ep0_status & USB_CSRL0_RXRDY) {
uint32_t read_count = HWREGH(USB_RXCOUNTx_BASE);
uint32_t read_count = HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET);
if (read_count != 8) {
return;
@@ -572,9 +601,9 @@ static void handle_ep0(void)
usb_musb_read_packet(0, (uint8_t *)&usb_dc_cfg.setup, 8);
if (usb_dc_cfg.setup.wLength) {
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_RXRDYC;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_RXRDYC;
} else {
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND);
}
usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
@@ -584,16 +613,16 @@ static void handle_ep0(void)
if (usb_dc_cfg.setup.bmRequestType & 0x80) {
usb_ep0_state = USB_EP0_STATE_IN_DATA;
if (ep0_last_size > usb_dc_cfg.in_ep[0].ep_mps) {
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_TXRDY;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_TXRDY;
} else {
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_TXRDY | USB_CSRL0_DATAEND);
usb_ep0_state = USB_EP0_STATE_OUT_STATUS;
}
} else {
usb_ep0_state = USB_EP0_STATE_OUT_DATA;
}
} else {
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_TXRDY | USB_CSRL0_DATAEND);
usb_ep0_state = USB_EP0_STATE_IN_STATUS;
}
}
@@ -603,9 +632,9 @@ static void handle_ep0(void)
case USB_EP0_STATE_IN_DATA:
usbd_event_notify_handler(USBD_EVENT_EP0_IN_NOTIFY, NULL);
if (ep0_last_size > usb_dc_cfg.in_ep[0].ep_mps) {
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_TXRDY;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_TXRDY;
} else {
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_TXRDY | USB_CSRL0_DATAEND);
usb_ep0_state = USB_EP0_STATE_OUT_STATUS;
}
break;
@@ -616,10 +645,10 @@ static void handle_ep0(void)
if (ep0_status & USB_CSRL0_RXRDY) {
usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
if (usb_dc_cfg.setup.wLength > usb_dc_cfg.out_ep[0].ep_mps) {
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_RXRDYC;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_RXRDYC;
} else {
usb_ep0_state = USB_EP0_STATE_IN_STATUS;
HWREGB(USB_TXCSRLx_BASE) = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND);
}
}
break;
@@ -640,23 +669,26 @@ void USBD_IRQHandler(void)
uint32_t rxis;
uint8_t old_ep_idx;
is = USB->IS;
txis = USB->TXIS;
rxis = USB->RXIS;
is = HWREGB(USB_BASE + MUSB_IS_OFFSET);
txis = HWREGH(USB_BASE + MUSB_TXIS_OFFSET);
rxis = HWREGH(USB_BASE + MUSB_RXIS_OFFSET);
HWREGB(USB_BASE + MUSB_IS_OFFSET) = is;
old_ep_idx = USBC_GetActiveEp();
/* Receive a reset signal from the USB bus */
if (is & USB_IS_RESET) {
usbd_event_notify_handler(USBD_EVENT_RESET, NULL);
USB->TXIE = USB_TXIE_EP0;
USB->RXIE = 0;
HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = USB_TXIE_EP0;
HWREGH(USB_BASE + MUSB_RXIE_OFFSET) = 0;
for (uint8_t i = 1; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
USB->EPIDX = i;
USB->TXFIFOSZ = 0;
USB->TXFIFOADD = 0;
USB->RXFIFOSZ = 0;
USB->RXFIFOADD = 0;
USBC_SelectActiveEp(i);
HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = 0;
HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = 0;
HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = 0;
HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = 0;
}
usb_dc_cfg.fifo_size_offset = USB_CTRL_EP_MPS;
}
@@ -670,35 +702,34 @@ void USBD_IRQHandler(void)
if (is & USB_IS_SUSPEND) {
}
USB->IS = is; // clear isr flag
txis &= USB->TXIE;
txis &= HWREGH(USB_BASE + MUSB_TXIE_OFFSET);
/* Handle EP0 interrupt */
if (txis & USB_TXIE_EP0) {
HWREGH(USB_BASE + MUSB_TXIS_OFFSET) = USB_TXIE_EP0;
USBC_SelectActiveEp(0);
handle_ep0();
txis &= ~USB_TXIE_EP0;
USB->TXIS = USB_TXIE_EP0; // clear isr flag
}
while (txis) {
uint8_t ep_idx = __builtin_ctz(txis);
USBC_SelectActiveEp(ep_idx);
if (HWREGB(USB_TXCSRLx_BASE) & USB_TXCSRL1_UNDRN) {
HWREGB(USB_TXCSRLx_BASE) &= ~USB_TXCSRL1_UNDRN;
HWREGH(USB_BASE + MUSB_TXIS_OFFSET) = (1 << ep_idx);
if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_UNDRN) {
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_TXCSRL1_UNDRN;
}
usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(0x80 | ep_idx));
txis &= ~(1 << ep_idx);
USB->TXIS = (1 << ep_idx); // clear isr flag
}
rxis &= USB->RXIE;
rxis &= HWREGH(USB_BASE + MUSB_RXIE_OFFSET);
while (rxis) {
uint8_t ep_idx = __builtin_ctz(rxis);
USBC_SelectActiveEp(ep_idx);
if (HWREGB(USB_RXCSRLx_BASE) & USB_RXCSRL1_RXRDY)
HWREGH(USB_BASE + MUSB_RXIS_OFFSET) = (1 << ep_idx);
if (HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_RXRDY)
usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(ep_idx & 0x7f));
rxis &= ~(1 << ep_idx);
USB->RXIS = (1 << ep_idx); // clear isr flag
}
USBC_SelectActiveEp(old_ep_idx);

356
port/musb/usb_hc_musb.c
View File

@@ -1,12 +1,17 @@
#include "usbh_core.h"
#include "usb_musb_reg.h"
#define HWREG(x) \
(*((volatile uint32_t *)(x)))
#define HWREGH(x) \
(*((volatile uint16_t *)(x)))
#define HWREGB(x) \
(*((volatile uint8_t *)(x)))
#ifdef CONFIG_USB_MUSB_SUNXI
#define SUNXI_USB0_BASE 0x01c13000
#ifndef USB_BASE
#define USB_BASE (SUNXI_USB0_BASE)
#define USB_BASE (0x01c13000)
#endif
#ifndef USBH_IRQHandler
@@ -14,6 +19,16 @@
void USBH_IRQHandler(int, void *);
#endif
#define MUSB_FADDR_OFFSET 0x98
#define MUSB_POWER_OFFSET 0x40
#define MUSB_TXIS_OFFSET 0x44
#define MUSB_RXIS_OFFSET 0x46
#define MUSB_TXIE_OFFSET 0x48
#define MUSB_RXIE_OFFSET 0x4A
#define MUSB_IS_OFFSET 0x4C
#define MUSB_IE_OFFSET 0x50
#define MUSB_EPIDX_OFFSET 0x42
#define MUSB_IND_TXMAP_OFFSET 0x80
#define MUSB_IND_TXCSRL_OFFSET 0x82
#define MUSB_IND_TXCSRH_OFFSET 0x83
@@ -25,7 +40,35 @@ void USBH_IRQHandler(int, void *);
#define MUSB_IND_TXINTERVAL_OFFSET 0x8D
#define MUSB_IND_RXTYPE_OFFSET 0x8E
#define MUSB_IND_RXINTERVAL_OFFSET 0x8F
#define MUSB_FIFO_OFFSET 0x00
#define MUSB_FIFO_OFFSET 0x00
#define MUSB_DEVCTL_OFFSET 0x41
#define MUSB_TXFIFOSZ_OFFSET 0x90
#define MUSB_RXFIFOSZ_OFFSET 0x94
#define MUSB_TXFIFOADD_OFFSET 0x92
#define MUSB_RXFIFOADD_OFFSET 0x96
#define MUSB_TXFUNCADDR0_OFFSET 0x98
#define MUSB_TXHUBADDR0_OFFSET 0x9A
#define MUSB_TXHUBPORT0_OFFSET 0x9B
#define MUSB_TXFUNCADDRx_OFFSET 0x98
#define MUSB_TXHUBADDRx_OFFSET 0x9A
#define MUSB_TXHUBPORTx_OFFSET 0x9B
#define MUSB_RXFUNCADDRx_OFFSET 0x9C
#define MUSB_RXHUBADDRx_OFFSET 0x9E
#define MUSB_RXHUBPORTx_OFFSET 0x9F
#define USB_TXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDRx_OFFSET)
#define USB_TXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXHUBADDRx_OFFSET)
#define USB_TXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXHUBPORTx_OFFSET)
#define USB_RXADDR_BASE(ep_idx) (USB_BASE + MUSB_RXFUNCADDRx_OFFSET)
#define USB_RXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_RXHUBADDRx_OFFSET)
#define USB_RXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_RXHUBPORTx_OFFSET)
#elif defined(CONFIG_USB_MUSB_CUSTOM)
#else
#ifndef USBH_IRQHandler
#define USBH_IRQHandler USB_INT_Handler
@@ -35,6 +78,17 @@ void USBH_IRQHandler(int, void *);
#define USB_BASE (0x40086400UL)
#endif
#define MUSB_FADDR_OFFSET 0x00
#define MUSB_POWER_OFFSET 0x01
#define MUSB_TXIS_OFFSET 0x02
#define MUSB_RXIS_OFFSET 0x04
#define MUSB_TXIE_OFFSET 0x06
#define MUSB_RXIE_OFFSET 0x08
#define MUSB_IS_OFFSET 0x0A
#define MUSB_IE_OFFSET 0x0B
#define MUSB_EPIDX_OFFSET 0x0E
#define MUSB_IND_TXMAP_OFFSET 0x10
#define MUSB_IND_TXCSRL_OFFSET 0x12
#define MUSB_IND_TXCSRH_OFFSET 0x13
@@ -46,46 +100,35 @@ void USBH_IRQHandler(int, void *);
#define MUSB_IND_TXINTERVAL_OFFSET 0x1B
#define MUSB_IND_RXTYPE_OFFSET 0x1C
#define MUSB_IND_RXINTERVAL_OFFSET 0x1D
#define MUSB_FIFO_OFFSET 0x20
#define MUSB_FIFO_OFFSET 0x20
#define MUSB_DEVCTL_OFFSET 0x60
#define MUSB_TXFIFOSZ_OFFSET 0x62
#define MUSB_RXFIFOSZ_OFFSET 0x63
#define MUSB_TXFIFOADD_OFFSET 0x64
#define MUSB_RXFIFOADD_OFFSET 0x66
#define MUSB_TXFUNCADDR0_OFFSET 0x80
#define MUSB_TXHUBADDR0_OFFSET 0x82
#define MUSB_TXHUBPORT0_OFFSET 0x83
#define MUSB_TXFUNCADDRx_OFFSET 0x88
#define MUSB_TXHUBADDRx_OFFSET 0x8A
#define MUSB_TXHUBPORTx_OFFSET 0x8B
#define MUSB_RXFUNCADDRx_OFFSET 0x8C
#define MUSB_RXHUBADDRx_OFFSET 0x8E
#define MUSB_RXHUBPORTx_OFFSET 0x8F
#define USB_TXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx)
#define USB_TXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 2)
#define USB_TXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 3)
#define USB_RXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 4)
#define USB_RXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 6)
#define USB_RXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 7)
#endif
#define USB ((USB0_Type *)USB_BASE)
#define HWREG(x) \
(*((volatile uint32_t *)(x)))
#define HWREGH(x) \
(*((volatile uint16_t *)(x)))
#define HWREGB(x) \
(*((volatile uint8_t *)(x)))
#define USB_TXMAPx_BASE (USB_BASE + MUSB_IND_TXMAP_OFFSET)
#define USB_RXMAPx_BASE (USB_BASE + MUSB_IND_RXMAP_OFFSET)
#define USB_TXCSRLx_BASE (USB_BASE + MUSB_IND_TXCSRL_OFFSET)
#define USB_RXCSRLx_BASE (USB_BASE + MUSB_IND_RXCSRL_OFFSET)
#define USB_TXCSRHx_BASE (USB_BASE + MUSB_IND_TXCSRH_OFFSET)
#define USB_RXCSRHx_BASE (USB_BASE + MUSB_IND_RXCSRH_OFFSET)
#define USB_RXCOUNTx_BASE (USB_BASE + MUSB_IND_RXCOUNT_OFFSET)
#define USB_FIFO_BASE(ep_idx) (USB_BASE + MUSB_FIFO_OFFSET + 0x4 * ep_idx)
#define USB_TXTYPEx_BASE (USB_BASE + MUSB_IND_TXTYPE_OFFSET)
#define USB_RXTYPEx_BASE (USB_BASE + MUSB_IND_RXTYPE_OFFSET)
#define USB_TXINTERVALx_BASE (USB_BASE + MUSB_IND_TXINTERVAL_OFFSET)
#define USB_RXINTERVALx_BASE (USB_BASE + MUSB_IND_RXINTERVAL_OFFSET)
#ifdef CONFIG_USB_MUSB_SUNXI
#define USB_TXADDR_BASE(ep_idx) (&USB->TXFUNCADDR0)
#define USB_TXHUBADDR_BASE(ep_idx) (&USB->TXHUBADDR0)
#define USB_TXHUBPORT_BASE(ep_idx) (&USB->TXHUBPORT0)
#define USB_RXADDR_BASE(ep_idx) (&USB->RXFUNCADDR0)
#define USB_RXHUBADDR_BASE(ep_idx) (&USB->RXHUBADDR0)
#define USB_RXHUBPORT_BASE(ep_idx) (&USB->RXHUBPORT0)
#else
#define USB_TXADDR_BASE(ep_idx) (&USB->TXFUNCADDR0 + 0x8 * ep_idx)
#define USB_TXHUBADDR_BASE(ep_idx) (&USB->TXFUNCADDR0 + 0x8 * ep_idx + 2)
#define USB_TXHUBPORT_BASE(ep_idx) (&USB->TXFUNCADDR0 + 0x8 * ep_idx + 3)
#define USB_RXADDR_BASE(ep_idx) (&USB->TXFUNCADDR0 + 0x8 * ep_idx + 4)
#define USB_RXHUBADDR_BASE(ep_idx) (&USB->TXFUNCADDR0 + 0x8 * ep_idx + 6)
#define USB_RXHUBPORT_BASE(ep_idx) (&USB->TXFUNCADDR0 + 0x8 * ep_idx + 7)
#endif
#ifndef CONIFG_USB_MUSB_EP_NUM
#define CONIFG_USB_MUSB_EP_NUM 5
@@ -134,28 +177,28 @@ volatile uint8_t ep0_outlen = 0;
/* get current active ep */
static uint8_t USBC_GetActiveEp(void)
{
return USB->EPIDX;
return HWREGB(USB_BASE + MUSB_EPIDX_OFFSET);
}
/* set the active ep */
static void USBC_SelectActiveEp(uint8_t ep_index)
{
USB->EPIDX = ep_index;
HWREGB(USB_BASE + MUSB_EPIDX_OFFSET) = ep_index;
}
static void usb_musb_fifo_flush(uint8_t ep)
{
uint8_t ep_idx = ep & 0x7f;
if (ep_idx == 0) {
if ((HWREGB(USB_TXCSRLx_BASE) & (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0)
HWREGB(USB_RXCSRLx_BASE) |= USB_CSRH0_FLUSH;
if ((HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0)
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) |= USB_CSRH0_FLUSH;
} else {
if (ep & 0x80) {
if (HWREGB(USB_TXCSRLx_BASE) & USB_TXCSRL1_TXRDY)
HWREGB(USB_TXCSRLx_BASE) |= USB_TXCSRL1_FLUSH;
if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_TXRDY)
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= USB_TXCSRL1_FLUSH;
} else {
if (HWREGB(USB_RXCSRLx_BASE) & USB_RXCSRL1_RXRDY)
HWREGB(USB_RXCSRLx_BASE) |= USB_RXCSRL1_FLUSH;
if (HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_RXRDY)
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) |= USB_RXCSRL1_FLUSH;
}
}
}
@@ -439,24 +482,25 @@ __WEAK void usb_hc_low_level_init(void)
int usb_hc_init(void)
{
uint8_t regval;
uint32_t fifo_offset = 0;
g_usbhost.connected = 0;
usb_hc_low_level_init();
USB->EPIDX = 0;
USB->TXFIFOADD = 0;
USB->TXFIFOSZ = USB_TXFIFOSZ_SIZE_64;
USB->RXFIFOADD = 0;
USB->RXFIFOSZ = USB_TXFIFOSZ_SIZE_64;
USBC_SelectActiveEp(0);
HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = USB_TXFIFOSZ_SIZE_64;
HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = 0;
HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = USB_TXFIFOSZ_SIZE_64;
HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = 0;
fifo_offset += 64;
for (uint8_t i = 1; i < CONIFG_USB_MUSB_EP_NUM; i++) {
USB->EPIDX = i;
USB->TXFIFOADD = fifo_offset;
USB->TXFIFOSZ = USB_TXFIFOSZ_SIZE_512;
USB->RXFIFOADD = fifo_offset;
USB->RXFIFOSZ = USB_TXFIFOSZ_SIZE_512;
USBC_SelectActiveEp(i);
HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = USB_TXFIFOSZ_SIZE_512;
HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = fifo_offset;
HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = USB_TXFIFOSZ_SIZE_512;
HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = fifo_offset;
fifo_offset += 512;
}
@@ -464,18 +508,22 @@ int usb_hc_init(void)
g_usbhost.exclsem[i] = usb_osal_mutex_create();
}
USB->IE = USB_IE_RESET | USB_IE_CONN | USB_IE_DISCON |
USB_IE_RESUME | USB_IE_SUSPND |
USB_IE_BABBLE | USB_IE_SESREQ | USB_IE_VBUSERR;
/* Enable USB interrupts */
regval = USB_IE_RESET | USB_IE_CONN | USB_IE_DISCON |
USB_IE_RESUME | USB_IE_SUSPND |
USB_IE_BABBLE | USB_IE_SESREQ | USB_IE_VBUSERR;
USB->TXIE = USB_TXIE_EP0;
USB->RXIE = 0;
HWREGB(USB_BASE + MUSB_IE_OFFSET) = regval;
HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = USB_TXIE_EP0;
HWREGH(USB_BASE + MUSB_RXIE_OFFSET) = 0;
USB->POWER |= USB_POWER_HSENAB;
USB->DEVCTL |= USB_DEVCTL_SESSION;
HWREGB(USB_BASE + MUSB_POWER_OFFSET) |= USB_POWER_HSENAB;
HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) |= USB_DEVCTL_SESSION;
#ifdef CONFIG_USB_MUSB_SUNXI
USB->CSRL0 = USB_CSRL0_TXRDY;
USBC_SelectActiveEp(0);
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_TXRDY;
#endif
return 0;
}
@@ -487,9 +535,9 @@ bool usbh_get_port_connect_status(const uint8_t port)
int usbh_reset_port(const uint8_t port)
{
USB->POWER |= USB_POWER_RESET;
HWREGB(USB_BASE + MUSB_POWER_OFFSET) |= USB_POWER_RESET;
usb_osal_msleep(20);
USB->POWER &= ~(USB_POWER_RESET);
HWREGB(USB_BASE + MUSB_POWER_OFFSET) &= ~(USB_POWER_RESET);
usb_osal_msleep(20);
return 0;
}
@@ -498,11 +546,11 @@ uint8_t usbh_get_port_speed(const uint8_t port)
{
uint8_t speed;
if (USB->POWER & USB_POWER_HSMODE)
if (HWREGB(USB_BASE + MUSB_POWER_OFFSET) & USB_POWER_HSMODE)
speed = USB_SPEED_HIGH;
else if (USB->DEVCTL & USB_DEVCTL_FSDEV)
else if (HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) & USB_DEVCTL_FSDEV)
speed = USB_SPEED_FULL;
else if (USB->DEVCTL & USB_DEVCTL_LSDEV)
else if (HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) & USB_DEVCTL_LSDEV)
speed = USB_SPEED_LOW;
return speed;
@@ -559,7 +607,7 @@ int usbh_ep_alloc(usbh_epinfo_t *ep, const struct usbh_endpoint_cfg *ep_cfg)
chan->waitsem = usb_osal_sem_create(0);
HWREGB(USB_TXINTERVALx_BASE) = 0;
HWREGB(USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) = 0;
*ep = (usbh_epinfo_t)chan;
} else {
@@ -586,9 +634,9 @@ int usbh_ep_alloc(usbh_epinfo_t *ep, const struct usbh_endpoint_cfg *ep_cfg)
chan->waitsem = usb_osal_sem_create(0);
if (chan->in) {
USB->RXIE |= (1 << ep_idx);
HWREGH(USB_BASE + MUSB_RXIE_OFFSET) |= (1 << ep_idx);
} else {
USB->TXIE |= (1 << ep_idx);
HWREGH(USB_BASE + MUSB_TXIE_OFFSET) |= (1 << ep_idx);
}
*ep = (usbh_epinfo_t)chan;
@@ -626,7 +674,7 @@ int usbh_control_transfer(usbh_epinfo_t ep, struct usb_setup_packet *setup, uint
USBC_SelectActiveEp(0);
HWREGB(USB_TXADDR_BASE(0)) = chan->hport->dev_addr;
HWREGB(USB_TXTYPEx_BASE) = chan->speed;
HWREGB(USB_BASE + MUSB_IND_TXTYPE_OFFSET) = chan->speed;
if (chan->hport->parent == NULL) {
HWREGB(USB_TXHUBADDR_BASE(0)) = 0;
HWREGB(USB_TXHUBPORT_BASE(0)) = 0;
@@ -649,7 +697,7 @@ int usbh_control_transfer(usbh_epinfo_t ep, struct usb_setup_packet *setup, uint
usb_ep0_state = USB_EP0_STATE_IN_STATUS;
}
USB->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_SETUP;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_TXRDY | USB_CSRL0_SETUP;
USBC_SelectActiveEp(old_ep_index);
ret = usb_musb_chan_wait(chan, CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT);
@@ -686,8 +734,8 @@ int usbh_ep_bulk_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t buflen, ui
if (chan->in) {
HWREGB(USB_RXADDR_BASE(chan->ep_idx)) = chan->hport->dev_addr;
HWREGB(USB_RXTYPEx_BASE) = chan->ep_idx | chan->speed | USB_TXTYPE1_PROTO_BULK;
HWREGB(USB_RXINTERVALx_BASE) = chan->interval;
HWREGB(USB_BASE + MUSB_IND_RXTYPE_OFFSET) = chan->ep_idx | chan->speed | USB_TXTYPE1_PROTO_BULK;
HWREGB(USB_BASE + MUSB_IND_RXINTERVAL_OFFSET) = chan->interval;
if (chan->hport->parent == NULL) {
HWREGB(USB_RXHUBADDR_BASE(chan->ep_idx)) = 0;
HWREGB(USB_RXHUBPORT_BASE(chan->ep_idx)) = 0;
@@ -698,12 +746,12 @@ int usbh_ep_bulk_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t buflen, ui
chan->buffer = buffer;
chan->buflen = buflen;
HWREGB(USB_TXCSRHx_BASE) &= ~USB_TXCSRH1_MODE;
HWREGB(USB_RXCSRLx_BASE) = USB_RXCSRL1_REQPKT;
HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) &= ~USB_TXCSRH1_MODE;
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = USB_RXCSRL1_REQPKT;
} else {
HWREGB(USB_TXADDR_BASE(chan->ep_idx)) = chan->hport->dev_addr;
HWREGB(USB_TXTYPEx_BASE) = chan->ep_idx | chan->speed | USB_TXTYPE1_PROTO_BULK;
HWREGB(USB_TXINTERVALx_BASE) = chan->interval;
HWREGB(USB_BASE + MUSB_IND_TXTYPE_OFFSET) = chan->ep_idx | chan->speed | USB_TXTYPE1_PROTO_BULK;
HWREGB(USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) = chan->interval;
if (chan->hport->parent == NULL) {
HWREGB(USB_TXHUBADDR_BASE(chan->ep_idx)) = 0;
HWREGB(USB_TXHUBPORT_BASE(chan->ep_idx)) = 0;
@@ -719,9 +767,9 @@ int usbh_ep_bulk_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t buflen, ui
}
usb_musb_write_packet(chan->ep_idx, chan->buffer, buflen);
HWREGB(USB_TXCSRHx_BASE) &= ~USB_TXCSRH1_MODE;
HWREGB(USB_TXCSRHx_BASE) |= USB_TXCSRH1_MODE;
HWREGB(USB_TXCSRLx_BASE) = USB_TXCSRL1_TXRDY;
HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) &= ~USB_TXCSRH1_MODE;
HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) |= USB_TXCSRH1_MODE;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY;
}
USBC_SelectActiveEp(old_ep_index);
@@ -759,8 +807,8 @@ int usbh_ep_intr_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t buflen, ui
if (chan->in) {
HWREGB(USB_RXADDR_BASE(chan->ep_idx)) = chan->hport->dev_addr;
HWREGB(USB_RXTYPEx_BASE) = chan->ep_idx | chan->speed | USB_TXTYPE1_PROTO_INT;
HWREGB(USB_RXINTERVALx_BASE) = chan->interval;
HWREGB(USB_BASE + MUSB_IND_RXTYPE_OFFSET) = chan->ep_idx | chan->speed | USB_TXTYPE1_PROTO_INT;
HWREGB(USB_BASE + MUSB_IND_RXINTERVAL_OFFSET) = chan->interval;
if (chan->hport->parent == NULL) {
HWREGB(USB_RXHUBADDR_BASE(chan->ep_idx)) = 0;
HWREGB(USB_RXHUBPORT_BASE(chan->ep_idx)) = 0;
@@ -771,12 +819,12 @@ int usbh_ep_intr_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t buflen, ui
chan->buffer = buffer;
chan->buflen = buflen;
HWREGB(USB_TXCSRHx_BASE) &= ~USB_TXCSRH1_MODE;
HWREGB(USB_RXCSRLx_BASE) = USB_RXCSRL1_REQPKT;
HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) &= ~USB_TXCSRH1_MODE;
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = USB_RXCSRL1_REQPKT;
} else {
HWREGB(USB_TXADDR_BASE(chan->ep_idx)) = chan->hport->dev_addr;
HWREGB(USB_TXTYPEx_BASE) = chan->ep_idx | chan->speed | USB_TXTYPE1_PROTO_INT;
HWREGB(USB_TXINTERVALx_BASE) = chan->interval;
HWREGB(USB_BASE + MUSB_IND_TXTYPE_OFFSET) = chan->ep_idx | chan->speed | USB_TXTYPE1_PROTO_INT;
HWREGB(USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) = chan->interval;
if (chan->hport->parent == NULL) {
HWREGB(USB_TXHUBADDR_BASE(chan->ep_idx)) = 0;
HWREGB(USB_TXHUBPORT_BASE(chan->ep_idx)) = 0;
@@ -792,9 +840,9 @@ int usbh_ep_intr_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t buflen, ui
}
usb_musb_write_packet(chan->ep_idx, chan->buffer, buflen);
HWREGB(USB_TXCSRHx_BASE) &= ~USB_TXCSRH1_MODE;
HWREGB(USB_TXCSRHx_BASE) |= USB_TXCSRH1_MODE;
HWREGB(USB_TXCSRLx_BASE) = USB_TXCSRL1_TXRDY;
HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) &= ~USB_TXCSRH1_MODE;
HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) |= USB_TXCSRH1_MODE;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY;
}
USBC_SelectActiveEp(old_ep_index);
@@ -836,8 +884,8 @@ int usbh_ep_bulk_async_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t bufl
if (chan->in) {
HWREGB(USB_RXADDR_BASE(chan->ep_idx)) = chan->hport->dev_addr;
HWREGB(USB_RXTYPEx_BASE) = chan->ep_idx | chan->speed | USB_TXTYPE1_PROTO_BULK;
HWREGB(USB_RXINTERVALx_BASE) = chan->interval;
HWREGB(USB_BASE + MUSB_IND_RXTYPE_OFFSET) = chan->ep_idx | chan->speed | USB_TXTYPE1_PROTO_BULK;
HWREGB(USB_BASE + MUSB_IND_RXINTERVAL_OFFSET) = chan->interval;
if (chan->hport->parent == NULL) {
HWREGB(USB_RXHUBADDR_BASE(chan->ep_idx)) = 0;
HWREGB(USB_RXHUBPORT_BASE(chan->ep_idx)) = 0;
@@ -848,12 +896,12 @@ int usbh_ep_bulk_async_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t bufl
chan->buffer = buffer;
chan->buflen = buflen;
HWREGB(USB_TXCSRHx_BASE) &= ~USB_TXCSRH1_MODE;
HWREGB(USB_RXCSRLx_BASE) = USB_RXCSRL1_REQPKT;
HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) &= ~USB_TXCSRH1_MODE;
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = USB_RXCSRL1_REQPKT;
} else {
HWREGB(USB_TXADDR_BASE(chan->ep_idx)) = chan->hport->dev_addr;
HWREGB(USB_TXTYPEx_BASE) = chan->ep_idx | chan->speed | USB_TXTYPE1_PROTO_BULK;
HWREGB(USB_TXINTERVALx_BASE) = chan->interval;
HWREGB(USB_BASE + MUSB_IND_TXTYPE_OFFSET) = chan->ep_idx | chan->speed | USB_TXTYPE1_PROTO_BULK;
HWREGB(USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) = chan->interval;
if (chan->hport->parent == NULL) {
HWREGB(USB_TXHUBADDR_BASE(chan->ep_idx)) = 0;
HWREGB(USB_TXHUBPORT_BASE(chan->ep_idx)) = 0;
@@ -869,9 +917,9 @@ int usbh_ep_bulk_async_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t bufl
}
usb_musb_write_packet(chan->ep_idx, chan->buffer, buflen);
HWREGB(USB_TXCSRHx_BASE) &= ~USB_TXCSRH1_MODE;
HWREGB(USB_TXCSRHx_BASE) |= USB_TXCSRH1_MODE;
HWREGB(USB_TXCSRLx_BASE) = USB_TXCSRL1_TXRDY;
HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) &= ~USB_TXCSRH1_MODE;
HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) |= USB_TXCSRH1_MODE;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY;
}
USBC_SelectActiveEp(old_ep_index);
@@ -908,8 +956,8 @@ int usbh_ep_intr_async_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t bufl
if (chan->in) {
HWREGB(USB_RXADDR_BASE(chan->ep_idx)) = chan->hport->dev_addr;
HWREGB(USB_RXTYPEx_BASE) = chan->ep_idx | chan->speed | USB_TXTYPE1_PROTO_INT;
HWREGB(USB_RXINTERVALx_BASE) = chan->interval;
HWREGB(USB_BASE + MUSB_IND_RXTYPE_OFFSET) = chan->ep_idx | chan->speed | USB_TXTYPE1_PROTO_INT;
HWREGB(USB_BASE + MUSB_IND_RXINTERVAL_OFFSET) = chan->interval;
if (chan->hport->parent == NULL) {
HWREGB(USB_RXHUBADDR_BASE(chan->ep_idx)) = 0;
HWREGB(USB_RXHUBPORT_BASE(chan->ep_idx)) = 0;
@@ -920,12 +968,12 @@ int usbh_ep_intr_async_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t bufl
chan->buffer = buffer;
chan->buflen = buflen;
HWREGB(USB_TXCSRHx_BASE) &= ~USB_TXCSRH1_MODE;
HWREGB(USB_RXCSRLx_BASE) = USB_RXCSRL1_REQPKT;
HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) &= ~USB_TXCSRH1_MODE;
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = USB_RXCSRL1_REQPKT;
} else {
HWREGB(USB_TXADDR_BASE(chan->ep_idx)) = chan->hport->dev_addr;
HWREGB(USB_TXTYPEx_BASE) = chan->ep_idx | chan->speed | USB_TXTYPE1_PROTO_INT;
HWREGB(USB_TXINTERVALx_BASE) = chan->interval;
HWREGB(USB_BASE + MUSB_IND_TXTYPE_OFFSET) = chan->ep_idx | chan->speed | USB_TXTYPE1_PROTO_INT;
HWREGB(USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) = chan->interval;
if (chan->hport->parent == NULL) {
HWREGB(USB_TXHUBADDR_BASE(chan->ep_idx)) = 0;
HWREGB(USB_TXHUBPORT_BASE(chan->ep_idx)) = 0;
@@ -941,9 +989,9 @@ int usbh_ep_intr_async_transfer(usbh_epinfo_t ep, uint8_t *buffer, uint32_t bufl
}
usb_musb_write_packet(chan->ep_idx, chan->buffer, buflen);
HWREGB(USB_TXCSRHx_BASE) &= ~USB_TXCSRH1_MODE;
HWREGB(USB_TXCSRHx_BASE) |= USB_TXCSRH1_MODE;
HWREGB(USB_TXCSRLx_BASE) = USB_TXCSRL1_TXRDY;
HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) &= ~USB_TXCSRH1_MODE;
HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) |= USB_TXCSRH1_MODE;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY;
}
USBC_SelectActiveEp(old_ep_index);
@@ -997,12 +1045,12 @@ int usb_ep_cancel(usbh_epinfo_t ep)
void handle_ep0(void)
{
uint8_t ep0_status = USB->CSRL0;
uint8_t ep0_status = HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET);
struct usb_musb_chan *chan;
chan = (struct usb_musb_chan *)g_usbhost.active_chan[0];
if (ep0_status & USB_CSRL0_ERROR) {
HWREGB(USB_TXCSRLx_BASE) &= ~USB_CSRL0_ERROR;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_ERROR;
usb_musb_fifo_flush(0);
usb_ep0_state = USB_EP0_STATE_SETUP;
chan->result = -EIO;
@@ -1010,7 +1058,7 @@ void handle_ep0(void)
}
if (ep0_status & USB_CSRL0_STALL) {
HWREGB(USB_TXCSRLx_BASE) &= ~USB_CSRL0_STALL;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_STALL;
usb_ep0_state = USB_EP0_STATE_SETUP;
chan->result = -EPERM;
goto chan_wait;
@@ -1019,30 +1067,31 @@ void handle_ep0(void)
case USB_EP0_STATE_SETUP:
break;
case USB_EP0_STATE_IN_DATA:
USB->CSRL0 = USB_RXCSRL1_REQPKT;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_RXCSRL1_REQPKT;
usb_ep0_state = USB_EP0_STATE_IN_DATA_C;
chan->xfrd += 8;
break;
case USB_EP0_STATE_IN_DATA_C:
if (USB->CSRL0 & USB_CSRL0_RXRDY) {
if (ep0_status & USB_CSRL0_RXRDY) {
uint32_t size = chan->buflen;
if (size > chan->mps) {
size = chan->mps;
}
size = MIN(size, USB->COUNT0);
size = MIN(size, HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET));
usb_musb_read_packet(0, chan->buffer, size);
USB->CSRL0 &= ~USB_CSRL0_RXRDY;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_RXRDY;
chan->buffer += size;
chan->buflen -= size;
chan->xfrd += size;
if ((size < chan->mps) || (chan->buflen == 0)) {
usb_ep0_state = USB_EP0_STATE_OUT_STATUS;
USB->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_STATUS;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_TXRDY | USB_CSRL0_STATUS);
} else {
USB->CSRL0 = USB_RXCSRL1_REQPKT;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_RXCSRL1_REQPKT;
}
}
break;
@@ -1052,7 +1101,7 @@ void handle_ep0(void)
goto chan_wait;
case USB_EP0_STATE_IN_STATUS_C:
if (ep0_status & (USB_CSRL0_RXRDY | USB_CSRL0_STATUS)) {
HWREGB(USB_TXCSRLx_BASE) &= ~(USB_CSRL0_RXRDY | USB_CSRL0_STATUS);
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~(USB_CSRL0_RXRDY | USB_CSRL0_STATUS);
}
usb_ep0_state = USB_EP0_STATE_SETUP;
@@ -1061,7 +1110,7 @@ void handle_ep0(void)
break;
case USB_EP0_STATE_IN_STATUS:
USB->CSRL0 = USB_CSRL0_REQPKT | USB_CSRL0_STATUS;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_REQPKT | USB_CSRL0_STATUS);
usb_ep0_state = USB_EP0_STATE_IN_STATUS_C;
chan->xfrd += 8;
break;
@@ -1080,11 +1129,10 @@ void handle_ep0(void)
chan->buflen -= size;
ep0_outlen = size;
if (size == chan->mps) {
USB->CSRL0 = USB_CSRL0_TXRDY;
} else {
USB->CSRL0 = USB_CSRL0_TXRDY;
usb_ep0_state = USB_EP0_STATE_IN_STATUS;
}
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_TXRDY;
}
break;
@@ -1109,9 +1157,11 @@ void USBH_IRQHandler(void)
uint8_t ep_idx;
uint8_t old_ep_idx;
is = USB->IS;
txis = USB->TXIS;
rxis = USB->RXIS;
is = HWREGB(USB_BASE + MUSB_IS_OFFSET);
txis = HWREGH(USB_BASE + MUSB_TXIS_OFFSET);
rxis = HWREGH(USB_BASE + MUSB_RXIS_OFFSET);
HWREGB(USB_BASE + MUSB_IS_OFFSET) = is;
old_ep_idx = USBC_GetActiveEp();
@@ -1120,7 +1170,6 @@ void USBH_IRQHandler(void)
g_usbhost.connected = true;
usbh_event_notify_handler(USBH_EVENT_CONNECTED, 1);
}
USB->IS = USB_IS_CONN;
}
if (is & USB_IS_DISCON) {
@@ -1137,38 +1186,31 @@ void USBH_IRQHandler(void)
usbh_event_notify_handler(USBH_EVENT_DISCONNECTED, 1);
}
USB->IS = USB_IS_DISCON;
}
if (is & USB_IS_SOF) {
USB->IS = USB_IS_SOF;
}
if (is & USB_IS_RESUME) {
USB->IS = USB_IS_RESUME;
}
if (is & USB_IS_SUSPEND) {
USB->IS = USB_IS_SUSPEND;
}
if (is & USB_IS_VBUSERR) {
USB->IS = USB_IS_VBUSERR;
}
if (is & USB_IS_SESREQ) {
USB->IS = USB_IS_SESREQ;
}
if (is & USB_IS_BABBLE) {
USB->IS = USB_IS_BABBLE;
}
txis &= USB->TXIE;
txis &= HWREGH(USB_BASE + MUSB_TXIE_OFFSET);
/* Handle EP0 interrupt */
if (txis & USB_TXIE_EP0) {
txis &= ~USB_TXIE_EP0;
USB->TXIS = USB_TXIE_EP0; // clear isr flag
HWREGH(USB_BASE + MUSB_TXIS_OFFSET) = USB_TXIE_EP0;
USBC_SelectActiveEp(0);
handle_ep0();
}
@@ -1176,25 +1218,25 @@ void USBH_IRQHandler(void)
while (txis) {
ep_idx = __builtin_ctz(txis);
txis &= ~(1 << ep_idx);
USB->TXIS = (1 << ep_idx); // clear isr flag
HWREGH(USB_BASE + MUSB_TXIS_OFFSET) = (1 << ep_idx);
chan = (struct usb_musb_chan *)g_usbhost.active_chan[ep_idx];
USBC_SelectActiveEp(ep_idx);
ep_csrl_status = HWREGB(USB_TXCSRLx_BASE);
ep_csrh_status = HWREGB(USB_TXCSRHx_BASE);
ep_csrl_status = HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET);
ep_csrh_status = HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET);
if (ep_csrl_status & USB_TXCSRL1_ERROR) {
HWREGB(USB_TXCSRLx_BASE) &= ~USB_TXCSRL1_ERROR;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_TXCSRL1_ERROR;
chan->result = -EIO;
usb_musb_chan_wakeup(chan);
} else if (ep_csrl_status & USB_TXCSRL1_NAKTO) {
HWREGB(USB_TXCSRLx_BASE) &= ~USB_TXCSRL1_NAKTO;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_TXCSRL1_NAKTO;
chan->result = -EBUSY;
usb_musb_chan_wakeup(chan);
} else if (ep_csrl_status & USB_TXCSRL1_STALL) {
HWREGB(USB_TXCSRLx_BASE) &= ~USB_TXCSRL1_STALL;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_TXCSRL1_STALL;
chan->result = -EPERM;
usb_musb_chan_wakeup(chan);
} else {
@@ -1213,34 +1255,34 @@ void USBH_IRQHandler(void)
usb_musb_chan_wakeup(chan);
} else {
usb_musb_write_packet(ep_idx, chan->buffer, size);
HWREGB(USB_TXCSRLx_BASE) = USB_TXCSRL1_TXRDY;
HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY;
}
}
}
rxis &= USB->RXIE;
rxis &= HWREGH(USB_BASE + MUSB_RXIE_OFFSET);
while (rxis) {
ep_idx = __builtin_ctz(rxis);
rxis &= ~(1 << ep_idx);
USB->RXIS = (1 << ep_idx); // clear isr flag
HWREGH(USB_BASE + MUSB_RXIS_OFFSET) = (1 << ep_idx); // clear isr flag
chan = (struct usb_musb_chan *)g_usbhost.active_chan[ep_idx];
USBC_SelectActiveEp(ep_idx);
ep_csrl_status = HWREGB(USB_RXCSRLx_BASE);
ep_csrh_status = HWREGB(USB_RXCSRHx_BASE);
ep_csrl_status = HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET);
ep_csrh_status = HWREGB(USB_BASE + MUSB_IND_RXCSRH_OFFSET);
if (ep_csrl_status & USB_RXCSRL1_ERROR) {
HWREGB(USB_RXCSRLx_BASE) &= ~USB_RXCSRL1_ERROR;
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~USB_RXCSRL1_ERROR;
chan->result = -EIO;
usb_musb_chan_wakeup(chan);
} else if (ep_csrl_status & USB_RXCSRL1_NAKTO) {
HWREGB(USB_RXCSRLx_BASE) &= ~USB_RXCSRL1_NAKTO;
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~USB_RXCSRL1_NAKTO;
chan->result = -EBUSY;
usb_musb_chan_wakeup(chan);
} else if (ep_csrl_status & USB_RXCSRL1_STALL) {
HWREGB(USB_RXCSRLx_BASE) &= ~USB_RXCSRL1_STALL;
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~USB_RXCSRL1_STALL;
chan->result = -EPERM;
usb_musb_chan_wakeup(chan);
} else if (ep_csrl_status & USB_RXCSRL1_RXRDY) {
@@ -1248,10 +1290,12 @@ void USBH_IRQHandler(void)
if (size > chan->mps) {
size = chan->mps;
}
size = MIN(size, HWREG(USB_RXCOUNTx_BASE));
size = MIN(size, HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET));
usb_musb_read_packet(ep_idx, chan->buffer, size);
HWREGB(USB_RXCSRLx_BASE) &= ~USB_RXCSRL1_RXRDY;
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~USB_RXCSRL1_RXRDY;
chan->buffer += size;
chan->buflen -= size;
chan->xfrd += size;
@@ -1259,7 +1303,7 @@ void USBH_IRQHandler(void)
chan->result = 0;
usb_musb_chan_wakeup(chan);
} else {
HWREGB(USB_RXCSRLx_BASE) = USB_RXCSRL1_REQPKT;
HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = USB_RXCSRL1_REQPKT;
}
}
}