diff --git a/demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/User/main.c b/demo/cdc_acm_template.c similarity index 53% rename from demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/User/main.c rename to demo/cdc_acm_template.c index 12fc0c13..d12b0a47 100644 --- a/demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/User/main.c +++ b/demo/cdc_acm_template.c @@ -1,15 +1,3 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : main.c -* Author : sakumisu -* Version : V1.0.0 -* Date : 2022/01/02 -* Description : cdc acm test. -*******************************************************************************/ - -/* - *@Note -*/ -#include "debug.h" #include "usbd_core.h" #include "usbd_cdc.h" @@ -28,7 +16,7 @@ /*!< global descriptor */ static const uint8_t cdc_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x02, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), CDC_ACM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, 0x02), /////////////////////////////////////// @@ -38,33 +26,35 @@ static const uint8_t cdc_descriptor[] = { /////////////////////////////////////// /// string1 descriptor /////////////////////////////////////// - 0x12, /* bLength */ + 0x14, /* bLength */ USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'B', 0x00, /* wcChar0 */ - 'o', 0x00, /* wcChar1 */ - 'u', 0x00, /* wcChar2 */ - 'f', 0x00, /* wcChar3 */ - 'f', 0x00, /* wcChar4 */ - 'a', 0x00, /* wcChar5 */ - 'l', 0x00, /* wcChar6 */ - 'o', 0x00, /* wcChar7 */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ /////////////////////////////////////// /// string2 descriptor /////////////////////////////////////// - 0x24, /* bLength */ + 0x26, /* bLength */ USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'B', 0x00, /* wcChar0 */ - 'o', 0x00, /* wcChar1 */ - 'u', 0x00, /* wcChar2 */ - 'f', 0x00, /* wcChar3 */ - 'f', 0x00, /* wcChar4 */ - 'a', 0x00, /* wcChar5 */ - 'l', 0x00, /* wcChar6 */ - 'o', 0x00, /* wcChar7 */ - ' ', 0x00, /* wcChar8 */ - 'C', 0x00, /* wcChar9 */ - 'D', 0x00, /* wcChar10 */ - 'C', 0x00, /* wcChar11 */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'C', 0x00, /* wcChar10 */ + 'D', 0x00, /* wcChar11 */ + 'C', 0x00, /* wcChar12 */ ' ', 0x00, /* wcChar13 */ 'D', 0x00, /* wcChar14 */ 'E', 0x00, /* wcChar15 */ @@ -78,13 +68,13 @@ static const uint8_t cdc_descriptor[] = { '2', 0x00, /* wcChar0 */ '0', 0x00, /* wcChar1 */ '2', 0x00, /* wcChar2 */ - '1', 0x00, /* wcChar3 */ - '0', 0x00, /* wcChar4 */ - '3', 0x00, /* wcChar5 */ - '1', 0x00, /* wcChar6 */ - '0', 0x00, /* wcChar7 */ - '0', 0x00, /* wcChar8 */ - '0', 0x00, /* wcChar9 */ + '2', 0x00, /* wcChar3 */ + '1', 0x00, /* wcChar4 */ + '2', 0x00, /* wcChar5 */ + '3', 0x00, /* wcChar6 */ + '4', 0x00, /* wcChar7 */ + '5', 0x00, /* wcChar8 */ + '6', 0x00, /* wcChar9 */ #ifdef CONFIG_USB_HS /////////////////////////////////////// /// device qualifier descriptor @@ -102,6 +92,7 @@ static const uint8_t cdc_descriptor[] = { #endif 0x00 }; + /*!< class */ usbd_class_t cdc_class; /*!< interface one */ @@ -114,8 +105,12 @@ void usbd_cdc_acm_out(uint8_t ep) { uint8_t data[64]; uint32_t read_byte; - + usbd_ep_read(ep, data, 64, &read_byte); + for (uint8_t i = 0; i < read_byte; i++) { + printf("%02x ", data[i]); + } + printf("\r\n"); printf("read len:%d\r\n", read_byte); usbd_ep_read(ep, NULL, 0, NULL); } @@ -137,7 +132,7 @@ usbd_endpoint_t cdc_in_ep = { }; /* function ------------------------------------------------------------------*/ -void cdc_init(void) +void cdc_acm_init(void) { usbd_desc_register(cdc_descriptor); /*!< add interface */ @@ -146,28 +141,9 @@ void cdc_init(void) /*!< interface add endpoint */ usbd_interface_add_endpoint(&cdc_data_intf, &cdc_out_ep); usbd_interface_add_endpoint(&cdc_data_intf, &cdc_in_ep); -} -void usb_dc_low_level_init(void) -{ - RCC_USBCLK48MConfig(RCC_USBCLK48MCLKSource_USBPHY); - RCC_USBHSPLLCLKConfig(RCC_HSBHSPLLCLKSource_HSE); - RCC_USBHSConfig(RCC_USBPLL_Div2); - RCC_USBHSPLLCKREFCLKConfig(RCC_USBHSPLLCKREFCLK_4M); - RCC_USBHSPHYPLLALIVEcmd(ENABLE); -#ifdef CONFIG_USB_HS - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBHS, ENABLE); -#else - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE); -#endif - - Delay_Us(100); -#ifndef CONFIG_USB_HS - //EXTEN->EXTEN_CTR |= EXTEN_USBD_PU_EN; - NVIC_EnableIRQ(OTG_FS_IRQn); -#else - NVIC_EnableIRQ( USBHS_IRQn ); -#endif + extern int usb_dc_init(void); + usb_dc_init(); } volatile uint8_t dtr_enable = 0; @@ -181,34 +157,10 @@ void usbd_cdc_acm_set_dtr(bool dtr) } } -/********************************************************************* - * @fn main - * - * @brief Main program. - * - * @return none - */ -int main(void) +void cdc_acm_data_send_with_dtr_test(void) { - Delay_Init(); - USART_Printf_Init(115200); - printf("SystemClk:%d\r\n", SystemCoreClock); - - Delay_Ms(10); - - cdc_init(); - extern int usb_dc_init(void); - usb_dc_init(); - - while (!usb_device_is_configured()) { + if (dtr_enable) { + uint8_t data_buffer[10] = { 0x31, 0x32, 0x33, 0x34, 0x35, 0x31, 0x32, 0x33, 0x34, 0x35 }; + usbd_ep_write(CDC_IN_EP, data_buffer, 10, NULL); } - while (1) { - if(dtr_enable) - { - uint8_t data_buffer[10] = { 0x31, 0x32, 0x33, 0x34, 0x35, 0x31, 0x32, 0x33, 0x34, 0x35 }; - usbd_ep_write(0x81, data_buffer, 10, NULL); - Delay_Ms(500); - } - - } -} +} \ No newline at end of file diff --git a/demo/ch32/ch32v307/SRC/Core/core_riscv.c b/demo/ch32/ch32v307/SRC/Core/core_riscv.c deleted file mode 100644 index 601a677b..00000000 --- a/demo/ch32/ch32v307/SRC/Core/core_riscv.c +++ /dev/null @@ -1,539 +0,0 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : core_riscv.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : RISC-V Core Peripheral Access Layer Source File -*******************************************************************************/ -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/********************************************************************* - * @fn __get_FFLAGS - * - * @brief Return the Floating-Point Accrued Exceptions - * - * @return fflags value - */ -uint32_t __get_FFLAGS(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "fflags" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_FFLAGS - * - * @brief Set the Floating-Point Accrued Exceptions - * - * @param value - set FFLAGS value - * - * @return none - */ -void __set_FFLAGS(uint32_t value) -{ - __ASM volatile ("csrw fflags, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_FRM - * - * @brief Return the Floating-Point Dynamic Rounding Mode - * - * @return frm value - */ -uint32_t __get_FRM(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "frm" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_FRM - * - * @brief Set the Floating-Point Dynamic Rounding Mode - * - * @param value - set frm value - * - * @return none - */ -void __set_FRM(uint32_t value) -{ - __ASM volatile ("csrw frm, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_FCSR - * - * @brief Return the Floating-Point Control and Status Register - * - * @return fcsr value - */ -uint32_t __get_FCSR(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "fcsr" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_FCSR - * - * @brief Set the Floating-Point Dynamic Rounding Mode - * - * @param value - set fcsr value - * - * @return none - */ -void __set_FCSR(uint32_t value) -{ - __ASM volatile ("csrw fcsr, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MSTATUS - * - * @brief Return the Machine Status Register - * - * @return mstatus value - */ -uint32_t __get_MSTATUS(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MSTATUS - * - * @brief Set the Machine Status Register - * - * @param value - set mstatus value - * - * @return none - */ -void __set_MSTATUS(uint32_t value) -{ - __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MISA - * - * @brief Return the Machine ISA Register - * - * @return misa value - */ -uint32_t __get_MISA(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MISA - * - * @brief Set the Machine ISA Register - * - * @param value - set misa value - * - * @return none - */ -void __set_MISA(uint32_t value) -{ - __ASM volatile ("csrw misa, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MIE - * - * @brief Return the Machine Interrupt Enable Register - * - * @return mie value - */ -uint32_t __get_MIE(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mie" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MISA - * - * @brief Set the Machine ISA Register - * - * @param value - set mie value - * - * @return none - */ -void __set_MIE(uint32_t value) -{ - __ASM volatile ("csrw mie, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MTVEC - * - * @brief Return the Machine Trap-Vector Base-Address Register - * - * @return mtvec value - */ -uint32_t __get_MTVEC(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MTVEC - * - * @brief Set the Machine Trap-Vector Base-Address Register - * - * @param value - set mtvec value - * - * @return none - */ -void __set_MTVEC(uint32_t value) -{ - __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MTVEC - * - * @brief Return the Machine Seratch Register - * - * @return mscratch value - */ -uint32_t __get_MSCRATCH(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MTVEC - * - * @brief Set the Machine Seratch Register - * - * @param value - set mscratch value - * - * @return none - */ -void __set_MSCRATCH(uint32_t value) -{ - __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MEPC - * - * @brief Return the Machine Exception Program Register - * - * @return mepc value - */ -uint32_t __get_MEPC(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MEPC - * - * @brief Set the Machine Exception Program Register - * - * @return mepc value - */ -void __set_MEPC(uint32_t value) -{ - __ASM volatile ("csrw mepc, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MCAUSE - * - * @brief Return the Machine Cause Register - * - * @return mcause value - */ -uint32_t __get_MCAUSE(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MEPC - * - * @brief Set the Machine Cause Register - * - * @return mcause value - */ -void __set_MCAUSE(uint32_t value) -{ - __ASM volatile ("csrw mcause, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MTVAL - * - * @brief Return the Machine Trap Value Register - * - * @return mtval value - */ -uint32_t __get_MTVAL(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MTVAL - * - * @brief Set the Machine Trap Value Register - * - * @return mtval value - */ -void __set_MTVAL(uint32_t value) -{ - __ASM volatile ("csrw mtval, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MIP - * - * @brief Return the Machine Interrupt Pending Register - * - * @return mip value - */ -uint32_t __get_MIP(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mip" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MIP - * - * @brief Set the Machine Interrupt Pending Register - * - * @return mip value - */ -void __set_MIP(uint32_t value) -{ - __ASM volatile ("csrw mip, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MCYCLE - * - * @brief Return Lower 32 bits of Cycle counter - * - * @return mcycle value - */ -uint32_t __get_MCYCLE(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mcycle" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MCYCLE - * - * @brief Set Lower 32 bits of Cycle counter - * - * @return mcycle value - */ -void __set_MCYCLE(uint32_t value) -{ - __ASM volatile ("csrw mcycle, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MCYCLEH - * - * @brief Return Upper 32 bits of Cycle counter - * - * @return mcycleh value - */ -uint32_t __get_MCYCLEH(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mcycleh" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MCYCLEH - * - * @brief Set Upper 32 bits of Cycle counter - * - * @return mcycleh value - */ -void __set_MCYCLEH(uint32_t value) -{ - __ASM volatile ("csrw mcycleh, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MINSTRET - * - * @brief Return Lower 32 bits of Instructions-retired counter - * - * @return mcause value - */ -uint32_t __get_MINSTRET(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "minstret" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MINSTRET - * - * @brief Set Lower 32 bits of Instructions-retired counter - * - * @return minstret value - */ -void __set_MINSTRET(uint32_t value) -{ - __ASM volatile ("csrw minstret, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MINSTRETH - * - * @brief Return Upper 32 bits of Instructions-retired counter - * - * @return minstreth value - */ -uint32_t __get_MINSTRETH(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "minstreth" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __set_MINSTRETH - * - * @brief Set Upper 32 bits of Instructions-retired counter - * - * @return minstreth value - */ -void __set_MINSTRETH(uint32_t value) -{ - __ASM volatile ("csrw minstreth, %0" : : "r" (value) ); -} - -/********************************************************************* - * @fn __get_MVENDORID - * - * @brief Return Vendor ID Register - * - * @return mvendorid value - */ -uint32_t __get_MVENDORID(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __get_MARCHID - * - * @brief Return Machine Architecture ID Register - * - * @return marchid value - */ -uint32_t __get_MARCHID(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __get_MIMPID - * - * @brief Return Machine Implementation ID Register - * - * @return mimpid value - */ -uint32_t __get_MIMPID(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); - return (result); -} - -/********************************************************************* - * @fn __get_MHARTID - * - * @brief Return Hart ID Register - * - * @return mhartid value - */ -uint32_t __get_MHARTID(void) -{ - uint32_t result; - - __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); - return (result); -} - - - diff --git a/demo/ch32/ch32v307/SRC/Peripheral/src/ch32v30x_gpio.c b/demo/ch32/ch32v307/SRC/Peripheral/src/ch32v30x_gpio.c deleted file mode 100644 index 5109bd8a..00000000 --- a/demo/ch32/ch32v307/SRC/Peripheral/src/ch32v30x_gpio.c +++ /dev/null @@ -1,568 +0,0 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_gpio.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the GPIO firmware functions. -*******************************************************************************/ -#include "ch32v30x_gpio.h" -#include "ch32v30x_rcc.h" - -/* MASK */ -#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) -#define LSB_MASK ((uint16_t)0xFFFF) -#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) -#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) -#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) -#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) - - -/********************************************************************* - * @fn GPIO_DeInit - * - * @brief Deinitializes the GPIOx peripheral registers to their default - * reset values. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @return none - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - if (GPIOx == GPIOA) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); - } - else if (GPIOx == GPIOB) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); - } - else if (GPIOx == GPIOC) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); - } - else if (GPIOx == GPIOD) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); - } - else if (GPIOx == GPIOE) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); - } -} - -/********************************************************************* - * @fn GPIO_AFIODeInit - * - * @brief Deinitializes the Alternate Functions (remap, event control - * and EXTI configuration) registers to their default reset values. - * - * @return none - */ -void GPIO_AFIODeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); -} - -/********************************************************************* - * @fn GPIO_Init - * - * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO peripheral. - * - * @return none - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; - uint32_t tmpreg = 0x00, pinmask = 0x00; - - currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); - - if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) - { - currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; - } - - if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) - { - tmpreg = GPIOx->CFGLR; - - for (pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if (currentpin == pos) - { - pos = pinpos << 2; - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - tmpreg |= (currentmode << pos); - - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BCR = (((uint32_t)0x01) << pinpos); - } - else - { - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSHR = (((uint32_t)0x01) << pinpos); - } - } - } - } - GPIOx->CFGLR = tmpreg; - } - - if (GPIO_InitStruct->GPIO_Pin > 0x00FF) - { - tmpreg = GPIOx->CFGHR; - - for (pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = (((uint32_t)0x01) << (pinpos + 0x08)); - currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); - - if (currentpin == pos) - { - pos = pinpos << 2; - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - tmpreg |= (currentmode << pos); - - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - } - } - GPIOx->CFGHR = tmpreg; - } -} - -/********************************************************************* - * @fn GPIO_StructInit - * - * @brief Fills each GPIO_InitStruct member with its default - * - * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure - * which will be initialized. - * - * @return none - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; -} - -/********************************************************************* - * @fn GPIO_ReadInputDataBit - * - * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @param GPIO_Pin - specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * - * @return The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - if ((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn GPIO_ReadInputData - * - * @brief Reads the specified GPIO input data port. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @return The output port pin value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - return ((uint16_t)GPIOx->INDR); -} - -/********************************************************************* - * @fn GPIO_ReadOutputDataBit - * - * @brief Reads the specified output data port bit. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - if ((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn GPIO_ReadOutputData - * - * @brief Reads the specified GPIO output data port. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * - * @return GPIO output port pin value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - return ((uint16_t)GPIOx->OUTDR); -} - -/********************************************************************* - * @fn GPIO_SetBits - * - * @brief Sets the selected data port bits. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - GPIOx->BSHR = GPIO_Pin; -} - -/********************************************************************* - * @fn GPIO_ResetBits - * - * @brief Clears the selected data port bits. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - GPIOx->BCR = GPIO_Pin; -} - -/********************************************************************* - * @fn GPIO_WriteBit - * - * @brief Sets or clears the selected data port bit. - * - * @param GPIO_Pin - specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * BitVal - specifies the value to be written to the selected bit. - * Bit_SetL - to clear the port pin. - * Bit_SetH - to set the port pin. - * - * @return none - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - if (BitVal != Bit_RESET) - { - GPIOx->BSHR = GPIO_Pin; - } - else - { - GPIOx->BCR = GPIO_Pin; - } -} - -/********************************************************************* - * @fn GPIO_Write - * - * @brief Writes data to the specified GPIO data port. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * PortVal - specifies the value to be written to the port output data register. - * - * @return none - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - GPIOx->OUTDR = PortVal; -} - -/********************************************************************* - * @fn GPIO_PinLockConfig - * - * @brief Locks GPIO Pins configuration registers. - * - * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. - * GPIO_Pin - specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * - * @return none - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint32_t tmp = 0x00010000; - - tmp |= GPIO_Pin; - GPIOx->LCKR = tmp; - GPIOx->LCKR = GPIO_Pin; - GPIOx->LCKR = tmp; - tmp = GPIOx->LCKR; - tmp = GPIOx->LCKR; -} - -/********************************************************************* - * @fn GPIO_EventOutputConfig - * - * @brief Selects the GPIO pin used as Event output. - * - * @param GPIO_PortSource - selects the GPIO port to be used as source - * for Event output. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). - * GPIO_PinSource - specifies the pin for the Event output. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * - * @return none - */ -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmpreg = 0x00; - - tmpreg = AFIO->ECR; - tmpreg &= ECR_PORTPINCONFIG_MASK; - tmpreg |= (uint32_t)GPIO_PortSource << 0x04; - tmpreg |= GPIO_PinSource; - AFIO->ECR = tmpreg; -} - -/********************************************************************* - * @fn GPIO_EventOutputCmd - * - * @brief Enables or disables the Event Output. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void GPIO_EventOutputCmd(FunctionalState NewState) -{ - if(NewState) - { - AFIO->ECR |= (1<<7); - } - else - { - AFIO->ECR &= ~(1<<7); - } -} - -/********************************************************************* - * @fn GPIO_PinRemapConfig - * - * @brief Changes the mapping of the specified pin. - * - * @param GPIO_Remap - selects the pin to remap. - * GPIO_Remap_SPI1 - SPI1 Alternate Function mapping - * GPIO_Remap_I2C1 - I2C1 Alternate Function mapping - * GPIO_Remap_USART1 - USART1 Alternate Function mapping - * GPIO_Remap_USART2 - USART2 Alternate Function mapping - * GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping - * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping - * GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping - * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping - * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping - * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping - * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping - * GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping - * GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping - * GPIO_Remap_TIM4 - TIM4 Alternate Function mapping - * GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping - * GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping - * GPIO_Remap_PD01 - PD01 Alternate Function mapping - * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping - * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping - * GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping - * GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping - * GPIO_Remap_ETH - Ethernet remapping - * GPIO_Remap_CAN2 - CAN2 remapping - * GPIO_Remap_MII_RMII_SEL - MII or RMII selection - * GPIO_Remap_SWJ_NoJTRST - Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST - * GPIO_Remap_SWJ_JTAGDisable - JTAG-DP Disabled and SW-DP Enabled - * GPIO_Remap_SWJ_Disable - Full SWJ Disabled (JTAG-DP + SW-DP) - * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected - * to TIM2 Internal Trigger 1 for calibration - * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) - * GPIO_Remap_TIM8 - TIM8 Alternate Function mapping - * GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping - * GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping - * GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping - * GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping - * GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping - * GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping - * GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping - * GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping - * GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping - * GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping - * GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping - * GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping - * GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping - * GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping - * GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping - * GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) -{ - uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; - - if((GPIO_Remap & 0x80000000) == 0x80000000) - { - tmpreg = AFIO->PCFR2; - } - else - { - tmpreg = AFIO->PCFR1; - } - - tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; - tmp = GPIO_Remap & LSB_MASK; - - /* Clear bit */ - if((GPIO_Remap & 0x80000000) == 0x80000000){ /* PCFR2 */ - if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */ - { - tmp1 = ((uint32_t)0x03) << (tmpmask+0x10); - tmpreg &= ~tmp1; - } - else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ - { - tmp1 = ((uint32_t)0x03) << tmpmask; - tmpreg &= ~tmp1; - } - else /* [31:0] 1bit */ - { - tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); - } - - } - else{ /* PCFR1 */ - if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SWD_JTAG */ - { - tmpreg &= DBGAFR_SWJCFG_MASK; - AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; - } - else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ - { - tmp1 = ((uint32_t)0x03) << tmpmask; - tmpreg &= ~tmp1; - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - else /* [31:0] 1bit */ - { - tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - } - - /* Set bit */ - if (NewState != DISABLE) - { - tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); - } - - if((GPIO_Remap & 0x80000000) == 0x80000000) - { - AFIO->PCFR2 = tmpreg; - } - else - { - AFIO->PCFR1 = tmpreg; - } -} - -/********************************************************************* - * @fn GPIO_EXTILineConfig - * - * @brief Selects the GPIO pin used as EXTI Line. - * - * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). - * GPIO_PinSource - specifies the EXTI line to be configured. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * - * @return none - */ -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmp = 0x00; - - tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); - AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; - AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); -} - -/********************************************************************* - * @fn GPIO_ETH_MediaInterfaceConfig - * - * @brief Selects the Ethernet media interface. - * - * @param GPIO_ETH_MediaInterface - specifies the Media Interface mode. - * GPIO_ETH_MediaInterface_MII - MII mode - * GPIO_ETH_MediaInterface_RMII - RMII mode - * - * @return none - */ -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) -{ - if(GPIO_ETH_MediaInterface) - { - AFIO->PCFR1 |= (1<<23); - } - else - { - AFIO->PCFR1 &= ~(1<<23); - } -} - - - - diff --git a/demo/ch32/ch32v307/SRC/Peripheral/src/ch32v30x_rcc.c b/demo/ch32/ch32v307/SRC/Peripheral/src/ch32v30x_rcc.c deleted file mode 100644 index 4778acee..00000000 --- a/demo/ch32/ch32v307/SRC/Peripheral/src/ch32v30x_rcc.c +++ /dev/null @@ -1,1391 +0,0 @@ -/********************************** (C) COPYRIGHT ******************************* -* File Name : ch32v30x_rcc.c -* Author : WCH -* Version : V1.0.0 -* Date : 2021/06/06 -* Description : This file provides all the RCC firmware functions. -*******************************************************************************/ -#include "ch32v30x_rcc.h" - -/* RCC registers bit address in the alias region */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) - -/* BDCTLR Register */ -#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) - -/* RCC registers bit mask */ - -/* CTLR register bit mask */ -#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) -#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) -#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) -#define CTLR_HSEON_Set ((uint32_t)0x00010000) -#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) - -#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) /* 103 */ -#define CFGR0_PLL_Mask_1 ((uint32_t)0xFFC2FFFF) /* 107 */ - -#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) -#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) -#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) -#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) -#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) -#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) -#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) -#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) -#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) -#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) -#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) -#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) -#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000) - -/* RSTSCKR register bit mask */ -#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) - -/* CFGR2 register bit mask */ -#define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) -#define CFGR2_PREDIV1 ((uint32_t)0x0000000F) -#define CFGR2_PREDIV2 ((uint32_t)0x000000F0) -#define CFGR2_PLL2MUL ((uint32_t)0x00000F00) -#define CFGR2_PLL3MUL ((uint32_t)0x0000F000) - -/* RCC Flag Mask */ -#define FLAG_Mask ((uint8_t)0x1F) - -/* INTR register byte 2 (Bits[15:8]) base address */ -#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) - -/* INTR register byte 3 (Bits[23:16]) base address */ -#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) - -/* CFGR0 register byte 4 (Bits[31:24]) base address */ -#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) - -/* BDCTLR register base address */ -#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) - - -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; - -/********************************************************************* - * @fn RCC_DeInit - * - * @brief Resets the RCC clock configuration to the default reset state. - * - * @return none - */ -void RCC_DeInit(void) -{ - RCC->CTLR |= (uint32_t)0x00000001; - RCC->CFGR0 &= (uint32_t)0xF8FF0000; - RCC->CTLR &= (uint32_t)0xFEF6FFFF; - RCC->CTLR &= (uint32_t)0xFFFBFFFF; - RCC->CFGR0 &= (uint32_t)0xFF80FFFF; - RCC->INTR = 0x009F0000; -} - -/********************************************************************* - * @fn RCC_HSEConfig - * - * @brief Configures the External High Speed oscillator (HSE). - * - * @param RCC_HSE - - * RCC_HSE_OFF - HSE oscillator OFF. - * RCC_HSE_ON - HSE oscillator ON. - * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. - * - * @return none - */ -void RCC_HSEConfig(uint32_t RCC_HSE) -{ - RCC->CTLR &= CTLR_HSEON_Reset; - RCC->CTLR &= CTLR_HSEBYP_Reset; - - switch(RCC_HSE) - { - case RCC_HSE_ON: - RCC->CTLR |= CTLR_HSEON_Set; - break; - - case RCC_HSE_Bypass: - RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; - break; - - default: - break; - } -} - -/********************************************************************* - * @fn RCC_WaitForHSEStartUp - * - * @brief Waits for HSE start-up. - * - * @return SUCCESS - HSE oscillator is stable and ready to use. - * ERROR - HSE oscillator not yet ready. - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - - ErrorStatus status = ERROR; - FlagStatus HSEStatus = RESET; - - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - - return (status); -} - -/********************************************************************* - * @fn RCC_AdjustHSICalibrationValue - * - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * - * @param HSICalibrationValue - specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * - * @return none - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CTLR; - tmpreg &= CTLR_HSITRIM_Mask; - tmpreg |= (uint32_t)HSICalibrationValue << 3; - RCC->CTLR = tmpreg; -} - -/********************************************************************* - * @fn RCC_HSICmd - * - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_HSICmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1<<0); - } - else{ - RCC->CTLR &= ~(1<<0); - } -} - -/********************************************************************* - * @fn RCC_PLLConfig - * - * @brief Configures the PLL clock source and multiplication factor. - * - * @param RCC_PLLSource - specifies the PLL entry clock source. - * RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2 - * selected as PLL clock entry. - * RCC_PLLSource_PREDIV1 - PREDIV1 clock selected as PLL clock - * entry. - * RCC_PLLMul - specifies the PLL multiplication factor. - * This parameter can be RCC_PLLMul_x where x:[2,16]. - * For CH32V307 - - * RCC_PLLMul_18_EXTEN - * RCC_PLLMul_3_EXTEN - * RCC_PLLMul_4_EXTEN - * RCC_PLLMul_5_EXTEN - * RCC_PLLMul_6_EXTEN - * RCC_PLLMul_7_EXTEN - * RCC_PLLMul_8_EXTEN - * RCC_PLLMul_9_EXTEN - * RCC_PLLMul_10_EXTEN - * RCC_PLLMul_11_EXTEN - * RCC_PLLMul_12_EXTEN - * RCC_PLLMul_13_EXTEN - * RCC_PLLMul_14_EXTEN - * RCC_PLLMul_6_5_EXTEN - * RCC_PLLMul_15_EXTEN - * RCC_PLLMul_16_EXTEN - * For other CH32V30x - - * RCC_PLLMul_2 - * RCC_PLLMul_3 - * RCC_PLLMul_4 - * RCC_PLLMul_5 - * RCC_PLLMul_6 - * RCC_PLLMul_7 - * RCC_PLLMul_8 - * RCC_PLLMul_9 - * RCC_PLLMul_10 - * RCC_PLLMul_11 - * RCC_PLLMul_12 - * RCC_PLLMul_13 - * RCC_PLLMul_14 - * RCC_PLLMul_15 - * RCC_PLLMul_16 - * RCC_PLLMul_18 - * - * @return none - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - - if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){ /* for other CH32V30x */ - tmpreg &= CFGR0_PLL_Mask; - } - else{ /* for CH32V307 */ - tmpreg &= CFGR0_PLL_Mask_1; - } - - tmpreg |= RCC_PLLSource | RCC_PLLMul; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PLLCmd - * - * @brief Enables or disables the PLL. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1<<24); - } - else{ - RCC->CTLR &= ~(1<<24); - } -} - -/********************************************************************* - * @fn RCC_SYSCLKConfig - * - * @brief Configures the system clock (SYSCLK). - * - * @param RCC_SYSCLKSource - specifies the clock source used as system clock. - * RCC_SYSCLKSource_HSI - HSI selected as system clock. - * RCC_SYSCLKSource_HSE - HSE selected as system clock. - * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. - * - * @return none - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_SW_Mask; - tmpreg |= RCC_SYSCLKSource; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_GetSYSCLKSource - * - * @brief Returns the clock source used as system clock. - * - * @return 0x00 - HSI used as system clock. - * 0x04 - HSE used as system clock. - * 0x08 - PLL used as system clock. - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); -} - -/********************************************************************* - * @fn RCC_HCLKConfig - * - * @brief Configures the AHB clock (HCLK). - * - * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. - * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. - * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. - * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. - * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. - * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. - * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. - * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. - * RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512. - * - * @return none - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_HPRE_Reset_Mask; - tmpreg |= RCC_SYSCLK; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PCLK1Config - * - * @brief Configures the Low Speed APB clock (PCLK1). - * - * @param RCC_HCLK - defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * RCC_HCLK_Div1 - APB1 clock = HCLK. - * RCC_HCLK_Div2 - APB1 clock = HCLK/2. - * RCC_HCLK_Div4 - APB1 clock = HCLK/4. - * RCC_HCLK_Div8 - APB1 clock = HCLK/8. - * RCC_HCLK_Div16 - APB1 clock = HCLK/16. - * - * @return none - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_PPRE1_Reset_Mask; - tmpreg |= RCC_HCLK; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PCLK2Config - * - * @brief Configures the High Speed APB clock (PCLK2). - * - * @param RCC_HCLK - defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * RCC_HCLK_Div1 - APB1 clock = HCLK. - * RCC_HCLK_Div2 - APB1 clock = HCLK/2. - * RCC_HCLK_Div4 - APB1 clock = HCLK/4. - * RCC_HCLK_Div8 - APB1 clock = HCLK/8. - * RCC_HCLK_Div16 - APB1 clock = HCLK/16. - * - * @return none - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_PPRE2_Reset_Mask; - tmpreg |= RCC_HCLK << 3; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_ITConfig - * - * @brief Enables or disables the specified RCC interrupts. - * - * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_LSERDY - LSE ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - *(__IO uint8_t *) INTR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - *(__IO uint8_t *) INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/********************************************************************* - * @fn RCC_ADCCLKConfig - * - * @brief Configures the ADC clock (ADCCLK). - * - * @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from - * the APB2 clock (PCLK2). - * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. - * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. - * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. - * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. - * - * @return none - */ -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR0; - tmpreg &= CFGR0_ADCPRE_Reset_Mask; - tmpreg |= RCC_PCLK2; - RCC->CFGR0 = tmpreg; -} - -/********************************************************************* - * @fn RCC_LSEConfig - * - * @brief Configures the External Low Speed oscillator (LSE). - * - * @param RCC_LSE - specifies the new state of the LSE. - * RCC_LSE_OFF - LSE oscillator OFF. - * RCC_LSE_ON - LSE oscillator ON. - * RCC_LSE_Bypass - LSE oscillator bypassed with external clock. - * - * @return none - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF; - *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF; - - switch(RCC_LSE) - { - case RCC_LSE_ON: - *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_ON; - break; - - case RCC_LSE_Bypass: - *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - - default: - break; - } -} - -/********************************************************************* - * @fn RCC_LSICmd - * - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_LSICmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->RSTSCKR |= (1<<0); - } - else{ - RCC->RSTSCKR &= ~(1<<0); - } -} - -/********************************************************************* - * @fn RCC_RTCCLKConfig - * - * @brief Once the RTC clock is selected it can't be changed unless the Backup domain is reset. - * - * @param RCC_RTCCLKSource - specifies the RTC clock source. - * RCC_RTCCLKSource_LSE - LSE selected as RTC clock. - * RCC_RTCCLKSource_LSI - LSI selected as RTC clock. - * RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock. - * - * @return none - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - RCC->BDCTLR |= RCC_RTCCLKSource; -} - -/********************************************************************* - * @fn RCC_RTCCLKCmd - * - * @brief This function must be used only after the RTC clock was selected - * using the RCC_RTCCLKConfig function. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->BDCTLR |= (1<<15); - } - else{ - RCC->BDCTLR &= ~(1<<15); - } -} - -/********************************************************************* - * @fn RCC_GetClocksFreq - * - * @brief The result of this function could be not correct when using - * fractional value for HSE crystal. - * - * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @return none - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0, Pll_6_5 = 0; - - tmp = RCC->CFGR0 & CFGR0_SWS_Mask; - - switch (tmp) - { - case 0x00: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - - case 0x04: - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - - case 0x08: - pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask; - pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; - - pllmull = ( pllmull >> 18) + 2; - - if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){ /* for other CH32V30x */ - if(pllmull == 17) pllmull = 18; - } - else{ /* for CH32V307 */ - if(pllmull == 2) pllmull = 18; - if(pllmull == 15){ - pllmull = 13; /* *6.5 */ - Pll_6_5 = 1; - } - if(pllmull == 16) pllmull = 15; - if(pllmull == 17) pllmull = 16; - } - - - if (pllsource == 0x00) - { - if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){ - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE) * pllmull; - } - else{ - RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >>1) * pllmull; - } - } - else - { - if ((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET) - { - RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; - } - else - { - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; - } - } - - if(Pll_6_5 == 1) RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency / 2); - - break; - - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - - tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask; - tmp = tmp >> 8; - presc = APBAHBPrescTable[tmp]; - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask; - tmp = tmp >> 11; - presc = APBAHBPrescTable[tmp]; - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; - tmp = tmp >> 14; - presc = ADCPrescTable[tmp]; - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; -} - -/********************************************************************* - * @fn RCC_AHBPeriphClockCmd - * - * @brief Enables or disables the AHB peripheral clock. - * - * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. - * RCC_AHBPeriph_DMA1. - * RCC_AHBPeriph_DMA2. - * RCC_AHBPeriph_SRAM. - * RCC_AHBPeriph_CRC. - * RCC_AHBPeriph_FSMC - * RCC_AHBPeriph_RNG - * RCC_AHBPeriph_SDIO - * RCC_AHBPeriph_USBHS - * RCC_AHBPeriph_OTG_FS - * RCC_AHBPeriph_DVP - * RCC_AHBPeriph_ETH_MAC - * RCC_AHBPeriph_ETH_MAC_Tx - * RCC_AHBPeriph_ETH_MAC_Rx - * NewState: ENABLE or DISABLE. - * - * @return none - */ -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->AHBPCENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBPCENR &= ~RCC_AHBPeriph; - } -} - -/********************************************************************* - * @fn RCC_APB2PeriphClockCmd - * - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * - * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. - * RCC_APB2Periph_AFIO. - * RCC_APB2Periph_GPIOA. - * RCC_APB2Periph_GPIOB. - * RCC_APB2Periph_GPIOC. - * RCC_APB2Periph_GPIOD. - * RCC_APB2Periph_GPIOE - * RCC_APB2Periph_ADC1. - * RCC_APB2Periph_ADC2 - * RCC_APB2Periph_TIM1. - * RCC_APB2Periph_SPI1. - * RCC_APB2Periph_TIM8 - * RCC_APB2Periph_USART1. - * RCC_APB2Periph_TIM9 - * RCC_APB2Periph_TIM10 - * NewState - ENABLE or DISABLE - * - * @return none - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->APB2PCENR |= RCC_APB2Periph; - } - else - { - RCC->APB2PCENR &= ~RCC_APB2Periph; - } -} - -/********************************************************************* - * @fn RCC_APB1PeriphClockCmd - * - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * - * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. - * RCC_APB1Periph_TIM2. - * RCC_APB1Periph_TIM3. - * RCC_APB1Periph_TIM4. - * RCC_APB1Periph_TIM5 - * RCC_APB1Periph_TIM6 - * RCC_APB1Periph_TIM7 - * RCC_APB1Periph_UART6 - * RCC_APB1Periph_UART7 - * RCC_APB1Periph_UART8 - * RCC_APB1Periph_WWDG. - * RCC_APB1Periph_SPI2. - * RCC_APB1Periph_SPI3. - * RCC_APB1Periph_USART2. - * RCC_APB1Periph_USART3. - * RCC_APB1Periph_UART4 - * RCC_APB1Periph_UART5 - * RCC_APB1Periph_I2C1. - * RCC_APB1Periph_I2C2. - * RCC_APB1Periph_USB. - * RCC_APB1Periph_CAN1. - * RCC_APB1Periph_BKP. - * RCC_APB1Periph_PWR. - * RCC_APB1Periph_DAC. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->APB1PCENR |= RCC_APB1Periph; - } - else - { - RCC->APB1PCENR &= ~RCC_APB1Periph; - } -} - -/********************************************************************* - * @fn RCC_APB2PeriphResetCmd - * - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * - * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. - * RCC_APB2Periph_AFIO. - * RCC_APB2Periph_GPIOA. - * RCC_APB2Periph_GPIOB. - * RCC_APB2Periph_GPIOC. - * RCC_APB2Periph_GPIOD. - * RCC_APB2Periph_GPIOE - * RCC_APB2Periph_ADC1. - * RCC_APB2Periph_ADC2 - * RCC_APB2Periph_TIM1. - * RCC_APB2Periph_SPI1. - * RCC_APB2Periph_TIM8 - * RCC_APB2Periph_USART1. - * RCC_APB2Periph_TIM9 - * RCC_APB2Periph_TIM10 - * NewState - ENABLE or DISABLE - * - * @return none - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->APB2PRSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2PRSTR &= ~RCC_APB2Periph; - } -} - -/********************************************************************* - * @fn RCC_APB1PeriphResetCmd - * - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * - * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. - * RCC_APB1Periph_TIM2. - * RCC_APB1Periph_TIM3. - * RCC_APB1Periph_TIM4. - * RCC_APB1Periph_TIM5 - * RCC_APB1Periph_TIM6 - * RCC_APB1Periph_TIM7 - * RCC_APB1Periph_UART6 - * RCC_APB1Periph_UART7 - * RCC_APB1Periph_UART8 - * RCC_APB1Periph_WWDG. - * RCC_APB1Periph_SPI2. - * RCC_APB1Periph_SPI3. - * RCC_APB1Periph_USART2. - * RCC_APB1Periph_USART3. - * RCC_APB1Periph_UART4 - * RCC_APB1Periph_UART5 - * RCC_APB1Periph_I2C1. - * RCC_APB1Periph_I2C2. - * RCC_APB1Periph_USB. - * RCC_APB1Periph_CAN1. - * RCC_APB1Periph_BKP. - * RCC_APB1Periph_PWR. - * RCC_APB1Periph_DAC. - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->APB1PRSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1PRSTR &= ~RCC_APB1Periph; - } -} - -/********************************************************************* - * @fn RCC_BackupResetCmd - * - * @brief Forces or releases the Backup domain reset. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->BDCTLR |= (1<<16); - } - else{ - RCC->BDCTLR &= ~(1<<16); - } -} - -/********************************************************************* - * @fn RCC_ClockSecuritySystemCmd - * - * @brief Enables or disables the Clock Security System. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1<<19); - } - else{ - RCC->CTLR &= ~(1<<19); - } -} - -/********************************************************************* - * @fn RCC_MCOConfig - * - * @brief Selects the clock source to output on MCO pin. - * - * @param RCC_MCO - specifies the clock source to output. - * RCC_MCO_NoClock - No clock selected. - * RCC_MCO_SYSCLK - System clock selected. - * RCC_MCO_HSI - HSI oscillator clock selected. - * RCC_MCO_HSE - HSE oscillator clock selected. - * RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected. - * RCC_MCO_PLL2CLK - PLL2 clock selected - * RCC_MCO_PLL3CLK_Div2 - PLL3 clock divided by 2 selected - * RCC_MCO_XT1 - External 3-25 MHz oscillator clock selected - * RCC_MCO_PLL3CLK - PLL3 clock selected - * - * @return none - */ -void RCC_MCOConfig(uint8_t RCC_MCO) -{ - *(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO; -} - -/********************************************************************* - * @fn RCC_GetFlagStatus - * - * @brief Checks whether the specified RCC flag is set or not. - * - * @param RCC_FLAG - specifies the flag to check. - * RCC_FLAG_HSIRDY - HSI oscillator clock ready. - * RCC_FLAG_HSERDY - HSE oscillator clock ready. - * RCC_FLAG_PLLRDY - PLL clock ready. - * RCC_FLAG_PLL2RDY - PLL2 clock ready. - * RCC_FLAG_PLL3RDY - PLL3 clock ready. - * RCC_FLAG_LSERDY - LSE oscillator clock ready. - * RCC_FLAG_LSIRDY - LSI oscillator clock ready. - * RCC_FLAG_PINRST - Pin reset. - * RCC_FLAG_PORRST - POR/PDR reset. - * RCC_FLAG_SFTRST - Software reset. - * RCC_FLAG_IWDGRST - Independent Watchdog reset. - * RCC_FLAG_WWDGRST - Window Watchdog reset. - * RCC_FLAG_LPWRRST - Low Power reset. - * - * @return FlagStatus - SET or RESET. - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - - FlagStatus bitstatus = RESET; - tmp = RCC_FLAG >> 5; - - if (tmp == 1) - { - statusreg = RCC->CTLR; - } - else if (tmp == 2) - { - statusreg = RCC->BDCTLR; - } - else - { - statusreg = RCC->RSTSCKR; - } - - tmp = RCC_FLAG & FLAG_Mask; - - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RCC_ClearFlag - * - * @brief Clears the RCC reset flags. - * - * @return none - */ -void RCC_ClearFlag(void) -{ - RCC->RSTSCKR |= RSTSCKR_RMVF_Set; -} - -/********************************************************************* - * @fn RCC_GetITStatus - * - * @brief Checks whether the specified RCC interrupt has occurred or not. - * - * @param RCC_IT - specifies the RCC interrupt source to check. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_LSERDY - LSE ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * RCC_IT_PLL2RDY - PLL2 ready interrupt. - * RCC_IT_PLL3RDY - PLL3 ready interrupt. - * RCC_IT_CSS - Clock Security System interrupt. - * - * @return ITStatus - SET or RESET. - */ - -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - - if ((RCC->INTR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/********************************************************************* - * @fn RCC_ClearITPendingBit - * - * @brief Clears the RCC's interrupt pending bits. - * - * @param RCC_IT - specifies the interrupt pending bit to clear. - * RCC_IT_LSIRDY - LSI ready interrupt. - * RCC_IT_LSERDY - LSE ready interrupt. - * RCC_IT_HSIRDY - HSI ready interrupt. - * RCC_IT_HSERDY - HSE ready interrupt. - * RCC_IT_PLLRDY - PLL ready interrupt. - * RCC_IT_PLL2RDY - PLL2 ready interrupt. - * RCC_IT_PLL3RDY - PLL3 ready interrupt. - * RCC_IT_CSS - Clock Security System interrupt. - * - * @return none - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - *(__IO uint8_t *) INTR_BYTE3_ADDRESS = RCC_IT; -} - -/********************************************************************* - * @fn RCC_PREDIV1Config - * - * @brief Configures the PREDIV1 division factor. - * - * @param RCC_PREDIV1_Source - specifies the PREDIV1 clock source. - * RCC_PREDIV1_Source_HSE - HSE selected as PREDIV1 clock - * RCC_PREDIV1_Source_PLL2 - PLL2 selected as PREDIV1 clock - * RCC_PREDIV1_Div - specifies the PREDIV1 clock division factor. - * This parameter can be RCC_PREDIV1_Divx where x[1,16] - * - * @return none - */ -void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR2; - tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); - tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; - RCC->CFGR2 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PREDIV2Config - * - * @brief Configures the PREDIV2 division factor. - * - * @param RCC_PREDIV2_Div - specifies the PREDIV2 clock division factor. - * This parameter can be RCC_PREDIV2_Divx where x:[1,16] - * - * @return none - */ -void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR2; - tmpreg &= ~CFGR2_PREDIV2; - tmpreg |= RCC_PREDIV2_Div; - RCC->CFGR2 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PLL2Config - * - * @brief Configures the PLL2 multiplication factor. - * - * @param RCC_PLL2Mul - specifies the PLL2 multiplication factor. - * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} - * - * @return none - */ -void RCC_PLL2Config(uint32_t RCC_PLL2Mul) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR2; - tmpreg &= ~CFGR2_PLL2MUL; - tmpreg |= RCC_PLL2Mul; - RCC->CFGR2 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PLL2Cmd - * - * @brief Enables or disables the PLL2. - * - * @param NewState - new state of the PLL2. This parameter can be - * ENABLE or DISABLE. - * - * @return none - */ -void RCC_PLL2Cmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1<<26); - } - else{ - RCC->CTLR &= ~(1<<26); - } -} - -/********************************************************************* - * @fn RCC_PLL3Config - * - * @brief Configures the PLL3 multiplication factor. - * - * @param RCC_PLL3Mul - specifies the PLL2 multiplication factor. - * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} - * - * @return none - */ -void RCC_PLL3Config(uint32_t RCC_PLL3Mul) -{ - uint32_t tmpreg = 0; - - tmpreg = RCC->CFGR2; - tmpreg &= ~CFGR2_PLL3MUL; - tmpreg |= RCC_PLL3Mul; - RCC->CFGR2 = tmpreg; -} - -/********************************************************************* - * @fn RCC_PLL3Cmd - * - * @brief Enables or disables the PLL3. - * - * @param NewState - new state of the PLL2. This parameter can be - * ENABLE or DISABLE. - * - * @return none - */ -void RCC_PLL3Cmd(FunctionalState NewState) -{ - if(NewState) - { - RCC->CTLR |= (1<<28); - } - else{ - RCC->CTLR &= ~(1<<28); - } -} - -/********************************************************************* - * @fn RCC_OTGFSCLKConfig - * - * @brief Configures the USB OTG FS clock (OTGFSCLK). - * - * @param RCC_OTGFSCLKSource - specifies the USB OTG FS clock source. - * RCC_OTGFSCLKSource_PLLCLK_Div1 - PLL clock divided by 1 - * selected as USB OTG FS clock source - * RCC_OTGFSCLKSource_PLLCLK_Div2 - PLL clock divided by 2 - * selected as USB OTG FS clock source - * RCC_OTGFSCLKSource_PLLCLK_Div3 - PLL clock divided by 3 - * selected as USB OTG FS clock source - * - * @return none - */ -void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) -{ - RCC->CFGR0 &= ~(3<<22); - RCC->CFGR0 |= RCC_OTGFSCLKSource<<22; -} - -/********************************************************************* - * @fn RCC_I2S2CLKConfig - * - * @brief Configures the I2S2 clock source(I2S2CLK). - * - * @param RCC_I2S2CLKSource - specifies the I2S2 clock source. - * RCC_I2S2CLKSource_SYSCLK - system clock selected as I2S2 clock entry - * RCC_I2S2CLKSource_PLL3_VCO - PLL3 VCO clock selected as I2S2 clock entry - * - * @return none - */ -void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) -{ - RCC->CFGR2 &= ~(1<<17); - RCC->CFGR2 |= RCC_I2S2CLKSource<<17; -} - -/********************************************************************* - * @fn RCC_I2S3CLKConfig - * - * @brief Configures the I2S3 clock source(I2S2CLK). - * - * @param RCC_I2S3CLKSource - specifies the I2S3 clock source. - * RCC_I2S3CLKSource_SYSCLK - system clock selected as I2S3 clock entry - * RCC_I2S3CLKSource_PLL3_VCO - PLL3 VCO clock selected as I2S3 clock entry - * - * @return none - */ -void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) -{ - RCC->CFGR2 &= ~(1<<18); - RCC->CFGR2 |= RCC_I2S3CLKSource<<18; -} - -/********************************************************************* - * @fn RCC_AHBPeriphResetCmd - * - * @brief Forces or releases AHB peripheral reset. - * - * @param RCC_AHBPeriph - specifies the AHB peripheral to reset. - * RCC_AHBPeriph_OTG_FS - * RCC_AHBPeriph_ETH_MAC - * NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->AHBRSTR |= RCC_AHBPeriph; - } - else - { - RCC->AHBRSTR &= ~RCC_AHBPeriph; - } -} - -/********************************************************************* - * @fn RCC_ADCCLKADJcmd - * - * @brief Enable ADC clock duty cycle adjustment. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ADCCLKADJcmd(FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->CFGR0 |= (1<<31); - } - else - { - RCC->CFGR0 &= ~(1<<31); - } -} - -/********************************************************************* - * @fn RCC_RNGCLKConfig - * - * @brief Configures the RNG clock source. - * - * @param RCC_RNGCLKSource - specifies the RNG clock source. - * RCC_RNGCLKSource_SYSCLK - system clock selected as RNG clock entry - * RCC_RNGCLKSource_PLL3_VCO - PLL3 VCO clock selected as RNG clock entry - * - * @return none - */ -void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource) -{ - RCC->CFGR2 &= ~(1<<19); - RCC->CFGR2 |= RCC_RNGCLKSource<<19; -} - -/********************************************************************* - * @fn RCC_ETH1GCLKConfig - * - * @brief Configures the ETH1G clock source. - * - * @param RCC_RNGCLKSource - specifies the ETH1G clock source. - * RCC_ETH1GCLKSource_PLL2_VCO - system clock selected as ETH1G clock entry - * RCC_ETH1GCLKSource_PLL3_VCO - PLL3 VCO clock selected as ETH1G clock entry - * RCC_ETH1GCLKSource_PB1_IN - GPIO PB1 input clock selected as ETH1G clock entry - * - * @return none - */ -void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource) -{ - RCC->CFGR2 &= ~(3<<20); - RCC->CFGR2 |= RCC_ETH1GCLKSource<<20; -} - -/********************************************************************* - * @fn RCC_ETH1G_125Mcmd - * - * @brief Enable ETH1G 125M. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_ETH1G_125Mcmd(FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->CFGR2 |= (1<<22); - } - else - { - RCC->CFGR2 &= ~(1<<22); - } -} - -/********************************************************************* - * @fn RCC_USBHSConfig - * - * @brief Configures the USBHS clock. - * - * @param RCC_USBHS - defines the USBHS clock divider. - * RCC_USBPLL_Div1 - USBHS clock = USBPLL. - * RCC_USBPLL_Div2 - USBHS clock = USBPLL/2. - * RCC_USBPLL_Div3 - USBHS clock = USBPLL/3. - * RCC_USBPLL_Div4 - USBHS clock = USBPLL/4. - * RCC_USBPLL_Div5 - USBHS clock = USBPLL/5. - * RCC_USBPLL_Div6 - USBHS clock = USBPLL/6. - * RCC_USBPLL_Div7 - USBHS clock = USBPLL/7. - * RCC_USBPLL_Div8 - USBHS clock = USBPLL/8. - * - * @return none - */ -void RCC_USBHSConfig(uint32_t RCC_USBHS) -{ - RCC->CFGR2 &= ~(7<<24); - RCC->CFGR2 |= RCC_USBHS<<24; -} - -/********************************************************************* - * @fn RCC_USBHSPLLCLKConfig - * - * @brief Configures the USBHSPLL clock source. - * - * @param RCC_HSBHSPLLCLKSource - specifies the USBHSPLL clock source. - * RCC_HSBHSPLLCLKSource_HSE - HSE clock selected as USBHSPLL clock entry - * RCC_HSBHSPLLCLKSource_HSI - HSI clock selected as USBHSPLL clock entry - * - * @return none - */ -void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource) -{ - RCC->CFGR2 &= ~(1<<27); - RCC->CFGR2 |= RCC_USBHSPLLCLKSource<<27; -} - -/********************************************************************* - * @fn RCC_USBHSPLLCKREFCLKConfig - * - * @brief Configures the USBHSPLL reference clock. - * - * @param RCC_USBHSPLLCKREFCLKSource - Select reference clock. - * RCC_USBHSPLLCKREFCLK_3M - reference clock 3Mhz. - * RCC_USBHSPLLCKREFCLK_4M - reference clock 4Mhz. - * RCC_USBHSPLLCKREFCLK_8M - reference clock 8Mhz. - * RCC_USBHSPLLCKREFCLK_5M - reference clock 5Mhz. - * - * @return none - */ -void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource) -{ - RCC->CFGR2 &= ~(3<<28); - RCC->CFGR2 |= RCC_USBHSPLLCKREFCLKSource<<28; -} - -/********************************************************************* - * @fn RCC_USBHSPHYPLLALIVEcmd - * - * @brief Enable USBHS PHY control. - * - * @param NewState - ENABLE or DISABLE. - * - * @return none - */ -void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState) -{ - if (NewState != DISABLE) - { - RCC->CFGR2 |= (1<<30); - } - else - { - RCC->CFGR2 &= ~(1<<30); - } -} - -/********************************************************************* - * @fn RCC_USBCLK48MConfig - * - * @brief Configures the USB clock 48MHz source. - * - * @param RCC_USBCLK48MSource - specifies the USB clock 48MHz source. - * RCC_USBCLK48MCLKSource_PLLCLK - PLLCLK clock selected as USB clock 48MHz clock entry - * RCC_USBCLK48MCLKSource_USBPHY - USBPHY clock selected as USB clock 48MHz clock entry - * - * @return none - */ -void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource) -{ - RCC->CFGR2 &= ~(1<<31); - RCC->CFGR2 |= RCC_USBCLK48MSource<<31; -} diff --git a/demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/.project b/demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/.project deleted file mode 100644 index 25be4dbc..00000000 --- a/demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/.project +++ /dev/null @@ -1,79 +0,0 @@ - - - usb_stack_cdc_acm - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - Core - 2 - PARENT-4-PROJECT_LOC/SRC/Core - - - Debug - 2 - PARENT-4-PROJECT_LOC/SRC/Debug - - - Ld - 2 - PARENT-4-PROJECT_LOC/SRC/Ld - - - Peripheral - 2 - PARENT-4-PROJECT_LOC/SRC/Peripheral - - - Startup - 2 - PARENT-4-PROJECT_LOC/SRC/Startup - - - USB_Stack - 2 - PARENT-7-PROJECT_LOC - - - User - 2 - PROJECT_LOC/User - - - usb_stack - 2 - C:/Users/lvjiazhen/Desktop/usb_stack - - - - - 1595986042669 - - 22 - - org.eclipse.ui.ide.multiFilter - 1.0-name-matches-false-false-*.wvproj - - - - diff --git a/demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/.settings/org.eclipse.core.resources.prefs b/demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/.settings/org.eclipse.core.resources.prefs deleted file mode 100644 index cd7dddfa..00000000 --- a/demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/.settings/org.eclipse.core.resources.prefs +++ /dev/null @@ -1,2 +0,0 @@ -eclipse.preferences.version=1 -encoding//usb_stack/port/ch32/usb_ch32_usbhs_reg.h=UTF-8 diff --git a/demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/.template b/demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/.template deleted file mode 100644 index ed6fc0b4..00000000 --- a/demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/.template +++ /dev/null @@ -1,13 +0,0 @@ - -Vendor=WCH -Link=WCH-Link -Toolchain= -Series= -Description= -Mcu Type=CH32V30x -Address=0x08000000 -Erase All=true -Program=true -Verify=true -Reset=true -Target Path=obj/usb_stack_cdc_acm.hex diff --git a/demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/USB_Stack_CDC_ACM.wvproj b/demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/USB_Stack_CDC_ACM.wvproj deleted file mode 100644 index 2cd99d98..00000000 --- a/demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/USB_Stack_CDC_ACM.wvproj +++ /dev/null @@ -1,2 +0,0 @@ -iCZ ?"ǁrF<.ſ?/XOĿChQN$*EBk!2t+buhnUb]xll| -+"