copy bouffalo ehci glue from official sdk
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134
port/ehci/usb_glue_bouffalo.c
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134
port/ehci/usb_glue_bouffalo.c
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#include "bflb_core.h"
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#include "usbh_core.h"
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#include "hardware/usb_v2_reg.h"
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#ifndef CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE
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#error "usb host must enable CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE"
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#endif
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#define BLFB_USB_BASE ((uint32_t)0x20072000)
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#define BFLB_PDS_BASE ((uint32_t)0x2000e000)
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#define PDS_USB_CTL_OFFSET (0x500) /* usb_ctl */
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#define PDS_USB_PHY_CTRL_OFFSET (0x504) /* usb_phy_ctrl */
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/* 0x500 : usb_ctl */
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#define PDS_REG_USB_SW_RST_N (1 << 0U)
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#define PDS_REG_USB_EXT_SUSP_N (1 << 1U)
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#define PDS_REG_USB_WAKEUP (1 << 2U)
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#define PDS_REG_USB_L1_WAKEUP (1 << 3U)
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#define PDS_REG_USB_DRVBUS_POL (1 << 4U)
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#define PDS_REG_USB_IDDIG (1 << 5U)
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/* 0x504 : usb_phy_ctrl */
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#define PDS_REG_USB_PHY_PONRST (1 << 0U)
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#define PDS_REG_USB_PHY_OSCOUTEN (1 << 1U)
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#define PDS_REG_USB_PHY_XTLSEL_SHIFT (2U)
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#define PDS_REG_USB_PHY_XTLSEL_MASK (0x3 << PDS_REG_USB_PHY_XTLSEL_SHIFT)
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#define PDS_REG_USB_PHY_OUTCLKSEL (1 << 4U)
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#define PDS_REG_USB_PHY_PLLALIV (1 << 5U)
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#define PDS_REG_PU_USB20_PSW (1 << 6U)
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#define USB_SOF_TIMER_MASK_AFTER_RESET_HS (0x44C)
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#define USB_SOF_TIMER_MASK_AFTER_RESET_FS (0x2710)
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extern void USBH_IRQHandler();
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static void bflb_usb_phy_init(void)
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{
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uint32_t regval;
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/* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0 */
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/* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */
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/* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1 */
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/* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0 */
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/* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1 */
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/* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1 */
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/* #1.2ms; wait UCLK */
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/* wait(soc616_b0.usb_uclk); */
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regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
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regval &= ~PDS_REG_USB_PHY_XTLSEL_MASK;
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putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
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regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
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regval |= PDS_REG_PU_USB20_PSW;
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putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
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regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
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regval |= PDS_REG_USB_PHY_PONRST;
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putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
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/* greater than 5T */
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bflb_mtimer_delay_us(1);
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regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
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regval &= ~PDS_REG_USB_SW_RST_N;
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putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
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/* greater than 5T */
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bflb_mtimer_delay_us(1);
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regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
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regval |= PDS_REG_USB_EXT_SUSP_N;
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putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
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/* wait UCLK 1.2ms */
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bflb_mtimer_delay_ms(3);
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regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
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regval |= PDS_REG_USB_SW_RST_N;
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putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
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bflb_mtimer_delay_ms(2);
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}
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void usb_hc_low_level_init(void)
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{
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uint32_t regval;
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bflb_usb_phy_init();
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bflb_irq_attach(37, USBH_IRQHandler, NULL);
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bflb_irq_enable(37);
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/* enable device-A for host */
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regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
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regval &= ~PDS_REG_USB_IDDIG;
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putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
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regval = getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
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regval |= USB_A_BUS_DROP_HOV;
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regval &= ~USB_A_BUS_REQ_HOV;
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putreg32(regval, BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
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bflb_mtimer_delay_ms(10);
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/* enable vbus and bus control */
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regval = getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
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regval &= ~USB_A_BUS_DROP_HOV;
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regval |= USB_A_BUS_REQ_HOV;
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putreg32(regval, BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
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regval = getreg32(BLFB_USB_BASE + USB_GLB_INT_OFFSET);
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regval |= USB_MDEV_INT;
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regval |= USB_MOTG_INT;
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regval &= ~USB_MHC_INT;
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putreg32(regval, BLFB_USB_BASE + USB_GLB_INT_OFFSET);
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}
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uint8_t usbh_get_port_speed(const uint8_t port)
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{
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uint8_t speed = 3;
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speed = (getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET) & USB_SPD_TYP_HOV_POV_MASK) >> USB_SPD_TYP_HOV_POV_SHIFT;
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if (speed == 0) {
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return USB_SPEED_FULL;
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} else if (speed == 1) {
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return USB_SPEED_LOW;
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} else if (speed == 2) {
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return USB_SPEED_HIGH;
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}
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return USB_SPEED_HIGH;
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}
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