From 3440e0cc1db71a8ec809fb244e1844848aa14ae1 Mon Sep 17 00:00:00 2001 From: sakumisu <1203593632@qq.com> Date: Sun, 26 Nov 2023 22:19:21 +0800 Subject: [PATCH] move out dwc2 ggcfg register and config by user --- SConscript | 8 +++---- port/dwc2/usb_dc_dwc2.c | 49 +++++++--------------------------------- port/dwc2/usb_dwc2_reg.h | 3 +++ port/dwc2/usb_glue_st.c | 23 +++++++++++++++++++ port/dwc2/usb_hc_dwc2.c | 24 ++++---------------- 5 files changed, 43 insertions(+), 64 deletions(-) create mode 100644 port/dwc2/usb_glue_st.c diff --git a/SConscript b/SConscript index b96c8c94..234c80ce 100644 --- a/SConscript +++ b/SConscript @@ -62,14 +62,12 @@ if GetDepend(['PKG_CHERRYUSB_DEVICE']): if GetDepend(['PKG_CHERRYUSB_DEVICE_DWC2']): src += Glob('port/dwc2/usb_dc_dwc2.c') + if GetDepend(['PKG_CHERRYUSB_DEVICE_DWC2_STM32']): + src += Glob('port/dwc2/usb_glue_st.c') if GetDepend(['PKG_CHERRYUSB_DEVICE_DWC2_PORT_FS']): CPPDEFINES += ['CONFIG_USB_DWC2_PORT=FS_PORT'] elif GetDepend(['PKG_CHERRYUSB_DEVICE_DWC2_PORT_HS']): CPPDEFINES += ['CONFIG_USB_DWC2_PORT=HS_PORT'] - if GetDepend(['SOC_SERIES_STM32F7']): - CPPDEFINES += ['STM32F7'] - elif GetDepend(['SOC_SERIES_STM32H7']): - CPPDEFINES += ['STM32H7'] if GetDepend(['PKG_CHERRYUSB_DEVICE_MUSB']): src += Glob('port/musb/usb_dc_musb.c') @@ -112,6 +110,8 @@ if GetDepend(['PKG_CHERRYUSB_HOST']): if GetDepend(['PKG_CHERRYUSB_HOST_DWC2']): src += Glob('port/dwc2/usb_hc_dwc2.c') + if GetDepend(['PKG_CHERRYUSB_HOST_DWC2_STM32']): + src += Glob('port/dwc2/usb_glue_st.c') if GetDepend(['PKG_CHERRYUSB_HOST_MUSB']): src += Glob('port/musb/usb_hc_musb.c') diff --git a/port/dwc2/usb_dc_dwc2.c b/port/dwc2/usb_dc_dwc2.c index 544d6e5c..5c68c320 100644 --- a/port/dwc2/usb_dc_dwc2.c +++ b/port/dwc2/usb_dc_dwc2.c @@ -64,12 +64,8 @@ #endif #ifndef USB_BASE -#ifdef STM32H7 -#define USB_BASE (0x40080000UL) -#else #define USB_BASE (0x50000000UL) #endif -#endif #define USB_RAM_SIZE 1280 /* define with minimum value*/ @@ -121,10 +117,8 @@ #define CONFIG_USB_DWC2_DMA_ENABLE #ifdef CONFIG_USB_DWC2_DMA_ENABLE -#if defined(STM32F7) || defined(STM32H7) #warning "if you enable dcache,please add .nocacheble section in your sct or ld or icf" #endif -#endif /*FIFO sizes in bytes (total available memory for FIFOs is 4KB )*/ #ifndef CONFIG_USB_DWC2_RX_FIFO_SIZE @@ -215,8 +209,6 @@ static inline int dwc2_core_init(void) { int ret; #if defined(CONFIG_USB_HS) - USB_OTG_GLB->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); - /* Init The ULPI Interface */ USB_OTG_GLB->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); @@ -231,8 +223,6 @@ static inline int dwc2_core_init(void) /* Reset after a PHY select */ ret = dwc2_reset(); - /* Activate the USB Transceiver */ - USB_OTG_GLB->GCCFG |= USB_OTG_GCCFG_PWRDWN; #endif return ret; } @@ -575,6 +565,7 @@ int usb_dc_init(void) endpoints = ((USB_OTG_GLB->GHWCFG2 & (0x0f << 10)) >> 10) + 1; USB_LOG_INFO("========== dwc2 udc params ==========\r\n"); + USB_LOG_INFO("GCCFG:%08x\r\n", USB_OTG_GLB->GCCFG); USB_LOG_INFO("CID:%08x\r\n", USB_OTG_GLB->CID); USB_LOG_INFO("GSNPSID:%08x\r\n", USB_OTG_GLB->GSNPSID); USB_LOG_INFO("GHWCFG1:%08x\r\n", USB_OTG_GLB->GHWCFG1); @@ -590,46 +581,22 @@ int usb_dc_init(void) USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + /* This is vendor register */ + USB_OTG_GLB->GCCFG = usbd_get_dwc2_gccfg_conf(); + ret = dwc2_core_init(); /* Force Device Mode*/ dwc2_set_mode(USB_OTG_MODE_DEVICE); + /* B-peripheral session valid override enable */ + // USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + // USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + for (uint8_t i = 0U; i < 15U; i++) { USB_OTG_GLB->DIEPTXF[i] = 0U; } -#if defined(STM32F7) || defined(STM32H7) || defined(STM32L4) -#ifdef CONFIG_DWC2_VBUS_SENSING_ENABLE - /* Enable HW VBUS sensing */ - USB_OTG_GLB->GCCFG |= USB_OTG_GCCFG_VBDEN; -#else - /* Deactivate VBUS Sensing B */ - USB_OTG_GLB->GCCFG &= ~USB_OTG_GCCFG_VBDEN; - - /* B-peripheral session valid override enable */ - USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; - USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; -#endif -#else -#ifdef CONFIG_DWC2_VBUS_SENSING_ENABLE - /* Enable HW VBUS sensing */ - USB_OTG_GLB->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; - USB_OTG_GLB->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; -#else -#ifdef CONFIG_DWC2_GD32 - USB_OTG_GLB->GCCFG |= USB_OTG_GCCFG_VBUSBSEN | USB_OTG_GCCFG_VBUSASEN; -#else - /* - * Disable HW VBUS sensing. VBUS is internally considered to be always - * at VBUS-Valid level (5V). - */ - USB_OTG_GLB->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; - USB_OTG_GLB->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; - USB_OTG_GLB->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; -#endif -#endif -#endif /* Restart the Phy Clock */ USB_OTG_PCGCCTL = 0U; diff --git a/port/dwc2/usb_dwc2_reg.h b/port/dwc2/usb_dwc2_reg.h index 173861d9..f45ba8c2 100644 --- a/port/dwc2/usb_dwc2_reg.h +++ b/port/dwc2/usb_dwc2_reg.h @@ -1705,4 +1705,7 @@ typedef struct #define USB_MASK_HALT_HC_INT(chnum) (USB_OTG_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) #define USB_UNMASK_HALT_HC_INT(chnum) (USB_OTG_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) #define CLEAR_HC_INT(chnum, __INTERRUPT__) (USB_OTG_HC(chnum)->HCINT = (__INTERRUPT__)) + +uint32_t usbd_get_dwc2_gccfg_conf(void); +uint32_t usbh_get_dwc2_gccfg_conf(void); #endif diff --git a/port/dwc2/usb_glue_st.c b/port/dwc2/usb_glue_st.c new file mode 100644 index 00000000..3b60a40f --- /dev/null +++ b/port/dwc2/usb_glue_st.c @@ -0,0 +1,23 @@ +#include "usb_config.h" +#include "stdint.h" +#include "usb_dwc2_reg.h" + +/* st different chips maybe have a little difference in this register, you should check this */ + +uint32_t usbd_get_dwc2_gccfg_conf(void) +{ +#ifdef CONFIG_USB_HS + return 0; +#else + return ((1 << 16) | (1 << 21)); +#endif +} + +uint32_t usbh_get_dwc2_gccfg_conf(void) +{ +#ifdef CONFIG_USB_DWC2_ULPI_PHY + return 0; +#else + return ((1 << 16) | (1 << 21)); +#endif +} \ No newline at end of file diff --git a/port/dwc2/usb_hc_dwc2.c b/port/dwc2/usb_hc_dwc2.c index 8848deed..cf921d53 100644 --- a/port/dwc2/usb_hc_dwc2.c +++ b/port/dwc2/usb_hc_dwc2.c @@ -82,7 +82,6 @@ static inline int dwc2_core_init(void) { int ret; #if defined(CONFIG_USB_DWC2_ULPI_PHY) - USB_OTG_GLB->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); /* Init The ULPI Interface */ USB_OTG_GLB->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); @@ -97,9 +96,6 @@ static inline int dwc2_core_init(void) USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; /* Reset after a PHY select */ ret = dwc2_reset(); - - /* Activate the USB Transceiver */ - USB_OTG_GLB->GCCFG |= USB_OTG_GCCFG_PWRDWN; #endif return ret; } @@ -465,6 +461,7 @@ int usb_hc_init(void) usb_hc_low_level_init(); USB_LOG_INFO("========== dwc2 hcd params ==========\r\n"); + USB_LOG_INFO("GCCFG:%08x\r\n", USB_OTG_GLB->GCCFG); USB_LOG_INFO("CID:%08x\r\n", USB_OTG_GLB->CID); USB_LOG_INFO("GSNPSID:%08x\r\n", USB_OTG_GLB->GSNPSID); USB_LOG_INFO("GHWCFG1:%08x\r\n", USB_OTG_GLB->GHWCFG1); @@ -482,7 +479,11 @@ int usb_hc_init(void) USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + /* This is vendor register */ + USB_OTG_GLB->GCCFG = usbh_get_dwc2_gccfg_conf(); + ret = dwc2_core_init(); + /* Force Host Mode*/ dwc2_set_mode(USB_OTG_MODE_HOST); usb_osal_msleep(50); @@ -490,21 +491,6 @@ int usb_hc_init(void) /* Restart the Phy Clock */ USB_OTG_PCGCCTL = 0U; -#if defined(STM32F7) || defined(STM32H7) - /* Disable HW VBUS sensing */ - USB_OTG_GLB->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); - /* Disable Battery chargin detector */ - USB_OTG_GLB->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); -#else - /* - * Disable HW VBUS sensing. VBUS is internally considered to be always - * at VBUS-Valid level (5V). - */ - USB_OTG_GLB->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; - USB_OTG_GLB->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; - USB_OTG_GLB->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; -#endif - /* Set default Max speed support */ USB_OTG_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);