remove mm32/imxrt/nuvoton old port
This commit is contained in:
sakumisu
@@ -1,129 +0,0 @@
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/*
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* Copyright (c) 2022, sakumisu
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef USB_TMC_H
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#define USB_TMC_H
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/**@addtogroup MODULE_TMC USB TMC class
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* @brief This module contains USB Device Test and Measurement Class definitions.
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* @details This module based on
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* [USB Device Test and Measurement Class Specification, Revision 1.0]
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* (https://www.usb.org/sites/default/files/USBTMC_1_006a.zip)
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* @{*/
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/**@name USB TMC class, subclass and protocol definitions
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* @{*/
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#define TMC_SUBCLASS_TMC 0x03
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#define TMC_PROTOCOL_NONE 0x00 /**< No subclass specification applies. */
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#define TMC_PROTOCOL_USB488 0x01 /**< USBTMC USB488 subclass interface. */
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/** @}*/
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/**@name USBTMC requests
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* @{*/
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#define TMC_REQUEST_INITIATE_ABORT_BULK_OUT 1
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#define TMC_REQUEST_CHECK_ABORT_BULK_OUT_STATUS 2
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#define TMC_REQUEST_INITIATE_ABORT_BULK_IN 3
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#define TMC_REQUEST_CHECK_ABORT_BULK_IN_STATUS 4
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#define TMC_REQUEST_INITIATE_CLEAR 5
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#define TMC_REQUEST_CHECK_CLEAR_STATUS 6
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#define TMC_REQUEST_GET_CAPABILITIES 7
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#define TMC_REQUEST_INDICATOR_PULSE 64
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/**@}*/
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/**@name USBTMC status values
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* @{*/
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#define TMC_STATUS_SUCCESS 0x01
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#define TMC_STATUS_PENDING 0x02
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#define TMC_STATUS_FAILED 0x80
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#define TMC_STATUS_TRANSFER_NOT_IN_PROGRESS 0x81
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#define TMC_STATUS_SPLIT_NOT_IN_PROGRESS 0x82
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#define TMC_STATUS_SPLIT_IN_PROGRESS 0x83
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/**@}*/
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/** GET_CAPABILITIES request response */
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struct tmc_get_capabilities_response {
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uint8_t USBTMC_status;
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uint8_t Reserved0;
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uint16_t bcdUSBTMC;
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uint8_t InterfaceCapabilities;
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uint8_t DeviceCapabilities;
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uint8_t Reserved1[18];
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} __PACKED;
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/**@name MsgId values
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* @{*/
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#define TMC_DEV_DEP_MSG_OUT 1
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#define TMC_REQUEST_DEV_DEP_MSG_IN 2
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#define TMC_DEV_DEP_MSG_IN 2
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#define TMC_VENDOR_SPECIFIC_OUT 126
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#define TMC_REQUEST_VENDOR_SPECIFIC_IN 127
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#define TMC_VENDOR_SPECIFIC_IN 127
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/**@}*/
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/**@name Transfer Attributes
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* @{*/
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/** The last USBTMC message data byte in the transfer is the last byte of the
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* USBTMC message. */
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#define TMC_TRANSFER_ATTR_EOM 0x01
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/** The Bulk-IN transfer must terminate on the specified TermChar. The Host may
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* only set this bit if the USBTMC interface indicates it supports TermChar in
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* the GET_CAPABILITIES response packet */
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#define TMC_TRANSFER_ATTR_TERM_CHAR 0x02
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/**@}*/
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/** Message specific part of bulk header */
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union usb_tmc_bulk_header_specific {
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struct {
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uint32_t TransferSize;
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uint8_t bmTransferAttributes;
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uint8_t Reserved[3];
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} dev_dep_msg_out;
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struct {
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uint32_t TransferSize;
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uint8_t bmTransferAttributes;
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uint8_t TermChar;
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uint8_t Reserved[2];
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} request_dev_dep_msg_in;
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struct {
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uint32_t TransferSize;
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uint8_t bmTransferAttributes;
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uint8_t Reserved[3];
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} dev_dep_msg_in;
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struct {
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uint32_t TransferSize;
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uint8_t Reserved[4];
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} vendor_specific_out;
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struct {
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uint32_t TransferSize;
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uint8_t Reserved[4];
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} request_vendor_specific_in;
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struct {
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uint32_t TransferSize;
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uint8_t Reserved[4];
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} vendor_specific_in;
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};
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/** Host must begin the first USB transaction in each Bulk transfer of
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* command message content with a Bulk Header. */
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struct usb_tmc_bulk_header {
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/** Specifies the USBTMC message and the type of the USBTMC message. */
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uint8_t MsgId;
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/** A transfer identifier. The Host must set bTag different than the
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* bTag used in the previous Bulk-OUT Header. The Host should increment
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* the bTag by 1 each time it sends a new Bulk-OUT Header. */
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uint8_t bTag;
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/** The inverse (one's complement) of the bTag */
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uint8_t bTagInverse;
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uint8_t Reserved;
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/** USBTMC command message specific */
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union usb_tmc_bulk_header_specific MsgSpecific;
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} __PACKED;
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#endif /* USB_TMC_H */
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@@ -1,12 +0,0 @@
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# Note
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## Support Chip List
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- IMXRT105x
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- IMXRT106x
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## Before Use
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- You should set the heap size on greater than the sum of all usb endpoint buffers.
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- Open the clock on USBPHY1.
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- Set macro CONFIG_USB_HS for use the high-speed mode otherwise the full-speed mode.
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File diff suppressed because it is too large
Load Diff
@@ -1,42 +0,0 @@
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#ifndef _USB_DC_IMXRT_PORT
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#define _USB_DC_IMXRT_PORT
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/* USB Device condfiguration */
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#define USB_DEVICE_USE_PORT (1U)
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#define USB_DEVICE_ENDPOINTS (8U)
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#define USB_DEVICE_MAX_DTD (USB_DEVICE_ENDPOINTS * 2)
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/*! @brief Whether the transfer buffer is cache-enabled or not. */
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#ifndef USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE
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#define USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE (0U)
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#endif
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/*! @brief Whether the low power mode is enabled or not. */
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#define USB_DEVICE_CONFIG_LOW_POWER_MODE (0U)
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/*! @brief Whether the device detached feature is enabled or not. */
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#define USB_DEVICE_CONFIG_DETACH_ENABLE (0U)
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/*! @brief Whether handle the USB bus error. */
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#define USB_DEVICE_CONFIG_ERROR_HANDLING (0U)
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/*! @brief Define big endian */
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#define USB_BIG_ENDIAN (0U)
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/*! @brief Define little endian */
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#define USB_LITTLE_ENDIAN (1U)
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/* USB PHY condfiguration */
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#define BOARD_USB_PHY_D_CAL (0x0CU)
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#define BOARD_USB_PHY_TXCAL45DP (0x06U)
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#define BOARD_USB_PHY_TXCAL45DM (0x06U)
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typedef struct
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{
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uint8_t sta;
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uint8_t type;
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uint16_t mps;
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uint8_t *pbuf;
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}usb_dtd_buffer_t;
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#if CONFIG_USB_HS
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void usbd_desc_hs_register(uint8_t *descriptor);
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#endif
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uint8_t usb_dtd_buf_node_register(uint8_t ep, uint32_t mps);
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int usb_transfer_data(uint8_t ep, uint8_t *data, uint16_t len);
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#endif // !_USB_DC_IMXRT_PORT
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@@ -1,368 +0,0 @@
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#ifndef __USB_IMXRT_REG_H__
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#define __USB_IMXRT_REG_H__
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define __I volatile const /*!< Defines 'read only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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/* ----------------------------------------------------------------------------
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-- USB Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
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* @{
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*/
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/** USB - Register Layout Typedef */
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// typedef struct {
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// __I uint32_t ID; /**< Identification register, offset: 0x0 */
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// __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */
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// __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */
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// __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */
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// __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */
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// __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */
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// uint8_t RESERVED_0[104];
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// __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */
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// __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */
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// __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */
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// __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */
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// __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */
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// uint8_t RESERVED_1[108];
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// __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */
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// uint8_t RESERVED_2[1];
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// __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */
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// __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */
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// __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */
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// uint8_t RESERVED_3[20];
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// __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */
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// uint8_t RESERVED_4[2];
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// __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */
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// uint8_t RESERVED_5[24];
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// __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */
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// __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */
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// __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */
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// __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */
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// uint8_t RESERVED_6[4];
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// union { /* offset: 0x154 */
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// __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */
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// __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */
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// };
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// union { /* offset: 0x158 */
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// __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */
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// __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */
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// };
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// uint8_t RESERVED_7[4];
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// __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */
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// __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */
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// uint8_t RESERVED_8[16];
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// __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */
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// __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */
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// __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */
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// __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */
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// uint8_t RESERVED_9[28];
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// __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */
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// __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */
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// __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */
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// __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */
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// __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */
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// __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */
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// __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */
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// __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */
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// __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */
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// } USB_Type;
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/*! @brief The maximum value of ISO type maximum packet size for HS in USB specification 2.0 */
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#define USB_DEVICE_MAX_HS_ISO_MAX_PACKET_SIZE (1024U)
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/*! @brief The maximum value of interrupt type maximum packet size for HS in USB specification 2.0 */
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#define USB_DEVICE_MAX_HS_INTERUPT_MAX_PACKET_SIZE (1024U)
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/*! @brief The maximum value of bulk type maximum packet size for HS in USB specification 2.0 */
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#define USB_DEVICE_MAX_HS_BULK_MAX_PACKET_SIZE (512U)
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/*! @brief The maximum value of control type maximum packet size for HS in USB specification 2.0 */
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#define USB_DEVICE_MAX_HS_CONTROL_MAX_PACKET_SIZE (64U)
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#define USB_DEVICE_MAX_TRANSFER_PRIME_TIMES \
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(10000000U) /* The max prime times of EPPRIME, if still doesn't take effect, means status has been reset*/
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/* Device QH */
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#define USB_DEVICE_EHCI_QH_POINTER_MASK (0xFFFFFFC0U)
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#define USB_DEVICE_EHCI_QH_MULT_MASK (0xC0000000U)
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#define USB_DEVICE_EHCI_QH_ZLT_MASK (0x20000000U)
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#define USB_DEVICE_EHCI_QH_MAX_PACKET_SIZE_MASK (0x07FF0000U)
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#define USB_DEVICE_EHCI_QH_MAX_PACKET_SIZE (0x00000800U)
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#define USB_DEVICE_EHCI_QH_IOS_MASK (0x00008000U)
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/* Device DTD */
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#define USB_DEVICE_ECHI_DTD_POINTER_MASK (0xFFFFFFE0U)
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#define USB_DEVICE_ECHI_DTD_TERMINATE_MASK (0x00000001U)
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#define USB_DEVICE_ECHI_DTD_PAGE_MASK (0xFFFFF000U)
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#define USB_DEVICE_ECHI_DTD_PAGE_OFFSET_MASK (0x00000FFFU)
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#define USB_DEVICE_ECHI_DTD_PAGE_BLOCK (0x00001000U)
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#define USB_DEVICE_ECHI_DTD_TOTAL_BYTES_MASK (0x7FFF0000U)
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#define USB_DEVICE_ECHI_DTD_TOTAL_BYTES (0x00004000U)
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#define USB_DEVICE_ECHI_DTD_IOC_MASK (0x00008000U)
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#define USB_DEVICE_ECHI_DTD_MULTIO_MASK (0x00000C00U)
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#define USB_DEVICE_ECHI_DTD_STATUS_MASK (0x000000FFU)
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#define USB_DEVICE_EHCI_DTD_STATUS_ERROR_MASK (0x00000068U)
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#define USB_DEVICE_ECHI_DTD_STATUS_ACTIVE (0x00000080U)
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#define USB_DEVICE_ECHI_DTD_STATUS_HALTED (0x00000040U)
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#define USB_DEVICE_ECHI_DTD_STATUS_DATA_BUFFER_ERROR (0x00000020U)
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#define USB_DEVICE_ECHI_DTD_STATUS_TRANSACTION_ERROR (0x00000008U)
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#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK (0x1800u)
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#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_SHFIT (11U)
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/*! @brief Define current endian */
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#ifndef ENDIANNESS
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#define ENDIANNESS USB_LITTLE_ENDIAN
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#endif
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/*
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* The following MACROs (USB_GLOBAL, USB_BDT, USB_RAM_ADDRESS_ALIGNMENT, etc) are only used for USB device stack.
|
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* The USB device global variables are put into the section m_usb_global and m_usb_bdt
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* by using the MACRO USB_GLOBAL and USB_BDT. In this way, the USB device
|
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* global variables can be linked into USB dedicated RAM by USB_STACK_USE_DEDICATED_RAM.
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* The MACRO USB_STACK_USE_DEDICATED_RAM is used to decide the USB stack uses dedicated RAM or not. The value of
|
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* the macro can be set as 0, USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL, or USB_STACK_DEDICATED_RAM_TYPE_BDT.
|
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* The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT_GLOBAL means USB device global variables, including USB_BDT and
|
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* USB_GLOBAL, are put into the USB dedicated RAM. This feature can only be enabled when the USB dedicated RAM
|
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* is not less than 2K Bytes.
|
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* The MACRO USB_STACK_DEDICATED_RAM_TYPE_BDT means USB device global variables, only including USB_BDT, are put
|
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* into the USB dedicated RAM, the USB_GLOBAL will be put into .bss section. This feature is used for some SOCs,
|
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* the USB dedicated RAM size is not more than 512 Bytes.
|
||||
*/
|
||||
#if defined(__ICCARM__)
|
||||
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||||
#define USB_WEAK_VAR __attribute__((weak))
|
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#define USB_WEAK_FUN __attribute__((weak))
|
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/* disable misra 19.13 */
|
||||
_Pragma("diag_suppress=Pm120")
|
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#define USB_ALIGN_PRAGMA(x) _Pragma(#x)
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_Pragma("diag_default=Pm120")
|
||||
|
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#define USB_RAM_ADDRESS_ALIGNMENT(n) USB_ALIGN_PRAGMA(data_alignment = n)
|
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_Pragma("diag_suppress=Pm120")
|
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#define USB_LINK_SECTION_PART(str) _Pragma(#str)
|
||||
#define USB_LINK_DMA_INIT_DATA(sec) USB_LINK_SECTION_PART(location = #sec)
|
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#define USB_LINK_USB_GLOBAL _Pragma("location = \"m_usb_global\"")
|
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#define USB_LINK_USB_BDT _Pragma("location = \"m_usb_bdt\"")
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#define USB_LINK_USB_GLOBAL_BSS
|
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#define USB_LINK_USB_BDT_BSS
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_Pragma("diag_default=Pm120")
|
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#define USB_LINK_DMA_NONINIT_DATA _Pragma("location = \"m_usb_dma_noninit_data\"")
|
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#define USB_LINK_NONCACHE_NONINIT_DATA _Pragma("location = \"NonCacheable\"")
|
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#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION))
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||||
#define USB_WEAK_VAR __attribute__((weak))
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||||
#define USB_WEAK_FUN __attribute__((weak))
|
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#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n)))
|
||||
#define USB_LINK_DMA_INIT_DATA(sec) __attribute__((section(#sec)))
|
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#if defined(__CC_ARM)
|
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#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global"))) __attribute__((zero_init))
|
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#else
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||||
#define USB_LINK_USB_GLOBAL __attribute__((section(".bss.m_usb_global")))
|
||||
#endif
|
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#if defined(__CC_ARM)
|
||||
#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt"))) __attribute__((zero_init))
|
||||
#else
|
||||
#define USB_LINK_USB_BDT __attribute__((section(".bss.m_usb_bdt")))
|
||||
#endif
|
||||
#define USB_LINK_USB_GLOBAL_BSS
|
||||
#define USB_LINK_USB_BDT_BSS
|
||||
#if defined(__CC_ARM)
|
||||
#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data"))) __attribute__((zero_init))
|
||||
#else
|
||||
#define USB_LINK_DMA_NONINIT_DATA __attribute__((section(".bss.m_usb_dma_noninit_data")))
|
||||
#endif
|
||||
#if defined(__CC_ARM)
|
||||
#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable"))) __attribute__((zero_init))
|
||||
#else
|
||||
#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section(".bss.NonCacheable")))
|
||||
#endif
|
||||
|
||||
#elif defined(__GNUC__)
|
||||
|
||||
#define USB_WEAK_VAR __attribute__((weak))
|
||||
#define USB_WEAK_FUN __attribute__((weak))
|
||||
#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n)))
|
||||
#define USB_LINK_DMA_INIT_DATA(sec) __attribute__((section(#sec)))
|
||||
#define USB_LINK_USB_GLOBAL __attribute__((section("m_usb_global, \"aw\", %nobits @")))
|
||||
#define USB_LINK_USB_BDT __attribute__((section("m_usb_bdt, \"aw\", %nobits @")))
|
||||
#define USB_LINK_USB_GLOBAL_BSS
|
||||
#define USB_LINK_USB_BDT_BSS
|
||||
#define USB_LINK_DMA_NONINIT_DATA __attribute__((section("m_usb_dma_noninit_data, \"aw\", %nobits @")))
|
||||
#define USB_LINK_NONCACHE_NONINIT_DATA __attribute__((section("NonCacheable, \"aw\", %nobits @")))
|
||||
|
||||
#elif (defined(__DSC__) && defined(__CW__))
|
||||
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
|
||||
#define USB_WEAK_VAR __attribute__((weak))
|
||||
#define USB_WEAK_FUN __attribute__((weak))
|
||||
#define USB_RAM_ADDRESS_ALIGNMENT(n) __attribute__((aligned(n)))
|
||||
#define USB_LINK_USB_BDT_BSS
|
||||
#define USB_LINK_USB_GLOBAL_BSS
|
||||
#else
|
||||
#error The tool-chain is not supported.
|
||||
#endif
|
||||
|
||||
#if (defined(USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE)) || \
|
||||
(defined(USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE) && (USB_HOST_CONFIG_BUFFER_PROPERTY_CACHEABLE))
|
||||
#define USB_DMA_DATA_NONINIT_SUB USB_LINK_DMA_NONINIT_DATA
|
||||
#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(m_usb_dma_init_data)
|
||||
#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
|
||||
#else
|
||||
#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE))
|
||||
#define USB_DMA_DATA_NONINIT_SUB USB_LINK_NONCACHE_NONINIT_DATA
|
||||
#define USB_DMA_DATA_INIT_SUB USB_LINK_DMA_INIT_DATA(NonCacheable.init)
|
||||
#define USB_CONTROLLER_DATA USB_LINK_NONCACHE_NONINIT_DATA
|
||||
#else
|
||||
#define USB_DMA_DATA_NONINIT_SUB
|
||||
#define USB_DMA_DATA_INIT_SUB
|
||||
#define USB_CONTROLLER_DATA USB_LINK_USB_GLOBAL
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*! @brief Endpoint initialization structure */
|
||||
typedef struct _usb_device_endpoint_init_struct
|
||||
{
|
||||
uint16_t maxPacketSize; /*!< Endpoint maximum packet size */
|
||||
uint8_t endpointAddress; /*!< Endpoint address*/
|
||||
uint8_t transferType; /*!< Endpoint transfer type*/
|
||||
uint8_t zlt; /*!< ZLT flag*/
|
||||
uint8_t interval; /*!< Endpoint interval*/
|
||||
} usb_device_endpoint_init_struct_t;
|
||||
|
||||
typedef struct _usb_device_ehci_qh_struct
|
||||
{
|
||||
union
|
||||
{
|
||||
volatile uint32_t capabilttiesCharacteristics;
|
||||
struct
|
||||
{
|
||||
volatile uint32_t reserved1 : 15;
|
||||
volatile uint32_t ios : 1;
|
||||
volatile uint32_t maxPacketSize : 11;
|
||||
volatile uint32_t reserved2 : 2;
|
||||
volatile uint32_t zlt : 1;
|
||||
volatile uint32_t mult : 2;
|
||||
} capabilttiesCharacteristicsBitmap;
|
||||
} capabilttiesCharacteristicsUnion;
|
||||
volatile uint32_t currentDtdPointer;
|
||||
volatile uint32_t nextDtdPointer;
|
||||
union
|
||||
{
|
||||
volatile uint32_t dtdToken;
|
||||
struct
|
||||
{
|
||||
volatile uint32_t status : 8;
|
||||
volatile uint32_t reserved1 : 2;
|
||||
volatile uint32_t multiplierOverride : 2;
|
||||
volatile uint32_t reserved2 : 3;
|
||||
volatile uint32_t ioc : 1;
|
||||
volatile uint32_t totalBytes : 15;
|
||||
volatile uint32_t reserved3 : 1;
|
||||
} dtdTokenBitmap;
|
||||
} dtdTokenUnion;
|
||||
volatile uint32_t bufferPointerPage[5];
|
||||
volatile uint32_t reserved1;
|
||||
uint32_t setupBuffer[2];
|
||||
uint32_t setupBufferBack[2];
|
||||
union
|
||||
{
|
||||
uint32_t endpointStatus;
|
||||
struct
|
||||
{
|
||||
uint32_t isOpened : 1;
|
||||
uint32_t zlt : 1;
|
||||
uint32_t : 30;
|
||||
} endpointStatusBitmap;
|
||||
} endpointStatusUnion;
|
||||
uint32_t reserved2;
|
||||
} usb_device_ehci_qh_struct_t;
|
||||
|
||||
typedef struct _usb_device_ehci_dtd_struct
|
||||
{
|
||||
volatile uint32_t nextDtdPointer;
|
||||
union
|
||||
{
|
||||
volatile uint32_t dtdToken;
|
||||
struct
|
||||
{
|
||||
volatile uint32_t status : 8;
|
||||
volatile uint32_t reserved1 : 2;
|
||||
volatile uint32_t multiplierOverride : 2;
|
||||
volatile uint32_t reserved2 : 3;
|
||||
volatile uint32_t ioc : 1;
|
||||
volatile uint32_t totalBytes : 15;
|
||||
volatile uint32_t reserved3 : 1;
|
||||
} dtdTokenBitmap;
|
||||
} dtdTokenUnion;
|
||||
volatile uint32_t bufferPointerPage[5];
|
||||
union
|
||||
{
|
||||
volatile uint32_t reserved;
|
||||
struct
|
||||
{
|
||||
uint32_t originalBufferOffest : 12;
|
||||
uint32_t originalBufferLength : 19;
|
||||
uint32_t dtdInvalid : 1;
|
||||
} originalBufferInfo;
|
||||
} reservedUnion;
|
||||
} usb_device_ehci_dtd_struct_t;
|
||||
|
||||
/*! @brief EHCI state structure */
|
||||
typedef struct _usb_device_ehci_state_struct
|
||||
{
|
||||
USB_Type *registerBase; /*!< The base address of the register */
|
||||
#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U))
|
||||
USBPHY_Type *registerPhyBase; /*!< The base address of the PHY register */
|
||||
#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U))
|
||||
USBNC_Type *registerNcBase; /*!< The base address of the USBNC register */
|
||||
#endif
|
||||
#endif
|
||||
usb_device_ehci_qh_struct_t *qh; /*!< The QH structure base address */
|
||||
usb_device_ehci_dtd_struct_t *dtd; /*!< The DTD structure base address */
|
||||
usb_device_ehci_dtd_struct_t *dtdFree; /*!< The idle DTD list head */
|
||||
usb_device_ehci_dtd_struct_t
|
||||
*dtdHead[USB_DEVICE_ENDPOINTS * 2]; /*!< The transferring DTD list head for each endpoint */
|
||||
usb_device_ehci_dtd_struct_t
|
||||
*dtdTail[USB_DEVICE_ENDPOINTS * 2]; /*!< The transferring DTD list tail for each endpoint */
|
||||
uint8_t dtdCount; /*!< The idle DTD node count */
|
||||
uint8_t endpointCount; /*!< The endpoint number of EHCI */
|
||||
uint8_t isResetting; /*!< Whether a PORT reset is occurring or not */
|
||||
uint8_t controllerId; /*!< Controller ID */
|
||||
uint8_t speed; /*!< Current speed of EHCI */
|
||||
uint8_t isSuspending; /*!< Is suspending of the PORT */
|
||||
} usb_device_ehci_state_struct_t;
|
||||
|
||||
/*! @brief USB error code */
|
||||
typedef enum _usb_status
|
||||
{
|
||||
kStatus_USB_Success = 0x00U, /*!< Success */
|
||||
kStatus_USB_Error, /*!< Failed */
|
||||
|
||||
kStatus_USB_Busy, /*!< Busy */
|
||||
kStatus_USB_InvalidHandle, /*!< Invalid handle */
|
||||
kStatus_USB_InvalidParameter, /*!< Invalid parameter */
|
||||
kStatus_USB_InvalidRequest, /*!< Invalid request */
|
||||
kStatus_USB_ControllerNotFound, /*!< Controller cannot be found */
|
||||
kStatus_USB_InvalidControllerInterface, /*!< Invalid controller interface */
|
||||
|
||||
kStatus_USB_NotSupported, /*!< Configuration is not supported */
|
||||
kStatus_USB_Retry, /*!< Enumeration get configuration retry */
|
||||
kStatus_USB_TransferStall, /*!< Transfer stalled */
|
||||
kStatus_USB_TransferFailed, /*!< Transfer failed */
|
||||
kStatus_USB_AllocFail, /*!< Allocation failed */
|
||||
kStatus_USB_LackSwapBuffer, /*!< Insufficient swap buffer for KHCI */
|
||||
kStatus_USB_TransferCancel, /*!< The transfer cancelled */
|
||||
kStatus_USB_BandwidthFail, /*!< Allocate bandwidth failed */
|
||||
kStatus_USB_MSDStatusFail, /*!< For MSD, the CSW status means fail */
|
||||
kStatus_USB_EHCIAttached,
|
||||
kStatus_USB_EHCIDetached,
|
||||
kStatus_USB_DataOverRun, /*!< The amount of data returned by the endpoint exceeded
|
||||
either the size of the maximum data packet allowed
|
||||
from the endpoint or the remaining buffer size. */
|
||||
} usb_status_t;
|
||||
|
||||
#endif /* __USB_IMXRT_REG_H__ */
|
||||
/* End of file ***************************************************************************/
|
||||
@@ -1,14 +0,0 @@
|
||||
# Note
|
||||
|
||||
## Support Chip List
|
||||
|
||||
- MM32F10x
|
||||
- MM32L0xx
|
||||
- MM32L3xx
|
||||
|
||||
## Before Use
|
||||
|
||||
Your should implement `usb_dc_low_level_init` and `usb_dc_low_level_deinit`.
|
||||
- Enable or disable USB clock and set USB clock for 48M.
|
||||
- Enable or disable gpio and gpio clk for usb dp and dm.
|
||||
- Enable or disable usb irq
|
||||
@@ -1,264 +0,0 @@
|
||||
#include "usbd_core.h"
|
||||
#include "usb_mm32_reg.h"
|
||||
|
||||
#ifndef USBD_IRQHandler
|
||||
#define USBD_IRQHandler USB_HP_CAN1_TX_IRQHandler //use actual usb irq name instead
|
||||
#endif
|
||||
|
||||
#define USB_BASE ((uint32_t)0x40005C00)
|
||||
#define USB ((USB_TypeDef *)USB_BASE)
|
||||
|
||||
#ifndef USB_NUM_BIDIR_ENDPOINTS
|
||||
#define USB_NUM_BIDIR_ENDPOINTS 5
|
||||
#endif
|
||||
|
||||
#define USB_GET_EPX_INT_STATE(ep_idx) (*(volatile uint32_t *)(&USB->rEP1_INT_STATE + (ep_idx - 1)))
|
||||
#define USB_SET_EPX_INT_STATE(ep_idx, val) (*(volatile uint32_t *)(&USB->rEP1_INT_STATE + (ep_idx - 1)) = val)
|
||||
#define USB_SET_EP_INT(ep_idx, val) (*(volatile uint32_t *)(&USB->rEP1_INT_EN + (ep_idx - 1)) = val)
|
||||
#define USB_GET_EP_RX_CNT(ep_idx) (*(volatile uint32_t *)(&USB->rEP0_AVIL + ep_idx))
|
||||
#define USB_GET_EP_CTRL(ep_idx) (*(volatile uint32_t *)(&USB->rEP0_CTRL + ep_idx))
|
||||
#define USB_SET_EP_CTRL(ep_idx, val) (*(volatile uint32_t *)(&USB->rEP0_CTRL + ep_idx) = val)
|
||||
#define USB_GET_EP_FIFO(ep_idx) (*(volatile uint32_t *)(&USB->rEP0_FIFO + ep_idx))
|
||||
#define USB_SET_EP_FIFO(ep_idx, val) (*(volatile uint32_t *)(&USB->rEP0_FIFO + ep_idx) = val)
|
||||
|
||||
/* Endpoint state */
|
||||
struct usb_dc_ep_state {
|
||||
/** Endpoint max packet size */
|
||||
uint16_t ep_mps;
|
||||
/** Endpoint Transfer Type.
|
||||
* May be Bulk, Interrupt, Control or Isochronous
|
||||
*/
|
||||
uint8_t ep_type;
|
||||
uint8_t ep_stalled; /** Endpoint stall flag */
|
||||
};
|
||||
|
||||
/* Driver state */
|
||||
struct usb_dc_config_priv {
|
||||
struct usb_dc_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/
|
||||
struct usb_dc_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
|
||||
} usb_dc_cfg;
|
||||
|
||||
__WEAK void usb_dc_low_level_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
__WEAK void usb_dc_low_level_deinit(void)
|
||||
{
|
||||
}
|
||||
|
||||
int usb_dc_init(void)
|
||||
{
|
||||
memset(&usb_dc_cfg, 0, sizeof(struct usb_dc_config_priv));
|
||||
|
||||
usb_dc_cfg.out_ep[0].ep_mps = USB_CTRL_EP_MPS;
|
||||
usb_dc_cfg.out_ep[0].ep_type = 0x00;
|
||||
usb_dc_cfg.in_ep[0].ep_mps = USB_CTRL_EP_MPS;
|
||||
usb_dc_cfg.in_ep[0].ep_type = 0x00;
|
||||
|
||||
usb_dc_low_level_init();
|
||||
|
||||
USB->rTOP = USB_TOP_RESET; //reset usb
|
||||
USB->rTOP &= ~USB_TOP_RESET;
|
||||
USB->rTOP &= ~USB_TOP_CONNECT; //usb disconnect
|
||||
|
||||
USB->rINT_STATE |= 0;
|
||||
USB->rEP_INT_STATE |= 0;
|
||||
USB->rEP0_INT_STATE |= 0;
|
||||
USB->rEP1_INT_STATE |= 0;
|
||||
USB->rEP2_INT_STATE |= 0;
|
||||
USB->rEP3_INT_STATE |= 0;
|
||||
USB->rEP4_INT_STATE |= 0;
|
||||
|
||||
USB->rEP0_CTRL = 0;
|
||||
USB->rEP1_CTRL = 0;
|
||||
USB->rEP2_CTRL = 0;
|
||||
USB->rEP3_CTRL = 0;
|
||||
USB->rEP4_CTRL = 0;
|
||||
|
||||
USB->rINT_EN = USB_INT_EN_RSTIE | USB_INT_EN_SUSPENDIE | USB_INT_EN_RESUMIE | USB_INT_EN_EPINTIE; //enable rst、suppend、resume、ep global irq
|
||||
USB->rEP0_INT_EN = EPn_INT_EN_SETUPIE | EPn_INT_EN_OUTACKIE | EPn_INT_EN_INACKIE | EPn_INT_EN_OUTSTALLIE | EPn_INT_EN_INSTALLIE; //enable ep0 setup、inack、outack irq
|
||||
|
||||
USB->rEP_INT_EN = EP_INT_EN_EP0IE; //enable ep0 irq
|
||||
USB->rEP_EN = EP_EN_EP0EN; //enable ep0
|
||||
USB->rADDR = 0; //set addr 0
|
||||
|
||||
USB->rTOP = USB_TOP_CONNECT | ((~USB_TOP_SPEED) & 0x01); //connect usb
|
||||
USB->rPOWER = USB_POWER_SUSPEN | USB_POWER_SUSP;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usb_dc_deinit(void)
|
||||
{
|
||||
usb_dc_low_level_deinit();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_set_address(const uint8_t addr)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
|
||||
{
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep_cfg->ep_addr);
|
||||
|
||||
if (ep_idx == 0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (USB_EP_DIR_IS_OUT(ep_cfg->ep_addr)) {
|
||||
usb_dc_cfg.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
|
||||
usb_dc_cfg.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
|
||||
USB_SET_EP_INT(ep_idx, EPn_INT_EN_OUTACKIE);
|
||||
} else {
|
||||
usb_dc_cfg.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
|
||||
usb_dc_cfg.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
|
||||
USB_SET_EP_INT(ep_idx, EPn_INT_EN_INACKIE);
|
||||
}
|
||||
USB->rEP_INT_EN |= (1 << ep_idx);
|
||||
USB->rEP_EN |= (1 << ep_idx);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_ep_close(const uint8_t ep)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_ep_set_stall(const uint8_t ep)
|
||||
{
|
||||
USB->rEP_HALT |= (1 << (ep & 0x7f));
|
||||
return 0;
|
||||
}
|
||||
int usbd_ep_clear_stall(const uint8_t ep)
|
||||
{
|
||||
USB->rEP_HALT &= ~(1 << (ep & 0x7f));
|
||||
return 0;
|
||||
}
|
||||
int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes)
|
||||
{
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep);
|
||||
uint8_t *pdata = (uint8_t *)data;
|
||||
if (!data && data_len) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (!data_len) {
|
||||
while (USB_GET_EP_CTRL(ep_idx) & 0x80) {
|
||||
}
|
||||
USB_SET_EP_CTRL(ep_idx, 0x80);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (data_len > usb_dc_cfg.in_ep[ep_idx].ep_mps) {
|
||||
data_len = usb_dc_cfg.in_ep[ep_idx].ep_mps;
|
||||
}
|
||||
|
||||
while (USB_GET_EP_CTRL(ep_idx) & 0x80) {
|
||||
}
|
||||
|
||||
for (uint8_t i = 0; i < data_len; i++) {
|
||||
USB_SET_EP_FIFO(ep_idx, *pdata);
|
||||
pdata++;
|
||||
}
|
||||
USB_SET_EP_CTRL(ep_idx, 0x80 | data_len);
|
||||
|
||||
if (ret_bytes) {
|
||||
*ret_bytes = data_len;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_t *read_bytes)
|
||||
{
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep);
|
||||
uint32_t read_count;
|
||||
uint8_t *pdata = (uint8_t *)data;
|
||||
if (!data && max_data_len) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (!max_data_len) {
|
||||
return 0;
|
||||
}
|
||||
if ((ep_idx == 0) && (max_data_len == 8) && !read_bytes) {
|
||||
for (uint8_t i = 0; i < 8; i++) {
|
||||
*(pdata + i) = USB->rSETUP[i];
|
||||
}
|
||||
|
||||
} else {
|
||||
read_count = USB_GET_EP_RX_CNT(ep_idx);
|
||||
read_count = MIN(read_count, max_data_len);
|
||||
|
||||
for (uint8_t i = 0; i < read_count; i++) {
|
||||
*(pdata + i) = USB_GET_EP_FIFO(ep_idx);
|
||||
}
|
||||
}
|
||||
|
||||
if (read_bytes) {
|
||||
*read_bytes = read_count;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void USBD_IRQHandler(void)
|
||||
{
|
||||
uint32_t int_status;
|
||||
uint32_t epindex;
|
||||
uint32_t ep_int_status;
|
||||
int_status = USB->rINT_STATE;
|
||||
USB->rINT_STATE = int_status;
|
||||
if (int_status & USB_INT_STATE_EPINTF) {
|
||||
epindex = USB->rEP_INT_STATE; //read all ep interrupt status
|
||||
USB->rEP_INT_STATE = epindex; //clear interrupt status
|
||||
|
||||
for (uint32_t i = 0; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
|
||||
if (epindex & (EP_INT_STATE_EP0F << i)) //read epx interrupt status
|
||||
{
|
||||
if (i == 0) {
|
||||
ep_int_status = USB->rEP0_INT_STATE;
|
||||
USB->rEP0_INT_STATE = ep_int_status;
|
||||
|
||||
if (ep_int_status & EPn_INT_STATE_SETUP) //setup interrupt status
|
||||
{
|
||||
usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
|
||||
}
|
||||
if (ep_int_status & EPn_INT_STATE_OUTACK) //outack interrupt status
|
||||
{
|
||||
usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
|
||||
}
|
||||
if (ep_int_status & EPn_INT_STATE_INACK) //inack interrupt status
|
||||
{
|
||||
usbd_event_notify_handler(USBD_EVENT_EP0_IN_NOTIFY, NULL);
|
||||
}
|
||||
} else {
|
||||
ep_int_status = USB_GET_EPX_INT_STATE(i);
|
||||
USB_SET_EPX_INT_STATE(i, ep_int_status);
|
||||
if (ep_int_status & EPn_INT_STATE_OUTACK) {
|
||||
usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(i & 0x7f));
|
||||
}
|
||||
if (ep_int_status & EPn_INT_STATE_INACK) {
|
||||
usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(i | 0x80));
|
||||
}
|
||||
}
|
||||
if (ep_int_status & EPn_INT_STATE_INSTALL) {
|
||||
}
|
||||
if (ep_int_status & EPn_INT_STATE_OUTSTALL) {
|
||||
}
|
||||
}
|
||||
}
|
||||
} else if (int_status & USB_INT_STATE_RSTF) {
|
||||
USB->rTOP |= USB_TOP_RESET;
|
||||
USB->rTOP &= ~USB_TOP_RESET;
|
||||
usbd_event_notify_handler(USBD_EVENT_RESET, NULL);
|
||||
} else if (int_status & USB_INT_STATE_SUSPENDF) {
|
||||
} else if (int_status & USB_INT_STATE_RESUMF) {
|
||||
}
|
||||
}
|
||||
@@ -1,410 +0,0 @@
|
||||
#ifndef __USB_MM32_REG_H__
|
||||
#define __USB_MM32_REG_H__
|
||||
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/**
|
||||
* @brief USB
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t rTOP; /*! Address offset: 0x00 */
|
||||
__IO uint32_t rINT_STATE; /*! Address offset: 0x04 */
|
||||
__IO uint32_t rEP_INT_STATE; /*! Address offset: 0x08 */
|
||||
__IO uint32_t rEP0_INT_STATE; /*! Address offset: 0x0C */
|
||||
__IO uint32_t rINT_EN; /*! Address offset: 0x10 */
|
||||
__IO uint32_t rEP_INT_EN; /*! Address offset: 0x14 */
|
||||
__IO uint32_t rEP0_INT_EN; /*! Address offset: 0x18 */
|
||||
|
||||
__IO uint32_t RESERVED0;
|
||||
|
||||
__IO uint32_t rEP1_INT_STATE; /*! Address offset: 0x20 */
|
||||
__IO uint32_t rEP2_INT_STATE; /*! Address offset: 0x24 */
|
||||
__IO uint32_t rEP3_INT_STATE; /*! Address offset: 0x28 */
|
||||
__IO uint32_t rEP4_INT_STATE; /*! Address offset: 0x2C */
|
||||
|
||||
__IO uint32_t RESERVED1; /*! Address offset: 0x30 */
|
||||
__IO uint32_t RESERVED2; /*! Address offset: 0x34 */
|
||||
__IO uint32_t RESERVED3; /*! Address offset: 0x38 */
|
||||
__IO uint32_t RESERVED4; /*! Address offset: 0x3C */
|
||||
|
||||
__IO uint32_t rEP1_INT_EN; /*! Address offset: 0x40 */
|
||||
__IO uint32_t rEP2_INT_EN; /*! Address offset: 0x44 */
|
||||
__IO uint32_t rEP3_INT_EN; /*! Address offset: 0x48 */
|
||||
__IO uint32_t rEP4_INT_EN; /*! Address offset: 0x4C */
|
||||
|
||||
__IO uint32_t RESERVED5; /*! Address offset: 0x50 */
|
||||
__IO uint32_t RESERVED6; /*! Address offset: 0x54 */
|
||||
__IO uint32_t RESERVED7; /*! Address offset: 0x58 */
|
||||
__IO uint32_t RESERVED8; /*! Address offset: 0x5C */
|
||||
|
||||
__IO uint32_t rADDR; /*! Address offset: 0x60 */
|
||||
__IO uint32_t rEP_EN; /*! Address offset: 0x64 */
|
||||
|
||||
__IO uint32_t RESERVED9; /*! Address offset: 0x68 */
|
||||
__IO uint32_t RESERVED10; /*! Address offset: 0x6C */
|
||||
__IO uint32_t RESERVED11; /*! Address offset: 0x70 */
|
||||
__IO uint32_t RESERVED12; /*! Address offset: 0x74 */
|
||||
|
||||
__IO uint32_t rTOG_CTRL1_4; /*! Address offset: 0x78 */
|
||||
|
||||
__IO uint32_t RESERVED13; /*! Address offset: 0x7C */
|
||||
|
||||
__IO uint32_t rSETUP[8]; /*! Address offset: 0x80 */
|
||||
//__IO uint32_t rSETUP0; /*! Address offset: 0x80 */
|
||||
//__IO uint32_t rSETUP1; /*! Address offset: 0x84 */
|
||||
//__IO uint32_t rSETUP2; /*! Address offset: 0x88 */
|
||||
//__IO uint32_t rSETUP3; /*! Address offset: 0x8C */
|
||||
//__IO uint32_t rSETUP4; /*! Address offset: 0x90 */
|
||||
//__IO uint32_t rSETUP5; /*! Address offset: 0x94 */
|
||||
//__IO uint32_t rSETUP6; /*! Address offset: 0x98 */
|
||||
//__IO uint32_t rSETUP7; /*! Address offset: 0x9C */
|
||||
__IO uint32_t rPAKET_SIZE0; /*! Address offset: 0xA0 */
|
||||
__IO uint32_t rPAKET_SIZE1; /*! Address offset: 0xA4 */
|
||||
|
||||
__IO uint32_t RESERVED14; /*! Address offset: 0xA8 */
|
||||
__IO uint32_t RESERVED15; /*! Address offset: 0xAC */
|
||||
|
||||
__IO uint32_t RESERVED16; /*! Address offset: 0xB0 */
|
||||
__IO uint32_t RESERVED17; /*! Address offset: 0xB4 */
|
||||
__IO uint32_t RESERVED18; /*! Address offset: 0xB8 */
|
||||
__IO uint32_t RESERVED19; /*! Address offset: 0xBC */
|
||||
|
||||
__IO uint32_t RESERVED20; /*! Address offset: 0xC0 */
|
||||
__IO uint32_t RESERVED21; /*! Address offset: 0xC4 */
|
||||
__IO uint32_t RESERVED22; /*! Address offset: 0xC8 */
|
||||
__IO uint32_t RESERVED23; /*! Address offset: 0xCC */
|
||||
|
||||
__IO uint32_t RESERVED24; /*! Address offset: 0xD0 */
|
||||
__IO uint32_t RESERVED25; /*! Address offset: 0xD4 */
|
||||
__IO uint32_t RESERVED26; /*! Address offset: 0xD8 */
|
||||
__IO uint32_t RESERVED27; /*! Address offset: 0xDC */
|
||||
|
||||
__IO uint32_t RESERVED28; /*! Address offset: 0xE0 */
|
||||
__IO uint32_t RESERVED29; /*! Address offset: 0xE4 */
|
||||
__IO uint32_t RESERVED30; /*! Address offset: 0xE8 */
|
||||
__IO uint32_t RESERVED31; /*! Address offset: 0xEC */
|
||||
|
||||
__IO uint32_t RESERVED32; /*! Address offset: 0xF0 */
|
||||
__IO uint32_t RESERVED33; /*! Address offset: 0xF4 */
|
||||
__IO uint32_t RESERVED34; /*! Address offset: 0xF8 */
|
||||
__IO uint32_t RESERVED35; /*! Address offset: 0xFC */
|
||||
|
||||
__IO uint32_t rEP0_AVIL; /*! Address offset: 0x100 */
|
||||
__IO uint32_t rEP1_AVIL; /*! Address offset: 0x104 */
|
||||
__IO uint32_t rEP2_AVIL; /*! Address offset: 0x108 */
|
||||
__IO uint32_t rEP3_AVIL; /*! Address offset: 0x10C */
|
||||
__IO uint32_t rEP4_AVIL; /*! Address offset: 0x110 */
|
||||
|
||||
__IO uint32_t RESERVED36; /*! Address offset: 0x114 */
|
||||
__IO uint32_t RESERVED37; /*! Address offset: 0x118 */
|
||||
__IO uint32_t RESERVED38; /*! Address offset: 0x11C */
|
||||
__IO uint32_t RESERVED39; /*! Address offset: 0x120 */
|
||||
|
||||
__IO uint32_t RESERVED40; /*! Address offset: 0x124 */
|
||||
__IO uint32_t RESERVED41; /*! Address offset: 0x128 */
|
||||
__IO uint32_t RESERVED42; /*! Address offset: 0x12C */
|
||||
__IO uint32_t RESERVED43; /*! Address offset: 0x130 */
|
||||
|
||||
__IO uint32_t RESERVED44; /*! Address offset: 0x134 */
|
||||
__IO uint32_t RESERVED45; /*! Address offset: 0x138 */
|
||||
__IO uint32_t RESERVED46; /*! Address offset: 0x13C */
|
||||
|
||||
__IO uint32_t rEP0_CTRL; /*! Address offset: 0x140 */
|
||||
__IO uint32_t rEP1_CTRL; /*! Address offset: 0x144 */
|
||||
__IO uint32_t rEP2_CTRL; /*! Address offset: 0x148 */
|
||||
__IO uint32_t rEP3_CTRL; /*! Address offset: 0x14C */
|
||||
__IO uint32_t rEP4_CTRL; /*! Address offset: 0x150 */
|
||||
|
||||
__IO uint32_t RESERVED47; /*! Address offset: 0x154 */
|
||||
__IO uint32_t RESERVED48; /*! Address offset: 0x158 */
|
||||
__IO uint32_t RESERVED49; /*! Address offset: 0x15C */
|
||||
//__IO uint32_t RESERVED50; /*! Address offset: 0x15C */
|
||||
|
||||
//__IO uint32_t rEPn_FIFO[5]; /*! Address offset: 0x160 */
|
||||
|
||||
__IO uint32_t rEP0_FIFO; /*! Address offset: 0x160 */
|
||||
__IO uint32_t rEP1_FIFO; /*! Address offset: 0x164 */
|
||||
__IO uint32_t rEP2_FIFO; /*! Address offset: 0x168 */
|
||||
__IO uint32_t rEP3_FIFO; /*! Address offset: 0x16C */
|
||||
__IO uint32_t rEP4_FIFO; /*! Address offset: 0x170 */
|
||||
|
||||
__IO uint32_t RESERVED51; /*! Address offset: 0x174 */
|
||||
__IO uint32_t RESERVED52; /*! Address offset: 0x178 */
|
||||
__IO uint32_t RESERVED53; /*! Address offset: 0x17C */
|
||||
|
||||
__IO uint32_t RESERVED54; /*! Address offset: 0x180 */
|
||||
|
||||
__IO uint32_t rEP_DMA; /*! Address offset: 0x184 */
|
||||
__IO uint32_t rEP_HALT; /*! Address offset: 0x188 */
|
||||
__IO uint32_t RESERVED55; /*! Address offset: 0x18C */
|
||||
|
||||
__IO uint32_t RESERVED56; /*! Address offset: 0x190 */
|
||||
__IO uint32_t RESERVED57; /*! Address offset: 0x194 */
|
||||
__IO uint32_t RESERVED58; /*! Address offset: 0x198 */
|
||||
__IO uint32_t RESERVED59; /*! Address offset: 0x19C */
|
||||
|
||||
__IO uint32_t RESERVED60; /*! Address offset: 0x1A0 */
|
||||
__IO uint32_t RESERVED61; /*! Address offset: 0x1A4 */
|
||||
__IO uint32_t RESERVED62; /*! Address offset: 0x1A8 */
|
||||
__IO uint32_t RESERVED63; /*! Address offset: 0x1AC */
|
||||
|
||||
__IO uint32_t RESERVED64; /*! Address offset: 0x1B0 */
|
||||
__IO uint32_t RESERVED65; /*! Address offset: 0x1B4 */
|
||||
__IO uint32_t RESERVED66; /*! Address offset: 0x1B8 */
|
||||
__IO uint32_t RESERVED67; /*! Address offset: 0x1BC */
|
||||
__IO uint32_t rPOWER; /*! Address offset: 0x1C0 */
|
||||
} USB_TypeDef;
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* USB */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
|
||||
/******************* Bit definition for USB_TOP register *******************/
|
||||
#define USB_TOP_SPEED ((uint16_t)0x0001)
|
||||
#define USB_TOP_CONNECT ((uint16_t)0x0002)
|
||||
#define USB_TOP_RESET ((uint16_t)0x0008)
|
||||
#define USB_TOP_SUSPEND ((uint16_t)0x0010)
|
||||
#define USB_TOP_ACTIVE ((uint16_t)0x0080)
|
||||
|
||||
#define USB_TOP_STATE ((uint16_t)0x0060)
|
||||
#define USB_TOP_STATE_0 ((uint16_t)0x0020)
|
||||
#define USB_TOP_STATE_1 ((uint16_t)0x0040)
|
||||
|
||||
/******************* Bit definition for USB_INT_STATE register *******************/
|
||||
#define USB_INT_STATE_RSTF ((uint16_t)0x0001)
|
||||
#define USB_INT_STATE_SUSPENDF ((uint16_t)0x0002)
|
||||
#define USB_INT_STATE_RESUMF ((uint16_t)0x0004)
|
||||
#define USB_INT_STATE_SOFF ((uint16_t)0x0008)
|
||||
#define USB_INT_STATE_EPINTF ((uint16_t)0x0010)
|
||||
|
||||
/******************* Bit definition for EP_INT_STATE register *******************/
|
||||
#define EP_INT_STATE_EP0F ((uint16_t)0x0001)
|
||||
#define EP_INT_STATE_EP1F ((uint16_t)0x0002)
|
||||
#define EP_INT_STATE_EP2F ((uint16_t)0x0004)
|
||||
#define EP_INT_STATE_EP3F ((uint16_t)0x0008)
|
||||
#define EP_INT_STATE_EP4F ((uint16_t)0x0010)
|
||||
|
||||
/******************* Bit definition for EP0_INT_STATE register *******************/
|
||||
#define EPn_INT_STATE_SETUP ((uint16_t)0x0001)
|
||||
#define EPn_INT_STATE_END ((uint16_t)0x0002)
|
||||
#define EPn_INT_STATE_INNACK ((uint16_t)0x0004)
|
||||
#define EPn_INT_STATE_INACK ((uint16_t)0x0008)
|
||||
#define EPn_INT_STATE_INSTALL ((uint16_t)0x0010)
|
||||
#define EPn_INT_STATE_OUTNACK ((uint16_t)0x0020)
|
||||
#define EPn_INT_STATE_OUTACK ((uint16_t)0x0040)
|
||||
#define EPn_INT_STATE_OUTSTALL ((uint16_t)0x0080)
|
||||
|
||||
/******************* Bit definition for USB_INT_EN register *******************/
|
||||
#define USB_INT_EN_RSTIE ((uint16_t)0x0001)
|
||||
#define USB_INT_EN_SUSPENDIE ((uint16_t)0x0002)
|
||||
#define USB_INT_EN_RESUMIE ((uint16_t)0x0004)
|
||||
#define USB_INT_EN_SOFIE ((uint16_t)0x0008)
|
||||
#define USB_INT_EN_EPINTIE ((uint16_t)0x0010)
|
||||
|
||||
/******************* Bit definition for EP_INT_EN register *******************/
|
||||
#define EP_INT_EN_EP0IE ((uint16_t)0x0001)
|
||||
#define EP_INT_EN_EP1IE ((uint16_t)0x0002)
|
||||
#define EP_INT_EN_EP2IE ((uint16_t)0x0004)
|
||||
#define EP_INT_EN_EP3IE ((uint16_t)0x0008)
|
||||
#define EP_INT_EN_EP4IE ((uint16_t)0x0010)
|
||||
|
||||
/******************* Bit definition for EP0_INT_EN register *******************/
|
||||
#define EPn_INT_EN_SETUPIE ((uint16_t)0x0001)
|
||||
#define EPn_INT_EN_ENDIE ((uint16_t)0x0002)
|
||||
#define EPn_INT_EN_INNACKIE ((uint16_t)0x0004)
|
||||
#define EPn_INT_EN_INACKIE ((uint16_t)0x0008)
|
||||
#define EPn_INT_EN_INSTALLIE ((uint16_t)0x0010)
|
||||
#define EPn_INT_EN_OUTNACKIE ((uint16_t)0x0020)
|
||||
#define EPn_INT_EN_OUTACKIE ((uint16_t)0x0040)
|
||||
#define EPn_INT_EN_OUTSTALLIE ((uint16_t)0x0080)
|
||||
|
||||
///******************* Bit definition for EP1_INT_STATE register *******************/
|
||||
//#define EP1_INT_STATE_END ((uint16_t)0x0002)
|
||||
//#define EP1_INT_STATE_INNACK ((uint16_t)0x0004)
|
||||
//#define EP1_INT_STATE_INACK ((uint16_t)0x0008)
|
||||
//#define EP1_INT_STATE_INSTALL ((uint16_t)0x0010)
|
||||
//#define EP1_INT_STATE_OUTNACK ((uint16_t)0x0020)
|
||||
//#define EP1_INT_STATE_OUTACK ((uint16_t)0x0040)
|
||||
//#define EP1_INT_STATE_OUTSTALL ((uint16_t)0x0080)
|
||||
|
||||
///******************* Bit definition for EP2_INT_STATE register *******************/
|
||||
//#define EP2_INT_STATE_END ((uint16_t)0x0002)
|
||||
//#define EP2_INT_STATE_INNACK ((uint16_t)0x0004)
|
||||
//#define EP2_INT_STATE_INACK ((uint16_t)0x0008)
|
||||
//#define EP2_INT_STATE_INSTALL ((uint16_t)0x0010)
|
||||
//#define EP2_INT_STATE_OUTNACK ((uint16_t)0x0020)
|
||||
//#define EP2_INT_STATE_OUTACK ((uint16_t)0x0040)
|
||||
//#define EP2_INT_STATE_OUTSTALL ((uint16_t)0x0080)
|
||||
|
||||
///******************* Bit definition for EP3_INT_STATE register *******************/
|
||||
//#define EP3_INT_STATE_END ((uint16_t)0x0002)
|
||||
//#define EP3_INT_STATE_INNACK ((uint16_t)0x0004)
|
||||
//#define EP3_INT_STATE_INACK ((uint16_t)0x0008)
|
||||
//#define EP3_INT_STATE_INSTALL ((uint16_t)0x0010)
|
||||
//#define EP3_INT_STATE_OUTNACK ((uint16_t)0x0020)
|
||||
//#define EP3_INT_STATE_OUTACK ((uint16_t)0x0040)
|
||||
//#define EP3_INT_STATE_OUTSTALL ((uint16_t)0x0080)
|
||||
|
||||
///******************* Bit definition for EP4_INT_STATE register *******************/
|
||||
//#define EP4_INT_STATE_END ((uint16_t)0x0002)
|
||||
//#define EP4_INT_STATE_INNACK ((uint16_t)0x0004)
|
||||
//#define EP4_INT_STATE_INACK ((uint16_t)0x0008)
|
||||
//#define EP4_INT_STATE_INSTALL ((uint16_t)0x0010)
|
||||
//#define EP4_INT_STATE_OUTNACK ((uint16_t)0x0020)
|
||||
//#define EP4_INT_STATE_OUTACK ((uint16_t)0x0040)
|
||||
//#define EP4_INT_STATE_OUTSTALL ((uint16_t)0x0080)
|
||||
|
||||
///******************* Bit definition for EP1_INT_EN register *******************/
|
||||
//#define EPn_INT_EN_ENDIE ((uint16_t)0x0002)
|
||||
//#define EPn_INT_EN_INNACKIE ((uint16_t)0x0004)
|
||||
//#define EPn_INT_EN_INACKIE ((uint16_t)0x0008)
|
||||
//#define EPn_INT_EN_INSTALLIE ((uint16_t)0x0010)
|
||||
//#define EPn_INT_EN_OUTNACKIE ((uint16_t)0x0020)
|
||||
//#define EPn_INT_EN_OUTACKIE ((uint16_t)0x0040)
|
||||
//#define EPn_INT_EN_OUTSTALLIE ((uint16_t)0x0080)
|
||||
|
||||
/******************* Bit definition for USB_ADDR register *******************/
|
||||
#define USB_ADDR_ADDR ((uint16_t)0x007F)
|
||||
|
||||
/******************* Bit definition for EP_EN register *******************/
|
||||
#define EP_EN_EP0EN ((uint16_t)0x0001)
|
||||
#define EP_EN_EP1EN ((uint16_t)0x0002)
|
||||
#define EP_EN_EP2EN ((uint16_t)0x0004)
|
||||
#define EP_EN_EP3EN ((uint16_t)0x0008)
|
||||
#define EP_EN_EP4EN ((uint16_t)0x0010)
|
||||
|
||||
/******************* Bit definition for TOG_CTRL1_4 register *******************/
|
||||
#define TOG_CTRL1_4_DTOG1 ((uint16_t)0x0001)
|
||||
#define TOG_CTRL1_4_DTOG1EN ((uint16_t)0x0002)
|
||||
#define TOG_CTRL1_4_DTOG2 ((uint16_t)0x0004)
|
||||
#define TOG_CTRL1_4_DTOG2EN ((uint16_t)0x0008)
|
||||
#define TOG_CTRL1_4_DTOG3 ((uint16_t)0x0010)
|
||||
#define TOG_CTRL1_4_DTOG3EN ((uint16_t)0x0020)
|
||||
#define TOG_CTRL1_4_DTOG4 ((uint16_t)0x0040)
|
||||
#define TOG_CTRL1_4_DTOG4EN ((uint16_t)0x0080)
|
||||
|
||||
/******************* Bit definition for SETUP0 register *******************/
|
||||
#define SETUP0 ((uint16_t)0x00FF)
|
||||
|
||||
/******************* Bit definition for SETUP1 register *******************/
|
||||
#define SETUP1 ((uint16_t)0x00FF)
|
||||
|
||||
/******************* Bit definition for SETUP2 register *******************/
|
||||
#define SETUP2 ((uint16_t)0x00FF)
|
||||
|
||||
/******************* Bit definition for SETUP3 register *******************/
|
||||
#define SETUP3 ((uint16_t)0x00FF)
|
||||
|
||||
/******************* Bit definition for SETUP4 register *******************/
|
||||
#define SETUP4 ((uint16_t)0x00FF)
|
||||
|
||||
/******************* Bit definition for SETUP5 register *******************/
|
||||
#define SETUP5 ((uint16_t)0x00FF)
|
||||
|
||||
/******************* Bit definition for SETUP6 register *******************/
|
||||
#define SETUP6 ((uint16_t)0x00FF)
|
||||
|
||||
/******************* Bit definition for SETUP7 register *******************/
|
||||
#define SETUP7 ((uint16_t)0x00FF)
|
||||
|
||||
/******************* Bit definition for PACKET_SIZE1 register *******************/
|
||||
#define PACKET_SIZE1 ((uint16_t)0x00FF)
|
||||
|
||||
/******************* Bit definition for PACKET_SIZE2 register *******************/
|
||||
#define PACKET_SIZE2 ((uint16_t)0x00FF)
|
||||
|
||||
/******************* Bit definition for EP0_AVIL register *******************/
|
||||
#define EP0_AVIL_EPXAVIL ((uint16_t)0x00FF)
|
||||
|
||||
/******************* Bit definition for EP1_AVIL register *******************/
|
||||
#define EP1_AVIL_EPXAVIL ((uint16_t)0x00FF)
|
||||
|
||||
/******************* Bit definition for EP2_AVIL register *******************/
|
||||
#define EP2_AVIL_EPXAVIL ((uint16_t)0x00FF)
|
||||
|
||||
/******************* Bit definition for EP3_AVIL register *******************/
|
||||
#define EP3_AVIL_EPXAVIL ((uint16_t)0x00FF)
|
||||
|
||||
/******************* Bit definition for EP4_AVIL register *******************/
|
||||
#define EP4_AVIL_EPXAVIL ((uint16_t)0x00FF)
|
||||
|
||||
/******************* Bit definition for EP0_CTRL register *******************/
|
||||
#define EP0_CTRL_TRANEN ((uint16_t)0x0080)
|
||||
|
||||
#define EP0_CTRL_TRANCOUNT ((uint16_t)0x007F)
|
||||
#define EP0_CTRL_TRANCOUNT_0 ((uint16_t)0x0001)
|
||||
#define EP0_CTRL_TRANCOUNT_1 ((uint16_t)0x0002)
|
||||
#define EP0_CTRL_TRANCOUNT_2 ((uint16_t)0x0004)
|
||||
#define EP0_CTRL_TRANCOUNT_3 ((uint16_t)0x0008)
|
||||
#define EP0_CTRL_TRANCOUNT_4 ((uint16_t)0x0010)
|
||||
#define EP0_CTRL_TRANCOUNT_5 ((uint16_t)0x0020)
|
||||
#define EP0_CTRL_TRANCOUNT_6 ((uint16_t)0x0040)
|
||||
|
||||
/******************* Bit definition for EP1_CTRL register *******************/
|
||||
#define EP1_CTRL_TRANEN ((uint16_t)0x0080)
|
||||
|
||||
#define EP1_CTRL_TRANCOUNT ((uint16_t)0x007F)
|
||||
#define EP1_CTRL_TRANCOUNT_0 ((uint16_t)0x0001)
|
||||
#define EP1_CTRL_TRANCOUNT_1 ((uint16_t)0x0002)
|
||||
#define EP1_CTRL_TRANCOUNT_2 ((uint16_t)0x0004)
|
||||
#define EP1_CTRL_TRANCOUNT_3 ((uint16_t)0x0008)
|
||||
#define EP1_CTRL_TRANCOUNT_4 ((uint16_t)0x0010)
|
||||
#define EP1_CTRL_TRANCOUNT_5 ((uint16_t)0x0020)
|
||||
#define EP1_CTRL_TRANCOUNT_6 ((uint16_t)0x0040)
|
||||
|
||||
/******************* Bit definition for EP2_CTRL register *******************/
|
||||
#define EP2_CTRL_TRANEN ((uint16_t)0x0080)
|
||||
|
||||
#define EP2_CTRL_TRANCOUNT ((uint16_t)0x007F)
|
||||
#define EP2_CTRL_TRANCOUNT_0 ((uint16_t)0x0001)
|
||||
#define EP2_CTRL_TRANCOUNT_1 ((uint16_t)0x0002)
|
||||
#define EP2_CTRL_TRANCOUNT_2 ((uint16_t)0x0004)
|
||||
#define EP2_CTRL_TRANCOUNT_3 ((uint16_t)0x0008)
|
||||
#define EP2_CTRL_TRANCOUNT_4 ((uint16_t)0x0010)
|
||||
#define EP2_CTRL_TRANCOUNT_5 ((uint16_t)0x0020)
|
||||
#define EP2_CTRL_TRANCOUNT_6 ((uint16_t)0x0040)
|
||||
|
||||
/******************* Bit definition for EP3_CTRL register *******************/
|
||||
#define EP3_CTRL_TRANEN ((uint16_t)0x0080)
|
||||
|
||||
#define EP3_CTRL_TRANCOUNT ((uint16_t)0x007F)
|
||||
#define EP3_CTRL_TRANCOUNT_0 ((uint16_t)0x0001)
|
||||
#define EP3_CTRL_TRANCOUNT_1 ((uint16_t)0x0002)
|
||||
#define EP3_CTRL_TRANCOUNT_2 ((uint16_t)0x0004)
|
||||
#define EP3_CTRL_TRANCOUNT_3 ((uint16_t)0x0008)
|
||||
#define EP3_CTRL_TRANCOUNT_4 ((uint16_t)0x0010)
|
||||
#define EP3_CTRL_TRANCOUNT_5 ((uint16_t)0x0020)
|
||||
#define EP3_CTRL_TRANCOUNT_6 ((uint16_t)0x0040)
|
||||
|
||||
/******************* Bit definition for EP4_CTRL register *******************/
|
||||
#define EP4_CTRL_TRANEN ((uint16_t)0x0080)
|
||||
|
||||
#define EP4_CTRL_TRANCOUNT ((uint16_t)0x007F)
|
||||
#define EP4_CTRL_TRANCOUNT_0 ((uint16_t)0x0001)
|
||||
#define EP4_CTRL_TRANCOUNT_1 ((uint16_t)0x0002)
|
||||
#define EP4_CTRL_TRANCOUNT_2 ((uint16_t)0x0004)
|
||||
#define EP4_CTRL_TRANCOUNT_3 ((uint16_t)0x0008)
|
||||
#define EP4_CTRL_TRANCOUNT_4 ((uint16_t)0x0010)
|
||||
#define EP4_CTRL_TRANCOUNT_5 ((uint16_t)0x0020)
|
||||
#define EP4_CTRL_TRANCOUNT_6 ((uint16_t)0x0040)
|
||||
|
||||
/******************* Bit definition for EP_DMA register *******************/
|
||||
#define EP_DMA_DMA1EN ((uint16_t)0x0001)
|
||||
#define EP_DMA_DMA2EN ((uint16_t)0x0002)
|
||||
|
||||
/******************* Bit definition for EP_HALT register *******************/
|
||||
#define EP_HALT_HALT0 ((uint16_t)0x0001)
|
||||
#define EP_HALT_HALT1 ((uint16_t)0x0002)
|
||||
#define EP_HALT_HALT2 ((uint16_t)0x0004)
|
||||
#define EP_HALT_HALT3 ((uint16_t)0x0008)
|
||||
#define EP_HALT_HALT4 ((uint16_t)0x0010)
|
||||
|
||||
/******************* Bit definition for USB_POWER register *******************/
|
||||
#define USB_POWER_SUSPEN ((uint16_t)0x0001)
|
||||
#define USB_POWER_SUSP ((uint16_t)0x0002)
|
||||
#define USB_POWER_WKUP ((uint16_t)0x0008)
|
||||
|
||||
#endif
|
||||
@@ -1,531 +0,0 @@
|
||||
#include "usbd_core.h"
|
||||
#include "usb_nuvoton_reg.h"
|
||||
|
||||
#ifndef USBD_IRQHandler
|
||||
#define USBD_IRQHandler USBD_IRQHandler
|
||||
#endif
|
||||
|
||||
#ifndef USB_BASE
|
||||
#define USB_BASE (0x40019000UL)
|
||||
#endif
|
||||
|
||||
#ifndef USB_NUM_BIDIR_ENDPOINTS
|
||||
#define USB_NUM_BIDIR_ENDPOINTS 13
|
||||
#endif
|
||||
|
||||
#define USBD ((USBD_T *)USB_BASE)
|
||||
|
||||
#define USBD_ENABLE_USB() ((uint32_t)(USBD->PHYCTL |= (USBD_PHYCTL_PHYEN_Msk | USBD_PHYCTL_DPPUEN_Msk))) /*!<Enable USB \hideinitializer */
|
||||
#define USBD_DISABLE_USB() ((uint32_t)(USBD->PHYCTL &= ~USBD_PHYCTL_DPPUEN_Msk)) /*!<Disable USB \hideinitializer */
|
||||
#define USBD_ENABLE_PHY() ((uint32_t)(USBD->PHYCTL |= USBD_PHYCTL_PHYEN_Msk)) /*!<Enable PHY \hideinitializer */
|
||||
#define USBD_DISABLE_PHY() ((uint32_t)(USBD->PHYCTL &= ~USBD_PHYCTL_PHYEN_Msk)) /*!<Disable PHY \hideinitializer */
|
||||
#define USBD_SET_SE0() ((uint32_t)(USBD->PHYCTL &= ~USBD_PHYCTL_DPPUEN_Msk)) /*!<Enable SE0, Force USB PHY Transceiver to Drive SE0 \hideinitializer */
|
||||
#define USBD_CLR_SE0() ((uint32_t)(USBD->PHYCTL |= USBD_PHYCTL_DPPUEN_Msk)) /*!<Disable SE0 \hideinitializer */
|
||||
#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr)) /*!<Set USB address \hideinitializer */
|
||||
#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR)) /*!<Get USB address \hideinitializer */
|
||||
#define USBD_ENABLE_USB_INT(intr) (USBD->GINTEN = (intr)) /*!<Enable USB Interrupt \hideinitializer */
|
||||
#define USBD_ENABLE_BUS_INT(intr) (USBD->BUSINTEN = (intr)) /*!<Enable BUS Interrupt \hideinitializer */
|
||||
#define USBD_GET_BUS_INT_FLAG() (USBD->BUSINTSTS) /*!<Clear Bus interrupt flag \hideinitializer */
|
||||
#define USBD_CLR_BUS_INT_FLAG(flag) (USBD->BUSINTSTS = flag) /*!<Clear Bus interrupt flag \hideinitializer */
|
||||
#define USBD_ENABLE_CEP_INT(intr) (USBD->CEPINTEN = (intr)) /*!<Enable CEP Interrupt \hideinitializer */
|
||||
#define USBD_CLR_CEP_INT_FLAG(flag) (USBD->CEPINTSTS = flag) /*!<Clear CEP interrupt flag \hideinitializer */
|
||||
#define USBD_SET_CEP_STATE(flag) (USBD->CEPCTL = flag) /*!<Set CEP state \hideinitializer */
|
||||
#define USBD_START_CEP_IN(size) (USBD->CEPTXCNT = size) /*!<Start CEP IN Transfer \hideinitializer */
|
||||
#define USBD_SET_MAX_PAYLOAD(ep, size) (USBD->EP[ep].EPMPS = (size)) /*!<Set EPx Maximum Packet Size \hideinitializer */
|
||||
#define USBD_ENABLE_EP_INT(ep, intr) (USBD->EP[ep].EPINTEN = (intr)) /*!<Enable EPx Interrupt \hideinitializer */
|
||||
#define USBD_GET_EP_INT_FLAG(ep) (USBD->EP[ep].EPINTSTS) /*!<Get EPx interrupt flag \hideinitializer */
|
||||
#define USBD_CLR_EP_INT_FLAG(ep, flag) (USBD->EP[ep].EPINTSTS = (flag)) /*!<Clear EPx interrupt flag \hideinitializer */
|
||||
#define USBD_SET_DMA_LEN(len) (USBD->DMACNT = len) /*!<Set DMA transfer length \hideinitializer */
|
||||
#define USBD_SET_DMA_ADDR(addr) (USBD->DMAADDR = addr) /*!<Set DMA transfer address \hideinitializer */
|
||||
#define USBD_SET_DMA_READ(epnum) (USBD->DMACTL = (USBD->DMACTL & ~USBD_DMACTL_EPNUM_Msk) | USBD_DMACTL_DMARD_Msk | epnum | 0x100) /*!<Set DMA transfer type to read \hideinitializer */
|
||||
#define USBD_SET_DMA_WRITE(epnum) (USBD->DMACTL = (USBD->DMACTL & ~(USBD_DMACTL_EPNUM_Msk | USBD_DMACTL_DMARD_Msk | 0x100)) | epnum) /*!<Set DMA transfer type to write \hideinitializer */
|
||||
#define USBD_ENABLE_DMA() (USBD->DMACTL |= USBD_DMACTL_DMAEN_Msk) /*!<Enable DMA transfer \hideinitializer */
|
||||
#define USBD_IS_ATTACHED() ((uint32_t)(USBD->PHYCTL & USBD_PHYCTL_VBUSDET_Msk)) /*!<Check cable connect state \hideinitializer */
|
||||
|
||||
/* Endpoint state */
|
||||
struct usb_dc_ep_state {
|
||||
/** Endpoint max packet size */
|
||||
uint16_t ep_mps;
|
||||
/** Endpoint Transfer Type.
|
||||
* May be Bulk, Interrupt, Control or Isochronous
|
||||
*/
|
||||
uint8_t ep_type;
|
||||
uint8_t ep_stalled; /** Endpoint stall flag */
|
||||
};
|
||||
|
||||
/* Driver state */
|
||||
struct usb_dc_config_priv {
|
||||
volatile uint8_t dev_addr;
|
||||
volatile uint32_t bufaddr;
|
||||
struct usb_dc_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/
|
||||
struct usb_dc_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
|
||||
} usb_dc_cfg;
|
||||
|
||||
static void usb_fifo_write(uint8_t ep_idx, uint8_t *buffer, uint16_t len)
|
||||
{
|
||||
uint32_t *buf32;
|
||||
uint8_t *buf8;
|
||||
uint32_t count32;
|
||||
uint32_t count8;
|
||||
int i;
|
||||
|
||||
if ((uint32_t)buffer & 0x03) {
|
||||
buf8 = buffer;
|
||||
if (ep_idx == 0) {
|
||||
for (i = 0; i < len; i++) {
|
||||
USBD->cep.CEPDAT_BYTE = *buf8;
|
||||
buf8++;
|
||||
}
|
||||
|
||||
} else {
|
||||
for (i = 0; i < len; i++) {
|
||||
USBD->EP[ep_idx - 1].ep.EPDAT_BYTE = *buf8;
|
||||
buf8++;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
count32 = len >> 2;
|
||||
count8 = len & 0x03;
|
||||
|
||||
buf32 = (uint32_t *)buffer;
|
||||
|
||||
if (ep_idx == 0) {
|
||||
while (count32--) {
|
||||
USBD->cep.CEPDAT = *buf32;
|
||||
buf32++;
|
||||
}
|
||||
|
||||
buf8 = (uint8_t *)buf32;
|
||||
|
||||
while (count8--) {
|
||||
USBD->cep.CEPDAT_BYTE = *buf8;
|
||||
buf8++;
|
||||
}
|
||||
} else {
|
||||
while (count32--) {
|
||||
USBD->EP[ep_idx - 1].ep.EPDAT = *buf32;
|
||||
buf32++;
|
||||
}
|
||||
buf8 = (uint8_t *)buf32;
|
||||
while (count8--) {
|
||||
USBD->EP[ep_idx - 1].ep.EPDAT_BYTE = *buf8;
|
||||
buf8++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void usb_fifo_read(uint8_t ep_idx, uint8_t *buffer, uint16_t len)
|
||||
{
|
||||
uint32_t *buf32;
|
||||
uint8_t *buf8;
|
||||
uint32_t count32;
|
||||
uint32_t count8;
|
||||
int i;
|
||||
|
||||
if ((uint32_t)buffer & 0x03) {
|
||||
buf8 = buffer;
|
||||
if (ep_idx == 0) {
|
||||
for (i = 0; i < len; i++) {
|
||||
*buf8 = USBD->cep.CEPDAT_BYTE;
|
||||
buf8++;
|
||||
}
|
||||
} else {
|
||||
for (i = 0; i < len; i++) {
|
||||
*buf8 = USBD->EP[ep_idx - 1].ep.EPDAT_BYTE;
|
||||
buf8++;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
count32 = len >> 2;
|
||||
count8 = len & 0x03;
|
||||
|
||||
buf32 = (uint32_t *)buffer;
|
||||
|
||||
if (ep_idx == 0) {
|
||||
while (count32--) {
|
||||
*buf32 = USBD->cep.CEPDAT;
|
||||
buf32++;
|
||||
}
|
||||
|
||||
buf8 = (uint8_t *)buf32;
|
||||
|
||||
while (count8--) {
|
||||
*buf8 = USBD->cep.CEPDAT_BYTE;
|
||||
buf8++;
|
||||
}
|
||||
|
||||
} else {
|
||||
while (count32--) {
|
||||
*buf32 = USBD->EP[ep_idx - 1].ep.EPDAT;
|
||||
buf32++;
|
||||
}
|
||||
buf8 = (uint8_t *)buf32;
|
||||
while (count8--) {
|
||||
*buf8 = USBD->EP[ep_idx - 1].ep.EPDAT_BYTE;
|
||||
buf8++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
__WEAK void usb_dc_low_level_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
__WEAK void usb_dc_low_level_deinit(void)
|
||||
{
|
||||
}
|
||||
|
||||
int usb_dc_init(void)
|
||||
{
|
||||
memset(&usb_dc_cfg, 0, sizeof(struct usb_dc_config_priv));
|
||||
|
||||
usb_dc_low_level_init();
|
||||
|
||||
/* Enable PHY */
|
||||
USBD_ENABLE_PHY();
|
||||
/* wait PHY clock ready */
|
||||
while (1) {
|
||||
USBD->EP[0].EPMPS = 0x20;
|
||||
if (USBD->EP[0].EPMPS == 0x20)
|
||||
break;
|
||||
}
|
||||
#ifdef CONFIG_USB_HS
|
||||
USBD->OPER |= USBD_OPER_HISPDEN_Msk; /* high-speed */
|
||||
#else
|
||||
USBD->OPER &= ~USBD_OPER_HISPDEN_Msk; /* full-speed */
|
||||
#endif
|
||||
/* Reset Address to 0 */
|
||||
USBD_SET_ADDR(0);
|
||||
|
||||
USBD->CEPINTEN = USBD_CEPINTEN_SETUPPKIEN_Msk | USBD_CEPINTEN_TXPKIEN_Msk | USBD_CEPINTEN_RXPKIEN_Msk | USBD_CEPINTEN_STSDONEIEN_Msk;
|
||||
/* Enable BUS interrupt */
|
||||
USBD->BUSINTEN = USBD_BUSINTEN_RSTIEN_Msk | USBD_BUSINTEN_VBUSDETIEN_Msk;
|
||||
/* Enable USB BUS, CEP and EPA global interrupt */
|
||||
USBD->GINTEN = USBD_GINTEN_USBIE_Msk | USBD_GINTEN_CEPIE_Msk;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usb_dc_deinit(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_set_address(const uint8_t addr)
|
||||
{
|
||||
if (addr == 0x00) {
|
||||
}
|
||||
usb_dc_cfg.dev_addr = addr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
|
||||
{
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep_cfg->ep_addr);
|
||||
uint8_t ep_type;
|
||||
uint8_t ep_dir;
|
||||
uint32_t intr;
|
||||
|
||||
if (USB_EP_DIR_IS_OUT(ep_cfg->ep_addr)) {
|
||||
ep_dir = USB_EP_CFG_DIR_OUT;
|
||||
intr = USBD_EPINTEN_RXPKIEN_Msk;
|
||||
usb_dc_cfg.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
|
||||
usb_dc_cfg.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
|
||||
} else {
|
||||
ep_dir = USB_EP_CFG_DIR_IN;
|
||||
intr = USBD_EPINTEN_TXPKIEN_Msk;
|
||||
usb_dc_cfg.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
|
||||
usb_dc_cfg.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
|
||||
}
|
||||
|
||||
if (ep_idx == 0) {
|
||||
/* Control endpoint */
|
||||
USBD->CEPBUFSTART = usb_dc_cfg.bufaddr;
|
||||
USBD->CEPBUFEND = usb_dc_cfg.bufaddr + 64 - 1;
|
||||
usb_dc_cfg.bufaddr += 64;
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (ep_cfg->ep_type) {
|
||||
case 0x01:
|
||||
ep_type = USB_EP_CFG_TYPE_ISO;
|
||||
USBD->EP[ep_idx - 1].EPRSPCTL = (USB_EP_RSPCTL_FLUSH | USB_EP_RSPCTL_MODE_FLY);
|
||||
break;
|
||||
case 0x02:
|
||||
ep_type = USB_EP_CFG_TYPE_BULK;
|
||||
USBD->EP[ep_idx - 1].EPRSPCTL = (USB_EP_RSPCTL_FLUSH | USB_EP_RSPCTL_MODE_AUTO);
|
||||
break;
|
||||
case 0x03:
|
||||
ep_type = USB_EP_CFG_TYPE_INT;
|
||||
USBD->EP[ep_idx - 1].EPRSPCTL = (USB_EP_RSPCTL_FLUSH | USB_EP_RSPCTL_MODE_MANUAL);
|
||||
break;
|
||||
}
|
||||
USBD->EP[ep_idx - 1].EPBUFSTART = usb_dc_cfg.bufaddr;
|
||||
USBD->EP[ep_idx - 1].EPBUFEND = usb_dc_cfg.bufaddr + ep_cfg->ep_mps - 1;
|
||||
USBD->EP[ep_idx - 1].EPMPS = ep_cfg->ep_mps;
|
||||
USBD->EP[ep_idx - 1].EPCFG = (ep_type | ep_dir | USB_EP_CFG_VALID | (ep_idx << 4));
|
||||
USBD->EP[ep_idx - 1].EPINTEN = intr;
|
||||
USBD->GINTEN |= (1 << (USBD_GINTEN_CEPIE_Pos + ep_idx));
|
||||
usb_dc_cfg.bufaddr += ep_cfg->ep_mps;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_ep_close(const uint8_t ep)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_ep_set_stall(const uint8_t ep)
|
||||
{
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep);
|
||||
|
||||
if (ep_idx == 0x00) {
|
||||
USBD_SET_CEP_STATE(USB_CEPCTL_STALL);
|
||||
} else {
|
||||
USBD->EP[ep_idx - 1].EPRSPCTL = (USBD->EP[ep_idx - 1].EPRSPCTL & 0xf7) | USB_EP_RSPCTL_HALT;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_ep_clear_stall(const uint8_t ep)
|
||||
{
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep);
|
||||
|
||||
if (ep_idx == 0x00) {
|
||||
return 0;
|
||||
}
|
||||
USBD->EP[ep_idx - 1].EPRSPCTL = USB_EP_RSPCTL_TOGGLE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes)
|
||||
{
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep);
|
||||
|
||||
if (!data && data_len) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (!data_len) {
|
||||
if (ep_idx == 0x00) {
|
||||
USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
|
||||
} else {
|
||||
USBD->EP[ep_idx - 1].EPRSPCTL = USB_EP_RSPCTL_ZEROLEN;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (data_len > usb_dc_cfg.in_ep[ep_idx].ep_mps) {
|
||||
data_len = usb_dc_cfg.in_ep[ep_idx].ep_mps;
|
||||
}
|
||||
|
||||
if (ep_idx == 0x00) {
|
||||
usb_fifo_write(0, (uint8_t *)data, data_len);
|
||||
USBD->CEPTXCNT = data_len;
|
||||
USBD->CEPCTL = USB_CEPCTL_NAKCLR;
|
||||
} else {
|
||||
while (USBD->EP[ep_idx - 1].EPDATCNT != 0) {
|
||||
}
|
||||
usb_fifo_write(ep_idx, (uint8_t *)data, data_len);
|
||||
USBD->EP[ep_idx - 1].EPTXCNT = data_len;
|
||||
USBD->EP[ep_idx - 1].EPRSPCTL = USB_EP_RSPCTL_SHORTTXEN;
|
||||
}
|
||||
if (ret_bytes) {
|
||||
*ret_bytes = data_len;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_t *read_bytes)
|
||||
{
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep);
|
||||
uint32_t read_count;
|
||||
|
||||
if (!data && max_data_len) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (!max_data_len) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (ep_idx == 0x00) {
|
||||
if (max_data_len == 0x08 && !read_bytes) {
|
||||
*((uint16_t *)(data + 0)) = (uint16_t)(USBD->SETUP1_0 & 0xFFFFUL);
|
||||
*((uint16_t *)(data + 2)) = (uint16_t)(USBD->SETUP3_2 & 0xFFFFUL);
|
||||
*((uint16_t *)(data + 4)) = (uint16_t)(USBD->SETUP5_4 & 0xFFFFUL);
|
||||
*((uint16_t *)(data + 6)) = (uint16_t)(USBD->SETUP7_6 & 0xFFFFUL);
|
||||
} else {
|
||||
read_count = USBD->CEPRXCNT & 0xFFFFUL;
|
||||
read_count = MIN(read_count, max_data_len);
|
||||
|
||||
usb_fifo_read(0, data, read_count);
|
||||
}
|
||||
} else {
|
||||
read_count = USBD->EP[ep_idx - 1].EPDATCNT & 0xFFFFUL;
|
||||
read_count = MIN(read_count, max_data_len);
|
||||
|
||||
usb_fifo_read(ep_idx, data, read_count);
|
||||
}
|
||||
if (read_bytes) {
|
||||
*read_bytes = read_count;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void USBD_IRQHandler(void)
|
||||
{
|
||||
volatile uint32_t IrqStL, IrqSt;
|
||||
IrqStL = USBD->GINTSTS & USBD->GINTEN; /* get interrupt status */
|
||||
if (!IrqStL)
|
||||
return;
|
||||
|
||||
/* USB interrupt */
|
||||
if (IrqStL & USBD_GINTSTS_USBIF_Msk) {
|
||||
IrqSt = USBD->BUSINTSTS & USBD->BUSINTEN;
|
||||
if (IrqSt & USBD_BUSINTSTS_SOFIF_Msk) {
|
||||
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_SOFIF_Msk);
|
||||
}
|
||||
if (IrqSt & USBD_BUSINTSTS_RSTIF_Msk) {
|
||||
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_RSTIF_Msk);
|
||||
|
||||
USBD->DMACNT = 0;
|
||||
USBD->DMACTL = 0x80;
|
||||
USBD->DMACTL = 0x00;
|
||||
for (uint8_t i = 1; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
|
||||
USBD->EP[i - 1].EPRSPCTL = USBD_EPRSPCTL_FLUSH_Msk;
|
||||
}
|
||||
USBD_SET_ADDR(0);
|
||||
USBD_CLR_CEP_INT_FLAG(0x1ffc);
|
||||
usb_dc_cfg.bufaddr = 0;
|
||||
usbd_event_notify_handler(USBD_EVENT_RESET, NULL);
|
||||
}
|
||||
|
||||
if (IrqSt & USBD_BUSINTSTS_RESUMEIF_Msk) {
|
||||
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_RESUMEIF_Msk);
|
||||
}
|
||||
|
||||
if (IrqSt & USBD_BUSINTSTS_SUSPENDIF_Msk) {
|
||||
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_SUSPENDIF_Msk);
|
||||
}
|
||||
|
||||
if (IrqSt & USBD_BUSINTSTS_HISPDIF_Msk) {
|
||||
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_HISPDIF_Msk);
|
||||
}
|
||||
if (IrqSt & USBD_BUSINTSTS_DMADONEIF_Msk) {
|
||||
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_DMADONEIF_Msk);
|
||||
if (USBD->DMACTL & USBD_DMACTL_DMARD_Msk) {
|
||||
}
|
||||
}
|
||||
|
||||
if (IrqSt & USBD_BUSINTSTS_PHYCLKVLDIF_Msk)
|
||||
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_PHYCLKVLDIF_Msk);
|
||||
|
||||
if (IrqSt & USBD_BUSINTSTS_VBUSDETIF_Msk) {
|
||||
if (USBD_IS_ATTACHED()) {
|
||||
/* USB Plug In */
|
||||
USBD_ENABLE_USB();
|
||||
} else {
|
||||
/* USB Un-plug */
|
||||
USBD_DISABLE_USB();
|
||||
}
|
||||
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_VBUSDETIF_Msk);
|
||||
}
|
||||
}
|
||||
if (IrqStL & USBD_GINTSTS_CEPIF_Msk) {
|
||||
IrqSt = USBD->CEPINTSTS & USBD->CEPINTEN;
|
||||
|
||||
if (IrqSt & USBD_CEPINTSTS_SETUPTKIF_Msk) {
|
||||
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_SETUPTKIF_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
if (IrqSt & USBD_CEPINTSTS_OUTTKIF_Msk) {
|
||||
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_OUTTKIF_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
if (IrqSt & USBD_CEPINTSTS_INTKIF_Msk) {
|
||||
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_INTKIF_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
if (IrqSt & USBD_CEPINTSTS_PINGIF_Msk) {
|
||||
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_PINGIF_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
if (IrqSt & USBD_CEPINTSTS_SETUPPKIF_Msk) {
|
||||
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_SETUPPKIF_Msk);
|
||||
usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
|
||||
return;
|
||||
}
|
||||
|
||||
if (IrqSt & USBD_CEPINTSTS_TXPKIF_Msk) {
|
||||
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_TXPKIF_Msk);
|
||||
usbd_event_notify_handler(USBD_EVENT_EP0_IN_NOTIFY, NULL);
|
||||
return;
|
||||
}
|
||||
|
||||
if (IrqSt & USBD_CEPINTSTS_RXPKIF_Msk) {
|
||||
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_RXPKIF_Msk);
|
||||
usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
|
||||
return;
|
||||
}
|
||||
|
||||
if (IrqSt & USBD_CEPINTSTS_NAKIF_Msk) {
|
||||
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_NAKIF_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
if (IrqSt & USBD_CEPINTSTS_STALLIF_Msk) {
|
||||
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STALLIF_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
if (IrqSt & USBD_CEPINTSTS_ERRIF_Msk) {
|
||||
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_ERRIF_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
if (IrqSt & USBD_CEPINTSTS_STSDONEIF_Msk) {
|
||||
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STSDONEIF_Msk);
|
||||
if (usb_dc_cfg.dev_addr > 0) {
|
||||
USBD_SET_ADDR(usb_dc_cfg.dev_addr);
|
||||
usb_dc_cfg.dev_addr = 0;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
if (IrqSt & USBD_CEPINTSTS_BUFFULLIF_Msk) {
|
||||
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_BUFFULLIF_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
if (IrqSt & USBD_CEPINTSTS_BUFEMPTYIF_Msk) {
|
||||
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_BUFEMPTYIF_Msk);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
for (uint8_t ep_idx = 1; ep_idx < USB_NUM_BIDIR_ENDPOINTS; ep_idx++) {
|
||||
if (IrqStL & (0x1UL << (USBD_GINTSTS_CEPIF_Pos + ep_idx))) {
|
||||
IrqSt = USBD->EP[ep_idx - 1].EPINTSTS & USBD->EP[ep_idx - 1].EPINTEN;
|
||||
USBD_CLR_EP_INT_FLAG(ep_idx - 1, IrqSt);
|
||||
if (usb_dc_cfg.in_ep[ep_idx].ep_mps) {
|
||||
usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(0x80 | ep_idx));
|
||||
} else if (usb_dc_cfg.out_ep[ep_idx].ep_mps) {
|
||||
usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(ep_idx & 0x7f));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,540 +0,0 @@
|
||||
#ifndef __USB_NUVOTON_REG_H__
|
||||
#define __USB_NUVOTON_REG_H__
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
union
|
||||
{
|
||||
volatile uint32_t EPDAT;
|
||||
volatile uint8_t EPDAT_BYTE;
|
||||
|
||||
} ep;
|
||||
volatile uint32_t EPINTSTS;
|
||||
volatile uint32_t EPINTEN;
|
||||
volatile const uint32_t EPDATCNT;
|
||||
volatile uint32_t EPRSPCTL;
|
||||
volatile uint32_t EPMPS;
|
||||
volatile uint32_t EPTXCNT;
|
||||
volatile uint32_t EPCFG;
|
||||
volatile uint32_t EPBUFSTART;
|
||||
volatile uint32_t EPBUFEND;
|
||||
|
||||
} USBD_EP_T;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile const uint32_t GINTSTS;
|
||||
uint32_t RESERVE0[1];
|
||||
volatile uint32_t GINTEN;
|
||||
uint32_t RESERVE1[1];
|
||||
volatile uint32_t BUSINTSTS;
|
||||
volatile uint32_t BUSINTEN;
|
||||
volatile uint32_t OPER;
|
||||
volatile const uint32_t FRAMECNT;
|
||||
volatile uint32_t FADDR;
|
||||
volatile uint32_t TEST;
|
||||
union
|
||||
{
|
||||
volatile uint32_t CEPDAT;
|
||||
volatile uint8_t CEPDAT_BYTE;
|
||||
} cep;
|
||||
volatile uint32_t CEPCTL;
|
||||
volatile uint32_t CEPINTEN;
|
||||
volatile uint32_t CEPINTSTS;
|
||||
volatile uint32_t CEPTXCNT;
|
||||
volatile const uint32_t CEPRXCNT;
|
||||
volatile const uint32_t CEPDATCNT;
|
||||
volatile const uint32_t SETUP1_0;
|
||||
volatile const uint32_t SETUP3_2;
|
||||
volatile const uint32_t SETUP5_4;
|
||||
volatile const uint32_t SETUP7_6;
|
||||
volatile uint32_t CEPBUFSTART;
|
||||
volatile uint32_t CEPBUFEND;
|
||||
volatile uint32_t DMACTL;
|
||||
volatile uint32_t DMACNT;
|
||||
USBD_EP_T EP[12];
|
||||
uint32_t RESERVE2[303];
|
||||
volatile uint32_t DMAADDR;
|
||||
volatile uint32_t PHYCTL;
|
||||
|
||||
} USBD_T;
|
||||
|
||||
#define USBD_GINTSTS_USBIF_Pos (0) /*!< USBD GINTSTS: USBIF Position */
|
||||
#define USBD_GINTSTS_USBIF_Msk (0x1ul << USBD_GINTSTS_USBIF_Pos) /*!< USBD GINTSTS: USBIF Mask */
|
||||
|
||||
#define USBD_GINTSTS_CEPIF_Pos (1) /*!< USBD GINTSTS: CEPIF Position */
|
||||
#define USBD_GINTSTS_CEPIF_Msk (0x1ul << USBD_GINTSTS_CEPIF_Pos) /*!< USBD GINTSTS: CEPIF Mask */
|
||||
|
||||
#define USBD_GINTSTS_EPAIF_Pos (2) /*!< USBD GINTSTS: EPAIF Position */
|
||||
#define USBD_GINTSTS_EPAIF_Msk (0x1ul << USBD_GINTSTS_EPAIF_Pos) /*!< USBD GINTSTS: EPAIF Mask */
|
||||
|
||||
#define USBD_GINTSTS_EPBIF_Pos (3) /*!< USBD GINTSTS: EPBIF Position */
|
||||
#define USBD_GINTSTS_EPBIF_Msk (0x1ul << USBD_GINTSTS_EPBIF_Pos) /*!< USBD GINTSTS: EPBIF Mask */
|
||||
|
||||
#define USBD_GINTSTS_EPCIF_Pos (4) /*!< USBD GINTSTS: EPCIF Position */
|
||||
#define USBD_GINTSTS_EPCIF_Msk (0x1ul << USBD_GINTSTS_EPCIF_Pos) /*!< USBD GINTSTS: EPCIF Mask */
|
||||
|
||||
#define USBD_GINTSTS_EPDIF_Pos (5) /*!< USBD GINTSTS: EPDIF Position */
|
||||
#define USBD_GINTSTS_EPDIF_Msk (0x1ul << USBD_GINTSTS_EPDIF_Pos) /*!< USBD GINTSTS: EPDIF Mask */
|
||||
|
||||
#define USBD_GINTSTS_EPEIF_Pos (6) /*!< USBD GINTSTS: EPEIF Position */
|
||||
#define USBD_GINTSTS_EPEIF_Msk (0x1ul << USBD_GINTSTS_EPEIF_Pos) /*!< USBD GINTSTS: EPEIF Mask */
|
||||
|
||||
#define USBD_GINTSTS_EPFIF_Pos (7) /*!< USBD GINTSTS: EPFIF Position */
|
||||
#define USBD_GINTSTS_EPFIF_Msk (0x1ul << USBD_GINTSTS_EPFIF_Pos) /*!< USBD GINTSTS: EPFIF Mask */
|
||||
|
||||
#define USBD_GINTSTS_EPGIF_Pos (8) /*!< USBD GINTSTS: EPGIF Position */
|
||||
#define USBD_GINTSTS_EPGIF_Msk (0x1ul << USBD_GINTSTS_EPGIF_Pos) /*!< USBD GINTSTS: EPGIF Mask */
|
||||
|
||||
#define USBD_GINTSTS_EPHIF_Pos (9) /*!< USBD GINTSTS: EPHIF Position */
|
||||
#define USBD_GINTSTS_EPHIF_Msk (0x1ul << USBD_GINTSTS_EPHIF_Pos) /*!< USBD GINTSTS: EPHIF Mask */
|
||||
|
||||
#define USBD_GINTSTS_EPIIF_Pos (10) /*!< USBD GINTSTS: EPIIF Position */
|
||||
#define USBD_GINTSTS_EPIIF_Msk (0x1ul << USBD_GINTSTS_EPIIF_Pos) /*!< USBD GINTSTS: EPIIF Mask */
|
||||
|
||||
#define USBD_GINTSTS_EPJIF_Pos (11) /*!< USBD GINTSTS: EPJIF Position */
|
||||
#define USBD_GINTSTS_EPJIF_Msk (0x1ul << USBD_GINTSTS_EPJIF_Pos) /*!< USBD GINTSTS: EPJIF Mask */
|
||||
|
||||
#define USBD_GINTSTS_EPKIF_Pos (12) /*!< USBD GINTSTS: EPKIF Position */
|
||||
#define USBD_GINTSTS_EPKIF_Msk (0x1ul << USBD_GINTSTS_EPKIF_Pos) /*!< USBD GINTSTS: EPKIF Mask */
|
||||
|
||||
#define USBD_GINTSTS_EPLIF_Pos (13) /*!< USBD GINTSTS: EPLIF Position */
|
||||
#define USBD_GINTSTS_EPLIF_Msk (0x1ul << USBD_GINTSTS_EPLIF_Pos) /*!< USBD GINTSTS: EPLIF Mask */
|
||||
|
||||
#define USBD_GINTEN_USBIE_Pos (0) /*!< USBD GINTEN: USBIE Position */
|
||||
#define USBD_GINTEN_USBIE_Msk (0x1ul << USBD_GINTEN_USBIE_Pos) /*!< USBD GINTEN: USBIE Mask */
|
||||
|
||||
#define USBD_GINTEN_CEPIE_Pos (1) /*!< USBD GINTEN: CEPIE Position */
|
||||
#define USBD_GINTEN_CEPIE_Msk (0x1ul << USBD_GINTEN_CEPIE_Pos) /*!< USBD GINTEN: CEPIE Mask */
|
||||
|
||||
#define USBD_GINTEN_EPAIE_Pos (2) /*!< USBD GINTEN: EPAIE Position */
|
||||
#define USBD_GINTEN_EPAIE_Msk (0x1ul << USBD_GINTEN_EPAIE_Pos) /*!< USBD GINTEN: EPAIE Mask */
|
||||
|
||||
#define USBD_GINTEN_EPBIE_Pos (3) /*!< USBD GINTEN: EPBIE Position */
|
||||
#define USBD_GINTEN_EPBIE_Msk (0x1ul << USBD_GINTEN_EPBIE_Pos) /*!< USBD GINTEN: EPBIE Mask */
|
||||
|
||||
#define USBD_GINTEN_EPCIE_Pos (4) /*!< USBD GINTEN: EPCIE Position */
|
||||
#define USBD_GINTEN_EPCIE_Msk (0x1ul << USBD_GINTEN_EPCIE_Pos) /*!< USBD GINTEN: EPCIE Mask */
|
||||
|
||||
#define USBD_GINTEN_EPDIE_Pos (5) /*!< USBD GINTEN: EPDIE Position */
|
||||
#define USBD_GINTEN_EPDIE_Msk (0x1ul << USBD_GINTEN_EPDIE_Pos) /*!< USBD GINTEN: EPDIE Mask */
|
||||
|
||||
#define USBD_GINTEN_EPEIE_Pos (6) /*!< USBD GINTEN: EPEIE Position */
|
||||
#define USBD_GINTEN_EPEIE_Msk (0x1ul << USBD_GINTEN_EPEIE_Pos) /*!< USBD GINTEN: EPEIE Mask */
|
||||
|
||||
#define USBD_GINTEN_EPFIE_Pos (7) /*!< USBD GINTEN: EPFIE Position */
|
||||
#define USBD_GINTEN_EPFIE_Msk (0x1ul << USBD_GINTEN_EPFIE_Pos) /*!< USBD GINTEN: EPFIE Mask */
|
||||
|
||||
#define USBD_GINTEN_EPGIE_Pos (8) /*!< USBD GINTEN: EPGIE Position */
|
||||
#define USBD_GINTEN_EPGIE_Msk (0x1ul << USBD_GINTEN_EPGIE_Pos) /*!< USBD GINTEN: EPGIE Mask */
|
||||
|
||||
#define USBD_GINTEN_EPHIE_Pos (9) /*!< USBD GINTEN: EPHIE Position */
|
||||
#define USBD_GINTEN_EPHIE_Msk (0x1ul << USBD_GINTEN_EPHIE_Pos) /*!< USBD GINTEN: EPHIE Mask */
|
||||
|
||||
#define USBD_GINTEN_EPIIE_Pos (10) /*!< USBD GINTEN: EPIIE Position */
|
||||
#define USBD_GINTEN_EPIIE_Msk (0x1ul << USBD_GINTEN_EPIIE_Pos) /*!< USBD GINTEN: EPIIE Mask */
|
||||
|
||||
#define USBD_GINTEN_EPJIE_Pos (11) /*!< USBD GINTEN: EPJIE Position */
|
||||
#define USBD_GINTEN_EPJIE_Msk (0x1ul << USBD_GINTEN_EPJIE_Pos) /*!< USBD GINTEN: EPJIE Mask */
|
||||
|
||||
#define USBD_GINTEN_EPKIE_Pos (12) /*!< USBD GINTEN: EPKIE Position */
|
||||
#define USBD_GINTEN_EPKIE_Msk (0x1ul << USBD_GINTEN_EPKIE_Pos) /*!< USBD GINTEN: EPKIE Mask */
|
||||
|
||||
#define USBD_GINTEN_EPLIE_Pos (13) /*!< USBD GINTEN: EPLIE Position */
|
||||
#define USBD_GINTEN_EPLIE_Msk (0x1ul << USBD_GINTEN_EPLIE_Pos) /*!< USBD GINTEN: EPLIE Mask */
|
||||
|
||||
#define USBD_BUSINTSTS_SOFIF_Pos (0) /*!< USBD BUSINTSTS: SOFIF Position */
|
||||
#define USBD_BUSINTSTS_SOFIF_Msk (0x1ul << USBD_BUSINTSTS_SOFIF_Pos) /*!< USBD BUSINTSTS: SOFIF Mask */
|
||||
|
||||
#define USBD_BUSINTSTS_RSTIF_Pos (1) /*!< USBD BUSINTSTS: RSTIF Position */
|
||||
#define USBD_BUSINTSTS_RSTIF_Msk (0x1ul << USBD_BUSINTSTS_RSTIF_Pos) /*!< USBD BUSINTSTS: RSTIF Mask */
|
||||
|
||||
#define USBD_BUSINTSTS_RESUMEIF_Pos (2) /*!< USBD BUSINTSTS: RESUMEIF Position */
|
||||
#define USBD_BUSINTSTS_RESUMEIF_Msk (0x1ul << USBD_BUSINTSTS_RESUMEIF_Pos) /*!< USBD BUSINTSTS: RESUMEIF Mask */
|
||||
|
||||
#define USBD_BUSINTSTS_SUSPENDIF_Pos (3) /*!< USBD BUSINTSTS: SUSPENDIF Position */
|
||||
#define USBD_BUSINTSTS_SUSPENDIF_Msk (0x1ul << USBD_BUSINTSTS_SUSPENDIF_Pos) /*!< USBD BUSINTSTS: SUSPENDIF Mask */
|
||||
|
||||
#define USBD_BUSINTSTS_HISPDIF_Pos (4) /*!< USBD BUSINTSTS: HISPDIF Position */
|
||||
#define USBD_BUSINTSTS_HISPDIF_Msk (0x1ul << USBD_BUSINTSTS_HISPDIF_Pos) /*!< USBD BUSINTSTS: HISPDIF Mask */
|
||||
|
||||
#define USBD_BUSINTSTS_DMADONEIF_Pos (5) /*!< USBD BUSINTSTS: DMADONEIF Position */
|
||||
#define USBD_BUSINTSTS_DMADONEIF_Msk (0x1ul << USBD_BUSINTSTS_DMADONEIF_Pos) /*!< USBD BUSINTSTS: DMADONEIF Mask */
|
||||
|
||||
#define USBD_BUSINTSTS_PHYCLKVLDIF_Pos (6) /*!< USBD BUSINTSTS: PHYCLKVLDIF Position */
|
||||
#define USBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << USBD_BUSINTSTS_PHYCLKVLDIF_Pos) /*!< USBD BUSINTSTS: PHYCLKVLDIF Mask */
|
||||
|
||||
#define USBD_BUSINTSTS_VBUSDETIF_Pos (8) /*!< USBD BUSINTSTS: VBUSDETIF Position */
|
||||
#define USBD_BUSINTSTS_VBUSDETIF_Msk (0x1ul << USBD_BUSINTSTS_VBUSDETIF_Pos) /*!< USBD BUSINTSTS: VBUSDETIF Mask */
|
||||
|
||||
#define USBD_BUSINTEN_SOFIEN_Pos (0) /*!< USBD BUSINTEN: SOFIEN Position */
|
||||
#define USBD_BUSINTEN_SOFIEN_Msk (0x1ul << USBD_BUSINTEN_SOFIEN_Pos) /*!< USBD BUSINTEN: SOFIEN Mask */
|
||||
|
||||
#define USBD_BUSINTEN_RSTIEN_Pos (1) /*!< USBD BUSINTEN: RSTIEN Position */
|
||||
#define USBD_BUSINTEN_RSTIEN_Msk (0x1ul << USBD_BUSINTEN_RSTIEN_Pos) /*!< USBD BUSINTEN: RSTIEN Mask */
|
||||
|
||||
#define USBD_BUSINTEN_RESUMEIEN_Pos (2) /*!< USBD BUSINTEN: RESUMEIEN Position */
|
||||
#define USBD_BUSINTEN_RESUMEIEN_Msk (0x1ul << USBD_BUSINTEN_RESUMEIEN_Pos) /*!< USBD BUSINTEN: RESUMEIEN Mask */
|
||||
|
||||
#define USBD_BUSINTEN_SUSPENDIEN_Pos (3) /*!< USBD BUSINTEN: SUSPENDIEN Position */
|
||||
#define USBD_BUSINTEN_SUSPENDIEN_Msk (0x1ul << USBD_BUSINTEN_SUSPENDIEN_Pos) /*!< USBD BUSINTEN: SUSPENDIEN Mask */
|
||||
|
||||
#define USBD_BUSINTEN_HISPDIEN_Pos (4) /*!< USBD BUSINTEN: HISPDIEN Position */
|
||||
#define USBD_BUSINTEN_HISPDIEN_Msk (0x1ul << USBD_BUSINTEN_HISPDIEN_Pos) /*!< USBD BUSINTEN: HISPDIEN Mask */
|
||||
|
||||
#define USBD_BUSINTEN_DMADONEIEN_Pos (5) /*!< USBD BUSINTEN: DMADONEIEN Position */
|
||||
#define USBD_BUSINTEN_DMADONEIEN_Msk (0x1ul << USBD_BUSINTEN_DMADONEIEN_Pos) /*!< USBD BUSINTEN: DMADONEIEN Mask */
|
||||
|
||||
#define USBD_BUSINTEN_PHYCLKVLDIEN_Pos (6) /*!< USBD BUSINTEN: PHYCLKVLDIEN Position */
|
||||
#define USBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << USBD_BUSINTEN_PHYCLKVLDIEN_Pos) /*!< USBD BUSINTEN: PHYCLKVLDIEN Mask */
|
||||
|
||||
#define USBD_BUSINTEN_VBUSDETIEN_Pos (8) /*!< USBD BUSINTEN: VBUSDETIEN Position */
|
||||
#define USBD_BUSINTEN_VBUSDETIEN_Msk (0x1ul << USBD_BUSINTEN_VBUSDETIEN_Pos) /*!< USBD BUSINTEN: VBUSDETIEN Mask */
|
||||
|
||||
#define USBD_OPER_RESUMEEN_Pos (0) /*!< USBD OPER: RESUMEEN Position */
|
||||
#define USBD_OPER_RESUMEEN_Msk (0x1ul << USBD_OPER_RESUMEEN_Pos) /*!< USBD OPER: RESUMEEN Mask */
|
||||
|
||||
#define USBD_OPER_HISPDEN_Pos (1) /*!< USBD OPER: HISPDEN Position */
|
||||
#define USBD_OPER_HISPDEN_Msk (0x1ul << USBD_OPER_HISPDEN_Pos) /*!< USBD OPER: HISPDEN Mask */
|
||||
|
||||
#define USBD_OPER_CURSPD_Pos (2) /*!< USBD OPER: CURSPD Position */
|
||||
#define USBD_OPER_CURSPD_Msk (0x1ul << USBD_OPER_CURSPD_Pos) /*!< USBD OPER: CURSPD Mask */
|
||||
|
||||
#define USBD_FRAMECNT_MFRAMECNT_Pos (0) /*!< USBD FRAMECNT: MFRAMECNT Position */
|
||||
#define USBD_FRAMECNT_MFRAMECNT_Msk (0x7ul << USBD_FRAMECNT_MFRAMECNT_Pos) /*!< USBD FRAMECNT: MFRAMECNT Mask */
|
||||
|
||||
#define USBD_FRAMECNT_FRAMECNT_Pos (3) /*!< USBD FRAMECNT: FRAMECNT Position */
|
||||
#define USBD_FRAMECNT_FRAMECNT_Msk (0x7fful << USBD_FRAMECNT_FRAMECNT_Pos) /*!< USBD FRAMECNT: FRAMECNT Mask */
|
||||
|
||||
#define USBD_FADDR_FADDR_Pos (0) /*!< USBD FADDR: FADDR Position */
|
||||
#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD FADDR: FADDR Mask */
|
||||
|
||||
#define USBD_TEST_TESTMODE_Pos (0) /*!< USBD TEST: TESTMODE Position */
|
||||
#define USBD_TEST_TESTMODE_Msk (0x7ul << USBD_TEST_TESTMODE_Pos) /*!< USBD TEST: TESTMODE Mask */
|
||||
|
||||
#define USBD_CEPDAT_DAT_Pos (0) /*!< USBD CEPDAT: DAT Position */
|
||||
#define USBD_CEPDAT_DAT_Msk (0xfffffffful << USBD_CEPDAT_DAT_Pos) /*!< USBD CEPDAT: DAT Mask */
|
||||
|
||||
#define USBD_CEPCTL_NAKCLR_Pos (0) /*!< USBD CEPCTL: NAKCLR Position */
|
||||
#define USBD_CEPCTL_NAKCLR_Msk (0x1ul << USBD_CEPCTL_NAKCLR_Pos) /*!< USBD CEPCTL: NAKCLR Mask */
|
||||
|
||||
#define USBD_CEPCTL_STALLEN_Pos (1) /*!< USBD CEPCTL: STALLEN Position */
|
||||
#define USBD_CEPCTL_STALLEN_Msk (0x1ul << USBD_CEPCTL_STALLEN_Pos) /*!< USBD CEPCTL: STALLEN Mask */
|
||||
|
||||
#define USBD_CEPCTL_ZEROLEN_Pos (2) /*!< USBD CEPCTL: ZEROLEN Position */
|
||||
#define USBD_CEPCTL_ZEROLEN_Msk (0x1ul << USBD_CEPCTL_ZEROLEN_Pos) /*!< USBD CEPCTL: ZEROLEN Mask */
|
||||
|
||||
#define USBD_CEPCTL_FLUSH_Pos (3) /*!< USBD CEPCTL: FLUSH Position */
|
||||
#define USBD_CEPCTL_FLUSH_Msk (0x1ul << USBD_CEPCTL_FLUSH_Pos) /*!< USBD CEPCTL: FLUSH Mask */
|
||||
|
||||
#define USBD_CEPINTEN_SETUPTKIEN_Pos (0) /*!< USBD CEPINTEN: SETUPTKIEN Position */
|
||||
#define USBD_CEPINTEN_SETUPTKIEN_Msk (0x1ul << USBD_CEPINTEN_SETUPTKIEN_Pos) /*!< USBD CEPINTEN: SETUPTKIEN Mask */
|
||||
|
||||
#define USBD_CEPINTEN_SETUPPKIEN_Pos (1) /*!< USBD CEPINTEN: SETUPPKIEN Position */
|
||||
#define USBD_CEPINTEN_SETUPPKIEN_Msk (0x1ul << USBD_CEPINTEN_SETUPPKIEN_Pos) /*!< USBD CEPINTEN: SETUPPKIEN Mask */
|
||||
|
||||
#define USBD_CEPINTEN_OUTTKIEN_Pos (2) /*!< USBD CEPINTEN: OUTTKIEN Position */
|
||||
#define USBD_CEPINTEN_OUTTKIEN_Msk (0x1ul << USBD_CEPINTEN_OUTTKIEN_Pos) /*!< USBD CEPINTEN: OUTTKIEN Mask */
|
||||
|
||||
#define USBD_CEPINTEN_INTKIEN_Pos (3) /*!< USBD CEPINTEN: INTKIEN Position */
|
||||
#define USBD_CEPINTEN_INTKIEN_Msk (0x1ul << USBD_CEPINTEN_INTKIEN_Pos) /*!< USBD CEPINTEN: INTKIEN Mask */
|
||||
|
||||
#define USBD_CEPINTEN_PINGIEN_Pos (4) /*!< USBD CEPINTEN: PINGIEN Position */
|
||||
#define USBD_CEPINTEN_PINGIEN_Msk (0x1ul << USBD_CEPINTEN_PINGIEN_Pos) /*!< USBD CEPINTEN: PINGIEN Mask */
|
||||
|
||||
#define USBD_CEPINTEN_TXPKIEN_Pos (5) /*!< USBD CEPINTEN: TXPKIEN Position */
|
||||
#define USBD_CEPINTEN_TXPKIEN_Msk (0x1ul << USBD_CEPINTEN_TXPKIEN_Pos) /*!< USBD CEPINTEN: TXPKIEN Mask */
|
||||
|
||||
#define USBD_CEPINTEN_RXPKIEN_Pos (6) /*!< USBD CEPINTEN: RXPKIEN Position */
|
||||
#define USBD_CEPINTEN_RXPKIEN_Msk (0x1ul << USBD_CEPINTEN_RXPKIEN_Pos) /*!< USBD CEPINTEN: RXPKIEN Mask */
|
||||
|
||||
#define USBD_CEPINTEN_NAKIEN_Pos (7) /*!< USBD CEPINTEN: NAKIEN Position */
|
||||
#define USBD_CEPINTEN_NAKIEN_Msk (0x1ul << USBD_CEPINTEN_NAKIEN_Pos) /*!< USBD CEPINTEN: NAKIEN Mask */
|
||||
|
||||
#define USBD_CEPINTEN_STALLIEN_Pos (8) /*!< USBD CEPINTEN: STALLIEN Position */
|
||||
#define USBD_CEPINTEN_STALLIEN_Msk (0x1ul << USBD_CEPINTEN_STALLIEN_Pos) /*!< USBD CEPINTEN: STALLIEN Mask */
|
||||
|
||||
#define USBD_CEPINTEN_ERRIEN_Pos (9) /*!< USBD CEPINTEN: ERRIEN Position */
|
||||
#define USBD_CEPINTEN_ERRIEN_Msk (0x1ul << USBD_CEPINTEN_ERRIEN_Pos) /*!< USBD CEPINTEN: ERRIEN Mask */
|
||||
|
||||
#define USBD_CEPINTEN_STSDONEIEN_Pos (10) /*!< USBD CEPINTEN: STSDONEIEN Position */
|
||||
#define USBD_CEPINTEN_STSDONEIEN_Msk (0x1ul << USBD_CEPINTEN_STSDONEIEN_Pos) /*!< USBD CEPINTEN: STSDONEIEN Mask */
|
||||
|
||||
#define USBD_CEPINTEN_BUFFULLIEN_Pos (11) /*!< USBD CEPINTEN: BUFFULLIEN Position */
|
||||
#define USBD_CEPINTEN_BUFFULLIEN_Msk (0x1ul << USBD_CEPINTEN_BUFFULLIEN_Pos) /*!< USBD CEPINTEN: BUFFULLIEN Mask */
|
||||
|
||||
#define USBD_CEPINTEN_BUFEMPTYIEN_Pos (12) /*!< USBD CEPINTEN: BUFEMPTYIEN Position */
|
||||
#define USBD_CEPINTEN_BUFEMPTYIEN_Msk (0x1ul << USBD_CEPINTEN_BUFEMPTYIEN_Pos) /*!< USBD CEPINTEN: BUFEMPTYIEN Mask */
|
||||
|
||||
#define USBD_CEPINTSTS_SETUPTKIF_Pos (0) /*!< USBD CEPINTSTS: SETUPTKIF Position */
|
||||
#define USBD_CEPINTSTS_SETUPTKIF_Msk (0x1ul << USBD_CEPINTSTS_SETUPTKIF_Pos) /*!< USBD CEPINTSTS: SETUPTKIF Mask */
|
||||
|
||||
#define USBD_CEPINTSTS_SETUPPKIF_Pos (1) /*!< USBD CEPINTSTS: SETUPPKIF Position */
|
||||
#define USBD_CEPINTSTS_SETUPPKIF_Msk (0x1ul << USBD_CEPINTSTS_SETUPPKIF_Pos) /*!< USBD CEPINTSTS: SETUPPKIF Mask */
|
||||
|
||||
#define USBD_CEPINTSTS_OUTTKIF_Pos (2) /*!< USBD CEPINTSTS: OUTTKIF Position */
|
||||
#define USBD_CEPINTSTS_OUTTKIF_Msk (0x1ul << USBD_CEPINTSTS_OUTTKIF_Pos) /*!< USBD CEPINTSTS: OUTTKIF Mask */
|
||||
|
||||
#define USBD_CEPINTSTS_INTKIF_Pos (3) /*!< USBD CEPINTSTS: INTKIF Position */
|
||||
#define USBD_CEPINTSTS_INTKIF_Msk (0x1ul << USBD_CEPINTSTS_INTKIF_Pos) /*!< USBD CEPINTSTS: INTKIF Mask */
|
||||
|
||||
#define USBD_CEPINTSTS_PINGIF_Pos (4) /*!< USBD CEPINTSTS: PINGIF Position */
|
||||
#define USBD_CEPINTSTS_PINGIF_Msk (0x1ul << USBD_CEPINTSTS_PINGIF_Pos) /*!< USBD CEPINTSTS: PINGIF Mask */
|
||||
|
||||
#define USBD_CEPINTSTS_TXPKIF_Pos (5) /*!< USBD CEPINTSTS: TXPKIF Position */
|
||||
#define USBD_CEPINTSTS_TXPKIF_Msk (0x1ul << USBD_CEPINTSTS_TXPKIF_Pos) /*!< USBD CEPINTSTS: TXPKIF Mask */
|
||||
|
||||
#define USBD_CEPINTSTS_RXPKIF_Pos (6) /*!< USBD CEPINTSTS: RXPKIF Position */
|
||||
#define USBD_CEPINTSTS_RXPKIF_Msk (0x1ul << USBD_CEPINTSTS_RXPKIF_Pos) /*!< USBD CEPINTSTS: RXPKIF Mask */
|
||||
|
||||
#define USBD_CEPINTSTS_NAKIF_Pos (7) /*!< USBD CEPINTSTS: NAKIF Position */
|
||||
#define USBD_CEPINTSTS_NAKIF_Msk (0x1ul << USBD_CEPINTSTS_NAKIF_Pos) /*!< USBD CEPINTSTS: NAKIF Mask */
|
||||
|
||||
#define USBD_CEPINTSTS_STALLIF_Pos (8) /*!< USBD CEPINTSTS: STALLIF Position */
|
||||
#define USBD_CEPINTSTS_STALLIF_Msk (0x1ul << USBD_CEPINTSTS_STALLIF_Pos) /*!< USBD CEPINTSTS: STALLIF Mask */
|
||||
|
||||
#define USBD_CEPINTSTS_ERRIF_Pos (9) /*!< USBD CEPINTSTS: ERRIF Position */
|
||||
#define USBD_CEPINTSTS_ERRIF_Msk (0x1ul << USBD_CEPINTSTS_ERRIF_Pos) /*!< USBD CEPINTSTS: ERRIF Mask */
|
||||
|
||||
#define USBD_CEPINTSTS_STSDONEIF_Pos (10) /*!< USBD CEPINTSTS: STSDONEIF Position */
|
||||
#define USBD_CEPINTSTS_STSDONEIF_Msk (0x1ul << USBD_CEPINTSTS_STSDONEIF_Pos) /*!< USBD CEPINTSTS: STSDONEIF Mask */
|
||||
|
||||
#define USBD_CEPINTSTS_BUFFULLIF_Pos (11) /*!< USBD CEPINTSTS: BUFFULLIF Position */
|
||||
#define USBD_CEPINTSTS_BUFFULLIF_Msk (0x1ul << USBD_CEPINTSTS_BUFFULLIF_Pos) /*!< USBD CEPINTSTS: BUFFULLIF Mask */
|
||||
|
||||
#define USBD_CEPINTSTS_BUFEMPTYIF_Pos (12) /*!< USBD CEPINTSTS: BUFEMPTYIF Position */
|
||||
#define USBD_CEPINTSTS_BUFEMPTYIF_Msk (0x1ul << USBD_CEPINTSTS_BUFEMPTYIF_Pos) /*!< USBD CEPINTSTS: BUFEMPTYIF Mask */
|
||||
|
||||
#define USBD_CEPTXCNT_TXCNT_Pos (0) /*!< USBD CEPTXCNT: TXCNT Position */
|
||||
#define USBD_CEPTXCNT_TXCNT_Msk (0xfful << USBD_CEPTXCNT_TXCNT_Pos) /*!< USBD CEPTXCNT: TXCNT Mask */
|
||||
|
||||
#define USBD_CEPRXCNT_RXCNT_Pos (0) /*!< USBD CEPRXCNT: RXCNT Position */
|
||||
#define USBD_CEPRXCNT_RXCNT_Msk (0xfful << USBD_CEPRXCNT_RXCNT_Pos) /*!< USBD CEPRXCNT: RXCNT Mask */
|
||||
|
||||
#define USBD_CEPDATCNT_DATCNT_Pos (0) /*!< USBD CEPDATCNT: DATCNT Position */
|
||||
#define USBD_CEPDATCNT_DATCNT_Msk (0xfffful << USBD_CEPDATCNT_DATCNT_Pos) /*!< USBD CEPDATCNT: DATCNT Mask */
|
||||
|
||||
#define USBD_SETUP1_0_SETUP0_Pos (0) /*!< USBD SETUP1_0: SETUP0 Position */
|
||||
#define USBD_SETUP1_0_SETUP0_Msk (0xfful << USBD_SETUP1_0_SETUP0_Pos) /*!< USBD SETUP1_0: SETUP0 Mask */
|
||||
|
||||
#define USBD_SETUP1_0_SETUP1_Pos (8) /*!< USBD SETUP1_0: SETUP1 Position */
|
||||
#define USBD_SETUP1_0_SETUP1_Msk (0xfful << USBD_SETUP1_0_SETUP1_Pos) /*!< USBD SETUP1_0: SETUP1 Mask */
|
||||
|
||||
#define USBD_SETUP3_2_SETUP2_Pos (0) /*!< USBD SETUP3_2: SETUP2 Position */
|
||||
#define USBD_SETUP3_2_SETUP2_Msk (0xfful << USBD_SETUP3_2_SETUP2_Pos) /*!< USBD SETUP3_2: SETUP2 Mask */
|
||||
|
||||
#define USBD_SETUP3_2_SETUP3_Pos (8) /*!< USBD SETUP3_2: SETUP3 Position */
|
||||
#define USBD_SETUP3_2_SETUP3_Msk (0xfful << USBD_SETUP3_2_SETUP3_Pos) /*!< USBD SETUP3_2: SETUP3 Mask */
|
||||
|
||||
#define USBD_SETUP5_4_SETUP4_Pos (0) /*!< USBD SETUP5_4: SETUP4 Position */
|
||||
#define USBD_SETUP5_4_SETUP4_Msk (0xfful << USBD_SETUP5_4_SETUP4_Pos) /*!< USBD SETUP5_4: SETUP4 Mask */
|
||||
|
||||
#define USBD_SETUP5_4_SETUP5_Pos (8) /*!< USBD SETUP5_4: SETUP5 Position */
|
||||
#define USBD_SETUP5_4_SETUP5_Msk (0xfful << USBD_SETUP5_4_SETUP5_Pos) /*!< USBD SETUP5_4: SETUP5 Mask */
|
||||
|
||||
#define USBD_SETUP7_6_SETUP6_Pos (0) /*!< USBD SETUP7_6: SETUP6 Position */
|
||||
#define USBD_SETUP7_6_SETUP6_Msk (0xfful << USBD_SETUP7_6_SETUP6_Pos) /*!< USBD SETUP7_6: SETUP6 Mask */
|
||||
|
||||
#define USBD_SETUP7_6_SETUP7_Pos (8) /*!< USBD SETUP7_6: SETUP7 Position */
|
||||
#define USBD_SETUP7_6_SETUP7_Msk (0xfful << USBD_SETUP7_6_SETUP7_Pos) /*!< USBD SETUP7_6: SETUP7 Mask */
|
||||
|
||||
#define USBD_CEPBUFSTART_SADDR_Pos (0) /*!< USBD CEPBUFSTART: SADDR Position */
|
||||
#define USBD_CEPBUFSTART_SADDR_Msk (0xffful << USBD_CEPBUFSTART_SADDR_Pos) /*!< USBD CEPBUFSTART: SADDR Mask */
|
||||
|
||||
#define USBD_CEPBUFEND_EADDR_Pos (0) /*!< USBD CEPBUFEND: EADDR Position */
|
||||
#define USBD_CEPBUFEND_EADDR_Msk (0xffful << USBD_CEPBUFEND_EADDR_Pos) /*!< USBD CEPBUFEND: EADDR Mask */
|
||||
|
||||
#define USBD_DMACTL_EPNUM_Pos (0) /*!< USBD DMACTL: EPNUM Position */
|
||||
#define USBD_DMACTL_EPNUM_Msk (0xful << USBD_DMACTL_EPNUM_Pos) /*!< USBD DMACTL: EPNUM Mask */
|
||||
|
||||
#define USBD_DMACTL_DMARD_Pos (4) /*!< USBD DMACTL: DMARD Position */
|
||||
#define USBD_DMACTL_DMARD_Msk (0x1ul << USBD_DMACTL_DMARD_Pos) /*!< USBD DMACTL: DMARD Mask */
|
||||
|
||||
#define USBD_DMACTL_DMAEN_Pos (5) /*!< USBD DMACTL: DMAEN Position */
|
||||
#define USBD_DMACTL_DMAEN_Msk (0x1ul << USBD_DMACTL_DMAEN_Pos) /*!< USBD DMACTL: DMAEN Mask */
|
||||
|
||||
#define USBD_DMACTL_SGEN_Pos (6) /*!< USBD DMACTL: SGEN Position */
|
||||
#define USBD_DMACTL_SGEN_Msk (0x1ul << USBD_DMACTL_SGEN_Pos) /*!< USBD DMACTL: SGEN Mask */
|
||||
|
||||
#define USBD_DMACTL_DMARST_Pos (7) /*!< USBD DMACTL: DMARST Position */
|
||||
#define USBD_DMACTL_DMARST_Msk (0x1ul << USBD_DMACTL_DMARST_Pos) /*!< USBD DMACTL: DMARST Mask */
|
||||
|
||||
#define USBD_DMACNT_DMACNT_Pos (0) /*!< USBD DMACNT: DMACNT Position */
|
||||
#define USBD_DMACNT_DMACNT_Msk (0xffffful << USBD_DMACNT_DMACNT_Pos) /*!< USBD DMACNT: DMACNT Mask */
|
||||
|
||||
#define USBD_EPDAT_EPDAT_Pos (0) /*!< USBD EPDAT: EPDAT Position */
|
||||
#define USBD_EPDAT_EPDAT_Msk (0xfffffffful << USBD_EPDAT_EPDAT_Pos) /*!< USBD EPDAT: EPDAT Mask */
|
||||
|
||||
#define USBD_EPINTSTS_BUFFULLIF_Pos (0) /*!< USBD EPINTSTS: BUFFULLIF Position */
|
||||
#define USBD_EPINTSTS_BUFFULLIF_Msk (0x1ul << USBD_EPINTSTS_BUFFULLIF_Pos) /*!< USBD EPINTSTS: BUFFULLIF Mask */
|
||||
|
||||
#define USBD_EPINTSTS_BUFEMPTYIF_Pos (1) /*!< USBD EPINTSTS: BUFEMPTYIF Position */
|
||||
#define USBD_EPINTSTS_BUFEMPTYIF_Msk (0x1ul << USBD_EPINTSTS_BUFEMPTYIF_Pos) /*!< USBD EPINTSTS: BUFEMPTYIF Mask */
|
||||
|
||||
#define USBD_EPINTSTS_SHORTTXIF_Pos (2) /*!< USBD EPINTSTS: SHORTTXIF Position */
|
||||
#define USBD_EPINTSTS_SHORTTXIF_Msk (0x1ul << USBD_EPINTSTS_SHORTTXIF_Pos) /*!< USBD EPINTSTS: SHORTTXIF Mask */
|
||||
|
||||
#define USBD_EPINTSTS_TXPKIF_Pos (3) /*!< USBD EPINTSTS: TXPKIF Position */
|
||||
#define USBD_EPINTSTS_TXPKIF_Msk (0x1ul << USBD_EPINTSTS_TXPKIF_Pos) /*!< USBD EPINTSTS: TXPKIF Mask */
|
||||
|
||||
#define USBD_EPINTSTS_RXPKIF_Pos (4) /*!< USBD EPINTSTS: RXPKIF Position */
|
||||
#define USBD_EPINTSTS_RXPKIF_Msk (0x1ul << USBD_EPINTSTS_RXPKIF_Pos) /*!< USBD EPINTSTS: RXPKIF Mask */
|
||||
|
||||
#define USBD_EPINTSTS_OUTTKIF_Pos (5) /*!< USBD EPINTSTS: OUTTKIF Position */
|
||||
#define USBD_EPINTSTS_OUTTKIF_Msk (0x1ul << USBD_EPINTSTS_OUTTKIF_Pos) /*!< USBD EPINTSTS: OUTTKIF Mask */
|
||||
|
||||
#define USBD_EPINTSTS_INTKIF_Pos (6) /*!< USBD EPINTSTS: INTKIF Position */
|
||||
#define USBD_EPINTSTS_INTKIF_Msk (0x1ul << USBD_EPINTSTS_INTKIF_Pos) /*!< USBD EPINTSTS: INTKIF Mask */
|
||||
|
||||
#define USBD_EPINTSTS_PINGIF_Pos (7) /*!< USBD EPINTSTS: PINGIF Position */
|
||||
#define USBD_EPINTSTS_PINGIF_Msk (0x1ul << USBD_EPINTSTS_PINGIF_Pos) /*!< USBD EPINTSTS: PINGIF Mask */
|
||||
|
||||
#define USBD_EPINTSTS_NAKIF_Pos (8) /*!< USBD EPINTSTS: NAKIF Position */
|
||||
#define USBD_EPINTSTS_NAKIF_Msk (0x1ul << USBD_EPINTSTS_NAKIF_Pos) /*!< USBD EPINTSTS: NAKIF Mask */
|
||||
|
||||
#define USBD_EPINTSTS_STALLIF_Pos (9) /*!< USBD EPINTSTS: STALLIF Position */
|
||||
#define USBD_EPINTSTS_STALLIF_Msk (0x1ul << USBD_EPINTSTS_STALLIF_Pos) /*!< USBD EPINTSTS: STALLIF Mask */
|
||||
|
||||
#define USBD_EPINTSTS_NYETIF_Pos (10) /*!< USBD EPINTSTS: NYETIF Position */
|
||||
#define USBD_EPINTSTS_NYETIF_Msk (0x1ul << USBD_EPINTSTS_NYETIF_Pos) /*!< USBD EPINTSTS: NYETIF Mask */
|
||||
|
||||
#define USBD_EPINTSTS_ERRIF_Pos (11) /*!< USBD EPINTSTS: ERRIF Position */
|
||||
#define USBD_EPINTSTS_ERRIF_Msk (0x1ul << USBD_EPINTSTS_ERRIF_Pos) /*!< USBD EPINTSTS: ERRIF Mask */
|
||||
|
||||
#define USBD_EPINTSTS_SHORTRXIF_Pos (12) /*!< USBD EPINTSTS: SHORTRXIF Position */
|
||||
#define USBD_EPINTSTS_SHORTRXIF_Msk (0x1ul << USBD_EPINTSTS_SHORTRXIF_Pos) /*!< USBD EPINTSTS: SHORTRXIF Mask */
|
||||
|
||||
#define USBD_EPINTEN_BUFFULLIEN_Pos (0) /*!< USBD EPINTEN: BUFFULLIEN Position */
|
||||
#define USBD_EPINTEN_BUFFULLIEN_Msk (0x1ul << USBD_EPINTEN_BUFFULLIEN_Pos) /*!< USBD EPINTEN: BUFFULLIEN Mask */
|
||||
|
||||
#define USBD_EPINTEN_BUFEMPTYIEN_Pos (1) /*!< USBD EPINTEN: BUFEMPTYIEN Position */
|
||||
#define USBD_EPINTEN_BUFEMPTYIEN_Msk (0x1ul << USBD_EPINTEN_BUFEMPTYIEN_Pos) /*!< USBD EPINTEN: BUFEMPTYIEN Mask */
|
||||
|
||||
#define USBD_EPINTEN_SHORTTXIEN_Pos (2) /*!< USBD EPINTEN: SHORTTXIEN Position */
|
||||
#define USBD_EPINTEN_SHORTTXIEN_Msk (0x1ul << USBD_EPINTEN_SHORTTXIEN_Pos) /*!< USBD EPINTEN: SHORTTXIEN Mask */
|
||||
|
||||
#define USBD_EPINTEN_TXPKIEN_Pos (3) /*!< USBD EPINTEN: TXPKIEN Position */
|
||||
#define USBD_EPINTEN_TXPKIEN_Msk (0x1ul << USBD_EPINTEN_TXPKIEN_Pos) /*!< USBD EPINTEN: TXPKIEN Mask */
|
||||
|
||||
#define USBD_EPINTEN_RXPKIEN_Pos (4) /*!< USBD EPINTEN: RXPKIEN Position */
|
||||
#define USBD_EPINTEN_RXPKIEN_Msk (0x1ul << USBD_EPINTEN_RXPKIEN_Pos) /*!< USBD EPINTEN: RXPKIEN Mask */
|
||||
|
||||
#define USBD_EPINTEN_OUTTKIEN_Pos (5) /*!< USBD EPINTEN: OUTTKIEN Position */
|
||||
#define USBD_EPINTEN_OUTTKIEN_Msk (0x1ul << USBD_EPINTEN_OUTTKIEN_Pos) /*!< USBD EPINTEN: OUTTKIEN Mask */
|
||||
|
||||
#define USBD_EPINTEN_INTKIEN_Pos (6) /*!< USBD EPINTEN: INTKIEN Position */
|
||||
#define USBD_EPINTEN_INTKIEN_Msk (0x1ul << USBD_EPINTEN_INTKIEN_Pos) /*!< USBD EPINTEN: INTKIEN Mask */
|
||||
|
||||
#define USBD_EPINTEN_PINGIEN_Pos (7) /*!< USBD EPINTEN: PINGIEN Position */
|
||||
#define USBD_EPINTEN_PINGIEN_Msk (0x1ul << USBD_EPINTEN_PINGIEN_Pos) /*!< USBD EPINTEN: PINGIEN Mask */
|
||||
|
||||
#define USBD_EPINTEN_NAKIEN_Pos (8) /*!< USBD EPINTEN: NAKIEN Position */
|
||||
#define USBD_EPINTEN_NAKIEN_Msk (0x1ul << USBD_EPINTEN_NAKIEN_Pos) /*!< USBD EPINTEN: NAKIEN Mask */
|
||||
|
||||
#define USBD_EPINTEN_STALLIEN_Pos (9) /*!< USBD EPINTEN: STALLIEN Position */
|
||||
#define USBD_EPINTEN_STALLIEN_Msk (0x1ul << USBD_EPINTEN_STALLIEN_Pos) /*!< USBD EPINTEN: STALLIEN Mask */
|
||||
|
||||
#define USBD_EPINTEN_NYETIEN_Pos (10) /*!< USBD EPINTEN: NYETIEN Position */
|
||||
#define USBD_EPINTEN_NYETIEN_Msk (0x1ul << USBD_EPINTEN_NYETIEN_Pos) /*!< USBD EPINTEN: NYETIEN Mask */
|
||||
|
||||
#define USBD_EPINTEN_ERRIEN_Pos (11) /*!< USBD EPINTEN: ERRIEN Position */
|
||||
#define USBD_EPINTEN_ERRIEN_Msk (0x1ul << USBD_EPINTEN_ERRIEN_Pos) /*!< USBD EPINTEN: ERRIEN Mask */
|
||||
|
||||
#define USBD_EPINTEN_SHORTRXIEN_Pos (12) /*!< USBD EPINTEN: SHORTRXIEN Position */
|
||||
#define USBD_EPINTEN_SHORTRXIEN_Msk (0x1ul << USBD_EPINTEN_SHORTRXIEN_Pos) /*!< USBD EPINTEN: SHORTRXIEN Mask */
|
||||
|
||||
#define USBD_EPDATCNT_DATCNT_Pos (0) /*!< USBD EPDATCNT: DATCNT Position */
|
||||
#define USBD_EPDATCNT_DATCNT_Msk (0xfffful << USBD_EPDATCNT_DATCNT_Pos) /*!< USBD EPDATCNT: DATCNT Mask */
|
||||
|
||||
#define USBD_EPDATCNT_DMALOOP_Pos (16) /*!< USBD EPDATCNT: DMALOOP Position */
|
||||
#define USBD_EPDATCNT_DMALOOP_Msk (0x7ffful << USBD_EPDATCNT_DMALOOP_Pos) /*!< USBD EPDATCNT: DMALOOP Mask */
|
||||
|
||||
#define USBD_EPRSPCTL_FLUSH_Pos (0) /*!< USBD EPRSPCTL: FLUSH Position */
|
||||
#define USBD_EPRSPCTL_FLUSH_Msk (0x1ul << USBD_EPRSPCTL_FLUSH_Pos) /*!< USBD EPRSPCTL: FLUSH Mask */
|
||||
|
||||
#define USBD_EPRSPCTL_MODE_Pos (1) /*!< USBD EPRSPCTL: MODE Position */
|
||||
#define USBD_EPRSPCTL_MODE_Msk (0x3ul << USBD_EPRSPCTL_MODE_Pos) /*!< USBD EPRSPCTL: MODE Mask */
|
||||
|
||||
#define USBD_EPRSPCTL_TOGGLE_Pos (3) /*!< USBD EPRSPCTL: TOGGLE Position */
|
||||
#define USBD_EPRSPCTL_TOGGLE_Msk (0x1ul << USBD_EPRSPCTL_TOGGLE_Pos) /*!< USBD EPRSPCTL: TOGGLE Mask */
|
||||
|
||||
#define USBD_EPRSPCTL_HALT_Pos (4) /*!< USBD EPRSPCTL: HALT Position */
|
||||
#define USBD_EPRSPCTL_HALT_Msk (0x1ul << USBD_EPRSPCTL_HALT_Pos) /*!< USBD EPRSPCTL: HALT Mask */
|
||||
|
||||
#define USBD_EPRSPCTL_ZEROLEN_Pos (5) /*!< USBD EPRSPCTL: ZEROLEN Position */
|
||||
#define USBD_EPRSPCTL_ZEROLEN_Msk (0x1ul << USBD_EPRSPCTL_ZEROLEN_Pos) /*!< USBD EPRSPCTL: ZEROLEN Mask */
|
||||
|
||||
#define USBD_EPRSPCTL_SHORTTXEN_Pos (6) /*!< USBD EPRSPCTL: SHORTTXEN Position */
|
||||
#define USBD_EPRSPCTL_SHORTTXEN_Msk (0x1ul << USBD_EPRSPCTL_SHORTTXEN_Pos) /*!< USBD EPRSPCTL: SHORTTXEN Mask */
|
||||
|
||||
#define USBD_EPRSPCTL_DISBUF_Pos (7) /*!< USBD EPRSPCTL: DISBUF Position */
|
||||
#define USBD_EPRSPCTL_DISBUF_Msk (0x1ul << USBD_EPRSPCTL_DISBUF_Pos) /*!< USBD EPRSPCTL: DISBUF Mask */
|
||||
|
||||
#define USBD_EPMPS_EPMPS_Pos (0) /*!< USBD EPMPS: EPMPS Position */
|
||||
#define USBD_EPMPS_EPMPS_Msk (0x7fful << USBD_EPMPS_EPMPS_Pos) /*!< USBD EPMPS: EPMPS Mask */
|
||||
|
||||
#define USBD_EPTXCNT_TXCNT_Pos (0) /*!< USBD EPTXCNT: TXCNT Position */
|
||||
#define USBD_EPTXCNT_TXCNT_Msk (0x7fful << USBD_EPTXCNT_TXCNT_Pos) /*!< USBD EPTXCNT: TXCNT Mask */
|
||||
|
||||
#define USBD_EPCFG_EPEN_Pos (0) /*!< USBD EPCFG: EPEN Position */
|
||||
#define USBD_EPCFG_EPEN_Msk (0x1ul << USBD_EPCFG_EPEN_Pos) /*!< USBD EPCFG: EPEN Mask */
|
||||
|
||||
#define USBD_EPCFG_EPTYPE_Pos (1) /*!< USBD EPCFG: EPTYPE Position */
|
||||
#define USBD_EPCFG_EPTYPE_Msk (0x3ul << USBD_EPCFG_EPTYPE_Pos) /*!< USBD EPCFG: EPTYPE Mask */
|
||||
|
||||
#define USBD_EPCFG_EPDIR_Pos (3) /*!< USBD EPCFG: EPDIR Position */
|
||||
#define USBD_EPCFG_EPDIR_Msk (0x1ul << USBD_EPCFG_EPDIR_Pos) /*!< USBD EPCFG: EPDIR Mask */
|
||||
|
||||
#define USBD_EPCFG_EPNUM_Pos (4) /*!< USBD EPCFG: EPNUM Position */
|
||||
#define USBD_EPCFG_EPNUM_Msk (0xful << USBD_EPCFG_EPNUM_Pos) /*!< USBD EPCFG: EPNUM Mask */
|
||||
|
||||
#define USBD_EPBUFSTART_SADDR_Pos (0) /*!< USBD EPBUFSTART: SADDR Position */
|
||||
#define USBD_EPBUFSTART_SADDR_Msk (0xffful << USBD_EPBUFSTART_SADDR_Pos) /*!< USBD EPBUFSTART: SADDR Mask */
|
||||
|
||||
#define USBD_EPBUFEND_EADDR_Pos (0) /*!< USBD EPBUFEND: EADDR Position */
|
||||
#define USBD_EPBUFEND_EADDR_Msk (0xffful << USBD_EPBUFEND_EADDR_Pos) /*!< USBD EPBUFEND: EADDR Mask */
|
||||
|
||||
#define USBD_DMAADDR_DMAADDR_Pos (0) /*!< USBD DMAADDR: DMAADDR Position */
|
||||
#define USBD_DMAADDR_DMAADDR_Msk (0xfffffffful << USBD_DMAADDR_DMAADDR_Pos) /*!< USBD DMAADDR: DMAADDR Mask */
|
||||
|
||||
#define USBD_PHYCTL_DPPUEN_Pos (8) /*!< USBD PHYCTL: DPPUEN Position */
|
||||
#define USBD_PHYCTL_DPPUEN_Msk (0x1ul << USBD_PHYCTL_DPPUEN_Pos) /*!< USBD PHYCTL: DPPUEN Mask */
|
||||
|
||||
#define USBD_PHYCTL_PHYEN_Pos (9) /*!< USBD PHYCTL: PHYEN Position */
|
||||
#define USBD_PHYCTL_PHYEN_Msk (0x1ul << USBD_PHYCTL_PHYEN_Pos) /*!< USBD PHYCTL: PHYEN Mask */
|
||||
|
||||
#define USBD_PHYCTL_WKEN_Pos (24) /*!< USBD PHYCTL: WKEN Position */
|
||||
#define USBD_PHYCTL_WKEN_Msk (0x1ul << USBD_PHYCTL_WKEN_Pos) /*!< USBD PHYCTL: WKEN Mask */
|
||||
|
||||
#define USBD_PHYCTL_VBUSDET_Pos (31) /*!< USBD PHYCTL: VBUSDET Position */
|
||||
#define USBD_PHYCTL_VBUSDET_Msk (0x1ul << USBD_PHYCTL_VBUSDET_Pos) /*!< USBD PHYCTL: VBUSDET Mask */
|
||||
|
||||
/********************* Bit definition of CEPCTL register **********************/
|
||||
#define USB_CEPCTL_NAKCLR ((uint32_t)0x00000000) /*!<NAK clear \hideinitializer */
|
||||
#define USB_CEPCTL_STALL ((uint32_t)0x00000002) /*!<Stall \hideinitializer */
|
||||
#define USB_CEPCTL_ZEROLEN ((uint32_t)0x00000004) /*!<Zero length packet \hideinitializer */
|
||||
#define USB_CEPCTL_FLUSH ((uint32_t)0x00000008) /*!<CEP flush \hideinitializer */
|
||||
|
||||
/********************* Bit definition of EPxRSPCTL register **********************/
|
||||
#define USB_EP_RSPCTL_FLUSH ((uint32_t)0x00000001) /*!<Buffer Flush \hideinitializer */
|
||||
#define USB_EP_RSPCTL_MODE_AUTO ((uint32_t)0x00000000) /*!<Auto-Validate Mode \hideinitializer */
|
||||
#define USB_EP_RSPCTL_MODE_MANUAL ((uint32_t)0x00000002) /*!<Manual-Validate Mode \hideinitializer */
|
||||
#define USB_EP_RSPCTL_MODE_FLY ((uint32_t)0x00000004) /*!<Fly Mode \hideinitializer */
|
||||
#define USB_EP_RSPCTL_MODE_MASK ((uint32_t)0x00000006) /*!<Mode Mask \hideinitializer */
|
||||
#define USB_EP_RSPCTL_TOGGLE ((uint32_t)0x00000008) /*!<Clear Toggle bit \hideinitializer */
|
||||
#define USB_EP_RSPCTL_HALT ((uint32_t)0x00000010) /*!<Endpoint halt \hideinitializer */
|
||||
#define USB_EP_RSPCTL_ZEROLEN ((uint32_t)0x00000020) /*!<Zero length packet IN \hideinitializer */
|
||||
#define USB_EP_RSPCTL_SHORTTXEN ((uint32_t)0x00000040) /*!<Packet end \hideinitializer */
|
||||
#define USB_EP_RSPCTL_DISBUF ((uint32_t)0x00000080) /*!<Disable buffer \hideinitializer */
|
||||
|
||||
/********************* Bit definition of EPxCFG register **********************/
|
||||
#define USB_EP_CFG_VALID ((uint32_t)0x00000001) /*!<Endpoint Valid \hideinitializer */
|
||||
#define USB_EP_CFG_TYPE_BULK ((uint32_t)0x00000002) /*!<Endpoint type - bulk \hideinitializer */
|
||||
#define USB_EP_CFG_TYPE_INT ((uint32_t)0x00000004) /*!<Endpoint type - interrupt \hideinitializer */
|
||||
#define USB_EP_CFG_TYPE_ISO ((uint32_t)0x00000006) /*!<Endpoint type - isochronous \hideinitializer */
|
||||
#define USB_EP_CFG_TYPE_MASK ((uint32_t)0x00000006) /*!<Endpoint type mask \hideinitializer */
|
||||
#define USB_EP_CFG_DIR_OUT ((uint32_t)0x00000000) /*!<OUT endpoint \hideinitializer */
|
||||
#define USB_EP_CFG_DIR_IN ((uint32_t)0x00000008) /*!<IN endpoint \hideinitializer */
|
||||
|
||||
#endif
|
||||
@@ -1,444 +0,0 @@
|
||||
/*
|
||||
* Apache NuttX
|
||||
* Copyright 2020 The Apache Software Foundation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef __INCLUDE_NUTTX_USB_OHCI_H
|
||||
#define __INCLUDE_NUTTX_USB_OHCI_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
/* Control and status registers (section 7.1) */
|
||||
|
||||
#define OHCI_HCIREV_OFFSET 0x0000 /* HcRevision: Version of HCI specification */
|
||||
#define OHCI_CTRL_OFFSET 0x0004 /* HcControl: HC control */
|
||||
#define OHCI_CMDST_OFFSET 0x0008 /* HcCommandStatus: HC command status */
|
||||
#define OHCI_INTST_OFFSET 0x000c /* HcInterruptStatus: HC interrupt status */
|
||||
#define OHCI_INTEN_OFFSET 0x0010 /* HcInterruptEnable: HC interrupt enable */
|
||||
#define OHCI_INTDIS_OFFSET 0x0014 /* HcInterruptDisable: HC interrupt disable */
|
||||
|
||||
/* Memory pointer registers (section 7.2) */
|
||||
|
||||
#define OHCI_HCCA_OFFSET 0x0018 /* HcHCCA: HC communication area */
|
||||
#define OHCI_PERED_OFFSET 0x001c /* HcPeriodCurrentED: Current isoc or int endpoint desc */
|
||||
#define OHCI_CTRLHEADED_OFFSET 0x0020 /* HcControlHeadED: First EP desc in the control list */
|
||||
#define OHCI_CTRLED_OFFSET 0x0024 /* HcControlCurrentED: Current EP desc in the control list */
|
||||
#define OHCI_BULKHEADED_OFFSET 0x0028 /* HcBulkHeadED: First EP desc in the bulk list */
|
||||
#define OHCI_BULKED_OFFSET 0x002c /* HcBulkCurrentED: Current EP desc in the bulk list */
|
||||
#define OHCI_DONEHEAD_OFFSET 0x0030 /* HcDoneHead: Last transfer desc added to DONE queue */
|
||||
|
||||
/* Frame counter registers (section 7.3) */
|
||||
|
||||
#define OHCI_FMINT_OFFSET 0x0034 /* HcFmInterval: Bit time interval that would not cause overrun */
|
||||
#define OHCI_FMREM_OFFSET 0x0038 /* HcFmRemaining: Bit time remaining in current frame */
|
||||
#define OHCI_FMNO_OFFSET 0x003c /* HcFmNumber: Frame number counter */
|
||||
#define OHCI_PERSTART_OFFSET 0x0040 /* HcPeriodicStart: Time to start processing periodic list */
|
||||
|
||||
/* Root hub registers (section 7.4) */
|
||||
|
||||
#define OHCI_LSTHRES_OFFSET 0x0044 /* HcLSThreshold: Commit to transfer threshold */
|
||||
#define OHCI_RHDESCA_OFFSET 0x0048 /* HcRhDescriptorA: Describes root hub (part A) */
|
||||
#define OHCI_RHDESCB_OFFSET 0x004c /* HcRhDescriptorB: Describes root hub (part B) */
|
||||
#define OHCI_RHSTATUS_OFFSET 0x0050 /* HcRhStatus: Root hub status */
|
||||
|
||||
#define OHCI_MAX_RHPORT 15 /* Maximum number of OHCI root hub ports */
|
||||
|
||||
#define OHCI_RHPORTST_OFFSET(n) (0x0054 + (((n) - 1) << 2))
|
||||
#define OHCI_RHPORTST1_OFFSET 0x0054 /* HcRhPort1Status: Root hub port status 1 */
|
||||
#define OHCI_RHPORTST2_OFFSET 0x0058 /* HcRhPort2Status: Root hub port status 2 */
|
||||
#define OHCI_RHPORTST3_OFFSET 0x005c /* HcRhPort3Status: Root hub port status 3 */
|
||||
#define OHCI_RHPORTST4_OFFSET 0x0060 /* HcRhPort4Status: Root hub port status 4 */
|
||||
#define OHCI_RHPORTST5_OFFSET 0x0064 /* HcRhPort5Status: Root hub port status 5 */
|
||||
#define OHCI_RHPORTST6_OFFSET 0x0068 /* HcRhPort6Status: Root hub port status 6 */
|
||||
#define OHCI_RHPORTST7_OFFSET 0x006c /* HcRhPort7Status: Root hub port status 7 */
|
||||
#define OHCI_RHPORTST8_OFFSET 0x0070 /* HcRhPort8Status: Root hub port status 8 */
|
||||
#define OHCI_RHPORTST9_OFFSET 0x0074 /* HcRhPort9Status: Root hub port status 9 */
|
||||
#define OHCI_RHPORTST10_OFFSET 0x0078 /* HcRhPort10Status: Root hub port status 10 */
|
||||
#define OHCI_RHPORTST11_OFFSET 0x007c /* HcRhPort11Status: Root hub port status 11 */
|
||||
#define OHCI_RHPORTST12_OFFSET 0x0080 /* HcRhPort12Status: Root hub port status 12 */
|
||||
#define OHCI_RHPORTST13_OFFSET 0x0084 /* HcRhPort13Status: Root hub port status 13 */
|
||||
#define OHCI_RHPORTST14_OFFSET 0x0088 /* HcRhPort14Status: Root hub port status 14 */
|
||||
#define OHCI_RHPORTST15_OFFSET 0x008c /* HcRhPort15Status: Root hub port status 15 */
|
||||
|
||||
/* Register bit definitions *************************************************/
|
||||
|
||||
/* HcRevision: Version of HCI specification (7.1.1) */
|
||||
|
||||
#define OHCI_HCIREV_SHIFT (0) /* Bits 0-7: HCI spec version (BCD) */
|
||||
#define OHCI_HCIREV_MASK (0xff << OHCI_HCIREV_SHIFT)
|
||||
|
||||
/* HcControl: HC control (7.1.2) */
|
||||
|
||||
#define OHCI_CTRL_CBSR (3 << 0) /* Bit 0: Control/bulk service ratio */
|
||||
#define OHCI_CTRL_PLE (1 << 2) /* Bit 1: Periodic list enable */
|
||||
#define OHCI_CTRL_IE (1 << 3) /* Bit 2: Isochronous enable */
|
||||
#define OHCI_CTRL_CLE (1 << 4) /* Bit 3: Control list enable */
|
||||
#define OHCI_CTRL_BLE (1 << 5) /* Bit 4: Bulk list enable */
|
||||
#define OHCI_CTRL_HCFS_SHIFT (6) /* Bits 6-7: Host controller functional state */
|
||||
#define OHCI_CTRL_HCFS_MASK (3 << OHCI_CTRL_HCFS_SHIFT)
|
||||
# define OHCI_CTRL_HCFS_RESET (0 << OHCI_CTRL_HCFS_SHIFT)
|
||||
# define OHCI_CTRL_HCFS_RESUME (1 << OHCI_CTRL_HCFS_SHIFT)
|
||||
# define OHCI_CTRL_HCFS_OPER (2 << OHCI_CTRL_HCFS_SHIFT)
|
||||
# define OHCI_CTRL_HCFS_SUSPEND (3 << OHCI_CTRL_HCFS_SHIFT)
|
||||
#define OHCI_CTRL_IR (1 << 8) /* Bit 8: Interrupt routing */
|
||||
#define OHCI_CTRL_RWC (1 << 9) /* Bit 9: Remote wakeup connected */
|
||||
#define OHCI_CTRL_RWE (1 << 10) /* Bit 10: Remote wakeup enable */
|
||||
/* Bits 11-31: Reserved */
|
||||
|
||||
/* HcCommandStatus: HC command status (7.1.3) */
|
||||
|
||||
#define OHCI_CMDST_HCR (1 << 0) /* Bit 0: Host controller reset */
|
||||
#define OHCI_CMDST_CLF (1 << 1) /* Bit 1: Control list filled */
|
||||
#define OHCI_CMDST_BLF (1 << 2) /* Bit 2: Bulk list filled */
|
||||
#define OHCI_CMDST_OCR (1 << 3) /* Bit 3: Ownership change request */
|
||||
/* Bits 4-15: Reserved */
|
||||
#define OHCI_CMDST_SOC (3 << 16) /* Bit 16: Scheduling overrun count */
|
||||
/* Bits 17-31: Reserved */
|
||||
|
||||
/* HcInterruptStatus: HC interrupt status (7.1.4),
|
||||
* HcInterruptEnable: HC interrupt enable (7.1.5), and
|
||||
* HcInterruptDisable: HC interrupt disable (7.1.6)
|
||||
*/
|
||||
|
||||
#define OHCI_INT_SO (1 << 0) /* Bit 0: Scheduling overrun */
|
||||
#define OHCI_INT_WDH (1 << 1) /* Bit 1: Writeback done head */
|
||||
#define OHCI_INT_SF (1 << 2) /* Bit 2: Start of frame */
|
||||
#define OHCI_INT_RD (1 << 3) /* Bit 3: Resume detected */
|
||||
#define OHCI_INT_UE (1 << 4) /* Bit 4: Unrecoverable error */
|
||||
#define OHCI_INT_FNO (1 << 5) /* Bit 5: Frame number overflow */
|
||||
#define OHCI_INT_RHSC (1 << 6) /* Bit 6: Root hub status change */
|
||||
/* Bits 7-29: Reserved */
|
||||
#define OHCI_INT_OC (1 << 30) /* Bit 30: Ownership change */
|
||||
#define OHCI_INT_MIE (1 << 31) /* Bit 31: Master interrupt enable
|
||||
* (Enable/disable only) */
|
||||
|
||||
/* HcHCCA: HC communication area (7.2.1):
|
||||
*
|
||||
* 32-bits aligned to 256 byte boundary.
|
||||
*/
|
||||
|
||||
/* HcPeriodCurrentED: Current isoc or int endpoint desc (7.2.2),
|
||||
* HcControlHeadED: First EP desc in the control list (7.2.3),
|
||||
* HcControlCurrentED: Current EP desc in the control list (7.2.4),
|
||||
* HcBulkHeadED: First EP desc in the bulk list (7.2.5),
|
||||
* HcBulkCurrentED: Current EP desc in the bulk list (7.2.6), and
|
||||
* HcDoneHead: Last transfer desc added to DONE queue (7.2.7):
|
||||
*
|
||||
* All 32-bits aligned to an 8-byte boundary
|
||||
*/
|
||||
|
||||
/* HcFmInterval: Bit time interval that would not cause overrun (7.3.1) */
|
||||
|
||||
#define OHCI_FMINT_FI_SHIFT (0) /* Bits 0-13: Frame interval */
|
||||
#define OHCI_FMINT_FI_MASK (0x3fff << OHCI_FMINT_FI_SHIFT)
|
||||
/* Bits 14-15: Reserved */
|
||||
#define OHCI_FMINT_FSMPS_SHIFT (16) /* Bits 16-30: FS largest packet data */
|
||||
#define OHCI_FMINT_FSMPS_MASK (0x7fff << OHCI_FMINT_FSMPS_SHIFT)
|
||||
#define OHCI_FMINT_FIT (1 << 31) /* Bit 31: Frame interval toggle */
|
||||
|
||||
/* HcFmRemaining: Bit time remaining in current frame (7.3.2) */
|
||||
|
||||
#define OHCI_FMREM_FR_SHIFT (0) /* Bits 0-13: Frame remaining */
|
||||
#define OHCI_FMREM_FR_MASK (0x3fff << OHCI_FMREM_FR_SHIFT)
|
||||
/* Bits 16-30: Reserved */
|
||||
#define OHCI_FMINT_FRT (1 << 31) /* Bit 31: Frame remaining toggle */
|
||||
|
||||
/* HcFmNumber: Frame number counter (7.3.3) */
|
||||
|
||||
#define OHCI_FMNO_FI_SHIFT (0) /* Bits 0-15: Frame number */
|
||||
#define OHCI_FMNO_FI_MASK (0xffff << OHCI_FMINT_FI_SHIFT)
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/* HcPeriodicStart: Time to start processing periodic list (7.3.4) */
|
||||
|
||||
#define OHCI_PERSTART_SHIFT (0) /* Bits 0-13: Periodic start */
|
||||
#define OHCI_PERSTART_MASK (0x3fff << OHCI_PERSTART_SHIFT)
|
||||
/* Bits 14-31: Reserved */
|
||||
|
||||
/* HcLSThreshold: Commit to transfer threshold (7.3.5) */
|
||||
|
||||
#define OHCI_LSTHRES_SHIFT (0) /* Bits 0-11: LS threshold */
|
||||
#define OHCI_LSTHRES_MASK (0x0fff << OHCI_PERSTART_SHIFT)
|
||||
/* Bits 12-31: Reserved */
|
||||
|
||||
/* HcRhDescriptorN: Describes root hub (part A) (7.4.1) */
|
||||
|
||||
#define OHCI_RHDESCA_NDP_SHIFT (0) /* Bits 0-7: Number downstream ports */
|
||||
#define OHCI_RHDESCA_NDP_MASK (0xff << OHCI_RHDESCA_NDP_SHIFT)
|
||||
#define OHCI_RHDESCA_PSM (1 << 8) /* Bit 8: Power switching mode */
|
||||
#define OHCI_RHDESCA_NPS (1 << 9) /* Bit 9: No power switching */
|
||||
#define OHCI_RHDESCA_DT (1 << 10) /* Bit 10: Device type */
|
||||
#define OHCI_RHDESCA_OCPM (1 << 11) /* Bit 11: Over current protection mode */
|
||||
#define OHCI_RHDESCA_NOCP (1 << 12) /* Bit 12: No over current protection */
|
||||
/* Bits 13-23: Reserved */
|
||||
#define OHCI_RHDESCA_POTPGT_SHIFT (24) /* Bits 24-31: Power on to power good time */
|
||||
#define OHCI_RHDESCA_POTPGT_MASK (0xff << OHCI_RHDESCA_POTPGT_SHIFT)
|
||||
|
||||
/* HcRhDescriptorB: Describes root hub (part B) (7.4.2) */
|
||||
|
||||
#define OHCI_RHDESCB_DR_SHIFT (0) /* Bits 0-15: Device removable */
|
||||
#define OHCI_RHDESCB_DR_MASK (0xffff << OHCI_RHDESCB_DR_SHIFT)
|
||||
# define OHCI_RHDESCB_ATTACHED(n) (1 << (OHCI_RHDESCB_DR_SHIFT+(n)))
|
||||
#define OHCI_RHDESCB_PPCM_SHIFT (16) /* Bits 16-31: Port power control mask */
|
||||
#define OHCI_RHDESCB_PPCM_MASK (0xffff << OHCI_RHDESCB_PPCM_SHIFT)
|
||||
# define OHCI_RHDESCB_POWERED(n) (1 << (OHCI_RHDESCB_DR_SHIFT+(n)))
|
||||
|
||||
/* HcRhStatus: Root hub status (7.4.3) */
|
||||
|
||||
#define OHCI_RHSTATUS_LPS (1 << 0) /* Bit 0: Local power status (read)*/
|
||||
#define OHCI_RHSTATUS_CGP (1 << 0) /* Bit 0: Clear global power (write)*/
|
||||
#define OHCI_RHSTATUS_OCI (1 << 1) /* Bit 1: Over current indicator */
|
||||
/* Bits 2-14: Reserved */
|
||||
#define OHCI_RHSTATUS_DRWE (1 << 15) /* Bit 15: Device remote wakeup enable */
|
||||
#define OHCI_RHSTATUS_LPSC (1 << 16) /* Bit 16: Local power status change (read) */
|
||||
#define OHCI_RHSTATUS_SGP (1 << 16) /* Bit 16: Set global power (write) */
|
||||
#define OHCI_RHSTATUS_OCIC (1 << 17) /* Bit 17: Overcurrent indicator change */
|
||||
/* Bits 18-30: Reserved */
|
||||
#define OHCI_RHSTATUS_CRWE (1 << 31) /* Bit 31: Clear remote wakeup enable */
|
||||
|
||||
/* HcRhPortStatus: Root hub port status (7.4.4) */
|
||||
|
||||
#define OHCI_RHPORTST_CCS (1 << 0) /* Bit 0: Current connect status */
|
||||
#define OHCI_RHPORTST_PES (1 << 1) /* Bit 1: Port enable status */
|
||||
#define OHCI_RHPORTST_PSS (1 << 2) /* Bit 2: Port suspend status */
|
||||
#define OHCI_RHPORTST_POCI (1 << 3) /* Bit 3: Port over current indicator */
|
||||
#define OHCI_RHPORTST_PRS (1 << 4) /* Bit 4: Port reset status */
|
||||
/* Bits 5-7: Reserved */
|
||||
#define OHCI_RHPORTST_PPS (1 << 8) /* Bit 8: Port power status */
|
||||
#define OHCI_RHPORTST_LSDA (1 << 9) /* Bit 9: Low speed device attached */
|
||||
/* Bits 10-15: Reserved */
|
||||
#define OHCI_RHPORTST_CSC (1 << 16) /* Bit 16: Connect status change */
|
||||
#define OHCI_RHPORTST_PESC (1 << 17) /* Bit 17: Port enable status change */
|
||||
#define OHCI_RHPORTST_PSSC (1 << 18) /* Bit 18: Port suspend status change */
|
||||
#define OHCI_RHPORTST_OCIC (1 << 19) /* Bit 19: Port over current indicator change */
|
||||
#define OHCI_RHPORTST_PRSC (1 << 20) /* Bit 20: Port reset status change */
|
||||
/* Bits 21-31: Reserved */
|
||||
|
||||
/* Transfer Descriptors *****************************************************/
|
||||
|
||||
/* Endpoint Descriptor Offsets (4.2.1) */
|
||||
|
||||
#define ED_CONTROL_OFFSET (0x00) /* ED status/control bits */
|
||||
#define ED_TAILP_OFFSET (0x04) /* TD Queue Tail Pointer (TailP) */
|
||||
#define ED_HEADP_OFFSET (0x08) /* TD Queue Head Pointer (HeadP) */
|
||||
#define ED_NEXTED_OFFSET (0x0c) /* Next Endpoint Descriptor (NextED) */
|
||||
|
||||
/* Endpoint Descriptor Bit Definitions (4.2.2) */
|
||||
|
||||
#define ED_CONTROL_FA_SHIFT (0) /* Bits 0-6: Function Address */
|
||||
#define ED_CONTROL_FA_MASK (0x7f << ED_CONTROL_FA_SHIFT)
|
||||
#define ED_CONTROL_EN_SHIFT (7) /* Bits 7-10: Endpoint number */
|
||||
#define ED_CONTROL_EN_MASK (15 << ED_CONTROL_EN_SHIFT)
|
||||
#define ED_CONTROL_D_SHIFT (11) /* Bits 11-12: Direction */
|
||||
#define ED_CONTROL_D_MASK (3 << ED_CONTROL_D_SHIFT)
|
||||
# define ED_CONTROL_D_TD1 (0 << ED_CONTROL_D_SHIFT) /* Get direction from TD */
|
||||
# define ED_CONTROL_D_OUT (1 << ED_CONTROL_D_SHIFT) /* OUT */
|
||||
# define ED_CONTROL_D_IN (2 << ED_CONTROL_D_SHIFT) /* IN */
|
||||
# define ED_CONTROL_D_TD2 (3 << ED_CONTROL_D_SHIFT) /* Get direction from TD */
|
||||
|
||||
#define ED_CONTROL_S (1 << 13) /* Bit 13: Speed (low) */
|
||||
#define ED_CONTROL_K (1 << 14) /* Bit 14: Skip */
|
||||
#define ED_CONTROL_F (1 << 15) /* Bit 15: Format (isochronous) */
|
||||
#define ED_CONTROL_MPS_SHIFT (16) /* Bits 16-26: Maximum packet size */
|
||||
#define ED_CONTROL_MPS_MASK (0x7ff << ED_CONTROL_MPS_SHIFT)
|
||||
|
||||
#define ED_HEADP_ADDR_SHIFT (0)
|
||||
#define ED_HEADP_ADDR_MASK 0xfffffff0
|
||||
#define ED_HEADP_H (1 << 0) /* Bit 0: Halted */
|
||||
#define ED_HEADP_C (1 << 1) /* Bit 1: Toggle carry */
|
||||
|
||||
/* General Transfer Descriptor Offsets (4.3.1) */
|
||||
|
||||
#define GTD_STATUS_OFFSET (0x00) /* TD status bits */
|
||||
#define GTD_CBP_OFFSET (0x04) /* Current Buffer Pointer (CBP) */
|
||||
#define GTD_NEXTTD_OFFSET (0x08) /* Next TD (NextTD) */
|
||||
#define GTD_BE_OFFSET (0x0c) /* Buffer End (BE) */
|
||||
|
||||
/* General Transfer Descriptor Bit Definitions */
|
||||
|
||||
/* Bits 0-17: Reserved */
|
||||
|
||||
#define GTD_STATUS_R (1 << 18) /* Bit 18: Buffer rounding */
|
||||
#define GTD_STATUS_DP_SHIFT (19) /* Bits 19-20: Direction/PID */
|
||||
#define GTD_STATUS_DP_MASK (3 << GTD_STATUS_DP_SHIFT)
|
||||
# define GTD_STATUS_DP_SETUP (0 << GTD_STATUS_DP_SHIFT) /* To endpoint */
|
||||
# define GTD_STATUS_DP_OUT (1 << GTD_STATUS_DP_SHIFT) /* To endpoint */
|
||||
# define GTD_STATUS_DP_IN (2 << GTD_STATUS_DP_SHIFT) /* From endpoint */
|
||||
|
||||
#define GTD_STATUS_DI_SHIFT (21) /* Bits 21-23: Delay input */
|
||||
#define GTD_STATUS_DI_MASK (7 << GTD_STATUS_DI_SHIFT)
|
||||
#define GTD_STATUS_T_SHIFT (24) /* Bits 24-25: Data Toggle */
|
||||
#define GTD_STATUS_T_MASK (3 << GTD_STATUS_T_SHIFT)
|
||||
# define GTD_STATUS_T_TOGGLE (0 << GTD_STATUS_T_SHIFT)
|
||||
# define GTD_STATUS_T_DATA0 (2 << GTD_STATUS_T_SHIFT)
|
||||
# define GTD_STATUS_T_DATA1 (3 << GTD_STATUS_T_SHIFT)
|
||||
#define GTD_STATUS_EC_SHIFT (26) /* Bits 26-27: Error count */
|
||||
#define GTD_STATUS_EC_MASK (3 << GTD_STATUS_EC_SHIFT)
|
||||
#define GTD_STATUS_CC_SHIFT (28) /* Bits 28-31: Condition code */
|
||||
#define GTD_STATUS_CC_MASK (15 << GTD_STATUS_CC_SHIFT)
|
||||
|
||||
/* Isochronous Transfer Descriptor Offsets (4.3.2) */
|
||||
|
||||
#define ITD_STATUS_OFFSET (0x00) /* TD status bits */
|
||||
#define ITD_BP0_OFFSET (0x04) /* Buffer page 0 (BP0) */
|
||||
#define ITD_NEXTTD_OFFSET (0x08) /* Next TD (NextTD) */
|
||||
#define ITD_BE_OFFSET (0x0c) /* Buffer End (BE) */
|
||||
|
||||
#define ITD_NPSW (8)
|
||||
#define ITD_PSW0_OFFSET (0x10) /* Offset0/PSW0 */
|
||||
#define ITD_PSW1_OFFSET (0x12) /* Offset1/PSW1 */
|
||||
#define ITD_PSW2_OFFSET (0x14) /* Offset2/PSW2 */
|
||||
#define ITD_PSW3_OFFSET (0x16) /* Offset3/PSW3 */
|
||||
#define ITD_PSW4_OFFSET (0x18) /* Offset4/PSW4 */
|
||||
#define ITD_PSW5_OFFSET (0x1a) /* Offset5/PSW5 */
|
||||
#define ITD_PSW6_OFFSET (0x1c) /* Offset6/PSW6 */
|
||||
#define ITD_PSW7_OFFSET (0x1e) /* Offset7/PSW7 */
|
||||
|
||||
/* Condition codes (Table 4-7) */
|
||||
|
||||
#define TD_CC_NOERROR 0x00
|
||||
#define TD_CC_CRC 0x01
|
||||
#define TD_CC_BITSTUFFING 0x02
|
||||
#define TD_CC_DATATOGGLEMISMATCH 0x03
|
||||
#define TD_CC_STALL 0x04
|
||||
#define TD_CC_DEVNOTRESPONDING 0x05
|
||||
#define TD_CC_PIDCHECKFAILURE 0x06
|
||||
#define TD_CC_UNEXPECTEDPID 0x07
|
||||
#define TD_CC_DATAOVERRUN 0x08
|
||||
#define TD_CC_DATAUNDERRUN 0x09
|
||||
#define TD_CC_BUFFEROVERRUN 0x0c
|
||||
#define TD_CC_BUFFERUNDERRUN 0x0d
|
||||
#define TD_CC_NOTACCESSED 0x0f
|
||||
|
||||
#define TD_CC_USER 0x10 /* For use by OHCI drivers */
|
||||
|
||||
/* Host Controller Communications Area Format (4.4.1) ***********************/
|
||||
|
||||
/* HccaInterruptTable: 32x32-bit pointers to interrupt EDs */
|
||||
|
||||
#define HCCA_INTTBL_OFFSET (0x00)
|
||||
#define HCCA_INTTBL_WSIZE (32)
|
||||
#define HCCA_INTTBL_BSIZE (HCCA_INTTBL_WSIZE * 4)
|
||||
|
||||
/* HccaFrameNumber: Current frame number */
|
||||
|
||||
#define HCCA_FMNO_OFFSET (0x80)
|
||||
#define HCCA_FMNO_BSIZE (2)
|
||||
|
||||
/* HccaPad1: Zero when frame no. updated */
|
||||
|
||||
#define HCCA_PAD1_OFFSET (0x82)
|
||||
#define HCCA_PAD1_BSIZE (2)
|
||||
|
||||
/* HccaDoneHead: When the HC reaches the end of a frame and its deferred
|
||||
* interrupt register is 0, it writes the current value of its HcDoneHead to
|
||||
* this location and generates an interrupt.
|
||||
*
|
||||
* The LSB of HCCADoneHead may be set to 1 to indicate that an unmasked
|
||||
* HcInterruptStatus was set when HccaDoneHead was written.
|
||||
*/
|
||||
|
||||
#define HCCA_DONEHEAD_OFFSET (0x84)
|
||||
#define HCCA_DONEHEAD_BSIZE (4)
|
||||
|
||||
#define HCCA_DONEHEAD_MASK 0xfffffffe
|
||||
#define HCCA_DONEHEAD_INTSTA (1 << 0)
|
||||
|
||||
/* 0x88: 116 bytes reserved */
|
||||
|
||||
#define HCCA_RESERVED_OFFSET (0x88)
|
||||
#define HCCA_RESERVED_BSIZE (116)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/* Endpoint Descriptor Offsets (4.2.1) */
|
||||
|
||||
struct ohci_ed_s
|
||||
{
|
||||
volatile uint32_t ctrl; /* ED status/control bits */
|
||||
volatile uint32_t tailp; /* TD Queue Tail Pointer (TailP) */
|
||||
volatile uint32_t headp; /* TD Queue Head Pointer (HeadP) */
|
||||
volatile uint32_t nexted; /* Next Endpoint Descriptor (NextED) */
|
||||
};
|
||||
|
||||
/* General Transfer Descriptor (4.3.1) */
|
||||
|
||||
struct ohci_gtd_s
|
||||
{
|
||||
volatile uint32_t ctrl; /* TD status/control bits */
|
||||
volatile uint32_t cbp; /* Current Buffer Pointer (CBP) */
|
||||
volatile uint32_t nexttd; /* Next TD (NextTD) */
|
||||
volatile uint32_t be; /* Buffer End (BE) */
|
||||
};
|
||||
|
||||
/* Isochronous Transfer Descriptor Offsets (4.3.2) */
|
||||
|
||||
struct ohci_itd_s
|
||||
{
|
||||
volatile uint32_t ctrl; /* TD status/control bits */
|
||||
volatile uint32_t bp0; /* Buffer page 0 (BP0 */
|
||||
volatile uint32_t nexttd; /* Next TD (NextTD) */
|
||||
volatile uint32_t be; /* Buffer End (BE) */
|
||||
volatile uint16_t psw[ITD_NPSW]; /* Offset/PSW */
|
||||
};
|
||||
|
||||
/* Host Controller Communications Area Format (4.4.1) */
|
||||
|
||||
struct ohci_hcca_s
|
||||
{
|
||||
/* HccaInterruptTable: 32x32-bit pointers to interrupt EDs */
|
||||
|
||||
volatile uint32_t inttbl[HCCA_INTTBL_WSIZE];
|
||||
|
||||
/* HccaFrameNumber: Current frame number and
|
||||
* HccaPad1: Zero when frame no. updated
|
||||
*/
|
||||
|
||||
volatile uint16_t fmno;
|
||||
volatile uint16_t pad1;
|
||||
|
||||
/* HccaDoneHead: When the HC reaches the end of a frame and its deferred
|
||||
* interrupt register is 0, it writes the current value of its HcDoneHead
|
||||
* to this location and generates an interrupt.
|
||||
*/
|
||||
|
||||
volatile uint32_t donehead;
|
||||
volatile uint8_t reserved[HCCA_RESERVED_BSIZE];
|
||||
volatile uint32_t extra;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCLUDE_NUTTX_USB_OHCI_H */
|
||||
Reference in New Issue
Block a user