diff --git a/port/dwc2/usb_dc_dwc2.c b/port/dwc2/usb_dc_dwc2.c index 4784e62e..4de89de1 100644 --- a/port/dwc2/usb_dc_dwc2.c +++ b/port/dwc2/usb_dc_dwc2.c @@ -51,87 +51,46 @@ #endif // clang-format on -#ifndef CONFIG_USB_DWC2_RAM_SIZE -#error "please define CONFIG_USB_DWC2_RAM_SIZE in usb_config.h, only support 1280 or 4096" -#endif - -#if CONFIG_USB_DWC2_RAM_SIZE == 1280 -/*FIFO sizes in bytes (total available memory for FIFOs is 1.25KB )*/ -#ifndef CONFIG_USB_DWC2_RX_FIFO_SIZE -#define CONFIG_USB_DWC2_RX_FIFO_SIZE (512) -#endif - -#ifndef CONFIG_USB_DWC2_TX0_FIFO_SIZE -#define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64) -#endif - -#ifndef CONFIG_USB_DWC2_TX1_FIFO_SIZE -#define CONFIG_USB_DWC2_TX1_FIFO_SIZE (128) -#endif - -#ifndef CONFIG_USB_DWC2_TX2_FIFO_SIZE -#define CONFIG_USB_DWC2_TX2_FIFO_SIZE (128) -#endif - -#ifndef CONFIG_USB_DWC2_TX3_FIFO_SIZE -#define CONFIG_USB_DWC2_TX3_FIFO_SIZE (128) -#endif - -#ifndef CONFIG_USB_DWC2_TX4_FIFO_SIZE -#define CONFIG_USB_DWC2_TX4_FIFO_SIZE (128) -#endif - -#ifndef CONFIG_USB_DWC2_TX5_FIFO_SIZE -#define CONFIG_USB_DWC2_TX5_FIFO_SIZE (128) -#endif - -#ifndef CONFIG_USBDEV_EP_NUM -#define CONFIG_USBDEV_EP_NUM 4 /* define with minimum value*/ -#endif - -#elif CONFIG_USB_DWC2_RAM_SIZE == 4096 - //#define CONFIG_USB_DWC2_DMA_ENABLE -#ifdef CONFIG_USB_DWC2_DMA_ENABLE -#warning "if you enable dcache,please add .nocacheble section in your sct or ld or icf" -#endif - -/*FIFO sizes in bytes (total available memory for FIFOs is 4KB )*/ -#ifndef CONFIG_USB_DWC2_RX_FIFO_SIZE -#define CONFIG_USB_DWC2_RX_FIFO_SIZE (1024) +#ifndef CONFIG_USB_DWC2_RXALL_FIFO_SIZE +#define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (320) #endif #ifndef CONFIG_USB_DWC2_TX0_FIFO_SIZE -#define CONFIG_USB_DWC2_TX0_FIFO_SIZE (256) +#define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4) #endif #ifndef CONFIG_USB_DWC2_TX1_FIFO_SIZE -#define CONFIG_USB_DWC2_TX1_FIFO_SIZE (1024) +#define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4) #endif #ifndef CONFIG_USB_DWC2_TX2_FIFO_SIZE -#define CONFIG_USB_DWC2_TX2_FIFO_SIZE (512) +#define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4) #endif #ifndef CONFIG_USB_DWC2_TX3_FIFO_SIZE -#define CONFIG_USB_DWC2_TX3_FIFO_SIZE (512) +#define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4) #endif #ifndef CONFIG_USB_DWC2_TX4_FIFO_SIZE -#define CONFIG_USB_DWC2_TX4_FIFO_SIZE (512) +#define CONFIG_USB_DWC2_TX4_FIFO_SIZE (64 / 4) #endif #ifndef CONFIG_USB_DWC2_TX5_FIFO_SIZE -#define CONFIG_USB_DWC2_TX5_FIFO_SIZE (256) +#define CONFIG_USB_DWC2_TX5_FIFO_SIZE (64 / 4) #endif -#ifndef CONFIG_USBDEV_EP_NUM -#define CONFIG_USBDEV_EP_NUM 6 /* define with minimum value*/ +#ifndef CONFIG_USB_DWC2_TX6_FIFO_SIZE +#define CONFIG_USB_DWC2_TX6_FIFO_SIZE (64 / 4) #endif -#else -#error "Unsupported CONFIG_USB_DWC2_RAM_SIZE value" +#ifndef CONFIG_USB_DWC2_TX7_FIFO_SIZE +#define CONFIG_USB_DWC2_TX7_FIFO_SIZE (64 / 4) +#endif + +#ifndef CONFIG_USB_DWC2_TX8_FIFO_SIZE +#define CONFIG_USB_DWC2_TX8_FIFO_SIZE (64 / 4) #endif #define USBD_BASE (g_usbdev_bus[0].reg_base) @@ -516,6 +475,7 @@ int usb_dc_init(uint8_t busid) uint8_t hsphy_type; uint8_t dma_support; uint8_t endpoints; + uint32_t fifo_num; memset(&g_dwc2_udc, 0, sizeof(struct dwc2_udc)); @@ -554,7 +514,7 @@ int usb_dc_init(uint8_t busid) USB_LOG_INFO("GHWCFG4:%08x\r\n", USB_OTG_GLB->GHWCFG4); USB_LOG_INFO("dwc2 fsphy type:%d, hsphy type:%d, dma support:%d\r\n", fsphy_type, hsphy_type, dma_support); - USB_LOG_INFO("dwc2 has %d endpoints, default config: %d endpoints\r\n", endpoints, CONFIG_USBDEV_EP_NUM); + USB_LOG_INFO("dwc2 has %d endpoints and dfifo depth(32-bit words) is %d, default config: %d endpoints\r\n", endpoints, (USB_OTG_GLB->GHWCFG3 >> 16), CONFIG_USBDEV_EP_NUM); USB_LOG_INFO("=================================\r\n"); if (endpoints < CONFIG_USBDEV_EP_NUM) { @@ -563,12 +523,6 @@ int usb_dc_init(uint8_t busid) } } - if ((hsphy_type == 0) && (CONFIG_USB_DWC2_RAM_SIZE != 1280)) { - USB_LOG_ERR("dwc2 hsphy type is 0, but ram size is not 1280, please check\r\n"); - while (1) { - } - } - USB_OTG_DEV->DCTL |= USB_OTG_DCTL_SDIS; USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; @@ -638,27 +592,45 @@ int usb_dc_init(uint8_t busid) USB_OTG_GLB->GINTMSK |= USB_OTG_GINTMSK_SOFM; #endif - USB_OTG_GLB->GRXFSIZ = (CONFIG_USB_DWC2_RX_FIFO_SIZE / 4); + USB_OTG_GLB->GRXFSIZ = (CONFIG_USB_DWC2_RXALL_FIFO_SIZE); - dwc2_set_txfifo(0, CONFIG_USB_DWC2_TX0_FIFO_SIZE / 4); - dwc2_set_txfifo(1, CONFIG_USB_DWC2_TX1_FIFO_SIZE / 4); - dwc2_set_txfifo(2, CONFIG_USB_DWC2_TX2_FIFO_SIZE / 4); - dwc2_set_txfifo(3, CONFIG_USB_DWC2_TX3_FIFO_SIZE / 4); + dwc2_set_txfifo(0, CONFIG_USB_DWC2_TX0_FIFO_SIZE); + dwc2_set_txfifo(1, CONFIG_USB_DWC2_TX1_FIFO_SIZE); + dwc2_set_txfifo(2, CONFIG_USB_DWC2_TX2_FIFO_SIZE); + dwc2_set_txfifo(3, CONFIG_USB_DWC2_TX3_FIFO_SIZE); + + fifo_num = CONFIG_USB_DWC2_RXALL_FIFO_SIZE; + fifo_num += CONFIG_USB_DWC2_TX0_FIFO_SIZE; + fifo_num += CONFIG_USB_DWC2_TX1_FIFO_SIZE; + fifo_num += CONFIG_USB_DWC2_TX2_FIFO_SIZE; + fifo_num += CONFIG_USB_DWC2_TX3_FIFO_SIZE; #if CONFIG_USBDEV_EP_NUM > 4 - dwc2_set_txfifo(4, CONFIG_USB_DWC2_TX4_FIFO_SIZE / 4); + dwc2_set_txfifo(4, CONFIG_USB_DWC2_TX4_FIFO_SIZE); + fifo_num += CONFIG_USB_DWC2_TX4_FIFO_SIZE; #endif #if CONFIG_USBDEV_EP_NUM > 5 - dwc2_set_txfifo(5, CONFIG_USB_DWC2_TX5_FIFO_SIZE / 4); + dwc2_set_txfifo(5, CONFIG_USB_DWC2_TX5_FIFO_SIZE); + fifo_num += CONFIG_USB_DWC2_TX5_FIFO_SIZE; #endif #if CONFIG_USBDEV_EP_NUM > 6 - dwc2_set_txfifo(6, CONFIG_USB_DWC2_TX6_FIFO_SIZE / 4); + dwc2_set_txfifo(6, CONFIG_USB_DWC2_TX6_FIFO_SIZE); + fifo_num += CONFIG_USB_DWC2_TX6_FIFO_SIZE; #endif #if CONFIG_USBDEV_EP_NUM > 7 - dwc2_set_txfifo(7, CONFIG_USB_DWC2_TX7_FIFO_SIZE / 4); + dwc2_set_txfifo(7, CONFIG_USB_DWC2_TX7_FIFO_SIZE); + fifo_num += CONFIG_USB_DWC2_TX7_FIFO_SIZE; #endif #if CONFIG_USBDEV_EP_NUM > 8 - dwc2_set_txfifo(8, CONFIG_USB_DWC2_TX8_FIFO_SIZE / 4); + dwc2_set_txfifo(8, CONFIG_USB_DWC2_TX8_FIFO_SIZE); + fifo_num += CONFIG_USB_DWC2_TX8_FIFO_SIZE; #endif + + if (fifo_num > (USB_OTG_GLB->GHWCFG3 >> 16)) { + USB_LOG_ERR("Your fifo config is overflow, please check\r\n"); + while (1) { + } + } + ret = dwc2_flush_txfifo(0x10U); ret = dwc2_flush_rxfifo(); diff --git a/port/dwc2/usb_hc_dwc2.c b/port/dwc2/usb_hc_dwc2.c index f051a0e8..64acf2a7 100644 --- a/port/dwc2/usb_hc_dwc2.c +++ b/port/dwc2/usb_hc_dwc2.c @@ -11,6 +11,24 @@ #define CONFIG_USBHOST_PIPE_NUM 12 #endif +/* largest non-periodic USB packet used / 4 */ +#ifndef CONFIG_USB_DWC2_NPTX_FIFO_SIZE +#define CONFIG_USB_DWC2_NPTX_FIFO_SIZE (512 / 4) +#endif + +/* largest periodic USB packet used / 4 */ +#ifndef CONFIG_USB_DWC2_PTX_FIFO_SIZE +#define CONFIG_USB_DWC2_PTX_FIFO_SIZE (1024 / 4) +#endif + +/* +(largest USB packet used / 4) + 1 for status information + 1 transfer complete + +1 location each for Bulk/Control endpoint for handling NAK/NYET scenario +*/ +#ifndef CONFIG_USB_DWC2_RX_FIFO_SIZE +#define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE) / 4) +#endif + #define USB_OTG_GLB ((USB_OTG_GlobalTypeDef *)(bus->hcd.reg_base)) #define USB_OTG_PCGCCTL *(__IO uint32_t *)((uint32_t)bus->hcd.reg_base + USB_OTG_PCGCCTL_BASE) #define USB_OTG_HPRT *(__IO uint32_t *)((uint32_t)bus->hcd.reg_base + USB_OTG_HOST_PORT_BASE) @@ -241,7 +259,6 @@ static inline void dwc2_chan_transfer(struct usbh_bus *bus, uint8_t ch_num, uint static void dwc2_halt(struct usbh_bus *bus, uint8_t ch_num) { - volatile uint32_t HcEpType = (USB_OTG_HC(ch_num)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; volatile uint32_t ChannelEna = (USB_OTG_HC(ch_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; volatile uint32_t count = 0U; __IO uint32_t value; @@ -434,7 +451,7 @@ int usb_hc_init(struct usbh_bus *bus) USB_LOG_INFO("GHWCFG3:%08x\r\n", USB_OTG_GLB->GHWCFG3); USB_LOG_INFO("GHWCFG4:%08x\r\n", USB_OTG_GLB->GHWCFG4); - USB_LOG_INFO("dwc2 has %d channels\r\n", ((USB_OTG_GLB->GHWCFG2 & (0x0f << 14)) >> 14) + 1); + USB_LOG_INFO("dwc2 has %d channels and dfifo depth(32-bit words) is %d\r\n", ((USB_OTG_GLB->GHWCFG2 & (0x0f << 14)) >> 14) + 1, (USB_OTG_GLB->GHWCFG3 >> 16)); if (((USB_OTG_GLB->GHWCFG2 & (0x3U << 3)) >> 3) != 2) { USB_LOG_ERR("This dwc2 version does not support dma mode, so stop working\r\n"); @@ -442,6 +459,12 @@ int usb_hc_init(struct usbh_bus *bus) } } + if ((CONFIG_USB_DWC2_RX_FIFO_SIZE + CONFIG_USB_DWC2_NPTX_FIFO_SIZE + CONFIG_USB_DWC2_PTX_FIFO_SIZE) > (USB_OTG_GLB->GHWCFG3 >> 16)) { + USB_LOG_ERR("Your fifo config is overflow, please check\r\n"); + while (1) { + } + } + USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; /* This is vendor register */ @@ -472,9 +495,9 @@ int usb_hc_init(struct usbh_bus *bus) USB_OTG_GLB->GINTSTS = 0xFFFFFFFFU; /* set Rx FIFO size */ - USB_OTG_GLB->GRXFSIZ = 0x200U; - USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); - USB_OTG_GLB->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); + USB_OTG_GLB->GRXFSIZ = CONFIG_USB_DWC2_RX_FIFO_SIZE; + USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((CONFIG_USB_DWC2_NPTX_FIFO_SIZE << 16) & USB_OTG_NPTXFD) | CONFIG_USB_DWC2_RX_FIFO_SIZE); + USB_OTG_GLB->HPTXFSIZ = (uint32_t)(((CONFIG_USB_DWC2_PTX_FIFO_SIZE << 16) & USB_OTG_HPTXFSIZ_PTXFD) | (CONFIG_USB_DWC2_RX_FIFO_SIZE + CONFIG_USB_DWC2_NPTX_FIFO_SIZE)); ret = dwc2_flush_txfifo(bus, 0x10U); ret = dwc2_flush_rxfifo(bus); @@ -491,7 +514,7 @@ int usb_hc_init(struct usbh_bus *bus) USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_GINT; - return 0; + return ret; } int usb_hc_deinit(struct usbh_bus *bus) @@ -899,7 +922,6 @@ static void dwc2_outchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num) uint32_t chan_intstatus; struct dwc2_chan *chan; struct usbh_urb *urb; - uint16_t buflen; chan_intstatus = USB_OTG_HC(ch_num)->HCINT;