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update novoton dcd driver and demo

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This commit is contained in:
sakumisu
2022-03-05 21:56:27 +08:00
parent 789783b256
commit 252e937ccf
23 changed files with 39123 additions and 4 deletions
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29089
demo/nuvoton/usb_device/nuc442/Device/Nuvoton/NUC472_442/Include/NUC472_442.h Normal file
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61
demo/nuvoton/usb_device/nuc442/Device/Nuvoton/NUC472_442/Include/system_NUC472_442.h Normal file
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/**************************************************************************//**
* @file system_NUC472_442.h
* @version V1.00
* $Revision: 5 $
* $Date: 14/05/29 1:13p $
* @brief NUC472/NUC442 system clock definition file
*
* @note
* SPDX-License-Identifier: Apache-2.0
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SYSTEM_NUC472_442_H__
#define __SYSTEM_NUC472_442_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __HXT (12000000UL) /*!< High Speed External Crystal Clock Frequency 12MHz */
#define __LXT (32768UL) /*!< Low Speed External Crystal Clock Frequency 32.768kHz */
#define __HIRC (22118400UL) /*!< High Speed Internal 22MHz RC Oscillator Frequency */
#define __LIRC (10000UL) /*!< Low Speed Internal 10kHz RC Oscillator Frequency */
#define __HSI (__HIRC) /* Factory Default is internal 12MHz */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
/**
* Initialize the system
*
* @return none
*
* @brief Setup the microcontroller system.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from CPU registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_NUC472_442_H__ */
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

543
demo/nuvoton/usb_device/nuc442/Device/Nuvoton/NUC472_442/Source/ARM/startup_NUC472_442.s Normal file
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;/******************************************************************************
; * @file startup_NUC472_442.s
; * @version V1.00
; * $Revision: 12 $
; * $Date: 15/09/22 10:25a $
; * @brief CMSIS ARM Cortex-M4 Core Device Startup File
; *
; * @note
; * SPDX-License-Identifier: Apache-2.0
; * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
;*****************************************************************************/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :LNOT: :DEF: Stack_Size
Stack_Size EQU 0x00001000
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :LNOT: :DEF: Heap_Size
Heap_Size EQU 0x00001000
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD BOD_IRQHandler ; 0: Brown Out detection
DCD IRC_IRQHandler ; 1: Internal RC
DCD PWRWU_IRQHandler ; 2: Power Down Wake Up
DCD SRAMF_IRQHandler ; 3: Reserved.
DCD CLKF_IRQHandler ; 4: CLKF
DCD Default_Handler ; 5: Reserved.
DCD RTC_IRQHandler ; 6: Real Time Clock
DCD TAMPER_IRQHandler ; 7: Tamper detection
DCD EINT0_IRQHandler ; 8: External Input 0
DCD EINT1_IRQHandler ; 9: External Input 1
DCD EINT2_IRQHandler ; 10: External Input 2
DCD EINT3_IRQHandler ; 11: External Input 3
DCD EINT4_IRQHandler ; 12: External Input 4
DCD EINT5_IRQHandler ; 13: External Input 5
DCD EINT6_IRQHandler ; 14: External Input 6
DCD EINT7_IRQHandler ; 15: External Input 7
DCD GPA_IRQHandler ; 16: GPIO Port A
DCD GPB_IRQHandler ; 17: GPIO Port B
DCD GPC_IRQHandler ; 18: GPIO Port C
DCD GPD_IRQHandler ; 19: GPIO Port D
DCD GPE_IRQHandler ; 20: GPIO Port E
DCD GPF_IRQHandler ; 21: GPIO Port F
DCD GPG_IRQHandler ; 22: GPIO Port G
DCD GPH_IRQHandler ; 23: GPIO Port H
DCD GPI_IRQHandler ; 24: GPIO Port I
DCD Default_Handler ; 25: Reserved.
DCD Default_Handler ; 26: Reserved.
DCD Default_Handler ; 27: Reserved.
DCD Default_Handler ; 28: Reserved.
DCD Default_Handler ; 29: Reserved.
DCD Default_Handler ; 30: Reserved.
DCD Default_Handler ; 31: Reserved.
DCD TMR0_IRQHandler ; 32: Timer 0
DCD TMR1_IRQHandler ; 33: Timer 1
DCD TMR2_IRQHandler ; 34: Timer 2
DCD TMR3_IRQHandler ; 35: Timer 3
DCD Default_Handler ; 36: Reserved.
DCD Default_Handler ; 37: Reserved.
DCD Default_Handler ; 38: Reserved.
DCD Default_Handler ; 39: Reserved.
DCD PDMA_IRQHandler ; 40: Peripheral DMA
DCD Default_Handler ; 41: Reserved.
DCD ADC_IRQHandler ; 42: ADC
DCD Default_Handler ; 43: Reserved.
DCD Default_Handler ; 44: Reserved.
DCD Default_Handler ; 45: Reserved.
DCD WDT_IRQHandler ; 46: Watch Dog Timer
DCD WWDT_IRQHandler ; 47: Window Watch Dog Timer
DCD EADC0_IRQHandler ; 48: EDAC 0
DCD EADC1_IRQHandler ; 49: EDAC 1
DCD EADC2_IRQHandler ; 50: EDAC 2
DCD EADC3_IRQHandler ; 51: EDAC 3
DCD Default_Handler ; 52: Reserved.
DCD Default_Handler ; 53: Reserved.
DCD Default_Handler ; 54: Reserved.
DCD Default_Handler ; 55: Reserved.
DCD ACMP_IRQHandler ; 56: Analog Comparator
DCD Default_Handler ; 57: Reserved.
DCD Default_Handler ; 58: Reserved.
DCD Default_Handler ; 59: Reserved.
DCD OPA0_IRQHandler ; 60: OPA 0
DCD OPA1_IRQHandler ; 61: OPA 1
DCD ICAP0_IRQHandler ; 62: ICAP 0
DCD ICAP1_IRQHandler ; 63: ICAP 1
DCD PWM0CH0_IRQHandler ; 64: PWM0 CH0
DCD PWM0CH1_IRQHandler ; 65: PWM0 CH1
DCD PWM0CH2_IRQHandler ; 66: PWM0 CH2
DCD PWM0CH3_IRQHandler ; 67: PWM0 CH3
DCD PWM0CH4_IRQHandler ; 68: PWM0 CH4
DCD PWM0CH5_IRQHandler ; 69: PWM0 CH5
DCD PWM0_BRK_IRQHandler ; 70: PWM0 Brake
DCD QEI0_IRQHandler ; 71: QEI 0
DCD PWM1CH0_IRQHandler ; 72: PWM1 CH0
DCD PWM1CH1_IRQHandler ; 73: PWM1 CH1
DCD PWM1CH2_IRQHandler ; 74: PWM1 CH2
DCD PWM1CH3_IRQHandler ; 75: PWM1 CH3
DCD PWM1CH4_IRQHandler ; 76: PWM1 CH4
DCD PWM1CH5_IRQHandler ; 77: PWM1 CH5
DCD PWM1_BRK_IRQHandler ; 78: PWM1 Brake
DCD QEI1_IRQHandler ; 79: QEI 1
DCD EPWM0_IRQHandler ; 80: EPWM0
DCD EPWM0BRK_IRQHandler ; 81: EPWM0 Brake
DCD EPWM1_IRQHandler ; 82: EPWM1
DCD EPWM1BRK_IRQHandler ; 83: EPWM1 Brake
DCD Default_Handler ; 84: Reserved.
DCD Default_Handler ; 85: Reserved.
DCD Default_Handler ; 86: Reserved.
DCD Default_Handler ; 87: Reserved.
DCD USBD_IRQHandler ; 88: USB Device
DCD USBH_IRQHandler ; 89: USB Host
DCD USB_OTG_IRQHandler ; 90: USB OTG
DCD Default_Handler ; 91: Reserved.
DCD EMAC_TX_IRQHandler ; 92: Ethernet MAC TX
DCD EMAC_RX_IRQHandler ; 93: Ethernet MAC RX
DCD Default_Handler ; 94: Reserved.
DCD Default_Handler ; 95: Reserved.
DCD SPI0_IRQHandler ; 96: SPI 0
DCD SPI1_IRQHandler ; 97: SPI 1
DCD SPI2_IRQHandler ; 98: SPI 2
DCD SPI3_IRQHandler ; 99: SPI 3
DCD Default_Handler ; 100: Reserved.
DCD Default_Handler ; 101: Reserved.
DCD Default_Handler ; 102: Reserved.
DCD Default_Handler ; 103: Reserved.
DCD UART0_IRQHandler ; 104: UART 0
DCD UART1_IRQHandler ; 105: UART 1
DCD UART2_IRQHandler ; 106: UART 2
DCD UART3_IRQHandler ; 107: UART 3
DCD UART4_IRQHandler ; 108: UART 4
DCD UART5_IRQHandler ; 109: UART 5
DCD Default_Handler ; 110: Reserved.
DCD Default_Handler ; 111: Reserved.
DCD I2C0_IRQHandler ; 112: I2C 0
DCD I2C1_IRQHandler ; 113: I2C 1
DCD I2C2_IRQHandler ; 114: I2C 2
DCD I2C3_IRQHandler ; 115: I2C 3
DCD I2C4_IRQHandler ; 116: I2C 4
DCD Default_Handler ; 117: Reserved.
DCD Default_Handler ; 118: Reserved.
DCD Default_Handler ; 119: Reserved.
DCD SC0_IRQHandler ; 120: Smart Card 0
DCD SC1_IRQHandler ; 121: Smart Card 1
DCD SC2_IRQHandler ; 122: Smart Card 2
DCD SC3_IRQHandler ; 123: Smart Card 3
DCD SC4_IRQHandler ; 124: Smart Card 4
DCD SC5_IRQHandler ; 125: Smart Card 5
DCD Default_Handler ; 126: Reserved.
DCD Default_Handler ; 127: Reserved.
DCD CAN0_IRQHandler ; 128: CAN 0
DCD CAN1_IRQHandler ; 129: CAN 1
DCD Default_Handler ; 130: Reserved.
DCD Default_Handler ; 131: Reserved.
DCD I2S0_IRQHandler ; 132: I2S 0
DCD I2S1_IRQHandler ; 133: I2S 1
DCD Default_Handler ; 134: Reserved.
DCD Default_Handler ; 135: Reserved.
DCD SD_IRQHandler ; 136: SD card
DCD Default_Handler ; 137: Reserved.
DCD PS2D_IRQHandler ; 138: PS/2 device
DCD CAP_IRQHandler ; 139: VIN
DCD CRYPTO_IRQHandler ; 140: CRYPTO
DCD CRC_IRQHandler ; 141: CRC
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
; Unlock Register
LDR R0, =0x40000100
LDR R1, =0x59
STR R1, [R0]
LDR R1, =0x16
STR R1, [R0]
LDR R1, =0x88
STR R1, [R0]
; Disable branch buffer if VCID is 0
LDR R2, =0x40000020
LDR R1, [R2]
CMP R1, #0
BNE Lock
LDR R2, =0x4000C018
LDR R1, [R2]
ORR R1, #0x80
STR R1, [R2]
Lock
; Init POR
LDR R2, =0x40000024
LDR R1, =0x00005AA5
STR R1, [R2]
; Lock register
MOVS R1, #0
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BOD_IRQHandler [WEAK]
EXPORT IRC_IRQHandler [WEAK]
EXPORT PWRWU_IRQHandler [WEAK]
EXPORT SRAMF_IRQHandler [WEAK]
EXPORT CLKF_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT EINT4_IRQHandler [WEAK]
EXPORT EINT5_IRQHandler [WEAK]
EXPORT EINT6_IRQHandler [WEAK]
EXPORT EINT7_IRQHandler [WEAK]
EXPORT GPA_IRQHandler [WEAK]
EXPORT GPB_IRQHandler [WEAK]
EXPORT GPC_IRQHandler [WEAK]
EXPORT GPD_IRQHandler [WEAK]
EXPORT GPE_IRQHandler [WEAK]
EXPORT GPF_IRQHandler [WEAK]
EXPORT GPG_IRQHandler [WEAK]
EXPORT GPH_IRQHandler [WEAK]
EXPORT GPI_IRQHandler [WEAK]
EXPORT TMR0_IRQHandler [WEAK]
EXPORT TMR1_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT PDMA_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT WWDT_IRQHandler [WEAK]
EXPORT EADC0_IRQHandler [WEAK]
EXPORT EADC1_IRQHandler [WEAK]
EXPORT EADC2_IRQHandler [WEAK]
EXPORT EADC3_IRQHandler [WEAK]
EXPORT ACMP_IRQHandler [WEAK]
EXPORT OPA0_IRQHandler [WEAK]
EXPORT OPA1_IRQHandler [WEAK]
EXPORT ICAP0_IRQHandler [WEAK]
EXPORT ICAP1_IRQHandler [WEAK]
EXPORT PWM0CH0_IRQHandler [WEAK]
EXPORT PWM0CH1_IRQHandler [WEAK]
EXPORT PWM0CH2_IRQHandler [WEAK]
EXPORT PWM0CH3_IRQHandler [WEAK]
EXPORT PWM0CH4_IRQHandler [WEAK]
EXPORT PWM0CH5_IRQHandler [WEAK]
EXPORT PWM0_BRK_IRQHandler [WEAK]
EXPORT QEI0_IRQHandler [WEAK]
EXPORT PWM1CH0_IRQHandler [WEAK]
EXPORT PWM1CH1_IRQHandler [WEAK]
EXPORT PWM1CH2_IRQHandler [WEAK]
EXPORT PWM1CH3_IRQHandler [WEAK]
EXPORT PWM1CH4_IRQHandler [WEAK]
EXPORT PWM1CH5_IRQHandler [WEAK]
EXPORT PWM1_BRK_IRQHandler [WEAK]
EXPORT QEI1_IRQHandler [WEAK]
EXPORT EPWM0_IRQHandler [WEAK]
EXPORT EPWM0BRK_IRQHandler [WEAK]
EXPORT EPWM1_IRQHandler [WEAK]
EXPORT EPWM1BRK_IRQHandler [WEAK]
EXPORT USBD_IRQHandler [WEAK]
EXPORT USBH_IRQHandler [WEAK]
EXPORT USB_OTG_IRQHandler [WEAK]
EXPORT EMAC_TX_IRQHandler [WEAK]
EXPORT EMAC_RX_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT I2C3_IRQHandler [WEAK]
EXPORT I2C4_IRQHandler [WEAK]
EXPORT SC0_IRQHandler [WEAK]
EXPORT SC1_IRQHandler [WEAK]
EXPORT SC2_IRQHandler [WEAK]
EXPORT SC3_IRQHandler [WEAK]
EXPORT SC4_IRQHandler [WEAK]
EXPORT SC5_IRQHandler [WEAK]
EXPORT CAN0_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
EXPORT SD_IRQHandler [WEAK]
EXPORT PS2D_IRQHandler [WEAK]
EXPORT CAP_IRQHandler [WEAK]
EXPORT CRYPTO_IRQHandler [WEAK]
EXPORT CRC_IRQHandler [WEAK]
Default__IRQHandler
BOD_IRQHandler
IRC_IRQHandler
PWRWU_IRQHandler
SRAMF_IRQHandler
CLKF_IRQHandler
RTC_IRQHandler
TAMPER_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
EINT4_IRQHandler
EINT5_IRQHandler
EINT6_IRQHandler
EINT7_IRQHandler
GPA_IRQHandler
GPB_IRQHandler
GPC_IRQHandler
GPD_IRQHandler
GPE_IRQHandler
GPF_IRQHandler
GPG_IRQHandler
GPH_IRQHandler
GPI_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
PDMA_IRQHandler
ADC_IRQHandler
WDT_IRQHandler
WWDT_IRQHandler
EADC0_IRQHandler
EADC1_IRQHandler
EADC2_IRQHandler
EADC3_IRQHandler
ACMP_IRQHandler
OPA0_IRQHandler
OPA1_IRQHandler
ICAP0_IRQHandler
ICAP1_IRQHandler
PWM0CH0_IRQHandler
PWM0CH1_IRQHandler
PWM0CH2_IRQHandler
PWM0CH3_IRQHandler
PWM0CH4_IRQHandler
PWM0CH5_IRQHandler
PWM0_BRK_IRQHandler
QEI0_IRQHandler
PWM1CH0_IRQHandler
PWM1CH1_IRQHandler
PWM1CH2_IRQHandler
PWM1CH3_IRQHandler
PWM1CH4_IRQHandler
PWM1CH5_IRQHandler
PWM1_BRK_IRQHandler
QEI1_IRQHandler
EPWM0_IRQHandler
EPWM0BRK_IRQHandler
EPWM1_IRQHandler
EPWM1BRK_IRQHandler
USBD_IRQHandler
USBH_IRQHandler
USB_OTG_IRQHandler
EMAC_TX_IRQHandler
EMAC_RX_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
SPI3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
I2C3_IRQHandler
I2C4_IRQHandler
SC0_IRQHandler
SC1_IRQHandler
SC2_IRQHandler
SC3_IRQHandler
SC4_IRQHandler
SC5_IRQHandler
CAN0_IRQHandler
CAN1_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SD_IRQHandler
PS2D_IRQHandler
CAP_IRQHandler
CRYPTO_IRQHandler
CRC_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
;/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

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demo/nuvoton/usb_device/nuc442/Device/Nuvoton/NUC472_442/Source/GCC/_syscalls.c Normal file
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195
demo/nuvoton/usb_device/nuc442/Device/Nuvoton/NUC472_442/Source/GCC/gcc_arm.ld Normal file
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/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* 512k */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000 /* 64k */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.vectors))
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
/*
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
LONG (__etext2)
LONG (__data2_start__)
LONG (__data2_end__ - __data2_start__)
__copy_table_end__ = .;
} > FLASH
*/
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
/*
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (__bss2_start__)
LONG (__bss2_end__ - __bss2_start__)
__zero_table_end__ = .;
} > FLASH
*/
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
KEEP(*(.stack*))
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

116
demo/nuvoton/usb_device/nuc442/Device/Nuvoton/NUC472_442/Source/GCC/semihosting.h Normal file
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#ifndef ARM_SEMIHOSTING_H_
#define ARM_SEMIHOSTING_H_
// ----------------------------------------------------------------------------
// Semihosting operations.
enum OperationNumber
{
// Regular operations
SEMIHOSTING_EnterSVC = 0x17,
SEMIHOSTING_ReportException = 0x18,
SEMIHOSTING_SYS_CLOSE = 0x02,
SEMIHOSTING_SYS_CLOCK = 0x10,
SEMIHOSTING_SYS_ELAPSED = 0x30,
SEMIHOSTING_SYS_ERRNO = 0x13,
SEMIHOSTING_SYS_FLEN = 0x0C,
SEMIHOSTING_SYS_GET_CMDLINE = 0x15,
SEMIHOSTING_SYS_HEAPINFO = 0x16,
SEMIHOSTING_SYS_ISERROR = 0x08,
SEMIHOSTING_SYS_ISTTY = 0x09,
SEMIHOSTING_SYS_OPEN = 0x01,
SEMIHOSTING_SYS_READ = 0x06,
SEMIHOSTING_SYS_READC = 0x07,
SEMIHOSTING_SYS_REMOVE = 0x0E,
SEMIHOSTING_SYS_RENAME = 0x0F,
SEMIHOSTING_SYS_SEEK = 0x0A,
SEMIHOSTING_SYS_SYSTEM = 0x12,
SEMIHOSTING_SYS_TICKFREQ = 0x31,
SEMIHOSTING_SYS_TIME = 0x11,
SEMIHOSTING_SYS_TMPNAM = 0x0D,
SEMIHOSTING_SYS_WRITE = 0x05,
SEMIHOSTING_SYS_WRITEC = 0x03,
SEMIHOSTING_SYS_WRITE0 = 0x04,
// Codes returned by SEMIHOSTING_ReportException
ADP_Stopped_ApplicationExit = ((2 << 16) + 38),
ADP_Stopped_RunTimeError = ((2 << 16) + 35),
};
// ----------------------------------------------------------------------------
// SWI numbers and reason codes for RDI (Angel) monitors.
#define AngelSWI_ARM 0x123456
#ifdef __thumb__
#define AngelSWI 0xAB
#else
#define AngelSWI AngelSWI_ARM
#endif
// For thumb only architectures use the BKPT instruction instead of SWI.
#if defined(__ARM_ARCH_7M__) \
|| defined(__ARM_ARCH_7EM__) \
|| defined(__ARM_ARCH_6M__)
#define AngelSWIInsn "bkpt"
#define AngelSWIAsm bkpt
#else
#define AngelSWIInsn "swi"
#define AngelSWIAsm swi
#endif
#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
// Testing the local semihosting handler cannot use another BKPT, since this
// configuration cannot trigger HaedFault exceptions while the debugger is
// connected, so we use an illegal op code, that will trigger an
// UsageFault exception.
#define AngelSWITestFault "setend be"
#define AngelSWITestFaultOpCode (0xB658)
#endif
static inline int
__attribute__ ((always_inline))
call_host (int reason, void* arg)
{
int value;
asm volatile (
" mov r0, %[rsn] \n"
" mov r1, %[arg] \n"
#if defined(OS_DEBUG_SEMIHOSTING_FAULTS)
" " AngelSWITestFault " \n"
#else
" " AngelSWIInsn " %[swi] \n"
#endif
" mov %[val], r0"
: [val] "=r" (value) /* Outputs */
: [rsn] "r" (reason), [arg] "r" (arg), [swi] "i" (AngelSWI) /* Inputs */
: "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"
// Clobbers r0 and r1, and lr if in supervisor mode
);
// Accordingly to page 13-77 of ARM DUI 0040D other registers
// can also be clobbered. Some memory positions may also be
// changed by a system call, so they should not be kept in
// registers. Note: we are assuming the manual is right and
// Angel is respecting the APCS.
return value;
}
// ----------------------------------------------------------------------------
// Function used in _exit() to return the status code as Angel exception.
static inline void
__attribute__ ((always_inline,noreturn))
report_exception (int reason)
{
call_host (SEMIHOSTING_ReportException, (void*) reason);
for (;;)
;
}
// ----------------------------------------------------------------------------
#endif // ARM_SEMIHOSTING_H_

502
demo/nuvoton/usb_device/nuc442/Device/Nuvoton/NUC472_442/Source/GCC/startup_NUC472_442.S Normal file
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/****************************************************************************//**
* @file startup_NUC472_442.S
* @version V1.00
* @brief CMSIS Cortex-M4 Core Device Startup File for NUC472_442
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
.syntax unified
.arch armv7-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00000800
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000100
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long BOD_IRQHandler /* 0: BOD */
.long IRC_IRQHandler /* 1: IRC */
.long PWRWU_IRQHandler /* 2: PWRWU */
.long RAMPE_IRQHandler /* 3: RAMPE */
.long CKFAIL_IRQHandler /* 4: CKFAIL */
.long 0 /* 5: Reserved */
.long RTC_IRQHandler /* 6: RTC */
.long TAMPER_IRQHandler /* 7: TAMPER */
.long EINT0_IRQHandler /* 8: EINT0 */
.long EINT1_IRQHandler /* 9: EINT1 */
.long EINT2_IRQHandler /* 10: EINT2 */
.long EINT3_IRQHandler /* 11: EINT3 */
.long EINT4_IRQHandler /* 12: EINT4 */
.long EINT5_IRQHandler /* 13: EINT5 */
.long EINT6_IRQHandler /* 14: EINT6 */
.long EINT7_IRQHandler /* 15: EINT7 */
.long GPA_IRQHandler /* 16: GPA */
.long GPB_IRQHandler /* 17: GPB */
.long GPC_IRQHandler /* 18: GPC */
.long GPD_IRQHandler /* 19: GPD */
.long GPE_IRQHandler /* 20: GPE */
.long GPF_IRQHandler /* 21: GPF */
.long GPG_IRQHandler /* 22: GPG */
.long GPH_IRQHandler /* 23: GPH */
.long GPI_IRQHandler /* 24: GPI */
.long 0 /* 25: Reserved */
.long 0 /* 26: Reserved */
.long 0 /* 27: Reserved */
.long 0 /* 28: Reserved */
.long 0 /* 29: Reserved */
.long 0 /* 30: Reserved */
.long 0 /* 31: Reserved */
.long TMR0_IRQHandler /* 32: TIMER0 */
.long TMR1_IRQHandler /* 33: TIMER1 */
.long TMR2_IRQHandler /* 34: TIMER2 */
.long TMR3_IRQHandler /* 35: TIMER3 */
.long 0 /* 36: Reserved */
.long 0 /* 37: Reserved */
.long 0 /* 38: Reserved */
.long 0 /* 39: Reserved */
.long PDMA_IRQHandler /* 40: PDMA */
.long 0 /* 41: Reserved */
.long ADC_IRQHandler /* 42: ADC */
.long 0 /* 43: Reserved */
.long 0 /* 44: Reserved */
.long 0 /* 45: Reserved */
.long WDT_IRQHandler /* 46: WDT */
.long WWDT_IRQHandler /* 47: WWDT */
.long EADC0_IRQHandler /* 48: EADC0 */
.long EADC1_IRQHandler /* 49: EADC1 */
.long EADC2_IRQHandler /* 50: EADC2 */
.long EADC3_IRQHandler /* 51: EADC3 */
.long 0 /* 52: Reserved */
.long 0 /* 53: Reserved */
.long 0 /* 54: Reserved */
.long 0 /* 55: Reserved */
.long ACMP_IRQHandler /* 56: ACMP */
.long 0 /* 57: Reserved */
.long 0 /* 58: Reserved */
.long 0 /* 59: Reserved */
.long OPA0_IRQHandler /* 60: OPA0 */
.long OPA1_IRQHandler /* 61: OPA1 */
.long ICAP0_IRQHandler /* 62: ICAP0 */
.long ICAP1_IRQHandler /* 63: ICAP1 */
.long PWM0CH0_IRQHandler /* 64: PWM00 */
.long PWM0CH1_IRQHandler /* 65: PWM01 */
.long PWM0CH2_IRQHandler /* 66: PWM02 */
.long PWM0CH3_IRQHandler /* 67: PWM03 */
.long PWM0CH4_IRQHandler /* 68: PWM04 */
.long PWM0CH5_IRQHandler /* 69: PWM05 */
.long PWM0_BRK_IRQHandler /* 70: PWM0BRK */
.long QEI0_IRQHandler /* 71: QEI0 */
.long PWM1CH0_IRQHandler /* 72: PWM10 */
.long PWM1CH1_IRQHandler /* 73: PWM11 */
.long PWM1CH2_IRQHandler /* 74: PWM12 */
.long PWM1CH3_IRQHandler /* 75: PWM13 */
.long PWM1CH4_IRQHandler /* 76: PWM14 */
.long PWM1CH5_IRQHandler /* 77: PWM15 */
.long PWM1_BRK_IRQHandler /* 78: PWM1BRK */
.long QEI1_IRQHandler /* 79: QEI1 */
.long EPWM0_IRQHandler /* 80: EPWM0 */
.long EPWM0BRK_IRQHandler /* 81: EPWM0BRK */
.long EPWM1_IRQHandler /* 82: EPWM1 */
.long EPWM1BRK_IRQHandler /* 83: EPWM1BRK */
.long 0 /* 84: Reserved */
.long 0 /* 85: Reserved */
.long 0 /* 86: Reserved */
.long 0 /* 87: Reserved */
.long USBD_IRQHandler /* 88: USBD */
.long USBH_IRQHandler /* 89: USBH */
.long USB_OTG_IRQHandler /* 90: USBOTG */
.long 0 /* 91: Reserved */
.long EMAC_TX_IRQHandler /* 92: EMAXTC */
.long EMAC_RX_IRQHandler /* 93: EMACRX */
.long 0 /* 94: Reserved */
.long 0 /* 95: Reserved */
.long SPI0_IRQHandler /* 96: SPI0 */
.long SPI1_IRQHandler /* 97: SPI1 */
.long SPI2_IRQHandler /* 98: SPI2 */
.long SPI3_IRQHandler /* 99: SPI3 */
.long 0 /* 100: Reserved */
.long 0 /* 101: Reserved */
.long 0 /* 102: Reserved */
.long 0 /* 103: Reserved */
.long UART0_IRQHandler /* 104: UART0 */
.long UART1_IRQHandler /* 105: UART1 */
.long UART2_IRQHandler /* 106: UART2 */
.long UART3_IRQHandler /* 107: UART3 */
.long UART4_IRQHandler /* 108: UART4 */
.long UART5_IRQHandler /* 109: UART5 */
.long 0 /* 110: Reserved */
.long 0 /* 111: Reserved */
.long I2C0_IRQHandler /* 112: I2C0 */
.long I2C1_IRQHandler /* 113: I2C1 */
.long I2C2_IRQHandler /* 114: I2C2 */
.long I2C3_IRQHandler /* 115: I2C3 */
.long I2C4_IRQHandler /* 116: I2C4 */
.long 0 /* 117: Reserved */
.long 0 /* 118: Reserved */
.long 0 /* 119: Reserved */
.long SC0_IRQHandler /* 120: SC0 */
.long SC1_IRQHandler /* 121: SC1 */
.long SC2_IRQHandler /* 122: SC2 */
.long SC3_IRQHandler /* 123: SC3 */
.long SC4_IRQHandler /* 124: SC4 */
.long SC5_IRQHandler /* 125: SC5 */
.long 0 /* 126: Reserved */
.long 0 /* 127: Reserved */
.long CAN0_IRQHandler /* 128: CAN0 */
.long CAN1_IRQHandler /* 129: CAN1 */
.long 0 /* 130: Reserved */
.long 0 /* 131: Reserved */
.long I2S0_IRQHandler /* 132: I2S0 */
.long I2S1_IRQHandler /* 133: I2S1 */
.long 0 /* 134: Reserved */
.long 0 /* 135: Reserved */
.long SD_IRQHandler /* 136: SD */
.long 0 /* 137: Reserved */
.long PS2D_IRQHandler /* 138: PS2D */
.long CAP_IRQHandler /* 139: CAP */
.long CRYPTO_IRQHandler /* 140: CRYPTO */
.long CRC_IRQHandler /* 141: CRC */
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
/* Unlock Register */
ldr r0, =0x40000100
ldr r1, =0x59
str r1, [r0]
ldr r1, =0x16
str r1, [r0]
ldr r1, =0x88
str r1, [r0]
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
/* Init POR */
ldr r0, =0x40000024
ldr r1, =0x00005AA5
str r1, [r0]
/* Disable branch buffer if VCID is 0 */
ldr r0, =0x40000020
ldr r1, [r0]
cmp r1, #0
bne Lock
ldr r0, =0x4000C018
ldr r1, [r0]
ORR r1, #0x80
str r1, [r0]
Lock:
/* Lock register */
ldr r0, =0x40000100
ldr r1, =0
str r1, [r0]
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler BOD_IRQHandler
def_irq_handler IRC_IRQHandler
def_irq_handler PWRWU_IRQHandler
def_irq_handler RAMPE_IRQHandler
def_irq_handler CKFAIL_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler TAMPER_IRQHandler
def_irq_handler EINT0_IRQHandler
def_irq_handler EINT1_IRQHandler
def_irq_handler EINT2_IRQHandler
def_irq_handler EINT3_IRQHandler
def_irq_handler EINT4_IRQHandler
def_irq_handler EINT5_IRQHandler
def_irq_handler EINT6_IRQHandler
def_irq_handler EINT7_IRQHandler
def_irq_handler GPA_IRQHandler
def_irq_handler GPB_IRQHandler
def_irq_handler GPC_IRQHandler
def_irq_handler GPD_IRQHandler
def_irq_handler GPE_IRQHandler
def_irq_handler GPF_IRQHandler
def_irq_handler GPG_IRQHandler
def_irq_handler GPH_IRQHandler
def_irq_handler GPI_IRQHandler
def_irq_handler TMR0_IRQHandler
def_irq_handler TMR1_IRQHandler
def_irq_handler TMR2_IRQHandler
def_irq_handler TMR3_IRQHandler
def_irq_handler PDMA_IRQHandler
def_irq_handler ADC_IRQHandler
def_irq_handler WDT_IRQHandler
def_irq_handler WWDT_IRQHandler
def_irq_handler EADC0_IRQHandler
def_irq_handler EADC1_IRQHandler
def_irq_handler EADC2_IRQHandler
def_irq_handler EADC3_IRQHandler
def_irq_handler ACMP_IRQHandler
def_irq_handler OPA0_IRQHandler
def_irq_handler OPA1_IRQHandler
def_irq_handler ICAP0_IRQHandler
def_irq_handler ICAP1_IRQHandler
def_irq_handler PWM0CH0_IRQHandler
def_irq_handler PWM0CH1_IRQHandler
def_irq_handler PWM0CH2_IRQHandler
def_irq_handler PWM0CH3_IRQHandler
def_irq_handler PWM0CH4_IRQHandler
def_irq_handler PWM0CH5_IRQHandler
def_irq_handler PWM0_BRK_IRQHandler
def_irq_handler QEI0_IRQHandler
def_irq_handler PWM1CH0_IRQHandler
def_irq_handler PWM1CH1_IRQHandler
def_irq_handler PWM1CH2_IRQHandler
def_irq_handler PWM1CH3_IRQHandler
def_irq_handler PWM1CH4_IRQHandler
def_irq_handler PWM1CH5_IRQHandler
def_irq_handler PWM1_BRK_IRQHandler
def_irq_handler QEI1_IRQHandler
def_irq_handler EPWM0_IRQHandler
def_irq_handler EPWM0BRK_IRQHandler
def_irq_handler EPWM1_IRQHandler
def_irq_handler EPWM1BRK_IRQHandler
def_irq_handler USBD_IRQHandler
def_irq_handler USBH_IRQHandler
def_irq_handler USB_OTG_IRQHandler
def_irq_handler EMAC_TX_IRQHandler
def_irq_handler EMAC_RX_IRQHandler
def_irq_handler SPI0_IRQHandler
def_irq_handler SPI1_IRQHandler
def_irq_handler SPI2_IRQHandler
def_irq_handler SPI3_IRQHandler
def_irq_handler UART0_IRQHandler
def_irq_handler UART1_IRQHandler
def_irq_handler UART2_IRQHandler
def_irq_handler UART3_IRQHandler
def_irq_handler UART4_IRQHandler
def_irq_handler UART5_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler I2C1_IRQHandler
def_irq_handler I2C2_IRQHandler
def_irq_handler I2C3_IRQHandler
def_irq_handler I2C4_IRQHandler
def_irq_handler SC0_IRQHandler
def_irq_handler SC1_IRQHandler
def_irq_handler SC2_IRQHandler
def_irq_handler SC3_IRQHandler
def_irq_handler SC4_IRQHandler
def_irq_handler SC5_IRQHandler
def_irq_handler CAN0_IRQHandler
def_irq_handler CAN1_IRQHandler
def_irq_handler I2S0_IRQHandler
def_irq_handler I2S1_IRQHandler
def_irq_handler SD_IRQHandler
def_irq_handler PS2D_IRQHandler
def_irq_handler CAP_IRQHandler
def_irq_handler CRYPTO_IRQHandler
def_irq_handler CRC_IRQHandler
.end

482
demo/nuvoton/usb_device/nuc442/Device/Nuvoton/NUC472_442/Source/IAR/startup_NUC472_442.s Normal file
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;/******************************************************************************
; * @file startup_NUC472_442.s
; * @version V1.00
; * $Revision: 11 $
; * $Date: 16/06/07 2:34p $
; * @brief CMSIS ARM Cortex-M4 Core Device Startup File
; *
; * @note
; * SPDX-License-Identifier: Apache-2.0
; * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
;*****************************************************************************/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN HardFault_Handler
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD BOD_IRQHandler ; 0: Brown Out detection
DCD IRC_IRQHandler ; 1: Internal RC
DCD PWRWU_IRQHandler ; 2: Power Down Wake Up
DCD Default_Handler ; 3: Reserved.
DCD CLKF_IRQHandler ; 4: CLKF
DCD Default_Handler ; 5: Reserved.
DCD RTC_IRQHandler ; 6: Real Time Clock
DCD TAMPER_IRQHandler ; 7: Tamper detection
DCD EINT0_IRQHandler ; 8: External Input 0
DCD EINT1_IRQHandler ; 9: External Input 1
DCD EINT2_IRQHandler ; 10: External Input 2
DCD EINT3_IRQHandler ; 11: External Input 3
DCD EINT4_IRQHandler ; 12: External Input 4
DCD EINT5_IRQHandler ; 13: External Input 5
DCD EINT6_IRQHandler ; 14: External Input 6
DCD EINT7_IRQHandler ; 15: External Input 7
DCD GPA_IRQHandler ; 16: GPIO Port A
DCD GPB_IRQHandler ; 17: GPIO Port B
DCD GPC_IRQHandler ; 18: GPIO Port C
DCD GPD_IRQHandler ; 19: GPIO Port D
DCD GPE_IRQHandler ; 20: GPIO Port E
DCD GPF_IRQHandler ; 21: GPIO Port F
DCD GPG_IRQHandler ; 22: GPIO Port G
DCD GPH_IRQHandler ; 23: GPIO Port H
DCD GPI_IRQHandler ; 24: GPIO Port I
DCD Default_Handler ; 25: Reserved.
DCD Default_Handler ; 26: Reserved.
DCD Default_Handler ; 27: Reserved.
DCD Default_Handler ; 28: Reserved.
DCD Default_Handler ; 29: Reserved.
DCD Default_Handler ; 30: Reserved.
DCD Default_Handler ; 31: Reserved.
DCD TMR0_IRQHandler ; 32: Timer 0
DCD TMR1_IRQHandler ; 33: Timer 1
DCD TMR2_IRQHandler ; 34: Timer 2
DCD TMR3_IRQHandler ; 35: Timer 3
DCD Default_Handler ; 36: Reserved.
DCD Default_Handler ; 37: Reserved.
DCD Default_Handler ; 38: Reserved.
DCD Default_Handler ; 39: Reserved.
DCD PDMA_IRQHandler ; 40: Peripheral DMA
DCD Default_Handler ; 41: Reserved.
DCD ADC_IRQHandler ; 42: ADC
DCD Default_Handler ; 43: Reserved.
DCD Default_Handler ; 44: Reserved.
DCD Default_Handler ; 45: Reserved.
DCD WDT_IRQHandler ; 46: Watch Dog Timer
DCD WWDT_IRQHandler ; 47: Window Watch Dog Timer
DCD EADC0_IRQHandler ; 48: EADC 0
DCD EADC1_IRQHandler ; 49: EADC 1
DCD EADC2_IRQHandler ; 50: EADC 2
DCD EADC3_IRQHandler ; 51: EADC 3
DCD Default_Handler ; 52: Reserved.
DCD Default_Handler ; 53: Reserved.
DCD Default_Handler ; 54: Reserved.
DCD Default_Handler ; 55: Reserved.
DCD ACMP_IRQHandler ; 56: Analog Comparator
DCD Default_Handler ; 57: Reserved.
DCD Default_Handler ; 58: Reserved.
DCD Default_Handler ; 59: Reserved.
DCD OPA0_IRQHandler ; 60: OPA 0
DCD OPA1_IRQHandler ; 61: OPA 1
DCD ICAP0_IRQHandler ; 62: ICAP 0
DCD ICAP1_IRQHandler ; 63: ICAP 1
DCD PWM0CH0_IRQHandler ; 64: PWMA CH0
DCD PWM0CH1_IRQHandler ; 65: PWMA CH1
DCD PWM0CH2_IRQHandler ; 66: PWMA CH2
DCD PWM0CH3_IRQHandler ; 67: PWMA CH3
DCD PWM0CH4_IRQHandler ; 68: PWMA CH4
DCD PWM0CH5_IRQHandler ; 69: PWMA CH5
DCD PWM0_BRK_IRQHandler ; 70: PWMA Brake
DCD QEI0_IRQHandler ; 71: QEI 0
DCD PWM1CH0_IRQHandler ; 72: PWM1 CH0
DCD PWM1CH1_IRQHandler ; 73: PWM1 CH1
DCD PWM1CH2_IRQHandler ; 74: PWM1 CH2
DCD PWM1CH3_IRQHandler ; 75: PWM1 CH3
DCD PWM1CH4_IRQHandler ; 76: PWM1 CH4
DCD PWM1CH5_IRQHandler ; 77: PWM1 CH5
DCD PWM1_BRK_IRQHandler ; 78: PWM1 Brake
DCD QEI1_IRQHandler ; 79: QEI 1
DCD EPWM0_IRQHandler ; 80: EPWM0
DCD EPWM0BRK_IRQHandler ; 81: EPWM0 Brake
DCD EPWM1_IRQHandler ; 82: EPWM1
DCD EPWM1BRK_IRQHandler ; 83: EPWM1 Brake
DCD Default_Handler ; 84: Reserved.
DCD Default_Handler ; 85: Reserved.
DCD Default_Handler ; 86: Reserved.
DCD Default_Handler ; 87: Reserved.
DCD USBD_IRQHandler ; 88: USB Device
DCD USBH_IRQHandler ; 89: USB Host
DCD USB_OTG_IRQHandler ; 90: USB OTG
DCD Default_Handler ; 91: Reserved.
DCD EMAC_TX_IRQHandler ; 92: Ethernet MAC TX
DCD EMAC_RX_IRQHandler ; 93: Ethernet MAC RX
DCD Default_Handler ; 94: Reserved.
DCD Default_Handler ; 95: Reserved.
DCD SPI0_IRQHandler ; 96: SPI 0
DCD SPI1_IRQHandler ; 97: SPI 1
DCD SPI2_IRQHandler ; 98: SPI 2
DCD SPI3_IRQHandler ; 99: SPI 3
DCD Default_Handler ; 100: Reserved.
DCD Default_Handler ; 101: Reserved.
DCD Default_Handler ; 102: Reserved.
DCD Default_Handler ; 103: Reserved.
DCD UART0_IRQHandler ; 104: UART 0
DCD UART1_IRQHandler ; 105: UART 1
DCD UART2_IRQHandler ; 106: UART 2
DCD UART3_IRQHandler ; 107: UART 3
DCD UART4_IRQHandler ; 108: UART 4
DCD UART5_IRQHandler ; 109: UART 5
DCD Default_Handler ; 110: Reserved.
DCD Default_Handler ; 111: Reserved.
DCD I2C0_IRQHandler ; 112: I2C 0
DCD I2C1_IRQHandler ; 113: I2C 1
DCD I2C2_IRQHandler ; 114: I2C 2
DCD I2C3_IRQHandler ; 115: I2C 3
DCD I2C4_IRQHandler ; 116: I2C 4
DCD Default_Handler ; 117: Reserved.
DCD Default_Handler ; 118: Reserved.
DCD Default_Handler ; 119: Reserved.
DCD SC0_IRQHandler ; 120: Smart Card 0
DCD SC1_IRQHandler ; 121: Smart Card 1
DCD SC2_IRQHandler ; 122: Smart Card 2
DCD SC3_IRQHandler ; 123: Smart Card 3
DCD SC4_IRQHandler ; 124: Smart Card 4
DCD SC5_IRQHandler ; 125: Smart Card 5
DCD Default_Handler ; 126: Reserved.
DCD Default_Handler ; 127: Reserved.
DCD CAN0_IRQHandler ; 128: CAN 0
DCD CAN1_IRQHandler ; 129: CAN 1
DCD Default_Handler ; 130: Reserved.
DCD Default_Handler ; 131: Reserved.
DCD I2S0_IRQHandler ; 132: I2S 0
DCD I2S1_IRQHandler ; 133: I2S 1
DCD Default_Handler ; 134: Reserved.
DCD Default_Handler ; 135: Reserved.
DCD SD_IRQHandler ; 136: SD card
DCD Default_Handler ; 137: Reserved.
DCD PS2D_IRQHandler ; 138: PS/2 device
DCD CAP_IRQHandler ; 139: CAP
DCD CRYPTO_IRQHandler ; 140: CRYPTO
DCD CRC_IRQHandler ; 141: CRC
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =0x40000100
; Unlock Register
LDR R1, =0x59
STR R1, [R0]
LDR R1, =0x16
STR R1, [R0]
LDR R1, =0x88
STR R1, [R0]
; Init POR
LDR R2, =0x40000024
LDR R1, =0x00005AA5
STR R1, [R2]
; Disable branch buffer if VCID is 0
LDR R2, =0x40000020
LDR R1, [R2]
CMP R1, #0
BNE Lock
LDR R2, =0x4000C018
LDR R1, [R2]
ORR R1, R1, #0x80
STR R1, [R2]
Lock
; Lock register
MOVS R1, #0
STR R1, [R0]
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK BOD_IRQHandler
PUBWEAK IRC_IRQHandler
PUBWEAK PWRWU_IRQHandler
PUBWEAK CLKF_IRQHandler
PUBWEAK RTC_IRQHandler
PUBWEAK TAMPER_IRQHandler
PUBWEAK EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
PUBWEAK EINT2_IRQHandler
PUBWEAK EINT3_IRQHandler
PUBWEAK EINT4_IRQHandler
PUBWEAK EINT5_IRQHandler
PUBWEAK EINT6_IRQHandler
PUBWEAK EINT7_IRQHandler
PUBWEAK GPA_IRQHandler
PUBWEAK GPB_IRQHandler
PUBWEAK GPC_IRQHandler
PUBWEAK GPD_IRQHandler
PUBWEAK GPE_IRQHandler
PUBWEAK GPF_IRQHandler
PUBWEAK GPG_IRQHandler
PUBWEAK GPH_IRQHandler
PUBWEAK GPI_IRQHandler
PUBWEAK TMR0_IRQHandler
PUBWEAK TMR1_IRQHandler
PUBWEAK TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
PUBWEAK PDMA_IRQHandler
PUBWEAK ADC_IRQHandler
PUBWEAK WDT_IRQHandler
PUBWEAK WWDT_IRQHandler
PUBWEAK EADC0_IRQHandler
PUBWEAK EADC1_IRQHandler
PUBWEAK EADC2_IRQHandler
PUBWEAK EADC3_IRQHandler
PUBWEAK ACMP_IRQHandler
PUBWEAK OPA0_IRQHandler
PUBWEAK OPA1_IRQHandler
PUBWEAK ICAP0_IRQHandler
PUBWEAK ICAP1_IRQHandler
PUBWEAK PWM0CH0_IRQHandler
PUBWEAK PWM0CH1_IRQHandler
PUBWEAK PWM0CH2_IRQHandler
PUBWEAK PWM0CH3_IRQHandler
PUBWEAK PWM0CH4_IRQHandler
PUBWEAK PWM0CH5_IRQHandler
PUBWEAK PWM0_BRK_IRQHandler
PUBWEAK QEI0_IRQHandler
PUBWEAK PWM1CH0_IRQHandler
PUBWEAK PWM1CH1_IRQHandler
PUBWEAK PWM1CH2_IRQHandler
PUBWEAK PWM1CH3_IRQHandler
PUBWEAK PWM1CH4_IRQHandler
PUBWEAK PWM1CH5_IRQHandler
PUBWEAK PWM1_BRK_IRQHandler
PUBWEAK QEI1_IRQHandler
PUBWEAK EPWM0_IRQHandler
PUBWEAK EPWM0BRK_IRQHandler
PUBWEAK EPWM1_IRQHandler
PUBWEAK EPWM1BRK_IRQHandler
PUBWEAK USBD_IRQHandler
PUBWEAK USBH_IRQHandler
PUBWEAK USB_OTG_IRQHandler
PUBWEAK EMAC_TX_IRQHandler
PUBWEAK EMAC_RX_IRQHandler
PUBWEAK SPI0_IRQHandler
PUBWEAK SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
PUBWEAK SPI3_IRQHandler
PUBWEAK UART0_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK UART2_IRQHandler
PUBWEAK UART3_IRQHandler
PUBWEAK UART4_IRQHandler
PUBWEAK UART5_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK I2C2_IRQHandler
PUBWEAK I2C3_IRQHandler
PUBWEAK I2C4_IRQHandler
PUBWEAK SC0_IRQHandler
PUBWEAK SC1_IRQHandler
PUBWEAK SC2_IRQHandler
PUBWEAK SC3_IRQHandler
PUBWEAK SC4_IRQHandler
PUBWEAK SC5_IRQHandler
PUBWEAK CAN0_IRQHandler
PUBWEAK CAN1_IRQHandler
PUBWEAK I2S0_IRQHandler
PUBWEAK I2S1_IRQHandler
PUBWEAK SD_IRQHandler
PUBWEAK PS2D_IRQHandler
PUBWEAK CAP_IRQHandler
PUBWEAK CRYPTO_IRQHandler
PUBWEAK CRC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
BOD_IRQHandler
IRC_IRQHandler
PWRWU_IRQHandler
CLKF_IRQHandler
RTC_IRQHandler
TAMPER_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
EINT4_IRQHandler
EINT5_IRQHandler
EINT6_IRQHandler
EINT7_IRQHandler
GPA_IRQHandler
GPB_IRQHandler
GPC_IRQHandler
GPD_IRQHandler
GPE_IRQHandler
GPF_IRQHandler
GPG_IRQHandler
GPH_IRQHandler
GPI_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
PDMA_IRQHandler
ADC_IRQHandler
WDT_IRQHandler
WWDT_IRQHandler
EADC0_IRQHandler
EADC1_IRQHandler
EADC2_IRQHandler
EADC3_IRQHandler
ACMP_IRQHandler
OPA0_IRQHandler
OPA1_IRQHandler
ICAP0_IRQHandler
ICAP1_IRQHandler
PWM0CH0_IRQHandler
PWM0CH1_IRQHandler
PWM0CH2_IRQHandler
PWM0CH3_IRQHandler
PWM0CH4_IRQHandler
PWM0CH5_IRQHandler
PWM0_BRK_IRQHandler
QEI0_IRQHandler
PWM1CH0_IRQHandler
PWM1CH1_IRQHandler
PWM1CH2_IRQHandler
PWM1CH3_IRQHandler
PWM1CH4_IRQHandler
PWM1CH5_IRQHandler
PWM1_BRK_IRQHandler
QEI1_IRQHandler
EPWM0_IRQHandler
EPWM0BRK_IRQHandler
EPWM1_IRQHandler
EPWM1BRK_IRQHandler
USBD_IRQHandler
USBH_IRQHandler
USB_OTG_IRQHandler
EMAC_TX_IRQHandler
EMAC_RX_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
SPI3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
I2C3_IRQHandler
I2C4_IRQHandler
SC0_IRQHandler
SC1_IRQHandler
SC2_IRQHandler
SC3_IRQHandler
SC4_IRQHandler
SC5_IRQHandler
CAN0_IRQHandler
CAN1_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SD_IRQHandler
PS2D_IRQHandler
CAP_IRQHandler
CRYPTO_IRQHandler
CRC_IRQHandler
Default_Handler
B Default_Handler
END
;/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

67
demo/nuvoton/usb_device/nuc442/Device/Nuvoton/NUC472_442/Source/system_NUC472_442.c Normal file
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/**************************************************************************//**
* @file system_NUC472_442.c
* @version V1.00
* $Revision: 17 $
* $Date: 15/04/20 8:54a $
* @brief NUC472/NUC442 system clock init code and assert handler
*
* @note
* SPDX-License-Identifier: Apache-2.0
* Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NUC472_442.h"
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock)*/
uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */
uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0, __LIRC, 0, 0, 0, __HIRC}; /*!< System clock source table */
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
uint32_t u32Freq, u32ClkSrc;
uint32_t u32HclkDiv;
u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
if(u32ClkSrc != CLK_CLKSEL0_HCLKSEL_PLL) {
/* Use the clock sources directly */
u32Freq = gau32ClkSrcTbl[u32ClkSrc];
} else {
/* Use PLL clock */
u32Freq = CLK_GetPLLClockFreq();
}
u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
/* Update System Core Clock */
SystemCoreClock = u32Freq/u32HclkDiv;
CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
}
/**
* Initialize the system
*
* @return none
*
* @brief Setup the micro controller system.
*/
void SystemInit (void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
}
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/

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demo/nuvoton/usb_device/nuc442/MDK-ARM/Nu_Link_Driver.ini Normal file
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309
demo/nuvoton/usb_device/nuc442/MDK-ARM/template.uvopt Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>84000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>1</RunSim>
<RunTarget>0</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>6</CpuCode>
<DebugOpt>
<uSim>1</uSim>
<uTrg>0</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>0</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>7</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>NULink\Nu_Link.dll</pMon>
</DebugOpt>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>CMSIS</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Device\Nuvoton\NUC472_442\Source\system_NUC472_442.c</PathWithFileName>
<FilenameWithoutPath>system_NUC472_442.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Device\Nuvoton\NUC472_442\Source\ARM\startup_NUC472_442.s</PathWithFileName>
<FilenameWithoutPath>startup_NUC472_442.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>Library</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
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<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\StdDriver\src\clk.c</PathWithFileName>
<FilenameWithoutPath>clk.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\StdDriver\src\usbd.c</PathWithFileName>
<FilenameWithoutPath>usbd.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>5</FileNumber>
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<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\StdDriver\src\uart.c</PathWithFileName>
<FilenameWithoutPath>uart.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\StdDriver\src\sys.c</PathWithFileName>
<FilenameWithoutPath>sys.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\StdDriver\src\retarget.c</PathWithFileName>
<FilenameWithoutPath>retarget.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>User</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\descriptors.c</PathWithFileName>
<FilenameWithoutPath>descriptors.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\User\vcom_serial.c</PathWithFileName>
<FilenameWithoutPath>vcom_serial.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
</ProjectOpt>

336
demo/nuvoton/usb_device/nuc442/MDK-ARM/template.uvoptx Normal file
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@@ -0,0 +1,336 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>84000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
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<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
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<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
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<AsmCond>1</AsmCond>
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<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
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</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>6</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
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<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
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<tRfunc>0</tRfunc>
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<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>7</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>NULink\Nu_Link.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0NUC400_AP_256 -FS00 -FL040000 -FP0($$Device:NUC442JG8AE$Flash\NUC400_AP_256.FLM))</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
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<vrSel>0</vrSel>
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<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
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<pMisraName></pMisraName>
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<pSingCmds></pSingCmds>
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<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
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<GroupName>CMSIS</GroupName>
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<File>
<GroupNumber>1</GroupNumber>
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<PathWithFileName>..\Device\Nuvoton\NUC472_442\Source\system_NUC472_442.c</PathWithFileName>
<FilenameWithoutPath>system_NUC472_442.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
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<PathWithFileName>..\Device\Nuvoton\NUC472_442\Source\ARM\startup_NUC472_442.s</PathWithFileName>
<FilenameWithoutPath>startup_NUC472_442.s</FilenameWithoutPath>
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</File>
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<GroupName>Library</GroupName>
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<File>
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<FileNumber>3</FileNumber>
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<PathWithFileName>..\StdDriver\src\clk.c</PathWithFileName>
<FilenameWithoutPath>clk.c</FilenameWithoutPath>
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<File>
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<FileNumber>4</FileNumber>
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<PathWithFileName>..\StdDriver\src\uart.c</PathWithFileName>
<FilenameWithoutPath>uart.c</FilenameWithoutPath>
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<File>
<GroupNumber>2</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
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<PathWithFileName>..\StdDriver\src\sys.c</PathWithFileName>
<FilenameWithoutPath>sys.c</FilenameWithoutPath>
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</File>
<File>
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<FileNumber>6</FileNumber>
<FileType>1</FileType>
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<PathWithFileName>..\StdDriver\src\retarget.c</PathWithFileName>
<FilenameWithoutPath>retarget.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
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</File>
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<Group>
<GroupName>User</GroupName>
<tvExp>1</tvExp>
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<FileNumber>7</FileNumber>
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<PathWithFileName>..\User\main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
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<File>
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<PathWithFileName>..\..\..\..\cdc_acm_template.c</PathWithFileName>
<FilenameWithoutPath>cdc_acm_template.c</FilenameWithoutPath>
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<Group>
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<FilenameWithoutPath>usb_dc_nuvoton.c</FilenameWithoutPath>
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</File>
</Group>
</ProjectOpt>

468
demo/nuvoton/usb_device/nuc442/MDK-ARM/template.uvprojx Normal file
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@@ -0,0 +1,468 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>NUC442JG8AE</Device>
<Vendor>Nuvoton</Vendor>
<PackID>Nuvoton.NuMicro_DFP.1.3.14</PackID>
<PackURL>https://github.com/OpenNuvoton/cmsis-packs/raw/master/</PackURL>
<Cpu>IRAM(0x20000000-0x2000FFFF) IROM(0-0x3FFFF) CLOCK(84000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile>undefined</StartupFile>
<FlashDriverDll></FlashDriverDll>
<DeviceId>8381</DeviceId>
<RegisterFile></RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>SFD\Nuvoton\NUC400_v1.SFR</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>template</OutputName>
<CreateExecutable>1</CreateExecutable>
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<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
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<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
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<BeforeCompile>
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</BeforeCompile>
<BeforeMake>
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<SVCSIdString></SVCSIdString>
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<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
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<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments></SimDllArguments>
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
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<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
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<DebugOption>
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<Oh166RecLen>16</Oh166RecLen>
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</DebugOption>
<Utilities>
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<DriverSelection>-1</DriverSelection>
</Flash1>
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<pFcarmOut></pFcarmOut>
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<TargetArmAds>
<ArmAdsMisc>
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<AdsCpuType>"Cortex-M4"</AdsCpuType>
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</Ocm4>
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</Ocm6>
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<StartAddress>0x20000000</StartAddress>
<Size>0x10000</Size>
</IRAM>
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<StartAddress>0x0</StartAddress>
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</IROM>
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<StartAddress>0x0</StartAddress>
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</XRAM>
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</OCR_RVCT1>
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</OCR_RVCT4>
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</OCR_RVCT6>
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<Size>0x10000</Size>
</OCR_RVCT9>
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<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
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441
demo/nuvoton/usb_device/nuc442/StdDriver/inc/clk.h Normal file
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/**************************************************************************//**
* @file CLK.h
* @version V1.0
* $Revision 1 $
* $Date: 15/11/19 10:06a $
* @brief NUC472/NUC442 CLK Header File
*
* @note
* SPDX-License-Identifier: Apache-2.0
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#ifndef __CLK_H__
#define __CLK_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
@{
*/
/** @addtogroup NUC472_442_CLK_Driver CLK Driver
@{
*/
/** @addtogroup NUC472_442_CLK_EXPORTED_CONSTANTS CLK Exported Constants
@{
*/
#define FREQ_500MHZ 500000000
#define FREQ_250MHZ 250000000
#define FREQ_200MHZ 200000000
#define FREQ_125MHZ 125000000
#define FREQ_72MHZ 72000000
#define FREQ_50MHZ 50000000
#define FREQ_25MHZ 25000000
#define FREQ_24MHZ 24000000
#define FREQ_22MHZ 22000000
#define FREQ_32KHZ 32000
#define FREQ_10KHZ 10000
/*---------------------------------------------------------------------------------------------------------*/
/* PLLCTL constant definitions. PLL = FIN * NF / NR / NO */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_PLLCTL_PLLSRC_HIRC (0x1UL<<CLK_PLLCTL_PLLSRC_Pos) /*!< For PLL clock source is internal RC clock. 4MHz < FIN < 24MHz \hideinitializer */
#define CLK_PLLCTL_PLLSRC_HXT (0x0UL<<CLK_PLLCTL_PLLSRC_Pos) /*!< For PLL clock source is external crystal. 4MHz < FIN < 24MHz \hideinitializer */
#define CLK_PLLCTL_NR(x) (((x)-2)<<9) /*!< x must be constant and 2 <= x <= 33. 1.6MHz < FIN/NR < 15MHz \hideinitializer */
#define CLK_PLLCTL_NF(x) ((x)-2) /*!< x must be constant and 2 <= x <= 513. 100MHz < FIN*NF/NR < 200MHz. (120MHz < FIN*NF/NR < 200MHz is preferred.) \hideinitializer */
#define CLK_PLLCTL_NO_1 (0x0UL<<CLK_PLLCTL_OUTDV_Pos) /*!< For output divider is 1 \hideinitializer */
#define CLK_PLLCTL_NO_2 (0x1UL<<CLK_PLLCTL_OUTDV_Pos) /*!< For output divider is 2 \hideinitializer */
#define CLK_PLLCTL_NO_4 (0x3UL<<CLK_PLLCTL_OUTDV_Pos) /*!< For output divider is 4 \hideinitializer */
#if (__HXT == 12000000)
#define CLK_PLLCTL_FOR_I2S (0xA54) /*!< Predefined PLLCTL setting for 147428571.428571Hz PLL output with 12MHz XTAL \hideinitializer */
#define CLK_PLLCTL_84MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 28) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 84MHz PLL output with 12MHz XTAL \hideinitializer */
#define CLK_PLLCTL_50MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 25) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 50MHz PLL output with 12MHz XTAL \hideinitializer */
#define CLK_PLLCTL_48MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(7) | CLK_PLLCTL_NF(112) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 48MHz PLL output with 12MHz XTAL \hideinitializer */
#define CLK_PLLCTL_36MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(7) | CLK_PLLCTL_NF( 84) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 36MHz PLL output with 12MHz XTAL \hideinitializer */
#define CLK_PLLCTL_32MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(6) | CLK_PLLCTL_NF( 64) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 32MHz PLL output with 12MHz XTAL \hideinitializer */
#define CLK_PLLCTL_24MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 16) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 24MHz PLL output with 12MHz XTAL \hideinitializer */
#else
# error "The PLL pre-definitions are only valid when external crystal is 12MHz"
#endif
#define CLK_PLLCTL_50MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13) | CLK_PLLCTL_NF( 59) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 50.1918MHz PLL output with 22.1184MHz IRC \hideinitializer */
#define CLK_PLLCTL_48MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13) | CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 48.064985MHz PLL output with 22.1184MHz IRC \hideinitializer */
#define CLK_PLLCTL_36MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(12) | CLK_PLLCTL_NF( 78) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 35.9424MHz PLL output with 22.1184MHz IRC \hideinitializer */
#define CLK_PLLCTL_32MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR( 9) | CLK_PLLCTL_NF( 52) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 31.9488MHz PLL output with 22.1184MHz IRC \hideinitializer */
#define CLK_PLLCTL_24MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR( 3) | CLK_PLLCTL_NF( 13) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 23.9616MHz PLL output with 22.1184MHz IRC \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* PLL2CTL constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_PLL2CTL_PLL2DIV(x) (((x)-1) << CLK_PLL2CTL_PLL2DIV_Pos) /*!< USBPLL clock frequency = (480 MHz) / 2 / (USB_N + 1). It could be 1~256, Max. PLL frequency :480MHz / 2 when XTL12M. \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL0 constant definitions. (Write-protection) */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL0_HCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL0_HCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as external XTAL 32.768KHz \hideinitializer */
#define CLK_CLKSEL0_HCLKSEL_PLL (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as PLL output \hideinitializer */
#define CLK_CLKSEL0_HCLKSEL_LIRC (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as internal 10KHz RC clock \hideinitializer */
#define CLK_CLKSEL0_HCLKSEL_PLL2 (0x04UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as USBPLL clock \hideinitializer */
#define CLK_CLKSEL0_HCLKSEL_HIRC (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL0_STCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL0_STCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as external XTAL 32.768KHz \hideinitializer */
#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as external XTAL/2 \hideinitializer */
#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as HCLK/2 \hideinitializer */
#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock/2 \hideinitializer */
#define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos) /*!< Setting SysTick clock source as HCLK */
#define CLK_CLKSEL0_PCLKSEL_HCLK (0x00UL<<CLK_CLKSEL0_PCLKSEL_Pos) /*!< Setting clock source as HCLK \hideinitializer */
#define CLK_CLKSEL0_PCLKSEL_HCLK_DIV2 (0x01UL<<CLK_CLKSEL0_PCLKSEL_Pos) /*!< Setting clock source as HCLK/2 \hideinitializer */
#define CLK_CLKSEL0_USBHSEL_PLL (0x01UL<<CLK_CLKSEL0_USBHSEL_Pos) /*!< Setting clock source as PLL \hideinitializer */
#define CLK_CLKSEL0_USBHSEL_PLL2 (0x00UL<<CLK_CLKSEL0_USBHSEL_Pos) /*!< Setting clock source as PLL2 \hideinitializer */
#define CLK_CLKSEL0_CAPSEL_HXT (0x00UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL0_CAPSEL_PLL (0x01UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as PLL \hideinitializer */
#define CLK_CLKSEL0_CAPSEL_HCLK (0x02UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as HCLK \hideinitializer */
#define CLK_CLKSEL0_CAPSEL_HIRC (0x03UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL0_ICAPSEL_HXT (0x00UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL0_ICAPSEL_PLL (0x01UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as PLL \hideinitializer */
#define CLK_CLKSEL0_ICAPSEL_HCLK (0x02UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as HCLK \hideinitializer */
#define CLK_CLKSEL0_ICAPSEL_HIRC (0x03UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL0_SDHSEL_HXT (0x00UL<<CLK_CLKSEL0_SDHSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL0_SDHSEL_PLL (0x01UL<<CLK_CLKSEL0_SDHSEL_Pos) /*!< Setting clock source as PLL2 \hideinitializer */
#define CLK_CLKSEL0_SDHSEL_HCLK (0x02UL<<CLK_CLKSEL0_SDHSEL_Pos) /*!< Setting clock source as HCLK \hideinitializer */
#define CLK_CLKSEL0_SDHSEL_HIRC (0x03UL<<CLK_CLKSEL0_SDHSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL1 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL1_WDTSEL_HXT (0x0UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as external XTAL 32.768KHz \hideinitializer */
#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as HCLK/2048 \hideinitializer */
#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as internal 10KHz RC clock \hideinitializer */
#define CLK_CLKSEL1_ADCSEL_HXT (0x0UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting ADC clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL1_ADCSEL_PLL (0x1UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting ADC clock source as PLL \hideinitializer */
#define CLK_CLKSEL1_ADCSEL_PCLK (0x2UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting ADC clock source as PCLK \hideinitializer */
#define CLK_CLKSEL1_ADCSEL_HIRC (0x3UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting ADC clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL1_EADCSEL_HXT (0x0UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting EADC clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL1_EADCSEL_PLL (0x1UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting EADC clock source as PLL \hideinitializer */
#define CLK_CLKSEL1_EADCSEL_PCLK (0x2UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting EADC clock source as PCLK \hideinitializer */
#define CLK_CLKSEL1_EADCSEL_HIRC (0x3UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting EADC clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL1_SPI0SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PLL \hideinitializer */
#define CLK_CLKSEL1_SPI0SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL1_SPI1SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI1SEL_Pos) /*!< Setting SPI1 clock source as PLL \hideinitializer */
#define CLK_CLKSEL1_SPI1SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI1SEL_Pos) /*!< Setting SPI1 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL1_SPI2SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI2SEL_Pos) /*!< Setting SPI2 clock source as PLL \hideinitializer */
#define CLK_CLKSEL1_SPI2SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI2SEL_Pos) /*!< Setting SPI2 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL1_SPI3SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI3SEL_Pos) /*!< Setting SPI3 clock source as PLL \hideinitializer */
#define CLK_CLKSEL1_SPI3SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI3SEL_Pos) /*!< Setting SPI3 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external XTAL 32.768KHz \hideinitializer */
#define CLK_CLKSEL1_TMR0SEL_PCLK (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external trigger \hideinitializer */
#define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as internal 10KHz RC clock \hideinitializer */
#define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external XTAL 32.768KHz \hideinitializer */
#define CLK_CLKSEL1_TMR1SEL_PCLK (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external trigger \hideinitializer */
#define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as internal 10KHz RC clock \hideinitializer */
#define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external XTAL 32.768KHz \hideinitializer */
#define CLK_CLKSEL1_TMR2SEL_PCLK (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL1_TMR2SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external trigger \hideinitializer */
#define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as internal 10KHz RC clock \hideinitializer */
#define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external XTAL 32.768KHz \hideinitializer */
#define CLK_CLKSEL1_TMR3SEL_PCLK (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL1_TMR3SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external trigger \hideinitializer */
#define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as internal 10KHz RC clock \hideinitializer */
#define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL1_UARTSEL_HXT (0x0UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UR clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL1_UARTSEL_PLL (0x1UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UR clock source as external PLL \hideinitializer */
#define CLK_CLKSEL1_UARTSEL_HIRC (0x3UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UR clock source as external internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external XTAL 32.768KHz \hideinitializer */
#define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HCLK \hideinitializer */
#define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting CLKO clock source as HCLK/2048 \hideinitializer */
#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting CLKO clock source as internal 10KHz RC clock \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL2 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL2_PWM0CH01SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL2_PWM0CH01SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as external XTAL 32.768KHz \hideinitializer */
#define CLK_CLKSEL2_PWM0CH01SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL2_PWM0CH01SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL2_PWM0CH01SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as internal 10KHz RC clock \hideinitializer */
#define CLK_CLKSEL2_PWM0CH23SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL2_PWM0CH23SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as external XTAL 32.768KHz \hideinitializer */
#define CLK_CLKSEL2_PWM0CH23SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL2_PWM0CH23SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL2_PWM0CH23SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as internal 10KHz RC clock \hideinitializer */
#define CLK_CLKSEL2_PWM0CH45SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL2_PWM0CH45SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as external XTAL 32.768KHz \hideinitializer */
#define CLK_CLKSEL2_PWM0CH45SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL2_PWM0CH45SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL2_PWM0CH45SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as internal 10KHz RC clock \hideinitializer */
#define CLK_CLKSEL2_PWM1CH01SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL2_PWM1CH01SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as external XTAL 32.768KHz \hideinitializer */
#define CLK_CLKSEL2_PWM1CH01SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL2_PWM1CH01SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL2_PWM1CH01SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as internal 10KHz RC clock \hideinitializer */
#define CLK_CLKSEL2_PWM1CH23SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL2_PWM1CH23SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as external XTAL 32.768KHz \hideinitializer */
#define CLK_CLKSEL2_PWM1CH23SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL2_PWM1CH23SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL2_PWM1CH23SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as internal 10KHz RC clock \hideinitializer */
#define CLK_CLKSEL2_PWM1CH45SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL2_PWM1CH45SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as external XTAL 32.768KHz \hideinitializer */
#define CLK_CLKSEL2_PWM1CH45SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL2_PWM1CH45SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL2_PWM1CH45SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as internal 10KHz RC clock \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL3 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL3_SC0SEL_HXT (0x0UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL3_SC0SEL_PLL (0x1UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PLL \hideinitializer */
#define CLK_CLKSEL3_SC0SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL3_SC1SEL_HXT (0x0UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL3_SC1SEL_PLL (0x1UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as PLL \hideinitializer */
#define CLK_CLKSEL3_SC1SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL3_SC2SEL_HXT (0x0UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL3_SC2SEL_PLL (0x1UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as PLL \hideinitializer */
#define CLK_CLKSEL3_SC2SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL3_SC3SEL_HXT (0x0UL<<CLK_CLKSEL3_SC3SEL_Pos) /*!< Setting SC3 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL3_SC3SEL_PLL (0x1UL<<CLK_CLKSEL3_SC3SEL_Pos) /*!< Setting SC3 clock source as PLL \hideinitializer */
#define CLK_CLKSEL3_SC3SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC3SEL_Pos) /*!< Setting SC3 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL3_SC3SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC3SEL_Pos) /*!< Setting SC3 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL3_SC4SEL_HXT (0x0UL<<CLK_CLKSEL3_SC4SEL_Pos) /*!< Setting SC4 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL3_SC4SEL_PLL (0x1UL<<CLK_CLKSEL3_SC4SEL_Pos) /*!< Setting SC4 clock source as PLL \hideinitializer */
#define CLK_CLKSEL3_SC4SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC4SEL_Pos) /*!< Setting SC4 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL3_SC4SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC4SEL_Pos) /*!< Setting SC4 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL3_SC5SEL_HXT (0x0UL<<CLK_CLKSEL3_SC5SEL_Pos) /*!< Setting SC5 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL3_SC5SEL_PLL (0x1UL<<CLK_CLKSEL3_SC5SEL_Pos) /*!< Setting SC5 clock source as PLL \hideinitializer */
#define CLK_CLKSEL3_SC5SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC5SEL_Pos) /*!< Setting SC5 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL3_SC5SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC5SEL_Pos) /*!< Setting SC5 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL3_I2S0SEL_PLL (0x1UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as PLL \hideinitializer */
#define CLK_CLKSEL3_I2S0SEL_PCLK (0x2UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as internal 22.1184MHz RC clock \hideinitializer */
#define CLK_CLKSEL3_I2S1SEL_HXT (0x0UL<<CLK_CLKSEL3_I2S1SEL_Pos) /*!< Setting I2S1 clock source as external XTAL \hideinitializer */
#define CLK_CLKSEL3_I2S1SEL_PLL (0x1UL<<CLK_CLKSEL3_I2S1SEL_Pos) /*!< Setting I2S1 clock source as PLL \hideinitializer */
#define CLK_CLKSEL3_I2S1SEL_PCLK (0x2UL<<CLK_CLKSEL3_I2S1SEL_Pos) /*!< Setting I2S1 clock source as PCLK \hideinitializer */
#define CLK_CLKSEL3_I2S1SEL_HIRC (0x3UL<<CLK_CLKSEL3_I2S1SEL_Pos) /*!< Setting I2S1 clock source as internal 22.1184MHz RC clock \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKDIV0 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKDIV0_HCLK(x) (((x)-1) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV Setting for HCLK clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV0_USB(x) (((x)-1) << CLK_CLKDIV0_USBHDIV_Pos) /*!< CLKDIV Setting for USB clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV0_UART(x) (((x)-1) << CLK_CLKDIV0_UARTDIV_Pos) /*!< CLKDIV Setting for UR clock divider. It could be 1~16 \hideinitializer */
#define CLK_CLKDIV0_ADC(x) (((x)-1) << CLK_CLKDIV0_ADCDIV_Pos) /*!< CLKDIV Setting for ADC clock divider. It could be 1~256 \hideinitializer */
#define CLK_CLKDIV0_SDH(x) (((x)-1) << CLK_CLKDIV0_SDHDIV_Pos) /*!< CLKDIV Setting for SDIO clock divider. It could be 1~256 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKDIV1 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKDIV1_SC0(x) (((x)-1) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV Setting for SC0 clock divider. It could be 1~256 \hideinitializer */
#define CLK_CLKDIV1_SC1(x) (((x)-1) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV Setting for SC1 clock divider. It could be 1~256 \hideinitializer */
#define CLK_CLKDIV1_SC2(x) (((x)-1) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV Setting for SC2 clock divider. It could be 1~256 \hideinitializer */
#define CLK_CLKDIV1_SC3(x) (((x)-1) << CLK_CLKDIV1_SC3DIV_Pos) /*!< CLKDIV Setting for SC3 clock divider. It could be 1~256 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKDIV2 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKDIV2_SC4(x) (((x)-1) << CLK_CLKDIV2_SC4DIV_Pos) /*!< CLKDIV Setting for SC4 clock divider. It could be 1~256 \hideinitializer */
#define CLK_CLKDIV2_SC5(x) (((x)-1) << CLK_CLKDIV2_SC5DIV_Pos) /*!< CLKDIV Setting for SC5 clock divider. It could be 1~256 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKDIV3 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKDIV3_CAP(x) (((x)-1) << CLK_CLKDIV3_CAPDIV_Pos) /*!< CLKDIV Setting for CAP Engine clock divider. It could be 1~256 \hideinitializer */
#define CLK_CLKDIV3_VSENSE(x) (((x)-1) << CLK_CLKDIV3_VSENSEDIV_Pos) /*!< CLKDIV Setting for Video Pixel clock divider. It could be 1~256 \hideinitializer */
#define CLK_CLKDIV3_EMAC(x) (((x)-1) << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLKDIV Setting for EMAC_MDCLK clock divider. It could be 1~256 \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* MODULE constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define MODULE_APBCLK(x) ((x >>30) & 0x3) /*!< Calculate AHBCLK/APBCLK offset on MODULE index \hideinitializer */
#define MODULE_CLKSEL(x) ((x >>28) & 0x3) /*!< Calculate CLKSEL offset on MODULE index \hideinitializer */
#define MODULE_CLKSEL_Msk(x) ((x >>25) & 0x7) /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */
#define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */
#define MODULE_CLKDIV(x) ((x >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index \hideinitializer */
#define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */
#define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */
#define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index \hideinitializer */
#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index \hideinitializer */
#define NA MODULE_NoMsk /*!< Not Available \hideinitializer */
#define MODULE_APBCLK_ENC(x) (((x) & 0x03) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07) << 25) /*!< CLKSEL mask offset on MODULE index */
#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) /*!< CLKSEL position offset on MODULE index */
#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1 */
#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) /*!< CLKDIV mask offset on MODULE index */
#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) /*!< CLKDIV position offset on MODULE index */
#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) /*!< AHBCLK/APBCLK offset on MODULE index */
/*--------------------------------------------------------------------------------------------------------------------------------------*/
/* AHBCLK/APBCLK(2) | CLKSEL(2) | CLKSEL_Msk(3) | CLKSEL_Pos(5) | CLKDIV(2) | CLKDIV_Msk(8) | CLKDIV_Pos(5) | IP_EN_Pos(5)*/
/*--------------------------------------------------------------------------------------------------------------------------------------*/
#define PDMA_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_PDMACKEN_Pos) /*!< PDMA Module \hideinitializer */
#define ISP_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISPCKEN_Pos) /*!< ISP Module \hideinitializer */
#define EBI_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBICKEN_Pos) /*!< EBI Module \hideinitializer */
#define USBH_MODULE ((0UL<<30)|(0<<28)|(1<<25) |( 8<<20)|(0<<18)|(0xF<<10) |( 4<<5)|CLK_AHBCLK_USBHCKEN_Pos) /*!< USBH Module \hideinitializer */
#define EMAC_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|(10<<20)|(3<<18)|(0xFF<<10) |(16<<5)|CLK_AHBCLK_EMACCKEN_Pos) /*!< EMAC Module \hideinitializer */
#define SDH_MODULE ((0UL<<30)|(0<<28)|(3<<25) |(20<<20)|(0<<18)|(0xFF<<10) |(24<<5)|CLK_AHBCLK_SDHCKEN_Pos) /*!< SDH Module \hideinitializer */
#define CRC_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_CRCCKEN_Pos) /*!< CRC Module \hideinitializer */
#define CAP_MODULE ((0UL<<30)|(0<<28)|(3<<25) |(16<<20)|(3<<18)|(0xFF<<10) |( 0<<5)|CLK_AHBCLK_CAPCKEN_Pos) /*!< CAP Module \hideinitializer */
#define SEN_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(3<<18)|(0xFF<<10) |( 8<<5)|CLK_AHBCLK_SENCKEN_Pos) /*!< Sensor Clock Module \hideinitializer */
#define USBD_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_USBDCKEN_Pos) /*!< USBD Module \hideinitializer */
#define CRPT_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_CRPTCKEN_Pos) /*!< CRYPTO Module \hideinitializer */
#define WDT_MODULE ((1UL<<30)|(1<<28)|(3<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_WDTCKEN_Pos) /*!< Watchdog Timer Module \hideinitializer */
#define WWDT_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(30<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_WDTCKEN_Pos) /*!< Window Watchdog Timer Module \hideinitializer */
#define RTC_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_RTCCKEN_Pos) /*!< RTC Module \hideinitializer */
#define TMR0_MODULE ((1UL<<30)|(1<<28)|(7<<25) |( 8<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR0CKEN_Pos) /*!< Timer0 Module \hideinitializer */
#define TMR1_MODULE ((1UL<<30)|(1<<28)|(7<<25) |(12<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR1CKEN_Pos) /*!< Timer1 Module \hideinitializer */
#define TMR2_MODULE ((1UL<<30)|(1<<28)|(7<<25) |(16<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR2CKEN_Pos) /*!< Timer2 Module \hideinitializer */
#define TMR3_MODULE ((1UL<<30)|(1<<28)|(7<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR3CKEN_Pos) /*!< Timer3 Module \hideinitializer */
#define CLKO_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(28<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLKO Module \hideinitializer */
#define ACMP_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_ACMPCKEN_Pos) /*!< ACMP Module \hideinitializer */
#define I2C0_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C0CKEN_Pos) /*!< I2C0 Module \hideinitializer */
#define I2C1_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C1CKEN_Pos) /*!< I2C1 Module \hideinitializer */
#define I2C2_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C2CKEN_Pos) /*!< I2C2 Module \hideinitializer */
#define I2C3_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C3CKEN_Pos) /*!< I2C3 Module \hideinitializer */
#define SPI0_MODULE ((1UL<<30)|(1<<28)|(1<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI0CKEN_Pos) /*!< SPI0 Module \hideinitializer */
#define SPI1_MODULE ((1UL<<30)|(1<<28)|(1<<25) |( 5<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI1CKEN_Pos) /*!< SPI1 Module \hideinitializer */
#define SPI2_MODULE ((1UL<<30)|(1<<28)|(1<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI2CKEN_Pos) /*!< SPI2 Module \hideinitializer */
#define SPI3_MODULE ((1UL<<30)|(1<<28)|(1<<25) |( 7<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI3CKEN_Pos) /*!< SPI3 Module \hideinitializer */
#define UART0_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART0CKEN_Pos) /*!< UART0 Module \hideinitializer */
#define UART1_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART1CKEN_Pos) /*!< UART1 Module \hideinitializer */
#define UART2_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART2CKEN_Pos) /*!< UART2 Module \hideinitializer */
#define UART3_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART3CKEN_Pos) /*!< UART3 Module \hideinitializer */
#define UART4_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART4CKEN_Pos) /*!< UART4 Module \hideinitializer */
#define UART5_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART5CKEN_Pos) /*!< UART5 Module \hideinitializer */
#define CAN0_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_CAN0CKEN_Pos) /*!< CAN0 Module \hideinitializer */
#define CAN1_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_CAN1CKEN_Pos) /*!< CAN1 Module \hideinitializer */
#define OTG_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_OTGCKEN_Pos) /*!< OTG Module \hideinitializer */
#define ADC_MODULE ((1UL<<30)|(1<<28)|(3<<25) |( 2<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK0_ADCCKEN_Pos) /*!< ADC Module \hideinitializer */
#define I2S0_MODULE ((1UL<<30)|(3<<28)|(3<<25) |(16<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2S0CKEN_Pos) /*!< I2S0 Module \hideinitializer */
#define I2S1_MODULE ((1UL<<30)|(3<<28)|(3<<25) |(18<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2S1CKEN_Pos) /*!< I2S1 Module \hideinitializer */
#define PS2_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_PS2CKEN_Pos) /*!< PS2 Module \hideinitializer */
#define SC0_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 0<<20)|(1<<18)|(0xFF<<10) |( 0<<5)|CLK_APBCLK1_SC0CKEN_Pos) /*!< SmartCard0 Module \hideinitializer */
#define SC1_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 2<<20)|(1<<18)|(0xFF<<10) |( 8<<5)|CLK_APBCLK1_SC1CKEN_Pos) /*!< SmartCard1 Module \hideinitializer */
#define SC2_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 4<<20)|(1<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK1_SC2CKEN_Pos) /*!< SmartCard2 Module \hideinitializer */
#define SC3_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 6<<20)|(1<<18)|(0xFF<<10) |(24<<5)|CLK_APBCLK1_SC3CKEN_Pos) /*!< SmartCard3 Module \hideinitializer */
#define SC4_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 8<<20)|(2<<18)|(0xFF<<10) |( 0<<5)|CLK_APBCLK1_SC4CKEN_Pos) /*!< SmartCard4 Module \hideinitializer */
#define SC5_MODULE ((2UL<<30)|(3<<28)|(3<<25) |(10<<20)|(2<<18)|(0xFF<<10) |( 8<<5)|CLK_APBCLK1_SC5CKEN_Pos) /*!< SmartCard5 Module \hideinitializer */
#define I2C4_MODULE ((2UL<<30)|(0<<28)|(0<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_I2C4CKEN_Pos) /*!< I2C4 Module */
#define PWM0CH01_MODULE ((2UL<<30)|(2<<28)|(7<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM0CH01CKEN_Pos) /*!< PWM0CH01 Module \hideinitializer */
#define PWM0CH23_MODULE ((2UL<<30)|(2<<28)|(7<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM0CH23CKEN_Pos) /*!< PWM0CH23 Module \hideinitializer */
#define PWM0CH45_MODULE ((2UL<<30)|(2<<28)|(7<<25) |( 8<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM0CH45CKEN_Pos) /*!< PWM0CH45 Module \hideinitializer */
#define PWM1CH01_MODULE ((2UL<<30)|(2<<28)|(7<<25) |(12<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM1CH01CKEN_Pos) /*!< PWM1CH01 Module \hideinitializer */
#define PWM1CH23_MODULE ((2UL<<30)|(2<<28)|(7<<25) |(16<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM1CH2345CKEN_Pos) /*!< PWM1CH23 Module \hideinitializer */
#define PWM1CH45_MODULE ((2UL<<30)|(2<<28)|(7<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM1CH2345CKEN_Pos) /*!< PWM1CH45 Module \hideinitializer */
#define QEI0_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_QEI0CKEN_Pos) /*!< QEI0 Module \hideinitializer */
#define QEI1_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_QEI1CKEN_Pos) /*!< QEI1 Module \hideinitializer */
#define ECAP0_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_ECAP0CKEN_Pos) /*!< ECAP0 Module \hideinitializer */
#define ECAP1_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_ECAP1CKEN_Pos) /*!< ECAP1 Module \hideinitializer */
#define EPWM0_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_EPWM0CKEN_Pos) /*!< EPWM0 Module \hideinitializer */
#define EPWM1_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_EPWM1CKEN_Pos) /*!< EPWM1 Module \hideinitializer */
#define OPA_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_OPACKEN_Pos) /*!< OPA Module \hideinitializer */
#define EADC_MODULE ((2UL<<30)|(1<<28)|(3<<25) |( 2<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK1_EADCCKEN_Pos) /*!< EADC Module \hideinitializer */
#define CLK_TIMEOUT_ERR (-1) /*!< Clock timeout error value \hideinitializer */
/*@}*/ /* end of group NUC472_442_CLK_EXPORTED_CONSTANTS */
extern int32_t g_CLK_i32ErrCode;
/** @addtogroup NUC472_442_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
@{
*/
void CLK_DisableCKO(void);
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
void CLK_PowerDown(void);
void CLK_Idle(void);
uint32_t CLK_GetHXTFreq(void);
uint32_t CLK_GetLXTFreq(void);
uint32_t CLK_GetHCLKFreq(void);
uint32_t CLK_GetPCLKFreq(void);
uint32_t CLK_GetCPUFreq(void);
uint32_t CLK_GetPLLClockFreq(void);
uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
void CLK_EnableXtalRC(uint32_t u32ClkMask);
void CLK_DisableXtalRC(uint32_t u32ClkMask);
void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
void CLK_DisablePLL(void);
int32_t CLK_SysTickDelay(uint32_t us);
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
void CLK_DisableSysTick(void);
/*@}*/ /* end of group NUC472_442_CLK_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group NUC472_442_CLK_Driver */
/*@}*/ /* end of group NUC472_442_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__CLK_H__
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file uart.h
* @version V1.00
* $Revision: 20 $
* $Date: 15/11/30 1:35p $
* @brief NUC472/NUC442 UART driver header file
*
* @note
* SPDX-License-Identifier: Apache-2.0
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __UART_H__
#define __UART_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
@{
*/
/** @addtogroup NUC472_442_UART_Driver UART Driver
@{
*/
/** @addtogroup NUC472_442_UART_EXPORTED_CONSTANTS UART Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* UART_FCR constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_FIFO_RFITL_1BYTE (0x0 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 byte */
#define UART_FIFO_RFITL_4BYTES (0x1 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bytes */
#define UART_FIFO_RFITL_8BYTES (0x2 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bytes */
#define UART_FIFO_RFITL_14BYTES (0x3 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bytes */
#define UART_FIFO_RTSTRGLV_1BYTE (0x0 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 1 byte */
#define UART_FIFO_RTSTRGLV_4BYTES (0x1 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 4 bytes */
#define UART_FIFO_RTSTRGLV_8BYTES (0x2 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 8 bytes */
#define UART_FIFO_RTSTRGLV_14BYTES (0x3 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 14 bytes */
/*---------------------------------------------------------------------------------------------------------*/
/* UART_LCR constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_WORD_LEN_5 (0) /*!< UART_LINE setting to set UART word length to 5 bits */
#define UART_WORD_LEN_6 (1) /*!< UART_LINE setting to set UART word length to 6 bits */
#define UART_WORD_LEN_7 (2) /*!< UART_LINE setting to set UART word length to 7 bits */
#define UART_WORD_LEN_8 (3) /*!< UART_LINE setting to set UART word length to 8 bits */
#define UART_PARITY_NONE (0x0 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity */
#define UART_PARITY_ODD (0x1 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity */
#define UART_PARITY_EVEN (0x3 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity */
#define UART_PARITY_MARK (0x5 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1' */
#define UART_PARITY_SPACE (0x7 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0' */
#define UART_STOP_BIT_1 (0x0 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit */
#define UART_STOP_BIT_1_5 (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length */
#define UART_STOP_BIT_2 (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length */
/*---------------------------------------------------------------------------------------------------------*/
/* UART RTS LEVEL TRIGGER constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_RTS_IS_HIGH_LEV_TRG (0x1 << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is High Level Trigger */
#define UART_RTS_IS_LOW_LEV_TRG (0x0 << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is Low Level Trigger */
/*---------------------------------------------------------------------------------------------------------*/
/* UART CTS LEVEL TRIGGER constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_CTS_IS_HIGH_LEV_TRG (0x1 << UART_MODEMSTS_CTSACTLV_Pos) /*!< Set CTS is High Level Trigger */
#define UART_CTS_IS_LOW_LEV_TRG (0x0 << UART_MODEMSTS_CTSACTLV_Pos) /*!< Set CTS is Low Level Trigger */
/*---------------------------------------------------------------------------------------------------------*/
/* UART_FUNC_SEL constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_FUNCSEL_UART (0x0 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function (Default) */
#define UART_FUNCSEL_IrDA (0x2 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function */
#define UART_FUNCSEL_RS485 (0x3 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function */
/*---------------------------------------------------------------------------------------------------------*/
/* UART BAUDRATE MODE constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_BAUD_MODE0 (0) /*!< Set UART Baudrate Mode is Mode0 */
#define UART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk) /*!< Set UART Baudrate Mode is Mode2 */
/*@}*/ /* end of group NUC472_442_UART_EXPORTED_CONSTANTS */
/** @addtogroup NUC472_442_UART_EXPORTED_FUNCTIONS UART Exported Functions
@{
*/
/**
* @brief Calculate UART baudrate mode0 divider
*
* @param[in] u32SrcFreq UART clock frequency
* @param[in] u32BaudRate Baudrate of UART module
*
* @return UART baudrate mode0 divider
* \hideinitializer
*
*/
#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-2)
/**
* @brief Calculate UART baudrate mode2 divider
*
* @param[in] u32SrcFreq UART clock frequency
* @param[in] u32BaudRate Baudrate of UART module
*
* @return UART baudrate mode2 divider
* \hideinitializer
*/
#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-2)
/**
* @brief Write Data to Tx data register
*
* @param[in] uart The base address of UART module.
* @param[in] u8Data Data byte to transmit
*
* @return None
* \hideinitializer
*/
#define UART_WRITE(uart, u8Data) (uart->DAT = (u8Data))
/**
* @brief Read Rx data register
*
* @param[in] uart The base address of UART module.
*
* @return The oldest data byte in RX FIFO
* \hideinitializer
*/
#define UART_READ(uart) (uart->DAT)
/**
* @brief Get Tx empty register value.
*
* @param[in] uart The base address of UART module
*
* @return Tx empty register value.
* \hideinitializer
*/
#define UART_GET_TX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk)
/**
* @brief Get Rx empty register value.
*
* @param[in] uart The base address of UART module
*
* @return Rx empty register value.
* \hideinitializer
*/
#define UART_GET_RX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
/**
* @brief Check specified uart port transmission is over.
*
* @param[in] uart The base address of UART module
*
* @return TE_Flag.
* \hideinitializer
*/
#define UART_IS_TX_EMPTY(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
/**
* @brief Wait specified uart port transmission is over
*
* @param[in] uart The base address of UART module
*
* @return None
* \hideinitializer
*/
#define UART_WAIT_TX_EMPTY(uart) while(!(((uart->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
/**
* @brief Check RDA_IF is set or not
*
* @param[in] uart The base address of UART module
*
* @return
* 0 : The number of bytes in the RX FIFO is less than the RFITL
* 1 : The number of bytes in the RX FIFO equals or larger than RFITL
* \hideinitializer
*/
#define UART_IS_RX_READY(uart) ((uart->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
/**
* @brief Check TX FIFO is full or not
*
* @param[in] uart The base address of UART module
*
* @return
* 1 = TX FIFO is full
* 0 = TX FIFO is not full
* \hideinitializer
*/
#define UART_IS_TX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
/**
* @brief Check RX FIFO is full or not
*
* @param[in] uart The base address of UART module
*
* @return
* 1 = RX FIFO is full
* 0 = RX FIFO is not full
* \hideinitializer
*
*/
#define UART_IS_RX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
/**
* @brief Get Tx full register value
*
* @param[in] uart The base address of UART module
*
* @return Tx full register value
* \hideinitializer
*/
#define UART_GET_TX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
/**
* @brief Get Rx full register value
*
* @param[in] uart The base address of UART module
*
* @return Rx full register value
* \hideinitializer
*/
#define UART_GET_RX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
/**
* @brief Enable specified interrupt
*
* @param[in] uart The base address of UART module
* @param[in] u32eIntSel Interrupt type select
* - \ref UART_INTEN_TOCNTEN_Msk : Rx Time Out interrupt
* - \ref UART_INTEN_WKCTSIEN_Msk : Wakeup interrupt
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
* - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
* - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
*
* @return None
* \hideinitializer
*/
#define UART_ENABLE_INT(uart, u32eIntSel) (uart->INTEN |= (u32eIntSel))
/**
* @brief Disable specified interrupt
*
* @param[in] uart The base address of UART module
* @param[in] u32eIntSel Interrupt type select
* - \ref UART_INTEN_TOCNTEN_Msk : Rx Time Out interrupt
* - \ref UART_INTEN_WKCTSIEN_Msk : Wakeup interrupt
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
* - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
* - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
* @return None
* \hideinitializer
*/
#define UART_DISABLE_INT(uart, u32eIntSel) (uart->INTEN &= ~ (u32eIntSel))
/**
* @brief Get specified interrupt flag/status
*
* @param[in] uart The base address of UART module
* @param[in] u32eIntTypeFlag Interrupt type select
* - \ref UART_INTSTS_HWBUFEINT_Msk : In DMA Mode, Buffer Error Interrupt Indicator.
* - \ref UART_INTSTS_HWTOINT_Msk : In DMA Mode, Time-out Interrupt Indicator.
* - \ref UART_INTSTS_HWMODINT_Msk : In DMA Mode, MODEM Status Interrupt Indicator.
* - \ref UART_INTSTS_HWRLSINT_Msk : In DMA Mode, Receive Line Status Interrupt Indicator.
* - \ref UART_INTSTS_HWBUFEIF_Msk : In DMA Mode, Buffer Error Interrupt Flag.
* - \ref UART_INTSTS_HWTOIF_Msk : In DMA Mode, Time-out Interrupt Flag.
* - \ref UART_INTSTS_HWMODIF_Msk : In DMA Mode, MODEM Interrupt Flag.
* - \ref UART_INTSTS_HWRLSIF_Msk : In DMA Mode, Receive Line Status Flag.
* - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator.
* - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator.
* - \ref UART_INTSTS_RXTOINT_Msk : Time-out Interrupt Indicator.
* - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator.
* - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator.
* - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator.
* - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator.
* - \ref UART_INTSTS_LINIF_Msk : LIN Bus Flag.
* - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag
* - \ref UART_INTSTS_RXTOIF_Msk : Rx time-out interrupt Flag
* - \ref UART_INTSTS_MODEMIF_Msk : Modem interrupt Flag
* - \ref UART_INTSTS_RLSIF_Msk : Rx Line status interrupt Flag
* - \ref UART_INTSTS_THREIF_Msk : Tx empty interrupt Flag
* - \ref UART_INTSTS_RDAIF_Msk : Rx ready interrupt Flag
*
* @return
* 0 = The specified interrupt is not happened.
* 1 = The specified interrupt is happened.
* \hideinitializer
*/
#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->INTSTS & (u32eIntTypeFlag))?1:0)
/**
* @brief Set RTS pin is low
*
* @param[in] uart The base address of UART module
* @return None
*/
__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart)
{
uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
uart->MODEM &= UART_MODEM_RTS_Msk;
}
/**
* @brief Set RTS pin is high
*
* @param[in] uart The base address of UART module
* @return None
*/
__STATIC_INLINE void UART_SET_RTS(UART_T* uart)
{
uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk;
}
/**
* @brief Clear RS-485 Address Byte Detection Flag
*
* @param[in] uart The base address of UART module
* @return None
* \hideinitializer
*/
#define UART_RS485_CLEAR_ADDR_FLAG(uart) (uart->FIFOSTS |= UART_FIFOSTS_ADDRDETF_Msk)
/**
* @brief Get RS-485 Address Byte Detection Flag
*
* @param[in] uart The base address of UART module
* @return RS-485 Address Byte Detection Flag
* \hideinitializer
*/
#define UART_RS485_GET_ADDR_FLAG(uart) ((uart->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)
void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag);
void UART_Close(UART_T* uart );
void UART_DisableFlowCtrl(UART_T* uart );
void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag );
void UART_EnableFlowCtrl(UART_T* uart );
void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag );
void UART_Open(UART_T* uart, uint32_t u32baudrate);
uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);
void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);
void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);
uint32_t UART_Write(UART_T* uart,uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
/*@}*/ /* end of group NUC472_442_UART_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group NUC472_442_UART_Driver */
/*@}*/ /* end of group NUC472_442_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__UART_H__
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file clk.c
* @version V1.00
* $Revision: 35 $
* $Date: 16/03/04 3:42p $
* @brief NUC472/NUC442 CLK driver source file
*
* @note
* SPDX-License-Identifier: Apache-2.0
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NUC472_442.h"
/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
@{
*/
/** @addtogroup NUC472_442_CLK_Driver CLK Driver
@{
*/
int32_t g_CLK_i32ErrCode = 0; /*!< CLK global error code */
/** @addtogroup NUC472_442_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
@{
*/
/**
* @brief Disable frequency output function
* @return None
* @details This function disable frequency output function.
*/
void CLK_DisableCKO(void)
{
/* Disable CKO clock source */
CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk);
}
/**
* @brief This function enable frequency divider module clock,
* enable frequency divider clock function and configure frequency divider.
* @param[in] u32ClkSrc is frequency divider function clock source
* - \ref CLK_CLKSEL1_CLKOSEL_HXT
* - \ref CLK_CLKSEL1_CLKOSEL_LXT
* - \ref CLK_CLKSEL1_CLKOSEL_HCLK
* - \ref CLK_CLKSEL1_CLKOSEL_HIRC
* @param[in] u32ClkDiv is system reset source
* @param[in] u32ClkDivBy1En is frequency divided by one enable.
* @return None
*
* @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv.
* The formula is:
* CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1)
* This function is just used to set CKO clock.
* User must enable I/O for CKO clock output pin by themselves.
*/
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
{
/* CKO = clock source / 2^(u32ClkDiv + 1) */
CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | u32ClkDivBy1En<<CLK_CLKOCTL_DIV1EN_Pos;
/* Enable CKO clock source */
CLK->APBCLK0 |= CLK_APBCLK0_CLKOCKEN_Msk;
/* Select CKO clock source */
CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_CLKOSEL_Msk)) | u32ClkSrc;
}
/**
* @brief Enter to Power-down mode
* @return None
* @details This function let system enter to Power-down mode.
*/
void CLK_PowerDown(void)
{
SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk | CLK_PWRCTL_PDWKDLY_Msk );
__WFI();
}
/**
* @brief Enter to Idle mode.
* @return None
* @details This function let system enter to Idle mode.
*/
void CLK_Idle(void)
{
/* Set the processor uses sleep as its low power mode */
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
/* Set chip in idle mode because of WFI command */
CLK->PWRCTL &= ~(CLK_PWRCTL_PDEN_Msk );
/* Chip enter idle mode after CPU run WFI instruction */
__WFI();
}
/**
* @brief This function get PCLK frequency. The frequency unit is Hz.
* @return PCLK frequency
*/
uint32_t CLK_GetPCLKFreq(void)
{
SystemCoreClockUpdate();
if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLKSEL_Msk)
return SystemCoreClock/2;
else
return SystemCoreClock;
}
/**
* @brief Get external high speed crystal clock frequency
* @return External high frequency crystal frequency
* @details This function get external high frequency crystal frequency. The frequency unit is Hz.
*/
uint32_t CLK_GetHXTFreq(void)
{
if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk )
return __HXT;
else
return 0;
}
/**
* @brief Get external low speed crystal clock frequency
* @return External low speed crystal clock frequency
* @details This function get external low frequency crystal frequency. The frequency unit is Hz.
*/
uint32_t CLK_GetLXTFreq(void)
{
if(CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk )
return __LXT;
else
return 0;
}
/**
* @brief Get HCLK frequency
* @return HCLK frequency
* @details This function get HCLK frequency. The frequency unit is Hz.
*/
uint32_t CLK_GetHCLKFreq(void)
{
SystemCoreClockUpdate();
return SystemCoreClock;
}
/**
* @brief Get CPU frequency
* @return CPU frequency
* @details This function get CPU frequency. The frequency unit is Hz.
*/
uint32_t CLK_GetCPUFreq(void)
{
SystemCoreClockUpdate();
return SystemCoreClock;
}
/**
* @brief This function get PLL frequency. The frequency unit is Hz.
* @return PLL frequency
*/
uint32_t CLK_GetPLLClockFreq(void)
{
uint32_t u32Freq =0, u32PLLSrc;
uint32_t u32NO,u32NF,u32NR,u32PllReg;
u32PllReg = CLK->PLLCTL;
if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk))
return 0; /* PLL is in power down mode or fix low */
if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk)
u32PLLSrc = __HIRC;
else
u32PLLSrc = __HXT;
u32NO=(u32PllReg & CLK_PLLCTL_OUTDV_Msk)>>CLK_PLLCTL_OUTDV_Pos;
switch(u32NO)
{
case 0:
u32NO=1;
break;
case 1:
case 2:
u32NO=2;
break;
case 3:
u32NO=4;
break;
}
u32NF = (u32PllReg & CLK_PLLCTL_FBDIV_Msk) + 2;
u32NR = ( (u32PllReg & CLK_PLLCTL_INDIV_Msk)>>CLK_PLLCTL_INDIV_Pos ) + 2;
/* u32PLLSrc is shifted 2 bits to avoid overflow */
u32Freq = (((u32PLLSrc >> 2) * u32NF) / (u32NR * u32NO) << 2);
return u32Freq;
}
/**
* @brief Set HCLK frequency
* @param[in] u32Hclk is HCLK frequency
* @return HCLK frequency
* @details This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 24 MHz ~ 96 MHz.
*/
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
{
uint32_t u32ClkSrc,u32NR, u32NF,u32Register;
u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
if(u32Hclk < FREQ_24MHZ)
u32Hclk =FREQ_24MHZ;
if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk)
{
u32Register = 0<<CLK_PLLCTL_PLLSRC_Pos;
u32ClkSrc = __HXT;
}
else
{
u32Register = 1<<CLK_PLLCTL_PLLSRC_Pos;
u32ClkSrc = __HIRC;
}
if(u32Hclk<FREQ_50MHZ)
{
u32Hclk <<=2;
u32Register |= (0x3<<CLK_PLLCTL_OUTDV_Pos);
}
else
{
u32Hclk <<=1;
u32Register |= (0x1<<CLK_PLLCTL_OUTDV_Pos);
}
u32NF = u32Hclk / 1000000;
u32NR = u32ClkSrc / 1000000;
while( u32NR>(0xF+2) || u32NF>(0xFF+2) )
{
u32NR = u32NR>>1;
u32NF = u32NF>>1;
}
CLK->PLLCTL = u32Register | ((u32NR - 2)<<9) | (u32NF - 2) ;
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1));
/* Update System Core Clock */
SystemCoreClockUpdate();
return SystemCoreClock;
}
/**
* @brief This function set HCLK clock source and HCLK clock divider
* @param[in] u32ClkSrc is HCLK clock source. Including :
* - \ref CLK_CLKSEL0_HCLKSEL_HXT
* - \ref CLK_CLKSEL0_HCLKSEL_LXT
* - \ref CLK_CLKSEL0_HCLKSEL_PLL
* - \ref CLK_CLKSEL0_HCLKSEL_LIRC
* - \ref CLK_CLKSEL0_HCLKSEL_HIRC
* @param[in] u32ClkDiv is HCLK clock divider. Including :
* - \ref CLK_CLKDIV0_HCLK(x)
* @return None
*/
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
{
CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLKDIV_Msk) | u32ClkDiv;
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLKSEL_Msk) | u32ClkSrc;
SystemCoreClockUpdate();
}
/**
* @brief This function set selected module clock source and module clock divider
* @param[in] u32ModuleIdx is module index.
* @param[in] u32ClkSrc is module clock source.
* @param[in] u32ClkDiv is module clock divider.
* @return None
* @details Valid parameter combinations listed in following table:
*
* |Module index |Clock source |Divider |
* | :------------------- | :------------------------------- | :------------------------- |
* |\ref PDMA_MODULE | x | x |
* |\ref ISP_MODULE | x | x |
* |\ref EBI_MODULE | x | x |
* |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBHSEL_PLL |\ref CLK_CLKDIV0_USB(x) |
* |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBHSEL_PLL2 |\ref CLK_CLKDIV0_USB(x) |
* |\ref EMAC_MODULE | x |\ref CLK_CLKDIV3_EMAC(x) |
* |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_HXT |\ref CLK_CLKDIV0_SDH(x) |
* |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_PLL |\ref CLK_CLKDIV0_SDH(x) |
* |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_HCLK |\ref CLK_CLKDIV0_SDH(x) |
* |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_HIRC |\ref CLK_CLKDIV0_SDH(x) |
* |\ref CRC_MODULE | x | x |
* |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_HXT |\ref CLK_CLKDIV3_CAP(x) |
* |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_PLL |\ref CLK_CLKDIV3_CAP(x) |
* |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_HCLK |\ref CLK_CLKDIV3_CAP(x) |
* |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_HIRC |\ref CLK_CLKDIV3_CAP(x) |
* |\ref SEN_MODULE | x | x |
* |\ref USBD_MODULE | x | x |
* |\ref CRPT_MODULE | x | x |
* |\ref ECAP1_MODULE | x | x |
* |\ref ECAP0_MODULE | x | x |
* |\ref EADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HXT |\ref CLK_CLKDIV0_ADC(x) |
* |\ref EADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PLL |\ref CLK_CLKDIV0_ADC(x) |
* |\ref EADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PCLK |\ref CLK_CLKDIV0_ADC(x) |
* |\ref EADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HIRC |\ref CLK_CLKDIV0_ADC(x) |
* |\ref OPA_MODULE | x | x |
* |\ref QEI1_MODULE | x | x |
* |\ref QEI0_MODULE | x | x |
* |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_HXT | x |
* |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_LXT | x |
* |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_PCLK | x |
* |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_LIRC | x |
* |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_HIRC | x |
* |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_HXT | x |
* |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_LXT | x |
* |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_PCLK | x |
* |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_LIRC | x |
* |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_HIRC | x |
* |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_HXT | x |
* |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_LXT | x |
* |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_PCLK | x |
* |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_LIRC | x |
* |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_HIRC | x |
* |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_HXT | x |
* |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_LXT | x |
* |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_PCLK | x |
* |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_LIRC | x |
* |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_HIRC | x |
* |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_HXT | x |
* |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_LXT | x |
* |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_PCLK | x |
* |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_LIRC | x |
* |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_HIRC | x |
* |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_HXT | x |
* |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_LXT | x |
* |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_PCLK | x |
* |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_LIRC | x |
* |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_HIRC | x |
* |\ref I2C4_MODULE | x | x |
* |\ref SC5_MODULE | x | x |
* |\ref SC4_MODULE | x | x |
* |\ref SC3_MODULE | x | x |
* |\ref SC2_MODULE | x | x |
* |\ref SC5_MODULE |\ref CLK_CLKSEL3_SC5SEL_HXT |\ref CLK_CLKDIV2_SC5(x) |
* |\ref SC5_MODULE |\ref CLK_CLKSEL3_SC5SEL_PLL |\ref CLK_CLKDIV2_SC5(x) |
* |\ref SC5_MODULE |\ref CLK_CLKSEL3_SC5SEL_PCLK |\ref CLK_CLKDIV2_SC5(x) |
* |\ref SC5_MODULE |\ref CLK_CLKSEL3_SC5SEL_HIRC |\ref CLK_CLKDIV2_SC5(x) |
* |\ref SC4_MODULE |\ref CLK_CLKSEL3_SC4SEL_HXT |\ref CLK_CLKDIV2_SC4(x) |
* |\ref SC4_MODULE |\ref CLK_CLKSEL3_SC4SEL_PLL |\ref CLK_CLKDIV2_SC4(x) |
* |\ref SC4_MODULE |\ref CLK_CLKSEL3_SC4SEL_PCLK |\ref CLK_CLKDIV2_SC4(x) |
* |\ref SC4_MODULE |\ref CLK_CLKSEL3_SC4SEL_HIRC |\ref CLK_CLKDIV2_SC4(x) |
* |\ref SC3_MODULE |\ref CLK_CLKSEL3_SC3SEL_HXT |\ref CLK_CLKDIV1_SC3(x) |
* |\ref SC3_MODULE |\ref CLK_CLKSEL3_SC3SEL_PLL |\ref CLK_CLKDIV1_SC3(x) |
* |\ref SC3_MODULE |\ref CLK_CLKSEL3_SC3SEL_PCLK |\ref CLK_CLKDIV1_SC3(x) |
* |\ref SC3_MODULE |\ref CLK_CLKSEL3_SC3SEL_HIRC |\ref CLK_CLKDIV1_SC3(x) |
* |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) |
* |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL |\ref CLK_CLKDIV1_SC2(x) |
* |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK |\ref CLK_CLKDIV1_SC2(x) |
* |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) |
* |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) |
* |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PLL |\ref CLK_CLKDIV1_SC1(x) |
* |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PCLK |\ref CLK_CLKDIV1_SC1(x) |
* |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) |
* |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) |
* |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) |
* |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK |\ref CLK_CLKDIV1_SC0(x) |
* |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) |
* |\ref PS2_MODULE |\ref CLK_CLKSEL3_I2S1SEL_HXT | x |
* |\ref I2S1_MODULE |\ref CLK_CLKSEL3_I2S1SEL_HXT | x |
* |\ref I2S1_MODULE |\ref CLK_CLKSEL3_I2S1SEL_PLL | x |
* |\ref I2S1_MODULE |\ref CLK_CLKSEL3_I2S1SEL_PCLK | x |
* |\ref I2S1_MODULE |\ref CLK_CLKSEL3_I2S1SEL_HIRC | x |
* |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HXT | x |
* |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLL | x |
* |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PCLK | x |
* |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC | x |
* |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HXT |\ref CLK_CLKDIV0_ADC(x) |
* |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PLL |\ref CLK_CLKDIV0_ADC(x) |
* |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PCLK |\ref CLK_CLKDIV0_ADC(x) |
* |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HIRC |\ref CLK_CLKDIV0_ADC(x) |
* |\ref OTG_MODULE | x | x |
* |\ref CAN1_MODULE | x | x |
* |\ref CAN0_MODULE | x | x |
* |\ref UART5_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART5_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART5_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART4_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART4_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART4_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
* |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
* |\ref SPI3_MODULE |\ref CLK_CLKSEL1_SPI3SEL_PLL | x |
* |\ref SPI3_MODULE |\ref CLK_CLKSEL1_SPI3SEL_PCLK | x |
* |\ref SPI2_MODULE |\ref CLK_CLKSEL1_SPI2SEL_PLL | x |
* |\ref SPI2_MODULE |\ref CLK_CLKSEL1_SPI2SEL_PCLK | x |
* |\ref SPI1_MODULE |\ref CLK_CLKSEL1_SPI1SEL_PLL | x |
* |\ref SPI1_MODULE |\ref CLK_CLKSEL1_SPI1SEL_PCLK | x |
* |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPI0SEL_PLL | x |
* |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPI0SEL_PCLK | x |
* |\ref I2C3_MODULE | x | x |
* |\ref I2C2_MODULE | x | x |
* |\ref I2C1_MODULE | x | x |
* |\ref I2C0_MODULE | x | x |
* |\ref ACMP_MODULE | x | x |
* |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x |
* |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x |
* |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x |
* |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x |
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x |
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x |
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK | x |
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x |
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT | x |
* |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x |
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x |
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x |
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK | x |
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x |
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT | x |
* |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x |
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x |
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x |
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK | x |
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x |
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT | x |
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x |
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x |
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x |
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK | x |
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x |
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT | x |
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x |
* |\ref RTC_MODULE | x | x |
* |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x |
* |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x |
* |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x |
* |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x |
* |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x |
*
*/
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
{
uint32_t u32tmp=0,u32sel=0,u32div=0;
if(MODULE_CLKDIV_Msk(u32ModuleIdx)!=MODULE_NoMsk)
{
u32div =(uint32_t)&CLK->CLKDIV0+((MODULE_CLKDIV(u32ModuleIdx))*4);
u32tmp = *(volatile uint32_t *)(u32div);
u32tmp = ( u32tmp & ~(MODULE_CLKDIV_Msk(u32ModuleIdx)<<MODULE_CLKDIV_Pos(u32ModuleIdx)) ) | u32ClkDiv;
*(volatile uint32_t *)(u32div) = u32tmp;
}
if(MODULE_CLKSEL_Msk(u32ModuleIdx)!=MODULE_NoMsk)
{
u32sel = (uint32_t)&CLK->CLKSEL0+((MODULE_CLKSEL(u32ModuleIdx))*4);
u32tmp = *(volatile uint32_t *)(u32sel);
u32tmp = ( u32tmp & ~(MODULE_CLKSEL_Msk(u32ModuleIdx)<<MODULE_CLKSEL_Pos(u32ModuleIdx)) ) | u32ClkSrc;
*(volatile uint32_t *)(u32sel) = u32tmp;
}
}
/**
* @brief This function enable clock source
* @param u32ClkMask is clock source mask. Including:
* - \ref CLK_PWRCTL_HXTEN_Msk
* - \ref CLK_PWRCTL_LXTEN_Msk
* - \ref CLK_PWRCTL_HIRCEN_Msk
* - \ref CLK_PWRCTL_LIRCEN_Msk
* @return None
*/
void CLK_EnableXtalRC(uint32_t u32ClkMask)
{
CLK->PWRCTL |= u32ClkMask;
}
/**
* @brief This function disable clock source
* @param u32ClkMask is clock source mask. Including:
* - \ref CLK_PWRCTL_HXTEN_Msk
* - \ref CLK_PWRCTL_LXTEN_Msk
* - \ref CLK_PWRCTL_HIRCEN_Msk
* - \ref CLK_PWRCTL_LIRCEN_Msk
* @return None
*/
void CLK_DisableXtalRC(uint32_t u32ClkMask)
{
CLK->PWRCTL &= ~u32ClkMask;
}
/**
* @brief This function enable module clock
* @param[in] u32ModuleIdx is module index. Including :
* - \ref PDMA_MODULE
* - \ref ISP_MODULE
* - \ref EBI_MODULE
* - \ref USBH_MODULE
* - \ref EMAC_MODULE
* - \ref SDH_MODULE
* - \ref CRC_MODULE
* - \ref CAP_MODULE
* - \ref USBD_MODULE
* - \ref CRPT_MODULE
* - \ref WDT_MODULE
* - \ref WWDT_MODULE
* - \ref RTC_MODULE
* - \ref TMR0_MODULE
* - \ref TMR1_MODULE
* - \ref TMR2_MODULE
* - \ref TMR3_MODULE
* - \ref CLKO_MODULE
* - \ref ACMP_MODULE
* - \ref I2C0_MODULE
* - \ref I2C1_MODULE
* - \ref I2C2_MODULE
* - \ref I2C3_MODULE
* - \ref SPI0_MODULE
* - \ref SPI1_MODULE
* - \ref SPI2_MODULE
* - \ref SPI3_MODULE
* - \ref UART0_MODULE
* - \ref UART1_MODULE
* - \ref UART2_MODULE
* - \ref UART3_MODULE
* - \ref UART4_MODULE
* - \ref UART5_MODULE
* - \ref CAN0_MODULE
* - \ref CAN1_MODULE
* - \ref OTG_MODULE
* - \ref ADC_MODULE
* - \ref I2S0_MODULE
* - \ref I2S1_MODULE
* - \ref PS2_MODULE
* - \ref SC0_MODULE
* - \ref SC1_MODULE
* - \ref SC2_MODULE
* - \ref SC3_MODULE
* - \ref SC4_MODULE
* - \ref SC5_MODULE
* - \ref I2C4_MODULE
* - \ref PWM0CH01_MODULE
* - \ref PWM0CH23_MODULE
* - \ref PWM0CH45_MODULE
* - \ref PWM1CH01_MODULE
* - \ref PWM1CH23_MODULE
* - \ref PWM1CH45_MODULE
* - \ref QEI0_MODULE
* - \ref QEI1_MODULE
* - \ref ECAP0_MODULE
* - \ref ECAP1_MODULE
* - \ref EPWM0_MODULE
* - \ref EPWM1_MODULE
* - \ref OPA_MODULE
* - \ref EADC_MODULE
* @return None
*/
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
{
*(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) |= 1<<MODULE_IP_EN_Pos(u32ModuleIdx);
}
/**
* @brief This function disable module clock
* @param[in] u32ModuleIdx is module index. Including :
* - \ref PDMA_MODULE
* - \ref ISP_MODULE
* - \ref EBI_MODULE
* - \ref USBH_MODULE
* - \ref EMAC_MODULE
* - \ref SDH_MODULE
* - \ref CRC_MODULE
* - \ref CAP_MODULE
* - \ref USBD_MODULE
* - \ref CRPT_MODULE
* - \ref WDT_MODULE
* - \ref WWDT_MODULE
* - \ref RTC_MODULE
* - \ref TMR0_MODULE
* - \ref TMR1_MODULE
* - \ref TMR2_MODULE
* - \ref TMR3_MODULE
* - \ref CLKO_MODULE
* - \ref ACMP_MODULE
* - \ref I2C0_MODULE
* - \ref I2C1_MODULE
* - \ref I2C2_MODULE
* - \ref I2C3_MODULE
* - \ref SPI0_MODULE
* - \ref SPI1_MODULE
* - \ref SPI2_MODULE
* - \ref SPI3_MODULE
* - \ref UART0_MODULE
* - \ref UART1_MODULE
* - \ref UART2_MODULE
* - \ref UART3_MODULE
* - \ref UART4_MODULE
* - \ref UART5_MODULE
* - \ref CAN0_MODULE
* - \ref CAN1_MODULE
* - \ref OTG_MODULE
* - \ref ADC_MODULE
* - \ref I2S0_MODULE
* - \ref I2S1_MODULE
* - \ref PS2_MODULE
* - \ref SC0_MODULE
* - \ref SC1_MODULE
* - \ref SC2_MODULE
* - \ref SC3_MODULE
* - \ref SC4_MODULE
* - \ref SC5_MODULE
* - \ref I2C4_MODULE
* - \ref PWM0CH01_MODULE
* - \ref PWM0CH23_MODULE
* - \ref PWM0CH45_MODULE
* - \ref PWM1CH01_MODULE
* - \ref PWM1CH23_MODULE
* - \ref PWM1CH45_MODULE
* - \ref QEI0_MODULE
* - \ref QEI1_MODULE
* - \ref ECAP0_MODULE
* - \ref ECAP1_MODULE
* - \ref EPWM0_MODULE
* - \ref EPWM1_MODULE
* - \ref OPA_MODULE
* - \ref EADC_MODULE
* @return None
*/
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
{
*(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) &= ~(1<<MODULE_IP_EN_Pos(u32ModuleIdx));
}
/**
* @brief This function set PLL frequency
* @param[in] u32PllClkSrc is PLL clock source. Including :
* - \ref CLK_PLLCTL_PLLSRC_HIRC
* - \ref CLK_PLLCTL_PLLSRC_HXT
* @param[in] u32PllFreq is PLL frequency
* @return None
*/
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
{
uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC;
uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR;
/* Disable PLL first to avoid unstable when setting PLL */
CLK_DisablePLL();
/* PLL source clock is from HXT */
if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
{
/* Enable HXT clock */
CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
/* Wait for HXT clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/* Select PLL source clock from HXT */
u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT;
u32PllSrcClk = __HXT;
/* u32NR start from 2 */
u32NR = 2;
}
/* PLL source clock is from HIRC */
else
{
/* Enable HIRC clock */
CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
/* Wait for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Select PLL source clock from HIRC */
u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC;
u32PllSrcClk = __HIRC;
/* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */
u32NR = 4;
}
/* Select "NO" according to request frequency */
if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq > FREQ_250MHZ))
{
u32NO = 0;
}
else if((u32PllFreq <= FREQ_250MHZ) && (u32PllFreq > FREQ_125MHZ))
{
u32NO = 1;
u32PllFreq = u32PllFreq << 1;
}
else if((u32PllFreq <= FREQ_125MHZ) && (u32PllFreq >= FREQ_50MHZ))
{
u32NO = 3;
u32PllFreq = u32PllFreq << 2;
}
else
{
/* Wrong frequency request. Just return default setting. */
goto lexit;
}
/* Find best solution */
u32Min = (uint32_t) - 1;
u32MinNR = 0;
u32MinNF = 0;
for(; u32NR <= 33; u32NR++)
{
u32Tmp = u32PllSrcClk / u32NR;
if((u32Tmp > 1600000) && (u32Tmp < 16000000))
{
for(u32NF = 2; u32NF <= 513; u32NF++)
{
u32Tmp2 = u32Tmp * u32NF;
if((u32Tmp2 >= 200000000) && (u32Tmp2 <= 500000000))
{
u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2;
if(u32Tmp3 < u32Min)
{
u32Min = u32Tmp3;
u32MinNR = u32NR;
u32MinNF = u32NF;
/* Break when get good results */
if(u32Min == 0)
break;
}
}
}
}
}
/* Enable and apply new PLL setting. */
CLK->PLLCTL = u32CLK_SRC | (u32NO << 14) | ((u32MinNR - 2) << 9) | (u32MinNF - 2);
/* Wait for PLL clock stable */
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
/* Return actual PLL output clock frequency */
return u32PllSrcClk / ((u32NO + 1) * u32MinNR) * u32MinNF;
lexit:
/* Apply default PLL setting and return */
if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT; /* 84MHz */
else
CLK->PLLCTL = CLK_PLLCTL_50MHz_HIRC; /* 50MHz */
/* Wait for PLL clock stable */
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
return CLK_GetPLLClockFreq();
}
/**
* @brief This function disable PLL
* @return None
*/
void CLK_DisablePLL(void)
{
CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
}
/**
* @brief This function set SysTick clock source
* @param[in] u32ClkSrc is SysTick clock source. Including :
* - \ref CLK_CLKSEL0_STCLKSEL_HXT
* - \ref CLK_CLKSEL0_STCLKSEL_LXT
* - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
* - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
* - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
* @return None
*/
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
{
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc ;
}
/**
* @brief This function execute delay function.
* @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
* 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ...
* @return Delay success or not
* @retval 0 Success, target delay time reached
* @details Use the SysTick to generate the delay time and the UNIT is in us.
* The SysTick clock source is from HCLK, i.e the same as system core clock.
* User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
*/
int32_t CLK_SysTickDelay(uint32_t us)
{
/* The u32TimeOutCnt value must be greater than the max delay time of 1398ms if HCLK=12MHz */
uint32_t u32TimeOutCnt = SystemCoreClock * 2;
SysTick->LOAD = us * CyclesPerUs;
SysTick->VAL = (0x00);
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
/* Waiting for down-count to zero */
while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0)
{
if(--u32TimeOutCnt == 0)
{
break;
}
}
/* Disable SysTick counter */
SysTick->CTRL = 0;
if(u32TimeOutCnt == 0)
return CLK_TIMEOUT_ERR;
else
return 0;
}
/**
* @brief This function check selected clock source status
* @param[in] u32ClkMask is selected clock source. Including
* - \ref CLK_STATUS_CLKSFAIL_Msk
* - \ref CLK_STATUS_HIRCSTB_Msk
* - \ref CLK_STATUS_LIRCSTB_Msk
* - \ref CLK_STATUS_PLLSTB_Msk
* - \ref CLK_STATUS_LXTSTB_Msk
* - \ref CLK_STATUS_HXTSTB_Msk
*
* @return 0 clock is not stable
* 1 clock is stable
*
* @details To wait for clock ready by specified CLKSTATUS bit or timeout (~500ms)
* @note This function sets g_CLK_i32ErrCode to CLK_TIMEOUT_ERR if clock source status is not stable
*/
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
{
uint32_t u32TimeOutCnt = SystemCoreClock / 2;
uint32_t u32Ret = 1U;
g_CLK_i32ErrCode = 0;
while((CLK->STATUS & u32ClkMask) != u32ClkMask)
{
if(--u32TimeOutCnt == 0)
{
u32Ret = 0U;
break;
}
}
if(u32TimeOutCnt == 0)
g_CLK_i32ErrCode = CLK_TIMEOUT_ERR;
return u32Ret;
}
/**
* @brief Enable System Tick counter
* @param[in] u32ClkSrc is System Tick clock source. Including:
* - \ref CLK_CLKSEL0_STCLKSEL_HXT
* - \ref CLK_CLKSEL0_STCLKSEL_LXT
* - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
* - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
* - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
* - \ref CLK_CLKSEL0_STCLKSEL_HCLK
* @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF.
* @return None
* @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n
* The register write-protection function should be disabled before using this function.
*/
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
{
/* Set System Tick counter disabled */
SysTick->CTRL = 0;
/* Set System Tick clock source */
if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK )
SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
else
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
/* Set System Tick reload value */
SysTick->LOAD = u32Count;
/* Clear System Tick current value and counter flag */
SysTick->VAL = 0;
/* Set System Tick interrupt enabled and counter enabled */
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
}
/**
* @brief Disable System Tick counter
* @param None
* @return None
* @details This function disable System Tick counter.
*/
void CLK_DisableSysTick(void)
{
/* Set System Tick counter disabled */
SysTick->CTRL = 0;
}
/*@}*/ /* end of group NUC472_442_CLK_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group NUC472_442_CLK_Driver */
/*@}*/ /* end of group NUC472_442_Device_Driver */
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

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demo/nuvoton/usb_device/nuc442/StdDriver/src/retarget.c Normal file
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@@ -0,0 +1,629 @@
/**************************************************************************//**
* @file retarget.c
* @version V1.00
* $Revision: 12 $
* $Date: 15/10/30 3:33p $
* @brief NUC472/NUC442 Debug Port and Semihost Setting Source File
*
* @note
* SPDX-License-Identifier: Apache-2.0
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include <stdio.h>
#include "NUC472_442.h"
#if defined ( __CC_ARM )
#if (__ARMCC_VERSION < 400000)
#else
/* Insist on keeping widthprec, to avoid X propagation by benign code in C-lib */
#pragma import _printf_widthprec
#endif
#endif
/* Un-comment this line to disable all printf and getchar. getchar() will always return 0x00*/
//#define DISABLE_UART
#if defined(DEBUG_ENABLE_SEMIHOST)
#ifndef DISABLE_UART
#define DISABLE_UART
#endif
#endif
/*--------------------------------------------------------------------------------------------------------- */
/* Global variables */
/*--------------------------------------------------------------------------------------------------------- */
#if !(defined(__ICCARM__) && (__VER__ >= 6010000))
# if (__ARMCC_VERSION < 6040000)
struct __FILE
{
int handle; /* Add whatever you need here */
};
# endif
#elif(__VER__ >= 8000000)
struct __FILE
{
int handle; /* Add whatever you need here */
};
#endif
FILE __stdout;
FILE __stdin;
enum { r0, r1, r2, r3, r12, lr, pc, psr};
/**
* @brief Helper function to dump register while hard fault occurred
* @param[in] stack pointer points to the dumped registers in SRAM
* @return None
*/
static void stackDump(uint32_t stack[])
{
printf("r0 = 0x%x\n", stack[r0]);
printf("r1 = 0x%x\n", stack[r1]);
printf("r2 = 0x%x\n", stack[r2]);
printf("r3 = 0x%x\n", stack[r3]);
printf("r12 = 0x%x\n", stack[r12]);
printf("lr = 0x%x\n", stack[lr]);
printf("pc = 0x%x\n", stack[pc]);
printf("psr = 0x%x\n", stack[psr]);
}
/**
* @brief Hard fault handler
* @param[in] stack pointer points to the dumped registers in SRAM
* @return None
* @note Replace while(1) at the end of this function with chip reset if WDT is not enabled for end product
*/
void Hard_Fault_Handler(uint32_t stack[])
{
printf("In Hard Fault Handler\n");
stackDump(stack);
// Replace while(1) with chip reset if WDT is not enabled for end product
while(1);
//SYS->IPRSTC1 = SYS_IPRSTC1_CHIP_RST_Msk;
}
#if defined(DEBUG_ENABLE_SEMIHOST)
/* The static buffer is used to speed up the semihost */
static char g_buf[16];
static char g_buf_len = 0;
/* Make sure won't goes here only because --gnu is defined , so
add !__CC_ARM and !__ICCARM__ checking */
# if defined ( __GNUC__ ) && !(__CC_ARM) && !(__ICCARM__)
# elif defined(__ICCARM__) // IAR
void SH_End(void)
{
asm("MOVS R0,#1 \n" //; Set return value to 1
"BX lr \n" //; Return
);
}
void SH_ICE(void)
{
asm("CMP R2,#0 \n"
"BEQ SH_End \n"
"STR R0,[R2] \n" //; Save the return value to *pn32Out_R0
);
}
/**
*
* @brief The function to process semihosted command
* @param[in] n32In_R0 : semihost register 0
* @param[in] n32In_R1 : semihost register 1
* @param[out] pn32Out_R0: semihost register 0
* @retval 0: No ICE debug
* @retval 1: ICE debug
*
*/
int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
{
asm("BKPT 0xAB \n" //; This instruction will cause ICE trap or system HardFault
"B SH_ICE \n"
"SH_HardFault: \n" //; Captured by HardFault
"MOVS R0,#0 \n" //; Set return value to 0
"BX lr \n" //; Return
);
return 1; //; Return 1 when it is trap by ICE
}
void Get_LR_and_Branch(void)
{
asm("MOV R1, LR \n" //; LR current value
"B Hard_Fault_Handler \n"
);
}
void Stack_Use_MSP(void)
{
asm("MRS R0, MSP \n" //; stack use MSP
"B Get_LR_and_Branch \n"
);
}
void HardFault_Handler_Ret(void)
{
asm("MOVS r0, #4 \n"
"MOV r1, LR \n"
"TST r0, r1 \n"
"BEQ Stack_Use_MSP \n"
"MRS R0, PSP \n" //; stack use PSP
"B Get_LR_and_Branch \n"
);
}
void SP_Read_Ready(void)
{
asm("LDR R1, [R0, #24] \n" //; Get previous PC
"LDRH R3, [R1] \n" //; Get instruction
"LDR R2, [pc, #8] \n" //; The special BKPT instruction
"CMP R3, R2 \n" //; Test if the instruction at previous PC is BKPT
"BNE HardFault_Handler_Ret \n" //; Not BKPT
"ADDS R1, #4 \n" //; Skip BKPT and next line
"STR R1, [R0, #24] \n" //; Save previous PC
"BX lr \n" //; Return
"DCD 0xBEAB \n" //; BKPT instruction code
"B HardFault_Handler_Ret \n"
);
}
void SP_is_PSP(void)
{
asm(
"MRS R0, PSP \n"
);
}
/**
* @brief This HardFault handler is implemented to support semihost
*
* @param None
*
* @returns None
*
* @details This function is implement to support semihost message print.
*
*/
void HardFault_Handler (void)
{
asm("MOV R0, lr \n"
"LSLS R0, #29 \n" //; Check bit 2
"BMI SP_is_PSP \n" //; previous stack is PSP
"MRS R0, MSP \n" //; previous stack is MSP, read MSP
"B SP_Read_Ready \n"
);
while(1);
}
# else
/**
* @brief This HardFault handler is implemented to support semihost
*
* @param None
*
* @returns None
*
* @details This function is implement to support semihost message print.
*
*/
__asm int32_t HardFault_Handler(void)
{
MOV R0, LR
LSLS R0, #29 //; Check bit 2
BMI SP_is_PSP //; previous stack is PSP
MRS R0, MSP //; previous stack is MSP, read MSP
B SP_Read_Ready
SP_is_PSP
MRS R0, PSP //; Read PSP
SP_Read_Ready
LDR R1, [R0, #24] //; Get previous PC
LDRH R3, [R1] //; Get instruction
LDR R2, =0xBEAB //; The special BKPT instruction
CMP R3, R2 //; Test if the instruction at previous PC is BKPT
BNE HardFault_Handler_Ret //; Not BKPT
ADDS R1, #4 //; Skip BKPT and next line
STR R1, [R0, #24] //; Save previous PC
BX LR //; Return
HardFault_Handler_Ret
/* TODO: Implement your own hard fault handler here. */
MOVS r0, #4
MOV r1, LR
TST r0, r1
BEQ Stack_Use_MSP
MRS R0, PSP ;stack use PSP
B Get_LR_and_Branch
Stack_Use_MSP
MRS R0, MSP ; stack use MSP
Get_LR_and_Branch
MOV R1, LR ; LR current value
LDR R2,=__cpp(Hard_Fault_Handler)
BX R2
B .
ALIGN
}
/**
*
* @brief The function to process semihosted command
* @param[in] n32In_R0 : semihost register 0
* @param[in] n32In_R1 : semihost register 1
* @param[out] pn32Out_R0: semihost register 0
* @retval 0: No ICE debug
* @retval 1: ICE debug
*
*/
__asm int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
{
BKPT 0xAB //; Wait ICE or HardFault
//; ICE will step over BKPT directly
//; HardFault will step BKPT and the next line
B SH_ICE
SH_HardFault //; Captured by HardFault
MOVS R0, #0 //; Set return value to 0
BX lr //; Return
SH_ICE //; Captured by ICE
//; Save return value
CMP R2, #0
BEQ SH_End
STR R0, [R2] //; Save the return value to *pn32Out_R0
SH_End
MOVS R0, #1 //; Set return value to 1
BX lr //; Return
}
#endif
#else
/* Make sure won't goes here only because --gnu is defined , so
add !__CC_ARM and !__ICCARM__ checking */
# if defined ( __GNUC__ ) && !(__CC_ARM) && !(__ICCARM__)
/**
* @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr
*
* @param None
*
* @returns None
*
* @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr.
*
*/
void HardFault_Handler(void)
{
asm("MOVS r0, #4 \n"
"MOV r1, LR \n"
"TST r0, r1 \n" /*; check LR bit 2 */
"BEQ 1f \n" /*; stack use MSP */
"MRS R0, PSP \n" /*; stack use PSP, read PSP */
"MOV R1, LR \n" /*; LR current value */
"B Hard_Fault_Handler \n"
"1: \n"
"MRS R0, MSP \n" /*; LR current value */
"B Hard_Fault_Handler \n"
::[Hard_Fault_Handler] "r" (Hard_Fault_Handler) // input
);
while(1);
}
# elif defined(__ICCARM__)
void Get_LR_and_Branch(void)
{
asm("MOV R1, LR \n" //; LR current value
"B Hard_Fault_Handler \n"
);
}
void Stack_Use_MSP(void)
{
asm("MRS R0, MSP \n" //; stack use MSP
"B Get_LR_and_Branch \n"
);
}
/**
* @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr
*
* @param None
*
* @returns None
*
* @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr.
*
*/
void HardFault_Handler(void)
{
asm("MOVS r0, #4 \n"
"MOV r1, LR \n"
"TST r0, r1 \n"
"BEQ Stack_Use_MSP \n"
"MRS R0, PSP \n" //; stack use PSP
"B Get_LR_and_Branch \n"
);
while(1);
}
# else
/**
* @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr
*
* @param None
*
* @returns None
*
* @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr
*
*/
__asm int32_t HardFault_Handler(void)
{
MOVS r0, #4
MOV r1, LR
TST r0, r1
BEQ Stack_Use_MSP
MRS R0, PSP ;stack use PSP
B Get_LR_and_Branch
Stack_Use_MSP
MRS R0, MSP ; stack use MSP
Get_LR_and_Branch
MOV R1, LR ; LR current value
LDR R2,=__cpp(Hard_Fault_Handler)
BX R2
}
#endif
#endif
#define DEBUG_PORT UART0
/**
* @brief Write a char to UART.
* @param ch The character sent to UART.
* @return None
*/
void SendChar_ToUART(int ch)
{
#ifndef DISABLE_UART
while((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)); //waits for TXFULL bit is clear
DEBUG_PORT->DAT = ch;
if(ch == '\n') {
while((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)); //waits for TXFULL bit is clear
DEBUG_PORT->DAT = '\r';
}
#endif
}
/**
* @brief Write a char to debug console.
* @param ch The character sent to debug console
* @return None
*/
void SendChar(int ch)
{
#if defined(DEBUG_ENABLE_SEMIHOST)
g_buf[g_buf_len++] = ch;
g_buf[g_buf_len] = '\0';
if(g_buf_len + 1 >= sizeof(g_buf) || ch == '\n' || ch == '\0') {
/* Send the char */
if(SH_DoCommand(0x04, (int)g_buf, NULL) != 0) {
g_buf_len = 0;
return;
} else {
int i;
for(i=0; i<g_buf_len; i++)
SendChar_ToUART(g_buf[i]);
g_buf_len = 0;
}
}
#else
SendChar_ToUART(ch);
#endif
}
/**
* @brief Read a char from debug console.
* @param None
* @return Received character from debug console
* @note This API waits until UART debug port or semihost input a character
*/
char GetChar(void)
{
#if defined(DEBUG_ENABLE_SEMIHOST)
# if defined ( __CC_ARM )
int nRet;
while(SH_DoCommand(0x101, 0, &nRet) != 0) {
if(nRet != 0) {
SH_DoCommand(0x07, 0, &nRet);
return (char)nRet;
}
}
# else
int nRet;
while(SH_DoCommand(0x7, 0, &nRet) != 0) {
if(nRet != 0)
return (char)nRet;
}
# endif
#endif
#ifndef DISABLE_UART
while (1) {
if((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0 ) {
return (DEBUG_PORT->DAT);
}
}
#else
return(0);
#endif
}
/**
* @brief Check whether UART receive FIFO is empty or not.
* @param None
* @return UART Rx FIFO empty status
* @retval 1 Indicates at least one character is available in UART Rx FIFO
* @retval 0 UART Rx FIFO is empty
*/
int kbhit(void)
{
#ifndef DISABLE_UART
return !(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXFULL_Msk);
#else
return(0);
#endif
}
/**
* @brief Check whether UART transmit FIFO is empty or not.
* @param None
* @return UART Tx FIFO empty status
* @retval 1 UART Tx FIFO is empty
* @retval 0 UART Tx FIFO is not empty
*/
int IsDebugFifoEmpty(void)
{
#ifndef DISABLE_UART
return (DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk);
#else
return(1);
#endif
}
/**
* @brief C library retargetting
* @param ch Character to send out
* @return None
* @details Check if message finished (FIFO empty of debug port)
*/
void _ttywrch(int ch)
{
SendChar(ch);
return;
}
#if defined ( __GNUC__ )
int _write (int fd, char *ptr, int len)
{
int i = len;
while(i--) {
while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
DEBUG_PORT->DAT = *ptr++;
if(*ptr == '\n') {
while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
DEBUG_PORT->DAT = '\r';
}
}
return len;
}
int _read (int fd, char *ptr, int len)
{
while((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) != 0);
*ptr = DEBUG_PORT->DAT;
return 1;
}
#else
/**
* @brief Write character to stream
* @param[in] ch Character to be written. The character is passed as its int promotion.
* @param[in] stream Pointer to a FILE object that identifies the stream where the character is to be written.
* @return If there are no errors, the same character that has been written is returned.
* If an error occurs, EOF is returned and the error indicator is set (see ferror).
* @details Writes a character to the stream and advances the position indicator.\n
* The character is written at the current position of the stream as indicated \n
* by the internal position indicator, which is then advanced one character.
* @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/fputc/.
*
*/
int fputc(int ch, FILE *stream)
{
SendChar(ch);
return ch;
}
/**
* @brief Get character from UART debug port or semihosting input
* @param[in] stream Pointer to a FILE object that identifies the stream on which the operation is to be performed.
* @return The character read from UART debug port or semihosting
* @details For get message from debug port or semihosting.
*
*/
int fgetc(FILE *stream)
{
return (GetChar());
}
/**
* @brief Check error indicator
* @param[in] stream Pointer to a FILE object that identifies the stream.
* @return If the error indicator associated with the stream was set, the function returns a nonzero value.
* Otherwise, it returns a zero value.
* @details Checks if the error indicator associated with stream is set, returning a value different
* from zero if it is. This indicator is generally set by a previous operation on the stream that failed.
* @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/ferror/.
*/
int ferror(FILE *stream)
{
return EOF;
}
#endif
#ifdef DEBUG_ENABLE_SEMIHOST
# ifdef __ICCARM__
void __exit(int return_code)
{
/* Check if link with ICE */
if(SH_DoCommand(0x18, 0x20026, NULL) == 0) {
/* Make sure all message is print out */
while(IsDebugFifoEmpty() == 0);
}
label:
goto label; /* endless loop */
}
# else
void _sys_exit(int return_code)
{
/* Check if link with ICE */
if(SH_DoCommand(0x18, 0x20026, NULL) == 0) {
/* Make sure all message is print out */
while(IsDebugFifoEmpty() == 0);
}
label:
goto label; /* endless loop */
}
# endif
#endif
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/

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/*************************************************************************//**
* @file sys.c
* @version V1.00
* $Revision: 16 $
* $Date: 15/10/21 1:39p $
* @brief NUC472/NUC442 SYS driver source file
*
* @note
* SPDX-License-Identifier: Apache-2.0
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NUC472_442.h"
/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
@{
*/
/** @addtogroup NUC472_442_SYS_Driver SYS Driver
@{
*/
/** @addtogroup NUC472_442_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
@{
*/
/**
* @brief This function clear the selected system reset source
* @param[in] u32RstSrc is system reset source. Including:
* - \ref SYS_RSTSTS_PORF_Msk
* - \ref SYS_RSTSTS_PINRF_Msk
* - \ref SYS_RSTSTS_WDTRF_Msk
* - \ref SYS_RSTSTS_LVRF_Msk
* - \ref SYS_RSTSTS_BODRF_Msk
* - \ref SYS_RSTSTS_SYSRF_Msk
* - \ref SYS_RSTSTS_CPURF_Msk
* @return None
*/
void SYS_ClearResetSrc(uint32_t u32RstSrc)
{
SYS->RSTSTS |= u32RstSrc;
}
/**
* @brief This function get Brown-out detector output status
* @return 0: System voltage is higher than BODVL setting or BODEN is 0.
* 1: System voltage is lower than BODVL setting.
* Note : If the BOD_EN is 0, this function always return 0.
*/
uint32_t SYS_GetBODStatus()
{
return (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk);
}
/**
* @brief This function get the system reset source register value
* @return Reset source
*/
uint32_t SYS_GetResetSrc(void)
{
return (SYS->RSTSTS);
}
/**
* @brief This function check register write-protection bit setting
* @return 0: Write-protection function is disabled.
* 1: Write-protection function is enabled.
*/
uint32_t SYS_IsRegLocked(void)
{
return !(SYS->REGLCTL & SYS_REGLCTL_REGLCTL_Msk);
}
/**
* @brief This function enable register write-protection function
* @return None
* @details To lock the protected register to forbid write access
*/
void SYS_LockReg(void)
{
SYS->REGLCTL = 0;
}
/**
* @brief This function disable register write-protection function
* @return None
* @details To unlock the protected register to allow write access
*/
void SYS_UnlockReg(void)
{
while(SYS->REGLCTL != SYS_REGLCTL_REGLCTL_Msk)
{
SYS->REGLCTL = 0x59;
SYS->REGLCTL = 0x16;
SYS->REGLCTL = 0x88;
}
}
/**
* @brief This function get product ID.
* @return Product ID
*/
uint32_t SYS_ReadPDID(void)
{
return SYS->PDID;
}
/**
* @brief This function reset chip.
* @return None
*/
void SYS_ResetChip(void)
{
SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
}
/**
* @brief This function reset CPU.
* @return None
*/
void SYS_ResetCPU(void)
{
SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk;
}
/**
* @brief This function reset selected modules.
* @param[in] u32ModuleIndex is module index. Including :
* - \ref PDMA_RST
* - \ref EBI_RST
* - \ref USBH_RST
* - \ref EMAC_RST
* - \ref SDH_RST
* - \ref CRC_RST
* - \ref CAP_RST
* - \ref CRYPTO_RST
* - \ref GPIO_RST
* - \ref TMR0_RST
* - \ref TMR1_RST
* - \ref TMR2_RST
* - \ref TMR3_RST
* - \ref ACMP_RST
* - \ref I2C0_RST
* - \ref I2C1_RST
* - \ref I2C2_RST
* - \ref I2C3_RST
* - \ref SPI0_RST
* - \ref SPI1_RST
* - \ref SPI2_RST
* - \ref SPI3_RST
* - \ref UART0_RST
* - \ref UART1_RST
* - \ref UART2_RST
* - \ref UART3_RST
* - \ref UART4_RST
* - \ref UART5_RST
* - \ref CAN0_RST
* - \ref CAN1_RST
* - \ref OTG_RST
* - \ref USBD_RST
* - \ref ADC_RST
* - \ref I2S0_RST
* - \ref I2S1_RST
* - \ref PS2_RST
* - \ref SC0_RST
* - \ref SC1_RST
* - \ref SC2_RST
* - \ref SC3_RST
* - \ref SC4_RST
* - \ref SC5_RST
* - \ref I2C4_RST
* - \ref PWM0_RST
* - \ref PWM1_RST
* - \ref QEI0_RST
* - \ref QEI1_RST
* @return None
*/
void SYS_ResetModule(uint32_t u32ModuleIndex)
{
*(volatile uint32_t *)((uint32_t)&(SYS->IPRST0) + (u32ModuleIndex>>24)) |= 1<<(u32ModuleIndex & 0x00ffffff);
*(volatile uint32_t *)((uint32_t)&(SYS->IPRST0) + (u32ModuleIndex>>24)) &= ~(1<<(u32ModuleIndex & 0x00ffffff));
}
/**
* @brief This function configure BOD function.
* Configure BOD reset or interrupt mode and set Brown-out voltage level.
* Enable Brown-out function
* @param[in] i32Mode is reset or interrupt mode. Including :
* - \ref SYS_BODCTL_BODRSTEN
* - \ref SYS_BODCTL_BODINTEN
* @param[in] u32BODLevel is Brown-out voltage level. Including :
* - \ref SYS_BODCTL_BODVL_2_2V
* - \ref SYS_BODCTL_BODVL_2_7V
* - \ref SYS_BODCTL_BODVL_3_8V
* - \ref SYS_BODCTL_BODVL_4_5V
*
* @return None
*/
void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
{
SYS->BODCTL &= ~(SYS_BODCTL_BODVL_Msk|SYS_BODCTL_BODRSTEN_Msk);
SYS->BODCTL |=(i32Mode|u32BODLevel|SYS_BODCTL_BODEN_Msk);
}
/**
* @brief This function disable BOD function.
* @return None
*/
void SYS_DisableBOD(void)
{
SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk;
}
/*@}*/ /* end of group NUC472_442_SYS_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group NUC472_442_SYS_Driver */
/*@}*/ /* end of group NUC472_442_Device_Driver */
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

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/**************************************************************************//**
* @file uart.c
* @version V1.00
* $Revision: 14 $
* $Date: 15/11/26 10:47a $
* @brief NUC472/NUC442 UART driver source file
*
* @note
* SPDX-License-Identifier: Apache-2.0
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include <stdio.h>
#include "NUC472_442.h"
/*---------------------------------------------------------------------------------------------------------*/
/* Includes of local headers */
/*---------------------------------------------------------------------------------------------------------*/
/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
@{
*/
/** @addtogroup NUC472_442_UART_Driver UART Driver
@{
*/
/** @addtogroup NUC472_442_UART_EXPORTED_FUNCTIONS UART Exported Functions
@{
*/
/**
* @brief The function is used to clear UART specified interrupt flag.
*
* @param[in] uart The base address of UART module.
* @param[in] u32InterruptFlag The specified interrupt of UART module..
*
* @return None
*/
void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag)
{
if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* clear Receive Line Status Interrupt */
{
uart->FIFOSTS |= UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk;
uart->FIFOSTS |= UART_FIFOSTS_ADDRDETF_Msk;
}
if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* clear Modem Interrupt */
uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk;
if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* clear Buffer Error Interrupt */
{
uart->FIFOSTS |= UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;
}
if(u32InterruptFlag & UART_INTSTS_RXTOINT_Msk) /* clear Modem Interrupt */
uart->INTSTS |= UART_INTSTS_RXTOIF_Msk;
}
/**
* @brief The function is used to disable UART.
*
* @param[in] uart The base address of UART module.
*
* @return None
*/
void UART_Close(UART_T* uart)
{
uart->INTEN = 0;
}
/**
* @brief The function is used to disable UART auto flow control.
*
* @param[in] uart The base address of UART module.
*
* @return None
*/
void UART_DisableFlowCtrl(UART_T* uart)
{
uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
}
/**
* @brief The function is used to disable UART specified interrupt and disable NVIC UART IRQ.
*
* @param[in] uart The base address of UART module.
* @param[in] u32InterruptFlag The specified interrupt of UART module.
* - \ref UART_INTEN_TOCNTEN_Msk : Rx Time Out interrupt
* - \ref UART_INTEN_WKCTSIEN_Msk : Wakeup interrupt
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
* - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
* - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
*
* @return None
*/
void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag )
{
uart->INTEN &= ~ u32InterruptFlag;
}
/**
* @brief The function is used to Enable UART auto flow control.
*
* @param[in] uart The base address of UART module.
*
* @return None
*/
void UART_EnableFlowCtrl(UART_T* uart )
{
uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
uart->MODEM &= ~UART_MODEM_RTS_Msk;
uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
}
/**
* @brief The function is used to enable UART specified interrupt and disable NVIC UART IRQ.
*
* @param[in] uart The base address of UART module.
* @param[in] u32InterruptFlag The specified interrupt of UART module:
* - \ref UART_INTEN_TOCNTEN_Msk : Rx Time Out interrupt
* - \ref UART_INTEN_WKCTSIEN_Msk : Wakeup interrupt
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
* - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
* - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
*
* @return None
*/
void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag )
{
uart->INTEN |= u32InterruptFlag;
}
/**
* @brief This function use to enable UART function and set baud-rate.
*
* @param[in] uart The base address of UART module.
* @param[in] u32baudrate The baudrate of UART module.
*
* @return None
*/
void UART_Open(UART_T* uart, uint32_t u32baudrate)
{
uint8_t u8UartClkSrcSel;
uint32_t u32ClkTbl[4] = {__HXT, 0, __HIRC, __HIRC};
uint32_t u32Clk;
uint32_t u32Baud_Div;
u32ClkTbl[1] = CLK_GetPLLClockFreq();
u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
uart->FUNCSEL = UART_FUNCSEL_UART;
uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
uart->FIFO = UART_FIFO_RFITL_1BYTE | UART_FIFO_RTSTRGLV_1BYTE;
u32Clk = (u32ClkTbl[u8UartClkSrcSel]) / (((CLK->CLKDIV0 & CLK_CLKDIV0_UARTDIV_Msk) >> CLK_CLKDIV0_UARTDIV_Pos) + 1);
if(u32baudrate != 0)
{
u32Baud_Div = UART_BAUD_MODE2_DIVIDER(u32Clk, u32baudrate);
if(u32Baud_Div > 0xFFFF)
uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(u32Clk, u32baudrate));
else
uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
}
}
/**
* @brief The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.
*
* @param[in] uart The base address of UART module.
* @param[out] pu8RxBuf The buffer to receive the data of receive FIFO.
* @param[in] u32ReadBytes The the read bytes number of data.
*
* @return u32Count: Receive byte count
*
*/
uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes)
{
uint32_t u32Count;
for(u32Count=0; u32Count < u32ReadBytes; u32Count++)
{
if(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */
{
return u32Count;
}
pu8RxBuf[u32Count] = uart->DAT; /* Get Data from UART RX */
}
return u32Count;
}
/**
* @brief This function use to config UART line setting.
*
* @param[in] uart The base address of UART module.
* @param[in] u32baudrate The register value of baudrate of UART module.
* if u32baudrate = 0, UART baudrate will not change.
* @param[in] u32data_width The data length of UART module. [ \ref UART_WORD_LEN_5 / \ref UART_WORD_LEN_6 / \ref UART_WORD_LEN_7 / \ref UART_WORD_LEN_8]
* @param[in] u32parity The parity setting (odd/even/none) of UART module. [ \ref UART_PARITY_NONE / \ref UART_PARITY_ODD /
* \ref UART_PARITY_EVEN / \ref UART_PARITY_MARK / \ref UART_PARITY_SPACE]
* @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module. [ \ref UART_STOP_BIT_1 / \ref UART_STOP_BIT_1_5 / \ref UART_STOP_BIT_2]
*
* @return None
*/
void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
{
uint8_t u8UartClkSrcSel;
uint32_t u32ClkTbl[4] = {__HXT, 0, __HIRC, __HIRC};
uint32_t u32Clk;
uint32_t u32Baud_Div = 0;
u32ClkTbl[1] = CLK_GetPLLClockFreq();
u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
u32Clk = (u32ClkTbl[u8UartClkSrcSel]) / (((CLK->CLKDIV0 & CLK_CLKDIV0_UARTDIV_Msk) >> CLK_CLKDIV0_UARTDIV_Pos) + 1);
if(u32baudrate != 0)
{
u32Baud_Div = UART_BAUD_MODE2_DIVIDER(u32Clk, u32baudrate);
if(u32Baud_Div > 0xFFFF)
uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(u32Clk, u32baudrate));
else
uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
}
uart->LINE = u32data_width | u32parity | u32stop_bits;
}
/**
* @brief This function use to set Rx timeout count.
*
* @param[in] uart The base address of UART module.
* @param[in] u32TOC Rx timeout counter.
*
* @return None
*/
void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)
{
uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk)| (u32TOC);
uart->INTEN |= UART_INTEN_TOCNTEN_Msk;
}
/**
* @brief The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
*
* @param[in] uart The base address of UART module.
* @param[in] u32Buadrate The baudrate of UART module.
* @param[in] u32Direction The direction(transmit:1/receive:0) of UART module in IrDA mode.
*
* @return None
*/
void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)
{
uint8_t u8UartClkSrcSel;
uint32_t u32ClkTbl[4] = {__HXT, 0, __HIRC, __HIRC};
uint32_t u32Clk;
u32ClkTbl[1] = CLK_GetPLLClockFreq();
u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
u32Clk = (u32ClkTbl[u8UartClkSrcSel]) / (((CLK->CLKDIV0 & CLK_CLKDIV0_UARTDIV_Msk) >> CLK_CLKDIV0_UARTDIV_Pos) + 1);
uart->BAUD = UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(u32Clk, u32Buadrate);
uart->IRDA &= ~UART_IRDA_TXINV_Msk;
uart->IRDA |= UART_IRDA_RXINV_Msk;
uart->IRDA = u32Direction ? uart->IRDA | UART_IRDA_TXEN_Msk : uart->IRDA &~ UART_IRDA_TXEN_Msk;
uart->FUNCSEL = (0x2 << UART_FUNCSEL_FUNCSEL_Pos);
}
/**
* @brief The function is used to set RS485 relative setting.
*
* @param[in] uart The base address of UART module.
* @param[in] u32Mode The operation mode( \ref UART_ALTCTL_RS485NMM_Msk / \ref UART_ALTCTL_RS485AUD_Msk / \ref UART_ALTCTL_RS485AAD_Msk).
* @param[in] u32Addr The RS485 address.
*
* @return None
*/
void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr)
{
uart->FUNCSEL = UART_FUNCSEL_RS485;
uart->ALTCTL = 0;
uart->ALTCTL |= u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos);
}
/**
* @brief The function is to write data into TX buffer to transmit data by UART.
*
* @param[in] uart The base address of UART module.
* @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO.
* @param[in] u32WriteBytes The byte number of data.
*
* @return u32Count: transfer byte count
* @note This function returns when the TX FIFO is full. So the transfer byte count(u32Count) maybe less than u32WriteBytes.
* Application should check the return value for the actual amount of data written to UART FIFO.
*/
uint32_t UART_Write(UART_T* uart,uint8_t *pu8TxBuf, uint32_t u32WriteBytes)
{
uint32_t u32Count;
for(u32Count=0; u32Count != u32WriteBytes; u32Count++)
{
if(uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) /* Wait Tx empty and Time-out manner */
{
return u32Count;
}
uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */
}
return u32Count;
}
/*@}*/ /* end of group NUC472_442_UART_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group NUC472_442_UART_Driver */
/*@}*/ /* end of group NUC472_442_Device_Driver */
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

104
demo/nuvoton/usb_device/nuc442/User/main.c Normal file
View File

@@ -0,0 +1,104 @@
/******************************************************************************
* @file main.c
* @brief Demonstrate how to implement a USB virtual com port device.
* @version 2.0.0
* @date 22, Sep, 2014
*
* @note
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#include <stdio.h>
#include "NUC472_442.h"
/*--------------------------------------------------------------------------*/
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable External XTAL (4~24 MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Waiting for 12MHz clock ready */
CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk);
/* Switch HCLK clock source to HXT */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware.*/
CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
/* Set PLL frequency */
CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT;
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
/* Switch HCLK clock source to PLL */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1));
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));
/* Enable IP clock */
CLK_EnableModuleClock(UART0_MODULE);
CLK_EnableModuleClock(USBD_MODULE);
/* Enable USB PHY */
SYS->USBPHY = 0x100; // USB device
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
SystemCoreClockUpdate();
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set GPG multi-function pins for UART0 RXD and TXD (15, 16) */
SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG1MFP_Msk | SYS_GPG_MFPL_PG2MFP_Msk);
SYS->GPG_MFPL |= (SYS_GPG_MFPL_PG1MFP_UART0_RXD | SYS_GPG_MFPL_PG2MFP_UART0_TXD);
/* Lock protected registers */
SYS_LockReg();
}
void DelayMs(uint32_t ulMs)
{
uint32_t i;
uint32_t j;
for(i = ulMs; i > 0; i--)
{
for(j = 4700; j > 0; j--);
}
}
/*---------------------------------------------------------------------------------------------------------*/
/* Main Function */
/*---------------------------------------------------------------------------------------------------------*/
int32_t main (void)
{
SYS_Init();
UART_Open(UART0, 115200);
printf("NuMicro USB CDC VCOM\n");
extern void cdc_acm_init(void);
cdc_acm_init();
NVIC_EnableIRQ(USBD_IRQn);
while(1)
{
extern void cdc_acm_data_send_with_dtr_test();
cdc_acm_data_send_with_dtr_test();
DelayMs(100);
}
}
/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/

337
port/nuvoton/usb_dc_nuvoton.c
View File

@@ -1,10 +1,43 @@
#include "usbd_core.h"
#include "usb_nuvoton_reg.h"
#ifndef USB_NUM_BIDIR_ENDPOINTS
#define USB_NUM_BIDIR_ENDPOINTS 5
#ifndef USB_BASE
#define USB_BASE (0x40000000 + 0x19000)
#endif
#define USBD ((USBD_T *)USB_BASE)
#ifndef USB_NUM_BIDIR_ENDPOINTS
#define USB_NUM_BIDIR_ENDPOINTS 13
#endif
#define USBD_ENABLE_USB() ((uint32_t)(USBD->PHYCTL |= (USBD_PHYCTL_PHYEN_Msk | USBD_PHYCTL_DPPUEN_Msk))) /*!<Enable USB \hideinitializer */
#define USBD_DISABLE_USB() ((uint32_t)(USBD->PHYCTL &= ~USBD_PHYCTL_DPPUEN_Msk)) /*!<Disable USB \hideinitializer */
#define USBD_ENABLE_PHY() ((uint32_t)(USBD->PHYCTL |= USBD_PHYCTL_PHYEN_Msk)) /*!<Enable PHY \hideinitializer */
#define USBD_DISABLE_PHY() ((uint32_t)(USBD->PHYCTL &= ~USBD_PHYCTL_PHYEN_Msk)) /*!<Disable PHY \hideinitializer */
#define USBD_SET_SE0() ((uint32_t)(USBD->PHYCTL &= ~USBD_PHYCTL_DPPUEN_Msk)) /*!<Enable SE0, Force USB PHY Transceiver to Drive SE0 \hideinitializer */
#define USBD_CLR_SE0() ((uint32_t)(USBD->PHYCTL |= USBD_PHYCTL_DPPUEN_Msk)) /*!<Disable SE0 \hideinitializer */
#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr)) /*!<Set USB address \hideinitializer */
#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR)) /*!<Get USB address \hideinitializer */
#define USBD_ENABLE_USB_INT(intr) (USBD->GINTEN = (intr)) /*!<Enable USB Interrupt \hideinitializer */
#define USBD_ENABLE_BUS_INT(intr) (USBD->BUSINTEN = (intr)) /*!<Enable BUS Interrupt \hideinitializer */
#define USBD_GET_BUS_INT_FLAG() (USBD->BUSINTSTS) /*!<Clear Bus interrupt flag \hideinitializer */
#define USBD_CLR_BUS_INT_FLAG(flag) (USBD->BUSINTSTS = flag) /*!<Clear Bus interrupt flag \hideinitializer */
#define USBD_ENABLE_CEP_INT(intr) (USBD->CEPINTEN = (intr)) /*!<Enable CEP Interrupt \hideinitializer */
#define USBD_CLR_CEP_INT_FLAG(flag) (USBD->CEPINTSTS = flag) /*!<Clear CEP interrupt flag \hideinitializer */
#define USBD_SET_CEP_STATE(flag) (USBD->CEPCTL = flag) /*!<Set CEP state \hideinitializer */
#define USBD_START_CEP_IN(size) (USBD->CEPTXCNT = size) /*!<Start CEP IN Transfer \hideinitializer */
#define USBD_SET_MAX_PAYLOAD(ep, size) (USBD->EP[ep].EPMPS = (size)) /*!<Set EPx Maximum Packet Size \hideinitializer */
#define USBD_ENABLE_EP_INT(ep, intr) (USBD->EP[ep].EPINTEN = (intr)) /*!<Enable EPx Interrupt \hideinitializer */
#define USBD_GET_EP_INT_FLAG(ep) (USBD->EP[ep].EPINTSTS) /*!<Get EPx interrupt flag \hideinitializer */
#define USBD_CLR_EP_INT_FLAG(ep, flag) (USBD->EP[ep].EPINTSTS = (flag)) /*!<Clear EPx interrupt flag \hideinitializer */
#define USBD_SET_DMA_LEN(len) (USBD->DMACNT = len) /*!<Set DMA transfer length \hideinitializer */
#define USBD_SET_DMA_ADDR(addr) (USBD->DMAADDR = addr) /*!<Set DMA transfer address \hideinitializer */
#define USBD_SET_DMA_READ(epnum) (USBD->DMACTL = (USBD->DMACTL & ~USBD_DMACTL_EPNUM_Msk) | USBD_DMACTL_DMARD_Msk | epnum | 0x100) /*!<Set DMA transfer type to read \hideinitializer */
#define USBD_SET_DMA_WRITE(epnum) (USBD->DMACTL = (USBD->DMACTL & ~(USBD_DMACTL_EPNUM_Msk | USBD_DMACTL_DMARD_Msk | 0x100)) | epnum) /*!<Set DMA transfer type to write \hideinitializer */
#define USBD_ENABLE_DMA() (USBD->DMACTL |= USBD_DMACTL_DMAEN_Msk) /*!<Enable DMA transfer \hideinitializer */
#define USBD_IS_ATTACHED() ((uint32_t)(USBD->PHYCTL & USBD_PHYCTL_VBUSDET_Msk)) /*!<Check cable connect state \hideinitializer */
/* Endpoint state */
struct usb_dc_ep_state {
/** Endpoint max packet size */
@@ -19,6 +52,7 @@ struct usb_dc_ep_state {
/* Driver state */
struct usb_dc_config_priv {
volatile uint8_t dev_addr;
volatile uint32_t bufaddr;
struct usb_dc_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/
struct usb_dc_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
} usb_dc_cfg;
@@ -36,6 +70,28 @@ int usb_dc_init(void)
memset(&usb_dc_cfg, 0, sizeof(struct usb_dc_config_priv));
usb_dc_low_level_init();
/* Enable PHY */
USBD_ENABLE_PHY();
/* wait PHY clock ready */
while (1) {
USBD->EP[0].EPMPS = 0x20;
if (USBD->EP[0].EPMPS == 0x20)
break;
}
#ifdef CONFIG_USB_HS
USBD->OPER |= USBD_OPER_HISPDEN_Msk; /* high-speed */
#else
USBD->OPER &= ~USBD_OPER_HISPDEN_Msk; /* full-speed */
#endif
/* Reset Address to 0 */
USBD_SET_ADDR(0);
USBD->CEPINTEN = USBD_CEPINTEN_SETUPPKIEN_Msk | USBD_CEPINTEN_TXPKIEN_Msk | USBD_CEPINTEN_RXPKIEN_Msk | USBD_CEPINTEN_STSDONEIEN_Msk;
/* Enable BUS interrupt */
USBD->BUSINTEN = USBD_BUSINTEN_RSTIEN_Msk | USBD_BUSINTEN_VBUSDETIEN_Msk;
/* Enable USB BUS, CEP and EPA global interrupt */
USBD->GINTEN = USBD_GINTEN_USBIE_Msk | USBD_GINTEN_CEPIE_Msk;
return 0;
}
@@ -45,20 +101,60 @@ void usb_dc_deinit(void)
int usbd_set_address(const uint8_t addr)
{
if (addr == 0x00) {
}
usb_dc_cfg.dev_addr = addr;
return 0;
}
int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
{
uint8_t ep_idx = USB_EP_GET_IDX(ep_cfg->ep_addr);
uint8_t ep_type;
uint8_t ep_dir;
uint32_t intr;
if (USB_EP_DIR_IS_OUT(ep_cfg->ep_addr)) {
ep_dir = USB_EP_CFG_DIR_OUT;
intr = USBD_EPINTEN_RXPKIEN_Msk;
usb_dc_cfg.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
usb_dc_cfg.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
} else {
ep_dir = USB_EP_CFG_DIR_IN;
intr = USBD_EPINTEN_TXPKIEN_Msk;
usb_dc_cfg.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
usb_dc_cfg.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
}
if (ep_idx == 0) {
/* Control endpoint */
USBD->CEPBUFSTART = usb_dc_cfg.bufaddr;
USBD->CEPBUFEND = usb_dc_cfg.bufaddr + 64 - 1;
usb_dc_cfg.bufaddr += 64;
return 0;
}
switch (ep_cfg->ep_type) {
case 0x01:
ep_type = USB_EP_CFG_TYPE_ISO;
USBD->EP[ep_idx - 1].EPRSPCTL = (USB_EP_RSPCTL_FLUSH | USB_EP_RSPCTL_MODE_FLY);
break;
case 0x02:
ep_type = USB_EP_CFG_TYPE_BULK;
USBD->EP[ep_idx - 1].EPRSPCTL = (USB_EP_RSPCTL_FLUSH | USB_EP_RSPCTL_MODE_AUTO);
break;
case 0x03:
ep_type = USB_EP_CFG_TYPE_INT;
USBD->EP[ep_idx - 1].EPRSPCTL = (USB_EP_RSPCTL_FLUSH | USB_EP_RSPCTL_MODE_MANUAL);
break;
}
USBD->EP[ep_idx - 1].EPBUFSTART = usb_dc_cfg.bufaddr;
USBD->EP[ep_idx - 1].EPBUFEND = usb_dc_cfg.bufaddr + ep_cfg->ep_mps - 1;
USBD->EP[ep_idx - 1].EPMPS = ep_cfg->ep_mps;
USBD->EP[ep_idx - 1].EPCFG = (ep_type | ep_dir | USB_EP_CFG_VALID | (ep_idx << 4));
USBD->EP[ep_idx - 1].EPINTEN = intr;
USBD->GINTEN |= (1 << (USBD_GINTEN_CEPIE_Pos + ep_idx));
usb_dc_cfg.bufaddr += ep_cfg->ep_mps;
return 0;
}
@@ -69,11 +165,25 @@ int usbd_ep_close(const uint8_t ep)
int usbd_ep_set_stall(const uint8_t ep)
{
uint8_t ep_idx = USB_EP_GET_IDX(ep);
if (ep_idx == 0x00) {
USBD_SET_CEP_STATE(USB_CEPCTL_STALL);
} else {
USBD->EP[ep_idx - 1].EPRSPCTL = (USBD->EP[ep_idx - 1].EPRSPCTL & 0xf7) | USB_EP_RSPCTL_HALT;
}
return 0;
}
int usbd_ep_clear_stall(const uint8_t ep)
{
uint8_t ep_idx = USB_EP_GET_IDX(ep);
if (ep_idx == 0x00) {
return 0;
}
USBD->EP[ep_idx - 1].EPRSPCTL = USB_EP_RSPCTL_TOGGLE;
return 0;
}
@@ -84,6 +194,11 @@ int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes)
{
uint32_t *buf32;
uint8_t buflen32;
uint8_t *buf8;
uint8_t buflen8;
uint8_t ep_idx = USB_EP_GET_IDX(ep);
if (!data && data_len) {
@@ -91,7 +206,11 @@ int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint
}
if (!data_len) {
if (ep_idx == 0x00) {
USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
} else {
USBD->EP[ep_idx - 1].EPRSPCTL = USB_EP_RSPCTL_ZEROLEN;
}
return 0;
}
@@ -99,6 +218,39 @@ int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint
data_len = usb_dc_cfg.in_ep[ep_idx].ep_mps;
}
buflen32 = data_len / 4;
buflen8 = data_len % 4;
buf32 = (uint32_t *)data;
if (ep_idx == 0x00) {
for (uint8_t i = 0; i < buflen32; i++) {
USBD->cep.CEPDAT = *buf32;
buf32++;
}
buf8 = (uint8_t *)buf32;
for (uint8_t i = 0; i < buflen8; i++) {
USBD->cep.CEPDAT_BYTE = *buf8;
buf8++;
}
USBD->CEPTXCNT = data_len;
USBD->CEPCTL = USB_CEPCTL_NAKCLR;
} else {
while (USBD->EP[ep_idx - 1].EPDATCNT != 0) {
}
for (uint8_t i = 0; i < buflen32; i++) {
USBD->EP[ep_idx - 1].ep.EPDAT = *buf32;
buf32++;
}
buf8 = (uint8_t *)buf32;
for (uint8_t i = 0; i < buflen8; i++) {
USBD->EP[ep_idx - 1].ep.EPDAT_BYTE = data[i];
buf8++;
}
USBD->EP[ep_idx - 1].EPTXCNT = data_len;
USBD->EP[ep_idx - 1].EPRSPCTL = USB_EP_RSPCTL_SHORTTXEN;
}
if (ret_bytes) {
*ret_bytes = data_len;
}
@@ -110,6 +262,10 @@ int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_
{
uint8_t ep_idx = USB_EP_GET_IDX(ep);
uint32_t read_count;
uint32_t *buf32;
uint8_t buflen32;
uint8_t *buf8;
uint8_t buflen8;
if (!data && max_data_len) {
return -1;
@@ -119,6 +275,38 @@ int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_
return 0;
}
if (ep_idx == 0x00) {
if (max_data_len == 0x08 && !read_bytes) {
*((uint16_t *)(data + 0)) = (uint16_t)(USBD->SETUP1_0 & 0xFFFFUL);
*((uint16_t *)(data + 2)) = (uint16_t)(USBD->SETUP3_2 & 0xFFFFUL);
*((uint16_t *)(data + 4)) = (uint16_t)(USBD->SETUP5_4 & 0xFFFFUL);
*((uint16_t *)(data + 6)) = (uint16_t)(USBD->SETUP7_6 & 0xFFFFUL);
} else {
read_count = USBD->CEPRXCNT & 0xFFFFUL;
read_count = MIN(read_count, max_data_len);
for (uint8_t i = 0; i < read_count; i++) {
data[i] = USBD->cep.CEPDAT_BYTE;
}
}
} else {
read_count = USBD->EP[ep_idx - 1].EPDATCNT & 0xFFFFUL;
read_count = MIN(read_count, max_data_len);
buflen32 = read_count / 4;
buflen8 = read_count % 4;
buf32 = (uint32_t *)data;
for (uint8_t i = 0; i < buflen32; i++) {
*buf32 = USBD->EP[ep_idx - 1].ep.EPDAT;
buf32++;
}
buf8 = (uint8_t *)buf32;
for (uint8_t i = 0; i < buflen8; i++) {
*buf8 = USBD->EP[ep_idx - 1].ep.EPDAT_BYTE;
buf8++;
}
}
if (read_bytes) {
*read_bytes = read_count;
}
@@ -133,5 +321,148 @@ int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_
*/
void USBD_IRQHandler(void)
{
volatile uint32_t IrqStL, IrqSt;
IrqStL = USBD->GINTSTS & USBD->GINTEN; /* get interrupt status */
if (!IrqStL)
return;
/* USB interrupt */
if (IrqStL & USBD_GINTSTS_USBIF_Msk) {
IrqSt = USBD->BUSINTSTS & USBD->BUSINTEN;
if (IrqSt & USBD_BUSINTSTS_SOFIF_Msk) {
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_SOFIF_Msk);
}
if (IrqSt & USBD_BUSINTSTS_RSTIF_Msk) {
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_RSTIF_Msk);
USBD->DMACNT = 0;
USBD->DMACTL = 0x80;
USBD->DMACTL = 0x00;
for (uint8_t i = 1; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
USBD->EP[i - 1].EPRSPCTL = USBD_EPRSPCTL_FLUSH_Msk;
}
USBD_SET_ADDR(0);
USBD_CLR_CEP_INT_FLAG(0x1ffc);
usb_dc_cfg.bufaddr = 0;
usbd_event_notify_handler(USBD_EVENT_RESET, NULL);
}
if (IrqSt & USBD_BUSINTSTS_RESUMEIF_Msk) {
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_RESUMEIF_Msk);
}
if (IrqSt & USBD_BUSINTSTS_SUSPENDIF_Msk) {
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_SUSPENDIF_Msk);
}
if (IrqSt & USBD_BUSINTSTS_HISPDIF_Msk) {
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_HISPDIF_Msk);
}
if (IrqSt & USBD_BUSINTSTS_DMADONEIF_Msk) {
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_DMADONEIF_Msk);
if (USBD->DMACTL & USBD_DMACTL_DMARD_Msk) {
}
}
if (IrqSt & USBD_BUSINTSTS_PHYCLKVLDIF_Msk)
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_PHYCLKVLDIF_Msk);
if (IrqSt & USBD_BUSINTSTS_VBUSDETIF_Msk) {
if (USBD_IS_ATTACHED()) {
/* USB Plug In */
USBD_ENABLE_USB();
} else {
/* USB Un-plug */
USBD_DISABLE_USB();
}
USBD_CLR_BUS_INT_FLAG(USBD_BUSINTSTS_VBUSDETIF_Msk);
}
}
if (IrqStL & USBD_GINTSTS_CEPIF_Msk) {
IrqSt = USBD->CEPINTSTS & USBD->CEPINTEN;
if (IrqSt & USBD_CEPINTSTS_SETUPTKIF_Msk) {
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_SETUPTKIF_Msk);
return;
}
if (IrqSt & USBD_CEPINTSTS_OUTTKIF_Msk) {
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_OUTTKIF_Msk);
return;
}
if (IrqSt & USBD_CEPINTSTS_INTKIF_Msk) {
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_INTKIF_Msk);
return;
}
if (IrqSt & USBD_CEPINTSTS_PINGIF_Msk) {
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_PINGIF_Msk);
return;
}
if (IrqSt & USBD_CEPINTSTS_SETUPPKIF_Msk) {
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_SETUPPKIF_Msk);
usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
return;
}
if (IrqSt & USBD_CEPINTSTS_TXPKIF_Msk) {
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_TXPKIF_Msk);
usbd_event_notify_handler(USBD_EVENT_EP0_IN_NOTIFY, NULL);
return;
}
if (IrqSt & USBD_CEPINTSTS_RXPKIF_Msk) {
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_RXPKIF_Msk);
usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
return;
}
if (IrqSt & USBD_CEPINTSTS_NAKIF_Msk) {
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_NAKIF_Msk);
return;
}
if (IrqSt & USBD_CEPINTSTS_STALLIF_Msk) {
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STALLIF_Msk);
return;
}
if (IrqSt & USBD_CEPINTSTS_ERRIF_Msk) {
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_ERRIF_Msk);
return;
}
if (IrqSt & USBD_CEPINTSTS_STSDONEIF_Msk) {
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STSDONEIF_Msk);
if (usb_dc_cfg.dev_addr > 0) {
USBD_SET_ADDR(usb_dc_cfg.dev_addr);
usb_dc_cfg.dev_addr = 0;
}
return;
}
if (IrqSt & USBD_CEPINTSTS_BUFFULLIF_Msk) {
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_BUFFULLIF_Msk);
return;
}
if (IrqSt & USBD_CEPINTSTS_BUFEMPTYIF_Msk) {
USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_BUFEMPTYIF_Msk);
return;
}
}
for (uint8_t ep_idx = 1; ep_idx < USB_NUM_BIDIR_ENDPOINTS; ep_idx++) {
if (IrqStL & (0x1UL << (USBD_GINTSTS_CEPIF_Pos + ep_idx))) {
IrqSt = USBD->EP[ep_idx - 1].EPINTSTS & USBD->EP[ep_idx - 1].EPINTEN;
USBD_CLR_EP_INT_FLAG(ep_idx - 1, IrqSt);
if (usb_dc_cfg.in_ep[ep_idx].ep_mps) {
usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(0x80 | ep_idx));
} else if (usb_dc_cfg.out_ep[ep_idx].ep_mps) {
usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(ep_idx & 0x7f));
}
}
}
}

29
port/nuvoton/usb_nuvoton_reg.h
View File

@@ -510,4 +510,31 @@ typedef struct
#define USBD_PHYCTL_VBUSDET_Pos (31) /*!< USBD PHYCTL: VBUSDET Position */
#define USBD_PHYCTL_VBUSDET_Msk (0x1ul << USBD_PHYCTL_VBUSDET_Pos) /*!< USBD PHYCTL: VBUSDET Mask */
#endif
/********************* Bit definition of CEPCTL register **********************/
#define USB_CEPCTL_NAKCLR ((uint32_t)0x00000000) /*!<NAK clear \hideinitializer */
#define USB_CEPCTL_STALL ((uint32_t)0x00000002) /*!<Stall \hideinitializer */
#define USB_CEPCTL_ZEROLEN ((uint32_t)0x00000004) /*!<Zero length packet \hideinitializer */
#define USB_CEPCTL_FLUSH ((uint32_t)0x00000008) /*!<CEP flush \hideinitializer */
/********************* Bit definition of EPxRSPCTL register **********************/
#define USB_EP_RSPCTL_FLUSH ((uint32_t)0x00000001) /*!<Buffer Flush \hideinitializer */
#define USB_EP_RSPCTL_MODE_AUTO ((uint32_t)0x00000000) /*!<Auto-Validate Mode \hideinitializer */
#define USB_EP_RSPCTL_MODE_MANUAL ((uint32_t)0x00000002) /*!<Manual-Validate Mode \hideinitializer */
#define USB_EP_RSPCTL_MODE_FLY ((uint32_t)0x00000004) /*!<Fly Mode \hideinitializer */
#define USB_EP_RSPCTL_MODE_MASK ((uint32_t)0x00000006) /*!<Mode Mask \hideinitializer */
#define USB_EP_RSPCTL_TOGGLE ((uint32_t)0x00000008) /*!<Clear Toggle bit \hideinitializer */
#define USB_EP_RSPCTL_HALT ((uint32_t)0x00000010) /*!<Endpoint halt \hideinitializer */
#define USB_EP_RSPCTL_ZEROLEN ((uint32_t)0x00000020) /*!<Zero length packet IN \hideinitializer */
#define USB_EP_RSPCTL_SHORTTXEN ((uint32_t)0x00000040) /*!<Packet end \hideinitializer */
#define USB_EP_RSPCTL_DISBUF ((uint32_t)0x00000080) /*!<Disable buffer \hideinitializer */
/********************* Bit definition of EPxCFG register **********************/
#define USB_EP_CFG_VALID ((uint32_t)0x00000001) /*!<Endpoint Valid \hideinitializer */
#define USB_EP_CFG_TYPE_BULK ((uint32_t)0x00000002) /*!<Endpoint type - bulk \hideinitializer */
#define USB_EP_CFG_TYPE_INT ((uint32_t)0x00000004) /*!<Endpoint type - interrupt \hideinitializer */
#define USB_EP_CFG_TYPE_ISO ((uint32_t)0x00000006) /*!<Endpoint type - isochronous \hideinitializer */
#define USB_EP_CFG_TYPE_MASK ((uint32_t)0x00000006) /*!<Endpoint type mask \hideinitializer */
#define USB_EP_CFG_DIR_OUT ((uint32_t)0x00000000) /*!<OUT endpoint \hideinitializer */
#define USB_EP_CFG_DIR_IN ((uint32_t)0x00000008) /*!<IN endpoint \hideinitializer */
#endif