Fix esp32-p4 cache operation adaptation issue
This commit is contained in:
@@ -1,6 +1,6 @@
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cmake_minimum_required(VERSION 3.15)
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cmake_minimum_required(VERSION 3.15)
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if(CONFIG_CHERRYUSB)
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if(CONFIG_CHERRYUSB OR ESP_PLATFORM)
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if(BL_SDK_BASE)
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if(BL_SDK_BASE)
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message(STATUS "enable cherryusb in bouffalo_sdk")
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message(STATUS "enable cherryusb in bouffalo_sdk")
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@@ -71,7 +71,7 @@ elseif(ESP_PLATFORM)
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${cherryusb_incs}
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${cherryusb_incs}
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${freertos_include}
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${freertos_include}
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PRIV_REQUIRES
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PRIV_REQUIRES
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usb
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usb esp_mm
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LDFRAGMENTS
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LDFRAGMENTS
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${ldfragments}
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${ldfragments}
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)
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)
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@@ -8,6 +8,7 @@
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#include "sdkconfig.h"
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#include "sdkconfig.h"
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#include "esp_rom_sys.h"
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#include "esp_rom_sys.h"
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#include "esp_attr.h"
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/* ================ USB common Configuration ================ */
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/* ================ USB common Configuration ================ */
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@@ -28,7 +29,7 @@
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// #define CONFIG_USB_DCACHE_ENABLE
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// #define CONFIG_USB_DCACHE_ENABLE
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/* attribute data into no cache ram */
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/* attribute data into no cache ram */
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#define USB_NOCACHE_RAM_SECTION
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#define USB_NOCACHE_RAM_SECTION DRAM_DMA_ALIGNED_ATTR
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/* use usb_memcpy default for high performance but cost more flash memory.
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/* use usb_memcpy default for high performance but cost more flash memory.
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* And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4.
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* And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4.
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@@ -340,9 +341,6 @@
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#define CONFIG_USB_DCACHE_ENABLE
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#define CONFIG_USB_DCACHE_ENABLE
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#undef CONFIG_USB_ALIGN_SIZE
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#undef CONFIG_USB_ALIGN_SIZE
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#define CONFIG_USB_ALIGN_SIZE 32
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#define CONFIG_USB_ALIGN_SIZE CONFIG_CACHE_L1_CACHE_LINE_SIZE
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void usb_dcache_clean(uintptr_t addr, uint32_t size);
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void usb_dcache_invalidate(uintptr_t addr, uint32_t size);
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void usb_dcache_flush(uintptr_t addr, uint32_t size);
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#endif
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#endif
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