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Add PUSB2 and XHCI driver and RTOS glue (#236)

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This commit is contained in:
zhugengyu
2024-08-09 22:43:22 +08:00
committed by GitHub
parent cbd6955bde
commit 18d9c21553
36 changed files with 2725 additions and 1170 deletions
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31
SConscript
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@@ -15,6 +15,8 @@ path += [cwd + '/class/vendor/net']
path += [cwd + '/class/vendor/serial']
src = []
LIBS = []
LIBPATH = []
CPPDEFINES = []
# USB DEVICE
@@ -68,6 +70,15 @@ if GetDepend(['PKG_CHERRYUSB_DEVICE']):
src += Glob('port/ch32/usb_dc_usbhs.c')
else:
src += Glob('port/ch32/usb_dc_usbfs.c')
if GetDepend(['PKG_CHERRYUSB_DEVICE_PUSB2']):
path += [cwd + '/port/xhci/rt-thread']
src += Glob('port/pusb2/rt-thread/usb_dc_glue_phytium.c')
if GetDepend(['ARCH_ARMV8']):
LIBPATH = [cwd + '/port/pusb2']
LIBS = ['libpusb2_dc_a64.a']
if GetDepend(['ARCH_ARM_CORTEX_A']):
LIBPATH = [cwd + '/port/pusb2']
LIBS = ['libpusb2_dc_a32_softfp_neon.a']
if GetDepend(['PKG_CHERRYUSB_DEVICE_CDC_ACM']):
src += Glob('class/cdc/usbd_cdc.c')
@@ -169,6 +180,26 @@ if GetDepend(['PKG_CHERRYUSB_HOST']):
src += Glob('port/musb/usb_glue_bk.c')
if GetDepend(['PKG_CHERRYUSB_HOST_MUSB_CUSTOM']):
src += Glob('port/musb/usb_hc_musb.c')
if GetDepend(['PKG_CHERRYUSB_HOST_PUSB2']):
path += [cwd + '/port/pusb2/rt-thread']
src += Glob('port/pusb2/rt-thread/usb_hc_glue_phytium.c')
if GetDepend(['ARCH_ARMV8']):
LIBPATH = [cwd + '/port/pusb2']
LIBS = ['libpusb2_hc_a64.a']
if GetDepend(['ARCH_ARM_CORTEX_A']):
LIBPATH = [cwd + '/port/pusb2']
LIBS = ['libpusb2_hc_a32_softfp_neon.a']
if GetDepend(['PKG_CHERRYUSB_HOST_XHCI']):
path += [cwd + '/port/xhci/phytium/rt-thread']
src += Glob('port/xhci/phytium/rt-thread/usb_glue_phytium_plat.c')
src += Glob('port/xhci/phytium/rt-thread/usb_glue_phytium.c')
if GetDepend(['ARCH_ARMV8']):
LIBPATH = [cwd + '/port/xhci/phytium']
LIBS = ['libxhci_a64.a']
if GetDepend(['ARCH_ARM_CORTEX_A']):
LIBPATH = [cwd + '/port/xhci/phytium']
LIBS = ['libxhci_a32_softfp_neon.a']
if GetDepend(['PKG_CHERRYUSB_HOST_CDC_ACM']):
src += Glob('class/cdc/usbh_cdc_acm.c')

2
core/usbd_core.c
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@@ -1374,7 +1374,7 @@ int usbd_send_remote_wakeup(uint8_t busid)
}
}
int usbd_initialize(uint8_t busid, uint32_t reg_base, void (*event_handler)(uint8_t busid, uint8_t event))
int usbd_initialize(uint8_t busid, uintptr_t reg_base, void (*event_handler)(uint8_t busid, uint8_t event))
{
int ret;
struct usbd_bus *bus;

4
core/usbd_core.h
View File

@@ -77,7 +77,7 @@ struct usb_descriptor {
struct usbd_bus {
uint8_t busid;
uint32_t reg_base;
uintptr_t reg_base;
};
extern struct usbd_bus g_usbdev_bus[];
@@ -104,7 +104,7 @@ uint8_t usbd_get_ep_mult(uint8_t busid, uint8_t ep);
bool usb_device_is_configured(uint8_t busid);
int usbd_send_remote_wakeup(uint8_t busid);
int usbd_initialize(uint8_t busid, uint32_t reg_base, void (*event_handler)(uint8_t busid, uint8_t event));
int usbd_initialize(uint8_t busid, uintptr_t reg_base, void (*event_handler)(uint8_t busid, uint8_t event));
int usbd_deinitialize(uint8_t busid);
#ifdef __cplusplus

4
core/usbh_core.c
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@@ -600,7 +600,7 @@ void usbh_hubport_release(struct usbh_hubport *hport)
}
}
static void usbh_bus_init(struct usbh_bus *bus, uint8_t busid, uint32_t reg_base)
static void usbh_bus_init(struct usbh_bus *bus, uint8_t busid, uintptr_t reg_base)
{
memset(bus, 0, sizeof(struct usbh_bus));
bus->busid = busid;
@@ -613,7 +613,7 @@ static void usbh_bus_init(struct usbh_bus *bus, uint8_t busid, uint32_t reg_base
usb_slist_add_tail(&g_bus_head, &bus->list);
}
int usbh_initialize(uint8_t busid, uint32_t reg_base)
int usbh_initialize(uint8_t busid, uintptr_t reg_base)
{
struct usbh_bus *bus;

4
core/usbh_core.h
View File

@@ -153,7 +153,7 @@ struct usbh_devaddr_map {
};
struct usbh_hcd {
uint32_t reg_base;
uintptr_t reg_base;
uint8_t hcd_id;
uint8_t roothub_intbuf[2]; /* at most 15 roothub ports */
struct usbh_hub roothub;
@@ -271,7 +271,7 @@ int usbh_get_string_desc(struct usbh_hubport *hport, uint8_t index, uint8_t *out
*/
int usbh_set_interface(struct usbh_hubport *hport, uint8_t intf, uint8_t altsetting);
int usbh_initialize(uint8_t busid, uint32_t reg_base);
int usbh_initialize(uint8_t busid, uintptr_t reg_base);
int usbh_deinitialize(uint8_t busid);
void *usbh_find_class_instance(const char *devname);

69
port/pusb2/README.md
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@@ -1,7 +1,66 @@
# USB2.0 OTG 控制器 (PUSB2)
# USB 2.0 OTG 控制器 (PUSB2)
- Phytium PI 和 Phyium E2000 系列开发板提供了兼容 USB2.0 的 OTG 接口
- 当前 Port 在 [RT-Thread](https://github.com/RT-Thread/rt-thread/tree/master/bsp/phytium) 上完成测试，具体使用方法参考 RT-Thread Phytium BSP 中的说明
- usb_dc_pusb2.c 主要实现 Device 模式，测试过 msc_ram_template.c 和 cdc_acm_template.c 两个 Demo
- usb_hc_pusb2.c 主要实现 Host 模式，测试过 usb_host.c，可以连接 USB Disk, HID 设备鼠标和键盘
- PUSB2 的驱动代码欢迎联系 `opensource_embedded@phytium.com.cn` 获取
- 相关的使用例程可以在 Phytium PI（飞腾派）和 E2000 D/Q Demo 板上运行，例程包括
---------------------------------------------
- Host 模式
- - 1. [FreeRTOS 上作为主机使用键盘/鼠标/U盘](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_host/README.md)
- - 5. [RT-Thread 上作为主机识别键盘/鼠标/U盘](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md)
---------------------------------------------
- Device 模式
- - 1. [裸机上模拟为一个 U 盘](https://gitee.com/phytium_embedded/phytium-standalone-sdk/tree/master/example/peripherals/usb/pusb2_device/README.md)
- - 2. [裸机上模拟为一个虚拟串口](https://gitee.com/phytium_embedded/phytium-standalone-sdk/tree/master/example/peripherals/usb/pusb2_device/README.md)
- - 3. [FreeRTOS 上模拟为一个 U 盘](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_device/README.md)
- - 4. [FreeRTOS 上模拟为虚拟串口](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_device/README.md)
- - 5. [RT-Thread 上模拟为一个 U 盘](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md)
---------------------------------------------
- PUSB2 的驱动功能以静态库的方式提供，
- - libpusb2_hc_a64.a : AARCH64 主机模式驱动库
- - libpusb2_dc_a64.a : AARCH64 从机模式驱动库
- - libpusb2_hc_a32_hardfp.a ：AARCH32 主机模式驱动库，使用硬浮点
- - libpusb2_hc_a32_softfp.a ：AARCH32 主机模式驱动库，使用软浮点
- - libpusb2_dc_a32_hardfp.a ：AARCH32 从机模式驱动库，使用硬浮点
- - libpusb2_dc_a32_softfp.a ：AARCH32 从机模式驱动库，使用软浮点
需要获取源代码请联系 `opensource_embedded@phytium.com.cn` 获取
# USB 2.0 OTG Controller (PUSB2)
- Phytium PI and the Phytium E2000 series development boards offer OTG interfaces compatible with USB 2.0.
- Relevant usage examples can be run on the Phytium PI and E2000 D/Q Demo boards, including:
---------------------------------------------
- Host Mode
- 1. [Using a keyboard/mouse/USB flash drive as a host on FreeRTOS](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_host/README.md)
- 5. [Recognizing a keyboard/mouse/USB flash drive as a host on RT-Thread](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md)
---------------------------------------------
- Device Mode
- 1. [Simulating as a USB flash drive on a standalone system](https://gitee.com/phytium_embedded/phytium-standalone-sdk/tree/master/example/peripherals/usb/pusb2_device/README.md)
- 2. [Simulating as a virtual serial port on a standalone system](https://gitee.com/phytium_embedded/phytium-standalone-sdk/tree/master/example/peripherals/usb/pusb2_device/README.md)
- 3. [Simulating as a USB flash drive on FreeRTOS](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_device/README.md)
- 4. [Simulating as a virtual serial port on FreeRTOS](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/pusb2_device/README.md)
- 5. [Simulating as a USB flash drive on RT-Thread](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md)
---------------------------------------------
- The driver functionality of PUSB2 is provided as static libraries:
- - `libpusb2_hc_a64.a` : Host mode driver library for AARCH64
- - `libpusb2_dc_a64.a` : Device mode driver library for AARCH64
- - `libpusb2_hc_a32_hardfp.a` : Host mode driver library for AARCH32, using hard floating point
- - `libpusb2_hc_a32_softfp.a` : Host mode driver library for AARCH32, using soft floating point
- - `libpusb2_dc_a32_hardfp.a` : Device mode driver library for AARCH32, using hard floating point
- - `libpusb2_dc_a32_softfp.a` : Device mode driver library for AARCH32, using soft floating point
- To obtain the source code, please contact `opensource_embedded@phytium.com.cn`.

284
port/pusb2/freertos/usb_config.h Normal file
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@@ -0,0 +1,284 @@
/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
#ifndef CHERRYUSB_CONFIG_H
#define CHERRYUSB_CONFIG_H
#include "sdkconfig.h"
#include "FreeRTOS.h"
#include "task.h"
#define CHERRYUSB_VERSION 0x010400
#define CHERRYUSB_VERSION_STR "v1.4.0"
/* ================ USB common Configuration ================ */
#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__)
int xPortIsInsideInterrupt(void);
void *usb_sys_mem_malloc(size_t size);
void usb_sys_mem_free(void *ptr);
void *usb_sys_malloc_align(size_t align, size_t size);
#define usb_malloc(size) usb_sys_mem_malloc(size)
#define usb_free(ptr) usb_sys_mem_free(ptr)
#define usb_align(align, size) usb_sys_malloc_align(align, size)
unsigned long usb_hc_get_register_base(uint32_t id);
unsigned long usb_dc_get_register_base(uint32_t id);
#ifndef CONFIG_USB_DBG_LEVEL
#if defined(CONFIG_LOG_ERROR)
#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR
#elif defined(CONFIG_LOG_WARN)
#define CONFIG_USB_DBG_LEVEL USB_DBG_WARNING
#elif defined(CONFIG_LOG_INFO)
#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO
#elif defined(CONFIG_LOG_DEBUG) || defined(CONFIG_LOG_VERBOS)
#define CONFIG_USB_DBG_LEVEL USB_DBG_LOG
#else
#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR
#endif
#endif
/* Enable print with color */
#define CONFIG_USB_PRINTF_COLOR_ENABLE
/* data align size when use dma */
#ifndef CONFIG_USB_ALIGN_SIZE
#define CONFIG_USB_ALIGN_SIZE 4
#endif
/* attribute data into no cache ram */
#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable")))
/* ================= USB Device Stack Configuration ================ */
/* Ep0 in and out transfer buffer */
#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN
#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512
#endif
/* Setup packet log for debug */
// #define CONFIG_USBDEV_SETUP_LOG_PRINT
/* Send ep0 in data from user buffer instead of copying into ep0 reqdata
* Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE
*/
// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY
/* Check if the input descriptor is correct */
// #define CONFIG_USBDEV_DESC_CHECK
/* Enable test mode */
// #define CONFIG_USBDEV_TEST_MODE
#ifndef CONFIG_USBDEV_MSC_MAX_LUN
#define CONFIG_USBDEV_MSC_MAX_LUN 1
#endif
#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE
#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 4096
#endif
#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING
#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING ""
#endif
#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING
#define CONFIG_USBDEV_MSC_PRODUCT_STRING ""
#endif
#ifndef CONFIG_USBDEV_MSC_VERSION_STRING
#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01"
#endif
// #define CONFIG_USBDEV_MSC_THREAD
#ifndef CONFIG_USBDEV_MSC_PRIO
#define CONFIG_USBDEV_MSC_PRIO 4
#endif
#ifndef CONFIG_USBDEV_MSC_STACKSIZE
#define CONFIG_USBDEV_MSC_STACKSIZE 2048
#endif
#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE
#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
#endif
/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/
#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE
#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580
#endif
#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID
#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff
#endif
#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC
#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB"
#endif
#define CONFIG_USBDEV_RNDIS_USING_LWIP
/* ================ USB HOST Stack Configuration ================== */
#define CONFIG_USBHOST_MAX_RHPORTS 1
#define CONFIG_USBHOST_MAX_EXTHUBS 0
#define CONFIG_USBHOST_MAX_EHPORTS 8
#define CONFIG_USBHOST_MAX_INTERFACES 8
#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8
#define CONFIG_USBHOST_MAX_ENDPOINTS 8
#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4
#define CONFIG_USBHOST_MAX_HID_CLASS 4
#define CONFIG_USBHOST_MAX_MSC_CLASS 2
#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1
#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1
#define CONFIG_USBHOST_DEV_NAMELEN 16
#ifndef CONFIG_USBHOST_PSC_PRIO
#define CONFIG_USBHOST_PSC_PRIO 0
#endif
#ifndef CONFIG_USBHOST_PSC_STACKSIZE
#define CONFIG_USBHOST_PSC_STACKSIZE 8192
#endif
//#define CONFIG_USBHOST_GET_STRING_DESC
// #define CONFIG_USBHOST_MSOS_ENABLE
#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE
#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00
#endif
/* Ep0 max transfer buffer */
#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN
#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512
#endif
#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT
#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500
#endif
#ifndef CONFIG_USBHOST_MSC_TIMEOUT
#define CONFIG_USBHOST_MSC_TIMEOUT 5000
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048)
#endif
#define CONFIG_USBHOST_BLUETOOTH_HCI_H4
// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG
#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE
#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048
#endif
#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE
#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048
#endif
/* ================ USB Device Port Configuration ================*/
#ifndef CONFIG_USBDEV_MAX_BUS
#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip
#endif
#ifndef CONFIG_USBDEV_EP_NUM
#define CONFIG_USBDEV_EP_NUM 8
#endif
/* ---------------- FSDEV Configuration ---------------- */
//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference
/* ---------------- DWC2 Configuration ---------------- */
/* (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for
* status information) + (2 * number of OUT endpoints) + 1 for Global NAK
*/
// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
/* IN Endpoints Max packet Size / 4 */
// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4)
// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
/* ---------------- MUSB Configuration ---------------- */
// #define CONFIG_USB_MUSB_SUNXI
/* ================ USB Host Port Configuration ==================*/
#ifndef CONFIG_INPUT_MOUSE_WHEEL
#define CONFIG_INPUT_MOUSE_WHEEL
#endif
#ifndef CONFIG_USBHOST_MAX_BUS
#define CONFIG_USBHOST_MAX_BUS 3
#endif
#ifndef CONFIG_USBHOST_PIPE_NUM
#define CONFIG_USBHOST_PIPE_NUM 10
#endif
/* ---------------- XHCI Configuration ---------------- */
#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0)
/* ---------------- PUSB2 Configuration ---------------- */
#define CONFIG_USB_PUSB2_BUS_NUM 3U
#define CONFIG_USB_PUSB2_BUS_ID 0U
#endif

141
port/pusb2/freertos/usb_dc_glue_phytium.c Normal file
View File

@@ -0,0 +1,141 @@
/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
/***************************** Include Files *********************************/
#include <stdio.h>
#include <string.h>
#include "fassert.h"
#include "fparameters.h"
#include "finterrupt.h"
#include "fcpu_info.h"
#include "fdebug.h"
#include "fcache.h"
#include "fmemory_pool.h"
#include "usbd_core.h"
/************************** Constant Definitions *****************************/
#define USB_MEMP_TOTAL_SIZE SZ_1M
/**************************** Type Definitions *******************************/
void USBD_IRQHandler(uint8_t busid);
/************************** Variable Definitions *****************************/
static FMemp memp;
static u8 memp_buf[USB_MEMP_TOTAL_SIZE] __attribute__((aligned(8))) = {0};
void usb_sys_mem_init(void)
{
if (FT_COMPONENT_IS_READY != memp.is_ready)
{
USB_ASSERT(FT_SUCCESS == FMempInit(&memp, &memp_buf[0], &memp_buf[0] + USB_MEMP_TOTAL_SIZE));
}
}
void usb_sys_mem_deinit(void)
{
if (FT_COMPONENT_IS_READY == memp.is_ready)
{
FMempDeinit(&memp);
}
}
void *usb_sys_malloc_align(size_t align, size_t size)
{
void *result = FMempMallocAlign(&memp, size, align);
if (result)
{
memset(result, 0U, size);
}
return result;
}
void *usb_sys_mem_malloc(size_t size)
{
return usb_sys_malloc_align(sizeof(void *), size);
}
void usb_sys_mem_free(void *ptr)
{
if (NULL != ptr)
{
FMempFree(&memp, ptr);
}
}
void usb_assert(const char *filename, int linenum)
{
FAssert(filename, linenum, 0xff);
}
static void usb_dc_pusb2_interrupt_handler(s32 vector, void *param)
{
USBD_IRQHandler(CONFIG_USB_PUSB2_BUS_ID);
}
static void usb_dc_setup_pusb2_interrupt(u32 id)
{
u32 cpu_id;
USB_ASSERT(id == FUSB2_ID_VHUB_0);
u32 irq_num = FUSB2_0_VHUB_IRQ_NUM;
u32 irq_priority = 13U;
GetCpuId(&cpu_id);
InterruptSetTargetCpus(irq_num, cpu_id);
InterruptSetPriority(irq_num, irq_priority);
/* register intr callback */
InterruptInstall(irq_num,
usb_dc_pusb2_interrupt_handler,
NULL,
NULL);
/* enable irq */
InterruptUmask(irq_num);
}
static void usb_dc_revoke_pusb2_interrupt(u32 id)
{
USB_ASSERT(id == FUSB2_ID_VHUB_0);
u32 irq_num = FUSB2_0_VHUB_IRQ_NUM;
/* disable irq */
InterruptMask(irq_num);
}
extern int vApplicationInIrq(void);
int xPortIsInsideInterrupt(void)
{
return vApplicationInIrq();
}
unsigned long usb_dc_get_register_base(uint32_t id)
{
USB_ASSERT(id == FUSB2_ID_VHUB_0);
return FUSB2_0_VHUB_BASE_ADDR;
}
/* implement cherryusb weak functions */
void usb_dc_low_level_init()
{
usb_sys_mem_init();
usb_dc_setup_pusb2_interrupt(CONFIG_USB_PUSB2_BUS_ID);
}
void usb_dc_low_level_deinit(void)
{
usb_dc_revoke_pusb2_interrupt(CONFIG_USB_PUSB2_BUS_ID);
usb_sys_mem_deinit();
}

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/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
/***************************** Include Files *********************************/
#include <stdio.h>
#include <string.h>
#include "fassert.h"
#include "fparameters.h"
#include "finterrupt.h"
#include "fcpu_info.h"
#include "fdebug.h"
#include "fcache.h"
#include "fmemory_pool.h"
#include "usbh_core.h"
/************************** Constant Definitions *****************************/
#define USB_MEMP_TOTAL_SIZE SZ_1M
/**************************** Type Definitions *******************************/
void USBH_IRQHandler(uint8_t busid);
/************************** Variable Definitions *****************************/
static FMemp memp;
static u8 memp_buf[USB_MEMP_TOTAL_SIZE] __attribute__((aligned(8))) = {0};
static u32 memp_ref_cnt = 0;
static const u32 irq_nums[] = {
FUSB2_0_VHUB_IRQ_NUM, FUSB2_1_IRQ_NUM, FUSB2_2_IRQ_NUM
};
void usb_sys_mem_init(void)
{
if (FT_COMPONENT_IS_READY != memp.is_ready)
{
USB_ASSERT(FT_SUCCESS == FMempInit(&memp, &memp_buf[0], &memp_buf[0] + USB_MEMP_TOTAL_SIZE));
}
}
void usb_sys_mem_deinit(void)
{
if (FT_COMPONENT_IS_READY == memp.is_ready)
{
FMempDeinit(&memp);
}
}
void *usb_sys_malloc_align(size_t align, size_t size)
{
void *result = FMempMallocAlign(&memp, size, align);
if (result)
{
memset(result, 0U, size);
}
return result;
}
void *usb_sys_mem_malloc(size_t size)
{
return usb_sys_malloc_align(sizeof(void *), size);
}
void usb_sys_mem_free(void *ptr)
{
if (NULL != ptr)
{
FMempFree(&memp, ptr);
}
}
void usb_assert(const char *filename, int linenum)
{
FAssert(filename, linenum, 0xff);
}
static void usb_hc_pusb2_interrupt_handler(s32 vector, void *param)
{
if (vector == FUSB2_0_VHUB_IRQ_NUM) {
USBH_IRQHandler(FUSB2_ID_VHUB_0);
} else if (vector == FUSB2_1_IRQ_NUM) {
USBH_IRQHandler(FUSB2_ID_1);
} else if (vector == FUSB2_2_IRQ_NUM) {
USBH_IRQHandler(FUSB2_ID_2);
}
}
static void usb_hc_setup_pusb2_interrupt(u32 id)
{
u32 cpu_id;
u32 irq_num = irq_nums[id];
u32 irq_priority = 13U;
GetCpuId(&cpu_id);
InterruptSetTargetCpus(irq_num, cpu_id);
InterruptSetPriority(irq_num, irq_priority);
/* register intr callback */
InterruptInstall(irq_num,
usb_hc_pusb2_interrupt_handler,
NULL,
NULL);
/* enable irq */
InterruptUmask(irq_num);
USB_LOG_DBG("Enable irq-%d\n", irq_num);
}
static void usb_hc_revoke_pusb2_interrupt(u32 id)
{
u32 irq_num = irq_nums[id];
/* disable irq */
InterruptMask(irq_num);
}
void usb_hc_low_level_init(struct usbh_bus *bus)
{
if (memp_ref_cnt == 0) {
usb_sys_mem_init(); /* create memory pool before first bus init */
}
memp_ref_cnt++; /* one more bus is using the memory pool */
usb_hc_setup_pusb2_interrupt(bus->busid);
}
void usb_hc_low_level_deinit(struct usbh_bus *bus)
{
memp_ref_cnt--; /* one more bus is leaving */
if (memp_ref_cnt == 0) {
usb_sys_mem_deinit(); /* release memory pool after the last bus left */
}
usb_hc_revoke_pusb2_interrupt(bus->busid);
}
unsigned long usb_hc_get_register_base(uint32_t id)
{
if (id == FUSB2_ID_VHUB_0) {
return FUSB2_0_VHUB_BASE_ADDR;
} else if (id == FUSB2_ID_1) {
return FUSB2_1_BASE_ADDR;
} else if (id == FUSB2_ID_2) {
return FUSB2_2_BASE_ADDR;
}
}
extern int vApplicationInIrq(void);
int xPortIsInsideInterrupt(void)
{
return vApplicationInIrq();
}

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/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
#ifndef CHERRYUSB_CONFIG_H
#define CHERRYUSB_CONFIG_H
#include "rtconfig.h"
#define CHERRYUSB_VERSION 0x010400
#define CHERRYUSB_VERSION_STR "v1.4.0"
/* ================ USB common Configuration ================ */
#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__)
void *usb_sys_mem_malloc(size_t size);
void usb_sys_mem_free(void *ptr);
void *usb_sys_malloc_align(size_t align, size_t size);
#define usb_malloc(size) usb_sys_mem_malloc(size)
#define usb_free(ptr) usb_sys_mem_free(ptr)
#define usb_align(align, size) usb_sys_malloc_align(align, size)
unsigned long usb_hc_get_register_base(uint32_t id);
unsigned long usb_dc_get_register_base(uint32_t id);
#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR
/* Enable print with color */
#define CONFIG_USB_PRINTF_COLOR_ENABLE
/* data align size when use dma */
#ifndef CONFIG_USB_ALIGN_SIZE
#define CONFIG_USB_ALIGN_SIZE 4
#endif
/* attribute data into no cache ram */
#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable")))
/* ================= USB Device Stack Configuration ================ */
/* Ep0 in and out transfer buffer */
#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN
#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512
#endif
/* Setup packet log for debug */
// #define CONFIG_USBDEV_SETUP_LOG_PRINT
/* Send ep0 in data from user buffer instead of copying into ep0 reqdata
* Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE
*/
// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY
/* Check if the input descriptor is correct */
// #define CONFIG_USBDEV_DESC_CHECK
/* Enable test mode */
// #define CONFIG_USBDEV_TEST_MODE
#ifndef CONFIG_USBDEV_MSC_MAX_LUN
#define CONFIG_USBDEV_MSC_MAX_LUN 1
#endif
#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE
#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 4096
#endif
#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING
#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING ""
#endif
#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING
#define CONFIG_USBDEV_MSC_PRODUCT_STRING ""
#endif
#ifndef CONFIG_USBDEV_MSC_VERSION_STRING
#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01"
#endif
// #define CONFIG_USBDEV_MSC_THREAD
#ifndef CONFIG_USBDEV_MSC_PRIO
#define CONFIG_USBDEV_MSC_PRIO 4
#endif
#ifndef CONFIG_USBDEV_MSC_STACKSIZE
#define CONFIG_USBDEV_MSC_STACKSIZE 8192
#endif
#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE
#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
#endif
/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/
#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE
#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580
#endif
#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID
#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff
#endif
#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC
#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB"
#endif
#define CONFIG_USBDEV_RNDIS_USING_LWIP
/* ================ USB HOST Stack Configuration ================== */
#define CONFIG_USBHOST_MAX_RHPORTS 1
#define CONFIG_USBHOST_MAX_EXTHUBS 0
#define CONFIG_USBHOST_MAX_EHPORTS 8
#define CONFIG_USBHOST_MAX_INTERFACES 8
#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8
#define CONFIG_USBHOST_MAX_ENDPOINTS 8
#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4
#define CONFIG_USBHOST_MAX_HID_CLASS 4
#define CONFIG_USBHOST_MAX_MSC_CLASS 2
#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1
#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1
#define CONFIG_USBHOST_DEV_NAMELEN 16
#ifndef CONFIG_USBHOST_PSC_PRIO
#define CONFIG_USBHOST_PSC_PRIO 0
#endif
#ifndef CONFIG_USBHOST_PSC_STACKSIZE
#define CONFIG_USBHOST_PSC_STACKSIZE 8192
#endif
//#define CONFIG_USBHOST_GET_STRING_DESC
// #define CONFIG_USBHOST_MSOS_ENABLE
#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE
#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00
#endif
/* Ep0 max transfer buffer */
#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN
#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512
#endif
#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT
#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500
#endif
#ifndef CONFIG_USBHOST_MSC_TIMEOUT
#define CONFIG_USBHOST_MSC_TIMEOUT 5000
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048)
#endif
#define CONFIG_USBHOST_BLUETOOTH_HCI_H4
// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG
#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE
#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048
#endif
#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE
#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048
#endif
/* ================ USB Device Port Configuration ================*/
#ifndef CONFIG_USBDEV_MAX_BUS
#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip
#endif
#ifndef CONFIG_USBDEV_EP_NUM
#define CONFIG_USBDEV_EP_NUM 8
#endif
/* ---------------- FSDEV Configuration ---------------- */
//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference
/* ---------------- DWC2 Configuration ---------------- */
/* (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for
* status information) + (2 * number of OUT endpoints) + 1 for Global NAK
*/
// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
/* IN Endpoints Max packet Size / 4 */
// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4)
// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
/* ---------------- MUSB Configuration ---------------- */
// #define CONFIG_USB_MUSB_SUNXI
/* ================ USB Host Port Configuration ==================*/
#ifndef CONFIG_INPUT_MOUSE_WHEEL
#define CONFIG_INPUT_MOUSE_WHEEL
#endif
#ifndef CONFIG_USBHOST_MAX_BUS
#define CONFIG_USBHOST_MAX_BUS 3
#endif
#ifndef CONFIG_USBHOST_PIPE_NUM
#define CONFIG_USBHOST_PIPE_NUM 10
#endif
/* ---------------- XHCI Configuration ---------------- */
#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0)
/* ---------------- PUSB2 Configuration ---------------- */
#define CONFIG_USB_PUSB2_BUS_NUM 3U
#define CONFIG_USB_PUSB2_BUS_ID 0U
#endif

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/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
#include "rtthread.h"
#include "interrupt.h"
#include "fparameters.h"
#include "usbd_core.h"
void USBD_IRQHandler(uint8_t busid);
void usb_assert(const char *filename, int linenum)
{
rt_assert_handler("", filename, linenum);
}
static void usb_dc_pusb2_interrupt_handler(int irqno, void *param)
{
USBD_IRQHandler(CONFIG_USB_PUSB2_BUS_ID);
}
static void usb_dc_setup_pusb2_interrupt(uint32_t id)
{
uint32_t irq_num = FUSB2_0_VHUB_IRQ_NUM;
rt_hw_interrupt_set_priority(irq_num, 0U);
rt_hw_interrupt_install(irq_num, usb_dc_pusb2_interrupt_handler, NULL, "pusb2-dc");
rt_hw_interrupt_umask(irq_num);
}
static void usb_dc_revoke_pusb2_interrupt(uint32_t id)
{
uint32_t irq_num = FUSB2_0_VHUB_IRQ_NUM;
rt_hw_interrupt_mask(irq_num);
}
unsigned long usb_dc_get_register_base(uint32_t id)
{
USB_ASSERT(id == FUSB2_ID_VHUB_0);
return FUSB2_0_VHUB_BASE_ADDR;
}
void usb_dc_low_level_init()
{
usb_dc_setup_pusb2_interrupt(CONFIG_USB_PUSB2_BUS_ID);
}
void usb_dc_low_level_deinit(void)
{
usb_dc_revoke_pusb2_interrupt(CONFIG_USB_PUSB2_BUS_ID);
}
void *usb_sys_mem_malloc(size_t size)
{
void *buf = rt_malloc(size);
if (buf) {
rt_memset(buf, 0, size);
}
return buf;
}
void usb_sys_mem_free(void *ptr)
{
if (ptr) {
rt_free(ptr);
}
}
void *usb_sys_malloc_align(size_t align, size_t size)
{
void *buf = rt_malloc_align(size, align);
if (buf) {
rt_memset(buf, 0, size);
}
return buf;
}

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port/pusb2/rt-thread/usb_hc_glue_phytium.c Normal file
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/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
#include "rtthread.h"
#include "interrupt.h"
#include "fparameters.h"
#include "usbh_core.h"
static const uint32_t irq_nums[] = {
FUSB2_0_VHUB_IRQ_NUM, FUSB2_1_IRQ_NUM, FUSB2_2_IRQ_NUM
};
void USBH_IRQHandler(uint8_t busid);
void usb_assert(const char *filename, int linenum)
{
rt_assert_handler("", filename, linenum);
}
static void usb_hc_pusb2_interrupt_handler(int irqno, void *param)
{
if (irqno == FUSB2_0_VHUB_IRQ_NUM) {
USBH_IRQHandler(FUSB2_ID_VHUB_0);
} else if (irqno == FUSB2_1_IRQ_NUM) {
USBH_IRQHandler(FUSB2_ID_1);
} else if (irqno == FUSB2_2_IRQ_NUM) {
USBH_IRQHandler(FUSB2_ID_2);
}
}
static void usb_hc_setup_pusb2_interrupt(uint32_t id)
{
uint32_t irq_num = irq_nums[id];
rt_hw_interrupt_set_priority(irq_num, 0U);
rt_hw_interrupt_install(irq_num, usb_hc_pusb2_interrupt_handler, NULL, "pusb2-hc");
rt_hw_interrupt_umask(irq_num);
USB_LOG_DBG("Enable irq-%d\n", irq_num);
}
static void usb_hc_revoke_pusb2_interrupt(uint32_t id)
{
uint32_t irq_num = irq_nums[id];
rt_hw_interrupt_mask(irq_num);
}
unsigned long usb_hc_get_register_base(uint32_t id)
{
if (id == FUSB2_ID_VHUB_0) {
return FUSB2_0_VHUB_BASE_ADDR;
} else if (id == FUSB2_ID_1) {
return FUSB2_1_BASE_ADDR;
} else if (id == FUSB2_ID_2) {
return FUSB2_2_BASE_ADDR;
} else {
USB_ASSERT(0);
return 0;
}
}
void usb_hc_low_level_init(struct usbh_bus *bus)
{
usb_hc_setup_pusb2_interrupt(bus->busid);
}
void usb_hc_low_level_deinit(struct usbh_bus *bus)
{
usb_hc_revoke_pusb2_interrupt(bus->busid);
}
void *usb_sys_mem_malloc(size_t size)
{
void *buf = rt_malloc(size);
if (buf) {
rt_memset(buf, 0, size);
}
return buf;
}
void usb_sys_mem_free(void *ptr)
{
if (ptr) {
rt_free(ptr);
}
}
void *usb_sys_malloc_align(size_t align, size_t size)
{
void *buf = rt_malloc_align(size, align);
if (buf) {
rt_memset(buf, 0, size);
}
return buf;
}

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/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
#ifndef CHERRYUSB_CONFIG_H
#define CHERRYUSB_CONFIG_H
#include "sdkconfig.h"
#define CHERRYUSB_VERSION 0x010400
#define CHERRYUSB_VERSION_STR "v1.4.0"
/* ================ USB common Configuration ================ */
#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__)
void *usb_sys_mem_malloc(size_t size);
void usb_sys_mem_free(void *ptr);
void *usb_sys_malloc_align(size_t align, size_t size);
#define usb_malloc(size) usb_sys_mem_malloc(size)
#define usb_free(ptr) usb_sys_mem_free(ptr)
#define usb_align(align, size) usb_sys_malloc_align(align, size)
unsigned long usb_dc_get_register_base(uint32_t id);
size_t usb_osal_enter_critical_section(void);
void usb_osal_leave_critical_section(size_t flag);
#ifndef CONFIG_USB_DBG_LEVEL
#if defined(CONFIG_LOG_ERROR)
#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR
#elif defined(CONFIG_LOG_WARN)
#define CONFIG_USB_DBG_LEVEL USB_DBG_WARNING
#elif defined(CONFIG_LOG_INFO)
#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO
#elif defined(CONFIG_LOG_DEBUG) || defined(CONFIG_LOG_VERBOS)
#define CONFIG_USB_DBG_LEVEL USB_DBG_LOG
#else
#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR
#endif
#endif
/* Enable print with color */
#define CONFIG_USB_PRINTF_COLOR_ENABLE
/* data align size when use dma */
#ifndef CONFIG_USB_ALIGN_SIZE
#define CONFIG_USB_ALIGN_SIZE 4
#endif
/* attribute data into no cache ram */
#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable")))
/* ================= USB Device Stack Configuration ================ */
/* Ep0 in and out transfer buffer */
#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN
#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512
#endif
/* Setup packet log for debug */
// #define CONFIG_USBDEV_SETUP_LOG_PRINT
/* Send ep0 in data from user buffer instead of copying into ep0 reqdata
* Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE
*/
// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY
/* Check if the input descriptor is correct */
// #define CONFIG_USBDEV_DESC_CHECK
/* Enable test mode */
// #define CONFIG_USBDEV_TEST_MODE
#ifndef CONFIG_USBDEV_MSC_MAX_LUN
#define CONFIG_USBDEV_MSC_MAX_LUN 1
#endif
#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE
#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 4096
#endif
#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING
#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING ""
#endif
#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING
#define CONFIG_USBDEV_MSC_PRODUCT_STRING ""
#endif
#ifndef CONFIG_USBDEV_MSC_VERSION_STRING
#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01"
#endif
// #define CONFIG_USBDEV_MSC_THREAD
#ifndef CONFIG_USBDEV_MSC_PRIO
#define CONFIG_USBDEV_MSC_PRIO 4
#endif
#ifndef CONFIG_USBDEV_MSC_STACKSIZE
#define CONFIG_USBDEV_MSC_STACKSIZE 2048
#endif
#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE
#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
#endif
/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/
#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE
#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580
#endif
#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID
#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff
#endif
#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC
#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB"
#endif
#define CONFIG_USBDEV_RNDIS_USING_LWIP
/* ================ USB HOST Stack Configuration ================== */
#define CONFIG_USBHOST_MAX_RHPORTS 1
#define CONFIG_USBHOST_MAX_EXTHUBS 1
#define CONFIG_USBHOST_MAX_EHPORTS 4
#define CONFIG_USBHOST_MAX_INTERFACES 8
#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8
#define CONFIG_USBHOST_MAX_ENDPOINTS 4
#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4
#define CONFIG_USBHOST_MAX_HID_CLASS 4
#define CONFIG_USBHOST_MAX_MSC_CLASS 2
#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1
#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1
#define CONFIG_USBHOST_DEV_NAMELEN 16
#ifndef CONFIG_USBHOST_PSC_PRIO
#define CONFIG_USBHOST_PSC_PRIO 0
#endif
#ifndef CONFIG_USBHOST_PSC_STACKSIZE
#define CONFIG_USBHOST_PSC_STACKSIZE 8192
#endif
//#define CONFIG_USBHOST_GET_STRING_DESC
// #define CONFIG_USBHOST_MSOS_ENABLE
#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE
#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00
#endif
/* Ep0 max transfer buffer */
#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN
#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512
#endif
#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT
#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500
#endif
#ifndef CONFIG_USBHOST_MSC_TIMEOUT
#define CONFIG_USBHOST_MSC_TIMEOUT 5000
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048)
#endif
#define CONFIG_USBHOST_BLUETOOTH_HCI_H4
// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG
#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE
#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048
#endif
#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE
#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048
#endif
/* ================ USB Device Port Configuration ================*/
#ifndef CONFIG_USBDEV_MAX_BUS
#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip
#endif
#ifndef CONFIG_USBDEV_EP_NUM
#define CONFIG_USBDEV_EP_NUM 8
#endif
/* ---------------- FSDEV Configuration ---------------- */
//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference
/* ---------------- DWC2 Configuration ---------------- */
/* (5 * number of control endpoints + 8) + ((largest USB packet used / 4) + 1 for
* status information) + (2 * number of OUT endpoints) + 1 for Global NAK
*/
// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
/* IN Endpoints Max packet Size / 4 */
// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4)
// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
/* ---------------- MUSB Configuration ---------------- */
// #define CONFIG_USB_MUSB_SUNXI
/* ================ USB Host Port Configuration ==================*/
#ifndef CONFIG_USBHOST_MAX_BUS
#define CONFIG_USBHOST_MAX_BUS 1
#endif
#ifndef CONFIG_USBHOST_PIPE_NUM
#define CONFIG_USBHOST_PIPE_NUM 10
#endif
/* ---------------- XHCI Configuration ---------------- */
#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0)
/* ---------------- PUSB2 Configuration ---------------- */
#define CONFIG_USB_PUSB2_BUS_NUM 1U
#define CONFIG_USB_PUSB2_BUS_ID 0U
#endif

144
port/pusb2/standalone/usb_dc_glue_phytium.c Normal file
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/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
/***************************** Include Files *********************************/
#include <stdio.h>
#include <string.h>
#include "fassert.h"
#include "fparameters.h"
#include "finterrupt.h"
#include "fcpu_info.h"
#include "fdebug.h"
#include "fcache.h"
#include "fmemory_pool.h"
#include "usbd_core.h"
/************************** Constant Definitions *****************************/
#define USB_MEMP_TOTAL_SIZE SZ_1M
/**************************** Type Definitions *******************************/
void USBD_IRQHandler(uint8_t busid);
/************************** Variable Definitions *****************************/
static FMemp memp;
static u8 memp_buf[USB_MEMP_TOTAL_SIZE] __attribute__((aligned(8))) = {0};
static void usb_sys_mem_init(void)
{
if (FT_COMPONENT_IS_READY != memp.is_ready)
{
USB_ASSERT(FT_SUCCESS == FMempInit(&memp, &memp_buf[0], &memp_buf[0] + USB_MEMP_TOTAL_SIZE));
}
}
static void usb_sys_mem_deinit(void)
{
if (FT_COMPONENT_IS_READY == memp.is_ready)
{
FMempRemove(&memp);
}
}
void *usb_sys_malloc_align(size_t align, size_t size)
{
void *result = FMempMallocAlign(&memp, size, align);
if (result)
{
memset(result, 0U, size);
}
return result;
}
void *usb_sys_mem_malloc(size_t size)
{
return usb_sys_malloc_align(sizeof(void *), size);
}
void usb_sys_mem_free(void *ptr)
{
if (NULL != ptr)
{
FMempFree(&memp, ptr);
}
}
void usb_assert(const char *filename, int linenum)
{
FAssert(filename, linenum, 0xff);
}
static void usb_dc_pusb2_interrupt_handler(s32 vector, void *param)
{
USBD_IRQHandler(CONFIG_USB_PUSB2_BUS_ID);
}
static void usb_dc_setup_pusb2_interrupt(u32 id)
{
u32 cpu_id;
USB_ASSERT(id == FUSB2_ID_VHUB_0);
u32 irq_num = FUSB2_0_VHUB_IRQ_NUM;
u32 irq_priority = 0U;
GetCpuId(&cpu_id);
InterruptSetTargetCpus(irq_num, cpu_id);
InterruptSetPriority(irq_num, irq_priority);
/* register intr callback */
InterruptInstall(irq_num,
usb_dc_pusb2_interrupt_handler,
NULL,
NULL);
/* enable irq */
InterruptUmask(irq_num);
}
static void usb_dc_revoke_pusb2_interrupt(u32 id)
{
USB_ASSERT(id == FUSB2_ID_VHUB_0);
u32 irq_num = FUSB2_0_VHUB_IRQ_NUM;
/* disable irq */
InterruptMask(irq_num);
}
unsigned long usb_dc_get_register_base(uint32_t id)
{
USB_ASSERT(id == FUSB2_ID_VHUB_0);
return FUSB2_0_VHUB_BASE_ADDR;
}
/* implement cherryusb weak functions */
void usb_dc_low_level_init()
{
usb_sys_mem_init();
usb_dc_setup_pusb2_interrupt(CONFIG_USB_PUSB2_BUS_ID);
}
void usb_dc_low_level_deinit(void)
{
usb_sys_mem_deinit();
usb_dc_revoke_pusb2_interrupt(CONFIG_USB_PUSB2_BUS_ID);
}
size_t usb_osal_enter_critical_section(void)
{
return 0;
}
void usb_osal_leave_critical_section(size_t flag)
{
}

474
port/pusb2/usb_dc_pusb2.c
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@@ -1,474 +0,0 @@
/*
* Copyright : (C) 2023 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: usb_dc_pusb2.c
* Date: 2021-08-25 14:53:42
* LastEditTime: 2021-08-26 09:01:26
* Description:  This file is for implementation of PUSB2 port to cherryusb for host mode
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2023/7/19 first commit
*/
#include "usbd_core.h"
#include "fpusb2.h"
/* Endpoint state */
struct pusb2_dc_ep_state {
uint16_t ep_mps; /* Endpoint max packet size */
uint8_t ep_type; /* Endpoint type */
uint8_t ep_stalled; /* Endpoint stall flag */
const struct usb_endpoint_descriptor *desc;
FPUsb2DcEp *priv_ep;
};
/* Data IN/OUT request */
struct pusb2_dc_request {
struct pusb2_dc_ep_state *ep;
FPUsb2DcReq *priv_req;
int status;
};
/* Driver state */
struct pusb2_udc {
FPUsb2 pusb2;
int speed;
FPUsb2Config config;
volatile uint8_t dev_addr;
int ep0_init_finish;
struct pusb2_dc_ep_state in_ep[FPUSB2_DC_EP_NUM]; /*!< IN endpoint parameters*/
struct pusb2_dc_ep_state out_ep[FPUSB2_DC_EP_NUM]; /*!< OUT endpoint parameters */
} g_pusb2_udc;
__WEAK void usb_dc_low_level_init(void)
{
}
__WEAK void usb_dc_low_level_deinit(void)
{
}
static void pusb2_dc_init_ep_state(struct pusb2_dc_ep_state *ep_state,
FPUsb2DcEp *priv_ep)
{
/* reset ep state and attach priv ep */
ep_state->ep_mps = 0U;
ep_state->ep_type = 0U;
ep_state->ep_stalled = 0U;
ep_state->desc = NULL;
ep_state->priv_ep = priv_ep;
}
static void pusb2_dc_connect_handler(FPUsb2DcController *instance)
{
FPUsb2DcDev *dc_dev = NULL;
extern void FPUsb2DcNoReset(FPUsb2DcController *instance);
FPUsb2DcGetDevInstance(&g_pusb2_udc.pusb2.device_ctrl, &dc_dev);
USB_ASSERT(dc_dev);
USB_LOG_DBG("%s \n", __func__);
usbd_event_reset_handler(0);
/* update speed and max packet size when connect */
g_pusb2_udc.speed = dc_dev->speed;
if (g_pusb2_udc.speed > USB_SPEED_HIGH) {
g_pusb2_udc.in_ep[0].ep_mps = 9;
g_pusb2_udc.out_ep[0].ep_mps = 9;
} else {
g_pusb2_udc.in_ep[0].ep_mps = dc_dev->ep0->max_packet;
g_pusb2_udc.out_ep[0].ep_mps = dc_dev->ep0->max_packet;
}
FPUsb2DcNoReset(instance);
}
static void pusb2_dc_disconnect_handler(FPUsb2DcController *instance)
{
USB_LOG_DBG("%s \n", __func__);
}
static void pusb2_dc_resume_handler(FPUsb2DcController *instance)
{
USB_LOG_DBG("%s \n", __func__);
}
static uint32_t pusb2_dc_receive_steup_handler(FPUsb2DcController *instance, FUsbSetup *setup)
{
USB_LOG_DBG("%s 0x%x:0x%x:0x%x:0x%x:0x%x\n",
__func__,
setup->bmRequestType,
setup->bRequest,
setup->wIndex,
setup->wLength,
setup->wValue);
usbd_event_ep0_setup_complete_handler(0, (u8 *)setup);
return 0;
}
static void pusb2_dc_suspend_handler(FPUsb2DcController *instance)
{
USB_LOG_DBG("%s \n", __func__);
}
static void* pusb2_dc_allocate_request_handler(FPUsb2DcController *instance, uint32_t size)
{
FPUsb2DcReq * cusbd_req = usb_malloc(size);
if (!cusbd_req) {
return NULL;
}
memset(cusbd_req, 0, sizeof(*cusbd_req));
return cusbd_req;
}
static void pusb2_dc_free_request_handler(FPUsb2DcController *instance, void *usb_request)
{
if (!usb_request)
return;
usb_free(usb_request);
}
static void pusb2_dc_pre_start_handler(FPUsb2DcController *instance)
{
FPUsb2DcEp *priv_epx = NULL;
FPUsb2DcDev *dc_dev = NULL;
FDListHead *list;
int ep_num;
FPUsb2DcGetDevInstance(&g_pusb2_udc.pusb2.device_ctrl, &dc_dev);
USB_ASSERT(dc_dev);
g_pusb2_udc.speed = dc_dev->max_speed;
pusb2_dc_init_ep_state(&g_pusb2_udc.in_ep[0], dc_dev->ep0);
pusb2_dc_init_ep_state(&g_pusb2_udc.out_ep[0], dc_dev->ep0);
for(list = dc_dev->ep_list.next;
list != &dc_dev->ep_list;
list = list->next) {
priv_epx = (FPUsb2DcEp*)list;
ep_num = USB_EP_GET_IDX(priv_epx->address);
if (USB_EP_DIR_IS_IN(priv_epx->address)) {
pusb2_dc_init_ep_state(&g_pusb2_udc.in_ep[ep_num], priv_epx);
} else {
pusb2_dc_init_ep_state(&g_pusb2_udc.out_ep[ep_num], priv_epx);
}
}
}
static void pusb2_dc_prepare_ctrl_config(FPUsb2Config *config)
{
*config = *FPUsb2LookupConfig(CONFIG_USBDEV_PUSB2_CTRL_ID);
config->mode = FPUSB2_MODE_PERIPHERAL;
/* allocate DMA buffer for TRB transfer */
config->trb_mem_addr = usb_align(64U, config->trb_mem_size);
USB_ASSERT(config->trb_mem_addr);
/* hook up device callbacks */
config->host_cb.givback_request = NULL;
config->host_cb.otg_state_change = NULL;
config->host_cb.port_status_change = NULL;
config->host_cb.set_ep_toggle = NULL;
config->host_cb.get_ep_toggle = NULL;
config->host_cb.pre_start = NULL;
config->device_cb.connect = pusb2_dc_connect_handler;
config->device_cb.disconnect= pusb2_dc_disconnect_handler;
config->device_cb.resume = pusb2_dc_resume_handler;
config->device_cb.setup = pusb2_dc_receive_steup_handler;
config->device_cb.suspend = pusb2_dc_suspend_handler;
config->device_cb.usb_request_mem_alloc = pusb2_dc_allocate_request_handler;
config->device_cb.usb_request_mem_free = pusb2_dc_free_request_handler;
config->device_cb.pre_start = pusb2_dc_pre_start_handler;
return;
}
int usb_dc_init(uint8_t busid)
{
memset(&g_pusb2_udc, 0, sizeof(struct pusb2_udc));
usb_dc_low_level_init();
pusb2_dc_prepare_ctrl_config(&g_pusb2_udc.config);
if (FPUSB2_SUCCESS != FPUsb2CfgInitialize(&g_pusb2_udc.pusb2,
&g_pusb2_udc.config)) {
USB_LOG_ERR("init pusb2 failed \n");
return -1;
}
USB_LOG_INFO("init pusb2 successed \n");
return 0;
}
int usb_dc_deinit(uint8_t busid)
{
usb_dc_low_level_deinit();
FPUsb2DeInitialize(&g_pusb2_udc.pusb2);
return 0;
}
int usbd_set_address(uint8_t busid, const uint8_t addr)
{
g_pusb2_udc.dev_addr = addr;
return 0;
}
static struct usb_endpoint_descriptor *usbd_get_ep0_desc(const struct usb_endpoint_descriptor *ep)
{
static struct usb_endpoint_descriptor ep0_desc;
/* Config EP0 mps from speed */
ep0_desc.bEndpointAddress = ep->bEndpointAddress;
ep0_desc.bDescriptorType = USB_DESCRIPTOR_TYPE_ENDPOINT;
ep0_desc.bmAttributes = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
ep0_desc.wMaxPacketSize = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
ep0_desc.bInterval = 0;
ep0_desc.bLength = 7;
return &ep0_desc;
}
int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep)
{
uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress);
struct pusb2_dc_ep_state *ep_state;
uint32_t error;
if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) {
ep_state = &g_pusb2_udc.out_ep[ep_idx];
} else {
ep_state = &g_pusb2_udc.in_ep[ep_idx];
}
ep_state->ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
ep_state->ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
ep_state->desc = usbd_get_ep0_desc(ep);
USB_ASSERT(ep_state->priv_ep != NULL);
USB_LOG_DBG("try to enable ep@0x%x 0x%x:0x%x\n", ep->bEndpointAddress,
ep_state->priv_ep, ep_state->desc );
error = FPUsb2DcEpEnable(&g_pusb2_udc.pusb2.device_ctrl,
ep_state->priv_ep,
(const FUsbEndpointDescriptor *)ep_state->desc);
if (FPUSB2_SUCCESS != error){
USB_LOG_ERR("enable ep-%d failed, error = 0x%x\n", ep->bEndpointAddress, error);
return -1;
}
g_pusb2_udc.ep0_init_finish = 1;
return 0;
}
int usbd_ep_close(uint8_t busid, const uint8_t ep)
{
uint8_t ep_idx = USB_EP_GET_IDX(ep);
struct pusb2_dc_ep_state *ep_state;
if (USB_EP_DIR_IS_OUT(ep)) {
ep_state = &g_pusb2_udc.out_ep[ep_idx];
} else {
ep_state = &g_pusb2_udc.in_ep[ep_idx];
}
ep_state->desc = NULL;
if (FPUSB2_SUCCESS != FPUsb2DcEpDisable(&g_pusb2_udc.pusb2.device_ctrl,
ep_state->priv_ep)){
USB_LOG_ERR("disable ep@0x%x failed\n", ep);
return -1;
}
return 0;
}
int usbd_ep_set_stall(uint8_t busid, const uint8_t ep)
{
uint8_t ep_idx = USB_EP_GET_IDX(ep);
struct pusb2_dc_ep_state *ep_state;
if (USB_EP_DIR_IS_OUT(ep)) {
ep_state = &g_pusb2_udc.out_ep[ep_idx];
} else {
ep_state = &g_pusb2_udc.in_ep[ep_idx];
}
if (FPUSB2_SUCCESS != FPUsb2DcEpSetHalt(&g_pusb2_udc.pusb2.device_ctrl,
ep_state->priv_ep, 1)){
USB_LOG_ERR("stall ep@0x%x failed\n", ep);
return -1;
}
ep_state->ep_stalled = 1;
return 0;
}
int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep)
{
uint8_t ep_idx = USB_EP_GET_IDX(ep);
struct pusb2_dc_ep_state *ep_state;
if (USB_EP_DIR_IS_OUT(ep)) {
ep_state = &g_pusb2_udc.out_ep[ep_idx];
} else {
ep_state = &g_pusb2_udc.in_ep[ep_idx];
}
if (FPUSB2_SUCCESS != FPUsb2DcEpSetHalt(&g_pusb2_udc.pusb2.device_ctrl,
ep_state->priv_ep, 0)){
USB_LOG_ERR("clear ep@0x%x stall status failed\n", ep);
return -1;
}
ep_state->ep_stalled = 0;
return 0;
}
int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled)
{
uint8_t ep_idx = USB_EP_GET_IDX(ep);
struct pusb2_dc_ep_state *ep_state;
if (USB_EP_DIR_IS_OUT(ep)) {
ep_state = &g_pusb2_udc.out_ep[ep_idx];
} else {
ep_state = &g_pusb2_udc.in_ep[ep_idx];
}
if (stalled) {
*stalled = ep_state->ep_stalled;
}
return 0;
}
static struct pusb2_dc_request *pusb2_dc_allocate_request(struct pusb2_dc_ep_state *ep_state)
{
struct pusb2_dc_request *request = usb_malloc(sizeof(*request));
if (!request) {
return NULL;
}
memset(request, 0, sizeof(*request));
request->ep = ep_state;
request->priv_req = NULL;
if (FPUSB2_SUCCESS != FPUsb2DcReqAlloc(&g_pusb2_udc.pusb2.device_ctrl,
ep_state->priv_ep,
&request->priv_req )){
USB_LOG_ERR("allocate request failed\n");
usb_free(request);
return NULL;
}
return request;
}
static void pusb2_dc_free_request(struct pusb2_dc_request *request)
{
USB_ASSERT(request);
struct pusb2_dc_ep_state *ep_state = request->ep;
FPUsb2DcReqFree(&g_pusb2_udc.pusb2.device_ctrl,
ep_state->priv_ep,
request->priv_req);
usb_free(request);
}
void pusb2_dc_callback_complete(FPUsb2DcEp *priv_ep, FPUsb2DcReq *priv_request)
{
USB_ASSERT(priv_ep && priv_request);
struct pusb2_dc_request *request;
request = priv_request->context;
if (USB_EP_DIR_IS_OUT(priv_ep->address)) {
usbd_event_ep_out_complete_handler(0, priv_ep->address, priv_request->actual);
} else {
usbd_event_ep_in_complete_handler(0, priv_ep->address, priv_request->actual);
}
request->status = priv_request->status;
if (request->status != 0) {
USB_LOG_ERR("Request failed, status = %d\n", request->status);
}
pusb2_dc_free_request(request);
priv_request->context = NULL;
}
int pusb2_dc_ep_read_write(const uint8_t ep, uintptr data, uint32_t data_len)
{
uint8_t ep_idx = USB_EP_GET_IDX(ep);
struct pusb2_dc_ep_state *ep_state;
struct pusb2_dc_request *request;
uint32_t error;
if (USB_EP_DIR_IS_OUT(ep)) {
ep_state = &g_pusb2_udc.out_ep[ep_idx];
} else {
ep_state = &g_pusb2_udc.in_ep[ep_idx];
}
request = pusb2_dc_allocate_request(ep_state);
if (!request) {
USB_LOG_ERR("failed to allocate request !!!\n");
return -1;
}
request->priv_req->dma = data;
request->priv_req->buf = (void *)data;
request->priv_req->length = data_len;
request->priv_req->complete = pusb2_dc_callback_complete;
request->priv_req->context = request;
request->priv_req->status = 0;
error = FPUsb2DcReqQueue(&g_pusb2_udc.pusb2.device_ctrl,
ep_state->priv_ep,
request->priv_req);
if (FPUSB2_SUCCESS != error){
USB_LOG_ERR("send req to ep@0x%x failed, error = 0x%x\n", ep, error);
return -1;
}
return 0;
}
int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len)
{
return pusb2_dc_ep_read_write(ep, (uintptr)data, data_len);
}
int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len)
{
return pusb2_dc_ep_read_write(ep, (uintptr)data, data_len);
}
void USBD_IRQHandler(uint8_t busid)
{
FPUsb2InterruptHandler(&g_pusb2_udc.pusb2);
}

684
port/pusb2/usb_hc_pusb2.c
View File

@@ -1,684 +0,0 @@
/*
* Copyright : (C) 2023 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: usb_hc_pusb2.c
* Date: 2021-08-25 14:53:42
* LastEditTime: 2021-08-26 09:01:26
* Description:  This file is for implementation of PUSB2 port to cherryusb for host mode
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2023/7/19 first commit
* 1.1 zhugengyu 2023/11/14 sync with 0.11.1 port interface
*/
#include <assert.h>
#include "usbh_core.h"
#include "usbh_hub.h"
#include "fpusb2.h"
struct pusb2_pipe;
struct pusb2_dev;
struct pusb2_hcd;
struct pusb2_hcd {
FPUsb2 pusb2;
FPUsb2Config config;
};
struct pusb2_dev {
FPUsb2HcEp ep0;
FPUsb2HcEp *epx_in[FPUSB2_HC_EP_NUM];
FPUsb2HcEp *epx_out[FPUSB2_HC_EP_NUM];
FPUsb2HcDevice udev;
/*one bit for each endpoint, with ([0] = IN, [1] = OUT) endpoints*/
unsigned int toggle[2];
#define PUSB2_GET_TOGGLE(dev, ep, out) (((dev)->toggle[out] >> (ep)) & 1)
#define PUSB2_DO_TOGGLE(dev, ep, out) ((dev)->toggle[out] ^= (1 << (ep)))
#define PUSB2_SET_TOGGLE(dev, ep, out, bit) \
((dev)->toggle[out] = ((dev)->toggle[out] & ~(1 << (ep))) | \
((bit) << (ep)))
};
struct pusb2_pipe {
struct pusb2_hcd *hcd;
struct pusb2_dev *dev;
uint8_t speed;
uint8_t dev_addr;
uint8_t ep_addr;
uint8_t ep_type;
uint8_t ep_num;
uint8_t ep_is_in;
uint8_t ep_interval;
uint16_t ep_mps;
bool inuse;
volatile bool waiter;
usb_osal_sem_t waitsem;
struct usbh_hubport *hport;
struct usbh_urb *urb;
const struct usb_endpoint_descriptor *desc;
};
static int usb_id = CONFIG_USBDEV_PUSB2_CTRL_ID;
static struct pusb2_hcd g_pusb2_hcd[CONFIG_USBDEV_PUSB2_CTRL_NUM];
__WEAK void usb_hc_low_level_init(void)
{
}
__WEAK void *usb_hc_malloc(size_t size)
{
return NULL;
}
__WEAK void *usb_hc_malloc_align(size_t align, size_t size)
{
return NULL;
}
__WEAK void usb_hc_free()
{
}
/* one may get xhci register base address by PCIe bus emuration */
__WEAK unsigned long usb_hc_get_register_base(uint32_t id)
{
return 0U;
}
static inline struct pusb2_dev *pusb2_hc_pipe_to_dev(struct pusb2_pipe *ppipe)
{
USB_ASSERT(ppipe && ppipe->dev);
return ppipe->dev;
}
static inline struct pusb2_hcd *pusb2_hc_get_hcd(void)
{
return &g_pusb2_hcd[usb_id];
}
static void pusb2_pipe_waitup(struct pusb2_pipe *pipe)
{
struct usbh_urb *urb;
urb = pipe->urb;
pipe->urb = NULL;
if (pipe->waiter) {
pipe->waiter = false;
usb_osal_sem_give(pipe->waitsem);
}
if (urb->complete) {
if (urb->errorcode < 0) {
urb->complete(urb->arg, urb->errorcode);
} else {
urb->complete(urb->arg, urb->actual_length);
}
}
}
static void pusb2_hc_request_giveback(FPUsb2HcController *instance, FPUsb2HcReq *req, u32 status)
{
struct usbh_urb *urb;
struct pusb2_pipe *pipe;
int error = 0;
urb = req->user_ext;
pipe = urb->pipe;
switch(status) {
case FPUSB2_HC_ESTALL:
error = -EPIPE;
break;
case FPUSB2_HC_EUNHANDLED:
error = -EPROTO;
break;
case FPUSB2_HC_ESHUTDOWN:
error = -ESHUTDOWN;
break;
}
urb->errorcode = error;
urb->actual_length = req->actual_length;
pusb2_pipe_waitup(pipe);
return;
}
static void pusb2_hc_otg_state_change(FPUsb2HcController *instance, int otg_state)
{
return;
}
static int pusb2_hub_status_data(FPUsb2HcController *instance, char *buf)
{
int retval = 0;
retval = FPUsb2VHubStatusChangeData(instance, (u8 *)buf);
if(retval != 0) {
return 0;
}
if(*buf == 0x02) {
return 1;
} else {
return 0;
}
}
static void pusb2_hc_rh_port_status_change(FPUsb2HcController *instance)
{
u32 status_hub = 0U;
u16 *status = (u16*)&status_hub;
FUsbSetup setup;
u32 retval = 0;
pusb2_hub_status_data(instance, (char*)status);
setup.bRequest = FUSB_REQ_GET_STATUS;
setup.bmRequestType = FUSB_REQ_TYPE_CLASS | FUSB_REQ_RECIPIENT_OTHER | FUSB_DIR_DEVICE_TO_HOST;
setup.wIndex = cpu_to_le16(1); /* port number */
setup.wLength = cpu_to_le16(4);
setup.wValue = 0;
retval = FPUsb2VHubControl(instance, &setup, (u8*)status);
if(retval) {
return;
}
if(status[1] & FUSB_PSC_CONNECTION) {
if(status[0] & FUSB_PS_CONNECTION) {
USB_LOG_DBG("resume roothub \n");
/* Report port status change */
usbh_roothub_thread_wakeup ( 1U );
}
}
}
static u8 pusb2_hc_get_ep_toggle(void *instance, struct FPUsb2HcDevice *udev, u8 ep_num, u8 is_in)
{
struct pusb2_dev *dev;
u8 toggle = 0;
dev = (struct pusb2_dev*) udev->user_ext;
toggle = PUSB2_GET_TOGGLE(dev, ep_num, !is_in);
return toggle;
}
static void pusb2_hc_set_ep_toggle(void *instance, struct FPUsb2HcDevice *udev, u8 ep_num, u8 is_in, u8 toggle)
{
struct pusb2_dev *dev;
dev = (struct pusb2_dev*) udev->user_ext;
PUSB2_SET_TOGGLE(dev, ep_num, !is_in, toggle);
}
static void pusb2_hc_prepare_ctrl_config(uint32_t id, FPUsb2Config *config)
{
*config = *FPUsb2LookupConfig(id);
config->mode = FPUSB2_MODE_HOST;
/* allocate DMA buffer for TRB transfer */
config->trb_mem_addr = usb_align(64U, config->trb_mem_size);
USB_ASSERT(config->trb_mem_addr);
/* hook up host callbacks */
config->host_cb.givback_request = pusb2_hc_request_giveback;
config->host_cb.otg_state_change = pusb2_hc_otg_state_change;
config->host_cb.port_status_change = pusb2_hc_rh_port_status_change;
config->host_cb.set_ep_toggle = pusb2_hc_set_ep_toggle;
config->host_cb.get_ep_toggle = pusb2_hc_get_ep_toggle;
config->host_cb.pre_start = NULL;
config->host_cb.usb_dev_callbacks = &config->device_cb;
config->device_cb.connect = NULL;
config->device_cb.disconnect= NULL;
config->device_cb.resume = NULL;
config->device_cb.setup = NULL;
config->device_cb.suspend = NULL;
config->device_cb.usb_request_mem_alloc = NULL;
config->device_cb.usb_request_mem_free = NULL;
config->device_cb.pre_start = NULL;
return;
}
int usb_hc_init(void)
{
int rc;
struct pusb2_hcd *hcd = pusb2_hc_get_hcd();
size_t flag = usb_osal_enter_critical_section(); /* no interrupt when init hc */
usb_hc_low_level_init(); /* set gic and memp */
memset(hcd, 0, sizeof(*hcd));
pusb2_hc_prepare_ctrl_config(usb_id, &hcd->config);
if (FPUSB2_SUCCESS != FPUsb2CfgInitialize(&hcd->pusb2,
&hcd->config)) {
USB_LOG_ERR("init pusb2 failed \n");
rc = -1;
} else {
USB_LOG_INFO("init pusb2 successed \n");
}
usb_osal_leave_critical_section(flag);
return rc;
}
uint16_t usbh_get_frame_number(void)
{
return 0;
}
int usbh_roothub_control(struct usb_setup_packet *setup, uint8_t *buf)
{
struct pusb2_hcd *hcd = pusb2_hc_get_hcd();
int retval = 0;
retval = FPUsb2VHubControl(&(hcd->pusb2.host_ctrl), (FUsbSetup *)setup, buf);
if(retval != 0) {
USB_LOG_ERR("%s failed, retval = %d \r\n", __func__, retval);
}
return retval;
}
static void pusb2_hc_update_device(struct pusb2_dev *dev, int dev_addr, int speed, int mps)
{
dev->udev.speed = (FUsbSpeed)speed;
dev->udev.devnum = dev_addr;
dev->ep0.ep_desc.max_packet_size = mps;
}
int usbh_ep_pipe_reconfigure(usbh_pipe_t pipe, uint8_t dev_addr, uint8_t mtu, uint8_t speed)
{
struct pusb2_pipe *ppipe = pipe;
struct usbh_hubport *hport = ppipe->hport;
struct pusb2_dev *dev = pusb2_hc_pipe_to_dev(ppipe);
pusb2_hc_update_device(dev, dev_addr, hport->speed, mtu);
return 0;
}
static struct pusb2_dev *pusb2_hc_allocate_dev(void)
{
struct pusb2_hcd *hcd = pusb2_hc_get_hcd();
struct pusb2_dev *dev;
dev = usb_malloc((sizeof *dev)+ FPUsb2HcGetPrivateDataSize(&(hcd->pusb2.host_ctrl)));
if (dev == NULL)
return NULL;
dev->ep0.hc_priv = &((u8*)dev)[sizeof *dev]; /* ep private data */
dev->udev.user_ext = (void*)dev;
dev->ep0.ep_desc.bLength = FUSB_DS_ENDPOINT;
dev->ep0.ep_desc.bDescriptorType = FUSB_DT_ENDPOINT;
FDLIST_INIT_HEAD(&dev->ep0.reqList);
dev->epx_in[0] = &dev->ep0;
dev->epx_out[0] = &dev->ep0;
return dev;
}
static void pusb2_hc_free_ep(struct pusb2_pipe *ppipe)
{
USB_ASSERT(ppipe && ppipe->hcd);
struct usbh_hubport *hport = ppipe->hport;
struct pusb2_hcd *hcd = ppipe->hcd;
struct pusb2_dev *dev = pusb2_hc_pipe_to_dev(ppipe);
int ep_num = USB_EP_GET_IDX(ppipe->ep_addr);
if (USB_EP_DIR_IS_IN(ppipe->ep_addr)) {
dev->epx_in[ep_num]->user_ext = NULL;
usb_free(dev->epx_in[ep_num]);
dev->epx_in[ep_num] = NULL;
} else {
dev->epx_out[ep_num]->user_ext = NULL;
usb_free(dev->epx_out[ep_num]);
dev->epx_out[ep_num] = NULL;
}
return;
}
static void pusb2_hc_free_dev(struct pusb2_pipe *ppipe)
{
USB_ASSERT(ppipe && ppipe->hcd);
struct usbh_hubport *hport = ppipe->hport;
struct pusb2_hcd *hcd = ppipe->hcd;
struct pusb2_dev *dev = pusb2_hc_pipe_to_dev(ppipe);
dev->epx_in[0] = NULL;
dev->epx_out[0] = NULL;
for (int i = 1; i < FPUSB2_HC_EP_NUM; i++) {
if (dev->epx_in[i]) {
dev->epx_in[i]->user_ext = NULL;
usb_free(dev->epx_in[i]);
dev->epx_in[i] = NULL;
}
if (dev->epx_out[i]) {
dev->epx_out[i]->user_ext = NULL;
usb_free(dev->epx_out[i]);
dev->epx_out[i] = NULL;
}
}
usb_free(dev);
return;
}
int usbh_pipe_alloc(usbh_pipe_t *pipe, const struct usbh_endpoint_cfg *ep_cfg)
{
struct usbh_hubport *hport = ep_cfg->hport;
struct pusb2_hcd *hcd = pusb2_hc_get_hcd();
struct pusb2_pipe *ppipe = usb_malloc(sizeof(struct pusb2_pipe));
struct pusb2_dev *dev;
if (NULL == ppipe) {
return -ENOMEM;
}
memset(ppipe, 0, sizeof(struct pusb2_pipe));
ppipe->waitsem = usb_osal_sem_create(0);
ppipe->waiter = false;
ppipe->urb = NULL;
ppipe->hport = hport;
ppipe->ep_addr = ep_cfg->ep_addr;
ppipe->ep_type = ep_cfg->ep_type;
ppipe->ep_num = USB_EP_GET_IDX(ep_cfg->ep_addr);
ppipe->ep_is_in = USB_EP_DIR_IS_IN(ep_cfg->ep_addr);
ppipe->ep_mps = ep_cfg->ep_mps;
ppipe->ep_interval = ep_cfg->ep_interval;
ppipe->hcd = hcd;
USB_LOG_DBG("allocate ep-%d\n", ppipe->ep_num);
if (ppipe->ep_addr == 0) { /* if try to allocate ctrl ep, open device first */
dev = pusb2_hc_allocate_dev();
if (NULL == dev) {
usb_free(ppipe);
return -ENOMEM;
}
ppipe->desc = (const struct usb_endpoint_descriptor *)&(dev->ep0.ep_desc);
ppipe->dev = dev;
} else {
dev = pusb2_hc_pipe_to_dev((struct pusb2_pipe *)hport->ep0);
struct pusb2_pipe *ppipe_ctrl = hport->ep0;
ppipe->desc = ppipe_ctrl->desc;
ppipe->dev = dev;
}
*pipe = (usbh_pipe_t)ppipe;
return 0;
}
int usbh_pipe_free(usbh_pipe_t pipe)
{
USB_ASSERT(pipe);
struct pusb2_pipe *ppipe = (struct pusb2_pipe *)pipe;
struct usbh_urb *urb = ppipe->urb;
size_t flags;
/* free any un-finished urb */
if (ppipe->urb) {
usbh_kill_urb(urb);
}
flags = usb_osal_enter_critical_section();
if (USB_EP_GET_IDX(ppipe->ep_addr) == 0) {
/* free control ep means free device */
pusb2_hc_free_dev(ppipe);
} else {
/* free work ep */
pusb2_hc_free_ep(ppipe);
}
usb_osal_leave_critical_section(flags);
return 0;
}
static void pusb2_hc_update_endpoint(struct pusb2_hcd *hcd, struct pusb2_dev *dev, struct pusb2_pipe *pipe)
{
USB_ASSERT(hcd && dev && pipe);
FPUsb2HcEp * priv_ep = NULL;
int epnum = pipe->ep_num;
int is_out = !pipe->ep_is_in;
if (is_out) {
if (dev->epx_out[epnum] == NULL) {
priv_ep = usb_malloc(sizeof(FPUsb2HcEp) + FPUsb2HcGetPrivateDataSize(&(hcd->pusb2.host_ctrl)));
USB_ASSERT(priv_ep);
dev->epx_out[epnum] = priv_ep;
} else {
priv_ep = dev->epx_out[epnum];
}
} else {
if (dev->epx_in[epnum] == NULL) {
priv_ep = usb_malloc(sizeof(FPUsb2HcEp) + FPUsb2HcGetPrivateDataSize(&(hcd->pusb2.host_ctrl)));
USB_ASSERT(priv_ep);
dev->epx_in[epnum] = priv_ep;
} else {
priv_ep = dev->epx_in[epnum];
}
}
priv_ep->ep_desc = *((FUsbEndpointDescriptor *)pipe->desc);
priv_ep->user_ext = (void *)pipe;
FDLIST_INIT_HEAD(&priv_ep->reqList);
priv_ep->hc_priv = &((u8*)priv_ep)[sizeof *priv_ep];
}
static int pusb2_hc_enqueue_urb(struct usbh_urb *urb)
{
struct pusb2_pipe *pipe = urb->pipe;
struct usbh_hubport *hport = pipe->hport;
struct pusb2_hcd *hcd = pusb2_hc_get_hcd();
struct pusb2_dev *dev;
u32 iso_frame_size;
FPUsb2HcReq *priv_req;
int ret;
if(!FPUsb2HcIsHostMode(&(hcd->pusb2.host_ctrl))) {
return -ENODEV;
}
dev = pusb2_hc_pipe_to_dev(pipe);
if(!dev)
return -ENODEV;
if (pipe->ep_is_in) {
if (!dev->epx_in[pipe->ep_num]) {
pusb2_hc_update_endpoint(hcd, dev, pipe);
}
} else {
if (!dev->epx_out[pipe->ep_num]) {
pusb2_hc_update_endpoint(hcd, dev, pipe);
}
}
iso_frame_size = urb->num_of_iso_packets * sizeof(FPUsb2HcIsoFrameDesc);
priv_req = (FPUsb2HcReq*)usb_malloc((sizeof *priv_req) + iso_frame_size);
if (!priv_req)
return -ENOMEM;
priv_req->iso_frames_desc = NULL;
priv_req->iso_frames_number = urb->num_of_iso_packets;
FDLIST_INIT_HEAD(&priv_req->list);
priv_req->user_ext = (void*) urb;
priv_req->actual_length = urb->actual_length;
priv_req->buf_address = urb->transfer_buffer;
priv_req->buf_dma = (uintptr_t)urb->transfer_buffer;
priv_req->buf_length = urb->transfer_buffer_length;
priv_req->ep_is_in = pipe->ep_is_in;
priv_req->ep_num = pipe->ep_num;
priv_req->ep_type = pipe->ep_type;
priv_req->faddress = dev->udev.devnum;
priv_req->interval = pipe->ep_interval;
priv_req->req_unlinked = 0;
priv_req->setup = (FUsbSetup*)urb->setup;
priv_req->setup_dma = (uintptr_t)urb->setup;
priv_req->status = FPUSB2_ERR_INPROGRESS;
priv_req->usb_dev = &dev->udev;
priv_req->usb_ep = priv_req->ep_is_in ? dev->epx_in[priv_req->ep_num]:
dev->epx_out[priv_req->ep_num];
if (priv_req->ep_num == 0) {
dev->ep0.ep_desc.max_packet_size = pipe->ep_mps;
}
urb->hcpriv = priv_req;
ret = FPUsb2HcReqQueue(&(hcd->pusb2.host_ctrl), priv_req);
if(ret) {
usb_free(priv_req);
return ret;
}
return ret;
}
int usbh_submit_urb(struct usbh_urb *urb)
{
struct pusb2_pipe *pipe = (struct pusb2_pipe *)urb->pipe;
size_t flags;
int ret = 0;
if (!urb) {
return -EINVAL;
}
if (!pipe->hport->connected) {
return -ENODEV;
}
if (pipe->urb) {
return -EBUSY;
}
if (urb->timeout > 0) {
flags = usb_osal_enter_critical_section();
}
pipe->waiter = false;
pipe->urb = urb;
urb->errorcode = -EBUSY;
urb->actual_length = 0;
if (urb->timeout > 0) {
pipe->waiter = true;
}
if (urb->timeout > 0) {
usb_osal_leave_critical_section(flags);
}
switch (pipe->ep_type) {
case USB_ENDPOINT_TYPE_CONTROL:
case USB_ENDPOINT_TYPE_BULK:
case USB_ENDPOINT_TYPE_INTERRUPT:
case USB_ENDPOINT_TYPE_ISOCHRONOUS:
ret = pusb2_hc_enqueue_urb(urb);
break;
default:
break;
}
if (urb->timeout > 0) {
/* wait until timeout or sem give */
ret = usb_osal_sem_take(pipe->waitsem, urb->timeout);
if (ret < 0) {
USB_LOG_ERR("wait request timeout, ret = %d \n", ret);
goto errout_timeout;
}
ret = urb->errorcode;
}
return ret;
errout_timeout:
pipe->waiter = false;
usbh_kill_urb(urb);
return ret;
}
static void pusb2_hc_dequeue_urb(struct usbh_urb *urb)
{
USB_ASSERT(urb);
struct pusb2_pipe *pipe = urb->pipe;
struct usbh_hubport *hport = pipe->hport;
struct pusb2_hcd *hcd = pusb2_hc_get_hcd();
struct pusb2_dev *dev;
FPUsb2HcReq *priv_req = urb->hcpriv;
USB_ASSERT(priv_req);
if (FPUSB2_SUCCESS != FPUsb2HcReqDequeue(&(hcd->pusb2.host_ctrl), priv_req, 0)) {
USB_LOG_ERR("failed to dequeue urb \n");
}
usb_free(priv_req);
urb->hcpriv = NULL;
return;
}
int usbh_kill_urb(struct usbh_urb *urb)
{
size_t flags;
if (!urb) {
return -EINVAL;
}
struct pusb2_pipe *pipe = urb->pipe;
flags = usb_osal_enter_critical_section();
pusb2_hc_dequeue_urb(urb);
pipe->urb = NULL;
if (pipe->waiter) {
pipe->waiter = false;
urb->errorcode = -ESHUTDOWN;
usb_osal_sem_give(pipe->waitsem);
}
usb_osal_sem_delete(pipe->waitsem);
usb_osal_leave_critical_section(flags);
return 0;
}
void USBH_IRQHandler(void *param)
{
struct pusb2_hcd *hcd = pusb2_hc_get_hcd();
FPUsb2InterruptHandler(&hcd->pusb2);
return;
}

70
port/xhci/phytium/README.md Normal file
View File

@@ -0,0 +1,70 @@
# USB 3.0 Host 控制器 (XHCI)
- Phytium PI 和 Phyium E2000 系列开发板提供符合 XHCI 1.1 规范的 USB 3.0 Host 控制器, 其它 Phytium 系列平台可以通过 PCIe 扩展卡获得 XHCI 控制器
- 相关的使用例程可以在 Phytium PI（飞腾派）、E2000 D/Q Demo 板以及 D2000 和后续平台上运行，例程包括
---------------------------------------------
- FreeRTOS
- - 1. [XHCI 平台控制器使用鼠标/键盘/U盘功能](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/xhci_platform/README.md)
- - 2. [XHCI PCIe控制器使用鼠标/键盘/U盘功能](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/xhci_pcie/README.md)
- - 3. [LVGL 中使用 XHCI 平台控制器连接的鼠标/键盘/U盘](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/example/peripheral/media/lvgl_indev/README.md)
---------------------------------------------
- RT-Thread
- - 1. [XHCI 平台控制器识别鼠标/键盘/U盘](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md)
---------------------------------------------
- Standalone 裸机
- - 暂不支持
---------------------------------------------
- XHCI 的驱动功能以静态库的方式提供，仅限在 Phytium 系列 CPU 平台使用，
- - libxhci_a64.a : AARCH64 驱动库
- - libxhci_a32_hardfp.a : AARCH32 驱动库，使用硬浮点
- - libxhci_a32_softfp.a : AARCH32 驱动库，使用软浮点
需要获取源代码请联系 `opensource_embedded@phytium.com.cn` 获取，如需移植运行到非 Phytium 系列 CPU 平台请提前联系`opensource_embedded@phytium.com.cn`获得允许
# USB 3.0 Host Controller (XHCI)
- The Phytium PI and Phytium E2000 series development boards provide USB 3.0 Host controllers that conform to the XHCI 1.1 specification. Other Phytium series platforms can obtain XHCI controllers through PCIe expansion cards.
- Related example routines can be run on Phytium PI (Fetion Pi), E2000 D/Q Demo boards, and D2000 and later platforms. Examples include:
---------------------------------------------
- FreeRTOS
- 1. [XHCI platform controller for mouse/keyboard/USB drive functions](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/xhci_platform/README.md)
- 2. [XHCI PCIe controller for mouse/keyboard/USB drive functions](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/tree/master/example/peripheral/usb/xhci_pcie/README.md)
- 3. [Using XHCI platform controller-connected mouse/keyboard/USB drive in LVGL](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk/blob/master/example/peripheral/media/lvgl_indev/README.md)
---------------------------------------------
- RT-Thread
- 1. [XHCI platform controller recognizing mouse/keyboard/USB drive](https://github.com/RT-Thread/rt-thread/blob/master/bsp/phytium/doc/use_cherryusb.md)
---------------------------------------------
- Standalone (Bare Metal)
- Not supported yet
---------------------------------------------
- This XHCI driver functionality is provided as a static library and is only available for Phytium series CPU platforms.
- - `libxhci_a64.a` : Driver library for AARCH64
- - `libxhci_a32_hardfp.a` : Driver library for AARCH32, using hard floating point
- - `libxhci_a32_softfp.a` : Driver library for AARCH32, using soft floating point
- To obtain the source code, please contact `opensource_embedded@phytium.com.cn`.
- For porting to non-Phytium CPU platforms, shall contact `opensource_embedded@phytium.com.cn` in advance for permission.

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port/xhci/phytium/freertos/usb_config.h Executable file
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/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
#ifndef CHERRYUSB_CONFIG_H
#define CHERRYUSB_CONFIG_H
#include "sdkconfig.h"
#include "FreeRTOS.h"
#include "task.h"
#define CHERRYUSB_VERSION 0x010400
#define CHERRYUSB_VERSION_STR "v1.4.0"
/* ================ USB common Configuration ================ */
#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__)
void *xhci_mem_malloc(size_t align, size_t size);
void xhci_mem_free(void *ptr);
#define XHCI_DCACHE_FLUSH (1 << 0)
#define XHCI_DCACHE_INVALIDATE (1 << 1)
void xhci_dcache_sync(void *ptr, size_t len, uint32_t flags);
unsigned long usb_hc_get_register_base(uint32_t id);
#define usb_malloc(size) xhci_mem_malloc(sizeof(int), size)
#define usb_free(ptr) xhci_mem_free(ptr)
#ifndef CONFIG_USB_DBG_LEVEL
#if defined(CONFIG_LOG_ERROR)
#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR
#elif defined(CONFIG_LOG_WARN)
#define CONFIG_USB_DBG_LEVEL USB_DBG_WARNING
#elif defined(CONFIG_LOG_INFO)
#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO
#elif defined(CONFIG_LOG_DEBUG) || defined(CONFIG_LOG_VERBOS)
#define CONFIG_USB_DBG_LEVEL USB_DBG_LOG
#else
#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR
#endif
#endif
/* Enable print with color */
#define CONFIG_USB_PRINTF_COLOR_ENABLE
/* data align size when use dma */
#ifndef CONFIG_USB_ALIGN_SIZE
#define CONFIG_USB_ALIGN_SIZE 4
#endif
/* attribute data into no cache ram */
#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable")))
/* ================= USB Device Stack Configuration ================ */
/* Ep0 in and out transfer buffer */
#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN
#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512
#endif
/* Setup packet log for debug */
// #define CONFIG_USBDEV_SETUP_LOG_PRINT
/* Send ep0 in data from user buffer instead of copying into ep0 reqdata
* Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE
*/
// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY
/* Check if the input descriptor is correct */
// #define CONFIG_USBDEV_DESC_CHECK
/* Enable test mode */
// #define CONFIG_USBDEV_TEST_MODE
#ifndef CONFIG_USBDEV_MSC_MAX_LUN
#define CONFIG_USBDEV_MSC_MAX_LUN 1
#endif
#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE
#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512
#endif
#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING
#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING ""
#endif
#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING
#define CONFIG_USBDEV_MSC_PRODUCT_STRING ""
#endif
#ifndef CONFIG_USBDEV_MSC_VERSION_STRING
#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01"
#endif
// #define CONFIG_USBDEV_MSC_THREAD
#ifndef CONFIG_USBDEV_MSC_PRIO
#define CONFIG_USBDEV_MSC_PRIO 4
#endif
#ifndef CONFIG_USBDEV_MSC_STACKSIZE
#define CONFIG_USBDEV_MSC_STACKSIZE 2048
#endif
#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE
#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
#endif
/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/
#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE
#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580
#endif
#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID
#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff
#endif
#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC
#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB"
#endif
#define CONFIG_USBDEV_RNDIS_USING_LWIP
/* ================ USB HOST Stack Configuration ================== */
#define CONFIG_USBHOST_MAX_RHPORTS 8
#define CONFIG_USBHOST_MAX_EXTHUBS 4
#define CONFIG_USBHOST_MAX_EHPORTS 8
#define CONFIG_USBHOST_MAX_INTERFACES 8
#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8
#define CONFIG_USBHOST_MAX_ENDPOINTS 8
#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4
#define CONFIG_USBHOST_MAX_HID_CLASS 4
#define CONFIG_USBHOST_MAX_MSC_CLASS 2
#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1
#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1
#define CONFIG_USBHOST_DEV_NAMELEN 16
#ifndef CONFIG_USBHOST_PSC_PRIO
#define CONFIG_USBHOST_PSC_PRIO 0
#endif
#ifndef CONFIG_USBHOST_PSC_STACKSIZE
#define CONFIG_USBHOST_PSC_STACKSIZE 8192
#endif
//#define CONFIG_USBHOST_GET_STRING_DESC
// #define CONFIG_USBHOST_MSOS_ENABLE
#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE
#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00
#endif
/* Ep0 max transfer buffer */
#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN
#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512
#endif
#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT
#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500
#endif
#ifndef CONFIG_USBHOST_MSC_TIMEOUT
#define CONFIG_USBHOST_MSC_TIMEOUT 0xffffffff
#endif
#ifndef CONFIG_INPUT_MOUSE_WHEEL
#define CONFIG_INPUT_MOUSE_WHEEL
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048)
#endif
#define CONFIG_USBHOST_BLUETOOTH_HCI_H4
// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG
#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE
#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048
#endif
#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE
#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048
#endif
/* ================ USB Device Port Configuration ================*/
#ifndef CONFIG_USBDEV_MAX_BUS
#define CONFIG_USBDEV_MAX_BUS 2 // for now, bus num must be 1 except hpm ip
#endif
#ifndef CONFIG_USBDEV_EP_NUM
#define CONFIG_USBDEV_EP_NUM 8
#endif
/* ---------------- FSDEV Configuration ---------------- */
//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference
/* ---------------- DWC2 Configuration ---------------- */
// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4)
// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
/* ---------------- MUSB Configuration ---------------- */
// #define CONFIG_USB_MUSB_SUNXI
/* ================ USB Host Port Configuration ==================*/
#ifndef CONFIG_USBHOST_MAX_BUS
#define CONFIG_USBHOST_MAX_BUS 2
#endif
#ifndef CONFIG_USBHOST_PIPE_NUM
#define CONFIG_USBHOST_PIPE_NUM 10
#endif
/* ---------------- EHCI Configuration ---------------- */
#define CONFIG_USB_EHCI_HCCR_OFFSET (0x0)
#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024
#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM
#define CONFIG_USB_EHCI_QTD_NUM 3
#define CONFIG_USB_EHCI_ITD_NUM 20
// #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE
// #define CONFIG_USB_EHCI_CONFIGFLAG
// #define CONFIG_USB_EHCI_ISO
// #define CONFIG_USB_EHCI_WITH_OHCI
/* ---------------- OHCI Configuration ---------------- */
#define CONFIG_USB_OHCI_HCOR_OFFSET (0x0)
/* ---------------- XHCI Configuration ---------------- */
#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0)
#ifndef CONFIG_USB_XHCI_ENABLE_SOFT_ISR
#define CONFIG_USB_XHCI_ENABLE_SOFT_ISR 0
#endif
#endif

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port/xhci/phytium/freertos/usb_glue_phytium.c Normal file
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/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
/***************************** Include Files *********************************/
#include <stdio.h>
#include <string.h>
#include "sdkconfig.h"
#include "fassert.h"
#include "finterrupt.h"
#include "fcpu_info.h"
#include "fdebug.h"
#include "fcache.h"
#include "fmemory_pool.h"
#include "usbh_core.h"
/************************** Constant Definitions *****************************/
#define FUSB_MEMP_TOTAL_SIZE SZ_1M
/**************************** Type Definitions *******************************/
#if defined(CONFIG_CHERRY_USB_PORT_XHCI_PLATFROM)
void usb_hc_setup_xhci_interrupt(u32 id);
#endif
#if defined(CONFIG_CHERRY_USB_PORT_XHCI_PCIE)
unsigned long usb_hc_setup_xhci_pcie(struct usbh_bus *bus);
#endif
/************************** Variable Definitions *****************************/
static FMemp memp;
static u8 memp_buf[FUSB_MEMP_TOTAL_SIZE] __attribute__((aligned(8))) = {0};
static u32 memp_ref_cnt = 0;
static void xhci_mem_init(void)
{
if (FT_COMPONENT_IS_READY != memp.is_ready)
{
USB_ASSERT(FT_SUCCESS == FMempInit(&memp, &memp_buf[0], &memp_buf[0] + FUSB_MEMP_TOTAL_SIZE));
}
}
static void xhci_mem_deinit(void)
{
if (FT_COMPONENT_IS_READY == memp.is_ready)
{
FMempDeinit(&memp);
}
}
void *xhci_mem_malloc(size_t align, size_t size)
{
void *result = FMempMallocAlign(&memp, size, align);
if (result)
{
memset(result, 0U, size);
}
return result;
}
void xhci_mem_free(void *ptr)
{
if (NULL != ptr)
{
FMempFree(&memp, ptr);
}
}
void xhci_dcache_sync(void *ptr, size_t len, uint32_t flags)
{
if (flags & XHCI_DCACHE_FLUSH)
{
FCacheDCacheFlushRange((uintptr_t)ptr, len);
}
else if (flags & XHCI_DCACHE_INVALIDATE)
{
FCacheDCacheInvalidateRange((uintptr_t)ptr, len);
}
}
void usb_assert(const char *filename, int linenum)
{
FAssert(filename, linenum, 0xff);
}
extern int vApplicationInIrq(void);
int xPortIsInsideInterrupt(void)
{
return vApplicationInIrq();
}
void usb_hc_low_level_init(struct usbh_bus *bus)
{
if (memp_ref_cnt == 0) {
xhci_mem_init(); /* create memory pool before first bus init */
}
memp_ref_cnt++; /* one more bus is using the memory pool */
if (bus->hcd.reg_base != 0) {
#if defined(CONFIG_CHERRY_USB_PORT_XHCI_PLATFROM)
/* platform XHCI controller */
usb_hc_setup_xhci_interrupt(bus->busid);
#else
USB_LOG_ERR("Platform XHCI not supported !!!\n");
USB_ASSERT(0);
#endif
} else {
#if defined(CONFIG_CHERRY_USB_PORT_XHCI_PCIE)
/* pcie XHCI controller */
bus->hcd.reg_base = usb_hc_setup_xhci_pcie(bus);
bus->busid = 0U; /* only support one pcie lane */
#else
USB_LOG_ERR("Invalid register base !!!\n");
USB_ASSERT(0);
#endif
}
}
void usb_hc_low_level_deinit(struct usbh_bus *bus)
{
memp_ref_cnt--; /* one more bus is leaving */
if (memp_ref_cnt == 0) {
xhci_mem_deinit(); /* release memory pool after the last bus left */
}
}

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port/xhci/phytium/freertos/usb_glue_phytium_pcie.c Normal file
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/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
/***************************** Include Files *********************************/
#include <stdio.h>
#include <string.h>
#include "FreeRTOS.h"
#include "task.h"
#include "sdkconfig.h"
#include "fassert.h"
#include "finterrupt.h"
#include "usbh_core.h"
#if defined(CONFIG_CHERRY_USB_PORT_XHCI_PCIE)
#include "fpcie_ecam.h"
#include "fpcie_ecam_common.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/************************** Variable Definitions *****************************/
static FPcieEcam pcie_device;
static void usb_hc_xhci_pcie_interrupt_handler(void *param)
{
extern void USBH_IRQHandler(uint8_t busid);
USBH_IRQHandler((uint8_t)(uintptr_t)0);
}
static void usb_hc_pcie_intx_init(FPcieEcam *instance_p)
{
u32 cpu_id;
u32 irq_num = FPCIE_ECAM_INTA_IRQ_NUM;
u32 irq_priority = 13U;
(void)GetCpuId(&cpu_id);
USB_LOG_DBG("interrupt num: %d", irq_num);
(void)InterruptSetTargetCpus(irq_num, cpu_id);
InterruptSetPriority(irq_num, irq_priority);
/* register intr callback */
InterruptInstall(irq_num,
FPcieEcamIntxIrqHandler,
&pcie_device,
NULL);
/* enable irq */
InterruptUmask(irq_num);
}
static FError usb_hc_pcie_init(FPcieEcam *pcie_device)
{
FError ret = FT_SUCCESS;
ret = FPcieEcamCfgInitialize(pcie_device, FPcieEcamLookupConfig(FPCIE_ECAM_INSTANCE0), NULL);
if (FT_SUCCESS != ret)
{
return ret;
}
USB_LOG_DBG("\n");
USB_LOG_DBG(" PCI:\n");
USB_LOG_DBG(" B:D:F VID:PID parent_BDF class_code\n");
ret = FPcieEcamEnumerateBus(pcie_device, 0);
if (FT_SUCCESS != ret)
{
return ret;
}
usb_hc_pcie_intx_init(pcie_device); /* register pcie_device intx handler */
return FT_SUCCESS;
}
static FError usb_hc_pcie_install_irq(FPcieEcam *pcie_device, struct usbh_bus *usb, u8 bus, u8 device, u8 function)
{
FError ret = FT_SUCCESS;
FPcieIntxFun intx_fun;
intx_fun.IntxCallBack = usb_hc_xhci_pcie_interrupt_handler;
intx_fun.args = usb;
intx_fun.bus = bus;
intx_fun.device = device;
intx_fun.function = function;
ret = FPcieEcamIntxRegister(pcie_device, bus, device, function, &intx_fun);
if (FT_SUCCESS != ret)
{
USB_LOG_ERR("FPcieIntxRegiterIrqHandler failed.\n");
return ret;
}
return ret;
}
unsigned long usb_hc_setup_xhci_pcie(struct usbh_bus *usb)
{
FError ret = FT_SUCCESS;
s32 host;
u32 bdf;
u32 class;
u16 pci_command;
u8 bus,device,function;
u16 vid, did;
uintptr bar0_addr = 0;
uintptr bar1_addr = 0;
unsigned long usb_base = 0U;
const u32 class_code = FPCI_CLASS_SERIAL_USB_XHCI; /* sub class and base class definition */
u32 config_data;
ret = usb_hc_pcie_init(&pcie_device);
if (FT_SUCCESS != ret)
{
USB_LOG_ERR("FPcieInit failed.\n");
return usb_base;
}
/* find xhci host from pcie_device instance */
for (host = 0; host < pcie_device.scans_bdf_count; host++)
{
bus = pcie_device.scans_bdf[host].bus;
device = pcie_device.scans_bdf[host].device;
function= pcie_device.scans_bdf[host].function;
FPcieEcamReadConfigSpace(&pcie_device,bus,device,function,FPCIE_CCR_REV_CLASSID_REGS,&config_data);
class = config_data >> 8;
if (class == class_code)
{
(void)FPcieEcamReadConfigSpace(&pcie_device,bus,device,function,FPCIE_CCR_ID_REG,&config_data);
vid = FPCIE_CCR_VENDOR_ID_MASK(config_data);
did = FPCIE_CCR_DEVICE_ID_MASK(config_data);
USB_LOG_DBG("xHCI-PCI HOST found !!!, b.d.f = %x.%x.%x\n", bus, device, function);
FPcieEcamReadConfigSpace(&pcie_device,bus,device,function,FPCIE_CCR_BAR_ADDR0_REGS,(u32 *)&bar0_addr);
bar0_addr &= ~0xfff;
#if defined(FAARCH64_USE)
FPcieEcamReadConfigSpace(&pcie_device,bus,device,function,FPCIE_CCR_BAR_ADDR1_REGS,(u32 *)&bar1_addr);
#endif
USB_LOG_DBG("FSataPcieIntrInstall BarAddress %p:%p", bar1_addr, bar0_addr);
if ((0x0 == bar0_addr) && (0x0 == bar1_addr))
{
USB_LOG_ERR("Invalid Bar address");
return usb_base;
}
usb_hc_pcie_install_irq(&pcie_device, usb, bus, device, function);
#if defined(FAARCH64_USE)
usb_base = (bar1_addr << 32U) | bar0_addr;
#else
usb_base = bar0_addr;
#endif
USB_LOG_INFO("xHCI base address: 0x%lx", usb_base);
}
}
return usb_base;
}
#endif

64
port/xhci/phytium/freertos/usb_glue_phytium_plat.c Executable file
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/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
/***************************** Include Files *********************************/
#include <stdio.h>
#include <string.h>
#include "sdkconfig.h"
#include "fassert.h"
#include "finterrupt.h"
#include "fcpu_info.h"
#include "fdebug.h"
#include "fcache.h"
#include "fmemory_pool.h"
#include "usbh_core.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/************************** Variable Definitions *****************************/
static void usb_hc_xhci_interrupt_handler(s32 vector, void *param)
{
extern void USBH_IRQHandler(uint8_t busid);
USBH_IRQHandler((uint8_t)(uintptr_t)param);
}
void usb_hc_setup_xhci_interrupt(u32 id)
{
u32 cpu_id;
u32 irq_num = (id == FUSB3_ID_0) ? FUSB3_0_IRQ_NUM : FUSB3_1_IRQ_NUM;
u32 irq_priority = 13U;
GetCpuId(&cpu_id);
InterruptSetTargetCpus(irq_num, cpu_id);
InterruptSetPriority(irq_num, irq_priority);
/* register intr callback */
InterruptInstall(irq_num,
usb_hc_xhci_interrupt_handler,
(void *)(uintptr_t)id,
NULL);
/* enable irq */
InterruptUmask(irq_num);
}
unsigned long usb_hc_get_register_base(uint32_t id)
{
if (FUSB3_ID_0 == id)
return FUSB3_0_BASE_ADDR + FUSB3_XHCI_OFFSET;
else
return FUSB3_1_BASE_ADDR + FUSB3_XHCI_OFFSET;
}

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/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
#ifndef CHERRYUSB_CONFIG_H
#define CHERRYUSB_CONFIG_H
#include "rtthread.h"
#define CHERRYUSB_VERSION 0x010400
#define CHERRYUSB_VERSION_STR "v1.4.0"
/* ================ USB common Configuration ================ */
#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__)
void *xhci_mem_malloc(size_t align, size_t size);
void xhci_mem_free(void *ptr);
#define XHCI_DCACHE_FLUSH (1 << 0)
#define XHCI_DCACHE_INVALIDATE (1 << 1)
void xhci_dcache_sync(void *ptr, size_t len, uint32_t flags);
unsigned long usb_hc_get_register_base(uint32_t id);
#define usb_malloc(size) xhci_mem_malloc(sizeof(int), size)
#define usb_free(ptr) xhci_mem_free(ptr)
#ifndef CONFIG_USB_DBG_LEVEL
#if defined(CONFIG_LOG_ERROR)
#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR
#elif defined(CONFIG_LOG_WARN)
#define CONFIG_USB_DBG_LEVEL USB_DBG_WARNING
#elif defined(CONFIG_LOG_INFO)
#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO
#elif defined(CONFIG_LOG_DEBUG) || defined(CONFIG_LOG_VERBOS)
#define CONFIG_USB_DBG_LEVEL USB_DBG_LOG
#else
#define CONFIG_USB_DBG_LEVEL USB_DBG_ERROR
#endif
#endif
/* Enable print with color */
#define CONFIG_USB_PRINTF_COLOR_ENABLE
/* data align size when use dma */
#ifndef CONFIG_USB_ALIGN_SIZE
#define CONFIG_USB_ALIGN_SIZE 4
#endif
/* attribute data into no cache ram */
#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable")))
/* ================= USB Device Stack Configuration ================ */
/* Ep0 in and out transfer buffer */
#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN
#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512
#endif
/* Setup packet log for debug */
// #define CONFIG_USBDEV_SETUP_LOG_PRINT
/* Send ep0 in data from user buffer instead of copying into ep0 reqdata
* Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE
*/
// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY
/* Check if the input descriptor is correct */
// #define CONFIG_USBDEV_DESC_CHECK
/* Enable test mode */
// #define CONFIG_USBDEV_TEST_MODE
#ifndef CONFIG_USBDEV_MSC_MAX_LUN
#define CONFIG_USBDEV_MSC_MAX_LUN 1
#endif
#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE
#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512
#endif
#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING
#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING ""
#endif
#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING
#define CONFIG_USBDEV_MSC_PRODUCT_STRING ""
#endif
#ifndef CONFIG_USBDEV_MSC_VERSION_STRING
#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01"
#endif
// #define CONFIG_USBDEV_MSC_THREAD
#ifndef CONFIG_USBDEV_MSC_PRIO
#define CONFIG_USBDEV_MSC_PRIO 4
#endif
#ifndef CONFIG_USBDEV_MSC_STACKSIZE
#define CONFIG_USBDEV_MSC_STACKSIZE 2048
#endif
#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE
#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
#endif
/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/
#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE
#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580
#endif
#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID
#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff
#endif
#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC
#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB"
#endif
#define CONFIG_USBDEV_RNDIS_USING_LWIP
/* ================ USB HOST Stack Configuration ================== */
#define CONFIG_USBHOST_MAX_RHPORTS 8
#define CONFIG_USBHOST_MAX_EXTHUBS 4
#define CONFIG_USBHOST_MAX_EHPORTS 8
#define CONFIG_USBHOST_MAX_INTERFACES 8
#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8
#define CONFIG_USBHOST_MAX_ENDPOINTS 8
#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4
#define CONFIG_USBHOST_MAX_HID_CLASS 4
#define CONFIG_USBHOST_MAX_MSC_CLASS 2
#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1
#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1
#define CONFIG_USBHOST_DEV_NAMELEN 16
#ifndef CONFIG_USBHOST_PSC_PRIO
#define CONFIG_USBHOST_PSC_PRIO 0
#endif
#ifndef CONFIG_USBHOST_PSC_STACKSIZE
#define CONFIG_USBHOST_PSC_STACKSIZE 8192
#endif
//#define CONFIG_USBHOST_GET_STRING_DESC
// #define CONFIG_USBHOST_MSOS_ENABLE
#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE
#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00
#endif
/* Ep0 max transfer buffer */
#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN
#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512
#endif
#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT
#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500
#endif
#ifndef CONFIG_USBHOST_MSC_TIMEOUT
#define CONFIG_USBHOST_MSC_TIMEOUT 0xffffffff
#endif
#ifndef CONFIG_INPUT_MOUSE_WHEEL
#define CONFIG_INPUT_MOUSE_WHEEL
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048)
#endif
/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
*/
#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE
#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048)
#endif
/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE
#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048)
#endif
#define CONFIG_USBHOST_BLUETOOTH_HCI_H4
// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG
#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE
#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048
#endif
#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE
#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048
#endif
/* ================ USB Device Port Configuration ================*/
#ifndef CONFIG_USBDEV_MAX_BUS
#define CONFIG_USBDEV_MAX_BUS 2 // for now, bus num must be 1 except hpm ip
#endif
#ifndef CONFIG_USBDEV_EP_NUM
#define CONFIG_USBDEV_EP_NUM 8
#endif
/* ---------------- FSDEV Configuration ---------------- */
//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference
/* ---------------- DWC2 Configuration ---------------- */
// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4)
// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4)
// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
/* ---------------- MUSB Configuration ---------------- */
// #define CONFIG_USB_MUSB_SUNXI
/* ================ USB Host Port Configuration ==================*/
#ifndef CONFIG_USBHOST_MAX_BUS
#define CONFIG_USBHOST_MAX_BUS 2
#endif
#ifndef CONFIG_USBHOST_PIPE_NUM
#define CONFIG_USBHOST_PIPE_NUM 10
#endif
/* ---------------- EHCI Configuration ---------------- */
#define CONFIG_USB_EHCI_HCCR_OFFSET (0x0)
#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024
#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM
#define CONFIG_USB_EHCI_QTD_NUM 3
#define CONFIG_USB_EHCI_ITD_NUM 20
// #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE
// #define CONFIG_USB_EHCI_CONFIGFLAG
// #define CONFIG_USB_EHCI_ISO
// #define CONFIG_USB_EHCI_WITH_OHCI
/* ---------------- OHCI Configuration ---------------- */
#define CONFIG_USB_OHCI_HCOR_OFFSET (0x0)
/* ---------------- XHCI Configuration ---------------- */
#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0)
#ifndef CONFIG_USB_XHCI_ENABLE_SOFT_ISR
#define CONFIG_USB_XHCI_ENABLE_SOFT_ISR 0
#endif
#endif

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port/xhci/phytium/rt-thread/usb_glue_phytium.c Normal file
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/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
#include "rtthread.h"
#include "usbh_core.h"
#include "usb_config.h"
void usb_hc_setup_xhci_interrupt(uint32_t id);
void usb_hc_revoke_xhci_interrupt(uint32_t id);
void *xhci_mem_malloc(size_t align, size_t size)
{
void *result = rt_malloc_align(size, align);
if (result)
{
memset(result, 0U, size);
}
return result;
}
void xhci_mem_free(void *ptr)
{
if (NULL != ptr)
{
rt_free(ptr);
}
}
void xhci_dcache_sync(void *ptr, size_t len, uint32_t flags)
{
if (flags & XHCI_DCACHE_FLUSH)
{
rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, ptr, len);
}
else if (flags & XHCI_DCACHE_INVALIDATE)
{
rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, ptr, len);
}
}
void usb_assert(const char *filename, int linenum)
{
rt_assert_handler("", filename, linenum);
}
void usb_hc_low_level_init(struct usbh_bus *bus)
{
/* platform XHCI controller */
usb_hc_setup_xhci_interrupt(bus->busid);
}
void usb_hc_low_level_deinit(struct usbh_bus *bus)
{
usb_hc_revoke_xhci_interrupt(bus->busid);
}

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port/xhci/phytium/rt-thread/usb_glue_phytium_plat.c Normal file
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/*
* Copyright : (C) 2024 Phytium Information Technology, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2024/6/26 first commit
*/
#include "rtthread.h"
#include "interrupt.h"
#include "fparameters.h"
void USBH_IRQHandler(uint8_t busid);
static void usb_hc_xhci_interrupt_handler(int irqno, void *param)
{
if (irqno == FUSB3_0_IRQ_NUM) {
USBH_IRQHandler(FUSB3_ID_0);
} else if (irqno == FUSB3_1_IRQ_NUM) {
USBH_IRQHandler(FUSB3_ID_1);
}
}
void usb_hc_setup_xhci_interrupt(uint32_t id)
{
uint32_t irq_num = (id == FUSB3_ID_0) ? FUSB3_0_IRQ_NUM : FUSB3_1_IRQ_NUM;
rt_hw_interrupt_set_priority(irq_num, 0xd0);
rt_hw_interrupt_install(irq_num, usb_hc_xhci_interrupt_handler,
NULL, "xhci");
rt_hw_interrupt_umask(irq_num);
}
void usb_hc_revoke_xhci_interrupt(uint32_t id)
{
uint32_t irq_num = (id == FUSB3_ID_0) ? FUSB3_0_IRQ_NUM : FUSB3_1_IRQ_NUM;
rt_hw_interrupt_mask(irq_num);
}
unsigned long usb_hc_get_register_base(uint32_t id)
{
if (FUSB3_ID_0 == id)
return FUSB3_0_BASE_ADDR + FUSB3_XHCI_OFFSET;
else
return FUSB3_1_BASE_ADDR + FUSB3_XHCI_OFFSET;
}