diff --git a/Kconfig.cherryusb b/Kconfig.cherryusb index 738bc0e2..4d44a750 100644 --- a/Kconfig.cherryusb +++ b/Kconfig.cherryusb @@ -36,12 +36,16 @@ if CHERRYUSB bool "dwc2_at" config CHERRYUSB_DEVICE_DWC2_GD bool "dwc2_gd" + config CHERRYUSB_DEVICE_DWC2_HC + bool "dwc2_hc" config CHERRYUSB_DEVICE_DWC2_CUSTOM bool "dwc2_custom" - config CHERRYUSB_DEVICE_MUSB_STANDARD - bool "musb_standard" + config CHERRYUSB_DEVICE_MUSB_ES + bool "musb_es" config CHERRYUSB_DEVICE_MUSB_SUNXI bool "musb_sunxi" + config CHERRYUSB_DEVICE_MUSB_BK + bool "musb_bk" config CHERRYUSB_DEVICE_MUSB_CUSTOM bool "musb_custom" config CHERRYUSB_DEVICE_BL @@ -168,12 +172,16 @@ if CHERRYUSB bool "dwc2_st" config CHERRYUSB_HOST_DWC2_ESP bool "dwc2_esp" + config CHERRYUSB_HOST_DWC2_HC + bool "dwc2_hc" config CHERRYUSB_HOST_DWC2_CUSTOM bool "dwc2_custom" - config CHERRYUSB_HOST_MUSB_STANDARD - bool "musb_standard" + config CHERRYUSB_HOST_MUSB_ES + bool "musb_es" config CHERRYUSB_HOST_MUSB_SUNXI bool "musb_sunxi" + config CHERRYUSB_HOST_MUSB_BK + bool "musb_bk" config CHERRYUSB_HOST_MUSB_CUSTOM bool "musb_custom" config CHERRYUSB_HOST_PUSB2 diff --git a/cherryusb.cmake b/cherryusb.cmake index 6a78e9dc..d8451d21 100644 --- a/cherryusb.cmake +++ b/cherryusb.cmake @@ -71,26 +71,39 @@ if(CONFIG_CHERRYUSB_DEVICE) endif() if(DEFINED CONFIG_CHERRYUSB_DEVICE_DCD) - if("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "dwc2_st") + if("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "fsdev") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/fsdev/usb_dc_fsdev.c) + elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "dwc2_st") list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_dc_dwc2.c) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_glue_st.c) elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "dwc2_esp") list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_dc_dwc2.c) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_glue_esp.c) - elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "dwc2_aic") - list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_dc_dwc2.c) - list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_glue_aic.c) elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "dwc2_at") list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_dc_dwc2.c) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_glue_at.c) - elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "fsdev") - list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/fsdev/usb_dc_fsdev.c) + elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "dwc2_gd") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_dc_dwc2.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_glue_gd.c) + elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "dwc2_hc") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_dc_dwc2.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_glue_hc.c) + elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "musb_es") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_dc_musb.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_glue_es.c) + elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "musb_sunxi") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_dc_musb.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_glue_sunxi.c) + elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "musb_bk") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_dc_musb.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_glue_bk.c) elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "hpm") list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/hpm/usb_dc_hpm.c) elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "bl") list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/bouffalolab/usb_dc_bl.c) - elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "musb") - list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_dc_musb.c) + elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "aic") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/aic/usb_dc_aic.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/aic/usb_dc_aic_ll.c) endif() endif() @@ -223,8 +236,18 @@ if(CONFIG_CHERRYUSB_HOST) elseif("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "dwc2_esp") list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_hc_dwc2.c) list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_glue_esp.c) - elseif("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "musb") + elseif("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "dwc2_hc") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_hc_dwc2.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_glue_hc.c) + elseif("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "musb_es") list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_hc_musb.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_glue_es.c) + elseif("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "musb_sunxi") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_hc_musb.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_glue_sunxi.c) + elseif("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "musb_bk") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_hc_musb.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_glue_bk.c) endif() endif() diff --git a/port/musb/README.md b/port/musb/README.md index d11e256c..ad2a527f 100644 --- a/port/musb/README.md +++ b/port/musb/README.md @@ -2,7 +2,7 @@ ## Support Chip List -### ES32 +### Eastsoft - ES32F3xx @@ -17,7 +17,3 @@ ### AllwinnerTech - F1Cxxx, F2Cxxx - -### HEZHOU - -- AIR105 diff --git a/port/musb/usb_dc_musb.c b/port/musb/usb_dc_musb.c index 4dd3342c..d66ec39e 100644 --- a/port/musb/usb_dc_musb.c +++ b/port/musb/usb_dc_musb.c @@ -78,10 +78,6 @@ #define USB_FIFO_BASE(ep_idx) (USB_BASE + MUSB_FIFO_OFFSET + 0x4 * ep_idx) -#ifndef CONFIG_USBDEV_EP_NUM -#define CONFIG_USBDEV_EP_NUM 8 -#endif - typedef enum { USB_EP0_STATE_SETUP = 0x0, /**< SETUP DATA */ USB_EP0_STATE_IN_DATA = 0x1, /**< IN DATA */ @@ -106,7 +102,6 @@ struct musb_ep_state { /* Driver state */ struct musb_udc { volatile uint8_t dev_addr; - volatile uint32_t fifo_size_offset; __attribute__((aligned(32))) struct usb_setup_packet setup; struct musb_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/ struct musb_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */ @@ -204,6 +199,40 @@ static uint32_t musb_get_fifo_size(uint16_t mps, uint16_t *used) return USB_TXFIFOSZ_SIZE_8; } +static uint32_t usbd_musb_fifo_config(struct musb_fifo_cfg *cfg, uint32_t offset) +{ + uint16_t fifo_used; + uint8_t c_size; + uint16_t c_off; + + c_off = offset >> 3; + c_size = musb_get_fifo_size(cfg->maxpacket, &fifo_used); + + musb_set_active_ep(cfg->ep_num); + + switch (cfg->style) { + case FIFO_TX: + HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = c_size & 0x0f; + HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = c_off; + break; + case FIFO_RX: + HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = c_size & 0x0f; + HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = c_off; + break; + case FIFO_TXRX: + HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = c_size & 0x0f; + HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = c_off; + HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = c_size & 0x0f; + HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = c_off; + break; + + default: + break; + } + + return (offset + fifo_used); +} + __WEAK void usb_dc_low_level_init(void) { } @@ -214,6 +243,10 @@ __WEAK void usb_dc_low_level_deinit(void) int usb_dc_init(uint8_t busid) { + uint16_t offset = 0; + uint8_t cfg_num; + struct musb_fifo_cfg *cfg; + usb_dc_low_level_init(); #ifdef CONFIG_USB_HS @@ -227,6 +260,18 @@ int usb_dc_init(uint8_t busid) HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) |= USB_DEVCTL_SESSION; + cfg_num = usbd_get_musb_fifo_cfg(&cfg); + + for (uint8_t i = 0; i < cfg_num; i++) { + offset = usbd_musb_fifo_config(&cfg[i], offset); + } + + if (offset > usb_get_musb_ram_size()) { + USB_LOG_ERR("offset:%d is overflow, please check your table\r\n", offset); + while (1) { + } + } + /* Enable USB interrupts */ HWREGB(USB_BASE + MUSB_IE_OFFSET) = USB_IE_RESET; HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = USB_TXIE_EP0; @@ -267,8 +312,6 @@ uint8_t usbd_get_port_speed(uint8_t busid) int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) { - uint16_t used = 0; - uint16_t fifo_size = 0; uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); uint8_t old_ep_idx; uint32_t ui32Flags = 0; @@ -297,6 +340,11 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) g_musb_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); g_musb_udc.out_ep[ep_idx].ep_enable = true; + if ((8 << HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET)) < g_musb_udc.out_ep[ep_idx].ep_mps) { + USB_LOG_ERR("Ep %02x fifo is overflow\r\n", ep->bEndpointAddress); + return -2; + } + HWREGH(USB_BASE + MUSB_IND_RXMAP_OFFSET) = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); // @@ -336,18 +384,16 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = (USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH); else HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = USB_RXCSRL1_CLRDT; - - fifo_size = musb_get_fifo_size(USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize), &used); - - HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = fifo_size & 0x0f; - HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = (g_musb_udc.fifo_size_offset >> 3); - - g_musb_udc.fifo_size_offset += used; } else { g_musb_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); g_musb_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); g_musb_udc.in_ep[ep_idx].ep_enable = true; + if ((8 << HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET)) < g_musb_udc.in_ep[ep_idx].ep_mps) { + USB_LOG_ERR("Ep %02x fifo is overflow\r\n", ep->bEndpointAddress); + return -2; + } + HWREGH(USB_BASE + MUSB_IND_TXMAP_OFFSET) = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); // @@ -381,13 +427,6 @@ int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH); else HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_CLRDT; - - fifo_size = musb_get_fifo_size(USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize), &used); - - HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = fifo_size & 0x0f; - HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = (g_musb_udc.fifo_size_offset >> 3); - - g_musb_udc.fifo_size_offset += used; } musb_set_active_ep(old_ep_idx); @@ -656,18 +695,10 @@ void USBD_IRQHandler(uint8_t busid) /* Receive a reset signal from the USB bus */ if (is & USB_IS_RESET) { memset(&g_musb_udc, 0, sizeof(struct musb_udc)); - g_musb_udc.fifo_size_offset = USB_CTRL_EP_MPS; usbd_event_reset_handler(0); HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = USB_TXIE_EP0; HWREGH(USB_BASE + MUSB_RXIE_OFFSET) = 0; - for (uint8_t i = 1; i < CONFIG_USBDEV_EP_NUM; i++) { - musb_set_active_ep(i); - HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = 0; - HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = 0; - HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = 0; - HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = 0; - } usb_ep0_state = USB_EP0_STATE_SETUP; } diff --git a/port/musb/usb_glue_bk.c b/port/musb/usb_glue_bk.c new file mode 100644 index 00000000..7eb987f9 --- /dev/null +++ b/port/musb/usb_glue_bk.c @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "sys_driver.h" +#include "gpio_driver.h" +#include +#include +#include +#include "bk_misc.h" +#include "usbd_core.h" +#include "usbh_core.h" +#include "usb_musb_reg.h" + +#define USB_BASE_ADDR SOC_USB_REG_BASE + +#if (CONFIG_SOC_BK7271) +#define REG_AHB2_USB_OTG_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x80))) +#define REG_AHB2_USB_DMA_ENDP (*((volatile unsigned char *)(USB_BASE_ADDR + 0x84))) +#define REG_AHB2_USB_VTH (*((volatile unsigned char *)(USB_BASE_ADDR + 0x88))) +#define REG_AHB2_USB_GEN (*((volatile unsigned char *)(USB_BASE_ADDR + 0x8C))) +#define REG_AHB2_USB_STAT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x90))) +#define REG_AHB2_USB_INT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x94))) +#define REG_AHB2_USB_RESET (*((volatile unsigned char *)(USB_BASE_ADDR + 0x98))) +#define REG_AHB2_USB_DEV_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x9C))) +#elif (CONFIG_SOC_BK7256XX) +#define REG_AHB2_USB_OTG_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x280))) +#define REG_AHB2_USB_DMA_ENDP (*((volatile unsigned char *)(USB_BASE_ADDR + 0x284))) +#define REG_AHB2_USB_VTH (*((volatile unsigned char *)(USB_BASE_ADDR + 0x288))) +#define REG_AHB2_USB_GEN (*((volatile unsigned char *)(USB_BASE_ADDR + 0x28C))) +#define REG_AHB2_USB_STAT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x290))) +#define REG_AHB2_USB_INT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x294))) +#define REG_AHB2_USB_RESET (*((volatile unsigned char *)(USB_BASE_ADDR + 0x298))) +#define REG_AHB2_USB_DEV_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x29C))) +#elif (CONFIG_SOC_BK7236XX) || (CONFIG_SOC_BK7239XX) || (CONFIG_SOC_BK7286XX) +#define REG_AHB2_USB_DEVICE_ID (*((volatile unsigned char *)(USB_BASE_ADDR + 0x280))) +#define REG_AHB2_USB_VERSION_ID (*((volatile unsigned char *)(USB_BASE_ADDR + 0x284))) +#define REG_AHB2_USB_GLOBAL_CTRL (*((volatile unsigned char *)(USB_BASE_ADDR + 0x288))) +#define REG_AHB2_USB_DEVICE_STATUS (*((volatile unsigned char *)(USB_BASE_ADDR + 0x28c))) +#define REG_AHB2_USB_OTG_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x290))) +#define REG_AHB2_USB_DMA_ENDP (*((volatile unsigned char *)(USB_BASE_ADDR + 0x294))) +#define REG_AHB2_USB_VTH (*((volatile unsigned char *)(USB_BASE_ADDR + 0x298))) +#define REG_AHB2_USB_GEN (*((volatile unsigned char *)(USB_BASE_ADDR + 0x29C))) +#define REG_AHB2_USB_STAT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x2A0))) +#define REG_AHB2_USB_INT (*((volatile unsigned char *)(USB_BASE_ADDR + 0x2A4))) +#define REG_AHB2_USB_RESET (*((volatile unsigned char *)(USB_BASE_ADDR + 0x2A8))) +#define REG_AHB2_USB_DEV_CFG (*((volatile unsigned char *)(USB_BASE_ADDR + 0x2AC))) + +#define REG_USB_USR_700 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x700))) +#define REG_USB_USR_704 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x704))) +#define REG_USB_USR_708 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x708))) +#define REG_USB_USR_70C (*((volatile unsigned long *)(USB_BASE_ADDR + 0x70C))) +#define REG_USB_USR_710 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x710))) +#define REG_USB_USR_714 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x714))) +#define REG_USB_PHY_00 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x400))) +#define REG_USB_PHY_01 (*((volatile unsigned long *)(USB_BASE_ADDR + 0x404))) +#endif + +#define USB_DP_CAPABILITY_VALUE (0xF) +#define USB_DN_CAPABILITY_VALUE (0xF) + +#define NANENG_PHY_FC_REG01 (0x01 * 4) +#define NANENG_PHY_FC_REG02 (0x02 * 4) +#define NANENG_PHY_FC_REG03 (0x03 * 4) +#define NANENG_PHY_FC_REG04 (0x04 * 4) +#define NANENG_PHY_FC_REG05 (0x05 * 4) +#define NANENG_PHY_FC_REG06 (0x06 * 4) +#define NANENG_PHY_FC_REG07 (0x07 * 4) +#define NANENG_PHY_FC_REG08 (0x08 * 4) +#define NANENG_PHY_FC_REG09 (0x09 * 4) +#define NANENG_PHY_FC_REG0A (0x0A * 4) +#define NANENG_PHY_FC_REG0B (0x0B * 4) +#define NANENG_PHY_FC_REG0C (0x0C * 4) +#define NANENG_PHY_FC_REG0D (0x0D * 4) +#define NANENG_PHY_FC_REG0E (0x0E * 4) +#define NANENG_PHY_FC_REG0F (0x0F * 4) +#define NANENG_PHY_FC_REG0F_BYTE 0x0F + +#define NANENG_PHY_FC_REG10 (0x10 * 4) +#define NANENG_PHY_FC_REG11 (0x11 * 4) +#define NANENG_PHY_FC_REG12 (0x12 * 4) +#define NANENG_PHY_FC_REG13 (0x13 * 4) +#define NANENG_PHY_FC_REG14 (0x14 * 4) +#define NANENG_PHY_FC_REG15 (0x15 * 4) +#define NANENG_PHY_FC_REG16 (0x16 * 4) +#define NANENG_PHY_FC_REG17 (0x17 * 4) +#define NANENG_PHY_FC_REG18 (0x18 * 4) +#define NANENG_PHY_FC_REG19 (0x19 * 4) +#define NANENG_PHY_FC_REG1A (0x1A * 4) +#define NANENG_PHY_FC_REG1B (0x1B * 4) +#define NANENG_PHY_FC_REG1C (0x1C * 4) +#define NANENG_PHY_FC_REG1D (0x1D * 4) +#define NANENG_PHY_FC_REG1E (0x1E * 4) +#define NANENG_PHY_FC_REG1F (0x1F * 4) + +#if CONFIG_USBDEV_EP_NUM != 8 +#error beken chips only support 8 endpoints +#endif + +#if CONFIG_USBHOST_PIPE_NUM != 8 +#error beken chips only support 8 pipes +#endif + +// clang-format off +static struct musb_fifo_cfg musb_device_table[] = { +{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, }, +{ .ep_num = 1, .style = FIFO_TX, .maxpacket = 1024, }, +{ .ep_num = 1, .style = FIFO_RX, .maxpacket = 1024, }, +{ .ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 6, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 7, .style = FIFO_TXRX, .maxpacket = 512, } +}; + +static struct musb_fifo_cfg musb_host_table[] = { +{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, }, +{ .ep_num = 1, .style = FIFO_TX, .maxpacket = 1024, }, +{ .ep_num = 1, .style = FIFO_RX, .maxpacket = 1024, }, +{ .ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 6, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 7, .style = FIFO_TXRX, .maxpacket = 512, } +}; +// clang-format on + +uint8_t usbd_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = musb_device_table; + return sizeof(musb_device_table) / sizeof(musb_device_table[0]); +} + +uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = musb_host_table; + return sizeof(musb_host_table) / sizeof(musb_host_table[0]); +} + +uint32_t usb_get_musb_ram_size(void) +{ + return 8192; +} + +extern void USBD_IRQHandler(uint8_t busid); + +void USBD_IRQ(void) +{ + USBD_IRQHandler(0); +} + +static void bk_analog_layer_usb_sys_related_ops(uint32_t usb_mode, bool ops) +{ + extern void delay(INT32 num); + +#if 0 + sys_drv_usb_analog_phy_en(ops, NULL); + sys_drv_usb_analog_speed_en(ops, NULL); + sys_drv_usb_analog_ckmcu_en(ops, NULL); +#endif + if (ops) { + sys_drv_usb_clock_ctrl(true, NULL); + delay(100); +#if 0 + sys_drv_usb_analog_deepsleep_en(false); +#endif + sys_drv_usb_analog_dp_capability(USB_DP_CAPABILITY_VALUE); + sys_drv_usb_analog_dn_capability(USB_DN_CAPABILITY_VALUE); + if (!sys_hal_psram_ldo_status()) { + sys_drv_psram_ldo_enable(1); + } + sys_drv_usb_analog_phy_en(1, NULL); + + if (usb_mode == 0) { + REG_USB_USR_708 = 0x0; + REG_USB_USR_710 &= ~(0x1 << 7); + delay(100); + + REG_USB_USR_710 |= (0x1 << 15); + //REG_USB_USR_710 |= (0x1<<14); + REG_USB_USR_710 |= (0x1 << 16); + REG_USB_USR_710 |= (0x1 << 17); + REG_USB_USR_710 |= (0x1 << 18); + REG_USB_USR_710 |= (0x1 << 19); + REG_USB_USR_710 &= ~(0x1 << 20); + REG_USB_USR_710 |= (0x1 << 21); + REG_USB_USR_710 |= (0x0 << 0); + REG_USB_USR_710 |= (0x1 << 5); + REG_USB_USR_710 |= (0x1 << 6); + REG_USB_USR_710 |= (0x1 << 9); + REG_USB_USR_710 |= (0x1 << 10); + REG_USB_USR_710 |= (0x1 << 1); + + REG_USB_USR_710 |= (0x1 << 7); + REG_USB_USR_708 = 0x1; +#if 0 + REG_USB_PHY_00 = 0x08; + REG_USB_PHY_01 = 0x02; + REG_USB_USR_710 |= (0x1<< 8); + while(1){ + reg = REG_USB_USR_70C; + if(reg & 0x100){ + USB_DRIVER_LOGI("SelfTest Fin!\r\n"); + USB_DRIVER_LOGI("test end!\r\n"); + break; + } else { + USB_DRIVER_LOGI("70c_reg:0x%x\r\n", reg); + delay(10000); + } + } + REG_USB_PHY_00 &= ~0x08; + REG_USB_PHY_01 &= ~0x02; + REG_USB_USR_710 &= ~(0x1<< 8); +#endif + } else { + REG_USB_USR_710 |= (0x1 << 15); + REG_USB_USR_710 |= (0x1 << 14); + REG_USB_USR_710 |= (0x1 << 16); + REG_USB_USR_710 |= (0x1 << 17); + REG_USB_USR_710 |= (0x1 << 18); + REG_USB_USR_710 |= (0x1 << 19); + REG_USB_USR_710 &= ~(0x1 << 20); + REG_USB_USR_710 |= (0x1 << 21); + REG_USB_USR_710 |= (0x0 << 0); + REG_USB_USR_710 |= (0x1 << 5); + REG_USB_USR_710 |= (0x1 << 6); + REG_USB_USR_710 |= (0x1 << 9); + REG_USB_USR_710 |= (0x1 << 10); + REG_USB_USR_710 |= (0x1 << 7); + + REG_USB_USR_708 = 0x1; + } + } else { + sys_drv_usb_analog_phy_en(0, NULL); + sys_drv_usb_clock_ctrl(false, NULL); + } +} + +void usb_dc_low_level_init(void) +{ +#if CONFIG_SYS_CPU0 + bk_pm_module_vote_sleep_ctrl(PM_SLEEP_MODULE_NAME_USB_1, 0x0, 0x0); +#endif + bk_analog_layer_usb_sys_related_ops(1, true); + bk_gpio_set_output_high(CONFIG_USB_VBAT_CONTROL_GPIO_ID); + + bk_pm_module_vote_cpu_freq(PM_DEV_ID_USB_1, PM_CPU_FRQ_120M); + + sys_hal_usb_analog_phy_en(true); + + sys_drv_usb_clock_ctrl(true, NULL); + sys_drv_int_enable(USB_INTERRUPT_CTRL_BIT); + + bk_int_isr_register(INT_SRC_USB, USBD_IRQ, NULL); + bk_int_set_priority(INT_SRC_USB, 2); +} + +void usb_dc_low_level_deinit(void) +{ + bk_pm_module_vote_cpu_freq(PM_DEV_ID_USB_1, PM_CPU_FRQ_DEFAULT); + sys_hal_usb_analog_phy_en(false); + sys_drv_usb_clock_ctrl(false, NULL); + sys_drv_int_disable(USB_INTERRUPT_CTRL_BIT); + bk_int_isr_unregister(INT_SRC_USB); + bk_analog_layer_usb_sys_related_ops(1, false); + sys_drv_dev_clk_pwr_up(CLK_PWR_ID_USB_1, CLK_PWR_CTRL_PWR_DOWN); +} + +extern void USBH_IRQHandler(uint8_t busid); + +void USBH_IRQ(void) +{ + USBH_IRQHandler(0); +} + +#define NANENG_PHY_CFG 1 +#define USB_PHY_BASE (SOC_USB_REG_BASE + 0x400) + +#define HWREG(x) \ + (*((volatile uint32_t *)(x))) +#define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +#define HWREGB(x) \ + (*((volatile uint8_t *)(x))) + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ +#if CONFIG_SYS_CPU0 + bk_pm_module_vote_sleep_ctrl(PM_SLEEP_MODULE_NAME_USB_1, 0x0, 0x0); +#endif + bk_analog_layer_usb_sys_related_ops(0, true); + bk_gpio_set_output_high(CONFIG_USB_VBAT_CONTROL_GPIO_ID); + +#if NANENG_PHY_CFG + //NANENG_PHY_CFG_HSRX_TEST + HWREGB(USB_PHY_BASE + NANENG_PHY_FC_REG0F) |= (0x1 << 4); + //disconnect value 640mv + HWREGB(USB_PHY_BASE + NANENG_PHY_FC_REG0B) = 0x7C; +#endif + bk_int_isr_register(INT_SRC_USB, USBH_IRQ, NULL); + sys_drv_int_enable(USB_INTERRUPT_CTRL_BIT); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + sys_drv_int_disable(USB_INTERRUPT_CTRL_BIT); + bk_int_isr_unregister(INT_SRC_USB); + sys_drv_dev_clk_pwr_up(CLK_PWR_ID_USB_1, CLK_PWR_CTRL_PWR_DOWN); + bk_analog_layer_usb_sys_related_ops(0, false); +} \ No newline at end of file diff --git a/port/musb/usb_glue_es.c b/port/musb/usb_glue_es.c new file mode 100644 index 00000000..adfc293c --- /dev/null +++ b/port/musb/usb_glue_es.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_config.h" +#include "stdint.h" +#include "usb_musb_reg.h" + +#if CONFIG_USBDEV_EP_NUM != 6 +#error es32 chips only support 6 endpoints +#endif + +#if CONFIG_USBHOST_PIPE_NUM != 6 +#error es32 chips only support 6 pipes +#endif + +// clang-format off +static struct musb_fifo_cfg musb_device_table[] = { +{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, }, +{ .ep_num = 1, .style = FIFO_TXRX, .maxpacket = 1024, }, +{ .ep_num = 2, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 4, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 5, .style = FIFO_TXRX, .maxpacket = 512, }, +}; + +static struct musb_fifo_cfg musb_host_table[] = { +{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, }, +{ .ep_num = 1, .style = FIFO_TXRX, .maxpacket = 1024, }, +{ .ep_num = 2, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 4, .style = FIFO_TXRX, .maxpacket = 512, }, +{ .ep_num = 5, .style = FIFO_TXRX, .maxpacket = 512, }, +}; +// clang-format on + +uint8_t usbd_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = musb_device_table; + return sizeof(musb_device_table) / sizeof(musb_device_table[0]); +} + +uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = musb_host_table; + return sizeof(musb_host_table) / sizeof(musb_host_table[0]); +} + +uint32_t usb_get_musb_ram_size(void) +{ + return 4096; +} \ No newline at end of file diff --git a/port/musb/usb_glue_sunxi.c b/port/musb/usb_glue_sunxi.c index 62074a6c..43392304 100644 --- a/port/musb/usb_glue_sunxi.c +++ b/port/musb/usb_glue_sunxi.c @@ -4,7 +4,56 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "usb_config.h" +#include "stdint.h" +#include "usb_musb_reg.h" #ifndef CONFIG_USB_MUSB_SUNXI #error must define CONFIG_USB_MUSB_SUNXI when use sunxi chips -#endif \ No newline at end of file +#endif + +#if CONFIG_USBDEV_EP_NUM != 4 +#error sunxi chips only support 4 endpoints +#endif + +#if CONFIG_USBHOST_PIPE_NUM != 4 +#error sunxi chips only support 4 pipes +#endif + +// clang-format off +static struct musb_fifo_cfg musb_device_table[] = { +{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, }, +{ .ep_num = 1, .style = FIFO_TX, .maxpacket = 1024, }, +{ .ep_num = 1, .style = FIFO_RX, .maxpacket = 1024, }, +{ .ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, +}; + +static struct musb_fifo_cfg musb_host_table[] = { +{ .ep_num = 0, .style = FIFO_TXRX, .maxpacket = 64, }, +{ .ep_num = 1, .style = FIFO_TX, .maxpacket = 1024, }, +{ .ep_num = 1, .style = FIFO_RX, .maxpacket = 1024, }, +{ .ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, +{ .ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, +}; +// clang-format on + +uint8_t usbd_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = musb_device_table; + return sizeof(musb_device_table) / sizeof(musb_device_table[0]); +} + +uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg) +{ + *cfg = musb_host_table; + return sizeof(musb_host_table) / sizeof(musb_host_table[0]); +} + +uint32_t usb_get_musb_ram_size(void) +{ + return 8192; +} \ No newline at end of file diff --git a/port/musb/usb_hc_musb.c b/port/musb/usb_hc_musb.c index f54db3a5..a59e1693 100644 --- a/port/musb/usb_hc_musb.c +++ b/port/musb/usb_hc_musb.c @@ -16,10 +16,6 @@ #define USB_BASE (bus->hcd.reg_base) -#if CONFIG_USBHOST_PIPE_NUM != 4 -#error musb host ip only supports 4 pipe num -#endif - #ifdef CONFIG_USB_MUSB_SUNXI #define MUSB_FADDR_OFFSET 0x98 #define MUSB_POWER_OFFSET 0x40 @@ -124,10 +120,6 @@ #define USB_FIFO_BASE(ep_idx) (USB_BASE + MUSB_FIFO_OFFSET + 0x4 * ep_idx) -#ifndef CONIFG_USB_MUSB_PIPE_NUM -#define CONIFG_USB_MUSB_PIPE_NUM 5 -#endif - typedef enum { USB_EP0_STATE_SETUP = 0x0, /**< SETUP DATA */ USB_EP0_STATE_IN_DATA, /**< IN DATA */ @@ -243,6 +235,56 @@ static void musb_read_packet(struct usbh_bus *bus, uint8_t ep_idx, uint8_t *buff } } +static uint32_t musb_get_fifo_size(uint16_t mps, uint16_t *used) +{ + uint32_t size; + + for (uint8_t i = USB_TXFIFOSZ_SIZE_8; i <= USB_TXFIFOSZ_SIZE_2048; i++) { + size = (8 << i); + if (mps <= size) { + *used = size; + return i; + } + } + + *used = 0; + return USB_TXFIFOSZ_SIZE_8; +} + +static uint32_t usbh_musb_fifo_config(struct usbh_bus *bus, struct musb_fifo_cfg *cfg, uint32_t offset) +{ + uint16_t fifo_used; + uint8_t c_size; + uint16_t c_off; + + c_off = offset >> 3; + c_size = musb_get_fifo_size(cfg->maxpacket, &fifo_used); + + musb_set_active_ep(bus, cfg->ep_num); + + switch (cfg->style) { + case FIFO_TX: + HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = c_size & 0x0f; + HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = c_off; + break; + case FIFO_RX: + HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = c_size & 0x0f; + HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = c_off; + break; + case FIFO_TXRX: + HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = c_size & 0x0f; + HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = c_off; + HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = c_size & 0x0f; + HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = c_off; + break; + + default: + break; + } + + return (offset + fifo_used); +} + void musb_control_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, struct usb_setup_packet *setup, uint8_t *buffer, uint32_t buflen) { uint8_t old_ep_index; @@ -269,7 +311,7 @@ void musb_control_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb musb_set_active_ep(bus, old_ep_index); } -void musb_bulk_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen) +int musb_bulk_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen) { uint8_t old_ep_index; uint8_t speed = USB_TXTYPE1_SPEED_FULL; @@ -286,6 +328,11 @@ void musb_bulk_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *ur } if (urb->ep->bEndpointAddress & 0x80) { + if ((8 << HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET)) < USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + USB_LOG_ERR("Ep %02x fifo is overflow\r\n", urb->ep->bEndpointAddress); + return -USB_ERR_RANGE; + } + HWREGB(USB_RXADDR_BASE(chidx)) = urb->hport->dev_addr; HWREGB(USB_BASE + MUSB_IND_RXTYPE_OFFSET) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; HWREGB(USB_BASE + MUSB_IND_RXINTERVAL_OFFSET) = 0; @@ -296,6 +343,11 @@ void musb_bulk_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *ur HWREGH(USB_BASE + MUSB_RXIE_OFFSET) |= (1 << chidx); } else { + if ((8 << HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET)) < USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + USB_LOG_ERR("Ep %02x fifo is overflow\r\n", urb->ep->bEndpointAddress); + return -USB_ERR_RANGE; + } + HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; HWREGB(USB_BASE + MUSB_IND_TXTYPE_OFFSET) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; HWREGB(USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) = 0; @@ -313,9 +365,10 @@ void musb_bulk_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *ur HWREGH(USB_BASE + MUSB_TXIE_OFFSET) |= (1 << chidx); } musb_set_active_ep(bus, old_ep_index); + return 0; } -void musb_intr_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen) +int musb_intr_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen) { uint8_t old_ep_index; uint8_t speed = USB_TXTYPE1_SPEED_FULL; @@ -332,6 +385,11 @@ void musb_intr_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *ur } if (urb->ep->bEndpointAddress & 0x80) { + if ((8 << HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET)) < USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + USB_LOG_ERR("Ep %02x fifo is overflow\r\n", urb->ep->bEndpointAddress); + return -USB_ERR_RANGE; + } + HWREGB(USB_RXADDR_BASE(chidx)) = urb->hport->dev_addr; HWREGB(USB_BASE + MUSB_IND_RXTYPE_OFFSET) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; HWREGB(USB_BASE + MUSB_IND_RXINTERVAL_OFFSET) = urb->ep->bInterval; @@ -342,6 +400,11 @@ void musb_intr_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *ur HWREGH(USB_BASE + MUSB_RXIE_OFFSET) |= (1 << chidx); } else { + if ((8 << HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET)) < USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + USB_LOG_ERR("Ep %02x fifo is overflow\r\n", urb->ep->bEndpointAddress); + return -USB_ERR_RANGE; + } + HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; HWREGB(USB_BASE + MUSB_IND_TXTYPE_OFFSET) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; HWREGB(USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) = urb->ep->bInterval; @@ -359,6 +422,7 @@ void musb_intr_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *ur HWREGH(USB_BASE + MUSB_TXIE_OFFSET) |= (1 << chidx); } musb_set_active_ep(bus, old_ep_index); + return 0; } static int usbh_reset_port(struct usbh_bus *bus, const uint8_t port) @@ -420,7 +484,9 @@ __WEAK void usb_hc_low_level_deinit(struct usbh_bus *bus) int usb_hc_init(struct usbh_bus *bus) { uint8_t regval; - uint32_t fifo_offset = 0; + uint16_t offset = 0; + uint8_t cfg_num; + struct musb_fifo_cfg *cfg; memset(&g_musb_hcd[bus->hcd.hcd_id], 0, sizeof(struct musb_hcd)); @@ -430,21 +496,16 @@ int usb_hc_init(struct usbh_bus *bus) usb_hc_low_level_init(bus); - musb_set_active_ep(bus, 0); - HWREGB(USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) = 0; - HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = USB_TXFIFOSZ_SIZE_64; - HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = 0; - HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = USB_TXFIFOSZ_SIZE_64; - HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = 0; - fifo_offset += 64; + cfg_num = usbh_get_musb_fifo_cfg(&cfg); - for (uint8_t i = 1; i < CONIFG_USB_MUSB_PIPE_NUM; i++) { - musb_set_active_ep(bus, i); - HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = USB_TXFIFOSZ_SIZE_512; - HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = fifo_offset; - HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = USB_TXFIFOSZ_SIZE_512; - HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = fifo_offset; - fifo_offset += 512; + for (uint8_t i = 0; i < cfg_num; i++) { + offset = usbh_musb_fifo_config(bus, &cfg[i], offset); + } + + if (offset > usb_get_musb_ram_size()) { + USB_LOG_ERR("offset:%d is overflow, please check your table\r\n", offset); + while (1) { + } } /* Enable USB interrupts */ @@ -652,10 +713,16 @@ int usbh_submit_urb(struct usbh_urb *urb) musb_control_urb_init(bus, 0, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); break; case USB_ENDPOINT_TYPE_BULK: - musb_bulk_urb_init(bus, chidx, urb, urb->transfer_buffer, urb->transfer_buffer_length); + ret = musb_bulk_urb_init(bus, chidx, urb, urb->transfer_buffer, urb->transfer_buffer_length); + if (ret < 0) { + return ret; + } break; case USB_ENDPOINT_TYPE_INTERRUPT: - musb_intr_urb_init(bus, chidx, urb, urb->transfer_buffer, urb->transfer_buffer_length); + ret = musb_intr_urb_init(bus, chidx, urb, urb->transfer_buffer, urb->transfer_buffer_length); + if (ret < 0) { + return ret; + } break; case USB_ENDPOINT_TYPE_ISOCHRONOUS: return -USB_ERR_NOTSUPP; @@ -919,7 +986,7 @@ void USBH_IRQHandler(uint8_t busid) handle_ep0(bus); } - for (ep_idx = 1; ep_idx < CONIFG_USB_MUSB_PIPE_NUM; ep_idx++) { + for (ep_idx = 1; ep_idx < CONFIG_USBHOST_PIPE_NUM; ep_idx++) { if (txis & (1 << ep_idx)) { HWREGH(USB_BASE + MUSB_TXIS_OFFSET) = (1 << ep_idx); @@ -965,7 +1032,7 @@ void USBH_IRQHandler(uint8_t busid) } rxis &= HWREGH(USB_BASE + MUSB_RXIE_OFFSET); - for (ep_idx = 1; ep_idx < CONIFG_USB_MUSB_PIPE_NUM; ep_idx++) { + for (ep_idx = 1; ep_idx < CONFIG_USBHOST_PIPE_NUM; ep_idx++) { if (rxis & (1 << ep_idx)) { HWREGH(USB_BASE + MUSB_RXIS_OFFSET) = (1 << ep_idx); // clear isr flag diff --git a/port/musb/usb_musb_reg.h b/port/musb/usb_musb_reg.h index 99d2cdfb..885bdd4a 100644 --- a/port/musb/usb_musb_reg.h +++ b/port/musb/usb_musb_reg.h @@ -3868,4 +3868,19 @@ typedef struct { /*!< USB0 Structure #define USB_MODE_DEV 0x00000003 #define USB_MODE_OTG 0x00000000 +#define FIFO_TX 0 +#define FIFO_RX 1 +#define FIFO_TXRX 2 + +struct musb_fifo_cfg { + uint8_t ep_num; + uint8_t style; + uint8_t mode; + uint32_t maxpacket; +}; + +uint8_t usbd_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg); +uint8_t usbh_get_musb_fifo_cfg(struct musb_fifo_cfg **cfg); +uint32_t usb_get_musb_ram_size(void); + #endif