remove duplicate es32 drivers

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_acmp.c

@@ -0,0 +1,336 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_acmp.c
+  * @brief   ACMP module driver.
+  *
+  * @version V1.0
+  * @date    26 Jun 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          26 Jun 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#include "ald_conf.h"
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup ACMP ACMP
+  * @brief ACMP module driver
+  * @{
+  */
+#ifdef ALD_ACMP
+
+/** @defgroup ACMP_Public_Functions ACMP Public Functions
+  * @{
+  */
+
+/** @defgroup ACMP_Public_Functions_Group1 Initialization functions
+  * @brief Initialization and Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the ACMP mode according to the specified parameters in
+  *         the acmp_init_t and create the associated handle.
+  * @param  hperh: Pointer to a acmp_handle_t structure that contains
+  *         the configuration information for the specified ACMP module.
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_acmp_init(acmp_handle_t *hperh)
+{
+	uint32_t tmp = 0;
+
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_ACMP_MODE_TYPE(hperh->init.mode));
+	assert_param(IS_ACMP_WARM_UP_TIME_TYPE(hperh->init.warm_time));
+	assert_param(IS_ACMP_HYSTSEL_TYPE(hperh->init.hystsel));
+	assert_param(IS_ACMP_POS_INPUT_TYPE(hperh->init.p_port));
+	assert_param(IS_ACMP_NEG_INPUT_TYPE(hperh->init.n_port));
+	assert_param(IS_ACMP_INACTVAL_TYPE(hperh->init.inactval));
+	assert_param(IS_FUNC_STATE(hperh->init.out_inv));
+	assert_param(IS_ACMP_EDGE_TYPE(hperh->init.edge));
+	assert_param(hperh->init.vdd_level < 64);
+
+	__LOCK(hperh);
+	tmp = ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) |
+		(hperh->init.inactval << ACMP_CON_INACTV_POS) | (hperh->init.hystsel << ACMP_CON_HYSTSEL_POSS));
+
+	hperh->perh->CON = tmp;
+
+	tmp |= ((hperh->init.p_port << ACMP_INPUTSEL_PSEL_POSS) | (hperh->init.n_port << ACMP_INPUTSEL_NSEL_POSS) |
+		(hperh->init.vdd_level << ACMP_INPUTSEL_VDDLVL_POSS));
+	hperh->perh->INPUTSEL = tmp;
+
+	if (hperh->init.out_inv)
+		SET_BIT(hperh->perh->CON, ACMP_CON_OUTINV_MSK);
+	else
+		CLEAR_BIT(hperh->perh->CON, ACMP_CON_OUTINV_MSK);
+
+	switch (hperh->init.edge) {
+	case ACMP_EDGE_NONE:
+		CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
+		CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
+		break;
+
+	case ACMP_EDGE_FALL:
+		SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
+		CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
+		break;
+
+	case ACMP_EDGE_RISE:
+		CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
+		SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
+		break;
+
+	case ACMP_EDGE_ALL:
+		SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
+		SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
+		break;
+
+	default:
+		break;
+	}
+
+	SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK);
+
+	tmp = 0;
+	while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0) {
+		if (tmp++ >= 600000) {
+			__UNLOCK(hperh);
+			return ERROR;
+		}
+	}
+
+	__UNLOCK(hperh);
+	return OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup ACMP_Public_Functions_Group2 Interrupt operation functions
+  * @brief ACMP Interrupt operation functions
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified ACMP interrupts.
+  * @param  hperh: Pointer to a acmp_handle_t structure that contains
+  *         the configuration information for the specified ACMP module.
+  * @param  it: Specifies the ACMP interrupt sources to be enabled or disabled.
+  *         This parameter can be one of the @ref acmp_it_t.
+  * @param  state: New status
+  *           - ENABLE
+  *           - DISABLE
+  * @retval None
+  */
+void ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state)
+{
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_ACMP_IT_TYPE(it));
+	assert_param(IS_FUNC_STATE(state));
+
+	if (state)
+		hperh->perh->IES = it;
+	else
+		hperh->perh->IEC = it;
+
+	return;
+}
+
+/**
+  * @brief  Checks whether the specified ACMP interrupt has set or not.
+  * @param  hperh: Pointer to a acmp_handle_t structure that contains
+  *         the configuration information for the specified ACMP module.
+  * @param  it: Specifies the ACMP interrupt sources to be enabled or disabled.
+  *         This parameter can be one of the @ref acmp_it_t.
+  * @retval it_status_t
+  *           - SET
+  *           - RESET
+  */
+it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it)
+{
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_ACMP_IT_TYPE(it));
+
+	if (hperh->perh->IEV & it)
+		return SET;
+
+	return RESET;
+}
+
+/**
+  * @brief  Checks whether the specified ACMP interrupt has occurred or not.
+  * @param  hperh: Pointer to a acmp_handle_t structure that contains
+  *         the configuration information for the specified ACMP module.
+  * @param  flag: Specifies the ACMP interrupt source to check.
+  *         This parameter can be one of the @ref acmp_flag_t.
+  * @retval flag_status_t
+  *           - SET
+  *           - RESET
+  */
+flag_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
+{
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_ACMP_FLAG_TYPE(flag));
+
+	if (hperh->perh->RIF & flag)
+		return SET;
+
+	return RESET;
+}
+
+/**
+  * @brief  Get the status of interrupt flag and interupt source.
+  * @param  hperh: Pointer to a acmp_handle_t structure that contains
+  *               the configuration information for the specified ACMP.
+  * @param  flag: Specifies the ACMP interrupt flag.
+  * @retval Status:
+  *           - 0: RESET
+  *           - 1: SET
+  */
+flag_status_t ald_acmp_get_mask_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
+{
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_ACMP_FLAG_TYPE(flag));
+
+	if (hperh->perh->IFM & flag)
+		return SET;
+
+	return RESET;
+}
+
+/** @brief  Clear the specified ACMP it flags.
+  * @param  hperh: Pointer to a acmp_handle_t structure that contains
+  *         the configuration information for the specified ACMP module.
+  * @param  flag: specifies the it flag.
+  *         This parameter can be one of the @ref acmp_flag_t.
+  * @retval None
+  */
+void ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
+{
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_ACMP_FLAG_TYPE(flag));
+
+	hperh->perh->IFC = flag;
+	return;
+}
+/**
+  * @}
+  */
+/** @defgroup ACMP_Public_Functions_Group3 Output value functions
+  * @brief ACMP Output value functions
+  * @{
+  */
+/**
+  * @brief  This function handles ACMP interrupt request.
+  * @param  hperh: Pointer to a acmp_handle_t structure that contains
+  *         the configuration information for the specified ACMP module.
+  * @retval None
+  */
+void ald_acmp_irq_handler(acmp_handle_t *hperh)
+{
+	if ((ald_acmp_get_mask_flag_status(hperh, ACMP_FLAG_WARMUP)) == SET) {
+		ald_acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP);
+
+		if (hperh->acmp_warmup_cplt_cbk)
+			hperh->acmp_warmup_cplt_cbk(hperh);
+	}
+
+	if ((ald_acmp_get_mask_flag_status(hperh, ACMP_FLAG_EDGE)) == SET) {
+		ald_acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE);
+
+		if (hperh->acmp_edge_cplt_cbk)
+			hperh->acmp_edge_cplt_cbk(hperh);
+	}
+
+	return;
+}
+
+/**
+  * @brief  This function config acmp output.
+  * @param  hperh: Pointer to a acmp_handle_t structure that contains
+  *         the configuration information for the specified ACMP module.
+  * @param  state: ENABLE/DISABLE.
+  * @retval None
+  */
+void ald_acmp_out_config(acmp_handle_t *hperh, type_func_t state)
+{
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_FUNC_STATE(state));
+
+	if (state)
+		SET_BIT(hperh->perh->PORT, ACMP_PORT_PEN_MSK);
+	else
+		CLEAR_BIT(hperh->perh->PORT, ACMP_PORT_PEN_MSK);
+
+	return;
+}
+
+/**
+  * @brief  This function output acmp result.
+  * @param  hperh: Pointer to a acmp_handle_t structure that contains
+  *         the configuration information for the specified ACMP module.
+  * @retval output value.
+  */
+uint8_t ald_acmp_out_result(acmp_handle_t *hperh)
+{
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+
+	return (READ_BIT(hperh->perh->STAT, ACMP_STAT_OUT_MSK) >> ACMP_STAT_OUT_POS);
+}
+
+/** @brief  Check whether the specified ACMP flag is set or not.
+  * @param  hperh: Pointer to a acmp_handle_t structure that contains
+  *         the configuration information for the specified ACMP module.
+  * @param  status: specifies the status to check.
+  *         This parameter can be one of the @ref acmp_status_t.
+  * @retval flag_status_t
+  *           - SET
+  *           - RESET
+  */
+flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status)
+{
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_ACMP_STATUS_TYPE(status));
+
+	if (hperh->perh->STAT & status)
+		return SET;
+
+	return RESET;
+}
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* ALD_ACMP */
+/**
+  * @}
+  */
+/**
+  * @}
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_bkpc.c

@@ -0,0 +1,185 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_bkpc.c
+  * @brief   BKPC module driver.
+  *
+  * @version V1.0
+  * @date    15 Dec 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          15 Dec 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#include "ald_conf.h"
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup BKPC BKPC
+  * @brief BKPC module driver
+  * @{
+  */
+#ifdef ALD_BKPC
+
+/** @defgroup BKPC_Public_Functions BKPC Public Functions
+  * @{
+  */
+
+/** @addtogroup BKPC_Public_Functions_Group1 Peripheral Control functions
+  * @brief Peripheral Control functions
+  *
+  * @verbatim
+  ==============================================================================
+              ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]  This section provides functions allowing to:
+    (+) ald_bkpc_standby_wakeup_config() API can configure STANDBY wakeup.
+    (+) ald_bkpc_rtc_clock_config() API can configure RTC clock.
+    (+) ald_bkpc_tsense_clock_config() API can configure Tsense clock.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure standby wakeup in backup field
+  * @param  port: Wakeup port
+  * @param  level: HIGH/LOW.
+  * @retval None
+  */
+void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
+{
+	assert_param(IS_BKPC_WAKEUP_PORT(port));
+	assert_param(IS_BKPC_WAKEUP_LEVEL(level));
+
+	if (port == PMU_STANDBY_PORT_SEL_NONE) {
+		BKPC_UNLOCK();
+		CLEAR_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK);
+		SET_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK);
+		BKPC_LOCK();
+		return;
+	}
+
+	BKPC_UNLOCK();
+	SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK | BKPC_CR_MRST_WKPEN_MSK);
+	MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS);
+	MODIFY_REG(BKPC->CR, BKPC_CR_WKPOL_MSK, level << BKPC_CR_WKPOL_POS);
+	BKPC_LOCK();
+
+	return;
+}
+
+/**
+  * @brief  Configure rtc clock in backup field
+  * @param  clock: Clock
+  * @retval None
+  */
+void ald_bkpc_rtc_clock_config(bkpc_preh_clk_t clock)
+{
+	assert_param(IS_BKPC_PREH_CLOCK(clock));
+
+	BKPC_UNLOCK();
+	MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, clock << BKPC_PCCR_RTCCS_POSS);
+	BKPC_LOCK();
+
+	return;
+}
+
+/**
+  * @brief  Configure tsense clock in backup field
+  * @param  clock: Clock
+  * @retval None
+  */
+void ald_bkpc_tsense_clock_config(bkpc_preh_clk_t clock)
+{
+	assert_param(IS_BKPC_PREH_CLOCK(clock));
+
+	BKPC_UNLOCK();
+	MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, clock << BKPC_PCCR_TSENSECS_POSS);
+	BKPC_LOCK();
+
+	return;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup BKPC_Public_Functions_Group2 IO operation functions
+  * @brief IO operation functions
+  *
+  * @verbatim
+  ==============================================================================
+              ##### IO operation functions #####
+  ==============================================================================
+  [..]  This section provides functions allowing to:
+    (+) ald_bkpc_write_ram() API can write data in backup ram.
+    (+) ald_bkpc_read_ram() API can read data from backup ram.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Write data into backup ram.
+  * @param  idx: Index of backup word.
+  * @param  value: Value which will be written to backup ram.
+  * @retval None
+  */
+void ald_bkpc_write_ram(uint8_t idx, uint32_t value)
+{
+	assert_param(IS_BKPC_RAM_IDX(idx));
+
+	RTC_UNLOCK();
+	WRITE_REG(RTC->BKPR[idx], value);
+	RTC_LOCK();
+
+	return;
+}
+
+/**
+  * @brief  Read data from backup ram.
+  * @param  idx: Index of backup word.
+  * @retval The data.
+  */
+uint32_t ald_bkpc_read_ram(uint8_t idx)
+{
+	assert_param(IS_BKPC_RAM_IDX(idx));
+
+	return READ_REG(RTC->BKPR[idx]);
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* ALD_BKPC */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_calc.c

@@ -0,0 +1,81 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_calc.c
+  * @brief   CALC module driver.
+  *
+  * @version V1.0
+  * @date    26 Jun 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          26 Jun 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#include "ald_conf.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup CALC CALC
+  * @brief CALC module driver
+  * @{
+  */
+#ifdef ALD_CALC
+
+/** @defgroup CALC_Public_Functions CALC Public Functions
+  * @brief    Accelerating calculate functions
+  *
+  * @verbatim
+  ==============================================================================
+              ##### Accelerating calculate functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Square root operation.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Square root operation.
+  * @param  data: The  radicand.
+  * @retval The value of square root.
+  */
+uint32_t ald_calc_sqrt(uint32_t data)
+{
+	WRITE_REG(CALC->RDCND, data);
+	while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK));
+
+	return READ_REG(CALC->SQRTRES);
+}
+/**
+  * @}
+  */
+#endif /* ALD_CALC */
+/**
+  * @}
+  */
+/**
+  * @}
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_crc.c

@@ -0,0 +1,535 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_crc.c
+  * @brief   CRC module driver.
+  *
+  * @version V1.0
+  * @date    18 Jun 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          18 Jun 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#include "ald_conf.h"
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup CRC CRC
+  * @brief CRC module driver
+  * @{
+  */
+#ifdef ALD_CRC
+
+/** @addtogroup CRC_Private_Functions   CRC Private Functions
+  * @{
+  */
+void ald_crc_reset(crc_handle_t *hperh);
+#ifdef ALD_DMA
+static void crc_dma_calculate_cplt(void *arg);
+static void crc_dma_error(void *arg);
+#endif
+/**
+  * @}
+  */
+
+
+/** @defgroup CRC_Public_Functions CRC Public Functions
+  * @{
+  */
+
+/** @defgroup CRC_Public_Functions_Group1 Initialization functions
+  * @brief Initialization and Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  Initializes the CRC mode according to the specified parameters in
+  *         the crc_handle_t and create the associated handle.
+  * @param  hperh: Pointer to a crc_handle_t structure that contains
+  *         the configuration information for the specified CRC module.
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_crc_init(crc_handle_t *hperh)
+{
+	uint32_t tmp = 0;
+
+	if (hperh == NULL)
+		return ERROR;
+
+	assert_param(IS_CRC(hperh->perh));
+	assert_param(IS_CRC_MODE(hperh->init.mode));
+	assert_param(IS_FUNC_STATE(hperh->init.chs_rev));
+	assert_param(IS_FUNC_STATE(hperh->init.data_inv));
+	assert_param(IS_FUNC_STATE(hperh->init.data_rev));
+	assert_param(IS_FUNC_STATE(hperh->init.chs_inv));
+
+	ald_crc_reset(hperh);
+	__LOCK(hperh);
+
+	CRC_ENABLE(hperh);
+
+	tmp = hperh->perh->CR;
+
+	tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATINV_POS) |
+		(hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) |
+		(CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) |
+		(0 << CRC_CR_BYTORD_POS));
+
+	hperh->perh->CR = tmp;
+	hperh->perh->SEED = hperh->init.seed;
+	CRC_RESET(hperh);
+
+	hperh->state = CRC_STATE_READY;
+
+	__UNLOCK(hperh);
+	return OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Public_Functions_Group2 Calculate functions
+  * @brief Calculate functions
+  * @{
+  */
+
+/**
+  * @brief  Calculate the crc value of data by byte.
+  * @param  hperh: Pointer to a crc_handle_t structure that contains
+  *         the configuration information for the specified CRC module.
+  * @param  buf: Pointer to data buffer
+  * @param  size: The size of data to be calculate
+  * @retval result, the result of a amount data
+  */
+uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size)
+{
+	uint32_t i;
+	uint32_t ret;
+
+	assert_param(IS_CRC(hperh->perh));
+
+	if (buf == NULL || size == 0)
+		return 0;
+
+	__LOCK(hperh);
+	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS);
+	hperh->state = CRC_STATE_BUSY;
+
+	for (i = 0; i < size; i++)
+		*((volatile uint8_t *)&(hperh->perh->DATA)) = buf[i];
+
+	ret          = CRC->CHECKSUM;
+	hperh->state = CRC_STATE_READY;
+	__UNLOCK(hperh);
+
+	return ret;
+}
+
+/**
+  * @brief  Calculate the crc value of data by halfword.
+  * @param  hperh: Pointer to a crc_handle_t structure that contains
+  *         the configuration information for the specified CRC module.
+  * @param  buf: Pointer to data buffer
+  * @param  size: The size of data to be calculate,width is 2 bytes.
+  * @retval result, the result of a amount data
+  */
+uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size)
+{
+	uint32_t i;
+	uint32_t ret;
+
+	assert_param(IS_CRC(hperh->perh));
+
+	if (buf == NULL || size == 0)
+		return 0;
+
+	__LOCK(hperh);
+	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS);
+	hperh->state = CRC_STATE_BUSY;
+
+	for (i = 0; i < size; i++)
+		*((volatile uint16_t *)&(hperh->perh->DATA)) = buf[i];
+
+	ret          = CRC->CHECKSUM;
+	hperh->state = CRC_STATE_READY;
+	__UNLOCK(hperh);
+
+	return ret;
+}
+
+/**
+  * @brief  Calculate the crc value of data by word.
+  * @param  hperh: Pointer to a crc_handle_t structure that contains
+  *         the configuration information for the specified CRC module.
+  * @param  buf: Pointer to data buffer
+  * @param  size: The size of data to be calculate,width is 4 bytes
+  * @retval result, the result of a amount data
+  */
+uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size)
+{
+	uint32_t i;
+	uint32_t ret;
+
+	assert_param(IS_CRC(hperh->perh));
+
+	if (buf == NULL || size == 0)
+		return 0;
+
+	__LOCK(hperh);
+	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS);
+	hperh->state = CRC_STATE_BUSY;
+
+	for (i = 0; i < size; i++)
+ 		CRC->DATA = buf[i];
+
+	for (i = 0; i < 3; i++);
+
+	ret          = CRC->CHECKSUM;
+	hperh->state = CRC_STATE_READY;
+	__UNLOCK(hperh);
+
+	return ret;
+}
+
+/**
+  * @}
+  */
+
+#ifdef ALD_DMA
+/** @defgroup CRC_Public_Functions_Group3 DMA operation functions
+  * @brief DMA operation functions
+  * @{
+  */
+
+/**
+  * @brief  Calculate an amount of data used dma channel
+  * @param  hperh: Pointer to a crc_handle_t structure that contains
+  *         the configuration information for the specified CRC module.
+  * @param  buf: Pointer to data buffer
+  * @param  res: Pointer to result
+  * @param  size: Amount of data to be Calculate
+  * @param  channel: DMA channel as CRC transmit
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
+{
+	if (hperh->state != CRC_STATE_READY)
+		return BUSY;
+
+	if (buf == NULL || size == 0)
+		return ERROR;
+
+	__LOCK(hperh);
+	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS);
+
+	hperh->state = CRC_STATE_BUSY;
+
+	hperh->cal_buf = buf;
+	hperh->cal_res = res;
+
+	if (hperh->hdma.perh == NULL)
+		hperh->hdma.perh = DMA0;
+
+	hperh->hdma.cplt_arg = (void *)hperh;
+	hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
+	hperh->hdma.err_arg  = (void *)hperh;
+	hperh->hdma.err_cbk  = &crc_dma_error;
+
+	ald_dma_config_struct(&(hperh->hdma.config));
+	hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE;
+	hperh->hdma.config.src        = (void *)buf;
+	hperh->hdma.config.dst        = (void *)&hperh->perh->DATA;
+	hperh->hdma.config.size       = size;
+	hperh->hdma.config.src_inc    = DMA_DATA_INC_BYTE;
+	hperh->hdma.config.dst_inc    = DMA_DATA_INC_NONE;
+	hperh->hdma.config.msel       = DMA_MSEL_CRC;
+	hperh->hdma.config.msigsel    = DMA_MSIGSEL_NONE;
+	hperh->hdma.config.channel    = channel;
+	hperh->hdma.config.burst      = ENABLE;
+	ald_dma_config_basic(&(hperh->hdma));
+
+	__UNLOCK(hperh);
+	CRC_DMA_ENABLE(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Calculate an amount of data used dma channel,data width is half-word.
+  * @param  hperh: Pointer to a crc_handle_t structure that contains
+  *         the configuration information for the specified CRC module.
+  * @param  buf: Pointer to half_word data buffer
+  * @param  res: Pointer to result
+  * @param  size: Amount of half_word data to be Calculate
+  * @param  channel: DMA channel as CRC transmit
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
+{
+	if (hperh->state != CRC_STATE_READY)
+		return BUSY;
+
+	if (buf == NULL || size == 0)
+		return ERROR;
+
+	__LOCK(hperh);
+	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS);
+
+	hperh->state = CRC_STATE_BUSY;
+
+	hperh->cal_buf = (uint8_t *)buf;
+	hperh->cal_res = res;
+
+	if (hperh->hdma.perh == NULL)
+		hperh->hdma.perh = DMA0;
+
+	hperh->hdma.cplt_arg = (void *)hperh;
+	hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
+	hperh->hdma.err_arg  = (void *)hperh;
+	hperh->hdma.err_cbk  = &crc_dma_error;
+
+	ald_dma_config_struct(&(hperh->hdma.config));
+	hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD;
+	hperh->hdma.config.src        = (void *)buf;
+	hperh->hdma.config.dst        = (void *)&hperh->perh->DATA;
+	hperh->hdma.config.size       = size;
+	hperh->hdma.config.src_inc    = DMA_DATA_INC_HALFWORD;
+	hperh->hdma.config.dst_inc    = DMA_DATA_INC_NONE;
+	hperh->hdma.config.msel       = DMA_MSEL_CRC;
+	hperh->hdma.config.msigsel    = DMA_MSIGSEL_NONE;
+	hperh->hdma.config.channel    = channel;
+	hperh->hdma.config.burst      = ENABLE;
+	ald_dma_config_basic(&(hperh->hdma));
+
+	__UNLOCK(hperh);
+	CRC_DMA_ENABLE(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Calculate an amount of data used dma channel,data width is word.
+  * @param  hperh: Pointer to a crc_handle_t structure that contains
+  *         the configuration information for the specified CRC module.
+  * @param  buf: Pointer to word data buffer
+  * @param  res: Pointer to result
+  * @param  size: Amount of word data to be Calculate
+  * @param  channel: DMA channel as CRC transmit
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
+{
+	if (hperh->state != CRC_STATE_READY)
+		return BUSY;
+
+	if (buf == NULL || size == 0)
+		return ERROR;
+
+	__LOCK(hperh);
+	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS);
+
+	hperh->state = CRC_STATE_BUSY;
+
+	hperh->cal_buf = (uint8_t *)buf;
+	hperh->cal_res = res;
+
+	if (hperh->hdma.perh == NULL)
+		hperh->hdma.perh = DMA0;
+
+	hperh->hdma.cplt_arg = (void *)hperh;
+	hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
+	hperh->hdma.err_arg  = (void *)hperh;
+	hperh->hdma.err_cbk  = &crc_dma_error;
+
+	ald_dma_config_struct(&(hperh->hdma.config));
+	hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD;
+	hperh->hdma.config.src        = (void *)buf;
+	hperh->hdma.config.dst        = (void *)&hperh->perh->DATA;
+	hperh->hdma.config.size       = size;
+	hperh->hdma.config.src_inc    = DMA_DATA_INC_WORD;
+	hperh->hdma.config.dst_inc    = DMA_DATA_INC_NONE;
+	hperh->hdma.config.msel       = DMA_MSEL_CRC;
+	hperh->hdma.config.msigsel    = DMA_MSIGSEL_NONE;
+	hperh->hdma.config.channel    = channel;
+	hperh->hdma.config.burst      = ENABLE;
+	ald_dma_config_basic(&(hperh->hdma));
+
+	__UNLOCK(hperh);
+	CRC_DMA_ENABLE(hperh);
+
+	return OK;
+}
+
+
+/**
+  * @brief  Pauses the DMA Transfer.
+  * @param  hperh: Pointer to a crc_handle_t structure that contains
+  *         the configuration information for the specified CRC module.
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_crc_dma_pause(crc_handle_t *hperh)
+{
+	__LOCK(hperh);
+	CRC_DMA_DISABLE(hperh);
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Resumes the DMA Transfer.
+  * @param  hperh: Pointer to a crc_handle_t structure that contains
+  *         the configuration information for the specified CRC module.
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_crc_dma_resume(crc_handle_t *hperh)
+{
+	__LOCK(hperh);
+	CRC_DMA_ENABLE(hperh);
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Stops the DMA Transfer.
+  * @param  hperh: Pointer to a crc_handle_t structure that contains
+  *         the configuration information for the specified CRC module.
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_crc_dma_stop(crc_handle_t *hperh)
+{
+	__LOCK(hperh);
+	CRC_DMA_DISABLE(hperh);
+	__UNLOCK(hperh);
+
+	hperh->state = CRC_STATE_READY;
+	return OK;
+}
+
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup CRC_Public_Functions_Group4 Peripheral State and Errors functions
+  * @brief    CRC State and Errors functions
+  * @{
+  */
+
+/**
+  * @brief  Returns the CRC state.
+  * @param  hperh: Pointer to a crc_handle_t structure that contains
+  *         the configuration information for the specified CRC module.
+  * @retval CRC state
+  */
+crc_state_t ald_crc_get_state(crc_handle_t *hperh)
+{
+	assert_param(IS_CRC(hperh->perh));
+
+	return hperh->state;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Functions   CRC Private Functions
+  *  @brief   CRC Private functions
+  * @{
+  */
+
+/**
+  * @brief  Reset the CRC peripheral.
+  * @param  hperh: Pointer to a crc_handle_t structure that contains
+  *         the configuration information for the specified CRC module.
+  * @retval None
+  */
+void ald_crc_reset(crc_handle_t *hperh)
+{
+	hperh->perh->DATA = 0x0;
+	hperh->perh->CR   = 0x2;
+	hperh->perh->SEED = 0xFFFFFFFF;
+
+	hperh->state = CRC_STATE_READY;
+	__UNLOCK(hperh);
+	return;
+}
+
+#ifdef ALD_DMA
+/**
+  * @brief  DMA CRC calculate process complete callback.
+  * @param  arg: Pointer to a crc_handle_t structure that contains
+  *         the configuration information for the specified CRC module.
+  * @retval None
+  */
+static void crc_dma_calculate_cplt(void *arg)
+{
+	crc_handle_t *hperh = (crc_handle_t *)arg;
+
+	*(hperh->cal_res) = CRC->CHECKSUM;
+	CRC_DMA_DISABLE(hperh);
+
+	hperh->state = CRC_STATE_READY;
+
+	if (hperh->cal_cplt_cbk)
+		hperh->cal_cplt_cbk(hperh);
+}
+
+/**
+  * @brief  DMA CRC communication error callback.
+  * @param  arg: Pointer to a crc_handle_t structure that contains
+  *         the configuration information for the specified CRC module.
+  * @retval None
+  */
+static void crc_dma_error(void *arg)
+{
+	crc_handle_t *hperh = (crc_handle_t *)arg;
+
+	CRC_CLEAR_ERROR_FLAG(hperh);
+	CRC_DMA_DISABLE(hperh);
+
+	hperh->state = CRC_STATE_READY;
+
+	if (hperh->err_cplt_cbk)
+		hperh->err_cplt_cbk(hperh);
+}
+#endif
+/**
+  * @}
+  */
+#endif /* ALD_CRC */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_dac.c

@@ -0,0 +1,349 @@
+/**
+  ******************************************************************************
+  * @file    ald_dac.c
+  * @brief   DAC module driver.
+  *
+  * @version V1.0
+  * @date    28 Jun 2019
+  * @author  AE Team.
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          28 Jun 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#include "ald_conf.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup DAC DAC
+  * @brief DAC module driver
+  * @{
+  */
+#ifdef ALD_DAC
+
+/** @defgroup DAC_Public_Functions DAC Public Functions
+  * @{
+  */
+/**
+  * @brief  Reset the dac mode.
+  * @param  hperh: Pointer to a dac_handle_t structure that contains
+  *         the configuration information for the specified DAC module.
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_dac_reset(dac_handle_t *hperh)
+{
+	assert_param(IS_DAC_TYPE(hperh->perh));
+
+	hperh->perh->CON      = 0;
+	hperh->perh->CH0CTRL  = 0;
+	hperh->perh->CH1CTRL  = 0;
+	hperh->perh->IES      = 0;
+	hperh->perh->IEC      = 0xFF;
+	hperh->perh->IFC      = 0xFF;
+	hperh->perh->CAL      = 0;
+
+	return OK;
+}
+
+/**
+  * @brief  Initializes the DAC peripheral.
+  * @param  hperh: Pointer to a dac_handle_t structure that contains
+  *         the configuration information for the specified DAC module.
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_dac_init(dac_handle_t *hperh)
+{
+	uint32_t tmp;
+
+	assert_param(IS_DAC_TYPE(hperh->perh));
+	assert_param(IS_DAC_CONVERT_TYPE(hperh->init.conv_mode));
+	assert_param(IS_DAC_OUTPUT_TYPE(hperh->init.out_mode));
+	assert_param(IS_DAC_NEG_REFRESH_TYPE(hperh->init.n_ref));
+	assert_param(IS_DAC_POS_REFRESH_TYPE(hperh->init.p_ref));
+	assert_param(IS_DAC_REFRESH_TYPE(hperh->init.refresh));
+	assert_param(IS_DAC_PRESCALE_TYPE(hperh->init.div));
+	assert_param(IS_FUNC_STATE(hperh->init.ch0_reset));
+	assert_param(IS_FUNC_STATE(hperh->init.o_ctrl_pis));
+	assert_param(IS_FUNC_STATE(hperh->init.sine));
+	assert_param(IS_FUNC_STATE(hperh->init.diff));
+
+	__LOCK(hperh);
+	ald_dac_reset(hperh);
+	DAC_CH0_DISABLE();
+	DAC_CH1_DISABLE();
+
+	MODIFY_REG(ADC0->CCR, ADC_CCR_VREFEN_MSK, 1 << ADC_CCR_VREFEN_POS);
+
+	if (hperh->init.p_ref == DAC_POS_REF_VREEFP_BUF || hperh->init.p_ref == DAC_POS_REF_2V)
+		SET_BIT(ADC0->CCR, (ADC_CCR_IREFEN_MSK | ADC_CCR_VRBUFEN_MSK | ADC_CCR_VCMBUFEN_MSK));
+
+	MODIFY_REG(ADC0->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS);
+	MODIFY_REG(ADC0->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS);
+
+	tmp = ((hperh->init.refresh << DAC_CON_RCYCLSEL_POSS) | (hperh->init.div << DAC_CON_PRES_POSS) |
+	       (hperh->init.ch0_reset << DAC_CON_CH0PRESRST_POS) | ( hperh->init.o_ctrl_pis << DAC_CON_OUTENPIS_POS) |
+	       (hperh->init.out_mode << DAC_CON_OUTMD_POSS) | (hperh->init.conv_mode << DAC_CON_CONVMD_POSS) |
+	       (hperh->init.sine << DAC_CON_SINEMD_POS) | (hperh->init.diff << DAC_CON_DIFEN_POS));
+	hperh->perh->CON = tmp;
+
+	/* Automatic calibration */
+	SET_BIT(hperh->perh->CAL, DAC_CAL_SELF_CALEN_MSK);
+	for (tmp = 0; tmp < 1000; ++tmp);
+	CLEAR_BIT(hperh->perh->CAL, DAC_CAL_SELF_CALEN_MSK);
+
+	__UNLOCK(hperh);
+	return OK;
+}
+
+/**
+  * @brief  Configure dac channel.
+  * @param  hperh: Pointer to a dac_handle_t structure that contains
+  *         the configuration information for the specified DAC module.
+  * @param  config: Pointer to a dac_channel_config_t structure that contains
+  *         the configutation information for dac channel.
+  * @param  ch: Specifies which dac channel to be config.
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_dac_channel_config(dac_handle_t *hperh, dac_channel_config_t *config, dac_channel_t ch)
+{
+	uint32_t tmp;
+
+	if ((hperh == NULL) || (config == NULL))
+		return ERROR;
+
+	assert_param(IS_DAC_TYPE(hperh->perh));
+	assert_param(IS_FUNC_STATE(config->enable));
+	assert_param(IS_DAC_TRIGGER_TYPE(config->trigger));
+	assert_param(IS_FUNC_STATE(config->refresh_en));
+	assert_param(IS_DAC_PISSEL_CH_TYPE(config->pis_ch));
+
+	__LOCK(hperh);
+	tmp = ((config->pis_ch << DAC_CH0CTRL_PISSEL_POSS) | (config->trigger << DAC_CH0CTRL_PISEN_POS) |
+	       (config->refresh_en << DAC_CH0CTRL_RCYCLEN_POS) | (config->enable << DAC_CH0CTRL_EN_POS));
+
+	switch (ch) {
+	case DAC_CHANNEL_0:
+		hperh->perh->CH0CTRL = tmp;
+		break;
+
+	case DAC_CHANNEL_1:
+		hperh->perh->CH1CTRL = tmp;
+		break;
+
+	default:
+		break;
+	}
+
+	__UNLOCK(hperh);
+	return OK;
+}
+
+/**
+  * @brief  Set dac channel output value.
+  * @param  hperh: Pointer to a dac_handle_t structure that contains
+  *         the configuration information for the specified DAC module.
+  * @param  ch: Specifies which dac channel to be set.
+  * @param  value: The value be converted,and the valid value is low 12 bit.
+  * @retval None
+  */
+void ald_dac_output_set(dac_handle_t *hperh, dac_channel_t ch, uint32_t value)
+{
+	assert_param(IS_DAC_TYPE(hperh->perh));
+	assert_param(IS_DAC_CHANNEL_TYPE(ch));
+
+	switch (ch) {
+	case DAC_CHANNEL_0:
+		hperh->perh->CH0DATA = value;
+		break;
+
+	case DAC_CHANNEL_1:
+		hperh->perh->CH1DATA = value;
+		break;
+
+	case DAC_CHANNEL_COMB:
+		hperh->perh->COMBDATA = value;
+		break;
+
+	default:
+		break;
+	}
+
+	return;
+}
+
+/**
+  * @brief  Checks whether the specified DAC flag is set or not.
+  * @param  hperh: Pointer to a dac_handle_t structure that contains
+  *               the configuration information for the specified dac.
+  * @param  status: Specifies the flag to check.
+  * @retval The new state.
+  */
+flag_status_t ald_dac_get_status(dac_handle_t *hperh, dac_status_t status)
+{
+	assert_param(IS_DAC_TYPE(hperh->perh));
+	assert_param(IS_DAC_STATUS_TYPE(status));
+
+	return hperh->perh->STAT & status ? SET : RESET;
+}
+
+/**
+  * @brief Enable or disable the specified interrupt
+  * @param hperh: Pointer to a dac_handle_t structure that contains
+  *               the configuration information for the specified DAC.
+  * @param it: Specifies the interrupt type to be enabled or disabled
+  *        @arg @ref DAC_IT_CH0 Channel 0 conversion complete interrupt
+  *        @arg @ref DAC_IT_CH1 Channel 1 conversion complete interrupt
+  *        @arg @ref DAC_IT_CH0_UF Channel 0 data underflow interrupt
+  *        @arg @ref DAC_IT_CH1_UF Channel 1 data underflow interrupt
+  * @param state: New state of the specified interrupt.
+  *        This parameter can be: ENABLE or DISABLE
+  * @retval Status, see @ref ald_status_t.
+  */
+void ald_dac_interrupt_config(dac_handle_t *hperh, dac_it_t it, type_func_t state)
+{
+	assert_param(IS_DAC_TYPE(hperh->perh));
+	assert_param(IS_DAC_INTERRUPT_TYPE(it));
+	assert_param(IS_FUNC_STATE(state));
+
+	if (state)
+		hperh->perh->IES |= it;
+	else
+		hperh->perh->IEC = it;
+
+	return;
+}
+
+/**
+  * @brief  Get the status of DAC interrupt source.
+  * @param  hperh: Pointer to a dac_handle_t structure that contains
+  *               the configuration information for the specified DAC.
+  * @param  it: Specifies the DAC interrupt source.
+  * @retval Status:
+  *           - 0: RESET
+  *           - 1: SET
+  */
+it_status_t ald_dac_get_it_status(dac_handle_t *hperh, dac_it_t it)
+{
+	assert_param(IS_DAC_TYPE(hperh->perh));
+	assert_param(IS_DAC_INTERRUPT_TYPE(it));
+
+	return hperh->perh->IEV & it ? SET : RESET;
+}
+
+/**
+  * @brief Checks whether the specified interrupt has occurred or not.
+  * @param hperh: Pointer to a dac_handle_t structure that contains
+  *               the configuration information for the specified DAC.
+  * @param flag: Specifies the interrupt type to check.
+  * @retval The new state.
+  */
+flag_status_t ald_dac_get_flag_status(dac_handle_t *hperh, dac_flag_t flag)
+{
+	assert_param(IS_DAC_TYPE(hperh->perh));
+	assert_param(IS_DAC_FLAG_TYPE(flag));
+
+	return hperh->perh->RIF & flag ? SET : RESET;
+}
+
+/**
+  * @brief  Get the status of interrupt flag and interupt source.
+  * @param  hperh: Pointer to a dac_handle_t structure that contains
+  *               the configuration information for the specified DAC.
+  * @param  flag: Specifies the DAC interrupt flag.
+  * @retval Status:
+  *           - 0: RESET
+  *           - 1: SET
+  */
+flag_status_t ald_dac_get_mask_flag_status(dac_handle_t *hperh, dac_flag_t flag)
+{
+	assert_param(IS_DAC_TYPE(hperh->perh));
+	assert_param(IS_DAC_FLAG_TYPE(flag));
+
+	return hperh->perh->IFM & flag ? SET : RESET;
+}
+
+/**
+  * @brief  Clear interrupt state flag
+  * @param  hperh: Pointer to a dac_handle_t structure that contains
+  *               the configuration information for the specified DAC.
+  * @param  flag: Specifies the interrupt type to clear
+  * @retval None
+  */
+void ald_dac_clear_flag_status(dac_handle_t *hperh, dac_flag_t flag)
+{
+	assert_param(IS_DAC_TYPE(hperh->perh));
+	assert_param(IS_DAC_FLAG_TYPE(flag));
+
+	hperh->perh->IFC = flag;
+	return;
+}
+
+/**
+  * @brief  This function handles DAC event interrupt request.
+  * @param hperh: Pointer to a dac_handle_t structure that contains
+  *               the configuration information for the specified DAC.
+  * @retval None
+  */
+void ald_dac_irq_handler(dac_handle_t *hperh)
+{
+	if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH0)) {
+		ald_dac_clear_flag_status(hperh, DAC_FLAG_CH0);
+
+		if (hperh->cbk)
+			hperh->cbk(hperh, DAC_EVENT_CH0_CPLT);
+	}
+
+	if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH1)) {
+		ald_dac_clear_flag_status(hperh, DAC_FLAG_CH1);
+
+		if (hperh->cbk)
+			hperh->cbk(hperh, DAC_EVENT_CH1_CPLT);
+	}
+
+	if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH0_UF)) {
+		ald_dac_clear_flag_status(hperh, DAC_FLAG_CH0_UF);
+
+		if (hperh->cbk)
+			hperh->cbk(hperh, DAC_EVENT_CH0_UF);
+	}
+
+	if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH1_UF)) {
+		ald_dac_clear_flag_status(hperh, DAC_FLAG_CH1_UF);
+
+		if (hperh->cbk)
+			hperh->cbk(hperh, DAC_EVENT_CH1_UF);
+	}
+
+	return;
+}
+/**
+  *@}
+  */
+#endif /* ALD_DAC */
+/**
+  *@}
+  */
+/**
+  *@}
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_ebi.c

@@ -0,0 +1,693 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_ebi.c
+  * @brief   EBI module driver.
+  *
+  * @version V1.0
+  * @date    20 Jan 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          20 Jan 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#include "ald_conf.h"
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup EBI EBI
+  * @brief EBI module driver
+  * @{
+  */  
+#ifdef ALD_EBI
+
+/** @defgroup EBI_Public_Functions EBI Public Functions
+  * @{
+  */
+
+/** @defgroup EBI_Public_Functions_Group1 NOR-FLASH SRAM initialize functions
+  * @brief NOR-FLASH SRAM initialize functions
+  * @{
+  */  
+/**
+  * @brief  Initialize the EBI_NOR_SRAM device according to the specified
+  *         control parameters in the EBI_NOR_SRAM_InitTypeDef
+  * @param  dev: Pointer to NOR_SRAM device instance
+  * @param  init: Pointer to NOR_SRAM Initialization structure
+  * @retval None
+  */
+void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init)
+{
+	assert_param(IS_EBI_NORSRAM_DEVICE(dev));
+	assert_param(IS_EBI_NORSRAM_BANK(init->bank));
+	assert_param(IS_EBI_MUX(init->mux));
+	assert_param(IS_EBI_MEMORY(init->type));
+	assert_param(IS_EBI_NORSRAM_MEMORY_WIDTH(init->width));
+	assert_param(IS_EBI_BURSTMODE(init->acc_mode));
+	assert_param(IS_EBI_WAIT_POLARITY(init->polarity));
+	assert_param(IS_EBI_WRAP_MODE(init->wrap_mode));
+	assert_param(IS_EBI_WAIT_SIGNAL_ACTIVE(init->active));
+	assert_param(IS_EBI_WRITE_OPERATION(init->write));
+	assert_param(IS_EBI_WAITE_SIGNAL(init->signal));
+	assert_param(IS_EBI_EXTENDED_MODE(init->ext_mode));
+	assert_param(IS_EBI_ASYNWAIT(init->wait));
+	assert_param(IS_EBI_WRITE_BURST(init->burst));
+
+	/* Disable NORSRAM device */
+	ald_ebi_nor_sram_disable(dev, init->bank);
+
+	/* Set NORSRAM device control parameters */
+	if (init->type == EBI_MEMORY_TYPE_NOR) {
+		MODIFY_REG(dev->BTCR[init->bank], BCTRLR_CLEAR_MASK, (uint32_t)((uint32_t)EBI_NORSRAM_FLASH_ACCESS_ENABLE
+		       | (uint32_t)init->mux
+		       | (uint32_t)init->type
+		       | (uint32_t)init->width
+		       | (uint32_t)init->acc_mode
+		       | (uint32_t)init->polarity
+		       | (uint32_t)init->wrap_mode
+		       | (uint32_t)init->active
+		       | (uint32_t)init->write
+		       | (uint32_t)init->signal
+		       | (uint32_t)init->ext_mode
+		       | (uint32_t)init->wait
+		       | (uint32_t)init->burst));
+	}
+	else {
+		MODIFY_REG(dev->BTCR[init->bank], BCTRLR_CLEAR_MASK, (uint32_t)(EBI_NORSRAM_FLASH_ACCESS_DISABLE
+		       | (uint32_t)init->mux
+		       | (uint32_t)init->type
+		       | (uint32_t)init->width
+		       | (uint32_t)init->acc_mode
+		       | (uint32_t)init->polarity
+		       | (uint32_t)init->wrap_mode
+		       | (uint32_t)init->active
+		       | (uint32_t)init->write
+		       | (uint32_t)init->signal
+		       | (uint32_t)init->ext_mode
+		       | (uint32_t)init->wait
+		       | (uint32_t)init->burst));
+	}
+}
+
+/**
+  * @brief  Initialize the EBI_NOR_SRAM Timing according to the specified
+  *         parameters in the EBI_NOR_SRAM_TimingTypeDef
+  * @param  dev: Pointer to NOR_SRAM device instance
+  * @param  timing: Pointer to NOR_SRAM Timing structure
+  * @param  bank: NOR_SRAM bank number
+  * @retval None
+  */
+void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank)
+{
+	assert_param(IS_EBI_NORSRAM_DEVICE(dev));
+	assert_param(IS_EBI_ADDRESS_SETUP_TIME(timing->addr_setup));
+	assert_param(IS_EBI_ADDRESS_HOLD_TIME(timing->addr_hold));
+	assert_param(IS_EBI_DATASETUP_TIME(timing->data_setup));
+	assert_param(IS_EBI_TURNAROUND_TIME(timing->bus_dur));
+	assert_param(IS_EBI_DATA_LATENCY(timing->latency));
+	assert_param(IS_EBI_ACCESS_MODE(timing->mode));
+	assert_param(IS_EBI_NORSRAM_BANK(bank));
+
+	/* Set EBI_NORSRAM device timing parameters */
+	MODIFY_REG(dev->BTCR[bank + 1U], BTR_CLEAR_MASK,                       \
+		(uint32_t)(timing->addr_setup                                | \
+			((timing->addr_hold)      << EBI_BTRx_ADDHOLD_POSS)  | \
+			((timing->data_setup)     << EBI_BTRx_DATAHOLD_POSS) | \
+			((timing->bus_dur)	  << EBI_BTRx_BUSTURN_POSS)  | \
+			(((timing->div) - 1U)     << EBI_BTRx_CLKDIV_POSS)   | \
+			(((timing->latency) - 1U) << EBI_BTRx_DATALAT_POSS)  | \
+			(timing->mode)));
+}
+
+/**
+  * @brief  Initialize the EBI_NOR_SRAM Extended mode Timing according to the specified
+  *         parameters in the EBI_NOR_SRAM_TimingTypeDef
+  * @param  dev: Pointer to NOR_SRAM device instance
+  * @param  timing: Pointer to NOR_SRAM Timing structure
+  * @param  bank: NOR_SRAM bank number
+  * @param  mode EBI Extended Mode
+  *         This parameter can be one of the following values:
+  *            @arg EBI_EXTENDED_MODE_DISABLE
+  *            @arg EBI_EXTENDED_MODE_ENABLE
+  * @retval None
+  */
+void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode)
+{
+	assert_param(IS_EBI_EXTENDED_MODE(mode));
+
+	/* Set NORSRAM device timing register for write configuration, if extended mode is used */
+	if (mode == EBI_EXTENDED_MODE_ENABLE) {
+		assert_param(IS_EBI_NORSRAM_EXTENDED_DEVICE(dev));
+		assert_param(IS_EBI_ADDRESS_SETUP_TIME(timing->addr_setup));
+		assert_param(IS_EBI_ADDRESS_HOLD_TIME(timing->addr_hold));
+		assert_param(IS_EBI_DATASETUP_TIME(timing->data_setup));
+		assert_param(IS_EBI_TURNAROUND_TIME(timing->bus_dur));
+		assert_param(IS_EBI_ACCESS_MODE(timing->mode));
+		assert_param(IS_EBI_NORSRAM_BANK(bank));
+
+		/* Set NORSRAM device timing register for write configuration, if extended mode is used */
+		MODIFY_REG(dev->BWTR[bank], BWTR_CLEAR_MASK,                              \
+		       (uint32_t)(timing->addr_setup                                    | \
+				  ((timing->addr_hold)  << EBI_BWRTRx_ADDHOLD_POSS)	 | \
+				  ((timing->data_setup) << EBI_BWRTRx_DATAHOLD_POSS)	 | \
+				  timing->mode                                          | \
+				  ((timing->bus_dur)    << EBI_BWRTRx_BUSTURN_POSS)));
+	}
+	else {
+		dev->BWTR[bank] = 0x0FFFFFFFU;
+	}
+}
+
+/**
+  * @brief  DeInitialize the EBI_NOR_SRAM peripheral 
+  * @param  dev: Pointer to NOR_SRAM device instance
+  * @param  e_dev: Pointer to NOR_SRAM extended mode device instance
+  * @param  bank: NOR_SRAM bank number  
+  * @retval ald status
+  */
+ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank)
+{
+	assert_param(IS_EBI_NORSRAM_DEVICE(dev));
+	assert_param(IS_EBI_NORSRAM_EXTENDED_DEVICE(e_dev));
+	assert_param(IS_EBI_NORSRAM_BANK(bank));
+
+	/* Disable the EBI_NOR/SRAM device */
+	ald_ebi_nor_sram_disable(dev, bank);
+
+	/* De-initialize the EBI_NOR/SRAM device */
+	if (bank == EBI_NORSRAM_BANK1)
+		dev->BTCR[bank] = 0x000030DBU;
+	else
+		dev->BTCR[bank] = 0x000030D2U;
+
+	dev->BTCR[bank + 1U] = 0x0FFFFFFFU;
+	e_dev->BWTR[bank]    = 0x0FFFFFFFU;
+
+	return OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup EBI_Public_Functions_Group2 NOR-FLASH SRAM control functions
+  * @brief NOR-FLASH SRAM control functions
+  * @{
+  */
+/**
+  * @brief  Enable the NOR/SRAM device access.
+  * @param  dev: NOR/SRAM Instance
+  * @param  bank: NOR/SRAM Bank
+  * @retval none
+  */
+void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
+{
+	assert_param(IS_EBI_NORSRAM_DEVICE(dev));
+	assert_param(IS_EBI_NORSRAM_BANK(bank));
+
+	SET_BIT(dev->BTCR[bank], EBI_BCTRLRx_MEMBKEN_MSK);
+}
+
+/**
+  * @brief  Disable the NORSRAM device access.
+  * @param  dev: EBI_NORSRAM Instance
+  * @param  bank: EBI_NORSRAM Bank
+  * @retval none
+  */
+void ald_ebi_nor_sram_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
+{
+	assert_param(IS_EBI_NORSRAM_DEVICE(dev));
+	assert_param(IS_EBI_NORSRAM_BANK(bank));
+
+	CLEAR_BIT(dev->BTCR[bank], EBI_BCTRLRx_MEMBKEN_MSK);
+}
+
+/**
+  * @brief  Enables dynamically NOR-FLASH/SRAM write operation.
+  * @param  dev: Pointer to NOR/SRAM device instance
+  * @param  bank: NOR/SRAM bank number
+  * @retval void
+  */
+void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
+{
+	assert_param(IS_EBI_NORSRAM_DEVICE(dev));
+	assert_param(IS_EBI_NORSRAM_BANK(bank));
+
+	/* Enable write operation */
+	SET_BIT(dev->BTCR[bank], EBI_WRITE_OPERATION_ENABLE);
+}
+
+/**
+  * @brief  Disables dynamically EBI_NORSRAM write operation.
+  * @param  dev: Pointer to NORSRAM device instance
+  * @param  bank: NORSRAM bank number
+  * @retval None
+  */
+void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
+{
+	assert_param(IS_EBI_NORSRAM_DEVICE(dev));
+	assert_param(IS_EBI_NORSRAM_BANK(bank));
+
+	/* Disable write operation */
+	CLEAR_BIT(dev->BTCR[bank], EBI_WRITE_OPERATION_ENABLE);
+}
+/**
+  * @}
+  */
+
+/** @defgroup EBI_Public_Functions_Group3 NAND-FLASH initialize functions
+  * @brief NAND-FLASH initialize functions
+  * @{
+  */
+/**
+  * @brief  Initializes the EBI_NAND device according to the specified
+  *         control parameters in the EBI_NAND_HandleTypeDef
+  * @param  dev: Pointer to NAND device instance
+  * @param  init: Pointer to NAND Initialization structure
+  * @retval None
+  */
+void ald_ebi_nand_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init)
+{
+	assert_param(IS_EBI_NAND_DEVICE(dev));
+	assert_param(IS_EBI_NAND_BANK(init->bank));
+	assert_param(IS_EBI_WAIT_FEATURE(init->wait));
+	assert_param(IS_EBI_NAND_MEMORY_WIDTH(init->width));
+	assert_param(IS_EBI_ECC_STATE(init->ecc));
+	assert_param(IS_EBI_ECCPAGE_SIZE(init->size));
+	assert_param(IS_EBI_TCLR_TIME(init->cle_time));
+	assert_param(IS_EBI_TAR_TIME(init->ale_time));
+
+	/* Set NAND device control parameters */
+	if (init->bank == EBI_NAND_BANK2) {
+		MODIFY_REG(dev->PCTRLR2, PCTRLR_CLEAR_MASK, ((uint32_t)init->wait      |
+				(uint32_t)EBI_PCTRLR_MEMORY_TYPE_NAND                  |
+				(uint32_t)init->width                                  |
+				(uint32_t)init->ecc                                    |
+				(uint32_t)init->size                                   |
+				(uint32_t)((init->cle_time) << EBI_PCTRLRx_CRDLY_POSS) |
+				(uint32_t)((init->ale_time) << EBI_PCTRLRx_ARDLY_POSS)));
+	}
+	else {
+		MODIFY_REG(dev->PCTRLR3, PCTRLR_CLEAR_MASK, ((uint32_t)init->wait      |
+				(uint32_t)EBI_PCTRLR_MEMORY_TYPE_NAND                  |
+				(uint32_t)init->width                                  |
+				(uint32_t)init->ecc                                    |
+				(uint32_t)init->size                                   |
+				(uint32_t)((init->cle_time) << EBI_PCTRLRx_CRDLY_POSS) |
+				(uint32_t)((init->ale_time) << EBI_PCTRLRx_ARDLY_POSS)));
+	}
+}
+
+/**
+  * @brief  Initializes the EBI_NAND Common space Timing according to the specified
+  *         parameters in the EBI_NAND_TimingTypeDef
+  * @param  dev: Pointer to NAND device instance
+  * @param  timing: Pointer to NAND timing structure
+  * @param  bank: NAND bank number
+  * @retval None
+  */
+void ald_ebi_nand_comm_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
+{
+	assert_param(IS_EBI_NAND_DEVICE(dev));
+	assert_param(IS_EBI_SETUP_TIME(timing->time));
+	assert_param(IS_EBI_WAIT_TIME(timing->wait_time));
+	assert_param(IS_EBI_HOLD_TIME(timing->hold_time));
+	assert_param(IS_EBI_HIZ_TIME(timing->hiz_time));
+	assert_param(IS_EBI_NAND_BANK(bank));
+
+	/* Set EBI_NAND device timing parameters */
+	if (bank == EBI_NAND_BANK2) {
+		MODIFY_REG(dev->PMEMR2, PMEMR_CLEAR_MASK, (timing->time          | \
+				((timing->wait_time) << EBI_PMEMRx_MEMWAIT_POSS) | \
+				((timing->hold_time) << EBI_PMEMRx_MEMHOLD_POSS) | \
+				((timing->hiz_time)  << EBI_PMEMRx_MEMHIZT_POSS)));
+	}
+	else {
+		MODIFY_REG(dev->PMEMR3, PMEMR_CLEAR_MASK, (timing->time          | \
+				((timing->wait_time) << EBI_PMEMRx_MEMWAIT_POSS) | \
+				((timing->hold_time) << EBI_PMEMRx_MEMHOLD_POSS) | \
+				((timing->hiz_time)  << EBI_PMEMRx_MEMHIZT_POSS)));
+	}
+}
+
+/**
+  * @brief  Initializes the EBI_NAND Attribute space Timing according to the specified
+  *         parameters in the EBI_NAND_TimingTypeDef
+  * @param  dev: Pointer to NAND device instance
+  * @param  timing: Pointer to NAND timing structure
+  * @param  bank: NAND bank number
+  * @retval None
+  */
+void ald_ebi_nand_attr_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
+{
+	assert_param(IS_EBI_NAND_DEVICE(dev));
+	assert_param(IS_EBI_SETUP_TIME(timing->time));
+	assert_param(IS_EBI_WAIT_TIME(timing->wait_time));
+	assert_param(IS_EBI_HOLD_TIME(timing->hold_time));
+	assert_param(IS_EBI_HIZ_TIME(timing->hiz_time));
+	assert_param(IS_EBI_NAND_BANK(bank));
+
+	/* Set FMC_NAND device timing parameters */
+	if (bank == EBI_NAND_BANK2) {
+		MODIFY_REG(dev->PATTR2, PATTR_CLEAR_MASK, (timing->time       | \
+				((timing->wait_time) << EBI_PATTRx_ATTWAIT_POSS) | \
+				((timing->hold_time) << EBI_PATTRx_ATTHOLD_POSS) | \
+				((timing->hiz_time)  << EBI_PATTRx_ATTHIZT_POSS)));
+	}
+	else {
+		MODIFY_REG(dev->PATTR3, PATTR_CLEAR_MASK, (timing->time       | \
+				((timing->wait_time) << EBI_PATTRx_ATTWAIT_POSS) | \
+				((timing->hold_time) << EBI_PATTRx_ATTHOLD_POSS) | \
+				((timing->hiz_time)  << EBI_PATTRx_ATTHIZT_POSS)));
+	}
+}
+
+/**
+  * @brief  DeInitializes the EBI_NAND device 
+  * @param  dev: Pointer to NAND device instance
+  * @param  bank: NAND bank number
+  * @retval None
+  */
+void ald_ebi_nand_deinit(EBI_NAND_TypeDef *dev, uint32_t bank)
+{
+	assert_param(IS_EBI_NAND_DEVICE(dev));
+	assert_param(IS_EBI_NAND_BANK(bank));
+
+	/* Disable the NAND Bank */
+	ald_ebi_nand_disable(dev, bank);
+
+	/* De-initialize the NAND Bank */
+	if (bank == EBI_NAND_BANK2) {
+		/* Set the EBI_NAND_BANK2 registers to their reset values */
+		WRITE_REG(dev->PCTRLR2,  0x00000018U);
+		WRITE_REG(dev->STAR2,    0x00000040U);
+		WRITE_REG(dev->PMEMR2,   0xFCFCFCFCU);
+		WRITE_REG(dev->PATTR2,   0xFCFCFCFCU);
+	}
+	/* EBI_Bank3_NAND */
+	else {
+		/* Set the EBI_NAND_BANK3 registers to their reset values */
+		WRITE_REG(dev->PCTRLR3, 0x00000018U);
+		WRITE_REG(dev->STAR3,   0x00000040U);
+		WRITE_REG(dev->PMEMR3,  0xFCFCFCFCU);
+		WRITE_REG(dev->PATTR3,  0xFCFCFCFCU);
+	}
+}
+/**
+  * @}
+  */
+
+/** @defgroup EBI_Public_Functions_Group4 NAND-FLASH control functions
+  * @brief NAND-FLASH control functions
+  * @{
+  */ 
+/**
+  * @brief  Enable the NAND device access
+  * @param  dev: EBI_NAND Instance
+  * @param  bank: EBI_NAND Bank
+  * @retval None
+  */
+void ald_ebi_nand_enable(EBI_NAND_TypeDef *dev, uint32_t bank)
+{
+	assert_param(IS_EBI_NAND_DEVICE(dev));
+	assert_param(IS_EBI_NAND_BANK(bank));
+
+	if (bank == EBI_NAND_BANK2)
+		SET_BIT(dev->PCTRLR2, EBI_PCTRLRx_MEMBKEN_MSK);
+	else
+		SET_BIT(dev->PCTRLR3, EBI_PCTRLRx_MEMBKEN_MSK);
+}
+
+/**
+  * @brief  Disable the NAND device access.
+  * @param  dev: EBI_NAND Instance
+  * @param  bank: EBI_NAND Bank
+  * @retval None
+  */
+void ald_ebi_nand_disable(EBI_NAND_TypeDef *dev, uint32_t bank)
+{
+	assert_param(IS_EBI_NAND_DEVICE(dev));
+	assert_param(IS_EBI_NAND_BANK(bank));
+
+	if (bank == EBI_NAND_BANK2)
+		CLEAR_BIT(dev->PCTRLR2, EBI_PCTRLRx_MEMBKEN_MSK);
+	else
+		CLEAR_BIT(dev->PCTRLR3, EBI_PCTRLRx_MEMBKEN_MSK);
+}
+
+/**
+  * @brief  Enable the NAND device interrupt.
+  * @param  dev: EBI_NAND Instance
+  * @param  bank: EBI_NAND Bank
+  * @param  it: EBI_NAND interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg EBI_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg EBI_IT_LEVEL: Interrupt level.
+  *            @arg EBI_IT_FALLING_EDGE: Interrupt falling edge.
+  * @retval None
+  */
+void ald_ebi_nand_enable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
+{
+	assert_param(IS_EBI_NAND_DEVICE(dev));
+	assert_param(IS_EBI_NAND_BANK(bank));
+
+	if (bank == EBI_NAND_BANK2)
+		SET_BIT(dev->STAR2, it);
+	else
+		SET_BIT(dev->STAR3, it);
+}
+
+/**
+  * @brief  Disable the NAND device interrupt.
+  * @param  dev: EBI_NAND Instance
+  * @param  bank: EBI_NAND Bank
+  * @param  it: EBI_NAND interrupt
+  *         This parameter can be any combination of the following values:
+  *            @arg EBI_IT_RISING_EDGE: Interrupt rising edge.
+  *            @arg EBI_IT_LEVEL: Interrupt level.
+  *            @arg EBI_IT_FALLING_EDGE: Interrupt falling edge.
+  * @retval None
+  */
+void ald_ebi_nand_disable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
+{
+	assert_param(IS_EBI_NAND_DEVICE(dev));
+	assert_param(IS_EBI_NAND_BANK(bank));
+
+	if (bank == EBI_NAND_BANK2)
+		CLEAR_BIT(dev->STAR2, it);
+	else
+		CLEAR_BIT(dev->STAR3, it);
+}
+
+/**
+  * @brief  Enables dynamically EBI_NAND ECC feature.
+  * @param  dev: Pointer to NAND device instance
+  * @param  bank: NAND bank number
+  * @retval None
+  */
+void ald_ebi_nand_ecc_enable(EBI_NAND_TypeDef *dev, uint32_t bank)
+{
+	assert_param(IS_EBI_NAND_DEVICE(dev));
+	assert_param(IS_EBI_NAND_BANK(bank));
+
+	/* Enable ECC feature */
+	if (bank == EBI_NAND_BANK2)
+		SET_BIT(dev->PCTRLR2, EBI_PCTRLRx_ECCEN_MSK);
+	else
+		SET_BIT(dev->PCTRLR3, EBI_PCTRLRx_ECCEN_MSK);
+}
+
+/**
+  * @brief  Disables dynamically EBI_NAND ECC feature.
+  * @param  dev: Pointer to NAND device instance
+  * @param  bank: NAND bank number
+  * @retval None
+  */
+void ald_ebi_nand_ecc_disable(EBI_NAND_TypeDef *dev, uint32_t bank)
+{
+	assert_param(IS_EBI_NAND_DEVICE(dev));
+	assert_param(IS_EBI_NAND_BANK(bank));
+
+	/* Disable ECC feature */
+	if (bank == EBI_NAND_BANK2)
+		CLEAR_BIT(dev->PCTRLR2, EBI_PCTRLRx_ECCEN_MSK);
+	else
+		CLEAR_BIT(dev->PCTRLR3, EBI_PCTRLRx_ECCEN_MSK);
+}
+
+/**
+  * @brief  Disables dynamically EBI_NAND ECC feature.
+  * @param  dev: Pointer to NAND device instance
+  * @param  val: Pointer to ECC value
+  * @param  bank: NAND bank number
+  * @param  timeout: Timeout wait value  
+  * @retval ALD status
+  */
+ald_status_t ald_ebi_nand_get_ecc(EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout)
+{
+	uint32_t tick;
+
+	assert_param(IS_EBI_NAND_DEVICE(dev));
+	assert_param(IS_EBI_NAND_BANK(bank));
+
+	tick = ald_get_tick();
+
+	/* Wait until FIFO is empty */
+	while (ald_ebi_nand_get_flag(dev, bank, EBI_FLAG_FEMPT) == RESET) {
+		if (timeout != ALD_MAX_DELAY) {
+			if ((timeout == 0U) || ((ald_get_tick() - tick) > timeout))
+				return TIMEOUT;
+		}
+	}
+
+	if (bank == EBI_NAND_BANK2)
+		*val = (uint32_t)dev->ECCRESULT2;
+	else
+		*val = (uint32_t)dev->ECCRESULT3;
+
+	return OK;
+}
+
+/**
+  * @brief  Get flag status of the NAND device.
+  * @param  dev: EBI_NAND Instance
+  * @param  bank  : EBI_NAND Bank
+  * @param  flag  : EBI_NAND flag
+  *         This parameter can be any combination of the following values:
+  *            @arg EBI_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg EBI_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg EBI_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg EBI_FLAG_FEMPT: FIFO empty flag.
+  * @retval Status:
+  *           - 0: RESET
+  *           - 1: SET
+  */
+flag_status_t ald_ebi_nand_get_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
+{
+	assert_param(IS_EBI_NAND_DEVICE(dev));
+	assert_param(IS_EBI_NAND_BANK(bank));
+
+	if (bank == EBI_NAND_BANK2) {
+		if (dev->STAR2 & flag)
+			return SET;
+	} else {
+		if (dev->STAR3 & flag)
+			return SET;
+	}
+
+	return RESET;
+}
+
+/**
+  * @brief  Clear flag status of the NAND device.
+  * @param  dev: EBI_NAND Instance
+  * @param  bank: EBI_NAND Bank
+  * @param  flag: EBI_NAND flag
+  *         This parameter can be any combination of the following values:
+  *            @arg EBI_FLAG_RISING_EDGE: Interrupt rising edge flag.
+  *            @arg EBI_FLAG_LEVEL: Interrupt level edge flag.
+  *            @arg EBI_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+  *            @arg EBI_FLAG_FEMPT: FIFO empty flag.
+  * @retval None
+  */
+void ald_ebi_nand_clear_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
+{
+	assert_param(IS_EBI_NAND_DEVICE(dev));
+	assert_param(IS_EBI_NAND_BANK(bank));
+
+	/* Enable ECC feature */
+	if (bank == EBI_NAND_BANK2)
+		CLEAR_BIT(dev->STAR2, flag);
+	else
+		CLEAR_BIT(dev->STAR3, flag);
+}
+/**
+  * @}
+  */
+
+/** @defgroup EBI_Public_Functions_Group5 LCD initialize functions
+  * @brief LCD initialize functions
+  * @{
+  */ 
+/**
+  * @brief  Initializes the EBI_LCD device according to the specified
+  *         control parameters in the nor_lcd_handle_t
+  * @param  hlcd: Pointer to LCD device instance
+  * @retval None
+  */
+void ald_ebi_lcd_init(ebi_lcd_handle_t *hlcd)
+{
+	assert_param(IS_EBI_LCD_DEVICE(hlcd->inst));
+	assert_param(IS_EBI_BANK_NUMBER(hlcd->init.bank));
+	assert_param(IS_EBI_HORIZONTAL_SYNCH(hlcd->init.h_polarity));
+	assert_param(IS_EBI_VERTICAL_SYNCH(hlcd->init.v_polarity));
+	assert_param(IS_EBI_DATA_ENABLE(hlcd->init.data_polarity));
+	assert_param(IS_EBI_LCD_ENABLE(hlcd->init.enable));
+	assert_param(IS_EBI_DATA_CLOCK(hlcd->init.clk_polarity));
+	assert_param(IS_EBI_LCD_DATASETUP_TIME(hlcd->init.setup));
+	assert_param(IS_EBI_HYSNC_PULSE_WIDTH(hlcd->init.h_width));
+	assert_param(IS_EBI_VSYNC_PULSE_WIDTH(hlcd->init.v_width));
+	assert_param(IS_EBI_FRAME_LINE_NUMBER(hlcd->init.nr_line));
+	assert_param(IS_EBI_FRAME_PIXEL_NUMBER(hlcd->init.nr_pixel));
+
+	MODIFY_REG(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4], LCDCTRL_CLEAR_MASK,
+				((uint32_t)hlcd->init.h_polarity                  |
+				(uint32_t)hlcd->init.v_polarity                   |
+				hlcd->init.data_polarity                          |
+				hlcd->init.enable                                 |
+				hlcd->init.clk_polarity                           |
+				hlcd->init.setup   << EBI_LCDCTRLx_DATASETUP_POSS |
+				hlcd->init.h_width << EBI_LCDCTRLx_VSYNCWID_POSS  |
+				hlcd->init.v_width << EBI_LCDCTRLx_HSYNCWID_POSS));
+
+	WRITE_REG(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4 + 1],
+						 (hlcd->init.nr_line  << EBI_LCDSTx_LINECNT_POSS |
+						  hlcd->init.nr_pixel << EBI_LCDSTx_PXLCNT_POSS));
+}
+
+/**
+  * @brief  Reset the EBI_LCD 
+  * @param  hlcd: Pointer to LCD device instance
+  * @retval None
+  */
+void ald_ebi_lcd_reset(ebi_lcd_handle_t *hlcd)
+{
+	assert_param(IS_EBI_LCD_RESET(hlcd->init.reset));
+	assert_param(IS_EBI_BANK_NUMBER(hlcd->init.bank));
+
+	SET_BIT(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4], hlcd->init.reset);
+}
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */												    
+#endif
+/**
+ * @}
+ */
+/**
+ * @}
+ */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_flash.c

@@ -0,0 +1,243 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_flash.c
+  * @brief   FLASH module driver.
+  *
+  * @version V1.0
+  * @date    17 Jun 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          17 Jun 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  * @verbatim
+  ==============================================================================
+                    ##### FLASH Peripheral features #####
+  ==============================================================================
+  [..]
+  Base address is 0x00000000
+
+  [..]
+  FLASH have just one programme mode , word programme.
+  word programme can programme 8 bytes once ;
+
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+  This driver provide private functions for ald_flash_ext.c to use
+  @endverbatim
+  */
+
+#include "ald_conf.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup FLASH FLASH
+  * @brief FLASH module driver
+  * @{
+  */
+
+#ifdef ALD_FLASH
+
+#if defined ( __ICCARM__ )
+#define __RAMFUNC       __ramfunc
+#else
+#define __RAMFUNC
+#endif
+
+/** @defgroup Flash_Private_Variables Flash Private Variables
+  * @{
+  */
+/* global variable*/
+static op_cmd_type OP_CMD = OP_FLASH;
+/**
+  * @}
+  */
+
+/** @defgroup Flash_Private_Functions Flash Private Functions
+  *  @brief   Flash Private functions
+  * @{
+  */
+/**
+  * @brief  Unlock the flash.
+  * @retval Status, see @ref ald_status_t.
+  */
+__RAMFUNC static ald_status_t flash_unlock(void)
+{
+	uint16_t i;
+	uint16_t op_cmd = OP_CMD;
+
+	if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
+		return ERROR;
+
+	FLASH_REG_UNLOCK();
+	FLASH_IAP_ENABLE();
+	FLASH_REQ();
+
+	for (i = 0; i < 0xFFFF; i++) {
+		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))
+			break;
+	}
+
+	return i == 0xFFFF ? ERROR : OK;
+}
+
+/**
+  * @brief  Lock the flash.
+  * @retval Status, see @ref ald_status_t.
+  */
+__RAMFUNC static ald_status_t flash_lock(void)
+{
+	uint16_t i;
+	uint16_t op_cmd = OP_CMD;
+
+	FLASH_REG_UNLOCK();
+	WRITE_REG(MSC->FLASHCR, 0x0);
+
+	for (i = 0; i < 0xFFFF; i++) {
+		if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)))
+			break;
+	}
+
+	return i == 0xFFFF ? ERROR : OK;
+}
+
+/**
+  * @brief  Erase one page.
+  * @param  addr: The erased page's address
+  * @retval Status, see @ref ald_status_t.
+  */
+__RAMFUNC ald_status_t flash_page_erase(uint32_t addr)
+{
+	uint32_t i;
+	uint16_t op_cmd = OP_CMD;
+
+	if (flash_unlock() != OK)
+		goto end;
+
+	if (op_cmd == OP_FLASH) {
+		CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
+		MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS);
+	}
+	else {
+		SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
+		MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS);
+	}
+
+	WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE);
+
+	for (i = 0; i < 0xFFFF; i++) {
+		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
+			continue;
+		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK))
+			goto end;
+		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK))
+			goto end;
+		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK))
+			break;
+	}
+
+	if (i == 0xFFFF)
+		goto end;
+
+	if (flash_lock() == ERROR)
+		goto end;
+
+	return OK;
+end:
+	flash_lock();
+	return ERROR;
+}
+
+/**
+  * @brief  Programme a word.
+  * @param  addr: The word's address, it is must word align.
+  * @param  data: The 8 bytes data be write.
+  * @param  len: The number of data be write.
+  * @param  fifo: Choose if use fifo.
+  * @retval Status, see @ref ald_status_t.
+  */
+__RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo)
+{
+	uint16_t i = 0;
+	uint16_t prog_len;
+	uint32_t *p_data = data;
+	uint16_t op_cmd = OP_CMD;
+
+	if (flash_unlock() != OK)
+		goto end;
+
+	if (op_cmd == OP_FLASH)
+		CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
+	else
+		SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
+
+	MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS);
+	MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS);
+
+	for (prog_len = 0; prog_len < len; prog_len++) {
+		if (fifo) {
+			WRITE_REG(MSC->FLASHFIFO, p_data[0]);
+			WRITE_REG(MSC->FLASHFIFO, p_data[1]);
+		}
+		else {
+			WRITE_REG(MSC->FLASHDL, p_data[0]);
+			WRITE_REG(MSC->FLASHDH, p_data[1]);
+			WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP);
+		}
+
+		p_data += 2;
+
+		for (i = 0; i < 0xFFFF; i++) {
+			if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
+				continue;
+			if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK))
+				break;
+		}
+	}
+	if (i == 0xFFFF)
+		goto end;
+
+	if (flash_lock() == ERROR)
+		goto end;
+
+	return OK;
+end:
+	flash_lock();
+	return ERROR;
+}
+/**
+  * @}
+  */
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_flash_ext.c

@@ -0,0 +1,343 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_flash_ext.c
+  * @brief   FLASH extra module driver.
+  *
+  * @version V1.0
+  * @date    17 Jun 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          17 Jun 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  * @verbatim
+  ==============================================================================
+                    ##### FLASH Peripheral features #####
+  ==============================================================================
+  [..]
+  Base address is 0x00000000
+
+  [..]
+  FLASH have just one programme mode , word programme.
+  word programme can programme 8 bytes once ;
+
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) programme flash using ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
+       (++) call the function and supply all the three paraments is needs, addr means
+            the first address to write in this operation, buf is a pointer to the data which
+	    need writing to flash.
+
+   (#) erase flash using ald_flash_erase(uint32_t addr, uint16_t len)
+       (++) call the function and supply two paraments, addr is the first address to erase,
+            len is the length to erase
+
+   (#) read flash using ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len)
+       (++) read the flash and save to a buffer, ram_addr is the buffer's first address,
+            addr is the start reading address in flash, len is the length need read
+
+    @endverbatim
+  */
+
+
+#include "ald_conf.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+#ifdef ALD_FLASH
+
+/** @addtogroup Flash_Private_Variables
+  * @{
+  */
+/* opration buffer*/
+static uint8_t write_buf[FLASH_PAGE_SIZE];
+/**
+  * @}
+  */
+
+/** @addtogroup Flash_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Check whether the flash between the given address section
+  *         have been writen, if it have been writen, return TRUE, else
+  *         return FALSE.
+  * @param  begin_addr: The begin address.
+  * @param  end_addr: The end address.
+  * @retval The check result
+  *         - TRUE
+  *         - FALSE
+  */
+static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr)
+{
+	uint8_t* addr_to_read;
+	uint8_t value;
+	uint32_t index;
+
+	/* Check the parameters */
+	assert_param(IS_FLASH_ADDRESS(begin_addr));
+	assert_param(IS_FLASH_ADDRESS(end_addr));
+
+	addr_to_read = (uint8_t *)begin_addr;
+	index        = begin_addr;
+	value        = 0xFF;
+
+	if (begin_addr > end_addr)
+		return FALSE;
+
+	while (index++ <= end_addr) {
+		value = *addr_to_read++;
+
+		if (value != 0xFF)
+			break;
+	}
+
+	return value == 0xFF ? FALSE : TRUE;
+}
+/**
+  * @}
+  */
+
+/** @defgroup Flash_Public_Functions Flash Public Functions
+  * @verbatim
+ ===============================================================================
+              ##### Flash operation functions #####
+ ===============================================================================
+  [..]
+    This section provides functions allowing to operate flash, such as read and write.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  read the specified length bytes from flash, and store to the specified area.
+  * @param  ram_addr: the specified area to store the reading bytes.
+  * @param  addr: the start address.
+  * @param  len: the length to read.
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len)
+{
+	uint32_t i;
+	uint32_t temp;
+
+	assert_param(IS_4BYTES_ALIGN(ram_addr));
+	assert_param(IS_FLASH_ADDRESS(addr));
+	assert_param(IS_FLASH_ADDRESS(addr + len - 1));
+
+	temp = (uint32_t)ram_addr;
+
+	if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0))
+		return ERROR;
+
+	for (i = 0; i < len; i++)
+		ram_addr[i] = ((uint32_t *)addr)[i];
+
+	return OK;
+}
+
+/**
+  * @brief  Write the give bytes to the given address section.
+  * @param  addr: The start address to write.
+  * @param  buf: The bytes' address.
+  * @param  len: The length to write,and multiple of 2.
+  * @retval Status, see @ref ald_status_t.
+  */
+
+ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
+{
+	uint32_t index = 0;
+	uint32_t para = 0;
+	uint32_t index2 = 0;
+	uint32_t start_write_addr;
+	uint32_t end_write_addr;
+	uint32_t start_word_addr;
+	uint32_t end_word_addr;
+	uint16_t len_to_write;
+	uint32_t len_index;
+	type_bool_t need_erase_page;
+
+	assert_param(IS_FLASH_ADDRESS(addr));
+	assert_param(IS_FLASH_ADDRESS(addr + len - 1));
+
+	len_to_write = len;
+
+	__disable_irq();
+	while (len_to_write > 0) {
+		need_erase_page = FALSE;
+
+		for (index = 0; index < FLASH_PAGE_SIZE; index++)
+			write_buf[index] = 0xFF;
+
+		start_write_addr = addr + (len - len_to_write);
+		end_write_addr   = addr + len - 1;
+		end_write_addr   = FLASH_PAGE_ADDR(start_write_addr) == FLASH_PAGE_ADDR(end_write_addr)
+		                   ? end_write_addr : FLASH_PAGEEND_ADDR(start_write_addr);
+		need_erase_page  = page_have_writen(FLASH_WORD_ADDR(start_write_addr),
+		                                    FLASH_WORDEND_ADDR(end_write_addr));
+
+		if (need_erase_page) {
+			if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr),
+                                 		  FLASH_PAGE_SIZE >> 2)) {
+				__enable_irq();
+				return ERROR;
+			}
+
+			if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr))) {
+				__enable_irq();
+				return ERROR;
+			}
+
+			para   = end_write_addr & (FLASH_PAGE_SIZE - 1);
+			index  = start_write_addr & (FLASH_PAGE_SIZE - 1);
+			index2 = len - len_to_write;
+
+			while (index <= para)
+				write_buf[index++] = buf[index2++];
+
+			index2     = 0;
+			index      = FLASH_PAGE_ADDR(start_write_addr);
+			len_index  = FLASH_PAGE_SIZE;
+		}
+		else {
+			para   = end_write_addr & (FLASH_PAGE_SIZE - 1);
+			index  = start_write_addr & (FLASH_PAGE_SIZE - 1);
+			index2 = len - len_to_write;
+
+			while (index <= para)
+				write_buf[index++] = buf[index2++];
+
+			start_word_addr = FLASH_WORD_ADDR(start_write_addr);
+			end_word_addr   = FLASH_WORDEND_ADDR(end_write_addr);
+			index2          = (FLASH_WORD_ADDR(start_word_addr) - FLASH_PAGE_ADDR(start_word_addr));
+			index           = start_word_addr;
+			len_index       = end_word_addr - start_word_addr + 1;
+		}
+
+		if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO)) {
+			__enable_irq();
+			return ERROR;
+		}
+
+		len_to_write = len_to_write - (end_write_addr - start_write_addr + 1);
+	}
+
+	__enable_irq();
+	return OK;
+}
+
+/**
+  * @brief  erase The flash between the given address section.
+  * @param  addr: The start address to erase.
+  * @param  len: The length to erase.
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_flash_erase(uint32_t addr, uint16_t len)
+{
+	uint32_t index;
+	int32_t para;
+	int32_t start_erase_addr;
+	int32_t end_erase_addr;
+	uint16_t len_not_erase;
+	uint32_t len_index;
+	type_bool_t page_need_save;
+
+	assert_param(IS_FLASH_ADDRESS(addr));
+	assert_param(IS_FLASH_ADDRESS(addr + len - 1));
+
+	len_not_erase = len;
+
+	__disable_irq();
+	while (len_not_erase > 0) {
+		page_need_save = FALSE;
+
+		start_erase_addr = addr + len - len_not_erase;
+		end_erase_addr   = addr + len - 1;
+		end_erase_addr   = (FLASH_PAGE_ADDR(start_erase_addr) == FLASH_PAGE_ADDR(end_erase_addr))
+		                    ? end_erase_addr : FLASH_PAGEEND_ADDR(start_erase_addr);
+
+		if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr)) {
+			if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1)))
+				page_need_save = TRUE;
+		}
+		if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) {
+			if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr)))
+				page_need_save = TRUE;
+		}
+
+		if (page_need_save) {
+			if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr),
+			                                                     FLASH_PAGE_SIZE >> 2)) {
+				__enable_irq();
+				return ERROR;
+			}
+		}
+
+		if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr))) {
+			__enable_irq();
+			return ERROR;
+		}
+
+		if (page_need_save) {
+			para  = end_erase_addr & (FLASH_PAGE_SIZE - 1);
+			index = start_erase_addr & (FLASH_PAGE_SIZE - 1);
+
+			while (index <= para)
+				write_buf[index++] = 0xFF;
+
+			index     = FLASH_PAGE_ADDR(start_erase_addr);
+			len_index = FLASH_PAGE_SIZE;
+			if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) {
+				__enable_irq();
+				return ERROR;
+			}
+		}
+		len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1);
+	}
+
+	__enable_irq();
+	return OK;
+}
+/**
+  * @}
+  */
+
+
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_gpio.c

@@ -0,0 +1,644 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_gpio.c
+  * @brief   GPIO module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+  *           + Initialization functions
+  *           + IO operation functions
+  *           + Control functions
+  *
+  * @version V1.0
+  * @date    07 Nov 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          07 Nov 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  * @verbatim
+  ==============================================================================
+                    ##### GPIO Peripheral features #####
+  ==============================================================================
+  [..]
+  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
+  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
+  in several modes:
+  (+) Input mode
+  (+) Analog mode
+  (+) Output mode
+  (+) External interrupt/event lines
+
+  [..]
+  During and just after reset, the external interrupt lines are not active and
+  the I/O ports are configured Analog mode.
+
+  [..]
+  All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+  activated or not.
+
+  [..]
+  In Output mode, each IO can be configured on open-drain or push-pull
+  type and the Output driver can be selected depending on ODRV register.
+
+  [..]
+  In Input mode, each IO can select filter function.
+
+  [..]
+  Each IO can select TTL or SMIT type.
+
+  [..]
+  Each IO have up to eight functions, user can configure the functions depend
+  on the user's environment.
+
+  [..]
+  Each IO can be locked. Once locked, uesr can only change the output data.
+  Only when the CPU reset to unlock the GPIO port.
+
+  [..]
+  All ports have external interrupt/event capability. To use external interrupt
+  lines, the port must be configured in input mode. All available GPIO pins are
+  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+  [..]
+  Each input line can be independently configured to select the type (event or interrupt) and
+  the corresponding trigger event (rising or falling). Each line can also masked
+  independently. A pending register maintains the status line of the interrupt requests.
+
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Enable the GPIO clock.
+
+   (#) Configure the GPIO pin(s) using ald_gpio_init().
+       (++) Configure the IO mode using "mode" member from gpio_init_t structure
+       (++) Activate Pull-up, Pull-down resistor using "pupd" member from gpio_init_t
+            structure.
+       (++) In Output mode, configured on open-drain or push-pull using "odos"
+            member from gpio_init_t structure.
+       (++) In Output mode, configured output driver using "odrv" member
+            from gpio_init_t structure.
+       (++) In Input mode, configured filter function using "flt" member
+            from gpio_init_t structure.
+       (++) Configured type using "type" member from gpio_init_t structure.
+       (++) Configured functions using "func" member from gpio_init_t structure.
+       (++) Analog mode is required when a pin is to be used as ADC channel
+            or DAC output.
+
+   (#) Configure the GPIO pin(s) using ald_gpio_init_default().
+       (++) Configure GPIO pin using default param:
+            init.mode  = GPIO_MODE_OUTPUT;
+            init.odos  = GPIO_PUSH_PULL;
+            init.pupd  = GPIO_PUSH_UP;
+            init.podrv = GPIO_OUT_DRIVE_6;
+            init.nodrv = GPIO_OUT_DRIVE_6;
+            init.flt   = GPIO_FILTER_DISABLE;
+            init.type  = GPIO_TYPE_CMOS;
+            init.func  = GPIO_FUNC_1;
+
+   (#) In case of external interrupt/event mode selection, user need invoke
+       ald_gpio_exti_init() to configure some param. And then invoke
+       ald_gpio_exti_interrupt_config() to enable/disable external interrupt/event.
+
+   (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+       mapped to the EXTI line using NVIC_SetPriority() and enable it using
+       NVIC_EnableIRQ().
+
+   (#) To get the level of a pin configured in input mode use GPIO_read_pin().
+
+   (#) To set/reset the level of a pin configured in output mode use
+       ald_gpio_write_pin()/ald_gpio_toggle_pin().
+
+   (#) To lock pin configuration until next reset use ald_gpio_lock_pin().
+
+   (#) Configure external interrupt mode and enable/disable using
+       ald_gpio_exti_interrupt_config().
+
+   (#) Get external interrupt flag status using ald_gpio_exti_get_flag_status().
+
+   (#) Clear pending external interrupt flag status using
+       ald_gpio_exti_clear_flag_status().
+
+    @endverbatim
+  */
+
+#include "ald_conf.h"
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup GPIO GPIO
+  * @brief GPIO module driver
+  * @{
+  */
+
+#ifdef ALD_GPIO
+
+/** @defgroup GPIO_Public_Functions GPIO Public Functions
+  * @{
+  */
+
+/** @defgroup GPIO_Public_Functions_Group1 Initialization functions
+  * @brief    Initialization and Configuration functions
+  *
+    @verbatim
+ ===============================================================================
+              ##### Initialization functions #####
+ ===============================================================================
+  [..]
+    This section provides functions allowing to initialize the GPIOs or external
+    interrupt to be ready for use.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the GPIOx peripheral according to the specified
+  *         parameters in the gpio_init_t.
+  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
+  * @param  pin: The pin which need to initialize.
+  * @param  init: Pointer to a gpio_init_t structure that can contains
+  *         the configuration information for the specified parameters.
+  * @retval None
+  */
+void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init)
+{
+	uint32_t i, pos, mask, tmp;
+
+	assert_param(IS_GPIO_PORT(GPIOx));
+	assert_param(IS_GPIO_PIN(pin));
+	assert_param(IS_GPIO_MODE(init->mode));
+	assert_param(IS_GPIO_ODOS(init->odos));
+	assert_param(IS_GPIO_PUPD(init->pupd));
+	assert_param(IS_GPIO_ODRV(init->podrv));
+	assert_param(IS_GPIO_ODRV(init->nodrv));
+	assert_param(IS_GPIO_FLT(init->flt));
+	assert_param(IS_GPIO_TYPE(init->type));
+	assert_param(IS_GPIO_FUNC(init->func));
+
+	for (i = 0; i < 16; ++i) {
+		if (((pin >> i) & 0x1) == 0)
+			continue;
+
+		/* Get position and 2-bits mask */
+		pos  = i << 1;
+		mask = 0x3 << pos;
+
+		/* Set PIN mode */
+		tmp  = READ_REG(GPIOx->MODE);
+		tmp &= ~mask;
+		tmp |= (init->mode << pos);
+		WRITE_REG(GPIOx->MODE, tmp);
+
+		/* Set PIN open-drain or push-pull */
+		tmp  = READ_REG(GPIOx->ODOS);
+		tmp &= ~mask;
+		tmp |= (init->odos << pos);
+		WRITE_REG(GPIOx->ODOS, tmp);
+
+		/* Set PIN push-up or/and push-down */
+		tmp  = READ_REG(GPIOx->PUPD);
+		tmp &= ~mask;
+		tmp |= (init->pupd << pos);
+		WRITE_REG(GPIOx->PUPD, tmp);
+
+		/* Set PIN output P-MOS driver */
+		tmp  = READ_REG(GPIOx->PODRV);
+		tmp &= ~mask;
+		tmp |= (init->podrv << pos);
+		WRITE_REG(GPIOx->PODRV, tmp);
+
+		/* Set PIN output N-MOS driver */
+		tmp  = READ_REG(GPIOx->NODRV);
+		tmp &= ~mask;
+		tmp |= (init->nodrv << pos);
+		WRITE_REG(GPIOx->NODRV, tmp);
+
+		/* Get position and 1-bit mask */
+		pos  = i;
+		mask = 0x1 << pos;
+
+		/* Set PIN filter enable or disable */
+		tmp  = READ_REG(GPIOx->FLT);
+		tmp &= ~mask;
+		tmp |= (init->flt << pos);
+		WRITE_REG(GPIOx->FLT, tmp);
+
+		/* Set PIN type ttl or smit */
+		tmp  = READ_REG(GPIOx->TYPE);
+		tmp &= ~mask;
+		tmp |= (init->type << pos);
+		WRITE_REG(GPIOx->TYPE, tmp);
+
+		/* Configure PIN function */
+		pos  = i < 8 ? (i << 2) : ((i - 8) << 2);
+		mask = 0xF << pos;
+		tmp  = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1);
+		tmp &= ~mask;
+		tmp |= (init->func << pos);
+		i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp);
+	}
+
+	return;
+}
+
+/**
+  * @brief  Initialize the GPIOx peripheral using the default parameters.
+  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
+  * @param  pin: The pin which need to initialize.
+  * @retval None
+  */
+void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin)
+{
+	gpio_init_t init;
+
+	/* Fill GPIO_init_t structure with default parameter */
+	init.mode  = GPIO_MODE_OUTPUT;
+	init.odos  = GPIO_PUSH_PULL;
+	init.pupd  = GPIO_PUSH_UP;
+	init.podrv = GPIO_OUT_DRIVE_6;
+	init.nodrv = GPIO_OUT_DRIVE_6;
+	init.flt   = GPIO_FILTER_DISABLE;
+	init.type  = GPIO_TYPE_CMOS;
+	init.func  = GPIO_FUNC_1;
+
+	ald_gpio_init(GPIOx, pin, &init);
+	return;
+}
+
+/**
+  * @brief  Sets GPIO function to default(func0).
+  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
+  * @retval None
+  */
+void ald_gpio_func_default(GPIO_TypeDef *GPIOx)
+{
+	WRITE_REG(GPIOx->FUNC0, 0x00);
+	WRITE_REG(GPIOx->FUNC1, 0x00);
+
+	return;
+}
+
+/**
+  * @brief  Initialize the external interrupt according to the specified
+  *         parameters in the exti_init_t.
+  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
+  * @param  pin: The pin which need to initialize.
+  * @param  init: Pointer to a exti_init_t structure that can contains
+  *         the configuration information for the specified parameters.
+  * @retval None
+  */
+void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init)
+{
+	uint8_t i;
+	uint8_t port;
+
+	assert_param(IS_GPIO_PORT(GPIOx));
+	assert_param(IS_GPIO_PIN(pin));
+	assert_param(IS_FUNC_STATE(init->filter));
+	assert_param(IS_EXTI_FLTCKS_TYPE(init->cks));
+
+	/* Get GPIO port */
+	if (GPIOx == GPIOA)
+		port = 0x0;
+	else if (GPIOx == GPIOB)
+		port = 0x1;
+	else if (GPIOx == GPIOC)
+		port = 2;
+	else if (GPIOx == GPIOD)
+		port = 3;
+	else if (GPIOx == GPIOE)
+		port = 4;
+	else if (GPIOx == GPIOF)
+		port = 5;
+	else if (GPIOx == GPIOG)
+		port = 6;
+	else if (GPIOx == GPIOH)
+		port = 7;
+	else
+		port = 0;
+
+	/* Get Pin index */
+	for (i = 0; i < 16; ++i) {
+		if (((pin >> i) & 0x1) == 0x1)
+			break;
+	}
+
+	/* Select external interrupt line */
+	if (i <= 7) {
+		EXTI->EXTIPSR0 &= ~(0x7U << (i * 4));
+		EXTI->EXTIPSR0 |= (port << (i * 4));
+	}
+	else {
+		i -= 8;
+		EXTI->EXTIPSR1 &= ~(0x7U << (i * 4));
+		EXTI->EXTIPSR1 |= (port << (i * 4));
+	}
+
+	/* Configure filter parameter */
+	if (init->filter == ENABLE) {
+		SET_BIT(EXTI->EXTIFLTCR, pin);
+		MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTCKS_MSK, init->cks << GPIO_EXTIFLTCR_FLTCKS_POSS);
+		MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS);
+	}
+	else {
+		CLEAR_BIT(EXTI->EXTIFLTCR, pin);
+	}
+
+	return;
+}
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Public_Functions_Group2 IO operation functions
+  * @brief   GPIO Read and Write
+  *
+    @verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the GPIOs.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read the specified input port pin.
+  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
+  * @param  pin: Specifies the pin to read.
+  * @retval The input pin value
+  */
+uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
+{
+	assert_param(IS_GPIO_PORT(GPIOx));
+	assert_param(IS_GPIO_PIN(pin));
+
+	if (READ_BIT(GPIOx->DIN, pin))
+		return 1;
+	else
+		return 0;
+}
+
+/**
+  * @brief  Set or clear the select Pin data.
+  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
+  * @param  pin: The specified pin to be written.
+  * @param  val: The specifies value to be written.
+  * @retval None
+  */
+void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val)
+{
+	assert_param(IS_GPIO_PORT(GPIOx));
+	assert_param(IS_GPIO_PIN(pin));
+
+	if ((val & (0x01)) == 0x00)
+		GPIOx->BSRR = pin << 16U;
+	else
+		GPIOx->BSRR = pin;
+
+	return;
+}
+
+/**
+  * @brief  Turn over the select data.
+  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
+  * @param  pin: Specifies the pin to turn over.
+  * @retval None
+  */
+void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
+{
+	assert_param(IS_GPIO_PORT(GPIOx));
+	assert_param(IS_GPIO_PIN(pin));
+
+	WRITE_REG(GPIOx->BIR, pin);
+	return;
+}
+
+/**
+  * @brief  Turn over the direction.
+  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
+  * @param  pin: Specifies the pin to turn over.
+  * @retval None
+  */
+void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin)
+{
+	uint32_t i, pos, mask, tmp, value;
+
+	assert_param(IS_GPIO_PORT(GPIOx));
+	assert_param(IS_GPIO_PIN(pin));
+
+	for (i = 0; i < 16; ++i) {
+		if (((pin >> i) & 0x1) == 0)
+			continue;
+
+		/* Get position and 2-bits mask */
+		pos  = i << 1;
+		mask = 0x3 << pos;
+
+		/* Get the new direction */
+		tmp = READ_REG(GPIOx->MODE);
+		value = (tmp >> pos) & 0x3;
+
+		if ((value == 2) || (value == 3))
+			value = 1;
+		else if (value == 1) {
+			value = 2;
+		}
+		else {
+			continue; /* do nothing */
+		}
+
+		/* Set PIN mode */
+		tmp &= ~mask;
+		tmp |= (value << pos);
+		WRITE_REG(GPIOx->MODE, tmp);
+	}
+
+	return;
+}
+
+/**
+  * @brief  Lock the GPIO prot. Once locked, can
+  *         only change the output data. Only when the CPU
+  *         reset to unlock the GPIO port.
+  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
+  * @param  pin: The specified Pin to be written.
+  * @retval None
+  */
+void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
+{
+	assert_param(IS_GPIO_PORT(GPIOx));
+	assert_param(IS_GPIO_PIN(pin));
+
+	MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, UNLOCK_KEY << GPIO_LOCK_KEY_POSS);
+	WRITE_REG(GPIOx->LOCK, pin);
+
+	return;
+}
+
+/**
+  * @brief  Read the specified input port pin.
+  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
+  * @retval The value;
+  */
+uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx)
+{
+	assert_param(IS_GPIO_PORT(GPIOx));
+
+	return READ_REG(GPIOx->DIN);
+}
+
+/**
+  * @brief  Set or clear the select Pin data.
+  * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
+  * @param  val: The specifies value to be written.
+  * @retval None
+  */
+void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val)
+{
+	assert_param(IS_GPIO_PORT(GPIOx));
+
+	WRITE_REG(GPIOx->DOUT, val);
+	return;
+}
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Public_Functions_Group3 Control functions
+  * @brief EXTI Control functions
+  *
+    @verbatim
+ ===============================================================================
+                       ##### Control functions #####
+ ===============================================================================
+  [..]
+    This subsection provides a set of functions allowing to
+    control external interrupt.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the interrupt according to the specified parameter.
+  * @param  pin: The Pin which need to configure.
+  * @param  style: External interrupt trigger style.
+  * @param  status:
+  *           @arg ENABLE
+  *           @arg DISABLE
+  * @retval None
+  */
+void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status)
+{
+	assert_param(IS_GPIO_PIN(pin));
+	assert_param(IS_TRIGGER_STYLE(style));
+	assert_param(IS_FUNC_STATE(status));
+
+	if (status == ENABLE) {
+		if (style == EXTI_TRIGGER_RISING_EDGE) {
+			SET_BIT(EXTI->EXTIRER, pin);
+		}
+		else if (style == EXTI_TRIGGER_TRAILING_EDGE) {
+			SET_BIT(EXTI->EXTIFER, pin);
+		}
+		else if (style == EXTI_TRIGGER_BOTH_EDGE) {
+			SET_BIT(EXTI->EXTIRER, pin);
+			SET_BIT(EXTI->EXTIFER, pin);
+		}
+		else {
+			; /* do nothing */
+		}
+
+		WRITE_REG(EXTI->EXTICFR, 0xffff);
+		SET_BIT(EXTI->EXTIEN, pin);
+	}
+	else {
+		if (style == EXTI_TRIGGER_RISING_EDGE) {
+			CLEAR_BIT(EXTI->EXTIRER, pin);
+		}
+		else if (style == EXTI_TRIGGER_TRAILING_EDGE) {
+			CLEAR_BIT(EXTI->EXTIFER, pin);
+		}
+		else if (style == EXTI_TRIGGER_BOTH_EDGE) {
+			CLEAR_BIT(EXTI->EXTIRER, pin);
+			CLEAR_BIT(EXTI->EXTIFER, pin);
+		}
+		else {
+			; /* do nothing */
+		}
+
+		CLEAR_BIT(EXTI->EXTIEN, pin);
+	}
+
+	return;
+}
+
+/**
+  * @brief  Get the Flag about external interrupt.
+  * @param  pin: The pin which belong to external interrupt.
+  * @retval Flag status
+  *         - SET
+  *         - RESET
+  */
+flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin)
+{
+	assert_param(IS_GPIO_PIN(pin));
+
+	if (READ_BIT(EXTI->EXTIFLAG, pin))
+		return SET;
+
+	return RESET;
+}
+
+/**
+  * @brief  Clear the external interrupt flag.
+  * @param  pin: The pin which belong to external interrupt.
+  * @retval None
+  */
+void ald_gpio_exti_clear_flag_status(uint16_t pin)
+{
+	assert_param(IS_GPIO_PIN(pin));
+
+	WRITE_REG(EXTI->EXTICFR, pin);
+	return;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ALD_GPIO */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_iap.c

@@ -0,0 +1,259 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_iap.c
+  * @brief   IAP module driver.
+  *
+  * @version V1.0
+  * @date    04 Dec 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          04 Dec 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#include "ald_conf.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup IAP IAP
+  * @brief IAP module driver
+  * @{
+  */
+#ifdef ALD_IAP
+
+
+/** @defgroup IAP_Public_Functions IAP Public Functions
+  *
+  * @verbatim
+  ==============================================================================
+              #####  Erase and Program flash functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Erase flash.
+      (+) Program flash.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Erases a specified page.
+  * @param  addr: The beginning address of the page to be erased.
+  * @retval The result:
+  *           - 0: SUCCESS
+  *           - 1: ERROR
+  */
+uint32_t ald_iap_erase_page(uint32_t addr)
+{
+	uint32_t status;
+	IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR);
+
+	__disable_irq();
+	status = (*iap_pe)(addr);
+	__enable_irq();
+
+	return !status;
+}
+
+/**
+  * @brief  Programs a word at a specified address.
+  * @param  addr: Specifies the address to be programmed.
+  *         Bit0-1 must be zero.
+  * @param  data: Specifies the data to be programmed.
+  * @retval The result:
+  *           - 0: SUCCESS
+  *           - 1: ERROR
+  */
+uint32_t ald_iap_program_word(uint32_t addr, uint32_t data)
+{
+	uint32_t status;
+	IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR);
+
+	if (addr & 0x3)
+		return 1;
+
+	__disable_irq();
+	status = (*iap_wp)(addr, data);
+	__enable_irq();
+
+	return !status;
+}
+
+/**
+  * @brief  Programs double words at a specified address.
+  * @param  addr: Specifies the address to be programmed.
+  *         Bit0-1 must be zero.
+  * @param  data_l: Specifies the LSB data to be programmed.
+  * @param  data_h: Specifies the MSB data to be programmed.
+  * @retval The result:
+  *           - 0: SUCCESS
+  *           - 1: ERROR
+  */
+uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h)
+{
+	uint32_t status;
+	IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR);
+
+	if (addr & 0x3)
+		return 1;
+
+	__disable_irq();
+	status = (*iap_dwp)(addr, data_l, data_h);
+	__enable_irq();
+
+	return !status;
+}
+
+/**
+  * @brief  Programs datas at a specified address.
+  * @param  addr: Specifies the address to be programmed.
+  *         Bit0-1 must be zero.
+  * @param  data: Specifies the data to be programmed.
+  * @param  len: Specifies the data length to be programmed.
+  *         Bit0-1 must be zero.
+  * @param  erase: Erase page flag before programming.
+  * @retval The result:
+  *           - 0: SUCCESS
+  *           - 1: ERROR
+  */
+uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)
+{
+	uint32_t status;
+	IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR);
+
+	if ((addr & 0x3) || (len & 0x3))
+		return 1;
+
+	__disable_irq();
+	status = (*iap_wsp)(addr, data, len, erase);
+	__enable_irq();
+
+	return !status;
+}
+
+/**
+  * @brief  Erases a specified page of dataflash.
+  * @param  addr: The beginning address of the page to be erased.
+  * @retval The result:
+  *           - 0: SUCCESS
+  *           - 1: ERROR
+  */
+uint32_t ald_iap_erase_page_df(uint32_t addr)
+{
+	uint32_t status;
+	IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PageErase_DF);
+
+	__disable_irq();
+	status = (*iap_pe)(addr);
+	__enable_irq();
+
+	return !status;
+}
+
+/**
+  * @brief  Programs a word at a specified address of dataflash.
+  * @param  addr: Specifies the address to be programmed.
+  *         Bit0-1 must be zero.
+  * @param  data: Specifies the data to be programmed.
+  * @retval The result:
+  *           - 0: SUCCESS
+  *           - 1: ERROR
+  */
+uint32_t ald_iap_program_word_df(uint32_t addr, uint32_t data)
+{
+	uint32_t status;
+	IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WordProgram_DF);
+
+	if (addr & 0x3)
+		return 1;
+
+	__disable_irq();
+	status = (*iap_wp)(addr, data);
+	__enable_irq();
+
+	return !status;
+}
+
+/**
+  * @brief  Programs double words at a specified address of dataflash.
+  * @param  addr: Specifies the address to be programmed.
+  *         Bit0-1 must be zero.
+  * @param  data_l: Specifies the LSB data to be programmed.
+  * @param  data_h: Specifies the MSB data to be programmed.
+  * @retval The result:
+  *           - 0: SUCCESS
+  *           - 1: ERROR
+  */
+uint32_t ald_iap_program_dword_df(uint32_t addr, uint32_t data_l, uint32_t data_h)
+{
+	uint32_t status;
+	IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWordProgram_DF);
+
+	if (addr & 0x3)
+		return 1;
+
+	__disable_irq();
+	status = (*iap_dwp)(addr, data_l, data_h);
+	__enable_irq();
+
+	return !status;
+}
+
+/**
+  * @brief  Programs datas at a specified address of dataflash.
+  * @param  addr: Specifies the address to be programmed.
+  *         Bit0-1 must be zero.
+  * @param  data: Specifies the data to be programmed.
+  * @param  len: Specifies the data length to be programmed.
+  *         Bit0-1 must be zero.
+  * @param  erase: Erase page flag before programming.
+  * @retval The result:
+  *           - 0: SUCCESS
+  *           - 1: ERROR
+  */
+uint32_t ald_iap_program_words_df(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)
+{
+	uint32_t status;
+	IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WordsProgram_DF);
+
+	if ((addr & 0x3) || (len & 0x3))
+		return 1;
+
+	__disable_irq();
+	status = (*iap_wsp)(addr, data, len, erase);
+	__enable_irq();
+
+	return !status;
+}
+/**
+  * @}
+  */
+#endif /* ALD_IAP */
+/**
+  * @}
+  */
+/**
+  * @}
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_nor_lcd.c

@@ -0,0 +1,610 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_nor_lcd.c
+  * @brief   EBI_NOR_LCD module driver.
+  *
+  * @version V1.0
+  * @date    25 Dec 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          25 Dec 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#include "ald_conf.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup NOR_LCD NOR_LCD
+  * @brief NOR_LCD driver modules
+  * @{
+  */
+#ifdef ALD_NOR
+
+/** @defgroup NOR_LCD_Private_Variables NOR_LCD Private Variables
+  * @{
+  */
+static uint32_t NORMEMDATWIDTH = NOR_MEMORY_8B;
+/**
+  * @}
+  */
+
+/** @defgroup NOR_LCD_Public_Functions NOR_LCD Public Functions
+  * @brief NOR_LCD public functions
+  * @{
+  */
+/** @defgroup NOR_LCD_Public_Functions_Group1 Initialization functions
+  * @brief NOR_LCD Initialization functions 
+  * @{
+ */
+/**
+  * @brief  Perform the NOR memory Initialization sequence
+  * @param  hperh: pointer to a nor_handle_t structure 
+  * @param  timing: pointer to NOR control timing structure 
+  * @param  ext_timing: pointer to NOR extended mode timing structure    
+  * @retval ald status 
+  */
+ald_status_t ald_nor_init(nor_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing)
+{
+	if (hperh == NULL)
+		return ERROR;
+	if (hperh->state == ALD_NOR_STATE_RESET)
+		hperh->lock = UNLOCK;
+
+	/* Initialize NOR control Interface */
+	ald_ebi_nor_sram_init(hperh->instance, &(hperh->init));
+	/* Initialize NOR timing Interface */
+	ald_ebi_nor_sram_timing_init(hperh->instance, timing, hperh->init.bank);
+	/* Initialize NOR extended mode timing Interface */
+	ald_ebi_nor_sram_ext_timing_init(hperh->ext, ext_timing, hperh->init.bank, hperh->init.ext_mode);
+	/* Enable the NORSRAM device */
+	ald_ebi_nor_sram_enable(hperh->instance, hperh->init.bank);
+
+	/* Initialize NOR Memory Data Width*/
+	if (hperh->init.width == EBI_NORSRAM_MEM_BUS_WIDTH_8)
+		NORMEMDATWIDTH = NOR_MEMORY_8B;
+	else
+		NORMEMDATWIDTH = NOR_MEMORY_16B;
+
+	hperh->state = ALD_NOR_STATE_READY;
+	return OK;
+}
+
+/**
+  * @brief  Perform NOR memory De-Initialization sequence
+  * @param  hperh: pointer to a nor_handle_t structure 
+  * @retval ald status
+  */
+ald_status_t ald_nor_deinit(nor_handle_t *hperh)
+{
+	ald_ebi_nor_sram_deinit(hperh->instance, hperh->ext, hperh->init.bank);
+	hperh->state = ALD_NOR_STATE_RESET;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup NOR_LCD_Public_Functions_Group2 I/O operation functions
+  * @brief NOR_LCD I/O operation functions
+  * @{
+  */
+/**
+  * @brief  Read NOR flash IDs
+  * @param  hperh: pointer to a nor_handle_t structure
+  * @param  id : pointer to NOR ID structure
+  * @retval ald status
+  */
+ald_status_t ald_nor_read_id(nor_handle_t *hperh, nor_id_t *id)
+{
+	uint32_t devaddr = 0;
+
+	__LOCK(hperh);
+
+	if (hperh->state == ALD_NOR_STATE_BUSY)
+		return BUSY;
+
+	/* Select the NOR device address */
+	if (hperh->init.bank == EBI_NORSRAM_BANK1)
+		devaddr = NOR_MEMORY_ADRESS1;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
+		devaddr = NOR_MEMORY_ADRESS2;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
+		devaddr = NOR_MEMORY_ADRESS3;
+	else
+		devaddr = NOR_MEMORY_ADRESS4;
+
+	hperh->state = ALD_NOR_STATE_BUSY;
+
+	/* Send read ID command */
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+
+	/* Read the NOR IDs */
+	id->m_code       = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, MC_ADDRESS);
+	id->device_code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE1_ADDR);
+	id->device_code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE2_ADDR);
+	id->device_code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE3_ADDR);
+
+	hperh->state = ALD_NOR_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Returns the NOR memory to Read mode.
+  * @param  hperh: pointer to a nor_handle_t structure 
+  * @retval ald status
+  */
+ald_status_t ald_nor_return_readmode(nor_handle_t *hperh)
+{
+	uint32_t devaddr = 0;
+
+	__LOCK(hperh);
+
+	if (hperh->state == ALD_NOR_STATE_BUSY)
+		return BUSY;
+
+	/* Select the NOR device address */
+	if (hperh->init.bank == EBI_NORSRAM_BANK1)
+		devaddr = NOR_MEMORY_ADRESS1;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
+		devaddr = NOR_MEMORY_ADRESS2;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
+		devaddr = NOR_MEMORY_ADRESS3;
+	else
+		devaddr = NOR_MEMORY_ADRESS4;
+
+	NOR_WRITE(devaddr, NOR_CMD_DATA_READ_RESET);
+	hperh->state = ALD_NOR_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Read data from NOR memory 
+  * @param  hperh: pointer to a nor_handle_t structure
+  * @param  addr: pointer to Device address
+  * @param  data: pointer to read data  
+  * @retval ald status
+  */
+ald_status_t ald_nor_read(nor_handle_t *hperh, uint32_t *addr, uint16_t *data)
+{
+	uint32_t devaddr = 0;
+
+	__LOCK(hperh);
+
+	if (hperh->state == ALD_NOR_STATE_BUSY)
+		return BUSY;
+
+	if (hperh->init.bank == EBI_NORSRAM_BANK1)
+		devaddr = NOR_MEMORY_ADRESS1;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
+		devaddr = NOR_MEMORY_ADRESS2;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
+		devaddr = NOR_MEMORY_ADRESS3;
+	else
+		devaddr = NOR_MEMORY_ADRESS4;
+
+	hperh->state = ALD_NOR_STATE_BUSY;
+
+	/* Send read data command */
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+	NOR_WRITE((uint32_t)addr, NOR_CMD_DATA_READ_RESET);
+
+	*data = *(__IO uint32_t *)(uint32_t)addr;
+	hperh->state = ALD_NOR_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Program data to NOR memory 
+  * @param  hperh: pointer to a nor_handle_t structure 
+  * @param  addr: device address
+  * @param  data: pointer to the data to write   
+  * @retval ald status
+  */
+ald_status_t ald_nor_program(nor_handle_t *hperh, uint32_t *addr, uint16_t *data)
+{
+	uint32_t devaddr = 0;
+
+	__LOCK(hperh);
+
+	if (hperh->state == ALD_NOR_STATE_BUSY)
+		return BUSY;
+
+	/* Select the NOR device address */
+	if (hperh->init.bank == EBI_NORSRAM_BANK1)
+		devaddr = NOR_MEMORY_ADRESS1;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
+		devaddr = NOR_MEMORY_ADRESS2;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
+		devaddr = NOR_MEMORY_ADRESS3;
+	else /* EBI_NORSRAM_BANK4 */
+		devaddr = NOR_MEMORY_ADRESS4;
+
+	hperh->state = ALD_NOR_STATE_BUSY;
+
+	/* Send program data command */
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+
+	/* Write the data */
+	NOR_WRITE(addr, *data);
+	hperh->state = ALD_NOR_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Reads a block of data from the EBI NOR memory
+  * @param  hperh: pointer to a nor_handle_t structure 
+  * @param  addr: nor memory internal address to read from
+  * @param  data: pointer to the buffer that receives the data read from the 
+  *         NOR memory
+  * @param  size : number of Half word to read
+  * @retval ald status
+  */
+ald_status_t ald_nor_read_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size)
+{
+	uint32_t devaddr = 0;
+
+	/* Process Locked */
+	__LOCK(hperh);
+
+	if (hperh->state == ALD_NOR_STATE_BUSY)
+		return BUSY;
+
+	if (hperh->init.bank == EBI_NORSRAM_BANK1)
+		devaddr = NOR_MEMORY_ADRESS1;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
+		devaddr = NOR_MEMORY_ADRESS2;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
+		devaddr = NOR_MEMORY_ADRESS3;
+	else
+		devaddr = NOR_MEMORY_ADRESS4;
+
+	hperh->state = ALD_NOR_STATE_BUSY;
+
+	/* Send read data command */
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+	NOR_WRITE(addr, NOR_CMD_DATA_READ_RESET);
+
+	/* Read buffer */
+	while (size > 0) {
+		*data++ = *(__IO uint16_t *)addr;
+		addr += 2U;
+		size--;
+	}
+
+	hperh->state = ALD_NOR_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Writes a half-word buffer to the EBI NOR memory
+  * @param  hperh: pointer to a nor_handle_t structure
+  * @param  addr: nor memory internal address from which the data 
+  * @param  data: pointer to source data buffer 
+  * @param  size: number of Half words to write  
+  * @retval ald status
+  */ 
+ald_status_t ald_nor_program_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size)
+{
+	uint16_t * p_currentaddr = (uint16_t *)NULL;
+	uint16_t * p_endaddr = (uint16_t *)NULL;
+	uint32_t lastloadedaddr = 0, devaddr = 0;
+
+	__LOCK(hperh);
+
+	if (hperh->state == ALD_NOR_STATE_BUSY)
+		return BUSY;
+
+	if (hperh->init.bank == EBI_NORSRAM_BANK1)
+		devaddr = NOR_MEMORY_ADRESS1;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
+		devaddr = NOR_MEMORY_ADRESS2;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
+		devaddr = NOR_MEMORY_ADRESS3;
+	else
+		devaddr = NOR_MEMORY_ADRESS4;
+
+	hperh->state = ALD_NOR_STATE_BUSY;
+
+	/* Initialize variables */
+	p_currentaddr  = (uint16_t*)((uint32_t)(addr));
+	p_endaddr      = p_currentaddr + (size - 1U);
+	lastloadedaddr = (uint32_t)(addr);
+
+	/* Issue unlock command sequence */
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+	/* Write Buffer Load Command */
+	NOR_WRITE((uint32_t)(p_currentaddr), NOR_CMD_DATA_BUFFER_AND_PROG);
+	NOR_WRITE((uint32_t)(p_currentaddr), (size - 1U));
+
+	/* Load Data into NOR Buffer */
+	while (p_currentaddr <= p_endaddr) {
+		lastloadedaddr = (uint32_t)p_currentaddr;
+		NOR_WRITE(p_currentaddr, *data++);
+		p_currentaddr++;
+	}
+
+	NOR_WRITE((uint32_t)(lastloadedaddr), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
+	hperh->state = ALD_NOR_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Erase the specified block of the NOR memory 
+  * @param  hperh: pointer to a nor_handle_t structure 
+  * @param  blkaddr : block to erase address 
+  * @param  addr: device address
+  * @retval ald status
+  */
+ald_status_t ald_nor_erase_block(nor_handle_t *hperh, uint32_t blkaddr, uint32_t addr)
+{
+	uint32_t devaddr = 0;
+
+	__LOCK(hperh);
+
+	if (hperh->state == ALD_NOR_STATE_BUSY)
+		return BUSY;
+
+	if (hperh->init.bank == EBI_NORSRAM_BANK1)
+		devaddr = NOR_MEMORY_ADRESS1;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
+		devaddr = NOR_MEMORY_ADRESS2;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
+		devaddr = NOR_MEMORY_ADRESS3;
+	else
+		devaddr = NOR_MEMORY_ADRESS4;
+
+	hperh->state = ALD_NOR_STATE_BUSY;
+
+	/* Send block erase command sequence */
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+	NOR_WRITE((uint32_t)(blkaddr + addr), NOR_CMD_DATA_BLOCK_ERASE);
+
+	hperh->state = ALD_NOR_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+
+}
+
+/**
+  * @brief  Erase the entire NOR chip.
+  * @param  hperh: pointer to a nor_handle_t structure
+  * @retval ald status
+  */
+ald_status_t ald_nor_erase_chip(nor_handle_t *hperh)
+{
+	uint32_t devaddr = 0;
+
+	__LOCK(hperh);
+
+	if (hperh->state == ALD_NOR_STATE_BUSY)
+		return BUSY;
+
+	/* Select the NOR device address */
+	if (hperh->init.bank == EBI_NORSRAM_BANK1)
+		devaddr = NOR_MEMORY_ADRESS1;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
+		devaddr = NOR_MEMORY_ADRESS2;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
+		devaddr = NOR_MEMORY_ADRESS3;
+	else
+		devaddr = NOR_MEMORY_ADRESS4;
+
+	hperh->state = ALD_NOR_STATE_BUSY;
+
+	/* Send NOR chip erase command sequence */
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+
+	hperh->state = ALD_NOR_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Read NOR flash CFI IDs
+  * @param  hperh: pointer to a nor_handle_t structure
+  * @param  cfi: pointer to NOR CFI IDs structure  
+  * @retval ald status
+  */
+ald_status_t ald_nor_read_cfi(nor_handle_t *hperh, nor_cfi_t *cfi)
+{
+	uint32_t devaddr = 0;
+
+	__LOCK(hperh);
+
+	if (hperh->state == ALD_NOR_STATE_BUSY)
+		return BUSY;
+
+	/* Select the NOR device address */
+	if (hperh->init.bank == EBI_NORSRAM_BANK1)
+		devaddr = NOR_MEMORY_ADRESS1;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK2)
+		devaddr = NOR_MEMORY_ADRESS2;
+	else if (hperh->init.bank == EBI_NORSRAM_BANK3)
+		devaddr = NOR_MEMORY_ADRESS3;
+	else
+		devaddr = NOR_MEMORY_ADRESS4;
+
+	hperh->state = ALD_NOR_STATE_BUSY;
+	NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+
+	cfi->cfi_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI1_ADDRESS);
+	cfi->cfi_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI2_ADDRESS);
+	cfi->cfi_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI3_ADDRESS);
+	cfi->cfi_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI4_ADDRESS);
+
+	hperh->state = ALD_NOR_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup NOR_LCD_Public_Functions_Group3 Control functions
+  * @brief NOR_LCD Control functions
+  * @{
+  */
+/**
+  * @brief  Enables dynamically NOR write operation.
+  * @param  hperh: pointer to a nor_handle_t structure
+  * @retval ald status
+  */
+ald_status_t ald_nor_write_enable(nor_handle_t *hperh)
+{
+	__LOCK(hperh);
+	/* Enable write operation */
+	ald_ebi_nor_sram_write_enable(hperh->instance, hperh->init.bank);
+	hperh->state = ALD_NOR_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Disables dynamically NOR write operation.
+  * @param  hperh: pointer to a nor_handle_t structure
+  * @retval ald status
+  */
+ald_status_t ald_nor_write_disable(nor_handle_t *hperh)
+{
+	__LOCK(hperh);
+	hperh->state = ALD_NOR_STATE_BUSY;
+	/* Disable write operation */
+	ald_ebi_nor_sram_write_disable(hperh->instance, hperh->init.bank);
+	hperh->state = ALD_NOR_STATE_PROTECTED;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup NOR_LCD_Public_Functions_Group4 State functions
+  * @brief NOR_LCD State functions
+  * @{
+  */
+/**
+  * @brief  return the NOR controller state
+  * @param  hperh: pointer to a nor_handle_t structure 
+  * @retval nor controller state
+  */
+ald_nor_state_t ald_nor_get_state(nor_handle_t *hperh)
+{
+	return hperh->state;
+}
+
+/**
+  * @brief  Returns the NOR operation status.
+  * @param  hperh: pointer to a nor_handle_t structure    
+  * @param  addr: device address
+  * @param  timeout: nor progamming timeout
+  * @retval nor status
+  */
+nor_status_t ald_nor_get_status(nor_handle_t *hperh, uint32_t addr, uint32_t timeout)
+{
+	nor_status_t status = ALD_NOR_STATUS_ONGOING;
+	uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
+	uint32_t tickstart = 0;
+
+	/* Get tick */
+	tickstart = ald_get_tick();
+	while ((status != ALD_NOR_STATUS_SUCCESS) && (status != ALD_NOR_STATUS_TIMEOUT)) {
+		/* Check for the Timeout */
+		if (timeout != ALD_MAX_DELAY) {
+			if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout))
+				status = ALD_NOR_STATUS_TIMEOUT;
+		}
+
+		/* Read NOR status register (DQ6 and DQ5) */
+		tmp_sr1 = *(__IO uint16_t *)addr;
+		tmp_sr2 = *(__IO uint16_t *)addr;
+
+		/* If DQ6 did not toggle between the two reads then return NOR_Success */
+		if ((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
+			return ALD_NOR_STATUS_SUCCESS;
+
+		if ((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
+			status = ALD_NOR_STATUS_ONGOING;
+
+		tmp_sr1 = *(__IO uint16_t *)addr;
+		tmp_sr2 = *(__IO uint16_t *)addr;
+
+		/* If DQ6 did not toggle between the two reads then return NOR_Success */
+		if ((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
+			return ALD_NOR_STATUS_SUCCESS;
+		else if ((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+			return ALD_NOR_STATUS_ERROR;
+	}
+
+	return status;
+}
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif
+/**
+  * @}
+  */
+/**
+  * @}		
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_pis.c

@@ -0,0 +1,323 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_pis.c
+  * @brief   PIS module driver.
+  *
+  * @version V1.0
+  * @date    27 Nov 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          27 Nov 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#include "ald_conf.h"
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup PIS PIS
+  * @brief PIS module driver
+  * @{
+  */
+#ifdef ALD_PIS
+
+/** @defgroup PIS_Public_Functions PIS Public Functions
+  * @{
+  */
+
+/** @defgroup PIS_Public_Functions_Group1 Initialization functions
+  * @brief Initialization and Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  Create the PIS mode according to the specified parameters in
+  *         the pis_handle_t and create the associated handle.
+  * @param  hperh: Pointer to a pis_handle_t structure that contains
+  *         the configuration information for the specified PIS module.
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_pis_create(pis_handle_t *hperh)
+{
+	if (hperh == NULL)
+		return ERROR;
+
+	assert_param(IS_PIS_SRC(hperh->init.producer_src));
+	assert_param(IS_PIS_TRIG(hperh->init.consumer_trig));
+	assert_param(IS_PIS_CLOCK(hperh->init.producer_clk));
+	assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk));
+	assert_param(IS_PIS_EDGE(hperh->init.producer_edge));
+	assert_param(IS_PIS_SIGNAL_MODE(hperh->init.producer_signal));
+
+	__LOCK(hperh);
+	hperh->perh = PIS;
+
+	/* get location of consumer in channel and position of con0/con1
+	 * accord to comsumer_trig information */
+	hperh->consumer_ch  = (pis_ch_t)(hperh->init.consumer_trig & 0x0F);
+	hperh->consumer_con = (pis_con_t)((hperh->init.consumer_trig >> 4) & 0x0F);
+	hperh->consumer_pos = (1U << (uint32_t)((hperh->init.consumer_trig >> 8) & 0xFF));
+
+	if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) {
+		__UNLOCK(hperh);
+		return BUSY;
+	}
+
+	MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS);
+	MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS);
+
+	if (hperh->init.producer_clk == hperh->init.consumer_clk) {
+		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_DIRECT << PIS_CH0_CON_SYNCSEL_POSS);
+		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, (hperh->init.consumer_clk) << PIS_CH0_CON_PULCK_POSS);
+	}
+	else {
+		if (hperh->init.producer_signal == PIS_OUT_LEVEL) {
+			if (hperh->init.consumer_clk == PIS_CLK_PCLK1)
+				MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_APB1 << PIS_CH0_CON_SYNCSEL_POSS);
+			if (hperh->init.consumer_clk == PIS_CLK_PCLK2)
+				MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_APB2 << PIS_CH0_CON_SYNCSEL_POSS);
+			if (hperh->init.consumer_clk == PIS_CLK_SYS)
+				MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS);
+		}
+
+		if (hperh->init.producer_signal == PIS_OUT_PULSE) {
+			if (hperh->init.consumer_clk == PIS_CLK_PCLK1)
+				MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_APB1 << PIS_CH0_CON_SYNCSEL_POSS);
+			if (hperh->init.consumer_clk == PIS_CLK_PCLK2)
+				MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_APB2 << PIS_CH0_CON_SYNCSEL_POSS);
+			if (hperh->init.consumer_clk == PIS_CLK_SYS)
+				MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS);
+		}
+	}
+
+	MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS);
+	MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS);
+	hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch];
+
+	/* enable consumer bit, switch pin of consumer */
+	if (hperh->init.input_chan == PIS_CHAN_INPUT) {
+		switch (hperh->consumer_con) {
+		case PIS_CON_0:
+			PIS->TAR_CON0 |= hperh->consumer_pos;
+			break;
+		case PIS_CON_1:
+			PIS->TAR_CON1 |= hperh->consumer_pos;
+			break;
+		default:
+			break;
+		}
+	}
+
+	__UNLOCK(hperh);
+	return OK;
+}
+
+/**
+  * @brief  Destroy the PIS mode according to the specified parameters in
+  *         the pis_init_t and create the associated handle.
+  * @param  hperh: Pointer to a pis_handle_t structure that contains
+  *         the configuration information for the specified PIS module.
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_pis_destroy(pis_handle_t *hperh)
+{
+	assert_param(IS_PIS(hperh->perh));
+
+	if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch])
+		return ERROR;
+
+	__LOCK(hperh);
+
+	CLEAR_BIT(PIS->CH_OER, (1U << (uint32_t)hperh->consumer_ch));
+	WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0);
+
+	switch (hperh->consumer_con) {
+	case PIS_CON_0:
+		PIS->TAR_CON0 &= ~(hperh->consumer_pos);
+		break;
+	case PIS_CON_1:
+		PIS->TAR_CON1 &= ~(hperh->consumer_pos);
+		break;
+	default:
+		break;
+	}
+
+	hperh->state = PIS_STATE_RESET;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup PIS_Public_Functions_Group2 Operation functions
+  * @brief PIS output enable or disable functions
+  * @{
+  */
+
+/**
+  * @brief  Start the PIS output function.
+  * @param  hperh: Pointer to a pis_handle_t structure that contains
+  *         the configuration information for the specified PIS module.
+  * @param  ch: The PIS channel enable output
+  *	    This parameter can be one of the following values:
+  *		@arg PIS_OUT_CH_0
+  *		@arg PIS_OUT_CH_1
+  *		@arg PIS_OUT_CH_2
+  *		@arg PIS_OUT_CH_3
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch)
+{
+	assert_param(IS_PIS(hperh->perh));
+	assert_param(IS_PIS_OUPUT_CH(ch));
+	__LOCK(hperh);
+	SET_BIT(PIS->CH_OER, (1 << (uint32_t)ch));
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Stop the PIS output function.
+  * @param  hperh: Pointer to a pis_handle_t structure that contains
+  *         the configuration information for the specified PIS module.
+  * @param  ch: The PIS channel disable output
+  *	    This parameter can be one of the following values:
+  *		@arg PIS_OUT_CH_0
+  *		@arg PIS_OUT_CH_1
+  *		@arg PIS_OUT_CH_2
+  *		@arg PIS_OUT_CH_3
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch)
+{
+	assert_param(IS_PIS(hperh->perh));
+	assert_param(IS_PIS_OUPUT_CH(ch));
+	__LOCK(hperh);
+	CLEAR_BIT(PIS->CH_OER, (1 << (uint32_t)ch));
+	__UNLOCK(hperh);
+
+	return OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup PIS_Public_Functions_Group3 Peripheral State and Errors functions
+  *  @brief   PIS State and Errors functions
+  * @{
+  */
+
+/**
+  * @brief  Returns the PIS state.
+  * @param  hperh: Pointer to a pis_handle_t structure that contains
+  *         the configuration information for the specified PIS module.
+  * @retval ALD state
+  */
+pis_state_t ald_pis_get_state(pis_handle_t *hperh)
+{
+	assert_param(IS_PIS(hperh->perh));
+	return hperh->state;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PIS_Public_Functions_Group4 modulate output functions
+  *  @brief   PIS modulate output signal functions
+  * @{
+  */
+
+/**
+  * @brief  Config the PIS modulate signal function
+  * @param  hperh: Pointer to a pis_handle_t structure that contains
+  *         the configuration information for the specified PIS module.
+  * @param  config: Pointer to a pis_modulate_config_t structure that
+  *         contains the selected target (UART0,UART1,UART2,UART3 or
+  *         LPUART0) how to modulate the target output signal.
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config)
+{
+	assert_param(IS_PIS(hperh->perh));
+	assert_param(IS_PIS_MODU_TARGET(config->target));
+	assert_param(IS_PIS_MODU_LEVEL(config->level));
+	assert_param(IS_PIS_MODU_SRC(config->src));
+	assert_param(IS_PIS_MODU_CHANNEL(config->channel));
+	__LOCK(hperh);
+
+	switch (config->target) {
+	case PIS_UART0_TX:
+		MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMLVLS_MSK, config->level << PIS_UART0_TXMCR_TXMLVLS_POS);
+		MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMSS_MSK, config->src << PIS_UART0_TXMCR_TXMSS_POSS);
+		MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXSIGS_MSK, config->channel << PIS_UART0_TXMCR_TXSIGS_POSS);
+		break;
+
+	case PIS_UART1_TX:
+		MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMLVLS_MSK, config->level << PIS_UART1_TXMCR_TXMLVLS_POS);
+		MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMSS_MSK, config->src << PIS_UART1_TXMCR_TXMSS_POSS);
+		MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXSIGS_MSK, config->channel << PIS_UART1_TXMCR_TXSIGS_POSS);
+		break;
+
+	case PIS_UART2_TX:
+		MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMLVLS_MSK, config->level << PIS_UART2_TXMCR_TXMLVLS_POS);
+		MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMSS_MSK, config->src << PIS_UART2_TXMCR_TXMSS_POSS);
+		MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXSIGS_MSK, config->channel << PIS_UART2_TXMCR_TXSIGS_POSS);
+		break;
+
+	case PIS_UART3_TX:
+		MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMLVLS_MSK, config->level << PIS_UART3_TXMCR_TXMLVLS_POS);
+		MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMSS_MSK, config->src << PIS_UART3_TXMCR_TXMSS_POSS);
+		MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXSIGS_MSK, config->channel << PIS_UART3_TXMCR_TXSIGS_POSS);
+		break;
+
+	case PIS_LPUART0_TX:
+		MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXMLVLS_MSK, config->level << PIS_LPUART0_TXMCR_TXMLVLS_POS);
+		MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXMSS_MSK, config->src << PIS_LPUART0_TXMCR_TXMSS_POSS);
+		MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXSIGS_MSK, config->channel << PIS_LPUART0_TXMCR_TXSIGS_POSS);
+		break;
+
+	default:
+		break;
+	}
+
+	__UNLOCK(hperh);
+	return OK;
+}
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* ALD_PIS */
+/**
+  * @}
+  */
+/**
+  * @}
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_pmu.c

@@ -0,0 +1,356 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_pmu.c
+  * @brief   PMU module driver.
+  *
+  * @version V1.0
+  * @date    04 Dec 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          04 Dec 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#include "ald_conf.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup PMU PMU
+  * @brief PMU module driver
+  * @{
+  */
+#ifdef ALD_PMU
+
+
+/** @defgroup PMU_Private_Functions PMU Private Functions
+  * @{
+  */
+
+/**
+  * @brief  PMU module interrupt handler
+  * @retval None
+  */
+void ald_lvd_irq_handler(void)
+{
+	SYSCFG_UNLOCK();
+	SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
+	SYSCFG_LOCK();
+
+	return;
+}
+/**
+  * @}
+  */
+
+/** @defgroup PMU_Public_Functions PMU Public Functions
+  * @{
+  */
+
+/** @addtogroup PMU_Public_Functions_Group1 Low Power Mode
+  * @brief Low power mode select functions
+  *
+  * @verbatim
+  ==============================================================================
+              ##### Low power mode select functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Enter stop1 mode.
+      (+) Enter stop2 mode.
+      (+) Enter standby mode.
+      (+) Get wakeup status.
+      (+) Clear wakeup status.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enter stop1 mode
+  * @retval None
+  */
+void ald_pmu_stop1_enter(void)
+{
+	int cnt = 4000;
+
+	SYSCFG_UNLOCK();
+	
+	CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);
+#ifdef ES32F336x  /* MCU Series: ES32F336x */
+	SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK);
+#endif
+	MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, PMU_LDO_18_HOLD << PMU_CR1_LDO18MOD_POSS);
+	MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STOP1 << PMU_CR0_LPM_POSS);
+	SYSCFG_LOCK();
+
+	while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--));
+
+	SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+	__WFI();
+	SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+
+	return;
+}
+
+/**
+  * @brief  Enter stop2 mode
+  * @retval None
+  */
+void ald_pmu_stop2_enter(void)
+{
+	int cnt = 4000;
+
+	SYSCFG_UNLOCK();
+
+	SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);
+#ifdef ES32F336x  /* MCU Series: ES32F336x */
+	SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK);
+#endif
+	MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, PMU_LDO_18_HOLD << PMU_CR1_LDO18MOD_POSS);
+	MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STOP2 << PMU_CR0_LPM_POSS);
+	SYSCFG_LOCK();
+
+	while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--));
+
+	SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+	__WFI();
+	SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+
+	return;
+}
+
+/**
+  * @brief  Enter standby mode
+  * @param  port: The port whick wake up the standby mode.
+  * @param  level: Wakeup level.
+  * @retval None
+  */
+void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
+{
+	ald_bkpc_standby_wakeup_config(port, level);
+
+	SYSCFG_UNLOCK();
+	MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STANDBY << PMU_CR0_LPM_POSS);
+	SYSCFG_LOCK();
+
+	SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+	__WFI();
+	SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+
+	return;
+}
+
+/**
+  * @brief  Enable/Disable LDO(1.2V) hold mode. It must be disabled in STOP1.
+  * @param  state: Enable/Disable
+  * @retval None
+  */
+void ald_pmu_ldo_12_config(type_func_t state)
+{
+	assert_param(IS_FUNC_STATE(state));
+	SYSCFG_UNLOCK();
+
+	if (state)
+		SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);
+	else
+		CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);
+
+	SYSCFG_LOCK();
+	return;
+}
+
+/**
+  * @brief  Configure LDO(1.8V) mode
+  * @param  mode: Mode of the LDO(1.8V)
+  * @retval None
+  */
+void ald_pmu_ldo_18_config(pmu_ldo_18_mode_t mode)
+{
+	uint32_t cnt = 4000;
+
+	assert_param(IS_PMU_LDO18_MODE(mode));
+
+	SYSCFG_UNLOCK();
+	MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, mode << PMU_CR1_LDO18MOD_POSS);
+	SYSCFG_LOCK();
+
+	while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--));
+	return;
+}
+
+#ifdef ES32F336x  /* MCU Series: ES32F336x */
+
+/**
+  * @brief  Configures low power mode. The system clock must
+  *         be less than 2MHz. Such as: LOSC or LRC.
+  * @param  vol: LDO output voltage select in low power mode.
+  * @param  state: New state, ENABLE/DISABLE;
+  * @retval None
+  */
+void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state)
+{
+	assert_param(IS_FUNC_STATE(state));
+	SYSCFG_UNLOCK();
+
+	if (state) {
+		assert_param(IS_PMU_LDO_LPMODE_OUTPUT(vol));
+
+		MODIFY_REG(PMU->CR0, PMU_CR0_LPVS_MSK, vol << PMU_CR0_LPVS_POSS);
+		SET_BIT(PMU->CR0, PMU_CR0_LPRUN_MSK);
+	}
+	else {
+		CLEAR_BIT(PMU->CR0, PMU_CR0_LPRUN_MSK);
+	}
+
+	SYSCFG_LOCK();
+	return;
+}
+#endif
+
+/**
+  * @brief  Get wakup status.
+  * @param  sr: Status bit.
+  * @retval Status.
+  */
+flag_status_t ald_pmu_get_status(pmu_status_t sr)
+{
+	assert_param(IS_PMU_STATUS(sr));
+
+	if (READ_BIT(PMU->SR, sr))
+		return SET;
+
+	return RESET;
+}
+
+/**
+  * @brief  Clear wakup status.
+  * @param  sr: Status bit.
+  * @retval None
+  */
+void ald_pmu_clear_status(pmu_status_t sr)
+{
+	assert_param(IS_PMU_STATUS(sr));
+	SYSCFG_UNLOCK();
+
+	if (sr == PMU_SR_WUF)
+		SET_BIT(PMU->CR0, PMU_CR0_CWUF_MSK);
+	else if (sr == PMU_SR_STANDBYF)
+		SET_BIT(PMU->CR0, PMU_CR0_CSTANDBYF_MSK);
+	else
+		;/* do nothing */
+
+	SYSCFG_LOCK();
+	return;
+}
+
+/**
+  * @brief  Configure peripheral power
+  * @param  perh: The peripheral
+  * @param  state: ENABLE/DISABLE
+  * @retval None
+  */
+void ald_pmu_perh_power_config(pmu_perh_power_t perh, type_func_t state)
+{
+	assert_param(IS_PMU_PERH_POWER(perh));
+	assert_param(IS_FUNC_STATE(state));
+
+	SYSCFG_UNLOCK();
+
+	if (state)
+		SET_BIT(PMU->PWRCR, perh);
+	else
+		CLEAR_BIT(PMU->PWRCR, perh);
+
+	SYSCFG_LOCK();
+	return;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup PMU_Public_Functions_Group2 LVD Configure
+  * @brief LVD configure functions
+  *
+  * @verbatim
+  ==============================================================================
+              ##### LVD configure functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure lvd parameters.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure lvd using specified parameters.
+  * @param  sel: LVD threshold voltage.
+  * @param  mode: LVD trigger mode.
+  * @param  state: New state, ENABLE/DISABLE;
+  * @retval None
+  */
+void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state)
+{
+	assert_param(IS_FUNC_STATE(state));
+	SYSCFG_UNLOCK();
+
+	if (state) {
+		assert_param(IS_PMU_LVD_VOL_SEL(sel));
+		assert_param(IS_PMU_LVD_TRIGGER_MODE(mode));
+
+		MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS);
+		MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS);
+		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK);
+		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
+		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
+		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
+	}
+	else {
+		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
+		CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
+		CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
+	}
+
+	SYSCFG_LOCK();
+	return;
+}
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+#endif /* ALD_PMU */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_rmu.c

@@ -0,0 +1,161 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_rmu.c
+  * @brief   RMU module driver.
+  *
+  * @version V1.0
+  * @date    04 Dec 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          04 Dec 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#include "ald_conf.h"
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup RMU RMU
+  * @brief RMU module driver
+  * @{
+  */
+#ifdef ALD_RMU
+
+/** @defgroup RMU_Public_Functions RMU Public Functions
+  * @{
+  */
+
+/**
+  * @brief  Configure BOR parameters.
+  * @param  flt: filter time.
+  * @param  vol: The voltage.
+  * @param  state: The new status: ENABLE/DISABLE.
+  * @retval None
+  */
+void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state)
+{
+	assert_param(IS_FUNC_STATE(state));
+
+	SYSCFG_UNLOCK();
+
+	if (state) {
+		assert_param(IS_RMU_BORFLT(flt));
+		assert_param(IS_RMU_BORVOL(vol));
+
+		MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS);
+		MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS);
+		SET_BIT(RMU->CR, RMU_CR_BOREN_MSK);
+	}
+	else {
+		CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK);
+	}
+
+	SYSCFG_LOCK();
+	return;
+}
+
+/**
+  * @brief  Get specified reset status
+  * @param  state: Speicifies the type of the reset,
+  * @retval The status.
+  */
+uint32_t ald_rmu_get_reset_status(rmu_state_t state)
+{
+	assert_param(IS_RMU_STATE(state));
+
+	if (state == RMU_RST_ALL)
+		return RMU->RSTSR;
+
+	if (READ_BIT(RMU->RSTSR, state))
+		return SET;
+
+	return RESET;
+}
+
+/**
+  * @brief  Clear the specified reset status
+  * @param  state: Specifies the type of the reset,
+  * @retval None
+  */
+void ald_rmu_clear_reset_status(rmu_state_t state)
+{
+	assert_param(IS_RMU_STATE_CLEAR(state));
+
+	SYSCFG_UNLOCK();
+	WRITE_REG(RMU->CRSTSR, state);
+	SYSCFG_LOCK();
+
+	return;
+}
+/**
+  * @brief  Reset peripheral device
+  * @param  perh: The peripheral device,
+  * @retval None
+  */
+void ald_rmu_reset_periperal(rmu_peripheral_t perh)
+{
+	uint32_t idx, pos;
+
+	assert_param(IS_RMU_PERH(perh));
+
+	idx = ((uint32_t)perh >> 27) & 0x7;
+	pos = perh & ~(0x7 << 27);
+	SYSCFG_UNLOCK();
+
+	switch (idx) {
+	case 0:
+		WRITE_REG(RMU->AHB1RSTR, pos);
+		break;
+
+	case 1:
+		WRITE_REG(RMU->AHB2RSTR, pos);
+		break;
+
+	case 2:
+		WRITE_REG(RMU->APB1RSTR, pos);
+		break;
+
+	case 4:
+		WRITE_REG(RMU->APB2RSTR, pos);
+		break;
+
+	default:
+		break;
+	}
+
+	SYSCFG_LOCK();
+	return;
+}
+
+/**
+  * @}
+  */
+#endif /* ALD_RMU */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_rtchw.c

@@ -0,0 +1,224 @@
+/**
+  ******************************************************************************
+  * @file    ald_rtchw.c
+  * @brief   RTCHW module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the RTC peripheral:
+  *           + Calibration functions
+  * @version V1.0
+  * @date    25 Apr 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          25 Apr 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#include "ald_conf.h"
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup RTCHW RTCHW
+  * @brief RTCHW module driver
+  * @{
+  */
+#ifdef ALD_RTC
+
+/** @addtogroup RTCHW_Private_Functions  RTCHW Private Functions
+  * @{
+  */
+/**
+  * @brief  delay losc clock
+  * @param  u: clock numbers.
+  * @retval None.
+  */
+static void delay_losc_clk(uint16_t u)
+{
+	uint16_t i, j;
+
+	for (i = 0; i < u; i++) {
+                for (j = 0; j < 60; j++) {
+                        __ASM volatile ("nop");
+                }
+	}
+}
+
+/**
+  * @brief  Check parameter for calibation
+  * @param  config: pointer to rtc_hw_cali_offset_t structure.
+  * @param  mode: Running mode, see @ref rtc_hw_cali_mode_t.
+  * @retval Status.
+  */
+static uint8_t rtc_hw_auto_check(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode)
+{
+	uint8_t tom = READ_BITS(TSENSE->CR, TSENSE_CR_TOM_MSK, TSENSE_CR_TOM_POSS);
+	uint8_t shift[8] = {0, 2, 4, 6, 8, 8, 8, 8};
+
+	if (mode == RTC_CALI_MODE_NORMAL) {
+		if ((RTC->CALCON & 0x1F3000F) != (RTCINFO->RTC_CALCR & 0x1F3000F))
+			return 1;
+	}
+	else {
+		if ((RTC->CALCON & 0x183000F) != (RTCINFO->RTC_CALCR & 0x183000F))
+			return 1;
+
+		if (READ_BITS(RTC->CALCON, RTC_CALCON_TCP_MSK, RTC_CALCON_TCP_POSS) != 7)	/* when sleep mode */ 
+			return 1;
+	}
+
+	if ((TSENSE->CR & 0x7702) != (RTCINFO->TEMP_CR & 0x7702))
+		return 1;
+	if (RTC->TEMPBDR != RTCINFO->RTC_TEMPBDR + config->offset_rtc_bdr)
+		return 1;
+	if (RTC->LTAXR != RTCINFO->RTC_LTAXR + config->offset_ltaxr)
+		return 1;
+	if (RTC->HTAXR != RTCINFO->RTC_HTAXR + config->offset_htaxr)
+		return 1;
+	if (RTC->HTAXR != RTCINFO->RTC_HTCAR + config->offset_htcar)
+		return 1;
+	if (RTC->HTCBR != RTCINFO->RTC_HTCBR + config->offset_htcbr)
+		return 1;
+	if (RTC->HTCCR != RTCINFO->RTC_HTCCR + config->offset_htccr)
+		return 1;
+	if (RTC->HTCDR != RTCINFO->RTC_HTCDR + config->offset_htcdr)
+		return 1;
+	if (RTC->HTCER != RTCINFO->RTC_HTCER + config->offset_htcer)
+		return 1;
+	if (RTC->LTAXR != RTCINFO->RTC_LTCAR + config->offset_ltcar)
+		return 1;
+	if (RTC->LTCBR != RTCINFO->RTC_LTCBR + config->offset_ltcbr)
+		return 1;
+	if (RTC->LTCCR != RTCINFO->RTC_LTCCR + config->offset_ltccr)
+		return 1;
+	if (RTC->LTCDR != RTCINFO->RTC_LTCDR + config->offset_ltcdr)
+		return 1;
+	if (RTC->LTCER != RTCINFO->RTC_LTCER + config->offset_ltcer)
+		return 1;
+	if (TSENSE->TBDR != (RTCINFO->TEMP_TBDR & 0xFFFF) + config->offset_temp_bdr)
+		return 1;
+	if (TSENSE->LTGR != RTCINFO->TEMP_LTGR + config->offset_ltgr)
+		return 1;
+	if (TSENSE->HTGR != RTCINFO->TEMP_HTGR + config->offset_htgr)
+		return 1;
+	if (TSENSE->TCALBDR != (((RTCINFO->TEMP_TCALBDR & 0x1FFFFFF) >> shift[tom]) & 0x1FFFF)
+				 + config->offset_tcalbdr)
+		return 1;
+
+	return 0;
+}
+/**
+  * @}
+  */
+
+/** @defgroup RTCHW_Public_Functions RTCHW Public Functions
+  * @{
+  */
+/**
+  * @brief  Hardware automatic calibate
+  * @param  config: pointer to rtc_hw_cali_offset_t structure.
+  * @param  mode: Running mode, see @ref rtc_hw_cali_mode_t
+  * @retval None
+  */
+void ald_rtc_hw_auto_cali(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode)
+{
+	uint8_t shift[8] = {0, 2, 4, 6, 8, 8, 8, 8};
+	uint8_t tmp;
+	uint32_t v = 0;
+	uint16_t temp_calf;
+
+	if (!(rtc_hw_auto_check(config, mode)))
+		return;
+
+	RTC_UNLOCK();
+	RTC_CALI_UNLOCK();
+	TSENSE_UNLOCK();
+
+	temp_calf = (uint16_t)RTC->CALDR;
+	while ((READ_BITS(RTC->IFR, RTC_IFR_TCCF_MSK, RTC_IFR_TCCF_POS) == 1) && (v < 0x20000))		/* no usr trig */
+		v++;
+
+	MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, 0 << RTC_CALCON_TCM_POSS);		/* disable auto compensation */
+	MODIFY_REG(TSENSE->CR, TSENSE_CR_REQEN_MSK, 0 << TSENSE_CR_REQEN_POS);		/* disable temp */
+
+	RTC->CALDR = temp_calf;
+	delay_losc_clk(3);
+
+	if (mode == RTC_CALI_MODE_NORMAL) {
+		v           = RTC->CALCON & ~0x01F0000F;
+		RTC->CALCON = v | (RTCINFO->RTC_CALCR & 0x01F0000F);
+	}
+	else {
+		v           = RTC->CALCON & ~0x0180000F;
+		RTC->CALCON = v | (RTCINFO->RTC_CALCR & 0x0180000F);
+		MODIFY_REG(RTC->CALCON, RTC_CALCON_TCP_MSK, 7 << RTC_CALCON_TCP_POSS);        // when sleep mode, caluate once in 1h
+	}
+
+	RTC->TEMPBDR  = RTCINFO->RTC_TEMPBDR + config->offset_rtc_bdr;
+	RTC->LTAXR    = RTCINFO->RTC_LTAXR + config->offset_ltaxr;
+	RTC->HTAXR    = RTCINFO->RTC_HTAXR + config->offset_htaxr;
+	RTC->LTCAR    = RTCINFO->RTC_LTCAR + config->offset_ltcar;
+	RTC->LTCBR    = RTCINFO->RTC_LTCBR + config->offset_ltcbr;
+	RTC->LTCCR    = RTCINFO->RTC_LTCCR + config->offset_ltccr;
+	RTC->LTCDR    = RTCINFO->RTC_LTCDR + config->offset_ltcdr;
+	RTC->LTCER    = RTCINFO->RTC_LTCER + config->offset_ltcer;
+	RTC->HTCAR    = RTCINFO->RTC_HTCAR + config->offset_htcar;
+	RTC->HTCBR    = RTCINFO->RTC_HTCBR + config->offset_htcbr;
+	RTC->HTCCR    = RTCINFO->RTC_HTCCR + config->offset_htccr;
+	RTC->HTCDR    = RTCINFO->RTC_HTCDR + config->offset_htcdr;
+	RTC->HTCER    = RTCINFO->RTC_HTCER + config->offset_htcer;
+	MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, 5 << RTC_CON_CKOS_POSS);		/* output accuracy 1Hz */
+
+	v               = TSENSE->CR & ~0x00007700;
+	TSENSE->CR      = v | (RTCINFO->TEMP_CR & 0x00007700);
+	TSENSE->HTGR    = RTCINFO->TEMP_HTGR + config->offset_htgr;
+	TSENSE->LTGR    = RTCINFO->TEMP_LTGR + config->offset_ltgr;
+	tmp             = READ_BITS(RTCINFO->TEMP_CR, TSENSE_CR_TOM_MSK, TSENSE_CR_TOM_POSS);
+	TSENSE->TCALBDR = ((RTCINFO->TEMP_TCALBDR & 0x1FFFFFF) >> shift[tmp]) + config->offset_tcalbdr;
+	TSENSE->TBDR    = RTCINFO->TEMP_TBDR + config->offset_temp_bdr;
+
+	delay_losc_clk(3);
+	tmp = READ_BITS(RTCINFO->TEMP_CR, TSENSE_CR_REQEN_MSK, TSENSE_CR_REQEN_POS);
+	MODIFY_REG(TSENSE->CR, TSENSE_CR_REQEN_MSK, tmp << TSENSE_CR_REQEN_POS);
+	MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, 3 << RTC_CALCON_TCM_POSS);	/* usr trig */
+
+	delay_losc_clk(3);
+	MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, 1 << RTC_TEMPR_VAL_POSS);	/* trig immediate*/
+
+	delay_losc_clk(3);
+	tmp           = READ_BITS(RTCINFO->RTC_CALCR, RTC_CALCON_TCM_MSK, RTC_CALCON_TCM_POSS);
+	MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, tmp << RTC_CALCON_TCM_POSS);
+
+	RTC_CALI_LOCK();
+	RTC_LOCK();
+	TSENSE_LOCK();
+	return;
+}
+/**
+  * @}
+  */
+#endif /* ALD_RTC */
+/**
+  * @}
+  */
+/**
+  * @}
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_sram.c

@@ -0,0 +1,397 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_sram.c
+  * @brief   SRAM module driver.
+  *
+  * @version V1.0
+  * @date    25 Dec 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          25 Dec 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+#include "ald_conf.h"
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup SRAM SRAM
+  * @brief SRAM module driver
+  * @{
+  */
+
+#ifdef ALD_SRAM
+
+/** @defgroup SRAM_Public_Functions SRAM Public Functions
+  * @{
+  */
+/** @defgroup SRAM_Public_Functions_Group1 Initialization functions
+  * @brief Initialization functions
+  * @{
+  */
+/**
+  * @brief  Performs the SRAM device initialization sequence
+  * @param  hperh: pointer to a sram_handle_t structure
+  * @param  timing: Pointer to SRAM control timing structure 
+  * @param  ext_timing: Pointer to SRAM extended mode timing structure  
+  * @retval ald status
+  */
+ald_status_t ald_sram_init(sram_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing)
+{
+	if (hperh == NULL)
+		return ERROR;
+
+	if (hperh->state == ALD_SRAM_STATE_RESET)
+		hperh->lock = UNLOCK;
+
+	/* Initialize SRAM control Interface */
+	ald_ebi_nor_sram_init(hperh->instance, &(hperh->init));
+	/* Initialize SRAM timing Interface */
+	ald_ebi_nor_sram_timing_init(hperh->instance, timing, hperh->init.bank);
+	/* Initialize SRAM extended mode timing Interface */
+	ald_ebi_nor_sram_ext_timing_init(hperh->ext, ext_timing, hperh->init.bank,  hperh->init.ext_mode);
+	/* Enable the NORSRAM device */
+	ald_ebi_nor_sram_enable(hperh->instance, hperh->init.bank);
+
+	return OK;
+}
+
+/**
+  * @brief  Performs the SRAM device De-initialization sequence.
+  * @param  hperh: pointer to a sram_handle_t structure 
+  * @retval ald status
+  */
+ald_status_t  ald_sram_deinit(sram_handle_t *hperh)
+{
+	ald_ebi_nor_sram_deinit(hperh->instance, hperh->ext, hperh->init.bank);
+	hperh->state = ALD_SRAM_STATE_RESET;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup SRAM_Public_Functions_Group2 I/O operation functions
+  * @brief I/O operation functions
+  * @{
+  */
+/**
+  * @brief  Reads 8-bit buffer from SRAM memory. 
+  * @param  hperh: pointer to a sram_handle_t structure 
+  * @param  addr: Pointer to read start address
+  * @param  buf: Pointer to destination buffer  
+  * @param  size: Size of the buffer to read from memory
+  * @retval ald status
+  */
+ald_status_t ald_sram_read_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size)
+{
+	__IO uint8_t * psramaddr = (uint8_t *)addr;
+
+	__LOCK(hperh);
+	hperh->state = ALD_SRAM_STATE_BUSY;
+
+	/* Read data from memory */
+	for (; size != 0U; size--)
+		*buf++ = *(__IO uint8_t *)psramaddr++;
+
+	hperh->state = ALD_SRAM_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Writes 8-bit buffer to SRAM memory. 
+  * @param  hperh: pointer to a sram_handle_t structure 
+  * @param  addr: Pointer to write start address
+  * @param  buf: Pointer to source buffer to write  
+  * @param  size: Size of the buffer to write to memory
+  * @retval ald status
+  */
+ald_status_t ald_sram_write_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size)
+{
+	__IO uint8_t * psramaddr = (uint8_t *)addr;
+
+	if (hperh->state == ALD_SRAM_STATE_PROTECTED)
+		return  ERROR;
+
+	__LOCK(hperh);
+	hperh->state = ALD_SRAM_STATE_BUSY;
+
+	/* Write data to memory */
+	for (; size != 0U; size--)
+		*(__IO uint8_t *)psramaddr++ = *buf++;
+
+	hperh->state = ALD_SRAM_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Reads 16-bit buffer from SRAM memory. 
+  * @param  hperh: pointer to a sram_handle_t structure that contains
+  *                the configuration information for SRAM module.
+  * @param  addr: Pointer to read start address
+  * @param  buf: Pointer to destination buffer  
+  * @param  size: Size of the buffer to read from memory
+  * @retval ald status
+  */
+ald_status_t ald_sram_read_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size)
+{
+	__IO uint16_t * psramaddr = (uint16_t *)addr;
+
+	__LOCK(hperh);
+	hperh->state = ALD_SRAM_STATE_BUSY;
+
+	/* Read data from memory */
+	for (; size != 0U; size--)
+		*buf++ = *(__IO uint16_t *)psramaddr++;
+
+	hperh->state = ALD_SRAM_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Writes 16-bit buffer to SRAM memory. 
+  * @param  hperh: pointer to a sram_handle_t structure that contains
+  *                the configuration information for SRAM module.
+  * @param  addr: Pointer to write start address
+  * @param  buf: Pointer to source buffer to write  
+  * @param  size: Size of the buffer to write to memory
+  * @retval ald status
+  */
+ald_status_t ald_sram_write_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size)
+{
+	__IO uint16_t * psramaddr = (uint16_t *)addr;
+
+	if (hperh->state == ALD_SRAM_STATE_PROTECTED)
+		return  ERROR;
+
+	__LOCK(hperh);
+	hperh->state = ALD_SRAM_STATE_BUSY;
+
+	/* Write data to memory */
+	for (; size != 0U; size--)
+		*(__IO uint16_t *)psramaddr++ = *buf++;
+
+	hperh->state = ALD_SRAM_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Reads 32-bit buffer from SRAM memory. 
+  * @param  hperh: pointer to a sram_handle_t structure 
+  * @param  addr: Pointer to read start address
+  * @param  buf: Pointer to destination buffer  
+  * @param  size: Size of the buffer to read from memory
+  * @retval ald status
+  */
+ald_status_t ald_sram_read_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size)
+{
+	__LOCK(hperh);
+	hperh->state = ALD_SRAM_STATE_BUSY;
+
+	/* Read data from memory */
+	for (; size != 0U; size--)
+		*buf++ = *(__IO uint32_t *)addr++;
+
+	hperh->state = ALD_SRAM_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Writes 32-bit buffer to SRAM memory. 
+  * @param  hperh: pointer to a sram_handle_t structure that contains
+  *                the configuration information for SRAM module.
+  * @param  addr: Pointer to write start address
+  * @param  buf: Pointer to source buffer to write  
+  * @param  size: Size of the buffer to write to memory
+  * @retval ald status
+  */
+ald_status_t ald_sram_write_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size)
+{
+	if (hperh->state == ALD_SRAM_STATE_PROTECTED)
+		return  ERROR;
+
+	__LOCK(hperh);
+	hperh->state = ALD_SRAM_STATE_BUSY;
+
+	/* Write data to memory */
+	for (; size != 0U; size--)
+		*(__IO uint32_t *)addr++ = *buf++;
+
+	hperh->state = ALD_SRAM_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+#ifdef ALD_DMA
+/**
+  * @brief  Reads a halfwords data from the SRAM memory using DMA transfer.
+  * @param  hperh: pointer to a sram_handle_t structure that contains
+  *                the configuration information for SRAM module.
+  * @param  addr: Pointer to read start address
+  * @param  buf: Pointer to destination buffer  
+  * @param  size: Size of the buffer to read from memory
+  * @param  ch: Index of DMA channel
+  * @retval ald status
+  */
+ald_status_t ald_sram_read_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch)
+{
+	if (buf == NULL)
+		return ERROR;
+
+	hperh->hdma.perh = DMA0;
+	hperh->hdma.cplt_cbk = hperh->cplt_cbk;
+	ald_dma_config_struct(&hperh->hdma.config);
+
+	hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD;
+	hperh->hdma.config.src        = (void *)addr;
+	hperh->hdma.config.dst        = (void *)buf;
+	hperh->hdma.config.size       = size;
+	hperh->hdma.config.src_inc    = DMA_DATA_INC_HALFWORD;
+	hperh->hdma.config.dst_inc    = DMA_DATA_INC_HALFWORD;
+	hperh->hdma.config.msel       = DMA_MSEL_NONE;
+	hperh->hdma.config.msigsel    = DMA_MSIGSEL_NONE;
+	hperh->hdma.config.channel    = ch;
+	hperh->hdma.config.R_power    = DMA_R_POWER_4;
+	hperh->hdma.config.burst      = ENABLE;
+
+	ald_dma_config_auto(&hperh->hdma);
+	return OK;
+}
+
+/**
+  * @brief  Write a halfwords data to the SRAM memory using DMA transfer.
+  * @param  hperh: pointer to a sram_handle_t structure that contains
+  *                the configuration information for SRAM module.
+  * @param  addr: Pointer to write start address
+  * @param  buf: Pointer to destination buffer  
+  * @param  size: Size of the buffer to write from memory
+  * @param  ch: Index of DMA channel
+  * @retval ald status
+  */
+ald_status_t ald_sram_write_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch)
+{
+	if (buf == NULL)
+		return ERROR;
+	;
+	hperh->hdma.perh = DMA0;
+	hperh->hdma.cplt_cbk = hperh->cplt_cbk;
+	ald_dma_config_struct(&hperh->hdma.config);
+
+	hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD;
+	hperh->hdma.config.src        = (void *)buf;
+	hperh->hdma.config.dst        = (void *)addr;
+	hperh->hdma.config.size       = size;
+	hperh->hdma.config.src_inc    = DMA_DATA_INC_HALFWORD;
+	hperh->hdma.config.dst_inc    = DMA_DATA_INC_HALFWORD;
+	hperh->hdma.config.msel       = DMA_MSEL_NONE;
+	hperh->hdma.config.msigsel    = DMA_MSIGSEL_NONE;
+	hperh->hdma.config.channel    = ch;
+	hperh->hdma.config.R_power    = DMA_R_POWER_4;
+	hperh->hdma.config.burst      = ENABLE;
+
+	ald_dma_config_auto(&hperh->hdma);
+	return OK;
+}
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup SRAM_Public_Functions_Group3 Control functions
+  * @brief Control functions
+  * @{
+  */
+/**
+  * @brief  Enables dynamically SRAM write operation.
+  * @param  hperh: pointer to a sram_handle_t structure
+  * @retval ald status
+  */
+ald_status_t ald_sram_write_enable(sram_handle_t *hperh)
+{
+	__LOCK(hperh);
+	ald_ebi_nor_sram_write_enable(hperh->instance, hperh->init.bank);
+	hperh->state = ALD_SRAM_STATE_READY;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+
+/**
+  * @brief  Disables dynamically SRAM write operation.
+  * @param  hperh: pointer to a sram_handle_t structure 
+  * @retval ald status
+  */
+ald_status_t ald_sram_write_disable(sram_handle_t *hperh)
+{
+	__LOCK(hperh);
+	hperh->state = ALD_SRAM_STATE_BUSY;
+	ald_ebi_nor_sram_write_disable(hperh->instance, hperh->init.bank);
+	hperh->state = ALD_SRAM_STATE_PROTECTED;
+	__UNLOCK(hperh);
+
+	return OK;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup SRAM_Public_Functions_Group4 State functions
+  * @brief State functions
+  * @{
+  */
+/**
+  * @brief  Returns the SRAM controller state
+  * @param  hperh: pointer to a SRAM_HandleTypeDef structure 
+  * @retval ald state
+  */
+ald_sram_state_t ald_sram_get_state(sram_handle_t *hperh)
+{
+	return hperh->state;
+}
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* ALD_SRAM */
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_trng.c

@@ -0,0 +1,323 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_trng.c
+  * @brief   TRNG module driver.
+  *
+  * @version V1.0
+  * @date    26 Jun 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          26 Jun 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#include "ald_conf.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup TRNG TRNG
+  * @brief TRNG module driver
+  * @{
+  */
+#ifdef ALD_TRNG
+
+/** @addtogroup CRYPT_Private_Functions CRYPT Private Functions
+  * @{
+  */
+void trng_reset(trng_handle_t *hperh);
+/**
+  * @}
+  */ 
+
+/** @defgroup TRNG_Public_Functions TRNG Public Functions
+  * @{
+  */
+
+/** @addtogroup TRNG_Public_Functions_Group1 Initialization functions
+  * @brief Initialization functions
+  *
+  * @verbatim
+  ==============================================================================
+              ##### Initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to initialize the TRNG:
+      (+) This parameters can be configured:
+        (++) Word Width
+        (++) Seed Type
+        (++) Seed
+        (++) Start Time
+        (++) Adjust parameter
+
+    @endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Initializes the TRNG according to the specified
+  *         parameters in the trng_init_t.
+  * @param  hperh: Pointer to a trng_handle_t structure that contains
+  *         the configuration information for the specified TRNG module.
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_trng_init(trng_handle_t *hperh)
+{
+	uint32_t tmp = 0;
+
+	if (hperh == NULL)
+		return ERROR;
+
+	assert_param(IS_TRNG_DATA_WIDTH(hperh->init.data_width));
+	assert_param(IS_TRNG_SEED_TYPE(hperh->init.seed_type));
+	assert_param(IS_TRNG_ADJC(hperh->init.adjc));
+	assert_param(IS_FUNC_STATE(hperh->init.posten));
+	assert_param(IS_TRNG_T_START(hperh->init.t_start));
+
+	__LOCK(hperh);
+	trng_reset(hperh);
+
+	if (hperh->state == TRNG_STATE_RESET)
+		__UNLOCK(hperh);
+
+	tmp = TRNG->CR;
+
+	if (hperh->init.adjc == 0)
+		tmp = (0 << TRNG_CR_ADJM_POS);
+	else
+		tmp = (1 << TRNG_CR_ADJM_POS);
+
+	tmp |= ((1 << TRNG_CR_TRNGSEL_POS) | (hperh->init.data_width << TRNG_CR_DSEL_POSS) |
+	       (hperh->init.seed_type << TRNG_CR_SDSEL_POSS) | (hperh->init.adjc << TRNG_CR_ADJC_POSS) |
+	       (hperh->init.posten << TRNG_CR_POSTEN_MSK));
+
+	TRNG->CR = tmp;
+
+	WRITE_REG(TRNG->SEED, hperh->init.seed);
+	MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (hperh->init.t_start) << TRNG_CFGR_TSTART_POSS);
+
+	hperh->state = TRNG_STATE_READY;
+	__UNLOCK(hperh);
+	return OK;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup TRNG_Public_Functions_Group2 Peripheral Control functions
+  * @brief Peripheral Control functions
+  *
+  * @verbatim
+  ==============================================================================
+              ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]  This section provides functions allowing to:
+    (+) ald_trng_get_result() API can Get the result.
+    (+) ald_trng_interrupt_config() API can be helpful to configure TRNG interrupt source.
+    (+) ald_trng_get_it_status() API can get the status of interrupt source.
+    (+) ald_trng_get_status() API can get the status of SR register.
+    (+) ald_trng_get_flag_status() API can get the status of interrupt flag.
+    (+) ald_trng_clear_flag_status() API can clear interrupt flag.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the result.
+  * @param  hperh: Pointer to a trng_handle_t structure that contains
+  *         the configuration information for the specified TRNG module.
+  * @retval The resultl
+  */
+uint32_t ald_trng_get_result(trng_handle_t *hperh)
+{
+	hperh->state = TRNG_STATE_READY;
+	hperh->data = hperh->perh->DR;
+	return (uint32_t)hperh->perh->DR;
+}
+
+/**
+  * @brief  Enable/disable the specified interrupts.
+  * @param  hperh: Pointer to a trng_handle_t structure that contains
+  *         the configuration information for the specified TRNG module.
+  * @param  it: Specifies the interrupt sources to be enabled or disabled.
+  *         This parameter can be one of the @ref trng_it_t.
+  * @param  state: New state of the specified interrupts.
+  *         This parameter can be:
+  *             @arg ENABLE
+  *             @arg DISABLE
+  * @retval None
+  */
+void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state)
+{
+	assert_param(IS_TRNG_IT(it));
+	assert_param(IS_FUNC_STATE(state));
+
+	if (state)
+		SET_BIT(hperh->perh->IER, it);
+	else
+		CLEAR_BIT(hperh->perh->IER, it);
+
+	return;
+}
+
+/**
+  * @brief  Get the status of SR register.
+  * @param  hperh: Pointer to a trng_handle_t structure that contains
+  *         the configuration information for the specified TRNG module.
+  * @param  status: Specifies the TRNG status type.
+  *         This parameter can be one of the @ref trng_status_t.
+  * @retval Status:
+  *           - 0: RESET
+  *           - 1: SET
+  */
+flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status)
+{
+	assert_param(IS_TRNG_STATUS(status));
+
+	if (READ_BIT(hperh->perh->SR, status))
+		return SET;
+
+	return RESET;
+}
+
+/**
+  * @brief  Get the status of interrupt source.
+  * @param  hperh: Pointer to a trng_handle_t structure that contains
+  *         the configuration information for the specified TRNG module.
+  * @param  it: Specifies the interrupt source.
+  *         This parameter can be one of the @ref trng_it_t.
+  * @retval Status:
+  *           - 0: RESET
+  *           - 1: SET
+  */
+it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it)
+{
+	assert_param(IS_TRNG_IT(it));
+
+	if (READ_BIT(hperh->perh->IER, it))
+		return SET;
+
+	return RESET;
+}
+
+/**
+  * @brief  Get the status of interrupt flag.
+  * @param  hperh: Pointer to a trng_handle_t structure that contains
+  *         the configuration information for the specified TRNG module.
+  * @param  flag: Specifies the interrupt flag.
+  *         This parameter can be one of the @ref trng_flag_t.
+  * @retval Status:
+  *           - 0: RESET
+  *           - 1: SET
+  */
+flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag)
+{
+	assert_param(IS_TRNG_FLAG(flag));
+
+	if (READ_BIT(hperh->perh->IFR, flag))
+		return SET;
+
+	return RESET;
+}
+
+/**
+  * @brief  Clear the interrupt flag.
+  * @param  hperh: Pointer to a trng_handle_t structure that contains
+  *         the configuration information for the specified TRNG module.
+  * @param  flag: Specifies the interrupt flag.
+  *         This parameter can be one of the @ref trng_flag_t.
+  * @retval None
+  */
+void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag)
+{
+	assert_param(IS_TRNG_FLAG(flag));
+	WRITE_REG(hperh->perh->IFCR, flag);
+
+	return;
+}
+
+/**
+  * @brief  Reset the TRNG peripheral.
+  * @param  hperh: Pointer to a trng_handle_t structure that contains
+  *         the configuration information for the specified TRNG module.
+  * @retval None
+  */
+void trng_reset(trng_handle_t *hperh)
+{
+	TRNG->CR   = 0;
+	TRNG->SEED = 0;
+	TRNG->CFGR = 0x1FF0707;
+	TRNG->IER  = 0;
+	TRNG->IFCR = 0xFFFFFFFF;
+
+	hperh->state = TRNG_STATE_READY;
+	__UNLOCK(hperh);
+	return;
+}
+
+/**
+  * @brief  This function handles TRNG interrupt request.
+  * @param  hperh: Pointer to a trng_handle_t structure that contains
+  *         the configuration information for the specified TRNG module.
+  * @retval None
+  */
+void ald_trng_irq_handler(trng_handle_t *hperh)
+{
+	if (ald_trng_get_flag_status(hperh, TRNG_IF_SERR) == SET) {
+		hperh->state = TRNG_STATE_ERROR;
+		ald_trng_clear_flag_status(hperh, TRNG_IF_SERR);
+		if (hperh->err_cplt_cbk)
+			hperh->err_cplt_cbk(hperh);
+		return;
+	}
+
+	if (ald_trng_get_flag_status(hperh, TRNG_IF_DAVLD) == SET) {
+		hperh->data = hperh->perh->DR;
+		hperh->state = TRNG_STATE_READY;
+		ald_trng_clear_flag_status(hperh, TRNG_IF_DAVLD);
+		if (hperh->trng_cplt_cbk)
+			hperh->trng_cplt_cbk(hperh);
+	}
+
+	if (ald_trng_get_flag_status(hperh, TRNG_IF_START) == SET) {
+		hperh->state = TRNG_STATE_BUSY;
+		ald_trng_clear_flag_status(hperh, TRNG_IF_START);
+		if (hperh->init_cplt_cbk)
+			hperh->init_cplt_cbk(hperh);
+	}
+}
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* ALD_TRNG */
+/**
+  * @}
+  */
+/**
+  * @}
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_tsense.c

@@ -0,0 +1,271 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_tsense.c
+  * @brief   TSENSE module driver.
+  *
+  * @version V1.0
+  * @date    26 Jun 2019
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          26 Jun 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#include "ald_conf.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup TSENSE TSENSE
+  * @brief TSENSE module driver
+  * @{
+  */
+#ifdef ALD_TSENSE
+
+
+/** @defgroup TSENSE_Private_Variables TSENSE Private Variables
+  * @{
+  */
+tsense_cbk __tsense_cbk;
+/**
+  * @}
+  */
+
+/** @defgroup TSENSE_Public_Functions TSENSE Public Functions
+  * @{
+  */
+
+/** @addtogroup TSENSE_Public_Functions_Group1 Initialization functions
+  * @brief Initialization functions
+  *
+  * @verbatim
+  ==============================================================================
+              ##### Initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to initialize the TSENSE:
+      (+) This parameters can be configured:
+        (++) Update Cycle
+        (++) Output Mode
+        (++) Perscaler
+      (+) Select TSENSE source clock(default LOSC)
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TSENSE according to the specified
+  * @retval None
+  */
+void ald_tsense_init(void)
+{
+	uint16_t tempt, temptinv;
+	uint32_t tscic, tscicinv;
+
+	TSENSE_UNLOCK();
+	TSENSE->CR = 0;
+
+	SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK);
+	SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK);
+	MODIFY_REG(TSENSE->CR, TSENSE_CR_TSU_MSK, 0x4 << TSENSE_CR_TSU_POSS);
+	MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, 0x3 << TSENSE_CR_TOM_POSS);
+	MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, 0x1 << TSENSE_PSR_PRS_POSS);
+
+	TSENSE->HTGR = 0x8564F;
+	TSENSE->LTGR = 0x87037;
+	tempt        = *(volatile uint16_t *)0x80348;
+	temptinv     = *(volatile uint16_t *)0x8034A;
+	tscic        = *(volatile uint32_t *)0x80350;
+	tscicinv     = *(volatile uint32_t *)0x80358;
+
+	if ((tempt == (uint16_t)(~temptinv)) && (tscic == (~tscicinv))) {
+		TSENSE->TBDR    = tempt;
+		TSENSE->TCALBDR = (tscic & 0x1FFFFFF) >> 6;
+	}
+	else {
+		TSENSE->TBDR    = 0x1E00;
+		TSENSE->TCALBDR = 0x1F849;
+	}
+
+	TSENSE_LOCK();
+	return;
+}
+
+/**
+  * @brief  Configure the TSENSE source.
+  * @param  sel: TSENSE source type.
+  * @retval None
+  */
+void ald_tsense_source_select(tsense_source_sel_t sel)
+{
+	assert_param(IS_TSENSE_SOURCE_SEL(sel));
+
+	BKPC_UNLOCK();
+	MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, sel << BKPC_PCCR_TSENSECS_POSS);
+
+	if (sel == TSENSE_SOURCE_LOSC) {
+		SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);
+	}
+	else if (sel == TSENSE_SOURCE_LRC) {
+		SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);
+	}
+	else {
+		; /* do nothing */
+	}
+
+	BKPC_LOCK();
+	return;
+}
+/**
+  * @}
+  */
+
+/** @addtogroup TSENSE_Public_Functions_Group2 Peripheral Control functions
+  * @brief Peripheral Control functions
+  *
+  * @verbatim
+  ==============================================================================
+              ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]  This section provides functions allowing to:
+    (+) ald_tsense_get_value() API can get the current temperature.
+    (+) ald_tsense_get_value_by_it() API can get the current temperature by interrupt.
+    (+) ald_tsense_irq_handler() API can handle the interrupt request.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the current temperature
+  * @param  tsense: The value of current temperature.
+  * @retval ALD status:
+  *         @arg @ref OK    The value is valid
+  *         @arg @ref ERROR The value is invalid
+  */
+ald_status_t ald_tsense_get_value(uint16_t *tsense)
+{
+	uint32_t tmp = 0;
+
+	TSENSE_UNLOCK();
+	SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
+	SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
+	TSENSE_LOCK();
+
+	while ((!(READ_BIT(TSENSE->IF, TSENSE_IF_TSENSE_MSK))) && (tmp++ < 1000000));
+
+	if (tmp >= 1000000) {
+		TSENSE_UNLOCK();
+		CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
+		TSENSE_LOCK();
+		return TIMEOUT;
+	}
+
+	TSENSE_UNLOCK();
+	SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
+	TSENSE_LOCK();
+
+	if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) {
+		TSENSE_UNLOCK();
+		CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
+		TSENSE_LOCK();
+		return ERROR;
+	}
+
+	*tsense = READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS);
+
+	TSENSE_UNLOCK();
+	CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
+	TSENSE_LOCK();
+
+	return OK;
+}
+
+/**
+  * @brief  Get the current temperature by interrupt
+  * @param  cbk: The callback function
+  * @retval None
+  */
+void ald_tsense_get_value_by_it(tsense_cbk cbk)
+{
+	__tsense_cbk = cbk;
+
+	TSENSE_UNLOCK();
+	SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
+	SET_BIT(TSENSE->IE, TSENSE_IE_TSENSE_MSK);
+	SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
+	TSENSE_LOCK();
+
+	return;
+}
+
+/**
+  * @brief  This function handles TSENSE interrupt request.
+  * @retval None
+  */
+void ald_tsense_irq_handler(void)
+{
+	TSENSE_UNLOCK();
+	SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
+	TSENSE_LOCK();
+
+	if (__tsense_cbk == NULL) {
+		TSENSE_UNLOCK();
+		CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
+		TSENSE_LOCK();
+		return;
+	}
+
+	if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) {
+		TSENSE_UNLOCK();
+		CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
+		TSENSE_LOCK();
+		__tsense_cbk(0, ERROR);
+
+		return;
+	}
+
+	__tsense_cbk(READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS), OK);
+
+	TSENSE_UNLOCK();
+	SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
+	CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
+	TSENSE_LOCK();
+
+	return;
+}
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+#endif /* ALD_TSENSE */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

demo/es32/Drivers/ALD/ES32F36xx/Source/ald_wdt.c

@@ -0,0 +1,238 @@
+/**
+ *********************************************************************************
+ *
+ * @file    ald_wdt.c
+ * @brief   WDT module driver.
+ *
+ * @version V1.0
+ * @date    18 Dec 2019
+ * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          18 Dec 2019     AE Team         The first version
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+ */
+#include "ald_conf.h"
+
+/** @addtogroup ES32FXXX_ALD
+ * @{
+ */
+
+/** @defgroup WDT WDT
+ * @brief WDT module driver
+ * @{
+ */
+#ifdef ALD_WDT
+
+
+/** @defgroup WWDT_Public_Functions WWDT Public Functions
+ * @brief Init and configure WWDT function
+ * @{
+ */
+/**
+ * @brief Initializes the WWDT according to the specified parameters.
+ * @param load: Specifies the free-running downcounter value.
+ * @param win: specifics the no dog windows,
+ *        the parameter can be one of the following values:
+ *        @arg @ref WWDT_WIN_25 No dog window size: 25%
+ *        @arg @ref WWDT_WIN_50 No dog window size: 50%
+ *        @arg @ref WWDT_WIN_75 No dog window size: 75%
+ *        @arg @ref WWDT_WIN_00 No dog window size: 0%
+ * @param interrupt: Enable or disable interrupt.
+ * @retval None
+ */
+void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt)
+{
+	assert_param(IS_WWDT_WIN_TYPE(win));
+	assert_param(IS_FUNC_STATE(interrupt));
+
+	WWDT_UNLOCK();
+	WRITE_REG(WWDT->LOAD, load);
+	MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, win << WWDT_CON_WWDTWIN_POSS);
+	SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK);
+	SET_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK);
+	MODIFY_REG(WWDT->CON, WWDT_CON_IE_MSK, interrupt << WWDT_CON_IE_POS);
+	WWDT_LOCK();
+
+	return;
+}
+
+/**
+ * @brief Start the WWDT
+ * @retval None
+ */
+void ald_wwdt_start(void)
+{
+	WWDT_UNLOCK();
+	SET_BIT(WWDT->CON, WWDT_CON_EN_MSK);
+	WWDT_LOCK();
+
+	return;
+}
+
+/**
+ * @brief Get the free-running downcounter value
+ * @retval Value
+ */
+uint32_t ald_wwdt_get_value(void)
+{
+	return WWDT->VALUE;
+}
+
+/**
+ * @brief Get interrupt state
+ * @retval Value
+ */
+it_status_t ald_wwdt_get_flag_status(void)
+{
+	if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK))
+		return SET;
+
+	return RESET;
+}
+
+/**
+ * @brief Clear interrupt state
+ * @retval None
+ */
+void ald_wwdt_clear_flag_status(void)
+{
+	WRITE_REG(WWDT->INTCLR, 1);
+	return;
+}
+
+/**
+ * @brief Refreshes the WWDT
+ * @retval None
+ */
+void ald_wwdt_feed_dog(void)
+{
+	uint16_t i = 0;
+	
+	WWDT_UNLOCK();
+	WRITE_REG(WWDT->INTCLR, 0x1);
+	WWDT_LOCK();
+	for (i = 0; i < 0x2ff; ++i)
+		__NOP();
+
+	return;
+}
+/**
+ * @}
+ */
+
+/** @defgroup IWDT_Public_Functions IWDT Public Functions
+ * @brief Init and configure IWDT function
+ * @{
+ */
+/**
+ * @brief Initializes the IWDG according to the specified parameters.
+ * @param load: Specifies the free-running downcounter value.
+ * @param interrupt: Enable or disable interrupt.
+ * @retval None
+ */
+void ald_iwdt_init(uint32_t load, type_func_t interrupt)
+{
+	assert_param(IS_FUNC_STATE(interrupt));
+
+	IWDT_UNLOCK();
+	WRITE_REG(IWDT->LOAD, load);
+	SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK);
+	SET_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK);
+	MODIFY_REG(IWDT->CON, IWDT_CON_IE_MSK, interrupt << IWDT_CON_IE_POS);
+	IWDT_LOCK();
+
+	return;
+}
+
+/**
+ * @brief Start the IWDT
+ * @retval None
+ */
+void ald_iwdt_start(void)
+{
+	IWDT_UNLOCK();
+	SET_BIT(IWDT->CON, IWDT_CON_EN_MSK);
+	IWDT_LOCK();
+
+	return;
+}
+
+/**
+ * @brief Get the free-running downcounter value
+ * @retval Value
+ */
+uint32_t ald_iwdt_get_value(void)
+{
+	return IWDT->VALUE;
+}
+
+/**
+ * @brief Get interrupt state
+ * @retval Value
+ */
+it_status_t ald_iwdt_get_flag_status(void)
+{
+	if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK))
+		return SET;
+
+	return RESET;
+}
+
+/**
+ * @brief Clear interrupt state
+ * @retval None
+ */
+void ald_iwdt_clear_flag_status(void)
+{
+	IWDT_UNLOCK();
+	WRITE_REG(IWDT->INTCLR, 1);
+	IWDT_LOCK();
+	return;
+}
+
+/**
+ * @brief Refreshes the WWDT
+ * @retval None
+ */
+void ald_iwdt_feed_dog(void)
+{
+	uint16_t i = 0;
+	
+	IWDT_UNLOCK();
+	WRITE_REG(IWDT->INTCLR, 1);
+	IWDT_LOCK();
+	for (i = 0; i < 0x2ff; ++i)
+		__NOP();
+	
+	return;
+}
+/**
+ * @}
+ */
+
+#endif /* ALD_WDT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */

demo/es32/Drivers/ALD/ES32F36xx/Source/utils.c

@@ -0,0 +1,715 @@
+/**
+  *********************************************************************************
+  *
+  * @file    utils.c
+  * @brief   This file contains the Utilities functions/types for the driver.
+  *
+  * @version V1.1
+  * @date    13 Apr 2021
+  * @author  AE Team
+  * @note
+  *          Change Logs:
+  *          Date            Author          Notes
+  *          07 Nov 2019     AE Team         The first version
+  *          13 Apr 2021     AE Team         Add API: sys_config()
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  **********************************************************************************
+  */
+
+#include <string.h>
+#include "ald_conf.h"
+
+/** @defgroup ES32FXXX_ALD EASTSOFT ES32F3xx ALD
+  * @brief Shanghai Eastsoft Microelectronics Cortex-M Chip Abstraction Layer Driver(ALD)
+  * @{
+  */
+
+/** @defgroup UTILS Utils
+  * @brief Utils module driver
+  * @{
+  */
+
+/** @defgroup ALD_Private_Constants Private Constants
+  * @brief ALD Private Constants
+  * @{
+  */
+
+/**
+  * @brief ALD version number
+  */
+#define __ALD_VERSION_MAIN	(0x01) /**< [31:24] main version */
+#define __ALD_VERSION_SUB1	(0x00) /**< [23:16] sub1 version */
+#define __ALD_VERSION_SUB2	(0x00) /**< [15:8]  sub2 version */
+#define __ALD_VERSION_RC	(0x00) /**< [7:0]  release candidate */
+#define __ALD_VERSION		((__ALD_VERSION_MAIN << 24) | \
+                                 (__ALD_VERSION_SUB1 << 16) | \
+                                 (__ALD_VERSION_SUB2 << 8 ) | \
+                                 (__ALD_VERSION_RC))
+/**
+  * @}
+  */
+
+/** @defgroup ALD_Private_Variables Private Variables
+  * @{
+  */
+/** @brief lib_tick: Increase by one millisecond
+  */
+static __IO uint32_t lib_tick;
+uint32_t __systick_interval = SYSTICK_INTERVAL_1MS;
+/**
+  * @}
+  */
+
+
+/** @defgroup ALD_Public_Functions Public Functions
+  * @{
+  */
+
+/** @defgroup ALD_Public_Functions_Group1 Initialization Function
+  * @brief    Initialization functions
+  *
+  * @verbatim
+ ===============================================================================
+              ##### Initialization functions #####
+ ===============================================================================
+   [..]  This section provides functions allowing to:
+      (+) Initializes interface, the NVIC allocation and initial clock
+          configuration. It initializes the source of time base also when timeout
+          is needed and the backup domain when enabled.
+      (+) Configure The time base source to have 1ms time base with a dedicated
+          Tick interrupt priority.
+        (++) Systick timer is used by default as source of time base, but user
+             can eventually implement his proper time base source (a general purpose
+             timer for example or other time source), keeping in mind that Time base
+             duration should be kept 1ms.
+        (++) Time base configuration function (ald_tick_init()) is called automatically
+             at the beginning of the program after reset by ald_cmu_init() or at
+	     any time when clock is configured.
+        (++) Source of time base is configured  to generate interrupts at regular
+             time intervals. Care must be taken if ald_delay_ms() is called from a
+             peripheral ISR process, the Tick interrupt line must have higher priority
+            (numerically lower) than the peripheral interrupt. Otherwise the caller
+            ISR process will be blocked.
+       (++) functions affecting time base configurations are declared as __weak
+             to make  override possible  in case of other implementations in user file.
+      (+) Configure the interval of Systick interrupt.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function Configures time base source, NVIC and DMA.
+  * @note   This function is called at the beginning of program after reset and before
+  *         the clock configuration.
+  * @note   The time base configuration is based on MSI clock when exiting from Reset.
+  *         Once done, time base tick start incrementing.
+  *         In the default implementation, Systick is used as source of time base.
+  *         The tick variable is incremented each 1ms in its ISR.
+  * @retval None
+  */
+void ald_cmu_init(void)
+{
+	NVIC_SetPriorityGrouping(NVIC_PRIORITY_GROUP_2);
+	ald_cmu_clock_config_default();
+	ald_tick_init(TICK_INT_PRIORITY);
+#ifdef ALD_DMA
+	ald_cmu_perh_clock_config(CMU_PERH_DMA, ENABLE);
+	ald_dma_init(DMA0);
+#endif
+	return;
+}
+
+/**
+  * @brief  This function configures the source of the time base.
+  *         The time source is configured to have 1ms time base with a dedicated
+  *         Tick interrupt priority.
+  * @note   In the default implementation, SysTick timer is the source of time base.
+  *         It is used to generate interrupts at regular time intervals.
+  *         Care must be taken if ald_delay_ms() is called from a peripheral ISR process,
+  *         The SysTick interrupt must have higher priority (numerically lower)
+  *         than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+  *         The function is declared as __weak to be overwritten in case of other
+  *         implementation in user file.
+  * @param  prio: Tick interrupt priority.
+  * @retval None
+  */
+__weak void ald_tick_init(uint32_t prio)
+{
+	/* Configure the SysTick IRQ */
+	SysTick_Config(ald_cmu_get_sys_clock() / SYSTICK_INTERVAL_1MS);
+	NVIC_SetPriority(SysTick_IRQn, prio);
+	
+	return;
+}
+
+/**
+  * @brief  Selects the interval of systick interrupt.
+  * @param  value: The value of interval:
+  *           @arg @ref SYSTICK_INTERVAL_1MS    1 millisecond
+  *           @arg @ref SYSTICK_INTERVAL_10MS   10 milliseconds
+  *           @arg @ref SYSTICK_INTERVAL_100MS  100 milliseconds
+  *           @arg @ref SYSTICK_INTERVAL_1000MS 1 second
+  * @retval None
+  */
+void ald_systick_interval_select(systick_interval_t value)
+{
+	assert_param(IS_SYSTICK_INTERVAL(value));
+	
+	if (value == 0) return;
+
+	SysTick_Config(ald_cmu_get_sys_clock() / value);
+	__systick_interval = value;
+
+	if (TICK_INT_PRIORITY != 15)
+		NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY);
+
+	return;
+}
+/**
+  * @}
+  */
+
+/** @defgroup ALD_Public_Functions_Group2 Control functions
+  * @brief    Control functions
+  *
+  * @verbatim
+ ===============================================================================
+                      ##### Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Provide a tick value in millisecond
+      (+) Provide a blocking delay in millisecond
+      (+) Suspend the time base source interrupt
+      (+) Resume the time base source interrupt
+      (+) Get the ALD version
+      (+) Waiting for flag
+      (+) Configure the interrupt
+      (+) Provide system tick value
+      (+) Initialize core timestamp
+      (+) Get core timestamp
+      (+) Get CPU ID
+      (+) Get UID
+      (+) Get CHIPID
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function invoked by Systick ISR.
+  * @note   This function is declared as __weak to be overwritten in case of
+  *         other implementations in user file.
+  * @retval None
+  */
+__weak void ald_systick_irq_cbk(void)
+{
+	/* do nothing */
+	return;
+}
+
+/**
+  * @brief  This function is called to increment a global variable "lib_tick"
+  *         used as application time base.
+  * @note   In the default implementation, this variable is incremented each 1ms
+  *         in Systick ISR.
+  * @note   This function is declared as __weak to be overwritten in case of other
+  *         implementations in user file.
+  * @retval None
+  */
+__weak void ald_inc_tick(void)
+{
+	++lib_tick;
+	ald_systick_irq_cbk();
+}
+
+/**
+  * @brief  Provides a tick value in millisecond.
+  * @note   This function is declared as __weak to be overwritten in case of other
+  *         implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t ald_get_tick(void)
+{
+	return lib_tick;
+}
+
+/**
+  * @brief  This function provides accurate delay (in microseconds) based
+  *         on variable incremented.
+  * @note   In the default implementation, SysTick timer is the source of time base.
+  *         It is used to generate interrupts at regular time intervals where lib_tick
+  *         is incremented.
+  * @note   This function is declared as __weak to be overwritten in case of other
+  *         implementations in user file.
+  * @param  delay: specifies the delay time length, in microseconds(us).
+  * @retval None
+  */
+__weak void ald_delay_us(__IO uint32_t delay)
+{
+    uint32_t start, now, delta, reload, us_tick;
+    start = SysTick->VAL;
+    reload = SysTick->LOAD;
+    us_tick = ald_cmu_get_sys_clock() / 1000000UL;
+    do
+    {
+        now = SysTick->VAL;
+        delta = (start > now) ? (start - now) : (reload + start - now);
+    }
+    while (delta <  (us_tick * delay));
+}
+
+/**
+  * @brief  This function provides accurate delay (in milliseconds) based
+  *         on variable incremented.
+  * @note   In the default implementation, SysTick timer is the source of time base.
+  *         It is used to generate interrupts at regular time intervals where lib_tick
+  *         is incremented.
+  * @note   This function is declared as __weak to be overwritten in case of other
+  *         implementations in user file.
+  * @param  delay: specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+__weak void ald_delay_ms(__IO uint32_t delay)
+{
+	uint32_t tick, __delay;
+
+	switch (__systick_interval) {
+	case SYSTICK_INTERVAL_1MS:
+		__delay = delay;
+		break;
+
+	case SYSTICK_INTERVAL_10MS:
+		__delay = delay / 10;
+		break;
+
+	case SYSTICK_INTERVAL_100MS:
+		__delay = delay / 100;
+		break;
+
+	case SYSTICK_INTERVAL_1000MS:
+		__delay = delay / 1000;
+		break;
+
+	default:
+		__delay = delay;
+		break;
+	}
+
+	tick    = ald_get_tick();
+	__delay = __delay == 0 ? 1 : __delay;
+
+	while ((ald_get_tick() - tick) < __delay)
+		;
+}
+
+/**
+  * @brief  Suspend Tick increment.
+  * @note   In the default implementation, SysTick timer is the source of time base.
+  *         It is used to generate interrupts at regular time intervals.
+  *         Once ald_suspend_tick() is called, the the SysTick interrupt
+  *         will be disabled and so Tick increment is suspended.
+  * @note   This function is declared as __weak to be overwritten
+  *         in case of other implementations in user file.
+  * @retval None
+  */
+__weak void ald_suspend_tick(void)
+{
+	CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Resume Tick increment.
+  * @note   In the default implementation, SysTick timer is the source of
+  *         time base. It is used to generate interrupts at regular time
+  *         intervals. Once ald_resume_tick() is called, the the SysTick
+  *         interrupt will be enabled and so Tick increment is resumed.
+  * @note   This function is declared as __weak to be overwritten
+  *         in case of other implementations in user file.
+  * @retval None
+  */
+__weak void ald_resume_tick(void)
+{
+	SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  This method returns the ALD revision
+  * @retval version: 0xXYZR (8bits for each decimal, R for RC)
+  */
+uint32_t ald_get_ald_version(void)
+{
+	return __ALD_VERSION;
+}
+
+/**
+  * @brief  Configure the flash wait period.
+  * @param  cycle: The period.
+  * @retval None
+  */
+void ald_flash_wait_config(uint8_t cycle)
+{
+	uint32_t tmp;
+
+	tmp = MSC->MEMWAIT;
+	MODIFY_REG(tmp, MSC_MEMWAIT_FLASH_W_MSK, (0x30U | cycle) << MSC_MEMWAIT_FLASH_W_POSS);
+	MSC->MEMWAIT = tmp;
+
+	return;
+}
+
+/**
+  * @brief  Waiting the specified bit in the register change to SET/RESET.
+  * @param  reg: The register address.
+  * @param  bit: The specified bit.
+  * @param  status: The status for waiting.
+  * @param  timeout: Timeout duration.
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout)
+{
+	uint32_t tick = ald_get_tick();
+
+	assert_param(timeout > 0);
+
+	if (status == SET) {
+		while (!(IS_BIT_SET(*reg, bit))) {
+			if (((ald_get_tick()) - tick) > timeout)
+				return TIMEOUT;
+		}
+	}
+	else {
+		while ((IS_BIT_SET(*reg, bit))) {
+			if (((ald_get_tick()) - tick) > timeout)
+				return TIMEOUT;
+		}
+	}
+
+	return OK;
+}
+
+/**
+  * @brief  Configure interrupt.
+  * @param  irq: Interrunpt type.
+  * @param  preempt_prio: preempt priority(0-3).
+  * @param  sub_prio: sub-priority(0-3).
+  * @param  status: Status.
+  *           @arg ENABLE
+  *           @arg DISABLE
+  * @retval None
+  */
+void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status)
+{
+	uint32_t pri;
+	uint8_t sub_bw, pre_bw;
+	uint8_t sub_mask = 0xF;
+
+	assert_param(IS_FUNC_STATE(status));
+	assert_param(IS_PREEMPT_PRIO(preempt_prio));
+	assert_param(IS_SUB_PRIO(sub_prio));
+
+	if (status == ENABLE) {
+		pre_bw     = 7 - (((SCB->AIRCR) >> 8) & 7);
+		sub_bw     = 4 - pre_bw;
+		sub_mask >>= pre_bw;
+
+		pri  = preempt_prio << sub_bw;
+		pri |= sub_prio & sub_mask;
+
+		NVIC_SetPriority(irq, pri);
+		NVIC_EnableIRQ(irq);
+	}
+	else {
+		NVIC_DisableIRQ(irq);
+	}
+
+	return;
+}
+
+/**
+  * @brief  Initialize core timestamp.
+  * @retval None
+  */
+void ald_mcu_timestamp_init(void)
+{
+	DEM_CR    |= (uint32_t)DEM_CR_TRCENA;
+	DWT_CYCCNT = 0x0;
+	DWT_CR    |= (uint32_t)DWT_CR_CYCCNTEA;
+
+	return;
+}
+
+/**
+  * @brief  Get core timestamp.
+  * @retval None
+  */
+uint32_t ald_mcu_get_timestamp(void)
+{
+	return (uint32_t)DWT_CYCCNT;
+}
+
+/**
+  * @brief  Get the CPU ID.
+  * @retval CPU ID.
+  */
+uint32_t ald_mcu_get_cpu_id(void)
+{
+	return SCB->CPUID;
+}
+
+/**
+  * @brief  Get the UID.
+  * @param  buf: Pointer to UID, len: 12Bytes(96-bits)
+  * @retval None
+  */
+void ald_mcu_get_uid(uint8_t *buf)
+{
+	memcpy(&buf[0], (void *)MCU_UID0_ADDR, 4);
+	memcpy(&buf[4], (void *)MCU_UID1_ADDR, 4);
+	memcpy(&buf[8], (void *)MCU_UID2_ADDR, 4);
+
+	return;
+}
+
+/**
+  * @brief  Get the CHIPID
+  * @retval CHPID
+  */
+uint32_t ald_mcu_get_chipid(void)
+{
+	return (uint32_t)*(uint32_t *)MCU_CHIPID_ADDR;
+}
+
+/**
+  * @brief  Bypass bootroom and set VR1_Ref 0xA
+  * @retval None
+  */
+void sys_config(void)
+{
+	uint32_t i = 0, tmp = 0;
+	uint8_t err = 0, flag = 0;
+	uint32_t inf014 = 0, inf0154 = 0, inf0244 = 0;
+	uint8_t cnt = 4;
+
+	uint32_t *inf0_addr = (uint32_t *)0x20003C00;
+	/* read bootroom cfg register */
+	inf014  = *((uint32_t *)(0x80000 + 56));
+	/* read VR1_VREF register */
+	inf0154 = *((uint32_t *)(0x80000 + 616));
+	/* read Chip_v */
+	inf0244 = *((uint32_t *)(0x80000 + 0x03D0));
+	
+	/* if D version ,do nothing */
+	if (inf0244 == 0xFFFFFF44) return;
+	
+	if (inf0154 == 0xFFFFFFFF)
+		while(1);
+	
+	/* if bypass bootroom */
+	if ((0xFFFFFFFF != inf014)) { 
+		/* change cfg_boot value = 0xffff */
+		inf014 = 0xFFFFFFFF; 
+		flag   = 0x1;
+	}
+
+	/* change CFG_VR1_VREF value, FLASH ref 0xA */
+	tmp = (inf0154 >> 8) & 0xF;
+	if (0xA != tmp) {
+		inf0154 &= (uint32_t)~(0xF << 8);
+		inf0154 |= (0xA << 8);
+		inf0154 = (inf0154 & (0x0000FFFF)) | ((~(inf0154 & 0xFFFF)) << 16);
+		flag = 0x1;
+	}
+	
+	/* if flag reset, return */
+	if (0x0 == flag)
+		return;
+	
+	/* 0x80000, 256words,INFO0 value */
+	for (i = 0; i < 256; i++)
+		inf0_addr[i] = *((uint32_t *)(0x80000 + i * 4));
+
+	/* refresh value */
+	inf0_addr[14]  = inf014;
+	inf0_addr[154] = inf0154;
+
+	while(--cnt) {
+		err = 0;
+		/* unlock */
+		*((volatile uint32_t *)(0x40080000)) = 0x55AA6996;
+		*((volatile uint32_t *)(0x40080100)) = 0x5A962814;
+		*((volatile uint32_t *)(0x40080100)) = 0xE7CB69A5;	
+
+		/* erase */
+		if (ald_iap_erase_page(0x80000) == OK) {
+			/* program 256*4bytes, info0 */
+			if (ald_iap_program_words(0x80000, (uint8_t *)inf0_addr, 1024, 0) == OK) {
+				/* check */
+				for (i = 0; i < 256; i++) {
+					if (inf0_addr[i] != *((uint32_t *)(0x80000 + i * 4))) {
+						err = 1;
+						break;;
+					}
+				}
+				if (err == 0) { 
+					/* lock */
+					*((volatile uint32_t *)(0x40080100)) = 0x123456;
+					*((volatile uint32_t *)(0x40080100)) = 0x123456;
+					*((volatile uint32_t *)(0x40080000)) = 0x123456;
+					return;
+				}
+			}
+			else {
+				err = 1;
+			}
+		}
+		else {
+			err = 1;
+		}
+	}
+
+	if (err) {
+		ald_iap_erase_page(0x80000);
+		/* lock */
+		*((volatile uint32_t *)(0x40080100)) = 0x123456;
+		*((volatile uint32_t *)(0x40080100)) = 0x123456;
+		*((volatile uint32_t *)(0x40080000)) = 0x123456;
+		while(1);
+	}
+}
+
+/**
+  * @brief  ADC adjust parameter config
+  * @retval None
+  */
+void adc_config(void)
+{
+	uint32_t inf0176 = 0, inf0178 = 0;
+	uint32_t inf0250 = 0, inf0251 = 0;
+	uint32_t inf0242 = 0, i = 0;
+	uint8_t flag = 0, err = 0;
+	uint8_t cnt = 4;
+	/* ram store inf0 1k buffer, 15k ~ 16k */
+	uint32_t *inf0_addr = (uint32_t *)0x20003C00;
+
+	/* Read ADC_GE */
+	inf0242 = *((uint32_t *)(0x80000 + 968));
+
+	if (0xF5230ADC == inf0242)  return;
+
+	/* read Lot ID */
+	inf0250 = *((uint32_t *)(0x80000 + 1000));
+	inf0251 = *((uint32_t *)(0x80000 + 1004));
+	inf0251 = (inf0251 & 0xFFFF0000) >> 16;
+
+	/* read CFG_ADC0DA/CFG_ADC1DA */
+	inf0176 = *((uint32_t *)(0x80000 + 704));
+	inf0178 = *((uint32_t *)(0x80000 + 712));
+
+	switch(inf0250) {
+		case 0x45465537:
+			if ((inf0251 == 0x3034) || (inf0251 == 0x3035))
+				flag = 1;
+			break;
+		case 0x45503931:
+			if ((inf0251 == 0x3732) || (inf0251 == 0x3734))
+				flag = 1;
+			break;
+		case 0x45503935:
+			if ((inf0251 == 0x3837) || (inf0251 == 0x3839))
+				flag = 1;
+			break;
+		default:
+			break;
+	}
+
+	if (!flag)  return;
+        
+	inf0176 ^= (0x1 << 15);
+	inf0176  = (inf0176 & 0x0000FFFF) | ((~(inf0176 & 0xFFFF)) << 16);
+
+	inf0178 ^= (0x1 << 15);
+	inf0178  = (inf0178 & 0x0000FFFF) | ((~(inf0178 & 0xFFFF)) << 16);
+
+	/* 0x80000, 256words,INFO0 value */
+	for (i = 0; i < 256; i++)
+		inf0_addr[i] = *((uint32_t *)(0x80000 + i * 4));
+
+	inf0_addr[176] = inf0176;
+	inf0_addr[178] = inf0178;
+	inf0_addr[242] = 0xF5230ADC;
+
+	while(--cnt) {
+		err = 0;
+		/* unlock */
+		*((volatile uint32_t *)(0x40080000)) = 0x55AA6996;
+		*((volatile uint32_t *)(0x40080100)) = 0x5A962814;
+		*((volatile uint32_t *)(0x40080100)) = 0xE7CB69A5;	
+
+		/* erase */
+		if (ald_iap_erase_page(0x80000) == OK) {
+			/* program 256*4bytes, info0 */
+			if (ald_iap_program_words(0x80000, (uint8_t *)inf0_addr, 1024, 0) == OK) {
+				/* check */
+				for (i = 0; i < 256; i++) {
+					if (inf0_addr[i] != *((uint32_t *)(0x80000 + i * 4))) {
+						err = 1;
+						break;;
+					}
+				}
+				if (err == 0) { 
+					/* lock */
+					*((volatile uint32_t *)(0x40080100)) = 0x123456;
+					*((volatile uint32_t *)(0x40080100)) = 0x123456;
+					*((volatile uint32_t *)(0x40080000)) = 0x123456;
+					return;
+				}
+			}
+			else {
+				err = 1;
+			}
+		}
+		else {
+			err = 1;
+		}
+	}
+
+	if (err) {
+		ald_iap_erase_page(0x80000);
+		/* lock */
+		*((volatile uint32_t *)(0x40080100)) = 0x123456;
+		*((volatile uint32_t *)(0x40080100)) = 0x123456;
+		*((volatile uint32_t *)(0x40080000)) = 0x123456;
+		while(1);
+	}
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */