From 07012ee1c1adb3d003a3ab8660fb6ad9c7fab3f2 Mon Sep 17 00:00:00 2001 From: sakumisu <1203593632@qq.com> Date: Sun, 29 May 2022 15:22:56 +0800 Subject: [PATCH] remove duplicate es32 drivers --- .../Drivers/ALD/ES32F36xx/Include/ald_acmp.h | 317 + .../Drivers/ALD/ES32F36xx/Include/ald_adc.h | 579 ++ .../Drivers/ALD/ES32F36xx/Include/ald_bkpc.h | 212 + .../Drivers/ALD/ES32F36xx/Include/ald_calc.h | 68 + .../Drivers/ALD/ES32F36xx/Include/ald_can.h | 492 + .../Drivers/ALD/ES32F36xx/Include/ald_cmu.h | 805 ++ .../Drivers/ALD/ES32F36xx/Include/ald_crc.h | 212 + .../Drivers/ALD/ES32F36xx/Include/ald_crypt.h | 341 + .../Drivers/ALD/ES32F36xx/Include/ald_dac.h | 321 + .../Drivers/ALD/ES32F36xx/Include/ald_dbgc.h | 172 + .../Drivers/ALD/ES32F36xx/Include/ald_dma.h | 446 + .../Drivers/ALD/ES32F36xx/Include/ald_ebi.h | 602 ++ .../Drivers/ALD/ES32F36xx/Include/ald_flash.h | 146 + .../Drivers/ALD/ES32F36xx/Include/ald_gpio.h | 339 + .../Drivers/ALD/ES32F36xx/Include/ald_i2c.h | 470 + .../Drivers/ALD/ES32F36xx/Include/ald_i2s.h | 391 + .../Drivers/ALD/ES32F36xx/Include/ald_iap.h | 104 + .../Drivers/ALD/ES32F36xx/Include/ald_nand.h | 222 + .../ALD/ES32F36xx/Include/ald_nor_lcd.h | 236 + .../Drivers/ALD/ES32F36xx/Include/ald_pis.h | 727 ++ .../Drivers/ALD/ES32F36xx/Include/ald_pmu.h | 309 + .../Drivers/ALD/ES32F36xx/Include/ald_qspi.h | 557 + .../Drivers/ALD/ES32F36xx/Include/ald_rmu.h | 314 + .../Drivers/ALD/ES32F36xx/Include/ald_rtc.h | 685 ++ .../Drivers/ALD/ES32F36xx/Include/ald_rtchw.h | 160 + .../Drivers/ALD/ES32F36xx/Include/ald_spi.h | 450 + .../Drivers/ALD/ES32F36xx/Include/ald_sram.h | 142 + .../ALD/ES32F36xx/Include/ald_syscfg.h | 93 + .../Drivers/ALD/ES32F36xx/Include/ald_timer.h | 1230 +++ .../Drivers/ALD/ES32F36xx/Include/ald_trng.h | 217 + .../ALD/ES32F36xx/Include/ald_tsense.h | 215 + .../Drivers/ALD/ES32F36xx/Include/ald_uart.h | 551 + .../Drivers/ALD/ES32F36xx/Include/ald_usb.h | 618 ++ .../Drivers/ALD/ES32F36xx/Include/ald_wdt.h | 132 + .../es32/Drivers/ALD/ES32F36xx/Include/type.h | 138 + .../Drivers/ALD/ES32F36xx/Include/utils.h | 208 + .../Drivers/ALD/ES32F36xx/ReleaseNote.html | 50 + .../es32/Drivers/ALD/ES32F36xx/ReleaseNote.md | 39 + demo/es32/Drivers/ALD/ES32F36xx/SConscript | 34 + .../Drivers/ALD/ES32F36xx/Source/ald_acmp.c | 336 + .../Drivers/ALD/ES32F36xx/Source/ald_adc.c | 1217 +++ .../Drivers/ALD/ES32F36xx/Source/ald_bkpc.c | 185 + .../Drivers/ALD/ES32F36xx/Source/ald_calc.c | 81 + .../Drivers/ALD/ES32F36xx/Source/ald_can.c | 1121 ++ .../Drivers/ALD/ES32F36xx/Source/ald_cmu.c | 1180 +++ .../Drivers/ALD/ES32F36xx/Source/ald_crc.c | 535 + .../Drivers/ALD/ES32F36xx/Source/ald_crypt.c | 1165 +++ .../Drivers/ALD/ES32F36xx/Source/ald_dac.c | 349 + .../Drivers/ALD/ES32F36xx/Source/ald_dma.c | 1032 ++ .../Drivers/ALD/ES32F36xx/Source/ald_ebi.c | 693 ++ .../Drivers/ALD/ES32F36xx/Source/ald_flash.c | 243 + .../ALD/ES32F36xx/Source/ald_flash_ext.c | 343 + .../Drivers/ALD/ES32F36xx/Source/ald_gpio.c | 644 ++ .../Drivers/ALD/ES32F36xx/Source/ald_i2c.c | 2769 +++++ .../Drivers/ALD/ES32F36xx/Source/ald_i2s.c | 1077 ++ .../Drivers/ALD/ES32F36xx/Source/ald_iap.c | 259 + .../Drivers/ALD/ES32F36xx/Source/ald_nand.c | 1272 +++ .../ALD/ES32F36xx/Source/ald_nor_lcd.c | 610 ++ .../Drivers/ALD/ES32F36xx/Source/ald_pis.c | 323 + .../Drivers/ALD/ES32F36xx/Source/ald_pmu.c | 356 + .../Drivers/ALD/ES32F36xx/Source/ald_qspi.c | 1116 ++ .../Drivers/ALD/ES32F36xx/Source/ald_rmu.c | 161 + .../Drivers/ALD/ES32F36xx/Source/ald_rtc.c | 1206 +++ .../Drivers/ALD/ES32F36xx/Source/ald_rtchw.c | 224 + .../Drivers/ALD/ES32F36xx/Source/ald_spi.c | 2022 ++++ .../Drivers/ALD/ES32F36xx/Source/ald_sram.c | 397 + .../Drivers/ALD/ES32F36xx/Source/ald_timer.c | 3705 +++++++ .../Drivers/ALD/ES32F36xx/Source/ald_trng.c | 323 + .../Drivers/ALD/ES32F36xx/Source/ald_tsense.c | 271 + .../Drivers/ALD/ES32F36xx/Source/ald_uart.c | 1543 +++ .../Drivers/ALD/ES32F36xx/Source/ald_usb.c | 1402 +++ .../Drivers/ALD/ES32F36xx/Source/ald_wdt.c | 238 + .../es32/Drivers/ALD/ES32F36xx/Source/utils.c | 715 ++ .../EastSoft/ES32F36xx/Include/es32f36xx.h | 9167 +++++++++++++++++ .../EastSoft/ES32F36xx/ReleaseNote.html | 14 + .../Device/EastSoft/ES32F36xx/ReleaseNote.md | 6 + .../Device/EastSoft/ES32F36xx/SConscript | 22 + .../ES32F36xx/Startup/gcc/startup_es32f36xx.s | 502 + .../ES32F36xx/Startup/iar/startup_es32f36xx.s | 571 + .../Startup/keil/startup_es32f36xx.s | 689 ++ .../ES32F36xx/System/system_es32f36xx.c | 44 + .../Drivers/CMSIS/Include/arm_common_tables.h | 121 + .../Drivers/CMSIS/Include/arm_const_structs.h | 66 + demo/es32/Drivers/CMSIS/Include/arm_math.h | 7157 +++++++++++++ demo/es32/Drivers/CMSIS/Include/cmsis_armcc.h | 870 ++ .../Drivers/CMSIS/Include/cmsis_armclang.h | 1877 ++++ .../Drivers/CMSIS/Include/cmsis_compiler.h | 266 + demo/es32/Drivers/CMSIS/Include/cmsis_gcc.h | 2088 ++++ .../es32/Drivers/CMSIS/Include/cmsis_iccarm.h | 913 ++ .../Drivers/CMSIS/Include/cmsis_version.h | 39 + .../Drivers/CMSIS/Include/core_armv8mbl.h | 1896 ++++ .../Drivers/CMSIS/Include/core_armv8mml.h | 2960 ++++++ demo/es32/Drivers/CMSIS/Include/core_cm0.h | 888 ++ .../es32/Drivers/CMSIS/Include/core_cm0plus.h | 1023 ++ demo/es32/Drivers/CMSIS/Include/core_cm23.h | 1899 ++++ demo/es32/Drivers/CMSIS/Include/core_cm3.h | 1933 ++++ demo/es32/Drivers/CMSIS/Include/core_cm33.h | 2963 ++++++ demo/es32/Drivers/CMSIS/Include/core_cm4.h | 2118 ++++ demo/es32/Drivers/CMSIS/Include/core_cm7.h | 2660 +++++ demo/es32/Drivers/CMSIS/Include/core_sc000.h | 1016 ++ demo/es32/Drivers/CMSIS/Include/core_sc300.h | 1903 ++++ demo/es32/Drivers/CMSIS/Include/mpu_armv7.h | 197 + demo/es32/Drivers/CMSIS/Include/mpu_armv8.h | 333 + demo/es32/Drivers/CMSIS/Include/tz_context.h | 70 + .../ES32F369x/MDK-ARM/example.uvoptx | 38 +- .../ES32F369x/MDK-ARM/example.uvprojx | 56 +- .../copy Drivers from es32 sdk here.txt | 0 .../usb_host/ES32F369x/MDK-ARM/example.uvoptx | 93 +- .../ES32F369x/MDK-ARM/example.uvprojx | 65 +- .../copy Drivers from es32 sdk here.txt | 0 110 files changed, 88834 insertions(+), 146 deletions(-) create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_acmp.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_adc.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_bkpc.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_calc.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_can.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_cmu.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_crc.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_crypt.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_dac.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_dbgc.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_dma.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_ebi.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_flash.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_gpio.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_i2c.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_i2s.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_iap.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_nand.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_nor_lcd.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_pis.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_pmu.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_qspi.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_rmu.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_rtc.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_rtchw.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_spi.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_sram.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_syscfg.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_timer.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_trng.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_tsense.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_uart.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_usb.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/ald_wdt.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/type.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Include/utils.h create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/ReleaseNote.html create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/ReleaseNote.md create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/SConscript create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_acmp.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_adc.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_bkpc.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_calc.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_can.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_cmu.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_crc.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_crypt.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_dac.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_dma.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_ebi.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_flash.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_flash_ext.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_gpio.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_i2c.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_i2s.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_iap.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_nand.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_nor_lcd.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_pis.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_pmu.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_qspi.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_rmu.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_rtc.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_rtchw.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_spi.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_sram.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_timer.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_trng.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_tsense.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_uart.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_usb.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/ald_wdt.c create mode 100644 demo/es32/Drivers/ALD/ES32F36xx/Source/utils.c create mode 100644 demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h create mode 100644 demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/ReleaseNote.html create mode 100644 demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/ReleaseNote.md create mode 100644 demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/SConscript create mode 100644 demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.s create mode 100644 demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/Startup/iar/startup_es32f36xx.s create mode 100644 demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s create mode 100644 demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/System/system_es32f36xx.c create mode 100644 demo/es32/Drivers/CMSIS/Include/arm_common_tables.h create mode 100644 demo/es32/Drivers/CMSIS/Include/arm_const_structs.h create mode 100644 demo/es32/Drivers/CMSIS/Include/arm_math.h create mode 100644 demo/es32/Drivers/CMSIS/Include/cmsis_armcc.h create mode 100644 demo/es32/Drivers/CMSIS/Include/cmsis_armclang.h create mode 100644 demo/es32/Drivers/CMSIS/Include/cmsis_compiler.h create mode 100644 demo/es32/Drivers/CMSIS/Include/cmsis_gcc.h create mode 100644 demo/es32/Drivers/CMSIS/Include/cmsis_iccarm.h create mode 100644 demo/es32/Drivers/CMSIS/Include/cmsis_version.h create mode 100644 demo/es32/Drivers/CMSIS/Include/core_armv8mbl.h create mode 100644 demo/es32/Drivers/CMSIS/Include/core_armv8mml.h create mode 100644 demo/es32/Drivers/CMSIS/Include/core_cm0.h create mode 100644 demo/es32/Drivers/CMSIS/Include/core_cm0plus.h create mode 100644 demo/es32/Drivers/CMSIS/Include/core_cm23.h create mode 100644 demo/es32/Drivers/CMSIS/Include/core_cm3.h create mode 100644 demo/es32/Drivers/CMSIS/Include/core_cm33.h create mode 100644 demo/es32/Drivers/CMSIS/Include/core_cm4.h create mode 100644 demo/es32/Drivers/CMSIS/Include/core_cm7.h create mode 100644 demo/es32/Drivers/CMSIS/Include/core_sc000.h create mode 100644 demo/es32/Drivers/CMSIS/Include/core_sc300.h create mode 100644 demo/es32/Drivers/CMSIS/Include/mpu_armv7.h create mode 100644 demo/es32/Drivers/CMSIS/Include/mpu_armv8.h create mode 100644 demo/es32/Drivers/CMSIS/Include/tz_context.h delete mode 100644 demo/es32/usb_device/ES32F369x/copy Drivers from es32 sdk here.txt delete mode 100644 demo/es32/usb_host/ES32F369x/copy Drivers from es32 sdk here.txt diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_acmp.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_acmp.h new file mode 100644 index 00000000..ad22ba6b --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_acmp.h @@ -0,0 +1,317 @@ +/** + ********************************************************************************* + * + * @file ald_acmp.h + * @brief Header file of ACMP module driver. + * + * @version V1.0 + * @date 26 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 26 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_ACMP_H__ +#define __ALD_ACMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup ACMP + * @{ + */ + +/** @defgroup ACMP_Public_Types ACMP Public Types + * @{ + */ + +/** + * @brief ACMP interrupt + */ +typedef enum { + ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */ + ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */ +} acmp_it_t; + +/** + * @brief ACMP interrupt flag + */ +typedef enum { + ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */ + ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */ +} acmp_flag_t; + +/** + * @brief ACMP status flag + */ +typedef enum { + ACMP_STATUS_ACT = (1U << 0), /**< Edge status flag */ + ACMP_STATUS_OUT = (1U << 1), /**< Warm up status flag */ +} acmp_status_t; + +/** + * @brief ACMP positive input + */ +typedef enum { + ACMP_POS_CH0 = 0x0U, /**< Channel 0 as positive input */ + ACMP_POS_CH1 = 0x1U, /**< Channel 1 as positive input */ + ACMP_POS_CH2 = 0x2U, /**< Channel 2 as positive input */ + ACMP_POS_CH3 = 0x3U, /**< Channel 3 as positive input */ + ACMP_POS_CH4 = 0x4U, /**< Channel 4 as positive input */ + ACMP_POS_CH5 = 0x5U, /**< Channel 5 as positive input */ + ACMP_POS_CH6 = 0x6U, /**< Channel 6 as positive input */ + ACMP_POS_CH7 = 0x7U, /**< Channel 7 as positive input */ +} acmp_pos_input_t; + +/** + * @brief ACMP negative input + */ +typedef enum { + ACMP_NEG_CH0 = 0x0U, /**< Channel 0 as negative input */ + ACMP_NEG_CH1 = 0x1U, /**< Channel 1 as negative input */ + ACMP_NEG_CH2 = 0x2U, /**< Channel 2 as negative input */ + ACMP_NEG_CH3 = 0x3U, /**< Channel 3 as negative input */ + ACMP_NEG_CH4 = 0x4U, /**< Channel 4 as negative input */ + ACMP_NEG_CH5 = 0x5U, /**< Channel 5 as negative input */ + ACMP_NEG_CH6 = 0x6U, /**< Channel 6 as negative input */ + ACMP_NEG_CH7 = 0x7U, /**< Channel 7 as negative input */ + ACMP_NEG_1V25 = 0x8U, /**< 1.25v as negative input */ + ACMP_NEG_2V5 = 0x9U, /**< 2.5v as negative input */ + ACMP_NEG_VDD = 0xAU, /**< VDD as negative input */ +} acmp_neg_input_t; + +/** + * @brief ACMP mode + */ +typedef enum { + ACMP_ULTRA_LOW_POWER = 0x0U, /**< Ultra low power mode */ + ACMP_LOW_POWER = 0x1U, /**< Low power mode */ + ACMP_MIDDLE_POWER = 0x2U, /**< Middle power mode */ + ACMP_HIGH_POWER = 0x3U, /**< High power mode */ +} acmp_mode_t; + +/** + * @brief ACMP warm-up time + */ +typedef enum { + ACMP_4_PCLK = 0x0U, /**< 4 hfperclk cycles */ + ACMP_8_PCLK = 0x1U, /**< 4 hfperclk cycles */ + ACMP_16_PCLK = 0x2U, /**< 4 hfperclk cycles */ + ACMP_32_PCLK = 0x3U, /**< 4 hfperclk cycles */ + ACMP_64_PCLK = 0x4U, /**< 4 hfperclk cycles */ + ACMP_128_PCLK = 0x5U, /**< 4 hfperclk cycles */ + ACMP_256_PCLK = 0x6U, /**< 4 hfperclk cycles */ + ACMP_512_PCLK = 0x7U, /**< 4 hfperclk cycles */ +} acmp_warm_time_t; + +/** + * @brief ACMP hysteresis level + */ +typedef enum { + ACMP_HYST_0 = 0x0U, /**< No hysteresis */ + ACMP_HYST_15 = 0x1U, /**< 15mV hysteresis */ + ACMP_HYST_22 = 0x2U, /**< 22mV hysteresis */ + ACMP_HYST_29 = 0x3U, /**< 29mV hysteresis */ + ACMP_HYST_36 = 0x4U, /**< 36mV hysteresis */ + ACMP_HYST_43 = 0x5U, /**< 43mV hysteresis */ + ACMP_HYST_50 = 0x6U, /**< 50mV hysteresis */ + ACMP_HYST_57 = 0x7U, /**< 57mV hysteresis */ +} acmp_hystsel_t; + +/** + * @brief ACMP inactive state + */ +typedef enum { + ACMP_INACTVAL_LOW = 0x0U, /**< The inactive value is 0 */ + ACMP_INACTVAL_HIGH = 0x1U, /**< The inactive value is 1 */ +} acmp_inactval_t; + +/** + * @brief which edges set up interrupt + */ +typedef enum { + ACMP_EDGE_NONE = 0x0U, /**< Disable EDGE interrupt */ + ACMP_EDGE_FALL = 0x1U, /**< Falling edges set EDGE interrupt */ + ACMP_EDGE_RISE = 0x2U, /**< rise edges set EDGE interrupt */ + ACMP_EDGE_ALL = 0x3U, /**< Falling edges and rise edges set EDGE interrupt */ +} acmp_edge_t; + +/** + * @brief ACMP output function + */ +typedef enum { + ACMP_OUT_DISABLE = 0x0U, /**< Disable acmp output */ + ACMP_OUT_ENABLE = 0x1U, /**< Enable acmp output */ +} acmp_out_func_t; + +/** + * @brief ACMP init structure definition + */ +typedef struct { + acmp_mode_t mode; /**< ACMP operation mode */ + acmp_warm_time_t warm_time; /**< ACMP warm up time */ + acmp_hystsel_t hystsel; /**< ACMP hysteresis level */ + acmp_pos_input_t p_port; /**< ACMP positive port select */ + acmp_neg_input_t n_port; /**< ACMP negative port select */ + acmp_inactval_t inactval; /**< ACMP inavtive output value */ + type_func_t out_inv; /**< ACMP output inverse */ + acmp_edge_t edge; /**< Select edges to set interrupt flag */ + uint8_t vdd_level; /**< Select scaling factor for CDD reference level, MAX is 63 */ +} acmp_init_t; + +/** + * @brief ACMP Handle Structure definition + */ +typedef struct acmp_handle_s { + ACMP_TypeDef *perh; /**< Register base address */ + acmp_init_t init; /**< ACMP required parameters */ + lock_state_t lock; /**< Locking object */ + + void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< ACMP warm-up complete callback */ + void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< ACMP edge trigger callback */ +} acmp_handle_t; +/** + * @} + */ + +/** @defgroup ACMP_Public_Macros ACMP Public Macros + * @{ + */ +#define ACMP_ENABLE(handle) (SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK)) +#define ACMP_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK)) +/** + * @} + */ + +/** @defgroup ACMP_Private_Macros ACMP Private Macros + * @{ + */ +#define IS_ACMP_TYPE(x) (((x) == ACMP0) || \ + ((x) == ACMP1) || \ + ((x) == ACMP2)) +#define IS_ACMP_MODE_TYPE(x) (((x) == ACMP_ULTRA_LOW_POWER) || \ + ((x) == ACMP_LOW_POWER) || \ + ((x) == ACMP_MIDDLE_POWER) || \ + ((x) == ACMP_HIGH_POWER)) +#define IS_ACMP_IT_TYPE(x) (((x) == ACMP_IT_EDGE) || \ + ((x) == ACMP_IT_WARMUP)) +#define IS_ACMP_FLAG_TYPE(x) (((x) == ACMP_FLAG_EDGE) || \ + ((x) == ACMP_FLAG_WARMUP)) +#define IS_ACMP_STATUS_TYPE(x) (((x) == ACMP_STATUS_ACT) || \ + ((x) == ACMP_STATUS_OUT)) +#define IS_ACMP_POS_INPUT_TYPE(x) (((x) == ACMP_POS_CH0) || \ + ((x) == ACMP_POS_CH1) || \ + ((x) == ACMP_POS_CH2) || \ + ((x) == ACMP_POS_CH3) || \ + ((x) == ACMP_POS_CH4) || \ + ((x) == ACMP_POS_CH5) || \ + ((x) == ACMP_POS_CH6) || \ + ((x) == ACMP_POS_CH7)) +#define IS_ACMP_NEG_INPUT_TYPE(x) (((x) == ACMP_NEG_CH0) || \ + ((x) == ACMP_NEG_CH1) || \ + ((x) == ACMP_NEG_CH2) || \ + ((x) == ACMP_NEG_CH3) || \ + ((x) == ACMP_NEG_CH4) || \ + ((x) == ACMP_NEG_CH5) || \ + ((x) == ACMP_NEG_CH6) || \ + ((x) == ACMP_NEG_CH7) || \ + ((x) == ACMP_NEG_1V25) || \ + ((x) == ACMP_NEG_2V5) || \ + ((x) == ACMP_NEG_VDD)) +#define IS_ACMP_WARM_UP_TIME_TYPE(x) (((x) == ACMP_4_PCLK) || \ + ((x) == ACMP_8_PCLK) || \ + ((x) == ACMP_16_PCLK) || \ + ((x) == ACMP_32_PCLK) || \ + ((x) == ACMP_64_PCLK) || \ + ((x) == ACMP_128_PCLK) || \ + ((x) == ACMP_256_PCLK) || \ + ((x) == ACMP_512_PCLK)) +#define IS_ACMP_HYSTSEL_TYPE(x) (((x) == ACMP_HYST_0) || \ + ((x) == ACMP_HYST_15) || \ + ((x) == ACMP_HYST_22) || \ + ((x) == ACMP_HYST_29) || \ + ((x) == ACMP_HYST_36) || \ + ((x) == ACMP_HYST_43) || \ + ((x) == ACMP_HYST_50) || \ + ((x) == ACMP_HYST_57)) +#define IS_ACMP_INACTVAL_TYPE(x) (((x) == ACMP_INACTVAL_LOW) || \ + ((x) == ACMP_INACTVAL_HIGH)) +#define IS_ACMP_EDGE_TYPE(x) (((x) == ACMP_EDGE_NONE) || \ + ((x) == ACMP_EDGE_FALL) || \ + ((x) == ACMP_EDGE_RISE) || \ + ((x) == ACMP_EDGE_ALL)) +/** + * @} + */ + +/** @addtogroup ACMP_Public_Functions + * @{ + */ + +/** @addtogroup ACMP_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_acmp_init(acmp_handle_t *hperh); +/** + * @} + */ +/** @addtogroup ACMP_Public_Functions_Group2 + * @{ + */ +void ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state); +it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it); +flag_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag); +flag_status_t ald_acmp_get_mask_flag_status(acmp_handle_t *hperh, acmp_flag_t flag); +void ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag); +/** + * @} + */ +/** @addtogroup ACMP_Public_Functions_Group3 + * @{ + */ +void ald_acmp_irq_handler(acmp_handle_t *hperh); +void ald_acmp_out_config(acmp_handle_t *hperh, type_func_t state); +uint8_t ald_acmp_out_result(acmp_handle_t *hperh); +flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +extern "C" } +#endif +#endif diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_adc.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_adc.h new file mode 100644 index 00000000..e95d7ba3 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_adc.h @@ -0,0 +1,579 @@ +/** + ****************************************************************************** + * @file ald_adc.h + * @brief Header file of ADC Module library. + * + * @version V1.0 + * @date 28 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 28 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_ADC_H__ +#define __ALD_ADC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" +#include "ald_pis.h" +#include "ald_timer.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Pubulic_Types ADC Pubulic Types + * @{ + */ + +/** + * @brief ADC State structures definition + */ +typedef enum { + ADC_STATE_RESET = 0x0U, /**< ADC not yet initialized or disabled */ + ADC_STATE_READY = 0x1U, /**< ADC peripheral ready for use */ + ADC_STATE_BUSY = 0x2U, /**< ADC is busy to internal process */ + ADC_STATE_TIMEOUT = 0x4U, /**< TimeOut occurrence */ + ADC_STATE_ERROR = 0x8U, /**< Internal error occurrence */ + ADC_STATE_BUSY_N = 0x10U, /**< Normal channel busy */ + ADC_STATE_BUSY_I = 0x20U, /**< Insert channel busy */ + ADC_STATE_BUSY_WDG = 0x40U, /**< Insert channel busy */ +} adc_state_t; + +/** + *@brief ADC Error Code + */ +typedef enum { + ADC_ERROR_NONE = 0x0U, /**< No error */ + ADC_ERROR_INTERNAL = 0x1U, /**< ADC IP internal error*/ + ADC_ERROR_OVR = 0x2U, /**< Overrun error */ + ADC_ERROR_DMA = 0x4U, /**< DMA transfer error */ +} adc_error_t; + +/** + *@brief ADC data alignment + */ +typedef enum { + ADC_DATAALIGN_RIGHT = 0x0U, /**< ADC data alignment right */ + ADC_DATAALIGN_LEFT = 0x1U, /**< ADC data alignment left */ +} adc_align_t; + +/** + *@brief ADC config hannal trigger the EOC IT mode + */ +typedef enum { + ADC_NCHESEL_MODE_ALL = 0x0U, /**< ADC set RCHE after convert sequence finish */ + ADC_NCHESEL_MODE_ONE = 0x1U, /**< ADC set RCHE after one convert finish */ +} adc_nchesel_t; + +/** + *@brief ADC channels + */ +typedef enum { + ADC_CHANNEL_0 = 0x0U, /**< ADC channel 0 */ + ADC_CHANNEL_1 = 0x1U, /**< ADC channel 1 */ + ADC_CHANNEL_2 = 0x2U, /**< ADC channel 2 */ + ADC_CHANNEL_3 = 0x3U, /**< ADC channel 3 */ + ADC_CHANNEL_4 = 0x4U, /**< ADC channel 4 */ + ADC_CHANNEL_5 = 0x5U, /**< ADC channel 5 */ + ADC_CHANNEL_6 = 0x6U, /**< ADC channel 6 */ + ADC_CHANNEL_7 = 0x7U, /**< ADC channel 7 */ + ADC_CHANNEL_8 = 0x8U, /**< ADC channel 8 */ + ADC_CHANNEL_9 = 0x9U, /**< ADC channel 9 */ + ADC_CHANNEL_10 = 0xAU, /**< ADC channel 10 */ + ADC_CHANNEL_11 = 0xBU, /**< ADC channel 11 */ + ADC_CHANNEL_12 = 0xCU, /**< ADC channel 12 */ + ADC_CHANNEL_13 = 0xDU, /**< ADC channel 13 */ + ADC_CHANNEL_14 = 0xEU, /**< ADC channel 14 */ + ADC_CHANNEL_15 = 0xFU, /**< ADC channel 15 */ + ADC_CHANNEL_16 = 0x10U, /**< ADC channel 16 */ + ADC_CHANNEL_17 = 0x11U, /**< ADC channel 17 */ + ADC_CHANNEL_18 = 0x12U, /**< ADC channel 18 */ +} adc_channel_t; + +/** + *@brief ADC sampling times + */ +typedef enum { + ADC_SAMPLETIME_1 = 0x0U, /**< ADC sampling times 1 clk */ + ADC_SAMPLETIME_2 = 0x1U, /**< ADC sampling times 2 clk */ + ADC_SAMPLETIME_4 = 0x2U, /**< ADC sampling times 4 clk */ + ADC_SAMPLETIME_15 = 0x3U, /**< ADC sampling times 15 clk */ +} adc_samp_t; + +/** + *@brief ADC index channel in normal group + */ +typedef enum { + ADC_NCH_IDX_1 = 0x1U, /**< ADC normal channel index 1 */ + ADC_NCH_IDX_2 = 0x2U, /**< ADC normal channel index 2 */ + ADC_NCH_IDX_3 = 0x3U, /**< ADC normal channel index 3 */ + ADC_NCH_IDX_4 = 0x4U, /**< ADC normal channel index 4 */ + ADC_NCH_IDX_5 = 0x5U, /**< ADC normal channel index 5 */ + ADC_NCH_IDX_6 = 0x6U, /**< ADC normal channel index 6 */ + ADC_NCH_IDX_7 = 0x7U, /**< ADC normal channel index 7 */ + ADC_NCH_IDX_8 = 0x8U, /**< ADC normal channel index 8 */ + ADC_NCH_IDX_9 = 0x9U, /**< ADC normal channel index 9 */ + ADC_NCH_IDX_10 = 0xAU, /**< ADC normal channel index 10 */ + ADC_NCH_IDX_11 = 0xBU, /**< ADC normal channel index 11 */ + ADC_NCH_IDX_12 = 0xCU, /**< ADC normal channel index 12 */ + ADC_NCH_IDX_13 = 0xDU, /**< ADC normal channel index 13 */ + ADC_NCH_IDX_14 = 0xEU, /**< ADC normal channel index 14 */ + ADC_NCH_IDX_15 = 0xFU, /**< ADC normal channel index 15 */ + ADC_NCH_IDX_16 = 0x10U, /**< ADC normal channel index 16 */ +} adc_nch_idx_t; + +/** + * @brief ADC index channel in insert group + */ +typedef enum { + ADC_ICH_IDX_1 = 0x1U, /**< ADC insert channel index 1 */ + ADC_ICH_IDX_2 = 0x2U, /**< ADC insert channel index 2 */ + ADC_ICH_IDX_3 = 0x3U, /**< ADC insert channel index 3 */ + ADC_ICH_IDX_4 = 0x4U, /**< ADC insert channel index 4 */ +} adc_ich_idx_t; + +/** + * @brief ADC analog watchdog mode + */ +typedef enum { + ADC_ANAWTD_NONE = 0x0U, /**< No watch dog */ + ADC_ANAWTD_SING_NM = 0x800200U, /**< One normal channel watch dog */ + ADC_ANAWTD_SING_IST = 0x400200U, /**< One insert channel Injec watch dog */ + ADC_ANAWTD_SING_NMIST = 0xC00200U, /**< One normal and insert channel watch dog */ + ADC_ANAWTD_ALL_NM = 0x800000U, /**< All normal channel watch dog */ + ADC_ANAWTD_ALL_IST = 0x400000U, /**< All insert channel watch dog */ + ADC_ANAWTD_ALL_NMIST = 0xC00000U, /**< All normal and insert channel watch dog */ +} adc_ana_wdg_t; + +/** + * @brief ADC Event type + */ +typedef enum { + ADC_AWD_EVENT = (1U << 0), /**< ADC analog watch dog event */ +} adc_event_type_t; + +/** + * @brief ADC interrupts definition + */ +typedef enum { + ADC_IT_NCH = (1U << 5), /**< ADC it normal */ + ADC_IT_AWD = (1U << 6), /**< ADC it awd */ + ADC_IT_ICH = (1U << 7), /**< ADC it insert */ + ADC_IT_OVR = (1U << 26), /**< ADC it overring */ +} adc_it_t; + +/** + * @brief ADC flags definition + */ +typedef enum { + ADC_FLAG_AWD = (1U << 0), /**perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK)) +#define ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK)) +#define ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK)) +#define ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET) +#define ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK)) +#define ADC_NETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, (mode) << ADC_CON1_NETS_POSS)) +#define ADC_IETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, (mode) << ADC_CON1_IETS_POSS)) +#define ADC_NETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, 0 << ADC_CON1_NETS_POSS)) +#define ADC_IETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, 0 << ADC_CON1_IETS_POSS)) +#define ADC_SPEED_HIGH_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK)) +#define ADC_SPEED_HIGH_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK)) +#define ADC_CALIBRATE_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK)) +#define ADC_CALIBRATE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK)) +/** + * @} + */ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +#define IS_ADC_ICH_IDX_TYPE(x) ((x) <= ADC_ICH_IDX_4) +#define IS_ADC_NCH_IDX_TYPE(x) ((x) <= ADC_NCH_IDX_16) +#define IS_ADC_SAMPLING_TIMES_TYPE(x) (((x) == ADC_SAMPLETIME_1) || \ + ((x) == ADC_SAMPLETIME_2) || \ + ((x) == ADC_SAMPLETIME_4) || \ + ((x) == ADC_SAMPLETIME_15)) +#define IS_ADC_CHANNELS_TYPE(x) ((x) <= ADC_CHANNEL_18) +#define IS_ADC_DATA_ALIGN_TYPE(x) (((x) == ADC_DATAALIGN_RIGHT) || \ + ((x) == ADC_DATAALIGN_LEFT)) +#define IS_ADC_ANALOG_WTD_MODE_TYPE(x) (((x) == ADC_ANAWTD_NONE) || \ + ((x) == ADC_ANAWTD_SING_NM) || \ + ((x) == ADC_ANAWTD_SING_IST) || \ + ((x) == ADC_ANAWTD_SING_NMIST) || \ + ((x) == ADC_ANAWTD_ALL_NM) || \ + ((x) == ADC_ANAWTD_ALL_IST) || \ + ((x) == ADC_ANAWTD_ALL_NMIST)) +#define IS_ADC_IT_TYPE(x) (((x) == ADC_IT_NCH) || \ + ((x) == ADC_IT_AWD) || \ + ((x) == ADC_IT_ICH) || \ + ((x) == ADC_IT_OVR )) +#define IS_ADC_FLAGS_TYPE(x) (((x) == ADC_FLAG_AWD) || \ + ((x) == ADC_FLAG_NCH) || \ + ((x) == ADC_FLAG_ICH) || \ + ((x) == ADC_FLAG_OVR) || \ + ((x) == ADC_FLAG_NCHS) || \ + ((x) == ADC_FLAG_ICHS)) +#define IS_ADC_CLK_DIV_TYPE(x) (((x) == ADC_CKDIV_1) || \ + ((x) == ADC_CKDIV_2) || \ + ((x) == ADC_CKDIV_4) || \ + ((x) == ADC_CKDIV_8) || \ + ((x) == ADC_CKDIV_16) || \ + ((x) == ADC_CKDIV_32) || \ + ((x) == ADC_CKDIV_64) || \ + ((x) == ADC_CKDIV_128)) +#define IS_ADC_NEG_REF_VOLTAGE_TYPE(x) (((x) == ADC_NEG_REF_VSS ) || \ + ((x) == ADC_NEG_REF_VREFN )) +#define IS_POS_REF_VOLTAGE_TYPE(x) (((x) == ADC_POS_REF_VDD) || \ + ((x) == ADC_POS_REF_2V) || \ + ((x) == ADC_POS_REF_VREEFP) || \ + ((x) == ADC_POS_REF_VREEFP_BUF)) +#define IS_ADC_NCH_NR_TYPE(x) ((x) <= ADC_NCH_NR_16) +#define IS_ADC_ICH_NR_TYPE(x) ((x) <= ADC_ICH_NR_4) +#define IS_ADC_DISC_NR_TYPE(x) ((x) <= ADC_DISC_NR_8) +#define IS_ADC_CONV_BIT_TYPE(x) (((x) == ADC_CONV_BIT_12) || \ + ((x) == ADC_CONV_BIT_6) || \ + ((x) == ADC_CONV_BIT_8) || \ + ((x) == ADC_CONV_BIT_10)) +#define IS_ADC_TYPE(x) (((x) == ADC0) || \ + ((x) == ADC1)) +#define IS_ADC_NCHESEL_MODE_TYPE(x) (((x) == ADC_NCHESEL_MODE_ALL) || \ + ((x) == ADC_NCHESEL_MODE_ONE)) +#define IS_ADC_EVENT_TYPE(x) ((x) == ADC_AWD_EVENT) +#define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xfff) +#define IS_HTR_TYPE(x) ((x) <= 0xfff) +#define IS_LTR_TYPE(x) ((x) <= 0xfff) +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions + * @{ + */ + +/** @addtogroup ADC_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_adc_init(adc_handle_t *hperh); +ald_status_t ald_adc_reset(adc_handle_t *hperh); +void ald_adc_offset_adjust(uint32_t refmv); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_adc_normal_start(adc_handle_t *hperh); +ald_status_t ald_adc_normal_stop(adc_handle_t *hperh); +ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); +ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout); +ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh); +ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh); +#ifdef ALD_DMA +ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel); +ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config); +ald_status_t ald_adc_timer_trigger_insert(adc_timer_config_t *config); +#endif +uint32_t ald_adc_normal_get_value(adc_handle_t *hperh); +ald_status_t ald_adc_insert_start(adc_handle_t *hperh); +ald_status_t ald_adc_insert_stop(adc_handle_t *hperh); +ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout); +ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh); +ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh); +uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t ih_rank); +void ald_adc_irq_handler(adc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group3 + * @{ + */ +ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config); +ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config); +ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config); +void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state); +it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it); +flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag); +void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag); +/** + * @} + */ + +/** @addtogroup ADC_Public_Functions_Group4 + * @{ + */ +uint32_t ald_adc_get_state(adc_handle_t *hperh); +uint32_t ald_adc_get_error(adc_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus + extern "C" } +#endif + +#endif /* __ALD_ADC_H */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_bkpc.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_bkpc.h new file mode 100644 index 00000000..b33ab04f --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_bkpc.h @@ -0,0 +1,212 @@ +/** + ********************************************************************************* + * + * @file ald_bkpc.h + * @brief Header file of BKPC module driver. + * + * @version V1.0 + * @date 15 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 15 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_BKPC_H__ +#define __ALD_BKPC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup BKPC + * @{ + */ + +/** @defgroup BKPC_Public_Macros BKPC Public Macros + * @{ + */ +#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0U)) +#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55U)) +#define BKPC_LRC_ENABLE() \ +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ + BKPC_LOCK(); \ +} while (0) +#define BKPC_LRC_DISABLE() \ +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \ + BKPC_LOCK(); \ +} while (0) +#define BKPC_LOSM_ENABLE() \ +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \ + BKPC_LOCK(); \ +} while (0) +#define BKPC_LOSM_DISABLE() \ +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\ + BKPC_LOCK(); \ +} while (0) +#define BKPC_LOSC_ENABLE() \ +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \ + BKPC_LOCK(); \ +} while (0) +#define BKPC_LOSC_DISABLE() \ +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\ + BKPC_LOCK(); \ +} while (0) + + +#define BKPC_MRST_WAKEUP_ENABLE() \ +do { \ + BKPC_UNLOCK(); \ + SET_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK); \ + BKPC_LOCK(); \ +} while (0) +#define BKPC_MRST_WAKEUP_DISABLE() \ +do { \ + BKPC_UNLOCK(); \ + CLEAR_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK); \ + BKPC_LOCK(); \ +} while (0) + +/** + * @} + */ + +/** @defgroup BKPC_Public_Types BKPC Public Types + * @{ + */ +/** + * @brief BKPC preipheral clock select. + */ +typedef enum { + BKPC_PREH_CLK_LOSM = 0x0U, /**< LOSM */ + BKPC_PREH_CLK_LRC = 0x1U, /**< LRC */ + BKPC_PREH_CLK_HRC_1M = 0x2U, /**< HRC down to 1MHz */ + BKPC_PREH_CLK_HOSC_1M = 0x3U, /**< HOSC down to 1MHz */ +} bkpc_preh_clk_t; + +/** + * @brief Standby wakeup port select + */ +typedef enum { + PMU_STANDBY_PORT_SEL_PA0 = 0x0U, /**< Wakeup by PA0 */ + PMU_STANDBY_PORT_SEL_PA1 = 0x1U, /**< Wakeup by PA1 */ + PMU_STANDBY_PORT_SEL_PA2 = 0x2U, /**< Wakeup by PA2 */ + PMU_STANDBY_PORT_SEL_PA3 = 0x3U, /**< Wakeup by PA3 */ + PMU_STANDBY_PORT_SEL_PA4 = 0x4U, /**< Wakeup by PA4 */ + PMU_STANDBY_PORT_SEL_PA5 = 0x5U, /**< Wakeup by PA5 */ + PMU_STANDBY_PORT_SEL_PA6 = 0x6U, /**< Wakeup by PA6 */ + PMU_STANDBY_PORT_SEL_PA7 = 0x7U, /**< Wakeup by PA7 */ + PMU_STANDBY_PORT_SEL_NONE = 0xFU, /**< Wakeup by other source */ +} bkpc_wakeup_port_t; + +/** + * @brief Standby wakeup level + */ +typedef enum { + PMU_STANDBY_LEVEL_HIGH = 0x0U, /**< High level */ + PMU_STANDBY_LEVEL_LOW = 0x1U, /**< Low level */ +} bkpc_wakeup_level_t; + +/** + * @} + */ + +/** + * @defgroup BKPC_Private_Macros BKPC Private Macros + * @{ + */ +#define IS_BKPC_WAKEUP_PORT(x) (((x) == PMU_STANDBY_PORT_SEL_PA0) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA1) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA2) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA3) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA4) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA5) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA6) || \ + ((x) == PMU_STANDBY_PORT_SEL_PA7) || \ + ((x) == PMU_STANDBY_PORT_SEL_NONE)) +#define IS_BKPC_WAKEUP_LEVEL(x) (((x) == PMU_STANDBY_LEVEL_HIGH) || \ + ((x) == PMU_STANDBY_LEVEL_LOW)) +#define IS_BKPC_PREH_CLOCK(x) (((x) == BKPC_PREH_CLK_LOSM) || \ + ((x) == BKPC_PREH_CLK_LRC) || \ + ((x) == BKPC_PREH_CLK_HRC_1M) || \ + ((x) == BKPC_PREH_CLK_HOSC_1M)) +#define IS_BKPC_RAM_IDX(x) ((x) < 32) +/** + * @} + */ + +/** @addtogroup BKPC_Public_Functions + * @{ + */ +/** @addtogroup BKPC_Public_Functions_Group1 + * @{ + */ +/* control functions */ +extern void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level); +extern void ald_bkpc_rtc_clock_config(bkpc_preh_clk_t clock); +extern void ald_bkpc_tsense_clock_config(bkpc_preh_clk_t clock); +/** + * @} + */ +/** @addtogroup BKPC_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +extern void ald_bkpc_write_ram(uint8_t idx, uint32_t value); +extern uint32_t ald_bkpc_read_ram(uint8_t idx); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_BKPC_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_calc.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_calc.h new file mode 100644 index 00000000..75110e47 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_calc.h @@ -0,0 +1,68 @@ +/** + ********************************************************************************* + * + * @file ald_calc.h + * @brief Header file of CALC module driver. + * + * @version V1.0 + * @date 26 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 26 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_CALC_H__ +#define __ALD_CALC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CALC + * @{ + */ + +/** @addtogroup CALC_Public_Functions + * @{ + */ +extern uint32_t ald_calc_sqrt(uint32_t data); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_CALC_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_can.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_can.h new file mode 100644 index 00000000..7fdc1632 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_can.h @@ -0,0 +1,492 @@ +/** + ****************************************************************************** + * @file ald_can.h + * @brief Header file of CAN Module driver. + * + * @version V1.0 + * @date 16 Apr 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 16 Apr 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_CAN_H +#define __ALD_CAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/** @defgroup CAN_Public_Types CAN Public Types + * @{ + */ +/** + * @brief ALD State structures definition + */ +typedef enum { + CAN_STATE_RESET = 0x00U, /**< CAN not yet initialized or disabled */ + CAN_STATE_READY = 0x01U, /**< CAN initialized and ready for use */ + CAN_STATE_BUSY = 0x02U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX = 0x11U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_RX0 = 0x21U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_RX1 = 0x41U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX_RX0 = 0x31U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX_RX1 = 0x51U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_RX0_RX1 = 0x61U, /**< CAN process is ongoing */ + CAN_STATE_BUSY_TX_RX0_RX1 = 0x71U, /**< CAN process is ongoing */ + CAN_STATE_TIMEOUT = 0x04U, /**< CAN in Timeout state */ + CAN_STATE_ERROR = 0x08U, /**< CAN error state */ +} can_state_t; + +/** + * @brief CAN Error Code + */ +typedef enum { + CAN_ERROR_NONE = 0x00U, /**< No error */ + CAN_ERROR_EWG = 0x01U, /**< EWG error */ + CAN_ERROR_EPV = 0x02U, /**< EPV error */ + CAN_ERROR_BOF = 0x04U, /**< BOF error */ + CAN_ERROR_STF = 0x08U, /**< Stuff error */ + CAN_ERROR_FOR = 0x10U, /**< Form error */ + CAN_ERROR_ACK = 0x20U, /**< Acknowledgment error */ + CAN_ERROR_BR = 0x40U, /**< Bit recessive */ + CAN_ERROR_BD = 0x80U, /**< LEC dominant */ + CAN_ERROR_CRC = 0x100U, /**< LEC transfer error */ + CAN_ERROR_UNK = 0x200U, /**< Unknown error */ +} can_error_t; + +/** + * @brief CAN Operating Mode + */ + typedef enum { + CAN_MODE_NORMAL = 0x00U, /**< Normal mode */ + CAN_MODE_LOOPBACK = 0x01U, /**< Loopback mode */ + CAN_MODE_SILENT = 0x02U, /**< Silent mode */ + CAN_MODE_SILENT_LOOPBACK = 0x03U, /**< Loopback combined with silent mode */ +} can_operate_mode_t; + +/** + * @brief CAN Synchronization Jump Width + */ +typedef enum { + CAN_SJW_1 = 0x0U, /**< 1 time quantum */ + CAN_SJW_2 = 0x1U, /**< 2 time quantum */ + CAN_SJW_3 = 0x2U, /**< 3 time quantum */ + CAN_SJW_4 = 0x3U, /**< 4 time quantum */ +} can_sjw_t; + +/** + * @brief CAN Time Quantum in Bit Segment 1 + */ +typedef enum { + CAN_SEG1_1 = 0x0U, /**< 1 time quantum */ + CAN_SEG1_2 = 0x1U, /**< 2 time quantum */ + CAN_SEG1_3 = 0x2U, /**< 3 time quantum */ + CAN_SEG1_4 = 0x3U, /**< 4 time quantum */ + CAN_SEG1_5 = 0x4U, /**< 5 time quantum */ + CAN_SEG1_6 = 0x5U, /**< 6 time quantum */ + CAN_SEG1_7 = 0x6U, /**< 7 time quantum */ + CAN_SEG1_8 = 0x7U, /**< 8 time quantum */ + CAN_SEG1_9 = 0x8U, /**< 9 time quantum */ + CAN_SEG1_10 = 0x9U, /**< 10 time quantum */ + CAN_SEG1_11 = 0xAU, /**< 11 time quantum */ + CAN_SEG1_12 = 0xBU, /**< 12 time quantum */ + CAN_SEG1_13 = 0xCU, /**< 13 time quantum */ + CAN_SEG1_14 = 0xDU, /**< 14 time quantum */ + CAN_SEG1_15 = 0xEU, /**< 15 time quantum */ + CAN_SEG1_16 = 0xFU, /**< 16 time quantum */ +} can_seg1_t; + +/** + * @brief CAN Time Quantum in Bit Segment 2 + */ +typedef enum { + CAN_SEG2_1 = 0x0U, /**< 1 time quantum */ + CAN_SEG2_2 = 0x1U, /**< 2 time quantum */ + CAN_SEG2_3 = 0x2U, /**< 3 time quantum */ + CAN_SEG2_4 = 0x3U, /**< 4 time quantum */ + CAN_SEG2_5 = 0x4U, /**< 5 time quantum */ + CAN_SEG2_6 = 0x5U, /**< 6 time quantum */ + CAN_SEG2_7 = 0x6U, /**< 7 time quantum */ + CAN_SEG2_8 = 0x7U, /**< 8 time quantum */ +} can_seg2_t; + +/** + * @brief CAN Filter Mode + */ +typedef enum { + CAN_FILTER_MODE_MASK = 0x0U, /**< Identifier mask mode */ + CAN_FILTER_MODE_LIST = 0x1U, /**< Identifier list mode */ +} can_filter_mode_t; + +/** + * @brief CAN Filter Scale + */ +typedef enum { + CAN_FILTER_SCALE_16 = 0x0U, /**< Two 16-bit filters */ + CAN_FILTER_SCALE_32 = 0x1U, /**< One 32-bit filter */ +} can_filter_scale_t; + +/** + * @brief CAN Filter fifo + */ +typedef enum { + CAN_FILTER_FIFO0 = 0x0U, /**< FIFO 0 assignment for filter */ + CAN_FILTER_FIFO1 = 0x1U, /**< FIFO 1 assignment for filter */ +} can_filter_fifo_t; + +/** + * @brief CAN Identifier Type + */ +typedef enum { + CAN_ID_STD = 0x0U, /**< Standard Id */ + CAN_ID_EXT = 0x1U, /**< Extended Id */ +} can_id_type_t; + +/** + * @brief CAN Remote Transmission Request + */ +typedef enum { + CAN_RTR_DATA = 0x0U, /**< Data frame */ + CAN_RTR_REMOTE = 0x1U, /**< Remote frame */ +} can_remote_req_t; + +/** + * @brief CAN Transmit Constants + */ +typedef enum { + CAN_TX_MAILBOX_0 = 0x0U, /**< TX mailbox index 0 */ + CAN_TX_MAILBOX_1 = 0x1U, /**< TX mailbox index 1 */ + CAN_TX_MAILBOX_2 = 0x2U, /**< TX mailbox index 2 */ + CAN_TX_MAILBOX_NONE = 0x3U, /**< MailBox can't be used */ +} can_tx_mailbox_t; + +/** + * @brief CAN Receive fifo Number + */ +typedef enum { + CAN_RX_FIFO0 = 0x0U, /**< CAN fifo 0 used to receive */ + CAN_RX_FIFO1 = 0x1U, /**< CAN fifo 1 used to receive */ +} can_rx_fifo_t; + +/** + * @brief CAN Flags + */ +typedef enum { + CAN_FLAG_SLPS = (1U << 1), /**< Sleep acknowledge flag */ + CAN_FLAG_ERR = (1U << 2), /**< Error flag*/ + CAN_FLAG_WK = (1U << 3), /**< Wake up flag */ + CAN_FLAG_SLP = (1U << 4), /**< Sleep acknowledge flag */ + CAN_FLAG_M0REQC = (1U << 20) | (1U << 0), /**< Request MailBox0 flag */ + CAN_FLAG_M0TXC = (1U << 20) | (1U << 1), /**< Transmission OK MailBox0 flag */ + CAN_FLAG_M1REQC = (1U << 20) | (1U << 8), /**< Request MailBox1 flag */ + CAN_FLAG_M1TXC = (1U << 20) | (1U << 9), /**< Transmission OK MailBox1 flag */ + CAN_FLAG_M2REQC = (1U << 20) | (1U << 16), /**< Request MailBox2 flag */ + CAN_FLAG_M2TXC = (1U << 20) | (1U << 17), /**< Transmission OK MailBox2 flag */ + CAN_FLAG_TXM0 = (1U << 20) | (1U << 26), /**< Transmit mailbox 0 empty flag */ + CAN_FLAG_TXM1 = (1U << 20) | (1U << 27), /**< Transmit mailbox 1 empty flag */ + CAN_FLAG_TXM2 = (1U << 20) | (1U << 28), /**< Transmit mailbox 2 empty flag */ + CAN_FLAG_FF0 = (2U << 20) | (1U << 3), /**< FIFO 0 Full flag */ + CAN_FLAG_FOV0 = (2U << 20) | (1U << 4), /**< FIFO 0 Overrun flag */ + CAN_FLAG_FF1 = (3U << 20) | (1U << 3), /**< FIFO 1 Full flag */ + CAN_FLAG_FOV1 = (3U << 20) | (1U << 4), /**< FIFO 1 Overrun flag */ + CAN_FLAG_WARN = (4U << 20) | (1U << 0), /**< Error warning flag */ + CAN_FLAG_PERR = (4U << 20) | (1U << 1), /**< Error passive flag */ + CAN_FLAG_BOF = (4U << 20) | (1U << 2), /**< Bus-Off flag */ +} can_flag_t; + +/** + * @brief CAN Interrupts + */ +typedef enum { + CAN_IT_TXM = (1U << 0), /**< Transmit mailbox empty interrupt bit */ + CAN_IT_FP0 = (1U << 1), /**< FIFO0 message pending interrupt bit */ + CAN_IT_FF0 = (1U << 2), /**< FIFO0 full interrupt bit */ + CAN_IT_FOV0 = (1U << 3), /**< FIFO0 overrun interrupt bit */ + CAN_IT_FP1 = (1U << 4), /**< FIFO1 message pending interrupt bit */ + CAN_IT_FF1 = (1U << 5), /**< FIFO1 full interrupt bit */ + CAN_IT_FOV1 = (1U << 6), /**< FIFO1 overrun interrupt bit */ + CAN_IT_WARN = (1U << 8), /**< Error warning interrupt bit */ + CAN_IT_PERR = (1U << 9), /**< Error passive interrupt bit */ + CAN_IT_BOF = (1U << 10), /**< Bus-off interrupt bit */ + CAN_IT_PRERR = (1U << 11), /**< Last error code interrupt bit */ + CAN_IT_ERR = (1U << 15), /**< Error interrupt bit */ + CAN_IT_WK = (1U << 16), /**< wake-up interrupt bit */ + CAN_IT_SLP = (1U << 17), /**< sleep interrupt bit */ +} can_it_t; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct { + uint32_t id_high; /**< Specifies the filter identification number */ + uint32_t id_low; /**< Specifies the filter identification number */ + uint32_t mask_id_high; /**< Specifies the filter mask number or identification number */ + uint32_t mask_id_low; /**< Specifies the filter mask number or identification number */ + can_filter_fifo_t fifo; /**< Specifies the fifo (0 or 1) which will be assigned to the filter. */ + uint32_t number; /**< Specifies the filter which will be initialized. */ + can_filter_mode_t mode; /**< Specifies the filter mode to be initialized. */ + can_filter_scale_t scale; /**< Specifies the filter scale. */ + type_func_t active; /**< Enable or disable the filter. */ +} can_filter_t; + +/** + * @brief CAN init structure definition + */ +typedef struct { + uint32_t psc; /**< Specifies the length of a time quantum. */ + can_operate_mode_t mode; /**< Specifies the CAN operating mode. */ + can_sjw_t sjw; /**< Specifies the maximum number of time quanta the CAN hardware is + allowed to lengthen or shorten a bit to perform resynchronization. */ + can_seg1_t seg1; /**< Specifies the number of time quanta in Bit Segment 1. */ + can_seg2_t seg2; /**< Specifies the number of time quanta in Bit Segment 2. */ + type_func_t ttcm; /**< Enable or disable the time triggered communication mode. */ + type_func_t abom; /**< Enable or disable the automatic bus-off management. */ + type_func_t awk; /**< Enable or disable the automatic wake-up mode. */ + type_func_t artx; /**< Enable or disable the non-automatic retransmission mode. */ + type_func_t rfom; /**< Enable or disable the Receive fifo Locked mode. */ + type_func_t txmp; /**< Enable or disable the transmit fifo priority. */ +} can_init_t; + +/** + * @brief CAN Tx message structure definition + */ +typedef struct { + uint32_t std; /**< Specifies the standard identifier. */ + uint32_t ext; /**< Specifies the extended identifier. */ + can_id_type_t type; /**< Specifies the type of identifier for the message that will be transmitted. */ + can_remote_req_t rtr; /**< Specifies the type of frame for the message that will be transmitted. */ + uint32_t len; /**< Specifies the length of the frame that will be transmitted. */ + uint8_t data[8]; /**< Contains the data to be transmitted. */ +} can_tx_msg_t; + +/** + * @brief CAN Rx message structure definition + */ +typedef struct { + uint32_t std; /**< Specifies the standard identifier. */ + uint32_t ext; /**< Specifies the extended identifier. */ + can_id_type_t type; /**< Specifies the type of identifier for the message that will be received. */ + can_remote_req_t rtr; /**< Specifies the type of frame for the received message. */ + uint32_t len; /**< Specifies the length of the frame that will be received. */ + uint8_t data[8]; /**< Contains the data to be received. */ + uint32_t fmi; /**< Specifies the index of the filter the message stored in the mailbox passes through. */ + can_rx_fifo_t num; /**< Specifies the receive fifo number. */ +} can_rx_msg_t; + +/** + * @brief CAN handle Structure definition + */ +typedef struct can_handle_s { + CAN_TypeDef *perh; /**< Register base address */ + can_init_t init; /**< CAN required parameters */ + can_rx_msg_t *rx0_msg; /**< Pointer to receive message from FIFO0 */ + can_rx_msg_t *rx1_msg; /**< Pointer to receive message from FIFO1 */ + lock_state_t lock; /**< CAN locking object */ + can_state_t state; /**< CAN communication state */ + can_error_t err; /**< CAN Error code */ + + void (*tx_cplt_cbk)(struct can_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct can_handle_s *arg, can_rx_fifo_t num); /**< Rx completed callback */ + void (*error_cbk)(struct can_handle_s *arg); /**< error callback */ +} can_handle_t; +/** + * @} + */ + +/** @defgroup CAN_Public_Macro CAN Public Macros + * @{ + */ +#define CAN_RESET_HANDLE_STATE(x) ((x)->state = CAN_STATE_RESET) +#define CAN_RX_MSG_PENDING(x, y) (((y) == CAN_RX_FIFO0) ? \ + (READ_BIT((x)->perh->RXF0, CAN_RXF0_PEND_MSK)) : (READ_BIT((x)->perh->RXF1, CAN_RXF1_PEND_MSK))) +#define CAN_DBG_FREEZE(x, y) (MODIFY_REG((x)->perh->CON, CAN_CON_DBGSTP_MSK, (y) << CAN_CON_DBGSTP_POS)) +#define CAN_TX_STAMP_ENABLE(x, y) (SET_BIT((x)->perh->TxMailBox[(y)].TXFCON, CAN_TXFCON0_TXGT_MSK)) +#define CAN_TX_STAMP_DISABLE(x, y) (CLEAR_BIT((x)->perh->TxMailBox[(y)].TXFCON, CAN_TXFCON0_TXGT_MSK)) +/** + * @} + */ + +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ +#define IS_CAN_ALL(x) ((x) == CAN0) +#define IS_CAN_FILTER_NUMBER(x) ((x) <= 13) +#define IS_CAN_MODE(x) (((x) == CAN_MODE_NORMAL) || \ + ((x) == CAN_MODE_LOOPBACK) || \ + ((x) == CAN_MODE_SILENT) || \ + ((x) == CAN_MODE_SILENT_LOOPBACK)) +#define IS_CAN_SJW(x) (((x) == CAN_SJW_1) || \ + ((x) == CAN_SJW_2) || \ + ((x) == CAN_SJW_3) || \ + ((x) == CAN_SJW_4)) +#define IS_CAN_BS1(x) ((x) <= CAN_SEG1_16) +#define IS_CAN_BS2(x) ((x) <= CAN_SEG2_8) +#define IS_CAN_FILTER_MODE(x) (((x) == CAN_FILTER_MODE_MASK) || \ + ((x) == CAN_FILTER_MODE_LIST)) +#define IS_CAN_FILTER_SCALE(x) (((x) == CAN_FILTER_SCALE_16) || \ + ((x) == CAN_FILTER_SCALE_32)) +#define IS_CAN_FILTER_FIFO(x) (((x) == CAN_FILTER_FIFO0) || \ + ((x) == CAN_FILTER_FIFO1)) +#define IS_CAN_IDTYPE(x) (((x) == CAN_ID_STD) || \ + ((x) == CAN_ID_EXT)) +#define IS_CAN_RTR(x) (((x) == CAN_RTR_DATA) || ((x) == CAN_RTR_REMOTE)) +#define IS_CAN_FIFO(x) (((x) == CAN_RX_FIFO0) || ((x) == CAN_RX_FIFO1)) +#define IS_CAN_TX_MAILBOX(x) ((x) <= CAN_TX_MAILBOX_NONE) +#define IS_CAN_STDID(x) ((x) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(x) ((x) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DATA_LEN(x) ((x) <= ((uint8_t)0x08)) +#define IS_CAN_PRESCALER(x) (((x) >= 1) && ((x) <= 1024)) +#define IS_CAN_GET_FLAG(x) (((x) == CAN_FLAG_SLPS) || \ + ((x) == CAN_FLAG_ERR) || \ + ((x) == CAN_FLAG_WK) || \ + ((x) == CAN_FLAG_SLP) || \ + ((x) == CAN_FLAG_M0REQC) || \ + ((x) == CAN_FLAG_M0TXC) || \ + ((x) == CAN_FLAG_M1REQC) || \ + ((x) == CAN_FLAG_M1TXC) || \ + ((x) == CAN_FLAG_M2REQC) || \ + ((x) == CAN_FLAG_M2TXC) || \ + ((x) == CAN_FLAG_TXM0) || \ + ((x) == CAN_FLAG_TXM1) || \ + ((x) == CAN_FLAG_TXM2) || \ + ((x) == CAN_FLAG_FF0) || \ + ((x) == CAN_FLAG_FOV0) || \ + ((x) == CAN_FLAG_FF1) || \ + ((x) == CAN_FLAG_FOV1) || \ + ((x) == CAN_FLAG_WARN) || \ + ((x) == CAN_FLAG_PERR) || \ + ((x) == CAN_FLAG_BOF)) +#define IS_CAN_CLEAR_FLAG(x) (((x) == CAN_FLAG_ERR) || \ + ((x) == CAN_FLAG_WK) || \ + ((x) == CAN_FLAG_SLP) || \ + ((x) == CAN_FLAG_M0REQC) || \ + ((x) == CAN_FLAG_M1REQC) || \ + ((x) == CAN_FLAG_M2REQC) || \ + ((x) == CAN_FLAG_FF0) || \ + ((x) == CAN_FLAG_FOV0) || \ + ((x) == CAN_FLAG_FF1) || \ + ((x) == CAN_FLAG_FOV1)) +#define IS_CAN_IT(x) (((x) == CAN_IT_TXM) || \ + ((x) == CAN_IT_FP0) || \ + ((x) == CAN_IT_FF0) || \ + ((x) == CAN_IT_FOV0) || \ + ((x) == CAN_IT_FP1) || \ + ((x) == CAN_IT_FF1) || \ + ((x) == CAN_IT_FOV1) || \ + ((x) == CAN_IT_WARN) || \ + ((x) == CAN_IT_PERR) || \ + ((x) == CAN_IT_BOF) || \ + ((x) == CAN_IT_PRERR) || \ + ((x) == CAN_IT_ERR) || \ + ((x) == CAN_IT_WK) || \ + ((x) == CAN_IT_SLP)) +#define CAN_TIMEOUT_VALUE 100 +#define CAN_STATE_TX_MASK (1U << 4) +#define CAN_STATE_RX0_MASK (1U << 5) +#define CAN_STATE_RX1_MASK (1U << 6) + +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions + * @{ + */ + +/** @addtogroup CAN_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void ald_can_reset(can_handle_t *hperh); +ald_status_t ald_can_init(can_handle_t *hperh); +ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config); +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +ald_status_t ald_can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout); +ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg); +ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout); +ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg); +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions_Group3 + * @{ + */ +/* Control function */ +ald_status_t ald_can_sleep(can_handle_t *hperh); +ald_status_t ald_can_wake_up(can_handle_t *hperh); +void ald_can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box); +void ald_can_irq_handler(can_handle_t *hperh); +type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box); +void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state); +it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it); +flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag); +void ald_can_clear_flag_status(can_handle_t *hperh, can_flag_t flag); +/** + * @} + */ + +/** @addtogroup CAN_Public_Functions_Group4 + * @{ + */ +/* State and Error functions */ +can_state_t ald_can_get_state(can_handle_t *hperh); +can_error_t ald_can_get_error(can_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_CAN_H */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_cmu.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_cmu.h new file mode 100644 index 00000000..7f1f3a0e --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_cmu.h @@ -0,0 +1,805 @@ +/** + ********************************************************************************* + * + * @file ald_cmu.h + * @brief Header file of CMU module driver. + * + * @version V1.0 + * @date 22 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 22 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_CMU_H__ +#define __ALD_CMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_syscfg.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CMU + * @{ + */ + +/** @defgroup CMU_Public_Macros CMU Public Macros + * @{ + */ +#define CMU_HRC_SEL_BY_SW() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CFGR, CMU_CFGR_HRCFCS_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_HRC_SEL_BY_CFGW() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFCS_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_HRC_DIV_1MHZ_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC1MEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_HRC_DIV_1MHZ_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HRC1MEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_HOSC_DIV_1MHZ_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSC1MEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_HOSC_DIV_1MHZ_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSC1MEN_MSK);\ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LOSC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LOSC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LRC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LRC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_ULRC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_ULRC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) + +/* Low power mode control */ +#define CMU_LP_LRC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LP_LRC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LP_LOSC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LP_LOSC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LP_HRC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LP_HRC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LP_HOSC_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define CMU_LP_HOSC_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +/** + * @} + */ + + +/** @defgroup CMU_Public_Types CMU Public Types + * @{ + */ +/** + * @brief CMU state structure definition + */ +typedef enum { + CMU_CLOCK_HRC = 0x1U, /**< HRC */ + CMU_CLOCK_LRC = 0x2U, /**< LRC */ + CMU_CLOCK_LOSC = 0x3U, /**< LOSC */ + CMU_CLOCK_PLL1 = 0x4U, /**< PLL1 */ + CMU_CLOCK_HOSC = 0x5U, /**< HOSC */ +} cmu_clock_t; + +/** + * @brief PLL1 output clock + */ +typedef enum { + CMU_PLL1_OUTPUT_36M = 0x0U, /**< x9 (36MHz) */ + CMU_PLL1_OUTPUT_48M = 0x1U, /**< x12 (48MHz) */ +#if defined(ES32F36xx) || defined(ES32F39xx) + CMU_PLL1_OUTPUT_72M = 0x2U, /**< x18 (72MHz) */ + CMU_PLL1_OUTPUT_96M = 0x3U, /**< x24 (96MHz) */ +#endif +} cmu_pll1_output_t; + +/** + * @brief PLL1 referance clock + */ +typedef enum { + CMU_PLL1_INPUT_HRC_6 = 0x0U, /**< HRC / 6 */ + CMU_PLL1_INPUT_PLL2 = 0x1U, /**< PLL2 */ + CMU_PLL1_INPUT_HOSC = 0x2U, /**< HOSC / 1 */ + CMU_PLL1_INPUT_HOSC_2 = 0x3U, /**< HOSC / 2 */ + CMU_PLL1_INPUT_HOSC_3 = 0x4U, /**< HOSC / 3 */ + CMU_PLL1_INPUT_HOSC_4 = 0x5U, /**< HOSC / 4 */ + CMU_PLL1_INPUT_HOSC_5 = 0x6U, /**< HOSC / 5 */ + CMU_PLL1_INPUT_HOSC_6 = 0x7U, /**< HOSC / 6 */ +} cmu_pll1_input_t; + +/** + * @brief HOSC range + */ +typedef enum { + CMU_HOSC_2M = 0x0U, /**< 0~2MHz */ + CMU_HOSC_4M = 0x1U, /**< 2~4MHz */ + CMU_HOSC_8M = 0x2U, /**< 4~8MHz */ + CMU_HOSC_16M = 0x3U, /**< 8~16MHz */ + CMU_HOSC_24M = 0x4U, /**< 16~24MHz */ +} cmu_hosc_range_t; + +/** + * @brief Safe clock source type + */ +typedef enum { + CMU_SAFE_CLK_HOSC = 0x0U, /**< HOSC */ + CMU_SAFE_CLK_LOSC = 0x1U, /**< LOSC */ + CMU_SAFE_CLK_PLL = 0x2U, /**< PLL */ +} cmu_clock_safe_type_t; + +/** + * @brief Frequency division select bit + */ +typedef enum { + CMU_DIV_1 = 0x0U, /**< Division by 1 */ + CMU_DIV_2 = 0x1U, /**< Division by 2 */ + CMU_DIV_4 = 0x2U, /**< Division by 4 */ + CMU_DIV_8 = 0x3U, /**< Division by 8 */ + CMU_DIV_16 = 0x4U, /**< Division by 16 */ + CMU_DIV_32 = 0x5U, /**< Division by 32 */ + CMU_DIV_64 = 0x6U, /**< Division by 64 */ + CMU_DIV_128 = 0x7U, /**< Division by 128 */ + CMU_DIV_256 = 0x8U, /**< Division by 256 */ + CMU_DIV_512 = 0x9U, /**< Division by 512 */ + CMU_DIV_1024 = 0xAU, /**< Division by 1024 */ + CMU_DIV_2048 = 0xBU, /**< Division by 2048 */ + CMU_DIV_4096 = 0xCU, /**< Division by 4096 */ +} cmu_div_t; + +/** + * @brief Bus type + */ +typedef enum { + CMU_HCLK_1 = 0x0U, /**< AHB1 bus */ + CMU_HCLK_2 = 0x1U, /**< AHB2 bus */ + CMU_SYS = 0x2U, /**< SYS bus */ + CMU_PCLK_1 = 0x3U, /**< APB1 bus */ + CMU_PCLK_2 = 0x4U, /**< APB2 bus */ +} cmu_bus_t; + +/** + * @brief Output high clock select + */ +typedef enum { + CMU_OUTPUT_HIGH_SEL_HOSC = 0x0U, /**< Select HOSC */ + CMU_OUTPUT_HIGH_SEL_LOSC = 0x1U, /**< Select LOSC */ + CMU_OUTPUT_HIGH_SEL_HRC = 0x2U, /**< Select HRC */ + CMU_OUTPUT_HIGH_SEL_LRC = 0x3U, /**< Select LRC */ + CMU_OUTPUT_HIGH_SEL_HOSM = 0x4U, /**< Select HOSM */ + CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5U, /**< Select PLL1 */ + CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6U, /**< Select PLL2 */ + CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7U, /**< Select SYSCLK */ +} cmu_output_high_sel_t; + +/** + * @brief Output frequency division + */ +typedef enum { + CMU_OUTPUT_DIV_1 = 0x0U, /**< Division by 1 */ + CMU_OUTPUT_DIV_2 = 0x1U, /**< Division by 2 */ + CMU_OUTPUT_DIV_4 = 0x2U, /**< Division by 4 */ + CMU_OUTPUT_DIV_8 = 0x3U, /**< Division by 8 */ + CMU_OUTPUT_DIV_16 = 0x4U, /**< Division by 16 */ + CMU_OUTPUT_DIV_32 = 0x5U, /**< Division by 32 */ + CMU_OUTPUT_DIV_64 = 0x6U, /**< Division by 64 */ + CMU_OUTPUT_DIV_128 = 0x7U, /**< Division by 128 */ +} cmu_output_high_div_t; + +/** + * @brief Output low clock select + */ +typedef enum { + CMU_OUTPUT_LOW_SEL_LOSC = 0x0U, /**< Select LOSC */ + CMU_OUTPUT_LOW_SEL_LRC = 0x1U, /**< Select LRC */ + CMU_OUTPUT_LOW_SEL_LOSM = 0x2U, /**< Select LOSM */ + CMU_OUTPUT_LOW_SEL_BUZZ = 0x3U, /**< Select BUZZ */ + CMU_OUTPUT_LOW_SEL_ULRC = 0x4U, /**< Select ULRC */ +} cmu_output_low_sel_t; + +/** + * @brief BUZZ frequency division + */ +typedef enum { + CMU_BUZZ_DIV_2 = 0x0U, /**< Division by 2 */ + CMU_BUZZ_DIV_4 = 0x1U, /**< Division by 4 */ + CMU_BUZZ_DIV_8 = 0x2U, /**< Division by 8 */ + CMU_BUZZ_DIV_16 = 0x3U, /**< Division by 16 */ + CMU_BUZZ_DIV_32 = 0x4U, /**< Division by 32 */ + CMU_BUZZ_DIV_64 = 0x5U, /**< Division by 64 */ + CMU_BUZZ_DIV_128 = 0x6U, /**< Division by 128 */ + CMU_BUZZ_DIV_256 = 0x7U, /**< Division by 256 */ +} cmu_buzz_div_t; + +/** + * @brief Low power peripheral clock select + */ +typedef enum { + CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0U, /**< Select PCLK2 */ + CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1U, /**< Select PLL1 */ + CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2U, /**< Select PLL2 */ + CMU_LP_PERH_CLOCK_SEL_HRC = 0x3U, /**< Select HRC */ + CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4U, /**< Select HOSC */ + CMU_LP_PERH_CLOCK_SEL_LRC = 0x5U, /**< Select LRC */ + CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6U, /**< Select LOSC */ + CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7U, /**< Select ULRC */ + CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8U, /**< Select HRC down to 1MHz */ + CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9U, /**< Select HOSC down to 1MHz */ + CMU_LP_PERH_CLOCK_SEL_LOSM = 0xAU, /**< Select LOSM */ + CMU_LP_PERH_CLOCK_SEL_HOSM = 0xBU, /**< Select HOSM */ +} cmu_lp_perh_clock_sel_t; + +/** + * @brief LCD clock select + */ +typedef enum { + CMU_LCD_SEL_LOSM = 0x0U, /**< Select LOSM */ + CMU_LCD_SEL_LOSC = 0x1U, /**< Select LOSC */ + CMU_LCD_SEL_LRC = 0x2U, /**< Select LRC */ + CMU_LCD_SEL_ULRC = 0x3U, /**< Select ULRC */ + CMU_LCD_SEL_HRC_1M = 0x4U, /**< Select HRC down to 1MHz */ + CMU_LCD_SEL_HOSC_1M = 0x5U, /**< Select HOSC down to 1MHz */ +} cmu_lcd_clock_sel_t; + +/** + * @brief QSPI clock select + */ +typedef enum { + CMU_QSPI_CLOCK_SEL_PCLK1 = 0x0U, /**< Select PCLK1 */ + CMU_QSPI_CLOCK_SEL_HCLK2 = 0x1U, /**< Select HCLK2 */ + CMU_QSPI_CLOCK_SEL_HRC = 0x2U, /**< Select HRC */ + CMU_QSPI_CLOCK_SEL_HOSC = 0x3U, /**< Select HOSC */ + CMU_QSPI_CLOCK_SEL_PLL1 = 0x4U, /**< Select PLL1 */ + CMU_QSPI_CLOCK_SEL_HOSM = 0x5U, /**< Select HOSC security management */ +} cmu_qspi_clock_sel_t; + +/** + * @brief USB clock select + */ +typedef enum { + CMU_USB_CLOCK_SEL_HOSC = 0x0U, /**< Select HOSC */ + CMU_USB_CLOCK_SEL_HRC = 0x1U, /**< Select HRC */ + CMU_USB_CLOCK_SEL_PCLK1 = 0x2U, /**< Select PCLK1 */ + CMU_USB_CLOCK_SEL_PLL1 = 0x3U, /**< Select PLL1 */ + CMU_USB_CLOCK_SEL_HOSM = 0x4U, /**< Select HOSC security management */ +} cmu_usb_clock_sel_t; + +/** + * @brief USB clock division + */ +typedef enum { + CMU_USB_DIV_1 = 0x0U, /**< Division by 1 */ + CMU_USB_DIV_2 = 0x1U, /**< Division by 2 */ + CMU_USB_DIV_4 = 0x2U, /**< Division by 4 */ + CMU_USB_DIV_8 = 0x3U, /**< Division by 8 */ + CMU_USB_DIV_16 = 0x4U, /**< Division by 16 */ + CMU_USB_DIV_32 = 0x5U, /**< Division by 32 */ + CMU_USB_DIV_64 = 0x6U, /**< Division by 64 */ + CMU_USB_DIV_128 = 0x7U, /**< Division by 128 */ + CMU_USB_DIV_256 = 0x8U, /**< Division by 256 */ + CMU_USB_DIV_512 = 0x9U, /**< Division by 512 */ + CMU_USB_DIV_1024 = 0xAU, /**< Division by 1024 */ + CMU_USB_DIV_2048 = 0xBU, /**< Division by 2048 */ + CMU_USB_DIV_4096 = 0xCU, /**< Division by 4096 */ +} cmu_usb_div_t; + +/** + * @brief Peripheral clock enable/disable + * @verbatim + In this module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + 1. For ES32F36xx series: + TIMER0 ----> AD16C4T0 + TIMER1 ----> AD16C4T1 + TIMER2 ----> GP32C4T0 + TIMER3 ----> GP32C4T1 + TIMER4 ----> BS16T0 + TIMER5 ----> BS16T1 + TIMER6 ----> GP16C4T0 + TIMER7 ----> GP16C4T1 + + 2. For ES32F393x/ES32F336x/ES32F392x series: + TIMER0 ----> GP16C4T0 + TIMER1 ----> GP16C4T1 + TIMER2 ----> GP32C4T0 + TIMER3 ----> GP32C4T1 + TIMER4 ----> BS16T0 + TIMER5 ----> BS16T1 + TIMER6 ----> GP16C4T2 + TIMER7 ----> GP16C4T3 + @endverbatim + */ +typedef enum { + CMU_PERH_GPIO = (1U << 0), /**< GPIO */ + CMU_PERH_CRC = (1U << 1), /**< CRC */ + CMU_PERH_CALC = (1U << 2), /**< CALC */ + CMU_PERH_CRYPT = (1U << 3), /**< CRYPT */ + CMU_PERH_TRNG = (1U << 4), /**< TRNG */ + CMU_PERH_PIS = (1U << 5), /**< PIS */ + CMU_PERH_EBI = (1U << 6), /**< EBI */ + CMU_PERH_QSPI_H = (1U << 7), /**< QSPI AHB */ + CMU_PERH_DMA = (1U << 8), /**< DMA */ + CMU_PERH_USB = (1U << 10), /**< USB */ + CMU_PERH_ECC = (1U << 11), /**< ECC */ + CMU_PERH_TIMER0 = (1U << 0) | (1U << 27), /**< TIMER0 */ + CMU_PERH_TIMER1 = (1U << 1) | (1U << 27), /**< TIMER1 */ + CMU_PERH_TIMER2 = (1U << 2) | (1U << 27), /**< TIMER2 */ + CMU_PERH_TIMER3 = (1U << 3) | (1U << 27), /**< TIMER3 */ + CMU_PERH_TIMER4 = (1U << 4) | (1U << 27), /**< TIMER4 */ + CMU_PERH_TIMER5 = (1U << 5) | (1U << 27), /**< TIMER5 */ + CMU_PERH_TIMER6 = (1U << 6) | (1U << 27), /**< TIMER6 */ + CMU_PERH_TIMER7 = (1U << 7) | (1U << 27), /**< TIMER7 */ + CMU_PERH_UART0 = (1U << 8) | (1U << 27), /**< UART0 */ + CMU_PERH_UART1 = (1U << 9) | (1U << 27), /**< UART1 */ + CMU_PERH_UART2 = (1U << 10) | (1U << 27), /**< UART2 */ + CMU_PERH_UART3 = (1U << 11) | (1U << 27), /**< UART3 */ + CMU_PERH_UART4 = (1U << 12) | (1U << 27), /**< UART4 */ + CMU_PERH_UART5 = (1U << 13) | (1U << 27), /**< UART5 */ + CMU_PERH_SPI0 = (1U << 16) | (1U << 27), /**< SPI0 */ + CMU_PERH_SPI1 = (1U << 17) | (1U << 27), /**< SPI1 */ + CMU_PERH_SPI2 = (1U << 18) | (1U << 27), /**< SPI2 */ + CMU_PERH_I2C0 = (1U << 20) | (1U << 27), /**< I2C0 */ + CMU_PERH_I2C1 = (1U << 21) | (1U << 27), /**< I2C1 */ + CMU_PERH_CAN = (1U << 24) | (1U << 27), /**< CAN */ + CMU_PERH_QSPI_P = (1U << 25) | (1U << 27), /**< QSPI APB */ + CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28), /**< LPTIM0 */ + CMU_PERH_LPUART0 = (1U << 2) | (1U << 28), /**< LPUART0 */ + CMU_PERH_ADC0 = (1U << 4) | (1U << 28), /**< ADC0 */ + CMU_PERH_ADC1 = (1U << 5) | (1U << 28), /**< ADC1 */ + CMU_PERH_ACMP0 = (1U << 6) | (1U << 28), /**< ACMP0 */ + CMU_PERH_ACMP1 = (1U << 7) | (1U << 28), /**< ACMP1 */ + CMU_PERH_OPAMP = (1U << 8) | (1U << 28), /**< OPAMP */ + CMU_PERH_DAC0 = (1U << 9) | (1U << 28), /**< DAC0 */ + CMU_PERH_ACMP2 = (1U << 11) | (1U << 28), /**< ACMP2 */ + CMU_PERH_WWDT = (1U << 12) | (1U << 28), /**< WWDT */ + CMU_PERH_LCD = (1U << 13) | (1U << 28), /**< LCD */ + CMU_PERH_IWDT = (1U << 14) | (1U << 28), /**< IWDT */ + CMU_PERH_RTC = (1U << 15) | (1U << 28), /**< RTC */ + CMU_PERH_TSENSE = (1U << 16) | (1U << 28), /**< TSENSE */ + CMU_PERH_BKPC = (1U << 17) | (1U << 28), /**< BKPC */ + CMU_PERH_DBGC = (1U << 19) | (1U << 28), /**< DBGC */ + CMU_PERH_ALL = (0x7FFFFFFFU), /**< ALL */ +} cmu_perh_t; + +/** + * @brief CMU interrupt type + */ +typedef enum { + CMU_LOSC_STOP = 0x0U, /**< LOSC STOP INTERRUPT */ + CMU_HOSC_STOP = 0x1U, /**< HOSC STOP INTERRUPT */ + CMU_PLL1_UNLOCK = 0x2U, /**< PLL1 UNLOCK INTERRUPT */ + CMU_LOSC_START = 0x3U, /**< LOSC START INTERRUPT */ + CMU_HOSC_START = 0x4U, /**< HOSC START INTERRUPT */ +} cmu_security_t; + +/** + * @brief CMU clock state type + */ +typedef enum { + CMU_CLOCK_STATE_HOSCACT = (1U << 0), /**< HOSC active */ + CMU_CLOCK_STATE_LOSCACT = (1U << 1), /**< LOSC active */ + CMU_CLOCK_STATE_HRCACT = (1U << 2), /**< HRC active */ + CMU_CLOCK_STATE_LRCACT = (1U << 3), /**< LRC active */ + CMU_CLOCK_STATE_ULRCACT = (1U << 4), /**< ULRC active */ + CMU_CLOCK_STATE_PLL1ACT = (1U << 8), /**< PLL1 active */ + CMU_CLOCK_STATE_PLL2ACT = (1U << 9), /**< PLL2 active */ + CMU_CLOCK_STATE_HOSCRDY = (1U << 16), /**< HOSC ready */ + CMU_CLOCK_STATE_LOSCRDY = (1U << 17), /**< LOSC ready */ + CMU_CLOCK_STATE_HRCRDY = (1U << 18), /**< HRC ready */ + CMU_CLOCK_STATE_LRCRDY = (1U << 19), /**< LRC ready */ + CMU_CLOCK_STATE_PLL1RDY = (1U << 24), /**< PLL1 ready */ + CMU_CLOCK_STATE_PLL2RDY = (1U << 25), /**< PLL2 ready */ +} cmu_clock_state_t; + +/** + * @brief Stop1 clock select type + */ +typedef enum { + CMU_STOP1_CLOCK_LRC = 0x0U, /**< LRC */ + CMU_STOP1_CLOCK_HRC_24M = 0x1U, /**< HRC 24MHz */ + CMU_STOP1_CLOCK_HRC_2M = 0x2U, /**< HRC 2MHz */ + CMU_STOP1_CLOCK_HRC_1M = 0x3U, /**< HRC divides to 1MHz */ + CMU_STOP1_CLOCK_HOSC = 0x4U, /**< HOSC */ + CMU_STOP1_CLOCK_HOSC_1M = 0x5U, /**< HOSC divides to 1MHz */ + CMU_STOP1_CLOCK_HOSCM = 0x6U, /**< HOSC security management */ +} cmu_stop1_clock_t; + +/** + * @} + */ + +/** + * @defgroup CMU_Private_Macros CMU Private Macros + * @{ + */ +#define IS_CMU_CLOCK(x) (((x) == CMU_CLOCK_HRC) || \ + ((x) == CMU_CLOCK_LRC) || \ + ((x) == CMU_CLOCK_LOSC) || \ + ((x) == CMU_CLOCK_PLL1) || \ + ((x) == CMU_CLOCK_HOSC)) +#if defined(ES32F36xx) || defined(ES32F39xx) +#define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_36M) || \ + ((x) == CMU_PLL1_OUTPUT_48M) || \ + ((x) == CMU_PLL1_OUTPUT_72M) || \ + ((x) == CMU_PLL1_OUTPUT_96M)) +#endif +#ifdef ES32F336x +#define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_36M) || \ + ((x) == CMU_PLL1_OUTPUT_48M)) +#endif +#define IS_CMU_PLL1_INPUT(x) (((x) == CMU_PLL1_INPUT_HRC_6) || \ + ((x) == CMU_PLL1_INPUT_PLL2) || \ + ((x) == CMU_PLL1_INPUT_HOSC) || \ + ((x) == CMU_PLL1_INPUT_HOSC_2) || \ + ((x) == CMU_PLL1_INPUT_HOSC_3) || \ + ((x) == CMU_PLL1_INPUT_HOSC_4) || \ + ((x) == CMU_PLL1_INPUT_HOSC_5) || \ + ((x) == CMU_PLL1_INPUT_HOSC_6)) +#define IS_CMU_HOSC_RANGE(x) (((x) == CMU_HOSC_2M) || \ + ((x) == CMU_HOSC_4M) || \ + ((x) == CMU_HOSC_8M) || \ + ((x) == CMU_HOSC_16M) || \ + ((x) == CMU_HOSC_24M)) +#define IS_CMU_DIV(x) (((x) == CMU_DIV_1) || \ + ((x) == CMU_DIV_2) || \ + ((x) == CMU_DIV_4) || \ + ((x) == CMU_DIV_8) || \ + ((x) == CMU_DIV_16) || \ + ((x) == CMU_DIV_32) || \ + ((x) == CMU_DIV_64) || \ + ((x) == CMU_DIV_128) || \ + ((x) == CMU_DIV_256) || \ + ((x) == CMU_DIV_512) || \ + ((x) == CMU_DIV_1024) || \ + ((x) == CMU_DIV_2048) || \ + ((x) == CMU_DIV_4096)) +#define IS_CMU_BUS(x) (((x) == CMU_HCLK_1) || \ + ((x) == CMU_HCLK_2) || \ + ((x) == CMU_SYS) || \ + ((x) == CMU_PCLK_1) || \ + ((x) == CMU_PCLK_2)) +#define IS_CMU_OUTPUT_HIGH_SEL(x) (((x) == CMU_OUTPUT_HIGH_SEL_HOSC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_HRC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_LRC) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \ + ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK)) +#define IS_CMU_OUTPUT_HIGH_DIV(x) (((x) == CMU_OUTPUT_DIV_1) || \ + ((x) == CMU_OUTPUT_DIV_2) || \ + ((x) == CMU_OUTPUT_DIV_4) || \ + ((x) == CMU_OUTPUT_DIV_8) || \ + ((x) == CMU_OUTPUT_DIV_16) || \ + ((x) == CMU_OUTPUT_DIV_32) || \ + ((x) == CMU_OUTPUT_DIV_64) || \ + ((x) == CMU_OUTPUT_DIV_128)) +#define IS_CMU_OUTPUT_LOW_SEL(x) (((x) == CMU_OUTPUT_LOW_SEL_LOSC) || \ + ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \ + ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \ + ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \ + ((x) == CMU_OUTPUT_LOW_SEL_ULRC)) +#define IS_CMU_SAFE_CLOCK_TYPE(x) (((x) == CMU_SAFE_CLK_HOSC) || \ + ((x) == CMU_SAFE_CLK_LOSC) || \ + ((x) == CMU_SAFE_CLK_PLL)) +#define IS_CMU_BUZZ_DIV(x) (((x) == CMU_BUZZ_DIV_2) || \ + ((x) == CMU_BUZZ_DIV_4) || \ + ((x) == CMU_BUZZ_DIV_8) || \ + ((x) == CMU_BUZZ_DIV_16) || \ + ((x) == CMU_BUZZ_DIV_32) || \ + ((x) == CMU_BUZZ_DIV_64) || \ + ((x) == CMU_BUZZ_DIV_128) || \ + ((x) == CMU_BUZZ_DIV_256)) +#define IS_CMU_LP_PERH_CLOCK_SEL(x) (((x) == CMU_LP_PERH_CLOCK_SEL_PCLK2) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LOSC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_ULRC) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM) || \ + ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM)) +#define IS_CMU_LCD_CLOCK_SEL(x) (((x) == CMU_LCD_SEL_LOSM) || \ + ((x) == CMU_LCD_SEL_LOSC) || \ + ((x) == CMU_LCD_SEL_LRC) || \ + ((x) == CMU_LCD_SEL_ULRC) || \ + ((x) == CMU_LCD_SEL_HRC_1M) || \ + ((x) == CMU_LCD_SEL_HOSC_1M)) +#define IS_CMU_QSPI_CLOCK_SEL(x) (((x) == CMU_QSPI_CLOCK_SEL_PCLK1) || \ + ((x) == CMU_QSPI_CLOCK_SEL_HCLK2) || \ + ((x) == CMU_QSPI_CLOCK_SEL_HRC) || \ + ((x) == CMU_QSPI_CLOCK_SEL_HOSC) || \ + ((x) == CMU_QSPI_CLOCK_SEL_PLL1) || \ + ((x) == CMU_QSPI_CLOCK_SEL_HOSM)) +#define IS_CMU_USB_CLOCK_SEL(x) (((x) == CMU_USB_CLOCK_SEL_HOSC) || \ + ((x) == CMU_USB_CLOCK_SEL_HRC) || \ + ((x) == CMU_USB_CLOCK_SEL_PCLK1) || \ + ((x) == CMU_USB_CLOCK_SEL_PLL1) || \ + ((x) == CMU_USB_CLOCK_SEL_HOSM)) +#define IS_CMU_USB_DIV(x) (((x) == CMU_USB_DIV_1) || \ + ((x) == CMU_USB_DIV_2) || \ + ((x) == CMU_USB_DIV_4) || \ + ((x) == CMU_USB_DIV_8) || \ + ((x) == CMU_USB_DIV_16) || \ + ((x) == CMU_USB_DIV_32) || \ + ((x) == CMU_USB_DIV_64) || \ + ((x) == CMU_USB_DIV_128) || \ + ((x) == CMU_USB_DIV_256) || \ + ((x) == CMU_USB_DIV_512) || \ + ((x) == CMU_USB_DIV_1024) || \ + ((x) == CMU_USB_DIV_2048) || \ + ((x) == CMU_USB_DIV_4096)) +#define IS_CMU_PERH(x) (((x) == CMU_PERH_GPIO) || \ + ((x) == CMU_PERH_CRC) || \ + ((x) == CMU_PERH_CALC) || \ + ((x) == CMU_PERH_CRYPT) || \ + ((x) == CMU_PERH_TRNG) || \ + ((x) == CMU_PERH_PIS) || \ + ((x) == CMU_PERH_EBI) || \ + ((x) == CMU_PERH_QSPI_H) || \ + ((x) == CMU_PERH_DMA) || \ + ((x) == CMU_PERH_USB) || \ + ((x) == CMU_PERH_ECC) || \ + ((x) == CMU_PERH_TIMER0) || \ + ((x) == CMU_PERH_TIMER1) || \ + ((x) == CMU_PERH_TIMER2) || \ + ((x) == CMU_PERH_TIMER3) || \ + ((x) == CMU_PERH_TIMER4) || \ + ((x) == CMU_PERH_TIMER5) || \ + ((x) == CMU_PERH_TIMER6) || \ + ((x) == CMU_PERH_TIMER7) || \ + ((x) == CMU_PERH_UART0) || \ + ((x) == CMU_PERH_UART1) || \ + ((x) == CMU_PERH_UART2) || \ + ((x) == CMU_PERH_UART3) || \ + ((x) == CMU_PERH_UART4) || \ + ((x) == CMU_PERH_UART5) || \ + ((x) == CMU_PERH_SPI0) || \ + ((x) == CMU_PERH_SPI1) || \ + ((x) == CMU_PERH_SPI2) || \ + ((x) == CMU_PERH_I2C0) || \ + ((x) == CMU_PERH_I2C1) || \ + ((x) == CMU_PERH_CAN) || \ + ((x) == CMU_PERH_QSPI_P) || \ + ((x) == CMU_PERH_LPTIM0) || \ + ((x) == CMU_PERH_LPUART0) || \ + ((x) == CMU_PERH_ADC0) || \ + ((x) == CMU_PERH_ADC1) || \ + ((x) == CMU_PERH_ACMP0) || \ + ((x) == CMU_PERH_ACMP1) || \ + ((x) == CMU_PERH_OPAMP) || \ + ((x) == CMU_PERH_DAC0) || \ + ((x) == CMU_PERH_ACMP2) || \ + ((x) == CMU_PERH_WWDT) || \ + ((x) == CMU_PERH_LCD) || \ + ((x) == CMU_PERH_IWDT) || \ + ((x) == CMU_PERH_RTC) || \ + ((x) == CMU_PERH_TSENSE) || \ + ((x) == CMU_PERH_BKPC) || \ + ((x) == CMU_PERH_DBGC) || \ + ((x) == CMU_PERH_ALL)) +#define IS_CMU_CLOCK_STATE(x) (((x) == CMU_CLOCK_STATE_HOSCACT) || \ + ((x) == CMU_CLOCK_STATE_LOSCACT) || \ + ((x) == CMU_CLOCK_STATE_HRCACT) || \ + ((x) == CMU_CLOCK_STATE_LRCACT) || \ + ((x) == CMU_CLOCK_STATE_ULRCACT) || \ + ((x) == CMU_CLOCK_STATE_PLL1ACT) || \ + ((x) == CMU_CLOCK_STATE_PLL2ACT) || \ + ((x) == CMU_CLOCK_STATE_HOSCRDY) || \ + ((x) == CMU_CLOCK_STATE_LOSCRDY) || \ + ((x) == CMU_CLOCK_STATE_HRCRDY) || \ + ((x) == CMU_CLOCK_STATE_LRCRDY) || \ + ((x) == CMU_CLOCK_STATE_PLL1RDY) || \ + ((x) == CMU_CLOCK_STATE_PLL2RDY)) +#define IS_CMU_STOP1_CLOCK(x) (((x) == CMU_STOP1_CLOCK_LRC) || \ + ((x) == CMU_STOP1_CLOCK_HRC_24M) || \ + ((x) == CMU_STOP1_CLOCK_HRC_2M) || \ + ((x) == CMU_STOP1_CLOCK_HRC_1M) || \ + ((x) == CMU_STOP1_CLOCK_HOSC) || \ + ((x) == CMU_STOP1_CLOCK_HOSC_1M) || \ + ((x) == CMU_STOP1_CLOCK_HOSCM)) +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions + * @{ + */ +/** @addtogroup CMU_Public_Functions_Group1 + * @{ + */ +/* System clock configure */ +ald_status_t ald_cmu_clock_config_default(void); +ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock); +void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output); +uint32_t ald_cmu_get_clock(void); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group2 + * @{ + */ +/* BUS division control */ +void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div); +uint32_t ald_cmu_get_hclk1_clock(void); +uint32_t ald_cmu_get_hclk2_clock(void); +uint32_t ald_cmu_get_sys_clock(void); +uint32_t ald_cmu_get_pclk1_clock(void); +uint32_t ald_cmu_get_pclk2_clock(void); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group3 + * @{ + */ +/* Clock safe configure */ +void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status); +void ald_cmu_losc_safe_config(type_func_t status); +void ald_cmu_pll_safe_config(type_func_t status); +uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type); +flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr); +void ald_cmu_irq_handler(void); +void ald_cmu_irq_cbk(cmu_security_t se); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group4 + * @{ + */ +/* Clock output configure */ +void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, + cmu_output_high_div_t div, type_func_t status); +void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status); +/** + * @} + */ + +/** @addtogroup CMU_Public_Functions_Group5 + * @{ + */ +/* Peripheral Clock configure */ +void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status); +void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock); +void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock); +void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock); +void ald_cmu_qspi_clock_select(cmu_qspi_clock_sel_t clock); +void ald_cmu_usb_clock_config(cmu_usb_clock_sel_t clock, cmu_usb_div_t div); +void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status); +void ald_cmu_stop1_clock_sel(cmu_stop1_clock_t clock); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_CMU_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_crc.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_crc.h new file mode 100644 index 00000000..5df4c7d3 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_crc.h @@ -0,0 +1,212 @@ +/** + ********************************************************************************* + * + * @file ald_crc.h + * @brief Header file of CRC module driver. + * + * @version V1.0 + * @date 18 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 18 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_CRC_H__ +#define __ALD_CRC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @defgroup CRC_Public_Types CRC Public Types + * @{ + */ + +/** + * @brief CRC mode + */ +typedef enum { + CRC_MODE_CCITT = 0U, /**< Ccitt */ + CRC_MODE_8 = 1U, /**< Crc8 */ + CRC_MODE_16 = 2U, /**< Crc16 */ + CRC_MODE_32 = 3U, /**< Crc32 */ +} crc_mode_t; + +/** + * @brief CRC input length + */ +typedef enum { + CRC_LEN_AUTO = 0U, /**< Auto */ + CRC_DATASIZE_8 = 1U, /**< Byte */ + CRC_DATASIZE_16 = 2U, /**< Half word */ + CRC_DATASIZE_32 = 3U, /**< Word */ +} crc_datasize_t; + +/** + * @brief CRC whether write error or no + */ +typedef enum { + CRC_WERR_NO = 0U, /**< No error */ + CRC_WERR_ERR = 1U, /**< Error */ +} crc_werr_t; + +/** + * @brief CRC state structures definition + */ +typedef enum { + CRC_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ + CRC_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ + CRC_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ + CRC_STATE_ERROR = 0x4U, /**< Error */ +} crc_state_t; + +/** + * @brief CRC init structure definition + */ +typedef struct { + crc_mode_t mode; /**< CRC mode */ + type_func_t data_rev; /**< CRC data reverse or no */ + type_func_t data_inv; /**< CRC data inverse or no */ + type_func_t chs_rev; /**< CRC check sum reverse or no */ + type_func_t chs_inv; /**< CRC check sum inverse or no */ + uint32_t seed; /**< CRC seed */ +} crc_init_t; + +/** + * @brief CRC Handle Structure definition + */ +typedef struct crc_handle_s { + CRC_TypeDef *perh; /**< Register base address */ + crc_init_t init; /**< CRC required parameters */ + uint8_t *cal_buf; /**< The pointer of preparing buffer */ + uint32_t *cal_res; /**< The pointer of result */ + + dma_handle_t hdma; /**< CRC DMA handle parameters */ + + lock_state_t lock; /**< Locking object */ + crc_state_t state; /**< CRC operation state */ + + void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */ + void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */ +} crc_handle_t; +/** + * @} + */ + +/** @defgroup CRC_Public_Macros CRC Public Macros + * @{ + */ +#define CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) +#define CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK)) +#define CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK)) +#define CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) +#define CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK)) +#define CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK)) +/** + * @} + */ + +/** @defgroup CRC_Private_Macros CRC Private Macros + * @{ + */ +#define IS_CRC(x) ((x) == CRC) +#define IS_CRC_MODE(x) (((x) == CRC_MODE_CCITT) || \ + ((x) == CRC_MODE_8) || \ + ((x) == CRC_MODE_16) || \ + ((x) == CRC_MODE_32)) +/** + * @} + */ + +/** @addtogroup CRC_Public_Functions + * @{ + */ + +/** @addtogroup CRC_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_crc_init(crc_handle_t *hperh); +void ald_crc_reset(crc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup CRC_Public_Functions_Group2 + * @{ + */ +uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size); +uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size); +uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size); +/** + * @} + */ + + +/** @addtogroup CRC_Public_Functions_Group3 + * @{ + */ +ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel); +ald_status_t ald_crc_dma_pause(crc_handle_t *hperh); +ald_status_t ald_crc_dma_resume(crc_handle_t *hperh); +ald_status_t ald_crc_dma_stop(crc_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup CRC_Public_Functions_Group4 + * @{ + */ +crc_state_t ald_crc_get_state(crc_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_CRC_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_crypt.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_crypt.h new file mode 100644 index 00000000..54b99638 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_crypt.h @@ -0,0 +1,341 @@ +/** + ********************************************************************************* + * + * @file ald_crypt.h + * @brief Header file of CRYPT module driver. + * + * @version V1.0 + * @date 19 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 19 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_CRYPT_H__ +#define __ALD_CRYPT_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup CRYPT + * @{ + */ + +/** @defgroup CRYPT_Public_Types CRYPT Public Types + * @{ + */ + +/** + * @brief CRYPT encrypt or decrypt select + */ +typedef enum { + CRYPT_DECRYPT = 0U, /**< Decrypt */ + CRYPT_ENCRYPT = 1U, /**< Encrypt */ +} crypt_encs_t; + +/** + * @brief CRYPT aes key select + */ +typedef enum { + CRYPT_BITS_128 = 0U, /**< 128bit key for aes */ + CRYPT_BITS_192 = 1U, /**< 192bit key for aes */ + CRYPT_BITS_256 = 2U, /**< 256bit key for aes */ +} crypt_aesks_t; + +/** + * @brief CRYPT mode select + */ +typedef enum { + CRYPT_MODE_ECB = 0U, /**< ECB */ + CRYPT_MODE_CBC = 1U, /**< CBC */ + CRYPT_MODE_CTR = 2U, /**< CTR */ +} crypt_mode_t; + +/** + * @brief CRYPT data type + */ +typedef enum { + CRYPT_DATA_CHANGE_NO = 0U, /**< No exchange */ + CRYPT_DATA_CHANGE_16 = 1U, /**< 16bit exchange */ + CRYPT_DATA_CHANGE_8 = 2U, /**< 8bit exchange */ + CRYPT_DATA_CHANGE_1 = 3U, /**< 1bit exchange */ +} crypt_datatype_t; + +/** + * @brief CRYPT des key select + */ +typedef enum { + CRYPT_KEYS_2 = 0U, /**< 2 key for des */ + CRYPT_KEYS_3 = 1U, /**< 3 key for des */ + CRYPT_KEYS_1 = 2U, /**< 1 key for des */ +} crypt_desks_t; + +/** + * @brief CRYPT crypt select + */ +typedef enum { + CRYPT_CRYSEL_AES = 0U, /**< AES */ + CRYPT_CRYSEL_DES = 1U, /**< DES */ +} crypt_crysel_t; + +/** + * @brief CRYPT interrupt + */ +typedef enum { + CRYPT_IT_IT = 0x80U, /**< Interrupt */ +} crypt_it_t; + +/** + * @brief CRYPT interrupt flag + */ +typedef enum { + CRYPT_FLAG_AESIF = 0x1U, /**< Aes flag */ + CRYPT_FLAG_DESIF = 0x2U, /**< Des flag */ + CRYPT_FLAG_DONE = 0x100U, /**< Complete flag */ +} crypt_flag_t; + +/** + * @brief CRYPT key select + */ +typedef enum { + CRYPT_AES_BITS_128 = 0x4U, /**< 128bit key of aes */ + CRYPT_AES_BITS_192 = 0x6U, /**< 192bit key of aes */ + CRYPT_AES_BITS_256 = 0x8U, /**< 192bit key of ase */ + CRYPT_DES_KEYS_1 = 0x12U, /**< 1 key of des */ + CRYPT_DES_KEYS_2 = 0x14U, /**< 2 key of des */ + CRYPT_DES_KEYS_3 = 0x16U, /**< 3 key of des */ +} crypt_ks_t; + +/** + * @brief CRYPT state structures definition + */ +typedef enum { + CRYPT_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ + CRYPT_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ + CRYPT_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ + CRYPT_STATE_ERROR = 0x4U, /**< Error */ +} crypt_state_t; + +/** + * @brief CRYPT key length + */ +typedef enum { + KEY_2_LEN = 2U, /**< Key's lenth is 2 */ + KEY_4_LEN = 4U, /**< Key's lenth is 4 */ + KEY_6_LEN = 6U, /**< Key's lenth is 6 */ + KEY_8_LEN = 8U, /**< Key's lenth is 8 */ +} crypt_key_len_t; + +/** + * @brief CRYPT iv length + */ +typedef enum { + IV_2_LEN = 2U, /**< iv's lenth is 2 */ + IV_4_LEN = 4U, /**< iv's lenth is 4 */ +} crypt_ivr_len_t; + +/** + * @brief CRYPT data type + */ +typedef enum { + DATA_32_BIT = 0U, /**< 32 bit data,don't swap */ + DATA_16_BIT = 1U, /**< 16 bit data,swap */ + DATA_8_BIT = 2U, /**< 8 bit data,swap */ + DATA_1_BIT = 3U, /**< 1 bit data, swap */ +} crypt_data_t; + +/** + * @brief CRYPT init structure definition + */ +typedef struct { + crypt_mode_t mode; /**< Crypt mode */ + crypt_data_t type; /**< Data type select */ + crypt_ks_t key; /**< Key select */ +} crypt_init_t; + +/** + * @brief CRYPT Handle Structure definition + */ +typedef struct crypt_handle_s { + CRYPT_TypeDef *perh; /**< Register base address */ + crypt_init_t init; /**< CRYPT required parameters */ + + dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */ + dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */ + + uint8_t *plain_text; /**< Pointer to plain text */ + uint8_t *cipher_text; /**< Pointer to cipher text */ + uint32_t size; /**< The size of crypt data buf */ + uint32_t count; /**< The count of crypt data buf */ + uint32_t step; /**< The step of once crypt 2(des) or 4(aes) */ + uint32_t dir; /**< ENCRYPT or DECRYPT */ + uint32_t iv[4]; /**< The iv of crypt */ + uint32_t iv_size; /**< The iv size */ + uint32_t key[8]; /**< The key of crypt */ + uint32_t key_size; /**< The key size */ + lock_state_t lock; /**< Locking object */ + crypt_state_t state; /**< CRYPT operation state */ + + void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */ + void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */ +} crypt_handle_t; +/** + * @} + */ + +/** @defgroup CRYPT_Public_Macros CRYPT Public Macros + * @{ + */ +#define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK)) +#define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) +#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK)) +#define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) +#define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK)) +#define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) +#define CRYPT_IE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK)) +#define CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) +#define CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK)) +#define CRYPT_SETDIR(handle, dir) do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS); \ + (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0) +#define CRYPT_WRITE_FIFO(handle, data) ((handle)->perh->FIFO = (data)) +#define CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO) +/** + * @} + */ + +/** @defgroup CRYPT_Private_Macros CRYPT Private Macros + * @{ + */ +#define IS_CRYPT(x) ((x) == CRYPT) +#define IS_CRYPT_MODE(x) (((x) == CRYPT_MODE_ECB) || \ + ((x) == CRYPT_MODE_CBC) || \ + ((x) == CRYPT_MODE_CTR)) +#define IS_CRYPT_KS(x) (((x) == CRYPT_AES_BITS_128) || \ + ((x) == CRYPT_AES_BITS_192) || \ + ((x) == CRYPT_AES_BITS_256) || \ + ((x) == CRYPT_DES_KEYS_1) || \ + ((x) == CRYPT_DES_KEYS_2) || \ + ((x) == CRYPT_DES_KEYS_3)) +#define IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT) +#define IS_CRYPT_FLAG(x) (((x) == CRYPT_FLAG_AESIF) || \ + ((x) == CRYPT_FLAG_DESIF) || \ + ((x) == CRYPT_FLAG_DONE)) +#define IS_CRYPT_IV_LEN(x) (((x) == IV_2_LEN) || \ + ((x) == IV_4_LEN)) +#define IS_CRYPT_KEY_LEN(x) (((x) == KEY_2_LEN) || \ + ((x) == KEY_4_LEN) || \ + ((x) == KEY_6_LEN) || \ + ((x) == KEY_8_LEN)) +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions + * @{ + */ + +/** @addtogroup CRYPT_Public_Functions_Group1 + * @{ + */ +extern ald_status_t ald_crypt_init(crypt_handle_t *hperh); +extern ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t * key, crypt_key_len_t len); +extern ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t * key, crypt_key_len_t len); +extern ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t * iv, crypt_ivr_len_t len); +extern ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t * iv, crypt_ivr_len_t len); +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions_Group2 + * @{ + */ +extern ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t * plain_text, uint8_t * cipher_text, uint32_t size); +extern ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t * cipher_text, uint8_t * plain_text, uint32_t size); +extern ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag); +extern ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size); +extern ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size); + +extern ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t * plain_text, + uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); +extern ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t * cipher_text, + uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m); + +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions_Group3 + * @{ + */ + +extern ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh); +extern ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh); +extern ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh); + +extern void ald_crypt_irq_handler(crypt_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions_Group4 + * @{ + */ +extern void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state); +extern flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag); +extern void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag); +extern it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it); +/** + * @} + */ + +/** @addtogroup CRYPT_Public_Functions_Group5 + * @{ + */ +extern crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_dac.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_dac.h new file mode 100644 index 00000000..203e5af6 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_dac.h @@ -0,0 +1,321 @@ +/** + ****************************************************************************** + * @file ald_dac.h + * @brief Header file of DAC Module library. + * + * @version V1.0 + * @date 28 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 28 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_DAC_H__ +#define __ALD_DAC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Pubulic_Types DAC Pubulic Types + * @{ + */ +/** + * @brief DAC channel + */ +typedef enum { + DAC_CHANNEL_0 = 1U, /**< DAC channel 0 */ + DAC_CHANNEL_1 = 2U, /**< DAC channel 1 */ + DAC_CHANNEL_COMB = 3U, /**< DAC channel 0 and 1 */ +} dac_channel_t; + +/** + * @brief DAC convert mode + */ +typedef enum { + DAC_CONV_MODE_CONTINUOUS = 0U, /**< DAC set in continuous mode */ + DAC_CONV_MODE_SAMPLEHOLD = 1U, /**< DAC set in sample/hold mode */ + DAC_CONV_MODE_SAMPLEOFF = 2U, /**< DAC set in sample/shut off mode */ +} dac_conv_mode_t; + +/** + * @brief DAC out mode + */ +typedef enum { + DAC_OUTPUT_DISABLE = 0U, /**< DAC output disable */ + DAC_OUTPUT_PIN = 1U, /**< DAC output to pin enable */ + DAC_OUTPUT_ADC = 2U, /**< DAC output to adc and acmp enable */ + DAC_OUTPUT_PIN_ADC = 3U, /**< DAC output to pin, adc and acmp enable */ +} dac_out_mode_t; + +/** + * @brief DAC pis input channel + */ +typedef enum { + DAC_PIS_CH_0 = 0U, /**< PIS channel 0 triggers DAC channel conversion */ + DAC_PIS_CH_1 = 1U, /**< PIS channel 1 triggers DAC channel conversion */ + DAC_PIS_CH_2 = 2U, /**< PIS channel 2 triggers DAC channel conversion */ + DAC_PIS_CH_3 = 3U, /**< PIS channel 3 triggers DAC channel conversion */ + DAC_PIS_CH_4 = 4U, /**< PIS channel 4 triggers DAC channel conversion */ + DAC_PIS_CH_5 = 5U, /**< PIS channel 5 triggers DAC channel conversion */ + DAC_PIS_CH_6 = 6U, /**< PIS channel 6 triggers DAC channel conversion */ + DAC_PIS_CH_7 = 7U, /**< PIS channel 7 triggers DAC channel conversion */ + DAC_PIS_CH_8 = 8U, /**< PIS channel 8 triggers DAC channel conversion */ + DAC_PIS_CH_9 = 9U, /**< PIS channel 9 triggers DAC channel conversion */ + DAC_PIS_CH_10 = 10U, /**< PIS channel 10 triggers DAC channel conversion */ + DAC_PIS_CH_11 = 11U, /**< PIS channel 11 triggers DAC channel conversion */ +} dac_pissel_t; + +/** + * @brief DAC negative reference voltage definition + */ +typedef enum { + DAC_NEG_REF_VSS = 0x0U, /**< DAC negative regerence voltage vss */ + DAC_NEG_REF_VREFN = 0x1U, /**< DAC negative regerence voltage vrefn */ +} dac_neg_ref_t; + +/** + * @brief DAC positive reference voltage definition + */ +typedef enum { + DAC_POS_REF_VDD = 0x0U, /**< DAC posotove reference is VDD */ + DAC_POS_REF_2V = 0x1U, /**< DAC posotove reference is internal 2V */ + DAC_POS_REF_VREEFP = 0x2U, /**< DAC posotove reference is VREEFP */ + DAC_POS_REF_VREEFP_BUF = 0x3U, /**< DAC posotove reference is VREEFP BUFFER */ +} dac_pos_ref_t; + +/** + * @brief Refresh interval select + */ +typedef enum { + DAC_REFRESH_8 = 0U, /**< Channel refreshed every 8 cycles */ + DAC_REFRESH_16 = 1U, /**< Channel refreshed every 16 cycles */ + DAC_REFRESH_32 = 2U, /**< Channel refreshed every 32 cycles */ + DAC_REFRESH_64 = 3U, /**< Channel refreshed every 64 cycles */ +} dac_refresh_t; + +/** + * @brief DAC prescale + */ +typedef enum { + DAC_PRES_DIV_1 = 0U, /**< No division */ + DAC_PRES_DIV_2 = 1U, /**< 2 clock division */ + DAC_PRES_DIV_4 = 2U, /**< 4 clock division */ + DAC_PRES_DIV_8 = 3U, /**< 8 clock division */ + DAC_PRES_DIV_16 = 4U, /**< 16 clock division */ + DAC_PRES_DIV_32 = 5U, /**< 32 clock division */ + DAC_PRES_DIV_64 = 6U, /**< 64 clock division */ + DAC_PRES_DIV_128 = 7U, /**< 128 clock division */ +} dac_prescale_div_t; + +/** + * @brief DAC output trigger select + */ +typedef enum { + DAC_TRIGGER_BY_DATA = 0U, /**< Channel is triggered by CHxDATA or COMBDATA write */ + DAC_TRIGGER_BY_PIS = 1U, /**< Channel is triggered by PIS input */ +} dac_trigger_t; + +/** + * @brief DAC interrupt type + */ +typedef enum { + DAC_IT_CH0 = (1U << 0), /**< Channel 0 conversion complete interrupt */ + DAC_IT_CH1 = (1U << 1), /**< Channel 1 conversion complete interrupt */ + DAC_IT_CH0_UF = (1U << 4), /**< Channel 0 data underflow interrupt */ + DAC_IT_CH1_UF = (1U << 5), /**< Channel 1 data underflow interrupt */ +} dac_it_t; + +/** + * @brief DAC interrupt flag type + */ +typedef enum { + DAC_FLAG_CH0 = (1U << 0), /**< Channel 0 conversion complete interrupt flag */ + DAC_FLAG_CH1 = (1U << 1), /**< Channel 1 conversion complete interrupt flag */ + DAC_FLAG_CH0_UF = (1U << 4), /**< Channel 0 data underflow interrupt flag */ + DAC_FLAG_CH1_UF = (1U << 5), /**< Channel 1 data underflow interrupt flag */ +} dac_flag_t; + +/** + * @brief DAC state flag + */ +typedef enum { + DAC_CH0_BSY = (1U << 0), /**< Channel_0 is BUSY */ + DAC_CH1_BSY = (1U << 1), /**< Channel_1 is BUSY */ +} dac_status_t; + +/** + * @brief DAC init structure definition + */ +typedef struct { + dac_conv_mode_t conv_mode; /**< Conversion mode */ + dac_out_mode_t out_mode; /**< Select output mode */ + dac_refresh_t refresh; /**< Refresh interval select */ + dac_prescale_div_t div; /**< Prescaler setting */ + type_func_t ch0_reset; /**< Select if prescaler is reset on channel 0 start */ + type_func_t o_ctrl_pis; /**< Enable pis control of dac output enable */ + type_func_t sine; /**< Sine mode enable/disable */ + type_func_t diff; /**< Differential mode enable/disable */ + dac_neg_ref_t n_ref; /**< The negative reference voltage select */ + dac_pos_ref_t p_ref; /**< The positive reference voltage select */ +} dac_init_t; + +/** + * @brief DAC channel initialize structure definition + */ +typedef struct { + type_func_t enable; /**< DAC channel output enable/disable */ + dac_trigger_t trigger; /**< Select channel conversion trigger */ + type_func_t refresh_en; /**< Set automatic refresh of channel function */ + dac_pissel_t pis_ch; /**< Select channel pis input channel */ +} dac_channel_config_t; + +/** + * @brief DAC handle Structure definition + */ +typedef struct dac_handle_s { + DAC_TypeDef *perh; /**< Register base address */ + dac_init_t init; /**< DAC initialize parameters */ + lock_state_t lock; /**< Locking object */ + + void (*cbk)(struct dac_handle_s *arg, uint32_t event); /**< DAC event callback */ +} dac_handle_t; +/** + * @} + */ + +/** @defgroup DAC_Public_Macros DAC Public Macros + * @{ + */ +#define DAC_CH0_ENABLE() (SET_BIT(DAC0->CH0CTRL, DAC_CH0CTRL_EN_MSK)) +#define DAC_CH1_ENABLE() (SET_BIT(DAC0->CH1CTRL, DAC_CH1CTRL_EN_MSK)) +#define DAC_CH0_DISABLE() (CLEAR_BIT(DAC0->CH0CTRL, DAC_CH0CTRL_EN_MSK)) +#define DAC_CH1_DISABLE() (CLEAR_BIT(DAC0->CH1CTRL, DAC_CH1CTRL_EN_MSK)) + +#define DAC_EVENT_CH0_CPLT 0x0 +#define DAC_EVENT_CH1_CPLT 0x1 +#define DAC_EVENT_CH0_UF 0x2 +#define DAC_EVENT_CH1_UF 0x3 +/** + * @} + */ + +/** @defgroup DAC_Private_Macros DAC Private Macros + * @{ + */ +#define IS_DAC_TYPE(x) ((x) == DAC0) +#define IS_DAC_CONVERT_TYPE(x) (((x) == DAC_CONV_MODE_CONTINUOUS) || \ + ((x) == DAC_CONV_MODE_SAMPLEHOLD) || \ + ((x) == DAC_CONV_MODE_SAMPLEOFF)) +#define IS_DAC_OUTPUT_TYPE(x) (((x) == DAC_OUTPUT_DISABLE) || \ + ((x) == DAC_OUTPUT_PIN) || \ + ((x) == DAC_OUTPUT_ADC) || \ + ((x) == DAC_OUTPUT_PIN_ADC)) +#define IS_DAC_NEG_REFRESH_TYPE(x) (((x) == DAC_NEG_REF_VSS) || \ + ((x) == DAC_NEG_REF_VREFN)) +#define IS_DAC_POS_REFRESH_TYPE(x) (((x) == DAC_POS_REF_VDD) || \ + ((x) == DAC_POS_REF_2V) || \ + ((x) == DAC_POS_REF_VREEFP) || \ + ((x) == DAC_POS_REF_VREEFP_BUF)) +#define IS_DAC_REFRESH_TYPE(x) (((x) == DAC_REFRESH_8) || \ + ((x) == DAC_REFRESH_16) || \ + ((x) == DAC_REFRESH_32) || \ + ((x) == DAC_REFRESH_64)) +#define IS_DAC_CHANNEL_TYPE(x) (((x) == DAC_CHANNEL_0) || \ + ((x) == DAC_CHANNEL_1) || \ + ((x) == DAC_CHANNEL_COMB)) +#define IS_DAC_PRESCALE_TYPE(x) (((x) == DAC_PRES_DIV_1) || \ + ((x) == DAC_PRES_DIV_2) || \ + ((x) == DAC_PRES_DIV_4) || \ + ((x) == DAC_PRES_DIV_8) || \ + ((x) == DAC_PRES_DIV_16) || \ + ((x) == DAC_PRES_DIV_32) || \ + ((x) == DAC_PRES_DIV_64) || \ + ((x) == DAC_PRES_DIV_128)) +#define IS_DAC_INTERRUPT_TYPE(x) (((x) == DAC_IT_CH0) || \ + ((x) == DAC_IT_CH1) || \ + ((x) == DAC_IT_CH0_UF) || \ + ((x) == DAC_IT_CH1_UF)) +#define IS_DAC_FLAG_TYPE(x) (((x) == DAC_FLAG_CH0) || \ + ((x) == DAC_FLAG_CH1) || \ + ((x) == DAC_FLAG_CH0_UF) || \ + ((x) == DAC_FLAG_CH1_UF)) +#define IS_DAC_PISSEL_CH_TYPE(x) (((x) == DAC_PIS_CH_0) || \ + ((x) == DAC_PIS_CH_1) || \ + ((x) == DAC_PIS_CH_2) || \ + ((x) == DAC_PIS_CH_3) || \ + ((x) == DAC_PIS_CH_4) || \ + ((x) == DAC_PIS_CH_5) || \ + ((x) == DAC_PIS_CH_6) || \ + ((x) == DAC_PIS_CH_7) || \ + ((x) == DAC_PIS_CH_8) || \ + ((x) == DAC_PIS_CH_9) || \ + ((x) == DAC_PIS_CH_10) || \ + ((x) == DAC_PIS_CH_11)) +#define IS_DAC_STATUS_TYPE(x) (((x) == DAC_CH0_BSY) || \ + ((x) == DAC_CH1_BSY)) +#define IS_DAC_TRIGGER_TYPE(x) (((x) == DAC_TRIGGER_BY_DATA) || \ + ((x) == DAC_TRIGGER_BY_PIS)) +/** + * @} + */ + +/** @addtogroup DAC_Public_Functions + * @{ + */ +ald_status_t ald_dac_reset(dac_handle_t *hperh); +ald_status_t ald_dac_init(dac_handle_t *hperh); +ald_status_t ald_dac_channel_config(dac_handle_t *hperh, dac_channel_config_t *config, dac_channel_t ch); +void ald_dac_output_set(dac_handle_t *hperh, dac_channel_t ch, uint32_t value); +flag_status_t ald_dac_get_status(dac_handle_t *hperh, dac_status_t status); +void ald_dac_interrupt_config(dac_handle_t *hperh, dac_it_t it, type_func_t state); +it_status_t ald_dac_get_it_status(dac_handle_t *hperh, dac_it_t it); +flag_status_t ald_dac_get_flag_status(dac_handle_t *hperh, dac_flag_t flag); +flag_status_t ald_dac_get_mask_flag_status(dac_handle_t *hperh, dac_flag_t flag); +void ald_dac_clear_flag_status(dac_handle_t *hperh, dac_flag_t flag); +void ald_dac_irq_handler(dac_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus + extern "C" } +#endif + +#endif /* __ALD_DAC_H */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_dbgc.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_dbgc.h new file mode 100644 index 00000000..fba87113 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_dbgc.h @@ -0,0 +1,172 @@ +/** + ********************************************************************************* + * + * @file ald_dbgc.h + * @brief DEBUGCON module driver. + * + * @version V1.0 + * @date 04 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 04 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_DBGC_H__ +#define __ALD_DBGC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup DBGC DBGC + * @brief DBGC module driver + * @{ + */ + + + +/** @defgroup DBGC_Public_Types DBGC Public Types + * @{ + */ +/** + * @brief Debug mode select + */ +typedef enum { + DEBC_MODE_SLEEP = (1U << 0), /**< Sleep mode */ + DEBC_MODE_STOP1 = (1U << 1), /**< STOP1 mode */ + DEBC_MODE_STOP2 = (1U << 2), /**< STOP2 mode */ + DEBC_MODE_STANDBY = (1U << 3), /**< Standby mode */ +} dbgc_mode_t; + +/** + * @brief Debug peripheral select + */ +typedef enum { + DEBC_PERH_TIMER0 = (1U << 0), /**< AD16C4T0 */ + DEBC_PERH_TIMER1 = (1U << 1), /**< BS16T0 */ + DEBC_PERH_TIMER2 = (1U << 2), /**< GP16C2T0 */ + DEBC_PERH_TIMER3 = (1U << 3), /**< GP16C2T1 */ + DEBC_PERH_TIMER4 = (1U << 4), /**< BS16T1 */ + DEBC_PERH_TIMER5 = (1U << 5), /**< BS16T2 */ + DEBC_PERH_TIMER6 = (1U << 6), /**< GP16C4T0 */ + DEBC_PERH_TIMER7 = (1U << 7), /**< BS16T3 */ + DEBC_PERH_I2C0 = (1U << 8), /**< I2C0 SMBUS */ + DEBC_PERH_I2C1 = (1U << 9), /**< I2C1 SMBUS */ + DEBC_PERH_CAN = (1U << 12), /**< CAN */ + DEBC_PERH_LPTIM0 = (1U << 0) | (1U << 16), /**< LPTIM0 */ + DEBC_PERH_IWDT = (1U << 8) | (1U << 16), /**< IWDT */ + DEBC_PERH_WWDT = (1U << 9) | (1U << 16), /**< WWDT */ + DEBC_PERH_RTC = (1U << 10) | (1U << 16), /**< RTC */ +} dbgc_perh_t; +/** + * @} + */ + +/** @defgroup DBGC_Public_Functions DBGC Public Functions + * @{ + */ +/** + * @brief Gets version. + * @retval Version + */ +__INLINE uint32_t ald_dbgc_get_rev_id(void) +{ + return (DBGC->IDCODE >> 16); +} + +/** + * @brief Gets core id. + * @retval Core id + */ +__INLINE uint32_t ald_dbgc_get_core_id(void) +{ + return (DBGC->IDCODE >> 12) & 0xF; +} + +/** + * @brief Gets device id + * @retval device id + */ +__INLINE uint32_t ald_dbgc_get_device_id(void) +{ + return DBGC->IDCODE & 0xFFF; +} + +/** + * @brief Configures low power debug mode + * @param mode: The mode of low power. + * @param state: ENABLE/DISABLE + * @retval None + */ +__INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state) +{ + if (state) + SET_BIT(DBGC->CR, mode); + else + CLEAR_BIT(DBGC->CR, mode); +} + +/** + * @brief Configures peripheral debug mode + * @param perh: The peripheral. + * @param state: ENABLE/DISABLE + * @retval None + */ +__INLINE void ald_dbgc_perh_config(dbgc_perh_t perh, type_func_t state) +{ + if ((perh >> 16) & 0x1) { + if (state) + SET_BIT(DBGC->APB2FZ, perh); + else + CLEAR_BIT(DBGC->APB2FZ, perh); + } + else { + if (state) + SET_BIT(DBGC->APB1FZ, perh); + else + CLEAR_BIT(DBGC->APB1FZ, perh); + } +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_dma.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_dma.h new file mode 100644 index 00000000..eca1ac21 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_dma.h @@ -0,0 +1,446 @@ +/** + ********************************************************************************* + * + * @file ald_dma.h + * @brief DMA module Library. + * + * @version V1.0 + * @date 09 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 09 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_DMA_H__ +#define __ALD_DMA_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** + * @defgroup DMA_Public_Macros DMA Public Macros + * @{ + */ +#define DMA_CH_COUNT 12U +#define DMA_ERR 31U +/** + * @} + */ + +/** + * @defgroup DMA_Public_Types DMA Public Types + * @{ + */ + +/** + * @brief Input source to DMA channel + * @verbatim + In this module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + 1. For ES32F36xx series: + TIMER0 ----> AD16C4T0 + TIMER1 ----> AD16C4T1 + TIMER2 ----> GP32C4T0 + TIMER3 ----> GP32C4T1 + TIMER4 ----> BS16T0 + TIMER5 ----> BS16T1 + TIMER6 ----> GP16C4T0 + TIMER7 ----> GP16C4T1 + + 2. For ES32F393x/ES32F336x/ES32F392x series: + TIMER0 ----> GP16C4T0 + TIMER1 ----> GP16C4T1 + TIMER2 ----> GP32C4T0 + TIMER3 ----> GP32C4T1 + TIMER4 ----> BS16T0 + TIMER5 ----> BS16T1 + TIMER6 ----> GP16C4T2 + TIMER7 ----> GP16C4T3 + @endverbatim + */ +typedef enum { + DMA_MSEL_NONE = 0x0U, /**< NONE */ + DMA_MSEL_GPIO = 0x1U, /**< GPIO */ + DMA_MSEL_CRYPT = 0x2U, /**< CRYPT */ + DMA_MSEL_DAC0 = 0x4U, /**< DAC0 */ + DMA_MSEL_ADC0 = 0x6U, /**< ADC0 */ + DMA_MSEL_CRC = 0x7U, /**< CRC */ + DMA_MSEL_UART0 = 0x8U, /**< UART0 */ + DMA_MSEL_UART1 = 0x9U, /**< UART1 */ + DMA_MSEL_UART2 = 0xAU, /**< UART2 */ + DMA_MSEL_UART3 = 0xBU, /**< UART3 */ + DMA_MSEL_UART4 = 0xCU, /**< UART4 */ + DMA_MSEL_UART5 = 0xDU, /**< UART5 */ + DMA_MSEL_SPI0 = 0xEU, /**< SPI0 */ + DMA_MSEL_SPI1 = 0xFU, /**< SPI1 */ + DMA_MSEL_I2C0 = 0x10U, /**< I2C0 */ + DMA_MSEL_I2C1 = 0x11U, /**< I2C1 */ + DMA_MSEL_TIMER0 = 0x12U, /**< TIMER0 */ + DMA_MSEL_TIMER1 = 0x13U, /**< TIMER1 */ + DMA_MSEL_TIMER2 = 0x14U, /**< TIMER2 */ + DMA_MSEL_TIMER3 = 0x15U, /**< TIMER3 */ + DMA_MSEL_LPUART0 = 0x18U, /**< LPUART0 */ + DMA_MSEL_SPI2 = 0x1AU, /**< SPI2 */ + DMA_MSEL_TIMER4 = 0x1BU, /**< TIMER4 */ + DMA_MSEL_TIMER5 = 0x1CU, /**< TIMER5 */ + DMA_MSEL_TIMER6 = 0x1DU, /**< TIMER6 */ + DMA_MSEL_TIMER7 = 0x1EU, /**< TIMER7 */ + DMA_MSEL_ADC1 = 0x1FU, /**< ADC1 */ + DMA_MSEL_PIS = 0x20U, /**< PIS */ + DMA_MSEL_TRNG = 0x21U, /**< TRNG */ + DMA_MSEL_QSPI = 0x22U, /**< QSPI */ + DMA_MSEL_USB = 0x23U, /**< USB */ +} dma_msel_t; + +/** + * @brief Input signal to DMA channel + */ +typedef enum { + DMA_MSIGSEL_NONE = 0x0U, /**< NONE */ + DMA_MSIGSEL_EXTI_0 = 0x0U, /**< External interrupt 0 */ + DMA_MSIGSEL_EXTI_1 = 0x1U, /**< External interrupt 1 */ + DMA_MSIGSEL_EXTI_2 = 0x2U, /**< External interrupt 2 */ + DMA_MSIGSEL_EXTI_3 = 0x3U, /**< External interrupt 3 */ + DMA_MSIGSEL_EXTI_4 = 0x4U, /**< External interrupt 4 */ + DMA_MSIGSEL_EXTI_5 = 0x5U, /**< External interrupt 5 */ + DMA_MSIGSEL_EXTI_6 = 0x6U, /**< External interrupt 6 */ + DMA_MSIGSEL_EXTI_7 = 0x7U, /**< External interrupt 7 */ + DMA_MSIGSEL_EXTI_8 = 0x8U, /**< External interrupt 8 */ + DMA_MSIGSEL_EXTI_9 = 0x9U, /**< External interrupt 9 */ + DMA_MSIGSEL_EXTI_10 = 0xAU, /**< External interrupt 10 */ + DMA_MSIGSEL_EXTI_11 = 0xBU, /**< External interrupt 11 */ + DMA_MSIGSEL_EXTI_12 = 0xCU, /**< External interrupt 12 */ + DMA_MSIGSEL_EXTI_13 = 0xDU, /**< External interrupt 13 */ + DMA_MSIGSEL_EXTI_14 = 0xEU, /**< External interrupt 14 */ + DMA_MSIGSEL_EXTI_15 = 0xFU, /**< External interrupt 15 */ + DMA_MSIGSEL_CRYPT_WRITE = 0x0U, /**< CRYPT write mode */ + DMA_MSIGSEL_CRYPT_READ = 0x1U, /**< CRYPT read mode */ + DMA_MSIGSEL_DAC0_CH0 = 0x0U, /**< DAC0 channel 0 complete */ + DMA_MSIGSEL_DAC0_CH1 = 0x1U, /**< DAC0 channel 1 complete */ + DMA_MSIGSEL_ADC = 0x0U, /**< ADC mode */ + DMA_MSIGSEL_UART_TXEMPTY = 0x0U, /**< UART0/UART1/UART2/UART3 transmit */ + DMA_MSIGSEL_UART_RNR = 0x1U, /**< UART0/UART1/UART2/UART3 receive */ + DMA_MSIGSEL_UART45_RNR = 0x0U, /**< UART4/UART5 reveive */ + DMA_MSIGSEL_UART45_TXEMPTY = 0x1U, /**< UART4/UART5 transmit */ + DMA_MSIGSEL_SPI_RNR = 0x0U, /**< SPI receive */ + DMA_MSIGSEL_SPI_TXEMPTY = 0x1U, /**< SPI transmit */ + DMA_MSIGSEL_I2C_RNR = 0x0U, /**< I2C receive */ + DMA_MSIGSEL_I2C_TXEMPTY = 0x1U, /**< I2C transmit */ + DMA_MSIGSEL_TIMER_CH1 = 0x0U, /**< TIM channal 1 */ + DMA_MSIGSEL_TIMER_CH2 = 0x1U, /**< TIM channal 2 */ + DMA_MSIGSEL_TIMER_CH3 = 0x2U, /**< TIM channal 3 */ + DMA_MSIGSEL_TIMER_CH4 = 0x3U, /**< TIM channal 4 */ + DMA_MSIGSEL_TIMER_TRI = 0x4U, /**< TIM trigger */ + DMA_MSIGSEL_TIMER_COMP = 0x5U, /**< TIM compare */ + DMA_MSIGSEL_TIMER_UPDATE = 0x6U, /**< TIM update */ + DMA_MSIGSEL_LPUART_RNR = 0x0U, /**< LPUART receive */ + DMA_MSIGSEL_LPUART_TXEMPTY = 0x1U, /**< LPUART transmit */ + DMA_MSIGSEL_PIS_CH0 = 0x0U, /**< PIS channal 0 */ + DMA_MSIGSEL_PIS_CH1 = 0x1U, /**< PIS channal 1 */ + DMA_MSIGSEL_PIS_CH2 = 0x2U, /**< PIS channal 2 */ + DMA_MSIGSEL_PIS_CH3 = 0x3U, /**< PIS channal 3 */ + DMA_MSIGSEL_PIS_CH4 = 0x4U, /**< PIS channal 4 */ + DMA_MSIGSEL_PIS_CH5 = 0x5U, /**< PIS channal 5 */ + DMA_MSIGSEL_PIS_CH6 = 0x6U, /**< PIS channal 6 */ + DMA_MSIGSEL_PIS_CH7 = 0x7U, /**< PIS channal 7 */ + DMA_MSIGSEL_PIS_CH8 = 0x8U, /**< PIS channal 8 */ + DMA_MSIGSEL_PIS_CH9 = 0x9U, /**< PIS channal 9 */ + DMA_MSIGSEL_PIS_CH10 = 0xAU, /**< PIS channal 10 */ + DMA_MSIGSEL_PIS_CH11 = 0xBU, /**< PIS channal 11 */ + DMA_MSIGSEL_PIS_CH12 = 0xCU, /**< PIS channal 12 */ + DMA_MSIGSEL_PIS_CH13 = 0xDU, /**< PIS channal 13 */ + DMA_MSIGSEL_PIS_CH14 = 0xEU, /**< PIS channal 14 */ + DMA_MSIGSEL_PIS_CH15 = 0xFU, /**< PIS channal 15 */ + DMA_MSIGSEL_QSPI_WRITE = 0x0U, /**< QSPI Write */ + DMA_MSIGSEL_QSPI_READ = 0x1U, /**< QSPI Read */ + DMA_MSIGSEL_EP_TX1 = 0x0U, /**< USB TX Endport 0 */ + DMA_MSIGSEL_EP_TX2 = 0x1U, /**< USB TX Endport 1 */ + DMA_MSIGSEL_EP_TX3 = 0x2U, /**< USB TX Endport 2 */ + DMA_MSIGSEL_EP_TX4 = 0x3U, /**< USB TX Endport 3 */ + DMA_MSIGSEL_EP_TX5 = 0x4U, /**< USB TX Endport 4 */ + DMA_MSIGSEL_EP_RX1 = 0x8U, /**< USB RX Endport 0 */ + DMA_MSIGSEL_EP_RX2 = 0x9U, /**< USB RX Endport 1 */ + DMA_MSIGSEL_EP_RX3 = 0xAU, /**< USB RX Endport 2 */ + DMA_MSIGSEL_EP_RX4 = 0xBU, /**< USB RX Endport 3 */ + DMA_MSIGSEL_EP_RX5 = 0xCU, /**< USB RX Endport 4 */ +} dma_msigsel_t; + +/** + * @brief DMA Descriptor control type + */ +typedef union { + struct { + uint32_t cycle_ctrl :3; /**< DMA operating mode @ref dma_cycle_ctrl_t */ + uint32_t next_useburst :1; /**< Uses the alternate data structure when complete a DMA cycle */ + uint32_t n_minus_1 :10; /**< Represent the total number of DMA transfers that DMA cycle contains. */ + uint32_t R_power :4; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ + uint32_t src_prot_ctrl :3; /**< Control the state of HPROT when reads the source data. */ + uint32_t dst_prot_ctrl :3; /**< Control the state of HPROT when writes the destination data */ + uint32_t src_size :2; /**< Source data size @ref dma_data_size_t */ + uint32_t src_inc :2; /**< Control the source address increment. @ref dma_data_inc_t */ + uint32_t dst_size :2; /**< Destination data size. @ref dma_data_size_t */ + uint32_t dst_inc :2; /**< Destination address increment. @ref dma_data_inc_t */ + }; + uint32_t word; +} dma_ctrl_t; + +/** + * @brief Channel control data structure + */ +typedef struct { + void *src; /**< Source data end pointer */ + void *dst; /**< Destination data end pointer */ + dma_ctrl_t ctrl; /**< Control data configuration @ref dma_ctrl_t */ + uint32_t use; /**< Reserve for user */ +} dma_descriptor_t; + +/** + * @brief data increment + */ +typedef enum { + DMA_DATA_INC_BYTE = 0x0U, /**< Address increment by byte */ + DMA_DATA_INC_HALFWORD = 0x1U, /**< Address increment by halfword */ + DMA_DATA_INC_WORD = 0x2U, /**< Address increment by word */ + DMA_DATA_INC_NONE = 0x3U, /**< No increment */ +} dma_data_inc_t; + +/** + * @brief Data size + */ +typedef enum { + DMA_DATA_SIZE_BYTE = 0x0U, /**< Byte */ + DMA_DATA_SIZE_HALFWORD = 0x1U, /**< Halfword */ + DMA_DATA_SIZE_WORD = 0x2U, /**< Word */ +} dma_data_size_t; + +/** + * @brief The operating mode of the DMA cycle + */ +typedef enum { + DMA_CYCLE_CTRL_NONE = 0x0U, /**< Stop */ + DMA_CYCLE_CTRL_BASIC = 0x1U, /**< Basic */ + DMA_CYCLE_CTRL_AUTO = 0x2U, /**< Auto-request */ + DMA_CYCLE_CTRL_PINGPONG = 0x3U, /**< Ping-pong */ + DMA_CYCLE_CTRL_MEM_SG_PRIMARY = 0x4U, /**< Memory scatter-gather using the primary structure */ + DMA_CYCLE_CTRL_MEM_SG_ALTERNATE = 0x5U, /**< Memory scatter-gather using the alternate structure */ + DMA_CYCLE_CTRL_PER_SG_PRIMARY = 0x6U, /**< Peripheral scatter-gather using the primary structure */ + DMA_CYCLE_CTRL_PER_SG_ALTERNATE = 0x7U, /**< Peripheral scatter-gather using the alternate structure */ +} dma_cycle_ctrl_t; + +/** + * @brief Control how many DMA transfers can occur + * before the controller re-arbitrates + */ +typedef enum { + DMA_R_POWER_1 = 0x0U, /**< Arbitrates after each DMA transfer */ + DMA_R_POWER_2 = 0x1U, /**< Arbitrates after 2 DMA transfer */ + DMA_R_POWER_4 = 0x2U, /**< Arbitrates after 4 DMA transfer */ + DMA_R_POWER_8 = 0x3U, /**< Arbitrates after 8 DMA transfer */ + DMA_R_POWER_16 = 0x4U, /**< Arbitrates after 16 DMA transfer */ + DMA_R_POWER_32 = 0x5U, /**< Arbitrates after 32 DMA transfer */ + DMA_R_POWER_64 = 0x6U, /**< Arbitrates after 64 DMA transfer */ + DMA_R_POWER_128 = 0x7U, /**< Arbitrates after 128 DMA transfer */ + DMA_R_POWER_256 = 0x8U, /**< Arbitrates after 256 DMA transfer */ + DMA_R_POWER_512 = 0x9U, /**< Arbitrates after 512 DMA transfer */ + DMA_R_POWER_1024 = 0xAU, /**< Arbitrates after 1024 DMA transfer */ +} dma_arbiter_config_t; + +/** + * @brief Callback function pointer and param + */ +typedef struct { + void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*err_cbk)(void* arg); /**< DMA occurs error callback */ + void *cplt_arg; /**< The parameter of cplt_cbk() */ + void *err_arg; /**< The parameter of err_cbk() */ +} dma_call_back_t; + +/** + * @brief DMA channal configure structure + */ +typedef struct { + void *src; /**< Source data begin pointer */ + void *dst; /**< Destination data begin pointer */ + uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */ + dma_data_size_t data_width; /**< Data width, @ref dma_data_size_t */ + dma_data_inc_t src_inc; /**< Source increment type. @ref dma_data_inc_t */ + dma_data_inc_t dst_inc; /**< Destination increment type. @ref dma_data_inc_t */ + dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */ + type_func_t primary; /**< Use primary descriptor or alternate descriptor */ + type_func_t burst; /**< Enable/Disable the useburst setting for this channel */ + type_func_t high_prio; /**< High priority or default priority */ + type_func_t interrupt; /**< Enable/disable interrupt */ + dma_msel_t msel; /**< Input source to DMA channel @ref dma_msel_t */ + dma_msigsel_t msigsel; /**< Input signal to DMA channel @ref dma_msigsel_t */ + uint8_t channel; /**< Channel index */ +} dma_config_t; + +/** + * @brief DMA handle structure definition + */ +typedef struct { + DMA_TypeDef *perh; /**< DMA registers base address */ + dma_config_t config; /**< Channel configure structure. @ref dma_config_t */ + void (*cplt_cbk)(void *arg); /**< DMA transfers complete callback */ + void (*err_cbk)(void *arg); /**< DMA bus occurs error callback */ + void *cplt_arg; /**< The parameter of cplt_cbk() */ + void *err_arg; /**< The parameter of err_cbk() */ +} dma_handle_t; + +/** + * @brief Descriptor complete state + */ +typedef enum { + DMA_DESCP_CPLT_PRI = 0x0U, /**< Primary descriptor has been completed */ + DMA_DESCP_CPLT_ALT = 0x1U, /**< Alternate descriptor has been completed */ + DMA_DESCP_CPLT_ALL = 0x2U, /**< Both primary and alternate descriptors have been completed */ +} dma_descrp_cplt_t; +/** + * @} + */ + +/** + * @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ +#define IS_DMA_MSEL_TYPE(x) ((x) <= DMA_MSEL_USB) +#define IS_DMA_MSIGSEL_TYPE(x) ((x) <= 0xF) +#define IS_DMA_DATAINC_TYPE(x) (((x) == DMA_DATA_INC_BYTE) || \ + ((x) == DMA_DATA_INC_HALFWORD) || \ + ((x) == DMA_DATA_INC_WORD) || \ + ((x) == DMA_DATA_INC_NONE)) +#define IS_DMA_DATASIZE_TYPE(x) (((x) == DMA_DATA_SIZE_BYTE) || \ + ((x) == DMA_DATA_SIZE_HALFWORD) || \ + ((x) == DMA_DATA_SIZE_WORD)) +#define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \ + ((x) == DMA_CYCLE_CTRL_BASIC) || \ + ((x) == DMA_CYCLE_CTRL_AUTO) || \ + ((x) == DMA_CYCLE_CTRL_PINGPONG) || \ + ((x) == DMA_CYCLE_CTRL_MEM_SG_PRIMARY) || \ + ((x) == DMA_CYCLE_CTRL_MEM_SG_ALTERNATE) || \ + ((x) == DMA_CYCLE_CTRL_PER_SG_PRIMARY) || \ + ((x) == DMA_CYCLE_CTRL_PER_SG_ALTERNATE)) +#define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \ + ((x) == DMA_R_POWER_2) || \ + ((x) == DMA_R_POWER_4) || \ + ((x) == DMA_R_POWER_8) || \ + ((x) == DMA_R_POWER_16) || \ + ((x) == DMA_R_POWER_32) || \ + ((x) == DMA_R_POWER_64) || \ + ((x) == DMA_R_POWER_128) || \ + ((x) == DMA_R_POWER_256) || \ + ((x) == DMA_R_POWER_512) || \ + ((x) == DMA_R_POWER_1024)) +#define IS_DMA(x) ((x) == DMA0) +#define IS_DMA_CHANNEL(x) ((x) <= 11) +#define IS_DMA_DATA_SIZE(x) ((x) <= 1024) +#define IS_DMA_IT_TYPE(x) (((x) <= 11) || ((x) == 31)) +/** + * @} + */ + +/** + * @addtogroup DMA_Public_Functions + * @{ + */ + +/** @addtogroup DMA_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +extern void ald_dma_reset(DMA_TypeDef *DMAx); +extern void ald_dma_init(DMA_TypeDef *DMAx); +extern void ald_dma_config_struct(dma_config_t *p); +extern void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory); +/** + * @} + */ + + +/** @addtogroup DMA_Public_Functions_Group2 + * @{ + */ +/* Configure DMA channel functions */ +extern void ald_dma_config_auto(dma_handle_t *hperh); +extern void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size); +extern void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, + uint16_t size, uint8_t channel, void (*cbk)(void *arg)); +extern void ald_dma_config_basic(dma_handle_t *hperh); +extern void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size); +extern void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, + dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); +extern void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config, + uint8_t first, void (*cbk)(void *arg)); +extern void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc, + uint32_t nr, uint8_t channel, void (*cbk)(void *arg)); +extern void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst, + dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)); +/** + * @} + */ + +/** @addtogroup DMA_Public_Functions_Group3 + * @{ + */ +/* DMA control functions */ +extern void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); +extern void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state); +extern it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel); +extern flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel); +extern void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel); +extern dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel); +extern void ald_dma_irq_handler(void); +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__ALD_DMA_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_ebi.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_ebi.h new file mode 100644 index 00000000..cdf1c297 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_ebi.h @@ -0,0 +1,602 @@ +/** + ********************************************************************************* + * + * @file ald_ebi.h + * @brief Header file of EBI module driver. + * + * @version V1.0 + * @date 20 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 20 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + + +#ifndef __ALD_EBI_H__ +#define __ALD_EBI_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup EBI + * @{ + */ + +/** + * @defgroup EBI_Public_Macros EBI Public Macros + * @{ + */ +#define EBI_NOR_SRAM_TypeDef EBI_Bank1_TypeDef +#define EBI_NOR_SRAM_EXTENDED_TypeDef EBI_Bank1E_TypeDef +#define EBI_NAND_TypeDef EBI_Bank2_3_TypeDef +#define EBI_LCD_TypeDef EBI_Bank1_LCD_TypeDef +#define EBI_NOR_SRAM_DEVICE EBI_Bank1 +#define EBI_NOR_SRAM_EXTENDED_DEVICE EBI_Bank1E +#define EBI_NAND_DEVICE EBI_Bank2_3 +#define EBI_LCD_DEVICE EBI_Bank1_LCD +#define EBI_NAND_BANK2 0x00000010U +#define EBI_NAND_BANK3 0x00000100U + +/* PCTRLR register clear mask */ +#define PCTRLR_CLEAR_MASK ((uint32_t)(EBI_PCTRLRx_WAITEN_MSK | EBI_PCTRLRx_MEMBKEN_MSK | \ + EBI_PCTRLRx_MEMTYP_MSK | EBI_PCTRLRx_DATBUSWID_MSK | \ + EBI_PCTRLRx_ECCEN_MSK | EBI_PCTRLRx_CRDLY_MSK | \ + EBI_PCTRLRx_ARDLY_MSK | EBI_PCTRLRx_ECCPSIZE_MSK)) + +/* PMEMR register clear mask */ +#define PMEMR_CLEAR_MASK ((uint32_t)(EBI_PMEMRx_MEMSETUP_MSK | EBI_PMEMRx_MEMWAIT_MSK | \ + EBI_PMEMRx_MEMHOLD_MSK | EBI_PMEMRx_MEMHIZT_MSK)) + +/* PATTR register clear mask */ +#define PATTR_CLEAR_MASK ((uint32_t)(EBI_PATTRx_ATTSETUP_MSK | EBI_PATTRx_ATTWAIT_MSK | \ + EBI_PATTRx_ATTHOLD_MSK | EBI_PATTRx_ATTHIZT_MSK)) + +/* BCTRLR register clear mask */ +#define BCTRLR_CLEAR_MASK ((uint32_t)(EBI_BCTRLRx_FLASHACCEN_MSK | EBI_BCTRLRx_MUXEN_MSK | \ + EBI_BCTRLRx_MEMTYP_MSK | EBI_BCTRLRx_MEMWID_MSK | \ + EBI_BCTRLRx_BURSTEN_MSK | EBI_BCTRLRx_WAITPOL_MSK | \ + EBI_BCTRLRx_WRAPMODE_MSK | EBI_BCTRLRx_WAITCFG_MSK | \ + EBI_BCTRLRx_WREN_MSK | EBI_BCTRLRx_WAITEN_MSK | \ + EBI_BCTRLRx_EXTMODEN_MSK | EBI_BCTRLRx_ASYNCWAIT_MSK | \ + EBI_BCTRLRx_RWCBURSTEN_MSK)) +/* BTR register clear mask */ +#define BTR_CLEAR_MASK ((uint32_t)(EBI_BTRx_ADDATASETUP_MSK | EBI_BTRx_ADDHOLD_MSK | \ + EBI_BTRx_DATAHOLD_MSK | EBI_BTRx_BUSTURN_MSK | \ + EBI_BTRx_CLKDIV_MSK | EBI_BTRx_DATALAT_MSK | \ + EBI_BTRx_ACCMODE_MSK)) + +/* BWRTR register clear mask */ +#define BWTR_CLEAR_MASK ((uint32_t)(EBI_BWRTRx_ADDATASETUP_MSK | EBI_BWRTRx_ADDHOLD_MSK | \ + EBI_BWRTRx_DATAHOLD_MSK | EBI_BWRTRx_BUSTURN_MSK | \ + EBI_BWRTRx_ACCMODE_MSK)) + +#define LCDCTRL_CLEAR_MASK ((uint32_t)(EBI_LCDCTRLx_HSYNCPOL_POS | EBI_LCDCTRLx_VSYNCPOL_MSK | \ + EBI_LCDCTRLx_DENPOL_MSK | EBI_LCDCTRLx_LCDEN_MSK | \ + EBI_LCDCTRLx_LCDINT_MSK | EBI_LCDCTRLx_DCLKPOL_MSK | \ + EBI_LCDCTRLx_DATASETUP_MSK)) +/** + * @} + */ + +/** @defgroup EBI_Public_Types EBI Public Types + * @{ + */ + +/** + * @brief EBI Access Mode + */ +typedef enum { + EBI_ACCESS_MODE_A = 0x0U, /**< EBI access mode A */ + EBI_ACCESS_MODE_B = (0x1U << 28), /**< EBI access mode B */ + EBI_ACCESS_MODE_C = (0x2U << 28), /**< EBI access mode C */ + EBI_ACCESS_MODE_D = (0x3U << 28), /**< EBI access mode D */ +} ebi_access_mode_t; + +/** + * @brief EBI NORSRAM Timing parameters structure definition + */ +typedef struct { + uint32_t addr_setup; /**< Address setup HCLK cycles number, the value between 0 and 15 */ + uint32_t addr_hold; /**< Address hold HCLK cycles number, the value between 0 and 15 */ + uint32_t data_setup; /**< Data setup HCLK cycles number, the value between 1 and 255 */ + uint32_t bus_dur; /**< Bus turnaround duration HCLK cycles, the value between 0 and 15 */ + uint32_t div; /**< Defines the period of CLK clock signal, the value between 2 and 16 */ + uint32_t latency; /**< Issue clock cycles before getting the first data, the value between 2 and 17 */ + ebi_access_mode_t mode; /**< Specifies the asynchronous access mode */ +} ald_ebi_nor_sram_timing_t; + +/** + * @brief EBI_Wait_feature EBI Wait feature + */ +typedef enum { + EBI_NAND_WAIT_FEATURE_DISABLE = 0x0U, /**< NAND wait feature disable */ + EBI_NAND_WAIT_FEATURE_ENABLE = (0x1U << 1), /**< NAND wait feature enable */ +} ebi_nand_wait_feature_t; + +/** + * @brief EBI NAND Data Width + */ +typedef enum { + EBI_NAND_MEM_BUS_WIDTH_8 = 0x0U, /**< NAND mem bus width 8-bits */ + EBI_NAND_MEM_BUS_WIDTH_16 = (0x3U << 4), /**< NAND mem bus width 16-bits */ +} ebi_nand_mem_bus_width_t; + +/** + * @brief EBI NAND ECC STATE + */ +typedef enum { + EBI_NAND_ECC_DISABLE = 0U, /**< NAND ecc disable */ + EBI_NAND_ECC_ENABLE = (0x1U << 6), /**< NAND ecc enable */ +} ebi_nand_ecc_t; + +/** + * @brief EBI ECC Page Size + */ +typedef enum { + EBI_NAND_ECC_PAGE_SIZE_256BYTE = 0U, /**< NAND ecc page size 256 bytes */ + EBI_NAND_ECC_PAGE_SIZE_512BYTE = (0x1U << 17), /**< NAND ecc page size 512 bytes */ + EBI_NAND_ECC_PAGE_SIZE_1024BYTE = (0x2U << 17), /**< NAND ecc page size 1024 bytes */ + EBI_NAND_ECC_PAGE_SIZE_2048BYTE = (0x3U << 17), /**< NAND ecc page size 2048 bytes */ + EBI_NAND_ECC_PAGE_SIZE_4096BYTE = (0x4U << 17), /**< NAND ecc page size 4096 bytes */ + EBI_NAND_ECC_PAGE_SIZE_8192BYTE = (0x5U << 17), /**< NAND ecc page size 8192 bytes */ +} ebi_md_ecc_page_size_t; + +/** + * @brief EBI NAND Configuration Structure definition + */ +typedef struct { + uint32_t bank; /**< Specifies the NAND memory device that will be used */ + ebi_nand_wait_feature_t wait; /**< Enables or disables the Wait feature for the NAND Memory device */ + ebi_nand_mem_bus_width_t width; /**< Specifies the external memory device width */ + ebi_nand_ecc_t ecc; /**< Enables or disables the ECC computation */ + ebi_md_ecc_page_size_t size; /**< Defines the page size for the extended ECC */ + uint32_t cle_time; /**< Number of HCLK cycles between CLE low and RE low, the value between 0 and 255 */ + uint32_t ale_time; /**< Number of HCLK cycles between ALE low and RE low */ +} ald_ebi_nand_init_t; + +/** + * @brief EBI NAND Timing parameters structure definition + */ +typedef struct { + uint32_t time; /**< Number of cycles to setup address, the value between 0 and 255 */ + uint32_t wait_time; /**< Number of HCLK cycles to assert the command ,the value between 0 and 255 */ + uint32_t hold_time; /**< Number of HCLK cycles to hold address or data, the value between 0 and 255 */ + uint32_t hiz_time; /**< Number of HCLK cycles data bus is kept in HiZ, the value between 0 and 255 */ +} ald_ebi_nand_timing_t; + +/** + * @brief EBI Data Address Bus Multiplexing + */ +typedef enum { + EBI_DATA_ADDRESS_MUX_DISABLE = 0x0U, /**< Data address mux disable */ + EBI_DATA_ADDRESS_MUX_ENABLE = (0x1U << 1), /**< Data address mux enable */ +} ebi_data_address_mux_t; + +/** + * @brief EBI NOR/SRAM Bank + */ +typedef enum { + EBI_NORSRAM_BANK1 = 0x0U, /**< Norsram bank 1 */ + EBI_NORSRAM_BANK2 = 0x2U, /**< Norsram bank 2 */ + EBI_NORSRAM_BANK3 = 0x4U, /**< Norsram bank 3 */ + EBI_NORSRAM_BANK4 = 0x6U, /**< Norsram bank 4 */ +} ebi_norsram_bank_t; + +/** + * @brief EBI Memory Type + */ +typedef enum { + EBI_MEMORY_TYPE_SRAM = 0x0U, /**< Memory tyepe SRAM */ + EBI_MEMORY_TYPE_PSRAM = (0x1U << 2), /**< Memory tyepe PSRAM */ + EBI_MEMORY_TYPE_NOR = (0x2U << 2), /**< Memory tyepe NOR */ +} ebi_memory_type_t; + +/** + * @brief EBI NOR/SRAM Data Width + */ +typedef enum { + EBI_NORSRAM_MEM_BUS_WIDTH_8 = 0x0U, /**< Norsram Memory width 8-bits */ + EBI_NORSRAM_MEM_BUS_WIDTH_16 = (0x1U << 4), /**< Norsram Memory width 16-bits */ + EBI_NORSRAM_MEM_BUS_WIDTH_32 = (0x2U << 4), /**< Norsram Memory width 32-bits */ +} ebi_norsram_mem_bus_width_t; + +/** + * @brief EBI NOR/SRAM Flash Access + */ +typedef enum { + EBI_NORSRAM_FLASH_ACCESS_DISABLE = 0x0U, /**< Norsram flash access disable */ + EBI_NORSRAM_FLASH_ACCESS_ENABLE = (0x1U << 6), /**< Norsram flash access enable */ +} ebi_norsram_flash_access_t; + +/** + * @brief EBI Burst Access Mode + */ +typedef enum { + EBI_BURST_ACCESS_MODE_DISABLE = 0x0U, /**< Burst access disable */ + EBI_BURST_ACCESS_MODE_ENABLE = (0x1U << 8), /**< Burst access enable */ +} ebi_burst_access_mode_t; + +/** + * @brief EBI Wait Signal Polarity + */ +typedef enum { + EBI_WAIT_SIGNAL_POLARITY_LOW = 0x0U, /**< Wait signal polarity low */ + EBI_WAIT_SIGNAL_POLARITY_HIGH = (0x1U << 9), /**< Wait signal polarity high */ +} ebi_wait_signal_polarity_t; + +/** + * @brief EBI Wrap Mode + */ +typedef enum { + EBI_WRAP_MODE_DISABLE = 0x0U, /**< Wrap mode disable */ + EBI_WRAP_MODE_ENABLE = (0x1U << 10), /**< Wrap mode enable */ +} ebi_wrap_mode_t; + +/** + * @brief EBI Wait Timing + */ +typedef enum { + EBI_WAIT_TIMING_BEFORE_WS = 0x0U, /**< Wait timing before ws */ + EBI_WAIT_TIMING_DURING_WS = (0x1U << 11), /**< Wait timing during ws */ +} ebi_wait_timing_t; + +/** + * @brief EBI Write Operation State + */ +typedef enum { + EBI_WRITE_OPERATION_DISABLE = 0x0U, /**< Write operation disable */ + EBI_WRITE_OPERATION_ENABLE = (0x1U << 12), /**< Write operation enable */ +} ebi_write_operation_t; + +/** + * @brief EBI Wait Signal + */ +typedef enum { + EBI_WAIT_SIGNAL_DISABLE = 0x0U, /**< Wait signal disable */ + EBI_WAIT_SIGNAL_ENABLE = (0x1U << 13), /**< Wait signal enable */ +} ebi_wait_signal_t; + +/** + * @brief EBI Extended Mode + */ +typedef enum { + EBI_EXTENDED_MODE_DISABLE = 0x0U, /**< EBI extended mode disable */ + EBI_EXTENDED_MODE_ENABLE = (0x1U << 14), /**< EBI extended mode enable */ +} ebi_extended_mode_t; + +/** + * @brief EBI Asynchronous Wait + */ +typedef enum { + EBI_ASYNCHRONOUS_WAIT_DISABLE = 0x0U, /**< Asynchronous wait disable */ + EBI_ASYNCHRONOUS_WAIT_ENABLE = (0x1U << 15), /**< Asynchronous wait enable */ +} ebi_asynchronous_wait_t; + +/** + * @brief EBI Write Burst + */ +typedef enum { + EBI_WRITE_BURST_DISABLE = 0x0U, /**< Write burst disable */ + EBI_WRITE_BURST_ENABLE = (0x1U << 19), /**< Write burst enable */ +} ebi_write_burst_t; + +/** + * @brief EBI PCR Memory Type + */ +typedef enum { + EBI_PCTRLR_MEMORY_TYPE_None = 0x0U, /**< PCR memory type none */ + EBI_PCTRLR_MEMORY_TYPE_NAND = (0x1U << 3), /**< PCR memory type nand */ +} ebi_pctrlr_memory_type_t; + +/** + * @brief EBI Interrupt definition + */ +typedef enum { + EBI_IT_RISING_EDGE = (1U << 3), /**< Rising edge trigger interrupt */ + EBI_IT_LEVEL = (1U << 4), /**< Level trigger interrupt */ + EBI_IT_FALLING_EDGE = (1U << 5), /**< Falling edge trigger interrupt */ +} ebi_it_t; + +/** + * @brief EBI Flag definition + */ +typedef enum { + EBI_FLAG_RISING_EDGE = (1U << 0), /**< Rising edge flag */ + EBI_FLAG_LEVEL = (1U << 1), /**< Level flag */ + EBI_FLAG_FALLING_EDGE = (1U << 2), /**< Falling edge flag */ + EBI_FLAG_FEMPT = (1U << 6), /**< Rising edge trigger interrupt */ +} ebi_flag_t; + +/** + * @brief EBI LCD_Horizontal Synch Polarity definition + */ +typedef enum { + EBI_LCD_HSYNCPOL_LOW = 0x0U, /**< Horizontal synch polarity low */ + EBI_LCD_HSYNCPOL_HIGH = (0x1U << 29), /**< Horizontal synch polarity high */ +} ebi_lcd_hsyncpol_t; + +/** + * @brief EBI LCD Vertical Synch Polarity definition + */ +typedef enum { + EBI_LCD_VSYNCPOL_LOW = 0x0U, /**< Vertical synch polarity low */ + EBI_LCD_VSYNCPOL_HIGH = (0x1U << 28), /**< Vertical synch polarity high */ +} ebi_lcd_vsyncpol_t; + +/** + * @brief EBI LCD Data Enable Polarity definition + */ +typedef enum { + EBI_LCD_DENPOL_LOW = 0x0U, /**< LCD data enable polarity low */ + EBI_LCD_DENPOL_HIGH = (0x1U << 27), /**< LCD data enable polarity high */ +} ebi_lcd_denpol_t; + +/** + * @brief EBI LCD Enable definition + */ +typedef enum { + EBI_LCD_LCDEN_DISABLE = 0x0U, /**< LCD disable */ + EBI_LCD_LCDEN_ENABLE = (0x1U << 26), /**< LCD data enable polarity low */ +} ebi_lcd_lcden_t; + +/** + * @brief EBI LCD Init Enable definition + */ +typedef enum { + EBI_LCD_LCDINT_DISABLE = 0x0U, /**< LCD init disable */ + EBI_LCD_LCDINT_ENABLE = (0x1 << 25), /**< LCD init enable */ +} ebi_lcd_lcdint_t; + +/** + * @brief EBI LCD Data Clock definition + */ +typedef enum { + EBI_LCD_DCLKPOL_FALLING = 0x0U, /**< LCD data clock falling edge */ + EBI_LCD_DCLKPOL_RISING = (0x1U << 24), /**< LCD data clock rising edge */ +} ebi_lcd_dclkpol_t; + +/** + * @brief EBI LCD parameters structure definition + */ +typedef struct { + uint8_t bank; /**< Specifies the NORSRAM memory device */ + ebi_lcd_hsyncpol_t h_polarity; /**< Horizontal sync polarity */ + ebi_lcd_vsyncpol_t v_polarity; /**< Vertical sync polarity */ + ebi_lcd_denpol_t data_polarity; /**< Data enable polarity */ + ebi_lcd_lcden_t enable; /**< LCD enable */ + ebi_lcd_dclkpol_t clk_polarity; /**< Data clock polarity */ + ebi_lcd_lcdint_t reset; /**< LCD Reset */ + uint8_t setup; /**< Data setup time */ + uint8_t v_width; /**< Vsync pulse width */ + uint8_t h_width; /**< Hsync puluse width */ + uint16_t nr_line; /**< Frame line number */ + uint16_t nr_pixel; /**< Frame pixel number */ +} ebi_lcd_init_t; + +/** + * @brief NOR LCD handle Structure definition + */ +typedef struct { + EBI_LCD_TypeDef *inst; + ebi_lcd_init_t init; +} ebi_lcd_handle_t; + +/** + * @brief EBI NORSRAM Configuration Structure definition + */ +typedef struct { + uint32_t bank; /**< Specifies the NORSRAM memory device, the value can be one of 0 ~ 3 */ + ebi_data_address_mux_t mux; /**< Address and data values are multiplexed or not */ + ebi_memory_type_t type; /**< Specifies the type of external memory */ + ebi_norsram_mem_bus_width_t width; /**< Specifies the external memory device width */ + ebi_burst_access_mode_t acc_mode; /**< Enables or disables the burst access mode for Flash memory */ + ebi_wait_signal_polarity_t polarity; /**< Wait signal polarity, valid only in burst mode */ + ebi_wrap_mode_t wrap_mode; /**< Enables or disables the Wrapped burst access mode, only in burst mode */ + ebi_wait_timing_t active; /**< Specifies if the wait signal is asserted, only in burst mode */ + ebi_write_operation_t write; /**< Enables or disables the write operation */ + ebi_wait_signal_t signal; /**< Enables or disables the wait state insertion, only in burst mode */ + ebi_extended_mode_t ext_mode; /**< Enables or disables the extended mode */ + ebi_asynchronous_wait_t wait; /**< Enables or disables wait signal during asynchronous transfers */ + ebi_write_burst_t burst; /**< Enables or disables the write burst operation */ +} ald_ebi_nor_sram_init_t; + +/** + * @} + */ + +/** @defgroup EBI_Private_Macros EBI Private Macros + * @{ + */ +#define IS_EBI_NORSRAM_BANK(x) (((x) == EBI_NORSRAM_BANK1) || \ + ((x) == EBI_NORSRAM_BANK2) || \ + ((x) == EBI_NORSRAM_BANK3) || \ + ((x) == EBI_NORSRAM_BANK4)) +#define IS_EBI_MUX(x) (((x) == EBI_DATA_ADDRESS_MUX_DISABLE) || \ + ((x) == EBI_DATA_ADDRESS_MUX_ENABLE)) +#define IS_EBI_MEMORY(x) (((x) == EBI_MEMORY_TYPE_SRAM) || \ + ((x) == EBI_MEMORY_TYPE_PSRAM) || \ + ((x) == EBI_MEMORY_TYPE_NOR)) +#define IS_EBI_NORSRAM_MEMORY_WIDTH(x) (((x) == EBI_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((x) == EBI_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((x) == EBI_NORSRAM_MEM_BUS_WIDTH_32)) +#define IS_EBI_WRITE_BURST(x) (((x) == EBI_WRITE_BURST_DISABLE) || \ + ((x) == EBI_WRITE_BURST_ENABLE)) +#define IS_EBI_ACCESS_MODE(x) (((x) == EBI_ACCESS_MODE_A) || \ + ((x) == EBI_ACCESS_MODE_B) || \ + ((x) == EBI_ACCESS_MODE_C) || \ + ((x) == EBI_ACCESS_MODE_D)) +#define IS_EBI_NAND_BANK(x) (((x) == EBI_NAND_BANK2) || \ + ((x) == EBI_NAND_BANK3)) +#define IS_EBI_WAIT_FEATURE(x) (((x) == EBI_NAND_WAIT_FEATURE_DISABLE) || \ + ((x) == EBI_NAND_WAIT_FEATURE_ENABLE)) +#define IS_EBI_NAND_MEMORY_WIDTH(x) (((x) == EBI_NAND_MEM_BUS_WIDTH_8) || \ + ((x) == EBI_NAND_MEM_BUS_WIDTH_16)) +#define IS_EBI_ECC_STATE(x) (((x) == EBI_NAND_ECC_DISABLE) || \ + ((x) == EBI_NAND_ECC_ENABLE)) +#define IS_EBI_ECCPAGE_SIZE(x) (((x) == EBI_NAND_ECC_PAGE_SIZE_256BYTE) || \ + ((x) == EBI_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((x) == EBI_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((x) == EBI_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((x) == EBI_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((x) == EBI_NAND_ECC_PAGE_SIZE_8192BYTE)) +#define IS_EBI_LCD_DEVICE(x) ((x) == EBI_LCD_DEVICE) +#define IS_EBI_HORIZONTAL_SYNCH(x) (((x) == EBI_LCD_HSYNCPOL_LOW) || \ + ((x) == EBI_LCD_HSYNCPOL_HIGH)) +#define IS_EBI_VERTICAL_SYNCH(x) (((x) == EBI_LCD_VSYNCPOL_LOW) || \ + ((x) == EBI_LCD_VSYNCPOL_HIGH)) +#define IS_EBI_DATA_ENABLE(x) (((x) == EBI_LCD_DENPOL_LOW) || \ + ((x) == EBI_LCD_DENPOL_HIGH)) +#define IS_EBI_LCD_ENABLE(x) (((x) == EBI_LCD_LCDEN_DISABLE) || \ + ((x) == EBI_LCD_LCDEN_ENABLE)) +#define IS_EBI_LCD_RESET(x) (((x) == EBI_LCD_LCDINT_DISABLE) || \ + ((x) == EBI_LCD_LCDINT_ENABLE)) +#define IS_EBI_DATA_CLOCK(x) (((x) == EBI_LCD_DCLKPOL_FALLING) || \ + ((x) == EBI_LCD_DCLKPOL_RISING)) +#define IS_EBI_LCD_DATASETUP_TIME(x) ((x) < 255U) +#define IS_EBI_HYSNC_PULSE_WIDTH(x) ((x) < 255U) +#define IS_EBI_VSYNC_PULSE_WIDTH(x) ((x) < 255U) +#define IS_EBI_FRAME_LINE_NUMBER(x) (((x) >= 1U) && ((x) < 65535)) +#define IS_EBI_FRAME_PIXEL_NUMBER(x) (((x) >= 1U) && ((x) < 65535)) + +#define IS_EBI_TCLR_TIME(x) ((x) <= 255U) +#define IS_EBI_TAR_TIME(x) ((x) <= 255U) +#define IS_EBI_SETUP_TIME(x) ((x) <= 255U) +#define IS_EBI_WAIT_TIME(x) ((x) <= 255U) +#define IS_EBI_HOLD_TIME(x) ((x) <= 255U) +#define IS_EBI_HIZ_TIME(x) ((x) <= 255U) +#define IS_EBI_NORSRAM_DEVICE(x) ((x) == EBI_NOR_SRAM_DEVICE) +#define IS_EBI_NORSRAM_EXTENDED_DEVICE(x) ((x) == EBI_NOR_SRAM_EXTENDED_DEVICE) +#define IS_EBI_NAND_DEVICE(x) ((x) == EBI_NAND_DEVICE) +#define IS_EBI_BURSTMODE(x) (((x) == EBI_BURST_ACCESS_MODE_DISABLE) || \ + ((x) == EBI_BURST_ACCESS_MODE_ENABLE)) +#define IS_EBI_WAIT_POLARITY(x) (((x) == EBI_WAIT_SIGNAL_POLARITY_LOW) || \ + ((x) == EBI_WAIT_SIGNAL_POLARITY_HIGH)) +#define IS_EBI_WRAP_MODE(x) (((x) == EBI_WRAP_MODE_DISABLE) || \ + ((x) == EBI_WRAP_MODE_ENABLE)) +#define IS_EBI_WAIT_SIGNAL_ACTIVE(x) (((x) == EBI_WAIT_TIMING_BEFORE_WS) || \ + ((x) == EBI_WAIT_TIMING_DURING_WS)) +#define IS_EBI_WRITE_OPERATION(x) (((x) == EBI_WRITE_OPERATION_DISABLE) || \ + ((x) == EBI_WRITE_OPERATION_ENABLE)) +#define IS_EBI_WAITE_SIGNAL(x) (((x) == EBI_WAIT_SIGNAL_DISABLE) || \ + ((x) == EBI_WAIT_SIGNAL_ENABLE)) +#define IS_EBI_EXTENDED_MODE(x) (((x) == EBI_EXTENDED_MODE_DISABLE) || \ + ((x) == EBI_EXTENDED_MODE_ENABLE)) +#define IS_EBI_ASYNWAIT(x) (((x) == EBI_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((x) == EBI_ASYNCHRONOUS_WAIT_ENABLE)) +#define IS_EBI_CLK_DIV(x) (((x) >= 1U) && ((x) <= 16U)) +#define IS_EBI_DATA_LATENCY(x) (((x) >= 1U) && ((x) <= 17U)) +#define IS_EBI_ADDRESS_SETUP_TIME(x) ((x) <= 15U) +#define IS_EBI_ADDRESS_HOLD_TIME(x) (((x) > 0U) && ((x) <= 15U)) +#define IS_EBI_DATASETUP_TIME(x) (((x) > 0U) && ((x) <= 255U)) +#define IS_EBI_TURNAROUND_TIME(x) ((x) <= 15U) +#define IS_EBI_BANK_NUMBER(x) (((x) > 0U) && ((x) <= 4U)) +/** + * @} + */ + +/** @addtogroup EBI_Public_Functions + * @{ + */ + +/** @addtogroup EBI_Public_Functions_Group1 + * @{ + */ +/* NOR-FLASH SRAM initialize functions */ +void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init); +void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank); +void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode); +ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank); +/** + * @} + */ + +/** @addtogroup EBI_Public_Functions_Group2 + * @{ + */ +/* NOR/SRAM Control functions */ +void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank); +void ald_ebi_nor_sram_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank); +void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank); +void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank); +/** + * @} + */ + +/** @addtogroup EBI_Public_Functions_Group3 + * @{ + */ +/* NAND-FLASH initialize functions */ +void ald_ebi_nand_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init); +void ald_ebi_nand_comm_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank); +void ald_ebi_nand_attr_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank); +void ald_ebi_nand_deinit(EBI_NAND_TypeDef *dev, uint32_t bank); +/** + * @} + */ + +/** @addtogroup EBI_Public_Functions_Group4 + * @{ + */ +/* NAND-FLASH control functions */ +void ald_ebi_nand_enable(EBI_NAND_TypeDef *dev, uint32_t bank); +void ald_ebi_nand_disable(EBI_NAND_TypeDef *dev, uint32_t bank); +void ald_ebi_nand_enable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it); +void ald_ebi_nand_disable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it); +void ald_ebi_nand_ecc_enable(EBI_NAND_TypeDef *dev, uint32_t bank); +void ald_ebi_nand_ecc_disable(EBI_NAND_TypeDef *dev, uint32_t bank); +ald_status_t ald_ebi_nand_get_ecc(EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout); +flag_status_t ald_ebi_nand_get_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag); +void ald_ebi_nand_clear_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag); +/** + * @} + */ + +/** @addtogroup EBI_Public_Functions_Group5 + * @{ + */ +void ald_ebi_lcd_init(ebi_lcd_handle_t *hlcd); +void ald_ebi_lcd_reset(ebi_lcd_handle_t *hlcd); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_EBI_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_flash.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_flash.h new file mode 100644 index 00000000..e91c3f3d --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_flash.h @@ -0,0 +1,146 @@ +/** + ********************************************************************************* + * + * @file ald_flash.h + * @brief Header file of FLASH driver + * + * @version V1.0 + * @date 17 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 17 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_FLASH_H__ +#define __ALD_FLASH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** + * @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ +#define FLASH_REG_UNLOCK() \ +do { \ + if (op_cmd == OP_FLASH) { \ + WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \ + WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \ + } \ + else { \ + WRITE_REG(MSC->INFOKEY, 0x7153BFD9); \ + WRITE_REG(MSC->INFOKEY, 0x0642CEA8); \ + } \ +} while (0) +#define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) +#define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK)) +#define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) +#define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK)) +#define FLASH_BASE_ADDR 0x00000000 +#define FLASH_PAGE_SIZE 1024UL +#define FLASH_WORD_SIZE 8UL +#define FLASH_TOTAL_SIZE 512UL +#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) +#define FLASH_WORD_MASK (FLASH_WORD_SIZE - 1) +#define IS_FLASH_ADDRESS(ADDR) ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE)) +#define IS_4BYTES_ALIGN(ADDR) (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0) +#define FLASH_PAGE_ADDR(ADDR) ((ADDR) & (~FLASH_PAGE_MASK)) +#define FLASH_PAGEEND_ADDR(ADDR) ((ADDR) | FLASH_PAGE_MASK) +#define FLASH_WORD_ADDR(ADDR) ((ADDR) & (~FLASH_WORD_MASK)) +#define FLASH_WORDEND_ADDR(ADDR) ((ADDR) | FLASH_WORD_MASK) +#define INFO_PAGE_SIZE 1024UL +#define INFO_PAGE_MASK (INFO_PAGE_SIZE - 1) +#define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK)) + +#ifdef USE_FLASH_FIFO + #define FLASH_FIFO 1 +#else + #define FLASH_FIFO 0 +#endif +/** + * @} + */ + +/** @defgroup FLASH_Private_Types FLASH Private Types + * @{ + */ +typedef enum { + FLASH_CMD_AE = 0x000051AEU, /**< Program area erase all */ + FLASH_CMD_PE = 0x00005EA1U, /**< Page erase */ + FLASH_CMD_WP = 0x00005DA2U, /**< Word program */ + FLASH_CMD_WP_FAST = 0x00005CA3U, /**< Flash quickly program */ + FLASH_CMD_DATAPE = 0x00005BA4U, /**< Data flash page page erase */ + FLASH_CMD_DATAWP = 0x00005AA5U, /**< Data flash word program */ + FLASH_CMD_DATAWP_FAST = 0x000059A6U, /**< Data flash quickly program */ + FLASH_CMD_NP_AE = 0x000050AFU, /**< No-private area erase all */ +} flash_cmd_type; + +typedef enum { + OP_FLASH = 0U, /**< Operate Pragram area */ + OP_INFO = 1U, /**< Operate info area */ +} op_cmd_type; + +/** + * @} + */ +/** @addtogroup Flash_Private_Functions + * @{ + */ +ald_status_t flash_page_erase(uint32_t addr); +ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo); +/** + * @} + */ + +/** @addtogroup Flash_Public_Functions + * @{ + */ +ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len); +ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len); +ald_status_t ald_flash_erase(uint32_t addr, uint16_t len); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_FLASH_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_gpio.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_gpio.h new file mode 100644 index 00000000..3c87e2ca --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_gpio.h @@ -0,0 +1,339 @@ +/** + ********************************************************************************* + * + * @file ald_gpio.h + * @brief Header file of GPIO module driver + * + * @version V1.0 + * @date 07 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_GPIO_H__ +#define __ALD_GPIO_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** + * @defgroup GPIO_Public_Macros GPIO Public Macros + * @{ + */ +#define GPIO_PIN_0 (0x1U) +#define GPIO_PIN_1 (0x2U) +#define GPIO_PIN_2 (0x4U) +#define GPIO_PIN_3 (0x8U) +#define GPIO_PIN_4 (0x10U) +#define GPIO_PIN_5 (0x20U) +#define GPIO_PIN_6 (0x40U) +#define GPIO_PIN_7 (0x80U) +#define GPIO_PIN_8 (0x100U) +#define GPIO_PIN_9 (0x200U) +#define GPIO_PIN_10 (0x400U) +#define GPIO_PIN_11 (0x800U) +#define GPIO_PIN_12 (0x1000U) +#define GPIO_PIN_13 (0x2000U) +#define GPIO_PIN_14 (0x4000U) +#define GPIO_PIN_15 (0x8000U) +#define GPIO_PIN_ALL (0xFFFF) + +/* Toggle IO */ +#define ALD_GPIOA_TOGGLE_PIN(x) (GPIOA->BIR = (x)) +#define ALD_GPIOB_TOGGLE_PIN(x) (GPIOB->BIR = (x)) +#define ALD_GPIOC_TOGGLE_PIN(x) (GPIOC->BIR = (x)) +#define ALD_GPIOD_TOGGLE_PIN(x) (GPIOD->BIR = (x)) +#define ALD_GPIOE_TOGGLE_PIN(x) (GPIOE->BIR = (x)) +#define ALD_GPIOF_TOGGLE_PIN(x) (GPIOF->BIR = (x)) +#define ALD_GPIOG_TOGGLE_PIN(x) (GPIOG->BIR = (x)) +#define ALD_GPIOH_TOGGLE_PIN(x) (GPIOH->BIR = (x)) + +/* Read IO level */ +#define ALD_GPIOA_READ_PIN(x) ((GPIOA->DIN & (x)) ? 1 : 0) +#define ALD_GPIOB_READ_PIN(x) ((GPIOB->DIN & (x)) ? 1 : 0) +#define ALD_GPIOC_READ_PIN(x) ((GPIOC->DIN & (x)) ? 1 : 0) +#define ALD_GPIOD_READ_PIN(x) ((GPIOD->DIN & (x)) ? 1 : 0) +#define ALD_GPIOE_READ_PIN(x) ((GPIOE->DIN & (x)) ? 1 : 0) +#define ALD_GPIOF_READ_PIN(x) ((GPIOF->DIN & (x)) ? 1 : 0) +#define ALD_GPIOG_READ_PIN(x) ((GPIOG->DIN & (x)) ? 1 : 0) +#define ALD_GPIOH_READ_PIN(x) ((GPIOH->DIN & (x)) ? 1 : 0) + +/* Set IO as high */ +#define ALD_GPIOA_SET_PIN(x) (GPIOA->BSRR = (x)) +#define ALD_GPIOB_SET_PIN(x) (GPIOB->BSRR = (x)) +#define ALD_GPIOC_SET_PIN(x) (GPIOC->BSRR = (x)) +#define ALD_GPIOD_SET_PIN(x) (GPIOD->BSRR = (x)) +#define ALD_GPIOE_SET_PIN(x) (GPIOE->BSRR = (x)) +#define ALD_GPIOF_SET_PIN(x) (GPIOF->BSRR = (x)) +#define ALD_GPIOG_SET_PIN(x) (GPIOG->BSRR = (x)) +#define ALD_GPIOH_SET_PIN(x) (GPIOH->BSRR = (x)) + +/* Set IO as low */ +#define ALD_GPIOA_RESET_PIN(x) (GPIOA->BSRR = ((x) << 16)) +#define ALD_GPIOB_RESET_PIN(x) (GPIOB->BSRR = ((x) << 16)) +#define ALD_GPIOC_RESET_PIN(x) (GPIOC->BSRR = ((x) << 16)) +#define ALD_GPIOD_RESET_PIN(x) (GPIOD->BSRR = ((x) << 16)) +#define ALD_GPIOE_RESET_PIN(x) (GPIOE->BSRR = ((x) << 16)) +#define ALD_GPIOF_RESET_PIN(x) (GPIOF->BSRR = ((x) << 16)) +#define ALD_GPIOG_RESET_PIN(x) (GPIOG->BSRR = ((x) << 16)) +#define ALD_GPIOH_RESET_PIN(x) (GPIOH->BSRR = ((x) << 16)) +/** + * @} + */ + +/** + * @defgroup GPIO_Public_Types GPIO Public Types + * @{ + */ + +/** + * @brief GPIO mode + */ +typedef enum { + GPIO_MODE_CLOSE = 0x0U, /**< Digital close Analog open */ + GPIO_MODE_INPUT = 0x1U, /**< Input */ + GPIO_MODE_OUTPUT = 0x2U, /**< Output */ +} gpio_mode_t; + +/** + * @brief GPIO open-drain or push-pull + */ +typedef enum { + GPIO_PUSH_PULL = 0x0U, /**< Push-Pull */ + GPIO_OPEN_DRAIN = 0x2U, /**< Open-Drain. Can't output high level */ + GPIO_OPEN_SOURCE = 0x3U, /**< Open-Source. Can't output low level */ +} gpio_odos_t; + +/** + * @brief GPIO push-up or push-down + */ +typedef enum { + GPIO_FLOATING = 0x0U, /**< Floating */ + GPIO_PUSH_UP = 0x1U, /**< Push-Up */ + GPIO_PUSH_DOWN = 0x2U, /**< Push-Down */ + GPIO_PUSH_UP_DOWN = 0x3U, /**< Push-Up and Push-Down */ +} gpio_push_t; + +/** + * @brief GPIO output drive + */ +typedef enum { + GPIO_OUT_DRIVE_0_1 = 0x0U, /**< 0.1mA */ + GPIO_OUT_DRIVE_1 = 0x1U, /**< 1mA */ + GPIO_OUT_DRIVE_6 = 0x2U, /**< 6mA */ + GPIO_OUT_DRIVE_20 = 0x3U, /**< 20mA */ +} gpio_out_drive_t; + +/** + * @brief GPIO filter + */ +typedef enum { + GPIO_FILTER_DISABLE = 0x0U, /**< Disable filter */ + GPIO_FILTER_ENABLE = 0x1U, /**< Enable filter */ +} gpio_filter_t; + +/** + * @brief GPIO type + */ +typedef enum { + GPIO_TYPE_CMOS = 0x0U, /**< CMOS Type */ + GPIO_TYPE_TTL = 0x1U, /**< TTL Type */ +} gpio_type_t; + +/** + * @brief GPIO functions + */ +typedef enum { + GPIO_FUNC_0 = 0U, /**< function #0 */ + GPIO_FUNC_1 = 1U, /**< function #1 */ + GPIO_FUNC_2 = 2U, /**< function #2 */ + GPIO_FUNC_3 = 3U, /**< function #3 */ + GPIO_FUNC_4 = 4U, /**< function #4 */ + GPIO_FUNC_5 = 5U, /**< function #5 */ + GPIO_FUNC_6 = 6U, /**< function #6 */ + GPIO_FUNC_7 = 7U, /**< function #7 */ +} gpio_func_t; + + +/** + * @brief GPIO Init Structure definition + */ +typedef struct { + gpio_mode_t mode; /**< Specifies the operating mode for the selected pins. + This parameter can be any value of @ref gpio_mode_t */ + gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins. + This parameter can be a value of @ref gpio_odos_t */ + gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins. + This parameter can be a value of @ref gpio_push_t */ + gpio_out_drive_t podrv; /**< Specifies the output P-MOS driver for the selected pins. + This parameter can be a value of @ref gpio_out_drive_t */ + gpio_out_drive_t nodrv; /**< Specifies the output N-MOS driver for the selected pins. + This parameter can be a value of @ref gpio_out_drive_t */ + gpio_filter_t flt; /**< Specifies the input filter for the selected pins. + This parameter can be a value of @ref gpio_filter_t */ + gpio_type_t type; /**< Specifies the type for the selected pins. + This parameter can be a value of @ref gpio_type_t */ + gpio_func_t func; /**< Specifies the function for the selected pins. + This parameter can be a value of @ref gpio_func_t */ +} gpio_init_t; + +/** + * @brief EXTI trigger style + */ +typedef enum { + EXTI_TRIGGER_RISING_EDGE = 0U, /**< Rising edge trigger */ + EXTI_TRIGGER_TRAILING_EDGE = 1U, /**< Trailing edge trigger */ + EXTI_TRIGGER_BOTH_EDGE = 2U, /**< Rising and trailing edge trigger */ +} exti_trigger_style_t; + +/** + * @brief EXTI filter clock select + */ +typedef enum { + EXTI_FILTER_CLOCK_10K = 0U, /**< cks = 10KHz */ + EXTI_FILTER_CLOCK_32K = 1U, /**< cks = 32KHz */ +} exti_filter_clock_t; + +/** + * @brief EXTI Init Structure definition + */ +typedef struct { + type_func_t filter; /**< Enable filter. */ + exti_filter_clock_t cks; /**< Filter clock select. */ + uint8_t filter_time; /**< Filter duration */ +} exti_init_t; +/** + * @} + */ + +/** + * @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define PIN_MASK 0xFFFFU +#define UNLOCK_KEY 0x55AAU + +#define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0)) +#define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \ + (GPIOx == GPIOB) || \ + (GPIOx == GPIOC) || \ + (GPIOx == GPIOD) || \ + (GPIOx == GPIOE) || \ + (GPIOx == GPIOF) || \ + (GPIOx == GPIOG) || \ + (GPIOx == GPIOH)) +#define IS_GPIO_MODE(x) (((x) == GPIO_MODE_CLOSE) || \ + ((x) == GPIO_MODE_INPUT) || \ + ((x) == GPIO_MODE_OUTPUT)) +#define IS_GPIO_ODOS(x) (((x) == GPIO_PUSH_PULL) || \ + ((x) == GPIO_OPEN_DRAIN) || \ + ((x) == GPIO_OPEN_SOURCE)) +#define IS_GPIO_PUPD(x) (((x) == GPIO_FLOATING) || \ + ((x) == GPIO_PUSH_UP) || \ + ((x) == GPIO_PUSH_DOWN) || \ + ((x) == GPIO_PUSH_UP_DOWN)) +#define IS_GPIO_ODRV(x) (((x) == GPIO_OUT_DRIVE_0_1) || \ + ((x) == GPIO_OUT_DRIVE_1) || \ + ((x) == GPIO_OUT_DRIVE_6) || \ + ((x) == GPIO_OUT_DRIVE_20)) +#define IS_GPIO_FLT(x) (((x) == GPIO_FILTER_DISABLE) || \ + ((x) == GPIO_FILTER_ENABLE)) +#define IS_GPIO_TYPE(x) (((x) == GPIO_TYPE_TTL) || \ + ((x) == GPIO_TYPE_CMOS)) +#define IS_TRIGGER_STYLE(x) (((x) == EXTI_TRIGGER_RISING_EDGE) || \ + ((x) == EXTI_TRIGGER_TRAILING_EDGE) || \ + ((x) == EXTI_TRIGGER_BOTH_EDGE)) +#define IS_EXTI_FLTCKS_TYPE(x) (((x) == EXTI_FILTER_CLOCK_10K) || \ + ((x) == EXTI_FILTER_CLOCK_32K)) +#define IS_GPIO_FUNC(x) ((x) <= 7) +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions + * @{ + */ + +/** @addtogroup GPIO_Public_Functions_Group1 + * @{ + */ +void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init); +void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_func_default(GPIO_TypeDef *GPIOx); +void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init); +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions_Group2 + * @{ + */ +uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val); +void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin); +void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin); +uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx); +void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val); +/** + * @} + */ + +/** @addtogroup GPIO_Public_Functions_Group3 + * @{ + */ +void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status); +flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin); +void ald_gpio_exti_clear_flag_status(uint16_t pin); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_GPIO_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_i2c.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_i2c.h new file mode 100644 index 00000000..5808c6d4 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_i2c.h @@ -0,0 +1,470 @@ +/** + ********************************************************************************* + * + * @file ald_i2c.h + * @brief Header file of I2C driver + * + * @version V1.0 + * @date 15 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 30 Jun 2020 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_I2C_H__ +#define __ALD_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" +#include "ald_cmu.h" +#include + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Public_Types I2C Public Types + * @{ + */ +/** + * @brief I2C Error Code + */ +typedef enum { + I2C_ERROR_NONE = 0x0U, /**< No error */ + I2C_ERROR_BERR = 0x1U, /**< Berr error */ + I2C_ERROR_ARLO = 0x2U, /**< Arlo error */ + I2C_ERROR_RUD = 0x4U, /**< Rx underflow error */ + I2C_ERROR_AF = 0x8U, /**< Af error */ + I2C_ERROR_ROV = 0x10U, /**< Rx overflow error */ + I2C_ERROR_RF = 0x20U, /**< Rx full error */ + I2C_ERROR_TUD = 0x40U, /**< Tx underflow error */ + I2C_ERROR_TOV = 0x80U, /**< Tx overflow error */ + I2C_ERROR_TE = 0x100U, /**< Tx empty error */ + I2C_ERROR_DMA = 0x200U, /**< Dma error */ + I2C_ERROR_TIMEOUT = 0x400U, /**< Timeout error */ +} i2c_error_t; + +/** + * @brief I2C state structure definition + */ +typedef enum { + I2C_STATE_RESET = 0x0U, /**< Peripheral is not yet Initialized */ + I2C_STATE_READY = 0x20U, /**< Peripheral Initialized and ready for use */ + I2C_STATE_BUSY = 0x24U, /**< An internal process is ongoing */ + I2C_STATE_BUSY_TX = 0x21U, /**< Data Transmission process is ongoing */ + I2C_STATE_BUSY_RX = 0x22U, /**< Data Reception process is ongoing */ + I2C_STATE_TIMEOUT = 0xA0U, /**< timeout state */ + I2C_STATE_ERROR = 0xE0U, /**< Error */ +} i2c_state_t; + +/** + * @brief I2C Addressing Mode + */ +typedef enum { + I2C_ADDR_7BIT = 0x0U, /**< 7 bit address */ + I2C_ADDR_10BIT = 0x1U, /**< 10 bit address */ +} i2c_addr_t; + +/** + * @brief I2C Dual Addressing Mode + */ +typedef enum { + I2C_DUALADDR_DISABLE = 0x0U, /**< dual address is disable */ + I2C_DUALADDR_ENABLE = 0x1U, /**< dual address is enable */ +} i2c_dual_addr_t; + +/** + * @brief I2C General Call Addressing mode + */ +typedef enum { + I2C_GENERALCALL_DISABLE = 0x0U, /**< general call address is disable */ + I2C_GENERALCALL_ENABLE = 0x1U, /**< general call address is enable */ +} i2c_general_addr_t; + +/** + * @brief I2C Nostretch Mode + */ +typedef enum { + I2C_NOSTRETCH_DISABLE = 0x0U, /**< Nostretch disable */ + I2C_NOSTRETCH_ENABLE = 0x1U, /**< Nostretch enable */ +} i2c_nostretch_t; + +/** + * @brief I2C Memory Address Size + */ +typedef enum { + I2C_MEMADD_SIZE_8BIT = 0x8U, /**< 8 bit memory address size */ + I2C_MEMADD_SIZE_16BIT = 0x10U, /**< 10 bit memory address size */ +} i2c_addr_size_t; + +/** + * @brief I2C mode structure definition + */ +typedef enum { + I2C_MODE_NONE = 0x0U, /**< No I2C communication on going */ + I2C_MODE_MASTER = 0x10U, /**< I2C communication is in Master mode */ + I2C_MODE_SLAVE = 0x20U, /**< I2C communication is in Slave mode */ + I2C_MODE_MEM = 0x40U, /**< I2C communication is in Memory mode */ +} i2c_mode_t; + +/** + * @brief I2C Clock + */ +typedef enum { + I2C_STANDARD_MODE_MAX_CLK = 100000U, /**< Standard mode clock */ + I2C_FAST_MODE_MAX_CLK = 400000U, /**< Fast mode clock */ + I2C_EXTREME_FAST_MODE_MAX_CLK = 1000000U, /**< Extreme mode clock */ +} i2c_clock_t; + +/** + * @brief I2C OAR2 Register + */ +typedef enum { + I2C_OAR2_ENDUAL = (1U << 0), /**< ENDUAL BIT */ + I2C_OAR2_ADD2 = (1U << 1) /**< ADD2 BIT */ +} i2c_oar2_t; + +/** + * @brief I2C CON1 Register + */ +typedef enum { + I2C_CON1_PE = (1U << 0), /**< Peripheral enable BIT */ + I2C_CON1_TXDMA = (1U << 14), /**< Transmit DMA BIT */ + I2C_CON1_RXDMA = (1U << 15), /**< Receive DMA BIT */ + I2C_CON1_SBC = (1U << 16), /**< Receive DMA BIT */ + I2C_CON1_NOSTRETCH = (1U << 17), /**< Slave bytes control BIT */ + I2C_CON1_GCEN = (1U << 19), /**< General call BIT */ + I2C_CON1_SMBHEN = (1U << 20), /**< SMBus slave device enable BIT */ + I2C_CON1_SMBDEN = (1U << 21), /**< SMBus master device enable BIT */ + I2C_CON1_ALERTEN = (1U << 22), /**< SMBus alert device enable BIT */ + I2C_CON1_PECEN = (1U << 23), /**< PEC enable BIT */ +} i2c_con1_t; + +/** + * @brief I2C CON2 Register + */ +typedef enum { + I2C_CON2_RD_WRN = (1U << 10), /**< Master R/W control BIT */ + I2C_CON2_ADD10 = (1U << 11), /**< 10bit address control BIT */ + I2C_CON2_HEAD10R = (1U << 12), /**< 10bit address master Receive control BIT */ + I2C_CON2_START = (1U << 13), /**< Master start singal control BIT */ + I2C_CON2_STOP = (1U << 14), /**< Master stop singal control BIT */ + I2C_CON2_NACK = (1U << 15), /**< Master Nack control BIT */ + I2C_CON2_RELOAD = (1U << 24), /**< Master communication reload control BIT */ + I2C_CON2_AUTOEND = (1U << 25), /**< Master Autoend control BIT */ + I2C_CON2_PECBYTE = (1U << 26), /**< PEC control BIT */ + I2C_CON2_HOLDACK = (1U << 28), /**< Hold ack control BIT */ +} i2c_con2_t; + +/** + * @brief I2C ADDR1 Register + */ +typedef enum { + I2C_OA1MODE = (1U << 10), /**< Addr1 bits choose BIT */ + I2C_OA1EN = (1U << 15), /**< Addr1 enable BIT */ +} i2c_addr1_t; + +/** + * @brief I2C ADDR2 Register + */ +typedef enum { + I2C_OA2EN = (1U << 15), /**< Addr2 enable BIT */ +} i2c_addr2_t; + +/** + * @brief I2C TIMEOUTR Register + */ +typedef enum { + I2C_TIMEOUTR_TIDLE = (1U << 12), /**< SCL idle check enable BIT */ + I2C_TIMEOUTR_TIMEOUTEN = (1U << 15), /**< Timeout enable BIT */ +} i2c_timoutr_t; + +/** + * @brief I2C peripherals module + */ +typedef enum { + I2C_MODULE_MASTER = (1U << 0), /**< Master module */ + I2C_MODULE_SLAVE = (1U << 1) /**< Slave module */ +} i2c_module_t; + +/** + * @brief I2C STAT Register + */ +typedef enum { + I2C_STAT_TXE = (1U << 0), /**< Transmit FIFO empty flag */ + I2C_STAT_TXF = (1U << 1), /**< Transmit FIFO full flag */ + I2C_STAT_TXOV = (1U << 2), /**< Transmit FIFO overrun flag */ + I2C_STAT_TXUD = (1U << 3), /**< Transmit FIFO underrun flag*/ + I2C_STAT_THTH = (1U << 4), /**< Transmit FIFO threshold flag */ + I2C_STAT_RXE = (1U << 5), /**< Receive FIFO empty flag*/ + I2C_STAT_RXF = (1U << 6), /**< Receive FIFO full flag*/ + I2C_STAT_RXOV = (1U << 7), /**< Receive FIFO overrun flag */ + I2C_STAT_RXUD = (1U << 8), /**< Receive FIFO underrun flag */ + I2C_STAT_RXTH = (1U << 9), /**< Receive FIFO threshold flag */ + I2C_STAT_TC = (1U << 10), /**< Transmit completed flag */ + I2C_STAT_TCR = (1U << 11), /**< Transmit and reload completed flag */ + I2C_STAT_BUSY = (1U << 15), /**< Bus status busy flag */ + I2C_STAT_DIR = (1U << 16), /**< Slave R/W flag */ +} i2c_stat_t; + +/** + * @brief Interrupt Configuration Definition + */ +typedef enum { + I2C_IT_TXE = (1U << 0), /**< Transmit FIFO empty interrupt */ + I2C_IT_TXOV = (1U << 2), /**< Transmit FIFO overrun interrupt */ + I2C_IT_TXUD = (1U << 3), /**< Transmit FIFO underrun interrupt*/ + I2C_IT_TXTH = (1U << 4), /**< Transmit FIFO threshold interrupt */ + I2C_IT_RXF = (1U << 6), /**< Receive FIFO full interrupt*/ + I2C_IT_RXOV = (1U << 7), /**< Receive FIFO overrun interrupt */ + I2C_IT_RXUD = (1U << 8), /**< Receive FIFO underrun interrupt */ + I2C_IT_RXTH = (1U << 9), /**< Receive FIFO threshold interrupt */ + I2C_IT_TC = (1U << 10), /**< Transmit completed interrupt */ + I2C_IT_TCR = (1U << 11), /**< Transmit and reload completed interrupt */ + I2C_IT_ADDR = (1U << 12), /**< Address matching interrupt */ + I2C_IT_NACK = (1U << 13), /**< NACK interrupt */ + I2C_IT_STOP = (1U << 14), /**< Stop detection interrupt */ + I2C_IT_BERR = (1U << 16), /**< Bus error interrupt */ + I2C_IT_ARLO = (1U << 17), /**< Arbitration loss interrupt */ + I2C_IT_PECE = (1U << 18), /**< PEC error interrupt */ + I2C_IT_TOUT = (1U << 19), /**< Timeout interrupt */ + I2C_IT_ALERT = (1U << 20), /**< SMBus Alert interrupt */ +} i2c_interrupt_t; + +/** + * @brief I2C TRISE Register + */ +typedef enum { + I2C_TRISE_TRISE = 0x3FU, /**< TRISE BITS */ +} i2c_trise_t; + +/** + * @brief I2C Configuration Structure definition + */ +typedef struct { + i2c_module_t module; /**< Specifies the communication module */ + uint32_t clk_speed; /**< Specifies the clock frequency */ + uint32_t own_addr1; /**< Specifies the first device own address */ + i2c_addr_t addr_mode; /**< Specifies addressing mode */ + i2c_dual_addr_t dual_addr; /**< Specifies if dual addressing mode is selected */ + uint32_t own_addr2; /**< Specifies the second device own address */ + i2c_general_addr_t general_call;/**< Specifies if general call mode is selected */ + i2c_nostretch_t no_stretch; /**< Specifies if nostretch mode is selected */ +} i2c_init_t; + +/** + * @brief I2C handle Structure definition + */ +typedef struct i2c_handle_s { + I2C_TypeDef *perh; /**< I2C registers base address */ + i2c_init_t init; /**< I2C communication parameters */ + uint8_t *p_buff; /**< Pointer to I2C transfer buffer */ + uint16_t xfer_size; /**< I2C transfer size */ + __IO uint16_t xfer_count; /**< I2C transfer counter */ + + dma_handle_t hdmatx; /**< I2C Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< I2C Rx DMA handle parameters */ + + lock_state_t lock; /**< I2C locking object */ + __IO i2c_state_t state; /**< I2C communication state */ + __IO i2c_mode_t mode; /**< I2C communication mode */ + __IO uint32_t error_code; /**< I2C Error code */ + + void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Tx completed callback */ + void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Master Rx completed callback */ + void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Tx completed callback */ + void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Slave Rx completed callback */ + void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg); /**< Tx to Memory completed callback */ + void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg); /**< Rx from Memory completed callback */ + void (*error_callback)(struct i2c_handle_s *arg); /**< Error callback */ +} i2c_handle_t; + +/** + * @} + */ + +/** @defgroup I2C_Public_Macro I2C Public Macros + * @{ + */ +#define I2C_FLAG_MASK (0xFFFFFFFFU) +#define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET) +#define I2C_ENABLE_IT(x, y) (SET_BIT((x)->perh->IER, (y))) +#define I2C_DISABLE_IT(x, y) (SET_BIT((x)->perh->IDR, (y))) +#define I2C_CLEAR_IT(x, y) (SET_BIT((x)->perh->ICR, (y))) +#define I2C_GET_IT_FLAG(x, y) (READ_BIT((x)->perh->RIF, (y))) +#define I2C_GET_IT_SOURCE(x, y) ((((x)->perh->IFM & (y)) == (y)) ? SET : RESET) +#define I2C_GET_FLAG(x, y) ((((x)->perh->STAT) & ((y) & I2C_FLAG_MASK)) != RESET) +#define I2C_MASTER_GET_DIR(x) (READ_BIT(((x)->perh->CON2), I2C_CON2_RD_WRN_MSK)) +#define I2C_SLAVE_GET_DIR(x) (READ_BIT(((x)->perh->STAT), I2C_STAT_DIR_MSK)) +#define I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PE_MSK)) +#define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PE_MSK)) +#define I2C_RST_TXFIFO(x) (SET_BIT((x)->perh->FCON, I2C_FCON_TXFRST_MSK)) +#define I2C_RST_RXFIFO(x) (SET_BIT((x)->perh->FCON, I2C_FCON_RXFRST_MSK)) +/** + * @} + */ + +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ +#define IS_I2C_TYPE(x) (((x) == I2C0) || ((x) == I2C1)) +#define IS_I2C_MODULE(x) (((x) == I2C_MODULE_MASTER) || ((x) == I2C_MODULE_SLAVE)) +#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDR_7BIT) || \ + ((ADDRESS) == I2C_ADDR_10BIT)) +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDR_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDR_ENABLE)) +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) +#define IS_I2C_MEMADD_size(size) (((size) == I2C_MEMADD_SIZE_8BIT) || \ + ((size) == I2C_MEMADD_SIZE_16BIT)) +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= I2C_EXTREME_FAST_MODE_MAX_CLK) ) +#define I2C_FREQ_RANGE(__PCLK__) ((__PCLK__) / 1000000) +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) &\ + (uint16_t)(0xFF00))) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) +#define IS_I2C_IT(x) (((x) == I2C_IT_TXE) || \ + ((x) == I2C_IT_TXOV) || \ + ((x) == I2C_IT_TXUD) || \ + ((x) == I2C_IT_TXTH) || \ + ((x) == I2C_IT_RXF) || \ + ((x) == I2C_IT_RXOV) || \ + ((x) == I2C_IT_RXUD) || \ + ((x) == I2C_IT_RXTH) || \ + ((x) == I2C_IT_TC) || \ + ((x) == I2C_IT_TCR) || \ + ((x) == I2C_IT_ADDR) || \ + ((x) == I2C_IT_NACK) || \ + ((x) == I2C_IT_STOP) || \ + ((x) == I2C_IT_BERR) || \ + ((x) == I2C_IT_ARLO) || \ + ((x) == I2C_IT_PECE) || \ + ((x) == I2C_IT_TOUT) || \ + ((x) == I2C_IT_ALERT)) +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions + * @{ + */ + +/** @addtogroup I2C_Public_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +ald_status_t ald_i2c_init(i2c_handle_t *hperh); +ald_status_t ald_i2c_reset(i2c_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group2 Input and Output operation functions + * @{ + */ + /** Blocking mode: Polling */ +ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout); + + /** Non-Blocking mode: Interrupt */ +ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint32_t size); +ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint32_t size); + + + /** Non-Blocking mode: DMA */ +ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint8_t size, uint8_t channel); +ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, + uint8_t *buf, uint8_t size, uint8_t channel); +ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel); +ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel); +ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint8_t size, uint8_t channel); +ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint8_t size, uint8_t channel); + +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group3 Peripheral state and Errors functions + * @{ + */ +i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh); +uint32_t ald_i2c_get_error(i2c_handle_t *hperh); +void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag); +flag_status_t ald_i2c_get_mask_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag); +flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag); +it_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it); +/** + * @} + */ + +/** @addtogroup I2C_Public_Functions_Group4 IRQ Handler and Callbacks + * @{ + */ +void ald_i2c_ev_irq_handler(i2c_handle_t *hperh); +void ald_i2c_er_irq_handler(i2c_handle_t *hperh); +void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_I2C_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_i2s.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_i2s.h new file mode 100644 index 00000000..ad220bd9 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_i2s.h @@ -0,0 +1,391 @@ +/** + ********************************************************************************* + * + * @file ald_i2s.c + * @brief Header file of I2S module driver. + * + * @version V1.0 + * @date 13 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 13 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_I2S_H__ +#define __ALD_I2S_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + +/** @defgroup I2S_Public_Types I2S Public Types + * @{ + */ + +/** + * @brief Channel length + */ +typedef enum { + I2S_WIDE_16 = 0x0U, /**< Channel length is 16 */ + I2S_WIDE_32 = 0x1U, /**< Channel length is 32 */ +} i2s_chlen_t; + +/** + * @brief Data length + */ +typedef enum { + I2S_LEN_16 = 0x0U, /**< Data length is 16 */ + I2S_LEN_24 = 0x1U, /**< Data length is 24 */ + I2S_LEN_32 = 0x2U, /**< Data length is 32 */ +} i2s_datalen_t; + +/** + * @brief Inactive state clock polarity + */ +typedef enum { + I2S_INACTIVE_LOW = 0x0U, /**< Inactive state is low */ + I2S_INACTIVE_HIGH = 0x1U, /**< Inactive state is high */ +} i2s_cpol_t; + +/** + * @brief I2s standard + */ +typedef enum { + I2S_STD_PHI = 0x0U, /**< Philips standard */ + I2S_STD_MSB = 0x1U, /**< MSB standard */ + I2S_STD_LSB = 0x2U, /**< LSB standard */ + I2S_STD_PCM = 0x3U, /**< PCM standard */ +} i2s_standard_t; + +/** + * @brief I2s configuration mode + */ +typedef enum { + I2S_MASTER_TRANSMIT = 0x2U, /**< I2S master transmit mode */ + I2S_MASTER_RECEIVE = 0x3U, /**< I2S master receive mode */ +} i2s_cfg_t; + +/** + * @brief Pcm frame synchronization + */ +typedef enum { + I2S_FRAME_SHORT = 0x0U, /**< I2S PCM short frame */ + I2S_FRAME_LONG = 0x1U, /**< I2S PCM long frame */ +} i2s_pcms_t; + +/** + * @brief I2S error status + */ +typedef enum { + I2S_ERROR_NONE = 0x0U, /**< none */ + I2S_ERROR_MODF = 0x1U, /**< mode fault */ + I2S_ERROR_DMA = 0x2U, /**< crc error */ + I2S_ERROR_FRE = 0x4U, /**< frame error */ + I2S_ERROR_RXOV = 0x8U, /**< receive over error */ + I2S_ERROR_TXOV = 0x10U, /**< dma error */ + I2S_ERROR_FLAG = 0x20U, /**< interrupt flag error */ +} i2s_error_t; + +/** + * @brief interrupt control + */ +typedef enum { + I2S_IT_TXE = (1U << 0), /**< Transmit fifo empty interrupt */ + I2S_IT_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt */ + I2S_IT_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt */ + I2S_IT_RXF = (1U << 9), /**< Receive fifo full interrupt */ + I2S_IT_RXOV = (1U << 10), /**< Receive fifo overflow interrupt */ + I2S_IT_RXUD = (1U << 11), /**< Receive fifo underflow interrupt */ + I2S_IT_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt */ + I2S_IT_CRCERR = (1U << 16), /**< Crc error interrupt */ + I2S_IT_MODF = (1U << 17), /**< Mode error interrupt */ + I2S_IT_FRE = (1U << 18), /**< Frame error interrupt */ +} i2s_it_t; + +/** + * @brief I2S dma request definition + */ +typedef enum { + I2S_DMA_REQ_TX = 0U, /**< TX dma request */ + I2S_DMA_REQ_RX = 1U, /**< RX dma request */ +} i2s_dma_req_t; + +/** + * @brief interrupt flag + */ +typedef enum { + I2S_IF_TXE = (1U << 0), /**< Transmit fifo empty interrupt flag */ + I2S_IF_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt flag */ + I2S_IF_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt flag */ + I2S_IF_RXF = (1U << 9), /**< Receive fifo full interrupt flag */ + I2S_IF_RXOV = (1U << 10), /**< Receive fifo overflow interrupt flag */ + I2S_IF_RXUD = (1U << 11), /**< Receive fifo underflow interrupt flag */ + I2S_IF_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt flag */ + I2S_IF_FRE = (1U << 18), /**< Frame error interrupt flag */ +} i2s_flag_t; + +/** + * @brief I2S state structures definition + */ +typedef enum { + I2S_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + I2S_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + I2S_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + I2S_STATE_BUSY_TX = 0x11U, /**< transmit is ongoing */ + I2S_STATE_BUSY_RX = 0x21U, /**< receive is ongoing */ + I2S_STATE_BUSY_TX_RX = 0x31U, /**< transmit and receive are ongoing */ + I2S_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + I2S_STATE_ERROR = 0x04U, /**< Error */ +} i2s_state_t; + +/** + * @brief I2S status definition + */ +typedef enum { + I2S_STATUS_TXE = (1U << 0), /**< Transmit fifo empty status */ + I2S_STATUS_TXF = (1U << 1), /**< Transmit fifo full status */ + I2S_STATUS_TXOV = (1U << 2), /**< Transmit fifo overflow status */ + I2S_STATUS_TXUD = (1U << 3), /**< Transmit fifo underflow status */ + I2S_STATUS_RXE = (1U << 8), /**< Receive fifo empty status */ + I2S_STATUS_RXF = (1U << 9), /**< Receive fifo full status */ + I2S_STATUS_RXOV = (1U << 10), /**< Receive fifo overflow status */ + I2S_STATUS_RXUD = (1U << 11), /**< Receive fifo underflow status */ + I2S_STATUS_CHSIDE = (1U << 14), /**< Sound channel status */ + I2S_STATUS_BUSY = (1U << 15), /**< BUSY status */ +} i2s_status_t; + +/** + * @brief Channel side + */ +typedef enum { + I2S_SIDE_LEFT = 0U, /**< Sound channel is left */ + I2S_SIDE_RIGHT = 1U, /**< Sound channel is right */ +} i2s_ch_side_t; + +/** + * @brief I2S TXE/RXNE status definition + */ +typedef enum { + I2S_SR_TXE = 0U, /**< STAT TXE set */ + I2S_SR_RXNE = 1U, /**< STAT RXTH set */ + I2S_SR_TXE_RXNE = 2U, /**< STAT TXE and RXTH set */ +} i2s_sr_status_t; + +/** + * @brief I2S init structure definition + */ +typedef struct { + i2s_chlen_t ch_len; /**< Channel length choose */ + i2s_datalen_t data_len; /**< Data length choose */ + i2s_cpol_t polarity; /**< Inactive clock polarity */ + i2s_standard_t standard; /**< Standard choose */ + i2s_pcms_t pcm_frame; /**< PCM frame synchronization */ + type_func_t ext_clk_en; /**< Choose external clock or APB1 clock */ + uint32_t ext_clk; /**< External clock, unit is Hz */ + type_func_t mck_en; /**< Main clock output function */ + uint32_t sampling; /**< Sampling rate. eg. 192*1024-192KHz, 96*1024-96KHz */ +} i2s_init_t; + +/** + * @brief I2S handle structure definition + */ +typedef struct i2s_handle_s { + SPI_I2S_TypeDef *perh; /**< I2S registers base address */ + i2s_init_t init; /**< I2S communication parameters */ + uint16_t *tx_buf; /**< Pointer to I2S Tx transfer buffer */ + uint32_t tx_size; /**< I2S Tx transfer size */ + uint32_t tx_count; /**< I2S Tx transfer counter */ + uint16_t *rx_buf; /**< Pointer to I2S Rx transfer buffer */ + uint32_t rx_size; /**< I2S Rx Transfer size */ + uint32_t rx_count; /**< I2S Rx Transfer Counter */ + + dma_handle_t hdmatx; /**< I2S DMA handle parameters */ + dma_handle_t hdmarx; /**< I2S DMA handle parameters */ + + lock_state_t lock; /**< Locking object */ + i2s_state_t state; /**< I2S communication state */ + uint8_t side; /**< I2S channel side */ + uint32_t err_code; /**< I2S error code */ + + void (*tx_cplt_cbk)(struct i2s_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct i2s_handle_s *arg); /**< Rx completed callback */ + void (*err_cbk)(struct i2s_handle_s *arg); /**< error callback */ +} i2s_handle_t; +/** + * @} + */ + +/** @defgroup I2S_Public_Macros I2S Public Macros + * @{ + */ +#define I2S_RESET_HANDLE_STATE(x) ((x)->state = I2S_STATE_RESET) +#define I2S_ENABLE(x) (SET_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK)) +#define I2S_DISABLE(x) (CLEAR_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK)) +/** + * @} + */ + +/** @defgroup I2S_Private_Macros I2S Private Macros + * @{ + */ +#define IS_I2S(x) (((x) == I2S0) || \ + ((x) == I2S1) || \ + ((x) == I2S2)) +#define IS_I2S_CH_LEN(x) (((x) == I2S_WIDE_16) || \ + ((x) == I2S_WIDE_32)) +#define IS_I2S_DATE_LEN(x) (((x) == I2S_LEN_16) || \ + ((x) == I2S_LEN_24) || \ + ((x) == I2S_LEN_32)) +#define IS_I2S_CPOL(x) (((x) == I2S_INACTIVE_LOW) || \ + ((x) == I2S_INACTIVE_HIGH)) +#define IS_I2S_STANDARD(x) (((x) == I2S_STD_PHI) || \ + ((x) == I2S_STD_MSB) || \ + ((x) == I2S_STD_LSB) || \ + ((x) == I2S_STD_PCM)) +#define IS_I2S_PCMS(x) (((x) == I2S_FRAME_SHORT) || \ + ((x) == I2S_FRAME_LONG)) +#define IS_I2S_IT(x) (((x) == I2S_IT_TXE) || \ + ((x) == I2S_IT_TXOV) || \ + ((x) == I2S_IT_TXUD) || \ + ((x) == I2S_IT_RXF) || \ + ((x) == I2S_IT_RXOV) || \ + ((x) == I2S_IT_RXUD) || \ + ((x) == I2S_IT_RXTH) || \ + ((x) == I2S_IT_CRCERR) || \ + ((x) == I2S_IT_MODF) || \ + ((x) == I2S_IT_FRE)) +#define IS_I2S_IF(x) (((x) == I2S_IF_TXE) || \ + ((x) == I2S_IF_TXOV) || \ + ((x) == I2S_IF_TXUD) || \ + ((x) == I2S_IF_RXF) || \ + ((x) == I2S_IF_RXOV) || \ + ((x) == I2S_IF_RXUD) || \ + ((x) == I2S_IF_RXTH) || \ + ((x) == I2S_IF_FRE)) +#define IS_I2S_FLAG(x) (((x) == I2S_FLAG_TXE) || \ + ((x) == I2S_FLAG_TXF) || \ + ((x) == I2S_FLAG_TXOV) || \ + ((x) == I2S_FLAG_TXUD) || \ + ((x) == I2S_FLAG_RXE) || \ + ((x) == I2S_FLAG_RXF) || \ + ((x) == I2S_FLAG_RXOV) || \ + ((x) == I2S_FLAG_RXUD) || \ + ((x) == I2S_FLAG_CHSIDE) || \ + ((x) == I2S_FLAG_BSY)) +#define IS_I2S_STATUS(x) (((x) == I2S_STATUS_TXE) || \ + ((x) == I2S_STATUS_TXF) || \ + ((x) == I2S_STATUS_TXOV) || \ + ((x) == I2S_STATUS_TXUD) || \ + ((x) == I2S_STATUS_RXE) || \ + ((x) == I2S_STATUS_RXF) || \ + ((x) == I2S_STATUS_RXOV) || \ + ((x) == I2S_STATUS_RXUD) || \ + ((x) == I2S_STATUS_CHSIDE) || \ + ((x) == I2S_STATUS_BUSY)) +#define IS_I2S_DMA_REQ(x) (((x) == I2S_DMA_REQ_TX) || \ + ((x) == I2S_DMA_REQ_RX)) +/** + * @} + */ + +/** @addtogroup I2S_Public_Functions + * @{ + */ + +/** @addtogroup I2S_Public_Functions_Group1 + * @{ + */ + +ald_status_t ald_i2s_init(i2s_handle_t *hperh); +void ald_i2s_reset(i2s_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup I2S_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_i2s_master_send(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2s_master_recv(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_i2s_master_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size); +ald_status_t ald_i2s_master_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size); + +ald_status_t ald_i2s_master_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel); +ald_status_t ald_i2s_master_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch); +ald_status_t ald_i2s_dma_pause(i2s_handle_t *hperh); +ald_status_t ald_i2s_dma_resume(i2s_handle_t *hperh); +ald_status_t ald_i2s_dma_stop(i2s_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup I2S_Public_Functions_Group3 + * @{ + */ +void ald_i2s_irq_handler(i2s_handle_t *hperh); +void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state); +void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state); +flag_status_t ald_i2s_get_status(i2s_handle_t *hperh, i2s_status_t status); +it_status_t ald_i2s_get_it_status(i2s_handle_t *hperh, i2s_it_t it); +flag_status_t ald_i2s_get_flag_status(i2s_handle_t *hperh, i2s_flag_t flag); +flag_status_t ald_i2s_get_mask_flag_status(i2s_handle_t *hperh, i2s_flag_t flag); +void ald_i2s_clear_flag_status(i2s_handle_t *hperh, i2s_flag_t flag); +/** + * @} + */ + +/** @addtogroup I2S_Public_Functions_Group4 + * @{ + */ +i2s_state_t ald_i2s_get_state(i2s_handle_t *hperh); +uint32_t ald_i2s_get_error(i2s_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_iap.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_iap.h new file mode 100644 index 00000000..5d022316 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_iap.h @@ -0,0 +1,104 @@ +/** + ********************************************************************************* + * + * @file ald_iap.h + * @brief Header file of IAP module driver. + * + * @version V1.0 + * @date 04 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 04 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_IAP_H__ +#define __ALD_IAP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup IAP + * @{ + */ + +/** + * @defgroup IAP_Private_Macros IAP Private Macros + * @{ + */ +#define IAP_WSP_ADDR 0x10000000U +#define IAP_PE_ADDR 0x10000004U +#define IAP_WP_ADDR 0x10000008U +#define IAP_DWP_ADDR 0x1000000cU +#define IAP_WordsProgram_DF 0x10000010U +#define IAP_PageErase_DF 0x10000014U +#define IAP_WordProgram_DF 0x10000018U +#define IAP_DWordProgram_DF 0x1000001cU +/** + * @} + */ + +/** @defgroup IAP_Private_Types IAP Private Types + * @{ + */ +typedef uint32_t (*IAP_PE)(uint32_t addr); +typedef uint32_t (*IAP_WP)(uint32_t addr, uint32_t data); +typedef uint32_t (*IAP_DWP)(uint32_t addr, uint32_t data_l, uint32_t data_h); +typedef uint32_t (*IAP_WSP)(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase); +/** + * @} + */ + +/** @addtogroup IAP_Public_Functions + * @{ + */ +uint32_t ald_iap_erase_page(uint32_t addr); +uint32_t ald_iap_program_word(uint32_t addr, uint32_t data); +uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h); +uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase); +uint32_t ald_iap_erase_page_df(uint32_t addr); +uint32_t ald_iap_program_word_df(uint32_t addr, uint32_t data); +uint32_t ald_iap_program_dword_df(uint32_t addr, uint32_t data_l, uint32_t data_h); +uint32_t ald_iap_program_words_df(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_IAP_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_nand.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_nand.h new file mode 100644 index 00000000..2f693062 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_nand.h @@ -0,0 +1,222 @@ +/** + ********************************************************************************* + * + * @file ald_nand.h + * @brief Header file of EBI_NAND module driver + * + * @version V1.0 + * @date 07 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_NAND_H_ +#define __ALD_NAND_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ald_ebi.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup NAND + * @{ + */ + +/** @defgroup NAND_Public_Types NAND Public Types + * @{ + */ + +/** + * @brief NAND State structures definition + */ +typedef enum { + ALD_NAND_STATE_RESET = 0x00U, /**< NAND not yet initialized or disabled */ + ALD_NAND_STATE_READY = 0x01U, /**< NAND initialized and ready for use */ + ALD_NAND_STATE_BUSY = 0x02U, /**< NAND internal process is ongoing */ + ALD_NAND_STATE_ERROR = 0x03U /**< NAND error state */ +} ald_nand_state_t; + +/** + * @brief NAND Memory electronic signature Structure definition + */ +typedef struct { + uint8_t maker_id; /**< Maker id */ + uint8_t device_id; /**< Device id */ + uint8_t third_id; /**< Third id */ + uint8_t fourth_id; /**< Fourth id */ +} nand_id_t; + +/** + * @brief NAND Memory address Structure definition + */ +typedef struct +{ + uint16_t page; /**< NAND memory Page address */ + uint16_t plane; /**< NAND memory Plane address */ + uint16_t block; /**< NAND memory Block address */ +} nand_address_t; + +/** + * @brief NAND Memory info Structure definition + */ +typedef struct +{ + uint32_t page_size; /**< NAND memory page (without spare area) size measured in bytes */ + uint32_t spare_size; /**< NAND memory spare area size measured in bytes */ + uint32_t block_size; /**< NAND memory block size measured in number of pages */ + uint32_t block_nbr; /**< NAND memory number of total block */ + uint32_t plane_nbr; /**< NAND memory number of planes */ + uint32_t plane_size; /**< NAND memory plane size measured in number of blocks */ + type_func_t extra_cmd; /**< NAND extra command needed for Page reading mode */ +} nand_device_cfg_t; + +/** + * @brief NAND handle Structure definition + */ +typedef struct +{ + EBI_NAND_TypeDef *instance; /**< Register base address */ + ald_ebi_nand_init_t init; /**< NAND device control configuration parameters */ + lock_state_t lock; /**< NAND locking object */ + __IO ald_nand_state_t state; /**< NAND device access state */ + nand_device_cfg_t config; /**< NAND phusical characteristic information structure */ +} nand_handle_t; + +/** + * @} + */ + +/** + * @defgroup Nand_Private_Constants Nand Private Constants + * @{ + */ + +#define NAND_DEVICE1 EBI_BANK2 +#define NAND_DEVICE2 EBI_BANK3 +#define NAND_WRITE_TIMEOUT 1000U +#define CMD_AREA (1U<<16U) /* A16 = CLE high */ +#define ADDR_AREA (1U<<17U) /* A17 = ALE high */ +#define NAND_CMD_AREA_A ((uint8_t)0x00U) +#define NAND_CMD_AREA_B ((uint8_t)0x01U) +#define NAND_CMD_AREA_C ((uint8_t)0x50U) +#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U) +#define NAND_CMD_WRITE0 ((uint8_t)0x80U) +#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U) +#define NAND_CMD_ERASE0 ((uint8_t)0x60U) +#define NAND_CMD_ERASE1 ((uint8_t)0xD0U) +#define NAND_CMD_READID ((uint8_t)0x90U) +#define NAND_CMD_STATUS ((uint8_t)0x70U) +#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU) +#define NAND_CMD_RESET ((uint8_t)0xFFU) +/* NAND memory status */ +#define NAND_VALID_ADDRESS 0x00000100U +#define NAND_INVALID_ADDRESS 0x00000200U +#define NAND_TIMEOUT_ERROR 0x00000400U +#define NAND_BUSY 0x00000000U +#define NAND_ERROR 0x00000001U +#define NAND_READY 0x00000040U +/** + * @} + */ + +/** @defgroup Nand_Private_Macros Nand Private Macros + * @{ + */ +#define ARRAY_ADDRESS(x , y) ((x)->page + \ + (((x)->block + (((x)->plane) * \ + ((y)->config.plane_size))) * ((y)->config.block_size))) +#define COLUMN_ADDRESS( x) ((x)->config.page_size) +#define ADDR_1ST_CYCLE(x) (uint8_t)(x) /* 1st addressing cycle */ +#define ADDR_2ND_CYCLE(x) (uint8_t)((x) >> 8U) /* 2nd addressing cycle */ +#define ADDR_3RD_CYCLE(x) (uint8_t)((x) >> 16U) /* 3rd addressing cycle */ +#define ADDR_4TH_CYCLE(x) (uint8_t)((x) >> 24U) /* 4th addressing cycle */ +#define COLUMN_1ST_CYCLE(x) (uint8_t)(x) /* 1st Column addressing cycle */ +#define COLUMN_2ND_CYCLE(x) (uint8_t)((x) >> 8U) /* 2nd Column addressing cycle */ +/** + * @} + */ + +/** @addtogroup Nand_Public_Functions + * @{ + */ +/** @addtogroup Nand_Public_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions */ +ald_status_t ald_nand_init(nand_handle_t *hperh, ald_ebi_nand_timing_t *ctiming, ald_ebi_nand_timing_t *atiming); +ald_status_t ald_nand_deinit(nand_handle_t *hperh); +ald_status_t ald_nand_reset(nand_handle_t *hperh); +void nand_config_device(nand_handle_t *hperh, nand_device_cfg_t *pdcfg); +/** + * @} + */ +/** @addtogroup Nand_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +ald_status_t ald_nand_read_id(nand_handle_t *hperh, nand_id_t *id); +ald_status_t ald_nand_read_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr); +ald_status_t ald_nand_write_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr); +ald_status_t ald_nand_read_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr); +ald_status_t ald_nand_write_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr); +ald_status_t ald_nand_read_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr); +ald_status_t ald_nand_write_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr); +ald_status_t ald_nand_read_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr); +ald_status_t ald_nand_write_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr); +ald_status_t ald_nand_erase_block(nand_handle_t *hperh, nand_address_t *addr); +/** + * @} + */ +/** @addtogroup Nand_Public_Functions_Group3 + * @{ + */ +/* NAND Control functions */ +void ald_nand_irq_handler(nand_handle_t *hperh); +void ald_nand_irq_cbk(nand_handle_t *hperh); +uint32_t ald_nand_address_inc(nand_handle_t *hperh, nand_address_t *addr); +uint32_t ald_nand_read_status(nand_handle_t *hperh); +ald_nand_state_t ald_nand_get_state(nand_handle_t *hperh); +ald_status_t ald_nand_ecc_enable(nand_handle_t *hperh); +ald_status_t ald_nand_ecc_disable(nand_handle_t *hperh); +ald_status_t ald_nand_get_ecc(nand_handle_t *hperh, uint32_t *val, uint32_t timeout); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_nor_lcd.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_nor_lcd.h new file mode 100644 index 00000000..579c7367 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_nor_lcd.h @@ -0,0 +1,236 @@ +/** + ********************************************************************************* + * + * @file ald_nor_lcd.h + * @brief Header file of EBI_NOR_LCD module driver + * + * @version V1.0 + * @date 07 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_NOR_LCD_H_ +#define __ALD_NOR_LCD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ald_ebi.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup NOR_LCD + * @{ + */ + +/** + * @defgroup NOR_LCD_Private_Constants NOR LCD Private Constants + * @{ + */ + +/* NOR device IDs addresses */ +#define MC_ADDRESS ((uint16_t)0x0000U) +#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U) +#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU) +#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU) + +/* NOR CFI IDs addresses */ +#define CFI1_ADDRESS ((uint16_t)0x10U) +#define CFI2_ADDRESS ((uint16_t)0x11U) +#define CFI3_ADDRESS ((uint16_t)0x12U) +#define CFI4_ADDRESS ((uint16_t)0x13U) + +/* NOR operation wait timeout */ +#define NOR_TMEOUT ((uint16_t)0xFFFFU) + +/* NOR memory data width */ +#define NOR_MEMORY_8B ((uint8_t)0x0U) +#define NOR_MEMORY_16B ((uint8_t)0x1U) + +/* NOR memory device read/write start address */ +#define NOR_MEMORY_ADRESS1 EBI_BANK1_1 +#define NOR_MEMORY_ADRESS2 EBI_BANK1_2 +#define NOR_MEMORY_ADRESS3 EBI_BANK1_3 +#define NOR_MEMORY_ADRESS4 EBI_BANK1_4 + +#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555U +#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055U +#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AAU +#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555U +#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555U +#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AAU +#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555U + +#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0U +#define NOR_CMD_DATA_FIRST (uint16_t)0x00AAU +#define NOR_CMD_DATA_SECOND (uint16_t)0x0055U +#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090U +#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0U +#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080U +#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AAU +#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055U +#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010U +#define NOR_CMD_DATA_CFI (uint16_t)0x0098U +#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25U +#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29U +#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30U +#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020U +#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040U +/** + * @} + */ + +/** @defgroup NOR_LCD_Private_Macros NOR_LCD Private Macros + * @{ + */ +#define NOR_ADDR_SHIFT(NOR_ADDR, NOR_MEMORY_WIDTH_, ADDRESS) \ + ((uint32_t)(((NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B) ? \ + ((uint32_t)((NOR_ADDR) + (2U * (ADDRESS)))): \ + ((uint32_t)((NOR_ADDR) + (ADDRESS))))) +#define NOR_WRITE(ADDR, DATA) (*(__IO uint16_t *)((uint32_t)(ADDR)) = (DATA)) +/** + * @} + */ + +/** @defgroup NOR_LCD_Public_Types NOR_LCD Public Types + * @{ + */ +/** + * @brief ALD SRAM State structures definition + */ +typedef enum { + ALD_NOR_STATE_RESET = 0x00U, /**< NOR not yet initialized or disabled */ + ALD_NOR_STATE_READY = 0x01U, /**< NOR initialized and ready for use */ + ALD_NOR_STATE_BUSY = 0x02U, /**< NOR internal processing is ongoing */ + ALD_NOR_STATE_ERROR = 0x03U, /**< NOR error state */ + ALD_NOR_STATE_PROTECTED = 0x04U /**< NOR NORSRAM device write protected */ +} ald_nor_state_t; + +/** + * @brief EBI NOR Status typedef + */ +typedef enum { + ALD_NOR_STATUS_SUCCESS = 0U, /**< NOR status success */ + ALD_NOR_STATUS_ONGOING, /**< NOR status ongoing */ + ALD_NOR_STATUS_ERROR, /**< NOR status error */ + ALD_NOR_STATUS_TIMEOUT, /**< NOR status timeout */ +} nor_status_t; + +/** + * @brief EBI NOR ID typedef + */ +typedef struct { + uint16_t m_code; /**< Defines the device's manufacturer code used to identify the memory */ + uint16_t device_code1; /**< DEVICE_CODE1_ADDR code1 */ + uint16_t device_code2; /**< DEVICE_CODE1_ADDR code2 */ + uint16_t device_code3; /**< DEVICE_CODE1_ADDR code3 */ +} nor_id_t; + +/** + * @brief EBI NOR CFI typedef + */ +typedef struct { + uint16_t cfi_1; /**< NOR CFI 1 */ + uint16_t cfi_2; /**< NOR CFI 2 */ + uint16_t cfi_3; /**< NOR CFI 3 */ + uint16_t cfi_4; /**< NOR CFI 4 */ +} nor_cfi_t; + +/** + * @brief NOR handle Structure definition + */ +typedef struct { + EBI_NOR_SRAM_TypeDef *instance; /**< Register base address */ + EBI_NOR_SRAM_EXTENDED_TypeDef *ext; /**< Extended mode register base address */ + ald_ebi_nor_sram_init_t init; /**< NOR device control configuration parameters */ + lock_state_t lock; /**< NOR locking object */ + __IO ald_nor_state_t state; /**< NOR device access state */ +} nor_handle_t; +/** + * @} + */ + +/** @addtogroup NOR_Public_Functions + * @{ + */ +/** @addtogroup NOR_Public_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions */ +ald_status_t ald_nor_init(nor_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing); +ald_status_t ald_nor_deinit(nor_handle_t *hperh); +/** + * @} + */ +/** @addtogroup NOR_LCD_Public_Functions_Group2 + * @{ + */ +/* I/O operation functions */ +ald_status_t ald_nor_read_id(nor_handle_t *hperh, nor_id_t *id); +ald_status_t ald_nor_return_readmode(nor_handle_t *hperh); +ald_status_t ald_nor_read(nor_handle_t *hperh, uint32_t *addr, uint16_t *data); +ald_status_t ald_nor_program(nor_handle_t *hperh, uint32_t *addr, uint16_t *data); +ald_status_t ald_nor_read_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size); +ald_status_t ald_nor_program_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size); +ald_status_t ald_nor_erase_block(nor_handle_t *hperh, uint32_t blkaddr, uint32_t addr); +ald_status_t ald_nor_erase_chip(nor_handle_t *hperh); +ald_status_t ald_nor_read_cfi(nor_handle_t *hperh, nor_cfi_t *cfi); +/** + * @} + */ +/** @addtogroup NOR_LCD_Public_Functions_Group3 + * @{ + */ +/* Control functions */ +ald_status_t ald_nor_write_enable(nor_handle_t *hperh); +ald_status_t ald_nor_write_disable(nor_handle_t *hperh); +/** + * @} + */ +/** @addtogroup NOR_LCD_Public_Functions_Group4 + * @{ + */ +/* State functions */ +ald_nor_state_t ald_nor_get_state(nor_handle_t *hperh); +nor_status_t ald_nor_get_status(nor_handle_t *hperh, uint32_t addr, uint32_t timeout); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_NOR_LCD_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_pis.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_pis.h new file mode 100644 index 00000000..06f357e3 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_pis.h @@ -0,0 +1,727 @@ +/** + ********************************************************************************* + * + * @file ald_pis.h + * @brief Header file of PIS driver. + * + * @version V1.0 + * @date 27 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 27 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_PIS_H__ +#define __ALD_PIS_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup PIS + * @{ + */ + +/** @defgroup PIS_Public_Types PIS Public Types + * @verbatim + In PIS module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + 1. For ES32F36xx series: + TIMER0 ----> AD16C4T0 + TIMER1 ----> AD16C4T1 + TIMER2 ----> GP32C4T0 + TIMER3 ----> GP32C4T1 + + 2. For ES32F393x/ES32F336x/ES32F392x series: + TIMER0 ----> GP16C4T0 + TIMER1 ----> GP16C4T1 + TIMER2 ----> GP32C4T0 + TIMER3 ----> GP32C4T1 + @endverbatim + * @{ + */ + +/** + * @brief Producer entry + */ +typedef enum { + PIS_NON = 0x0U, /**< No async */ + PIS_GPIO_PIN0 = 0x10U, /**< Pin0, level,support async */ + PIS_GPIO_PIN1 = 0x11U, /**< Pin1, level,support async */ + PIS_GPIO_PIN2 = 0x12U, /**< Pin2, level,support async */ + PIS_GPIO_PIN3 = 0x13U, /**< Pin3, level,support async */ + PIS_GPIO_PIN4 = 0x14U, /**< Pin4, level,support async */ + PIS_GPIO_PIN5 = 0x15U, /**< Pin5, level,support async */ + PIS_GPIO_PIN6 = 0x16U, /**< Pin6, level,support async */ + PIS_GPIO_PIN7 = 0x17U, /**< Pin7, level,support async */ + PIS_GPIO_PIN8 = 0x18U, /**< Pin8, level,support async */ + PIS_GPIO_PIN9 = 0x19U, /**< Pin9, level,support async */ + PIS_GPIO_PIN10 = 0x1aU, /**< Pin10, level,support async */ + PIS_GPIO_PIN11 = 0x1bU, /**< Pin11, level,support async */ + PIS_GPIO_PIN12 = 0x1cU, /**< Pin12, level,support async */ + PIS_GPIO_PIN13 = 0x1dU, /**< Pin13, level,support async */ + PIS_GPIO_PIN14 = 0x1eU, /**< Pin14, level,support async */ + PIS_GPIO_PIN15 = 0x1fU, /**< Pin15, level,support async */ + PIS_ACMP_OUT0 = 0x30U, /**< Acmp0 output, level,support async */ + PIS_ACMP_OUT1 = 0x31U, /**< Acmp1 output, level,support async */ + PIS_DAC0_CH0 = 0x40U, /**< Dac0 channel 0, pclk2 pulse,support async */ + PIS_DAC0_CH1 = 0x41U, /**< Dac0 channel 1, pclk2 pulse,support async */ + PIS_ADC0_INSERT = 0x60U, /**< Adc0 insert, pclk2 pulse,support async */ + PIS_ADC0_NORMAL = 0x61U, /**< Adc0 normal, pclk2 pulse,support async */ + PIS_ADC0_RESERVE = 0x62U, /**< Adc0 reserve */ + PIS_LVD = 0x70U, /**< Lvd, level,support async */ + PIS_UART0_RESERVE0 = 0x80U, /**< Uart0 reserve bit 0 */ + PIS_UART0_RESERVE1 = 0x81U, /**< Uart0 reserve bit 1*/ + PIS_UART0_IRDAOUT = 0x82U, /**< Uart0 irdaout, level,support async */ + PIS_UART0_RTSOUT = 0x83U, /**< Uart0 rtsout, level,support async */ + PIS_UART0_TXOUT = 0x84U, /**< Uart0 txout, level,support async */ + PIS_UART0_SYN_SEND = 0x85U, /**< Uart0 syn send, pulse,support async */ + PIS_UART0_SYN_RECV = 0x86U, /**< Uart0 syn recv, pulse,support async */ + PIS_UART1_RESERVE0 = 0x90U, /**< Uart1 reserve bit 0 */ + PIS_UART1_RESERVE1 = 0x91U, /**< Uart1 reserve bit 1*/ + PIS_UART1_IRDA = 0x92U, /**< Uart1 irdaout, level,support async */ + PIS_UART1_RTS = 0x93U, /**< Uart1 rtsout, level,support async */ + PIS_UART1_TXOUT = 0x94U, /**< Uart1 txout, level,support async */ + PIS_UART1_SYN_SEND = 0x95U, /**< Uart1 syn send, pulse,support async */ + PIS_UART1_SYN_RECV = 0x96U, /**< Uart1 syn recv, pulse,support async */ + PIS_UART2_RESERVE0 = 0xa0U, /**< Uart2 reserve bit 0 */ + PIS_UART2_RESERVE1 = 0xa1U, /**< Uart2 reserve bit 1*/ + PIS_UART2_IRDA = 0xa2U, /**< Uart2 irdaout, level,support async */ + PIS_UART2_RTS = 0xa3U, /**< Uart2 rtsout, level,support async */ + PIS_UART2_TXOUT = 0xa4U, /**< Uart2 txout, level,support async */ + PIS_UART2_SYN_SEND = 0xa5U, /**< Uart2 syn send, pulse,support async */ + PIS_UART2_SYN_RECV = 0xa6U, /**< Uart2 syn recv, pulse,support async */ + PIS_UART3_RESERVE0 = 0xb1U, /**< Uart3 reserve bit 0 */ + PIS_UART3_RESERVE1 = 0xb2U, /**< Uart3 reserve bit 1*/ + PIS_UART3_IRDA = 0xb3U, /**< Uart3 irdaout, level,support async */ + PIS_UART3_RTS = 0xb4U, /**< Uart3 rtsout, level,support async */ + PIS_UART3_TXOUT = 0xb5U, /**< Uart3 txout, level,support async */ + PIS_UART3_SYN_SEND = 0xb6U, /**< Uart3 syn send, pulse,support async */ + PIS_UART3_SYN_RECV = 0xb7U, /**< Uart3 syn recv, pulse,support async */ + PIS_UART4_RECV = 0xc0U, /**< uart4 recv, plck1 pulse */ + PIS_UART4_SEND = 0xc1U, /**< uart4 send, plck1 pulse */ + PIS_UART4_TXOUT = 0xc2U, /**< uart4 txout, plck1 level */ + PIS_UART5_RECV = 0xd0U, /**< uart5 recv, plck1 pulse */ + PIS_UART5_SEND = 0xd1U, /**< uart5 send, plck1 pulse */ + PIS_UART5_TXOUT = 0xd2U, /**< uart5 txout, plck1 level */ + PIS_SPI0_RECV = 0xe0U, /**< Spi0 recv, plck1 pulse */ + PIS_SPI0_SEND = 0xe1U, /**< Spi0 send, plck1 pulse */ + PIS_SPI0_NE = 0xe2U, /**< Spi0 ne, plck1 level */ + PIS_SPI1_RECV = 0xf0U, /**< Spi1 recv, plck1 pulse */ + PIS_SPI1_SEND = 0xf1U, /**< Spi1 send, plck1 pulse */ + PIS_SPI1_NE = 0xf2U, /**< Spi1 ne, plck1 level */ + PIS_I2C0_RECV = 0x100U, /**< I2c0 recv, plck1 level */ + PIS_I2C0_SEND = 0x101U, /**< I2c0 send, plck1 level */ + PIS_I2C1_RECV = 0x110U, /**< I2c1 recv, plck1 level */ + PIS_I2C1_SEND = 0x111U, /**< I2c1 send, plck1 level */ + PIS_TIMER0_UPDATA = 0x120U, /**< Timer0 updata, plck1 pulse */ + PIS_TIMER0_TRIG = 0x121U, /**< Timer0 trig, plck1 pulse */ + PIS_TIMER0_INPUT_1 = 0x122U, /**< Timer0 chan1 input catch, plck1 pulse */ + PIS_TIMER0_OUTPUT_1 = 0x123U, /**< Timer0 chan1 output compare, plck1 pulse */ + PIS_TIMER0_INPUT_2 = 0x124U, /**< Timer0 chan2 input catch, plck1 pulse */ + PIS_TIMER0_OUTPUT_2 = 0x125U, /**< Timer0 chan2 output compare, plck1 pulse */ + PIS_TIMER0_INPUT_3 = 0x126U, /**< Timer0 chan3 input catch, plck1 pulse */ + PIS_TIMER0_OUTPUT_3 = 0x127U, /**< Timer0 chan3 output compare, plck1 pulse */ + PIS_TIMER0_INPUT_4 = 0x128U, /**< Timer0 chan4 input catch, plck1 pulse */ + PIS_TIMER0_OUTPUT_4 = 0x129U, /**< Timer0 chan4 output compare, plck1 pulse */ + PIS_TIMER1_UPDATA = 0x130U, /**< Timer1 updata, plck1 pulse */ + PIS_TIMER1_TRIG = 0x131U, /**< Timer1 trig, plck1 pulse */ + PIS_TIMER1_INPUT_1 = 0x132U, /**< Timer1 chan1 input catch, plck1 pulse */ + PIS_TIMER1_OUTPUT_1 = 0x133U, /**< Timer1 chan1 output compare, plck1 pulse */ + PIS_TIMER1_INPUT_2 = 0x134U, /**< Timer1 chan2 input catch, plck1 pulse */ + PIS_TIMER1_OUTPUT_2 = 0x135U, /**< Timer1 chan2 output compare, plck1 pulse */ + PIS_TIMER1_INPUT_3 = 0x136U, /**< Timer1 chan3 input catch, plck1 pulse */ + PIS_TIMER1_OUTPUT_3 = 0x137U, /**< Timer1 chan3 output compare, plck1 pulse */ + PIS_TIMER1_INPUT_4 = 0x138U, /**< Timer1 chan4 input catch, plck1 pulse */ + PIS_TIMER1_OUTPUT_4 = 0x139U, /**< Timer1 chan4 output compare, plck1 pulse */ + PIS_TIMER2_UPDATA = 0x140U, /**< Timer2 updata, plck1 pulse */ + PIS_TIMER2_TRIG = 0x141U, /**< Timer2 trig, plck1 pulse */ + PIS_TIMER2_INPUT_1 = 0x142U, /**< Timer2 chan1 input catch, plck1 pulse */ + PIS_TIMER2_OUTPUT_1 = 0x143U, /**< Timer2 chan1 output compare, plck1 pulse */ + PIS_TIMER2_INPUT_2 = 0x144U, /**< Timer2 chan2 input catch, plck1 pulse */ + PIS_TIMER2_OUTPUT_2 = 0x145U, /**< Timer2 chan2 output compare, plck1 pulse */ + PIS_TIMER2_INPUT_3 = 0x146U, /**< Timer2 chan3 input catch, plck1 pulse */ + PIS_TIMER2_OUTPUT_3 = 0x147U, /**< Timer2 chan3 output compare, plck1 pulse */ + PIS_TIMER2_INPUT_4 = 0x148U, /**< Timer2 chan4 input catch, plck1 pulse */ + PIS_TIMER2_OUTPUT_4 = 0x149U, /**< Timer2 chan4 output compare, plck1 pulse */ + PIS_TIMER3_UPDATA = 0x150U, /**< Timer3 updata, plck1 pulse */ + PIS_TIMER3_TRIG = 0x151U, /**< Timer3 trig, plck1 pulse */ + PIS_TIMER3_INPUT_1 = 0x152U, /**< Timer3 chan1 input catch, plck1 pulse */ + PIS_TIMER3_OUTPUT_1 = 0x153U, /**< Timer3 chan1 output compare, plck1 pulse */ + PIS_TIMER3_INPUT_2 = 0x154U, /**< Timer3 chan2 input catch, plck1 pulse */ + PIS_TIMER3_OUTPUT_2 = 0x155U, /**< Timer3 chan2 output compare, plck1 pulse */ + PIS_TIMER3_INPUT_3 = 0x156U, /**< Timer3 chan3 input catch, plck1 pulse */ + PIS_TIMER3_OUTPUT_3 = 0x157U, /**< Timer3 chan3 output compare, plck1 pulse */ + PIS_TIMER3_INPUT_4 = 0x158U, /**< Timer3 chan4 input catch, plck1 pulse */ + PIS_TIMER3_OUTPUT_4 = 0x159U, /**< Timer3 chan4 output compare, plck1 pulse */ + PIS_RTC_CLOCK = 0x160U, /**< Rtc clock, pulse,support async */ + PIS_RTC_ALARM = 0x161U, /**< Rtc alarm, pulse,support async */ + PIS_LPTIMER0_SYN_UPDATA = 0x170U, /**< Lptimer0 syn updata, pulse,support async */ + PIS_LPTIMER0_ASY_UPDATA = 0x171U, /**< Lptimer0 asy updata, pulse,support async */ + PIS_LPUART0_ASY_RECV = 0x180U, /**< Lpuart0 asy recv, pulse,support async */ + PIS_LPUART0_ASY_SEND = 0x181U, /**< Lpuart0 asy send, pulse,support async */ + PIS_LPUART0_SYN_RECV = 0x182U, /**< Lpuart0 syn recv, pulse,support async */ + PIS_LPUART0_SYN_SEND = 0x183U, /**< Lpuart0 syn recv, pulse,support async */ + PIS_DMA = 0x190U, /**< Dma, pulse,support async */ + PIS_ADC1_INSERT = 0x1a0U, /**< Adc1 insert, pclk2 pulse,support async */ + PIS_ADC1_NORMAL = 0x1a1U, /**< Adc1 normal, pclk2 pulse,support async */ + PIS_ADC1_RESERVE = 0x1a2U, /**< Adc1 reserve */ +} pis_src_t; + +/** + * @brief Consumer entry + */ +typedef enum { + PIS_CH12_TIMER0_ITR0 = 0x003CU, /** Tim0 internal input chan0 */ + PIS_CH13_TIMER0_ITR1 = 0x003DU, /** Tim0 internal input chan1 */ + PIS_CH14_TIMER0_ITR2 = 0x003EU, /** Tim0 internal input chan2 */ + PIS_CH15_TIMER0_ITR3 = 0x003FU, /** Tim0 internal input chan3 */ + PIS_CH12_TIMER1_ITR0 = 0x003CU, /** Tim1 internal input chan0 */ + PIS_CH13_TIMER1_ITR1 = 0x003DU, /** Tim1 internal input chan1 */ + PIS_CH14_TIMER1_ITR2 = 0x003EU, /** Tim1 internal input chan2 */ + PIS_CH15_TIMER1_ITR3 = 0x003FU, /** Tim1 internal input chan3 */ + PIS_CH12_TIMER2_ITR0 = 0x003CU, /** Tim2 internal input chan0 */ + PIS_CH13_TIMER2_ITR1 = 0x003DU, /** Tim2 internal input chan1 */ + PIS_CH14_TIMER2_ITR2 = 0x003EU, /** Tim2 internal input chan2 */ + PIS_CH15_TIMER2_ITR3 = 0x003FU, /** Tim2 internal input chan3 */ + PIS_CH12_TIMER3_ITR0 = 0x003CU, /** Tim3 internal input chan0 */ + PIS_CH13_TIMER3_ITR1 = 0x003DU, /** Tim3 internal input chan1 */ + PIS_CH14_TIMER3_ITR2 = 0x003EU, /** Tim3 internal input chan2 */ + PIS_CH15_TIMER3_ITR3 = 0x003FU, /** Tim3 internal input chan3 */ + PIS_CH6_ADC0_NORMAL = 0x0036U, /** ADC0 normal transform */ + PIS_CH7_ADC0_INSERT = 0x0037U, /** ADC0 insert transform */ + PIS_CH0_ADC1_NORMAL = 0x0030U, /** ADC1 normal transform */ + PIS_CH1_ADC1_INSERT = 0x0031U, /** ADC1 insert transform */ + PIS_CH0_LPTIM0_EXT0 = 0x0030U, /** Lptim0 external trigger 0 */ + PIS_CH1_LPTIM0_EXT1 = 0x0031U, /** Lptim0 external trigger 1 */ + PIS_CH2_LPTIM0_EXT2 = 0x0032U, /** Lptim0 external trigger 2 */ + PIS_CH3_LPTIM0_EXT3 = 0x0033U, /** Lptim0 external trigger 3 */ + PIS_CH4_LPTIM0_EXT4 = 0x0034U, /** Lptim0 external trigger 4 */ + PIS_CH5_LPTIM0_EXT5 = 0x0035U, /** Lptim0 external trigger 5 */ + PIS_CH6_LPTIM0_EXT6 = 0x0036U, /** Lptim0 external trigger 6 */ + PIS_CH7_LPTIM0_EXT7 = 0x0037U, /** Lptim0 external trigger 7 */ + PIS_CH7_DMA_REQUEST = 0x0037U, /** DMA request 7 */ + PIS_CH15_LPUART0_RXD = 0x081FU, /**< Lpuart Rx data */ + PIS_CH14_UART5_RXD = 0x071EU, /**< Uart5 Rx data */ + PIS_CH13_UART4_RXD = 0x061DU, /**< Uart4 Rx data */ + PIS_CH12_UART3_RXD = 0x031CU, /**< Uart3 Rx data */ + PIS_CH11_UART2_RXD = 0x021BU, /**< Uart2 Rx data */ + PIS_CH10_UART1_RXD = 0x011AU, /**< Uart1 Rx data */ + PIS_CH9_UART0_RXD = 0x0019U, /**< Uart0 Rx data */ + PIS_CH8_TIMER3_CH4IN = 0x1B08U, /**< Tim3 input chan4 */ + PIS_CH8_TIMER2_CH4IN = 0x1308U, /**< Tim2 input chan4 */ + PIS_CH8_SPI1_CLK = 0x0F18U, /**< Spi1 clk */ + PIS_CH7_TIMER3_CH3IN = 0x1A07U, /**< Tim3 input chan3 */ + PIS_CH7_TIMER2_CH3IN = 0x1207U, /**< Tim2 input chan3 */ + PIS_CH7_SPI1_RX = 0x0E17U, /**< Spi1 rx */ + PIS_CH6_TIMER3_CH2IN = 0x1906U, /**< Tim3 input chan2 */ + PIS_CH6_TIMER2_CH2IN = 0x1106U, /**< Tim2 input chan2 */ + PIS_CH6_SPI0_CLK = 0x0D16U, /**< SPI0 CLK */ + PIS_CH5_TIMER3_CH1IN = 0x1805U, /**< Tim3 input chan1 */ + PIS_CH5_TIMER2_CH1IN = 0x1005U, /**< Tim2 input chan1 */ + PIS_CH5_SPI0_RX = 0x0C15U, /**< SPI0 RX */ + PIS_CH4_TIMER1_CH4IN = 0x0B04U, /**< Tim1 input chan4 */ + PIS_CH4_TIMER0_CH4IN = 0x0304U, /**< Tim0 input chan4 */ + PIS_CH3_TIMER1_CH3IN = 0x0A03U, /**< Tim1 input chan3 */ + PIS_CH3_TIMER0_CH3IN = 0x0203U, /**< Tim0 input chan3 */ + PIS_CH2_TIMER1_CH2IN = 0x0902U, /**< Tim1 input chan2 */ + PIS_CH2_TIMER0_CH2IN = 0x0102U, /**< Tim0 input chan2 */ + PIS_CH1_TIMER1_CH1IN = 0x0801U, /**< Tim1 input chan1 */ + PIS_CH0_TIMER0_CH1IN = 0x0000U, /**< Tim0 input chan1 */ + PIS_CH0_TIMER0_BRKIN = 0x0400U, /**< Tim0 break in */ + PIS_CH0_TIMER1_BRKIN = 0x0C00U, /**< Tim1 break in */ + PIS_TRIG_RESERVE = 0xFFFFU, /**< Other Consumer */ +} pis_trig_t; + +/** + * @brief Clock select + */ +typedef enum { + PIS_CLK_PCLK1 = 0U, /**< APB1 peripherals clock */ + PIS_CLK_PCLK2 = 1U, /**< APB2 peripherals clock */ + PIS_CLK_SYS = 2U, /**< AHB peripherals clock */ + PIS_CLK_RESERVE = 3U, /**< reserve clock */ +} pis_clock_t; + +/** + * @brief Level select + */ +typedef enum { + PIS_EDGE_NONE = 0U, /**< None edge */ + PIS_EDGE_UP = 1U, /**< Up edge */ + PIS_EDGE_DOWN = 2U, /**< Down edge */ + PIS_EDGE_UP_DOWN = 3U, /**< Up and down edge */ +} pis_edge_t; + +/** + * @brief Output style + */ +typedef enum { + PIS_OUT_LEVEL = 0U, /**< Level */ + PIS_OUT_PULSE = 1U, /**< Pulse */ +} pis_output_t; +/** + * @brief Sync select + */ +typedef enum { + PIS_SYN_DIRECT = 0U, /**< Direct */ + PIS_SYN_LEVEL_ASY_APB1 = 1U, /**< Producer level signal and Consumer in APB1 */ + PIS_SYN_LEVEL_ASY_APB2 = 2U, /**< Producer level signal and Consumer in APB2 */ + PIS_SYN_LEVEL_ASY_AHB = 3U, /**< Producer level signal and Consumer in AHB */ + PIS_SYN_PULSE_ASY_APB1 = 4U, /**< Producer Pulse signal and Consumer in APB1 */ + PIS_SYN_PULSE_ASY_APB2 = 5U, /**< Producer Pulse signal and Consumer in APB2 */ + PIS_SYN_PULSE_ASY_AHB = 6U, /**< Producer Pulse signal and Consumer in AHB */ +} pis_syncsel_t; + +/** + * @brief Pis channel + */ +typedef enum { + PIS_CH_0 = 0U, /**< Channel 0 */ + PIS_CH_1 = 1U, /**< Channel 1 */ + PIS_CH_2 = 2U, /**< Channel 2 */ + PIS_CH_3 = 3U, /**< Channel 3 */ + PIS_CH_4 = 4U, /**< Channel 4 */ + PIS_CH_5 = 5U, /**< Channel 5 */ + PIS_CH_6 = 6U, /**< Channel 6 */ + PIS_CH_7 = 7U, /**< Channel 7 */ + PIS_CH_8 = 8U, /**< Channel 8 */ + PIS_CH_9 = 9U, /**< Channel 9 */ + PIS_CH_10 = 10U,/**< Channel 10 */ + PIS_CH_11 = 11U,/**< Channel 11 */ + PIS_CH_12 = 12U,/**< Channel 12 */ + PIS_CH_13 = 13U,/**< Channel 13 */ + PIS_CH_14 = 14U,/**< Channel 14 */ + PIS_CH_15 = 15U,/**< Channel 15 */ +} pis_ch_t; + +/** + * @brief Pis output channel + */ +typedef enum { + PIS_OUT_CH_0 = 0U, /**< Channel 0 */ + PIS_OUT_CH_1 = 1U, /**< Channel 1 */ + PIS_OUT_CH_2 = 2U, /**< Channel 2 */ + PIS_OUT_CH_3 = 3U, /**< Channel 3 */ +} pis_out_ch_t; + +/** + * @brief Indirect value,no care of it. + */ +typedef enum { + PIS_CON_0 = 0U, /**< Con 0 */ + PIS_CON_1 = 1U, /**< Con 1 */ + PIS_CON_NONE = 2U, /**< None */ +} pis_con_t; + +/** + * @brief PIS state structures definition + */ +typedef enum { + PIS_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + PIS_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + PIS_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ + PIS_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + PIS_STATE_ERROR = 0x04U, /**< Error */ +} pis_state_t; + +/** + * @brief PIS modulate target + */ +typedef enum { + PIS_UART0_TX = 0U, /**< Modulate uart0 tx */ + PIS_UART1_TX = 1U, /**< Modulate uart1 tx */ + PIS_UART2_TX = 2U, /**< Modulate uart2 tx */ + PIS_UART3_TX = 3U, /**< Modulate uart3 tx */ + PIS_LPUART0_TX = 4U, /**< Modulate lpuart0 tx */ +} pis_modu_targ_t; + +/** + * @brief PIS modulate level + */ +typedef enum { + PIS_LOW_LEVEL = 0U, /**< Modulate low level */ + PIS_HIGH_LEVEL = 1U, /**< Modulate high level */ +} pis_modu_level_t; + +/** + * @brief PIS modulate source + */ +typedef enum { + PIS_SRC_NONE = 0U, /**< Stop modulate */ + PIS_SRC_TIMER0 = 1U, /**< Modulate source is TIMER0 */ + PIS_SRC_TIMER1 = 2U, /**< Modulate source is TIMER1 */ + PIS_SRC_TIMER2 = 3U, /**< Modulate source is TIMER2 */ + PIS_SRC_TIMER3 = 4U, /**< Modulate source is TIMER3 */ + PIS_SRC_TIMER6 = 5U, /**< Modulate source is TIMER6 */ + PIS_SRC_TIMER7 = 6U, /**< Modulate source is TIMER7 */ + PIS_SRC_LPTIM0 = 7U, /**< Modulate source is LPTIM0 */ + PIS_SRC_BUZ = 8U, /**< Modulate source is buz */ +} pis_modu_src_t; + +/** + * @brief PIS modulate channel + */ +typedef enum { + PIS_TIMER_CH1 = 0U, /**< Src is TIMERx and choose channel 1 */ + PIS_TIMER_CH2 = 1U, /**< Src is TIMERx and choose channel 2 */ + PIS_TIMER_CH3 = 2U, /**< Src is TIMERx and choose channel 3 */ + PIS_TIMER_CH4 = 3U, /**< Src is TIMERx and choose channel 4 */ +} pis_modu_channel_t; + +/** + * @brief PIS input channel chose + */ +typedef enum { + PIS_NONE_INPUT = 0U, /**< Consumer input none */ + PIS_PORT_INPUT = 1U, /**< Consumer input choose external port */ + PIS_CHAN_INPUT = 2U, /**< Consumer input choose pis channel */ +} pis_input_sel_t; + +/** + * @brief PIS init structure definition + */ +typedef struct { + pis_src_t producer_src; /**< Producer entry */ + pis_output_t producer_signal; /**< Producer signal mode */ + pis_clock_t producer_clk; /**< Producer module clock */ + pis_edge_t producer_edge; /**< Producer module pin output edge */ + pis_trig_t consumer_trig; /**< Consumer entry */ + pis_clock_t consumer_clk; /**< Consumer clock */ + pis_input_sel_t input_chan; /**< Consumer input channel */ +} pis_init_t; + +/** + * @brief PIS modulate config structure definition + */ +typedef struct { + pis_modu_targ_t target; /**< Modulate target */ + pis_modu_level_t level; /**< Modulate level */ + pis_modu_src_t src; /**< Modulate src */ + pis_modu_channel_t channel; /**< Modulate channel */ +} pis_modulate_config_t; + +/** + * @brief PIS Handle Structure definition + */ +typedef struct pis_handle_s { + PIS_TypeDef *perh; /**< Register base address */ + pis_init_t init; /**< PIS required parameters */ + pis_ch_t consumer_ch; /**< Indirect value, no care of it */ + pis_con_t consumer_con; /**< Indirect value, no care of it */ + uint8_t consumer_pos; /**< Indirect value, no care of it */ + uint32_t check_info; /**< When destroy a handle ,user need check whether is right that ready to destroy */ + lock_state_t lock; /**< Locking object */ + pis_state_t state; /**< PIS operation state */ +} pis_handle_t; +/** + * @} + */ + + +/** @defgroup PIS_Private_Macros PIS Private Macros + * @{ + */ +#define IS_PIS(x) (((x) == PIS)) +#define IS_PIS_SRC(x) (((x) == PIS_NON) || \ + ((x) == PIS_GPIO_PIN0) || \ + ((x) == PIS_GPIO_PIN1) || \ + ((x) == PIS_GPIO_PIN2) || \ + ((x) == PIS_GPIO_PIN3) || \ + ((x) == PIS_GPIO_PIN4) || \ + ((x) == PIS_GPIO_PIN5) || \ + ((x) == PIS_GPIO_PIN6) || \ + ((x) == PIS_GPIO_PIN7) || \ + ((x) == PIS_GPIO_PIN8) || \ + ((x) == PIS_GPIO_PIN9) || \ + ((x) == PIS_GPIO_PIN10) || \ + ((x) == PIS_GPIO_PIN11) || \ + ((x) == PIS_GPIO_PIN12) || \ + ((x) == PIS_GPIO_PIN13) || \ + ((x) == PIS_GPIO_PIN14) || \ + ((x) == PIS_GPIO_PIN15) || \ + ((x) == PIS_ACMP_OUT0) || \ + ((x) == PIS_ACMP_OUT1) || \ + ((x) == PIS_DAC0_CH0) || \ + ((x) == PIS_DAC0_CH1) || \ + ((x) == PIS_ADC0_INSERT) || \ + ((x) == PIS_ADC0_NORMAL) || \ + ((x) == PIS_ADC0_RESERVE) || \ + ((x) == PIS_LVD) || \ + ((x) == PIS_UART0_RESERVE0) || \ + ((x) == PIS_UART0_RESERVE1) || \ + ((x) == PIS_UART0_IRDAOUT) || \ + ((x) == PIS_UART0_RTSOUT) || \ + ((x) == PIS_UART0_TXOUT) || \ + ((x) == PIS_UART0_SYN_SEND) || \ + ((x) == PIS_UART0_SYN_RECV) || \ + ((x) == PIS_UART1_RESERVE0) || \ + ((x) == PIS_UART1_RESERVE1) || \ + ((x) == PIS_UART1_IRDA) || \ + ((x) == PIS_UART1_RTS) || \ + ((x) == PIS_UART1_TXOUT) || \ + ((x) == PIS_UART1_SYN_SEND) || \ + ((x) == PIS_UART1_SYN_RECV) || \ + ((x) == PIS_UART2_RESERVE0) || \ + ((x) == PIS_UART2_RESERVE1) || \ + ((x) == PIS_UART2_IRDA) || \ + ((x) == PIS_UART2_RTS) || \ + ((x) == PIS_UART2_TXOUT) || \ + ((x) == PIS_UART2_SYN_SEND) || \ + ((x) == PIS_UART2_SYN_RECV) || \ + ((x) == PIS_UART3_RESERVE0) || \ + ((x) == PIS_UART3_RESERVE1) || \ + ((x) == PIS_UART3_IRDA) || \ + ((x) == PIS_UART3_RTS) || \ + ((x) == PIS_UART3_TXOUT) || \ + ((x) == PIS_UART3_SYN_SEND) || \ + ((x) == PIS_UART3_SYN_RECV) || \ + ((x) == PIS_UART4_RECV) || \ + ((x) == PIS_UART4_SEND) || \ + ((x) == PIS_UART4_TXOUT) || \ + ((x) == PIS_UART5_RECV) || \ + ((x) == PIS_UART5_SEND) || \ + ((x) == PIS_UART5_TXOUT) || \ + ((x) == PIS_SPI0_RECV) || \ + ((x) == PIS_SPI0_SEND) || \ + ((x) == PIS_SPI0_NE) || \ + ((x) == PIS_SPI1_RECV) || \ + ((x) == PIS_SPI1_SEND) || \ + ((x) == PIS_SPI1_NE) || \ + ((x) == PIS_I2C0_RECV) || \ + ((x) == PIS_I2C0_SEND) || \ + ((x) == PIS_I2C1_RECV) || \ + ((x) == PIS_I2C1_SEND) || \ + ((x) == PIS_TIMER0_UPDATA) || \ + ((x) == PIS_TIMER0_TRIG) || \ + ((x) == PIS_TIMER0_INPUT_1) || \ + ((x) == PIS_TIMER0_OUTPUT_1) || \ + ((x) == PIS_TIMER0_INPUT_2) || \ + ((x) == PIS_TIMER0_OUTPUT_2) || \ + ((x) == PIS_TIMER0_INPUT_3) || \ + ((x) == PIS_TIMER0_OUTPUT_3) || \ + ((x) == PIS_TIMER0_INPUT_4) || \ + ((x) == PIS_TIMER0_OUTPUT_4) || \ + ((x) == PIS_TIMER1_UPDATA) || \ + ((x) == PIS_TIMER1_TRIG) || \ + ((x) == PIS_TIMER1_INPUT_1) || \ + ((x) == PIS_TIMER1_OUTPUT_1) || \ + ((x) == PIS_TIMER1_INPUT_2) || \ + ((x) == PIS_TIMER1_OUTPUT_2) || \ + ((x) == PIS_TIMER1_INPUT_3) || \ + ((x) == PIS_TIMER1_OUTPUT_3) || \ + ((x) == PIS_TIMER1_INPUT_4) || \ + ((x) == PIS_TIMER1_OUTPUT_4) || \ + ((x) == PIS_TIMER2_UPDATA) || \ + ((x) == PIS_TIMER2_TRIG) || \ + ((x) == PIS_TIMER2_INPUT_1) || \ + ((x) == PIS_TIMER2_OUTPUT_1) || \ + ((x) == PIS_TIMER2_INPUT_2) || \ + ((x) == PIS_TIMER2_OUTPUT_2) || \ + ((x) == PIS_TIMER2_INPUT_3) || \ + ((x) == PIS_TIMER2_OUTPUT_3) || \ + ((x) == PIS_TIMER2_INPUT_4) || \ + ((x) == PIS_TIMER2_OUTPUT_4) || \ + ((x) == PIS_TIMER3_UPDATA) || \ + ((x) == PIS_TIMER3_TRIG) || \ + ((x) == PIS_TIMER3_INPUT_1) || \ + ((x) == PIS_TIMER3_OUTPUT_1) || \ + ((x) == PIS_TIMER3_INPUT_2) || \ + ((x) == PIS_TIMER3_OUTPUT_2) || \ + ((x) == PIS_TIMER3_INPUT_3) || \ + ((x) == PIS_TIMER3_OUTPUT_3) || \ + ((x) == PIS_TIMER3_INPUT_4) || \ + ((x) == PIS_TIMER3_OUTPUT_4) || \ + ((x) == PIS_RTC_CLOCK) || \ + ((x) == PIS_RTC_ALARM) || \ + ((x) == PIS_LPTIMER0_SYN_UPDATA) || \ + ((x) == PIS_LPTIMER0_ASY_UPDATA) || \ + ((x) == PIS_LPUART0_ASY_RECV) || \ + ((x) == PIS_LPUART0_ASY_SEND) || \ + ((x) == PIS_LPUART0_SYN_RECV) || \ + ((x) == PIS_LPUART0_SYN_SEND) || \ + ((x) == PIS_DMA) || \ + ((x) == PIS_ADC1_INSERT) || \ + ((x) == PIS_ADC1_NORMAL) || \ + ((x) == PIS_ADC1_RESERVE)) +#define IS_PIS_TRIG(x) (((x) == PIS_CH12_TIMER0_ITR0) || \ + ((x) == PIS_CH13_TIMER0_ITR1) || \ + ((x) == PIS_CH14_TIMER0_ITR2) || \ + ((x) == PIS_CH15_TIMER0_ITR3) || \ + ((x) == PIS_CH12_TIMER1_ITR0) || \ + ((x) == PIS_CH13_TIMER1_ITR1) || \ + ((x) == PIS_CH14_TIMER1_ITR2) || \ + ((x) == PIS_CH15_TIMER1_ITR3) || \ + ((x) == PIS_CH12_TIMER2_ITR0) || \ + ((x) == PIS_CH13_TIMER2_ITR1) || \ + ((x) == PIS_CH14_TIMER2_ITR2) || \ + ((x) == PIS_CH15_TIMER2_ITR3) || \ + ((x) == PIS_CH12_TIMER3_ITR0) || \ + ((x) == PIS_CH13_TIMER3_ITR1) || \ + ((x) == PIS_CH14_TIMER3_ITR2) || \ + ((x) == PIS_CH15_TIMER3_ITR3) || \ + ((x) == PIS_CH6_ADC0_NORMAL ) || \ + ((x) == PIS_CH7_ADC0_INSERT) || \ + ((x) == PIS_CH0_ADC1_NORMAL) || \ + ((x) == PIS_CH1_ADC1_INSERT) || \ + ((x) == PIS_CH0_LPTIM0_EXT0) || \ + ((x) == PIS_CH1_LPTIM0_EXT1) || \ + ((x) == PIS_CH2_LPTIM0_EXT2) || \ + ((x) == PIS_CH3_LPTIM0_EXT3) || \ + ((x) == PIS_CH4_LPTIM0_EXT4) || \ + ((x) == PIS_CH5_LPTIM0_EXT5) || \ + ((x) == PIS_CH6_LPTIM0_EXT6) || \ + ((x) == PIS_CH7_LPTIM0_EXT7) || \ + ((x) == PIS_CH7_DMA_REQUEST) || \ + ((x) == PIS_CH15_LPUART0_RXD) || \ + ((x) == PIS_CH14_UART5_RXD) || \ + ((x) == PIS_CH13_UART4_RXD) || \ + ((x) == PIS_CH12_UART3_RXD) || \ + ((x) == PIS_CH11_UART2_RXD) || \ + ((x) == PIS_CH10_UART1_RXD) || \ + ((x) == PIS_CH9_UART0_RXD) || \ + ((x) == PIS_CH8_TIMER3_CH4IN) || \ + ((x) == PIS_CH8_TIMER2_CH4IN) || \ + ((x) == PIS_CH8_SPI1_CLK) || \ + ((x) == PIS_CH7_TIMER3_CH3IN) || \ + ((x) == PIS_CH7_TIMER2_CH3IN) || \ + ((x) == PIS_CH7_SPI1_RX) || \ + ((x) == PIS_CH6_TIMER3_CH2IN) || \ + ((x) == PIS_CH6_TIMER2_CH2IN) || \ + ((x) == PIS_CH6_SPI0_CLK) || \ + ((x) == PIS_CH5_TIMER3_CH1IN) || \ + ((x) == PIS_CH5_TIMER2_CH1IN) || \ + ((x) == PIS_CH5_SPI0_RX) || \ + ((x) == PIS_CH4_TIMER1_CH4IN) || \ + ((x) == PIS_CH4_TIMER0_CH4IN) || \ + ((x) == PIS_CH3_TIMER1_CH3IN) || \ + ((x) == PIS_CH3_TIMER0_CH3IN) || \ + ((x) == PIS_CH2_TIMER1_CH2IN) || \ + ((x) == PIS_CH2_TIMER0_CH2IN) || \ + ((x) == PIS_CH1_TIMER1_CH1IN) || \ + ((x) == PIS_CH0_TIMER0_CH1IN) || \ + ((x) == PIS_CH0_TIMER0_BRKIN) || \ + ((x) == PIS_CH0_TIMER1_BRKIN) || \ + ((x) == PIS_TRIG_RESERVE) || \ + ((x) == PIS_CH8_SPI1_CLK)) +#define IS_PIS_CLOCK(x) (((x) == PIS_CLK_PCLK1) || \ + ((x) == PIS_CLK_PCLK2) || \ + ((x) == PIS_CLK_SYS)) +#define IS_PIS_SIGNAL_MODE(x) (((x) == PIS_OUT_LEVEL) || \ + ((x) == PIS_OUT_PULSE)) +#define IS_PIS_EDGE(x) (((x) == PIS_EDGE_NONE) || \ + ((x) == PIS_EDGE_UP) || \ + ((x) == PIS_EDGE_DOWN) || \ + ((x) == PIS_EDGE_UP_DOWN)) +#define IS_PIS_OUTPUT(x) (((x) == PIS_OUT_LEVEL) || \ + ((x) == PIS_OUT_PULSE)) +#define IS_PIS_OUPUT_CH(x) (((x) == PIS_OUT_CH_0) || \ + ((x) == PIS_OUT_CH_1) || \ + ((x) == PIS_OUT_CH_2) || \ + ((x) == PIS_OUT_CH_3)) +#define IS_PIS_MODU_TARGET(x) (((x) == PIS_UART0_TX) || \ + ((x) == PIS_UART1_TX) || \ + ((x) == PIS_UART2_TX) || \ + ((x) == PIS_UART3_TX) || \ + ((x) == PIS_LPUART0_TX)) +#define IS_PIS_MODU_LEVEL(x) (((x) == PIS_LOW_LEVEL) || \ + ((x) == PIS_HIGH_LEVEL)) +#define IS_PIS_MODU_SRC(x) (((x) == PIS_SRC_NONE) || \ + ((x) == PIS_SRC_TIMER0) || \ + ((x) == PIS_SRC_TIMER1) || \ + ((x) == PIS_SRC_TIMER2) || \ + ((x) == PIS_SRC_TIMER3) || \ + ((x) == PIS_SRC_TIMER6) || \ + ((x) == PIS_SRC_TIMER7) || \ + ((x) == PIS_SRC_LPTIM0) || \ + ((x) == PIS_SRC_BUZ)) +#define IS_PIS_MODU_CHANNEL(x) (((x) == PIS_TIMER_CH1) || \ + ((x) == PIS_TIMER_CH2) || \ + ((x) == PIS_TIMER_CH3) || \ + ((x) == PIS_TIMER_CH4)) +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions + * @{ + */ + +/** @addtogroup PIS_Public_Functions_Group1 + * @{ + */ +ald_status_t ald_pis_create(pis_handle_t *hperh); +ald_status_t ald_pis_destroy(pis_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group2 + * @{ + */ +ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch); +ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group3 + * @{ + */ +pis_state_t ald_pis_get_state(pis_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup PIS_Public_Functions_Group4 + * @{ + */ +ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_PIS_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_pmu.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_pmu.h new file mode 100644 index 00000000..a6bc2591 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_pmu.h @@ -0,0 +1,309 @@ +/** + ********************************************************************************* + * + * @file ald_pmu.h + * @brief Header file of PMU module driver. + * + * @version V1.0 + * @date 04 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 04 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_PMU_H__ +#define __ALD_PMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_syscfg.h" +#include "ald_bkpc.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup PMU + * @{ + */ + +/** @defgroup PMU_Public_Macros PMU Public Macros + * @{ + */ +#define PMU_LPSTOP_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define PMU_LPSTOP_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define PMU_FLASH_MODE_IDLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR0, PMU_CR0_SFPD_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define PMU_FLASH_MODE_WAIT() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR0, PMU_CR0_SFPD_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define PMU_MTSTOP_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define PMU_MTSTOP_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define PMU_VREF_ENABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + SET_BIT(PMU->VREFCR, PMU_VREFCR_VREFEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) +#define PMU_VREF_DISABLE() \ +do { \ + SYSCFG_UNLOCK(); \ + CLEAR_BIT(PMU->VREFCR, PMU_VREFCR_VREFEN_MSK); \ + SYSCFG_LOCK(); \ +} while (0) + +#define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS)) +/** + * @} + */ + + +/** @defgroup PMU_Public_Types PMU Public Types + * @{ + */ +/** + * @brief Low power mode + */ +typedef enum { + PMU_LP_STOP1 = 0x0U, /**< Stop1 */ + PMU_LP_STOP2 = 0x1U, /**< Stop2 */ + PMU_LP_STANDBY = 0x2U, /**< Standby */ +} pmu_lp_mode_t; + +/** + * @brief LDO_18 mode + */ +typedef enum { + PMU_LDO_18_DRV_HIGH = 0x0U, /**< High drive */ + PMU_LDO_18_DRV_LOW = 0x1U, /**< Low drive */ + PMU_LDO_18_HOLD = 0x2U, /**< Hold */ + PMU_LDO_18_OFF = 0x3U, /**< Turn off */ +} pmu_ldo_18_mode_t; + +typedef enum { + PMU_SR_WUF = (1U << 0), /**< WakeUp status */ + PMU_SR_STANDBYF = (1U << 1), /**< Standby status */ + PMU_SR_USBRDY = (1U << 2), /**< USB Readby status */ + PMU_SR_RSTAT = (1U << 3), /**< RUN/LPRUAN status */ +} pmu_status_t; + +/** + * @brief LVD voltage select + */ +typedef enum { + PMU_LVD_VOL_SEL_2_2 = 0x0U, /**< 2.2V ~ 2.25V */ + PMU_LVD_VOL_SEL_2_4 = 0x1U, /**< 2.4V ~ 2.45V */ + PMU_LVD_VOL_SEL_2_6 = 0x2U, /**< 2.6V ~ 2.65V */ + PMU_LVD_VOL_SEL_2_8 = 0x3U, /**< 2.8V ~ 2.85V */ + PMU_LVD_VOL_SEL_3_0 = 0x4U, /**< 3.0V ~ 3.05V */ + PMU_LVD_VOL_SEL_3_2 = 0x5U, /**< 3.2V ~ 3.25V */ + PMU_LVD_VOL_SEL_3_4 = 0x6U, /**< 3.4V ~ 3.45V */ + PMU_LVD_VOL_SEL_3_6 = 0x7U, /**< 3.6V ~ 3.65V */ + PMU_LVD_VOL_SEL_3_8 = 0x8U, /**< 3.8V ~ 3.85V */ + PMU_LVD_VOL_SEL_4_0 = 0x9U, /**< 4.0V ~ 4.05V */ + PMU_LVD_VOL_SEL_4_2 = 0xAU, /**< 4.2V ~ 4.25V */ + PMU_LVD_VOL_SEL_4_4 = 0xBU, /**< 4.4V ~ 4.45V */ + PMU_LVD_VOL_SEL_4_6 = 0xCU, /**< 4.6V ~ 4.65V */ + PMU_LVD_VOL_SEL_4_8 = 0xDU, /**< 4.8V ~ 4.85V */ + PMU_LVD_VOL_SEL_EXT = 0xFU, /**< Select external input. It must be 1.2V */ +} pmu_lvd_voltage_sel_t; + +/** + * @brief LVD trigger mode + */ +typedef enum { + PMU_LVD_TRIGGER_RISING_EDGE = 0x0U, /**< Rising edge */ + PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U, /**< Falling edge */ + PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U, /**< High level */ + PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U, /**< Low level */ + PMU_LVD_TRIGGER_RISING_FALLING = 0x4U, /**< Rising and falling edge */ +} pmu_lvd_trigger_mode_t; + +/** + * @brief LDO output voltage selest in low power mode + */ +typedef enum { + PMU_LDO_LPMODE_OUTPUT_0_9 = 0x0U, /**< 0.9V */ + PMU_LDO_LPMODE_OUTPUT_1_0 = 0x1U, /**< 1.0V */ + PMU_LDO_LPMODE_OUTPUT_1_1 = 0x2U, /**< 1.1V */ + PMU_LDO_LPMODE_OUTPUT_1_2 = 0x3U, /**< 1.2V */ +} pmu_ldo_lpmode_output_t; + +typedef enum { + PMU_POWER_SRAM0 = 0x1U, /**< SRAM0 */ + PMU_POWER_SRAM1 = 0x2U, /**< SRAM1 */ + PMU_POWER_SRAM2 = 0x4U, /**< SRAM2 */ + PMU_POWER_SRAM3 = 0x8U, /**< SRAM3 */ + PMU_POWER_SRAM4 = 0x10U, /**< SRAM4 */ + PMU_POWER_SRAM5 = 0x20U, /**< SRAM5 */ + PMU_POWER_CAN = 0x100U, /**< CAN */ + PMU_POWER_QSPI = 0x400U, /**< QSPI */ + PMU_POWER_USB = 0x800U, /**< USB */ + PMU_POWER_ROM = 0x1000U, /**< ROM */ +} pmu_perh_power_t; + +/** + * @} + */ + +/** + * @defgroup PMU_Private_Macros PMU Private Macros + * @{ + */ +#define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \ + ((x) == PMU_LP_STOP2) || \ + ((x) == PMU_LP_STANDBY)) +#define IS_PMU_LDO18_MODE(x) (((x) == PMU_LDO_18_DRV_HIGH) || \ + ((x) == PMU_LDO_18_DRV_LOW) || \ + ((x) == PMU_LDO_18_HOLD) || \ + ((x) == PMU_LDO_18_OFF)) +#define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || \ + ((x) == PMU_SR_STANDBYF) || \ + ((x) == PMU_SR_USBRDY) || \ + ((x) == PMU_SR_RSTAT)) +#define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_2) || \ + ((x) == PMU_LVD_VOL_SEL_2_4) || \ + ((x) == PMU_LVD_VOL_SEL_2_6) || \ + ((x) == PMU_LVD_VOL_SEL_2_8) || \ + ((x) == PMU_LVD_VOL_SEL_3_0) || \ + ((x) == PMU_LVD_VOL_SEL_3_2) || \ + ((x) == PMU_LVD_VOL_SEL_3_4) || \ + ((x) == PMU_LVD_VOL_SEL_3_6) || \ + ((x) == PMU_LVD_VOL_SEL_3_8) || \ + ((x) == PMU_LVD_VOL_SEL_4_0) || \ + ((x) == PMU_LVD_VOL_SEL_4_2) || \ + ((x) == PMU_LVD_VOL_SEL_4_4) || \ + ((x) == PMU_LVD_VOL_SEL_4_6) || \ + ((x) == PMU_LVD_VOL_SEL_4_8) || \ + ((x) == PMU_LVD_VOL_SEL_EXT)) +#define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \ + ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \ + ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \ + ((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \ + ((x) == PMU_LVD_TRIGGER_RISING_FALLING)) +#define IS_PMU_LDO_LPMODE_OUTPUT(x) (((x) == PMU_LDO_LPMODE_OUTPUT_0_9) || \ + ((x) == PMU_LDO_LPMODE_OUTPUT_1_0) || \ + ((x) == PMU_LDO_LPMODE_OUTPUT_1_1) || \ + ((x) == PMU_LDO_LPMODE_OUTPUT_1_2)) +#define IS_PMU_PERH_POWER(x) (((x) == PMU_POWER_SRAM0) || \ + ((x) == PMU_POWER_SRAM1) || \ + ((x) == PMU_POWER_SRAM2) || \ + ((x) == PMU_POWER_SRAM3) || \ + ((x) == PMU_POWER_SRAM4) || \ + ((x) == PMU_POWER_SRAM5) || \ + ((x) == PMU_POWER_CAN) || \ + ((x) == PMU_POWER_QSPI) || \ + ((x) == PMU_POWER_USB) || \ + ((x) == PMU_POWER_ROM)) + +/** + * @} + */ + +/** @addtogroup PMU_Public_Functions + * @{ + */ +/** @addtogroup PMU_Public_Functions_Group1 + * @{ + */ +/* Low power mode select */ +__STATIC_INLINE__ void ald_pmu_sleep() +{ + __WFI(); +} + +__STATIC_INLINE__ void ald_pmu_sleep_deep() +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); +} + +void ald_pmu_stop1_enter(void); +void ald_pmu_stop2_enter(void); +void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level); +void ald_pmu_ldo_12_config(type_func_t state); +void ald_pmu_ldo_18_config(pmu_ldo_18_mode_t mode); +#ifdef ES32F336x /* MCU Series: ES32F336x */ +void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state); +#endif +flag_status_t ald_pmu_get_status(pmu_status_t sr); +void ald_pmu_clear_status(pmu_status_t sr); +void ald_pmu_perh_power_config(pmu_perh_power_t perh, type_func_t state); +/** + * @} + */ +/** @addtogroup PMU_Public_Functions_Group2 + * @{ + */ +/* LVD configure */ +void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state); +void ald_lvd_irq_handler(void); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_PMU_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_qspi.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_qspi.h new file mode 100644 index 00000000..9c19c681 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_qspi.h @@ -0,0 +1,557 @@ +/***************************************************************************//** + * @file ald_qspi.h + * @brief Header file of QSPI module driver. + * @version V1.0 + * @date 09 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 09 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_QSPI_H_ +#define __ALD_QSPI_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup QSPI + * @{ + */ +/** @defgroup QSPI_Public_Types QSPI Public Types + * @{ + */ +/** + * @brief ALD QSPI state + */ +typedef enum { + QSPI_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ + QSPI_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ +} qspi_state_t; + +/** + * @brief QSPI Instruction Transfer Type + */ +typedef enum { + QSPI_XFER_SINGLE = 0x00U, /**< Instruction shifted on DQ0 only*/ + QSPI_XFER_DUAL = 0x01U, /**< Instruction,Address and data sent on DQ0 and DQ1*/ + QSPI_XFER_QUAD = 0x02U, /**< Instruction,Address and data sent on DQ0,DQ1 and DQ2*/ +} qspi_xfer_t; + +/** + * @brief QSPI Indirect Access SRAM fill level + */ +typedef enum { + QSPI_SRAM_RD = 0U, /**< SRAM fill level(indirect write partition)in units of words(4bytes)*/ + QSPI_SRAM_WR = 1U, /**< SRAM fill level(indirect read partition)in units of words(4bytes)*/ +} qspi_sram_t; + +/** + * @brief QSPI Clock Phase + */ +typedef enum { + QSPI_CPHA_1E = 0U, /**< First edge*/ + QSPI_CPHA_2E = 1U, /**< Second edge*/ +} qspi_cpha_t; + +/** + * @brief QSPI_Clock_Polarity QSPI Clock Polarity + */ +typedef enum { + QSPI_CPOL_L = 0U, /**< QSPI clock polarity low */ + QSPI_CPOL_H = 1U, /**< QSPI clock polarity high */ +} qspi_cpol_t; + +/** + * @brief QSPI peripheral select decode + */ +typedef enum { + QSPI_SINGLE_CHIP = 0x0U, /**< Only 1 of 4 selects n_ss_out[3:0] is active */ + QSPI_MULTI_CHIP = 0x1U, /**< Allow external 4-to-16 decode */ +} qspi_nss_decode_t; + +/** + * @brief QSPI_Baud_Rate_Clock_Prescaler QSPI Baud Rate Clock Prescaler + */ +typedef enum { + QSPI_DIV_2 = 0x0U, /**< Master mode baud rate dibisor 2*/ + QSPI_DIV_4 = 0x1U, /**< Master mode baud rate dibisor 4*/ + QSPI_DIV_6 = 0x2U, /**< Master mode baud rate dibisor 6*/ + QSPI_DIV_8 = 0x3U, /**< Master mode baud rate dibisor 8*/ + QSPI_DIV_10 = 0x4U, /**< Master mode baud rate dibisor 10*/ + QSPI_DIV_12 = 0x5U, /**< Master mode baud rate dibisor 12*/ + QSPI_DIV_14 = 0x6U, /**< Master mode baud rate dibisor 14*/ + QSPI_DIV_16 = 0x7U, /**< Master mode baud rate dibisor 16*/ + QSPI_DIV_18 = 0x8U, /**< Master mode baud rate dibisor 18*/ + QSPI_DIV_20 = 0x9U, /**< Master mode baud rate dibisor 20*/ + QSPI_DIV_22 = 0xAU, /**< Master mode baud rate dibisor 22*/ + QSPI_DIV_24 = 0xBU, /**< Master mode baud rate dibisor 24*/ + QSPI_DIV_26 = 0xCU, /**< Master mode baud rate dibisor 26*/ + QSPI_DIV_28 = 0xDU, /**< Master mode baud rate dibisor 28*/ + QSPI_DIV_30 = 0xEU, /**< Master mode baud rate dibisor 30*/ + QSPI_DIV_32 = 0xFU, /**< Master mode baud rate dibisor 32*/ +} qspi_clk_div_t; + +/** + * @brief QSPI Peripheral chip select decode + */ +typedef enum { + QSPI_CS_NSS0 = 0x0U, /**< NSS0 active*/ + QSPI_CS_NSS1 = 0x1U, /**< NSS1 active*/ + QSPI_CS_NSS2 = 0x3U, /**< NSS2 active*/ + QSPI_CS_NSS3 = 0x7U, /**< NSS3 active*/ +} qspi_nss_t; + +/** + *@brief Size of flash connected to CS[x](x = 0 ~ 3)pin + */ +typedef enum { + QSPI_NSS_512M = 0x0U, /**< size of 512Mb*/ + QSPI_NSS_1G = 0x1U, /**< size of 1Gb*/ + QSPI_NSS_2G = 0x2U, /**< size of 2Gb*/ + QSPI_NSS_4G = 0x3U, /**< size of 3Gb*/ +} qspi_nss_size_t; + +/** + *@brief Qspi external flash device configuration + */ +typedef struct { + uint8_t addr; /**< Peripheral address */ + uint16_t page; /**< Flash page size */ + uint16_t blk; /**< Flash block size */ + qspi_nss_size_t cs0; /**< NSS0 flash size */ + qspi_nss_size_t cs1; /**< NSS1 flash size */ + qspi_nss_size_t cs2; /**< NSS2 flash size */ + qspi_nss_size_t cs3; /**< NSS3 flash size */ +} qspi_device_size_t; + +/** + * @brief QSPI Sample Edge Selection + */ +typedef enum { + QSPI_FALLING_E = 0x0U, /**< Data outputs from flash are sampled on falling edge of the ref_clk*/ + QSPI_RISING_E = 0x1U, /**< Data outputs from flash are sampled on rising edge of the ref_clk*/ +} qspi_data_sampled_t; + +/** + * @brief Flash write-protected blocks configuration. + */ +typedef struct { + uint32_t lowblk; /**< the lower block in the range of blocks that is to be locked from writing*/ + uint32_t upblk; /**< upper block in the range of blocks that is to be locked from writing*/ +} qspi_wr_protect_t; + +/** + * @brief QSPI STIG Command Structure. + */ +typedef struct { + uint32_t code; /**< command op-code*/ + uint32_t rd_len; /**< Number of Read Data Bytes*/ + uint32_t addr_len; /**< Number of Address Bytes*/ + uint32_t wr_len; /**< Number of Write Data Bytes*/ + uint32_t d_sycle; /**< Number of dummy cycles*/ + type_func_t mode_bit; /**< Mode Bit Configuration register are sent following the address bytes*/ + type_func_t op_addr; /**< If opcde requires an address*/ + uint32_t val; /**< Mode bits,sent to device following the address*/ + uint32_t addr; /**< Flash opcde address*/ + void *rd_buf; /**< Buffer for read data*/ + void *wr_buf; /**< Buffer with data to write*/ +} qspi_stig_cmd_t; + +/** + * @brief QSPI base initialization structure. + */ +typedef struct { + qspi_clk_div_t clkdiv; /**< QSPI Baud Rate Clock Prescaler*/ + type_func_t wrppin; /**< QSPI Set Write Protect Pin*/ + qspi_nss_decode_t nssdcode; /**< QSPI Peripheral Select Decode*/ + qspi_nss_t chipsel; /**< QSPI Peripheral Select Line*/ + qspi_cpol_t cpol; /**< QSPI polarity */ + qspi_cpha_t chpa; /**< QSPI phase */ +} qspi_init_t; + +/** + * @brief QSPI legacy initialization structure. + */ +typedef struct { + uint8_t tx_thrd; /**< Tx FIFO threshhold */ + uint8_t rx_thrd; /**< Rx FIFO threshhold */ +} qspi_legacy_cfg_t; + +/** + * @brief QSPI Device Read Instruction Configuration structure. + */ +typedef struct { + uint8_t rdcde; /**< Read opcode in non-xip mode*/ + uint8_t dcyles; /**< Number of dummy read clock cycles*/ + uint8_t mbitval; /**< Mode bits,sent to device following the address bytes*/ + type_func_t ddrbit; /**< Opcode from bit 7 to 0 is compliant with DDR command*/ + type_func_t modebit; /**< Enable mode bit*/ + qspi_xfer_t addxfer; /**< Transfer type used for address*/ + qspi_xfer_t datxfer; /**< Transfer type used for data*/ + qspi_xfer_t instxfer; /**< Transfer type used for instruction*/ +} qspi_read_cfg_t; + +/** + * @brief QSPI Device Write Instruction Configuration structure. + */ +typedef struct { + uint8_t wrcde; /**< Write opcode*/ + uint8_t dcyles; /**< Number of dummy read clock cycles*/ + qspi_xfer_t addxfer; /**< Transfer type used for address*/ + qspi_xfer_t datxfer; /**< Transfer type used for data*/ + qspi_xfer_t instxfer; /**< Transfer type used for instruction*/ + type_func_t autowel; /**< Turn off automatic*/ +} qspi_write_cfg_t; + +/** + * @brief QSPI Indirect Configuration structure.involatile parameters + */ +typedef struct { + uint32_t saddr; /**< Flash start address, commence write operation*/ + uint32_t wrlen; /**< Number of indirect write bytes*/ +} qspi_indac_wr_cfg_t; + +typedef struct { + uint32_t saddr; /**< FLASH start address, commence read operation*/ + uint32_t rdlen; /**< Number of indirect read bytes*/ +} qspi_indac_rd_cfg_t; + +typedef struct { + uint32_t srampt; /**< Defines the size of the indirect read partion in the SRAM*/ + uint32_t trgaddr; /**< Indirect trigger address which is used by AHB controller*/ + uint32_t trgrng; /**< The offset of indirect trigger address*/ + uint32_t wrwmark; /**< Maximum fill level of SRAM before a DMA, 0xFFFFFFFF disable the function*/ + uint32_t rdwmark; /**< Fill level passes watermark, an interrupt generated*/ +} qspi_indac_cfg_t; + +/** + * @brief QSPI DAC configuration. + */ +typedef struct { + type_func_t dtrprtcol; /**< DTR protocol*/ + type_func_t ahbdecoder; /**< AHB decoder, direct access mode only*/ + type_func_t xipimmed; /**< QSPI Enter XIP Immediately*/ + type_func_t xipnextrd; /**< QSPI Enter XIP Next Read*/ + type_func_t addrremap; /**< Enable AHB address re-mapping*/ + uint32_t remapaddr; /**< Remap incoming AHB address to different address*/ + type_func_t dmaperh; /**< QSPI dma interface*/ + qspi_read_cfg_t rdinit; /**< QSPI read instruction configuration*/ + qspi_write_cfg_t wrinit; /**< QSPI write instruction configuration*/ +} qspi_dac_cfg_t; + +/** + * @brief QSPI Handle Structure definition + */ +typedef struct { + QSPI_TypeDef *perh; /**< QSPI registers base address*/ + qspi_init_t init; /**< QSPI communication parameters*/ + uint8_t *tx_buf; /**< Pointer to QSPI transfer buffer */ + uint16_t tx_size; /**< QSPI transfer size */ + uint16_t tx_cnt; /**< QSPI transfer counter */ + uint8_t *rx_buf; /**< Pointer to QSPI receive buffer */ + uint16_t rx_size; /**< QSPI receive size */ + uint16_t rx_cnt; /**< QSPI receive counter */ + + dma_handle_t hdma; /**< QSPI Rx/Tx DMA Handle parameters*/ + + qspi_state_t state; /**< QSPI communication state */ + __IO lock_state_t lock; /**< Locking object*/ +} qspi_handle_t; + +/** + * @brief Defines command to be executed using STIG mechanism. + */ +typedef struct { + uint32_t ccsot; /**< range [0 ~ 255]*/ + uint32_t cseot; /**< range [0 ~ 255]*/ + uint32_t csdads; /**< range [0 ~ 255]*/ + uint32_t csda; /**< range [0 ~ 255]*/ +} qspi_dly_cfg_t; + +/** + * @brief QSPI Read Data Capture Configuration. + */ +typedef struct { + uint32_t dlytd; /**< Delay transmitted data [0 ~ 15]*/ + uint32_t dlydcl; /**< Delay the read data capturing logic [0 ~ 15]*/ + qspi_data_sampled_t smpledge; /**< Sample edge selection(of the flash data outputs) @ref qspi_data_sampled_t*/ +} qspi_data_capture_cfg_t; + +/** + * @brief QSPI Indirect Write Progress Status. + */ +typedef enum { + QSPI_INDWR_PROGRESS = (1U << 2), /**< Indirect write operation in progress*/ + QSPI_INDWR_CPLT = (1U << 5), /**< Indirect write completion*/ +} qspi_indwr_status_t; + +/** + * @brief QSPI Indirect Read Progress Status. + */ +typedef enum { + QSPI_INDRD_PROGRESS = (1U << 2), /**< Indirect read operation in progress*/ + QSPI_RD_CPLT = (1U << 5), /**< Indirect read completion*/ +} qspi_indrd_flag_t; + +/** + * @brief QSPI Auto Poll Configuration Struction. + */ +typedef struct { + uint32_t opcode; /**< Automatically poll operation code */ + uint32_t indx; /**< Polling bit index */ + uint32_t polarity; /**< Defines polling polarity */ + uint32_t validcnt; /**< Expect true result times */ + uint32_t repdly; /**< Defines additional delay for maintain de-assert during auto-polling phase */ + uint32_t polexpcnt; /**< Poll cycles,which polling expiration interrupt is generated*/ +} qspi_auto_poll_t; + +/** + *@brief QSPI_Interrupt_definition QSPI Interrupt Definition + */ +typedef enum { + QSPI_IT_POLLF = (1U << 13), /**< Programmed polls cycles expired flag */ + QSPI_IT_INDRSFF = (1U << 12), /**< Indirect read partition of SRAM is full flag */ + QSPI_IT_SRFFF = (1U << 11), /**< Small rx FIFO full flag */ + QSPI_IT_SRFNEF = (1U << 10), /**< Small rx FIFO not empty flag */ + QSPI_IT_STFFF = (1U << 9), /**< Small tx FIFO full flag */ + QSPI_IT_STFNFF = (1U << 8), /**< Small tx FIFO not full flag */ + QSPI_IT_ROVF = (1U << 7), /**< Receive overflow flag */ + QSPI_IT_INDTWF = (1U << 6), /**< Indirect transfer watermark level breached flag */ + QSPI_IT_AHBAEF = (1U << 5), /**< Illegal AHB access detected flag */ + QSPI_IT_WPAF = (1U << 4), /**< Write to protected area was rejected flag */ + QSPI_IT_INDRRF = (1U << 3), /**< Indirect operation could not be accepted flag */ + QSPI_IT_INDCF = (1U << 2), /**< Controller has completed last triggered indirect operation flag */ + QSPI_IT_UDFF = (1U << 1), /**< Underflow detected flag */ + QSPI_IT_MODFF = (1U << 0), /**< Mode fail M flag */ +} qspi_it_t; +/** + * @brief QSPI_Flag_definition QSPI Flag Definition + */ +typedef enum { + QSPI_IF_POLLF = (1U << 13), /**< Programmed polls cycles expired flag */ + QSPI_IF_INDRSFF = (1U << 12), /**< Indirect read partition of SRAM is full flag */ + QSPI_IF_SRFFF = (1U << 11), /**< Small rx FIFO full flag */ + QSPI_IF_SRFNEF = (1U << 10), /**< Small rx FIFO not empty flag */ + QSPI_IF_STFFF = (1U << 9), /**< Small tx FIFO full flag */ + QSPI_IF_STFNFF = (1U << 8), /**< Small tx FIFO not full flag */ + QSPI_IF_ROVF = (1U << 7), /**< Receive overflow flag */ + QSPI_IF_INDTWF = (1U << 6), /**< Indirect transfer watermark level breached flag */ + QSPI_IF_AHBAEF = (1U << 5), /**< Illegal AHB access detected flag */ + QSPI_IF_WPAF = (1U << 4), /**< Write to protected area was rejected flag */ + QSPI_IF_INDRRF = (1U << 3), /**< Indirect operation could not be accepted flag */ + QSPI_IF_INDCF = (1U << 2), /**< Controller has completed last triggered indirect operation flag */ + QSPI_IF_UDFF = (1U << 1), /**< Underflow detected flag */ + QSPI_IF_MODFF = (1U << 0), /**< Mode fail M flag */ +} qspi_flag_t; +/** + * @} + */ + +/** @defgroup QSPI_Private_Macros QSPI Private Macros + * @{ + */ +#define IS_QSPI_SRAM_PARTITION(x) ((x) < 255) +#define IS_QSPI_INDIRECT_TRIGGER_RANGE(x) (((x) < 16)) +#define IS_QSPI_INDIRECT_READ_WATERMARK(x) ((x) < 512) +#define IS_QSPI_INDIRECT_SRAM_FILL_TYPE(x) (((x) == QSPI_SRAM_RD) || ((x) == QSPI_SRAM_WR)) +#define IS_QSPI_INDIRECT_READ_STATUS(x) (((x) == QSPI_INDRD_PROGRESS) || ((x) == QSPI_RD_CPLT)) +#define IS_QSPI_INDIRECT_WRITE_STATUS(x) (((x) == QSPI_INDWR_PROGRESS) || ((x) == QSPI_INDWR_CPLT)) +#define IS_QSPI_DEVICE_DELAY_CCSOT(x) ((x) < 256) +#define IS_QSPI_DEVICE_DELAY_CSEOT(x) ((x) < 256) +#define IS_QSPI_DEVICE_DELAY_CSDADS(x) ((x) < 256) +#define IS_QSPI_DEVICE_DELAY_CSDA(x) ((x) < 256) + +#define IS_QSPI_READ_DATA_CAPTURE_DELAY_READ(x) ((x) < 16) +#define IS_QSPI_READ_DATA_SAMPLE_EDGE(x) (((x) == QSPI_FALLING_E) || \ + ((x) == QSPI_RISING_E)) +#define IS_QSPI_READ_DATA_DELAY_TRANSMIT(x) ((x) < 16) +#define IS_QSPI_ALL(x) ((x) == QSPI) +#define IS_QSPI_DCYLES(x) ((x) <= 31) + +#define IS_QSPI_ADDR_SIZE(x) ((x) <= 15) +#define IS_QSPI_PAGE_SIZE(x) ((x) <= 0xfff) +#define IS_QSPI_BLOCK_SIZE(x) ((x) <= 0x1f) +#define IS_QSPI_NSS_SIZE(x) ((x) <= 3) + +#define IS_QSPI_XFER_TYPE(x) (((x) == QSPI_XFER_SINGLE) || \ + ((x) == QSPI_XFER_DUAL) || \ + ((x) == QSPI_XFER_QUAD)) +#define IS_QSPI_DDR_BIT_ENABLE(x) (((x) == QSPI_READ_DDR_BIT_DISABLE) || \ + ((x) == QSPI_READ_DDR_BIT_ENABLE)) +#define IS_QSPI_MODE_BIT_ENABLE(x) (((x) == QSPI_READ_INST_MODE_BIT_DISABLE) || \ + ((x) == QSPI_READ_INST_MODE_BIT_ENABLE)) +#define IS_QSPI_RD_OPCODE(x) (((x) < 0xFF)) +#define IS_QSPI_WR_OPCODE(x) (((x) < 0xFF)) +#define IS_QSPI_CLOCK_PRESCALER(x) (((x) == QSPI_DIV_2) || \ + ((x) == QSPI_DIV_4) || \ + ((x) == QSPI_DIV_6) || \ + ((x) == QSPI_DIV_8) || \ + ((x) == QSPI_DIV_10) || \ + ((x) == QSPI_DIV_12) || \ + ((x) == QSPI_DIV_14) || \ + ((x) == QSPI_DIV_16) || \ + ((x) == QSPI_DIV_18) || \ + ((x) == QSPI_DIV_20) || \ + ((x) == QSPI_DIV_22) || \ + ((x) == QSPI_DIV_24) || \ + ((x) == QSPI_DIV_26) || \ + ((x) == QSPI_DIV_28) || \ + ((x) == QSPI_DIV_30) || \ + ((x) == QSPI_DIV_32)) +#define IS_QSPI_CLOCK_PHASE(x) (((x) == QSPI_CPHA_1E) || \ + ((x) == QSPI_CPHA_2E)) +#define IS_QSPI_CLOCK_POLARITY(x) (((x) == QSPI_CPOL_L) || \ + ((x) == QSPI_CPOL_H)) +#define IS_QSPI_IF(x) (((x) == QSPI_IF_POLLF) || \ + ((x) == QSPI_IF_INDRSFF) || \ + ((x) == QSPI_IF_SRFFF) || \ + ((x) == QSPI_IF_SRFNEF) || \ + ((x) == QSPI_IF_STFFF) || \ + ((x) == QSPI_IF_STFNFF) || \ + ((x) == QSPI_IF_ROVF) || \ + ((x) == QSPI_IF_INDTWF) || \ + ((x) == QSPI_IF_AHBAEF) || \ + ((x) == QSPI_IF_WPAF) || \ + ((x) == QSPI_IF_INDRRF) || \ + ((x) == QSPI_IF_INDCF) || \ + ((x) == QSPI_IF_UDFF) || \ + ((x) == QSPI_IF_MODFF)) +#define IS_QSPI_IT(x) (((x) == QSPI_IT_POLLF) || \ + ((x) == QSPI_IT_INDRSFF) || \ + ((x) == QSPI_IT_SRFFF) || \ + ((x) == QSPI_IT_SRFNEF) || \ + ((x) == QSPI_IT_STFFF) || \ + ((x) == QSPI_IT_STFNFF) || \ + ((x) == QSPI_IT_ROVF) || \ + ((x) == QSPI_IT_INDTWF) || \ + ((x) == QSPI_IT_AHBAEF) || \ + ((x) == QSPI_IT_WPAF) || \ + ((x) == QSPI_IT_INDRRF) || \ + ((x) == QSPI_IT_INDCF) || \ + ((x) == QSPI_IT_UDFF) || \ + ((x) == QSPI_IT_MODFF)) + +/** + * @} + */ + +/** + * @defgroup QSPI_Public_Macros QSPI Public Macros + * @{ + */ +#define QSPI_MEMORY_ADDRESS 0x90000000U +#define QSPI_SRAM_SIZE 255U +#define QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5s */ +#define QSPI_SRAM_DEPTH 0xFFU +#define QSPI_DAC_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK) +#define QSPI_DAC_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK) +#define QSPI_LEGACY_SPI_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK) +#define QSPI_LEGACY_SPI_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK) +#define QSPI_WRITE_PROTECT_ENABLE(hperh) SET_BIT((hperh)->perh->WPCR, QSPI_WPCR_WPEN_MSK); +#define QSPI_WRITE_PROTECT_DISABLE(hperh) CLEAR_BIT((hperh)->perh->WPCR, QSPI_WPCR_WPEN_MSK); +#define QSPI_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_EN_MSK) +#define QSPI_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_EN_MSK) +#define QSPI_AUTO_POLL_ENABLE(hperh) CLEAR_BIT((hperh)->perh->WCR, QSPI_WCR_PDIS_MSK) +#define QSPI_AUTO_POLL_DISABLE(hperh) SET_BIT((hperh)->perh->WCR, QSPI_WCR_PDIS_MSK) +#define QSPI_DMA_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_DMAEN_MSK) +#define QSPI_DMA_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DMAEN_MSK) +#define QSPI_CANCEL_INDIRECT_READ(hperh) SET_BIT((hperh)->perh->IRTR, QSPI_IRTR_RDDIS_MSK) +/** + * @} + */ + +/** @addtogroup QSPI_Public_Functions + * @{ + */ + +/** @addtogroup QSPI_Public_Functions_Group1 + * @{ + */ +/* QSPI basic execution functions */ +void ald_qspi_init(qspi_handle_t *hperh); +uint32_t ald_qspi_dac_rd(uint32_t addr); +void ald_qspi_dac_wr(uint32_t addr, uint32_t dat); +ald_status_t ald_qspi_read_config(qspi_handle_t* hperh, const qspi_read_cfg_t * rdcfg); +ald_status_t ald_qspi_write_config(qspi_handle_t* hperh, const qspi_write_cfg_t * wrcfg); +ald_status_t ald_qspi_device_delay_config(qspi_handle_t * hperh, qspi_dly_cfg_t *dlycfg); +ald_status_t ald_qspi_read_data_capture_config(qspi_handle_t * hperh, qspi_data_capture_cfg_t *dtcptcfg); +ald_status_t ald_qspi_device_size_config(qspi_handle_t *hperh, qspi_device_size_t * devcfg); +ald_status_t qspi_dac_config(qspi_handle_t * hperh, qspi_dac_cfg_t * dcfg); +/** + * @} + */ +/** @addtogroup QSPI_Public_Functions_Group2 + * @{ + */ +/* QSPI indirect and stig access execution functions */ +ald_status_t ald_qspi_indac_config(qspi_handle_t * hperh, qspi_indac_cfg_t *indcfg); +ald_status_t ald_qspi_indac_transmit_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size); +ald_status_t ald_qspi_indac_transmit_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size); +ald_status_t ald_qspi_indac_read_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size); +ald_status_t ald_qspi_indac_read_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size); +ald_status_t ald_qspi_execute_stig_cmd(qspi_handle_t* hperh, const qspi_stig_cmd_t * scmd); +#ifdef ALD_DMA +ald_status_t ald_qspi_indac_transmit_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *psrc, uint16_t size); +ald_status_t ald_qspi_indac_read_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *pdbuf, uint16_t size); +#endif +/** + * @} + */ +/** @addtogroup QSPI_Public_Functions_Group3 + * @{ + */ +/* QSPI status functions */ +flag_status_t qspi_get_flag_status(qspi_handle_t *hperh, qspi_flag_t flag); +void ald_qspi_clear_it_flag(qspi_handle_t *hperh, qspi_flag_t flag); +uint16_t qspi_read_sram_fill_level(qspi_handle_t * hperh, qspi_sram_t srt); +void ald_qspi_write_proect_config(qspi_handle_t * hperh, qspi_wr_protect_t* wpcfg); +void ald_qspi_write_proect_inverse(qspi_handle_t * hperh, type_func_t state); +ald_status_t ald_qspi_auto_poll(qspi_handle_t *hperh, qspi_auto_poll_t* apcfg); +void ald_qspi_irq_handler(qspi_handle_t *hperh); +void ald_qspi_interrupt_config(qspi_handle_t *hperh, qspi_it_t it, type_func_t state); +void ald_qspi_legacy_config(qspi_handle_t* hperh, const qspi_legacy_cfg_t *config); +flag_status_t qspi_indwr_get_status(qspi_handle_t *hperh, qspi_indwr_status_t status); +ald_status_t qspi_indwr_wait_flag(qspi_handle_t *hperh, qspi_indwr_status_t flag, flag_status_t status, uint32_t timeout); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif /* __ALD_QSPI_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_rmu.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_rmu.h new file mode 100644 index 00000000..8dc9c330 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_rmu.h @@ -0,0 +1,314 @@ +/** + ********************************************************************************* + * + * @file ald_rmu.h + * @brief Header file of RMU module driver. + * + * @version V1.0 + * @date 04 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 04 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_RMU_H__ +#define __ALD_RMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup RMU + * @{ + */ + +/** @defgroup RMU_Public_Types RMU Public Types + * @{ + */ +/** + * @brief RMU BOR fliter + */ +typedef enum { + RMU_BORFLT_1 = 0x1U, /**< 1 cycle */ + RMU_BORFLT_2 = 0x2U, /**< 2 cycles */ + RMU_BORFLT_3 = 0x3U, /**< 3 cycles */ + RMU_BORFLT_4 = 0x4U, /**< 4 cycles */ + RMU_BORFLT_5 = 0x5U, /**< 5 cycles */ + RMU_BORFLT_6 = 0x6U, /**< 6 cycles */ + RMU_BORFLT_7 = 0x7U, /**< 7 cycles */ +} rmu_bor_filter_t; + +/** + * @brief RMU BOR voltage + */ +typedef enum { + RMU_VOL_NONE = 0x0U, /**< Disable */ + RMU_VOL_2_0 = 0x1U, /**< 2.0V */ + RMU_VOL_2_2 = 0x2U, /**< 2.2V */ + RMU_VOL_2_4 = 0x3U, /**< 2.4V */ + RMU_VOL_2_6 = 0x4U, /**< 2.6V */ + RMU_VOL_2_8 = 0x5U, /**< 2.8V */ + RMU_VOL_3_0 = 0x6U, /**< 3.0V */ + RMU_VOL_3_2 = 0x7U, /**< 3.2V */ + RMU_VOL_3_4 = 0x8U, /**< 3.4V */ + RMU_VOL_3_6 = 0x9U, /**< 3.6V */ + RMU_VOL_3_8 = 0xAU, /**< 3.8V */ + RMU_VOL_4_0 = 0xBU, /**< 4.0V */ + RMU_VOL_4_2 = 0xCU, /**< 4.2V */ + RMU_VOL_4_4 = 0xDU, /**< 4.4V */ + RMU_VOL_4_6 = 0xEU, /**< 4.6V */ + RMU_VOL_4_8 = 0xFU, /**< 4.8V */ +} rmu_bor_vol_t; + +/** + * @brief RMU reset status + */ +typedef enum { + RMU_RST_POR = (1U << 0), /**< POR */ + RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */ + RMU_RST_BOR = (1U << 2), /**< BOR */ + RMU_RST_NMRST = (1U << 3), /**< NMRST */ + RMU_RST_IWDT = (1U << 4), /**< IWDT */ + RMU_RST_WWDT = (1U << 5), /**< WWDT */ + RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */ + RMU_RST_CHIP = (1U << 7), /**< CHIP */ + RMU_RST_MCU = (1U << 8), /**< MCU */ + RMU_RST_CPU = (1U << 9), /**< CPU */ + RMU_RST_CFG = (1U << 10), /**< CFG */ + RMU_RST_CFGERR = (1U << 16), /**< CFG Error */ + RMU_RST_ALL = (0xFFFFFU), /**< ALL */ +} rmu_state_t; + +/** + * @brief RMU periperal select bit + * @verbatim + In this module, for the convenience of code maintenance, + TIMERx is used to indicate the sequence of the timer peripheral. + Different product series TIMERx represent different meanings: + 1. For ES32F36xx series: + TIMER0 ----> AD16C4T0 + TIMER1 ----> AD16C4T1 + TIMER2 ----> GP32C4T0 + TIMER3 ----> GP32C4T1 + TIMER4 ----> BS16T0 + TIMER5 ----> BS16T1 + TIMER6 ----> GP16C4T0 + TIMER7 ----> GP16C4T1 + + 2. For ES32F393x/ES32F336x/ES32F392x series: + TIMER0 ----> GP16C4T0 + TIMER1 ----> GP16C4T1 + TIMER2 ----> GP32C4T0 + TIMER3 ----> GP32C4T1 + TIMER4 ----> BS16T0 + TIMER5 ----> BS16T1 + TIMER6 ----> GP16C4T2 + TIMER7 ----> GP16C4T3 + @endverbatim + */ +typedef enum { + RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */ + RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */ + RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */ + RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */ + RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */ + RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */ + RMU_PERH_USB = (1U << 10), /**< AHB1: USB */ + RMU_PERH_ECC = (1U << 11), /**< AHB1: ECC */ + RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */ + RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */ + RMU_PERH_EBI = (1U << 8) | (1U << 27), /**< AHB2: EBI */ + RMU_PERH_TIMER0 = (1U << 0) | (1U << 28), /**< APB1: TIMER0 */ + RMU_PERH_TIMER1 = (1U << 1) | (1U << 28), /**< APB1: TIMER1 */ + RMU_PERH_TIMER2 = (1U << 2) | (1U << 28), /**< APB1: TIMER2 */ + RMU_PERH_TIMER3 = (1U << 3) | (1U << 28), /**< APB1: TIMER3 */ + RMU_PERH_TIMER4 = (1U << 4) | (1U << 28), /**< APB1: TIMER4 */ + RMU_PERH_TIMER5 = (1U << 5) | (1U << 28), /**< APB1: TIMER5 */ + RMU_PERH_TIMER6 = (1U << 6) | (1U << 28), /**< APB1: TIMER6 */ + RMU_PERH_TIMER7 = (1U << 7) | (1U << 28), /**< APB1: TIMER7 */ + RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */ + RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */ + RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */ + RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */ + RMU_PERH_UART4 = (1U << 12) | (1U << 28), /**< APB1: UART4 */ + RMU_PERH_UART5 = (1U << 13) | (1U << 28), /**< APB1: UART5 */ + RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */ + RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */ + RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */ + RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */ + RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */ + RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */ + RMU_PERH_QSPI = (1U << 25) | (1U << 28), /**< APB1: QSPI */ + RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */ + RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */ + RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */ + RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */ + RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */ + RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */ + RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */ + RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */ + RMU_PERH_ACMP2 = (1U << 11) | (1U << 29), /**< APB2: WWDT */ + RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */ + RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */ + RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */ + RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */ + RMU_PERH_TSENSE = (1U << 16) | (1U << 29), /**< APB2: TSENSE */ + RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */ + RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */ +} rmu_peripheral_t; +/** + * @} + */ + +/** + * @defgroup RMU_Private_Macros RMU Private Macros + * @{ + */ +#define IS_RMU_BORFLT(x) (((x) == RMU_BORFLT_1) || \ + ((x) == RMU_BORFLT_2) || \ + ((x) == RMU_BORFLT_3) || \ + ((x) == RMU_BORFLT_4) || \ + ((x) == RMU_BORFLT_5) || \ + ((x) == RMU_BORFLT_6) || \ + ((x) == RMU_BORFLT_7)) +#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_NONE) || \ + ((x) == RMU_VOL_2_0) || \ + ((x) == RMU_VOL_2_2) || \ + ((x) == RMU_VOL_2_4) || \ + ((x) == RMU_VOL_2_6) || \ + ((x) == RMU_VOL_2_8) || \ + ((x) == RMU_VOL_3_0) || \ + ((x) == RMU_VOL_3_2) || \ + ((x) == RMU_VOL_3_4) || \ + ((x) == RMU_VOL_3_6) || \ + ((x) == RMU_VOL_3_8) || \ + ((x) == RMU_VOL_4_0) || \ + ((x) == RMU_VOL_4_2) || \ + ((x) == RMU_VOL_4_4) || \ + ((x) == RMU_VOL_4_6) || \ + ((x) == RMU_VOL_4_8)) +#define IS_RMU_STATE(x) (((x) == RMU_RST_POR) || \ + ((x) == RMU_RST_WAKEUP) || \ + ((x) == RMU_RST_BOR) || \ + ((x) == RMU_RST_NMRST) || \ + ((x) == RMU_RST_IWDT) || \ + ((x) == RMU_RST_WWDT) || \ + ((x) == RMU_RST_LOCKUP) || \ + ((x) == RMU_RST_CHIP) || \ + ((x) == RMU_RST_MCU) || \ + ((x) == RMU_RST_CPU) || \ + ((x) == RMU_RST_CFG) || \ + ((x) == RMU_RST_CFGERR) || \ + ((x) == RMU_RST_ALL)) +#define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \ + ((x) == RMU_RST_WAKEUP) || \ + ((x) == RMU_RST_BOR) || \ + ((x) == RMU_RST_NMRST) || \ + ((x) == RMU_RST_IWDT) || \ + ((x) == RMU_RST_WWDT) || \ + ((x) == RMU_RST_LOCKUP) || \ + ((x) == RMU_RST_CHIP) || \ + ((x) == RMU_RST_MCU) || \ + ((x) == RMU_RST_CPU) || \ + ((x) == RMU_RST_CFG) || \ + ((x) == RMU_RST_ALL)) +#define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \ + ((x) == RMU_PERH_CRC) || \ + ((x) == RMU_PERH_CALC) || \ + ((x) == RMU_PERH_CRYPT) || \ + ((x) == RMU_PERH_TRNG) || \ + ((x) == RMU_PERH_PIS) || \ + ((x) == RMU_PERH_USB) || \ + ((x) == RMU_PERH_ECC) || \ + ((x) == RMU_PERH_CHIP) || \ + ((x) == RMU_PERH_CPU) || \ + ((x) == RMU_PERH_EBI) || \ + ((x) == RMU_PERH_TIMER0) || \ + ((x) == RMU_PERH_TIMER1) || \ + ((x) == RMU_PERH_TIMER2) || \ + ((x) == RMU_PERH_TIMER3) || \ + ((x) == RMU_PERH_TIMER4) || \ + ((x) == RMU_PERH_TIMER5) || \ + ((x) == RMU_PERH_TIMER6) || \ + ((x) == RMU_PERH_TIMER7) || \ + ((x) == RMU_PERH_UART0) || \ + ((x) == RMU_PERH_UART1) || \ + ((x) == RMU_PERH_UART2) || \ + ((x) == RMU_PERH_UART3) || \ + ((x) == RMU_PERH_UART4) || \ + ((x) == RMU_PERH_UART5) || \ + ((x) == RMU_PERH_SPI0) || \ + ((x) == RMU_PERH_SPI1) || \ + ((x) == RMU_PERH_SPI2) || \ + ((x) == RMU_PERH_I2C0) || \ + ((x) == RMU_PERH_I2C1) || \ + ((x) == RMU_PERH_CAN0) || \ + ((x) == RMU_PERH_QSPI) || \ + ((x) == RMU_PERH_LPTIM0) || \ + ((x) == RMU_PERH_LPUART0) || \ + ((x) == RMU_PERH_ADC0) || \ + ((x) == RMU_PERH_ADC1) || \ + ((x) == RMU_PERH_ACMP0) || \ + ((x) == RMU_PERH_ACMP1) || \ + ((x) == RMU_PERH_OPAMP) || \ + ((x) == RMU_PERH_DAC0) || \ + ((x) == RMU_PERH_ACMP2) || \ + ((x) == RMU_PERH_WWDT) || \ + ((x) == RMU_PERH_LCD) || \ + ((x) == RMU_PERH_IWDT) || \ + ((x) == RMU_PERH_RTC) || \ + ((x) == RMU_PERH_TSENSE) || \ + ((x) == RMU_PERH_BKPC) || \ + ((x) == RMU_PERH_BKPRAM)) +/** + * @} + */ + +/** @addtogroup RMU_Public_Functions + * @{ + */ +void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state); +uint32_t ald_rmu_get_reset_status(rmu_state_t state); +void ald_rmu_clear_reset_status(rmu_state_t state); +void ald_rmu_reset_periperal(rmu_peripheral_t perh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_RMU_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_rtc.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_rtc.h new file mode 100644 index 00000000..d8eaa542 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_rtc.h @@ -0,0 +1,685 @@ +/** + ****************************************************************************** + * @file ald_rtc.h + * @brief Header file of RTC Module driver. + * + * @version V1.0 + * @date 16 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 16 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_RTC_H__ +#define __ALD_RTC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** @defgroup RTC_Public_Types RTC Public Types + * @{ + */ + +/** + * @brief Hours format + */ +typedef enum { + RTC_HOUR_FORMAT_24 = 0x0U, /**< 24-hours format */ + RTC_HOUR_FORMAT_12 = 0x1U, /**< 12-hours format */ +} rtc_hour_format_t; + +/** + * @brief Output mode + */ +typedef enum { + RTC_OUTPUT_DISABLE = 0x0U, /**< Disable output */ + RTC_OUTPUT_ALARM_A = 0x1U, /**< Output alarm_a signal */ + RTC_OUTPUT_ALARM_B = 0x2U, /**< Output alarm_b signal */ + RTC_OUTPUT_WAKEUP = 0x3U, /**< Output wakeup signal */ +} rtc_output_select_t; + +/** + * @brief Output polarity + */ +typedef enum { + RTC_OUTPUT_POLARITY_HIGH = 0x0U, /**< Polarity is high */ + RTC_OUTPUT_POLARITY_LOW = 0x1U, /**< Polarity is low */ +} rtc_output_polarity_t; + +/** + * @brief Initialization structure + */ +typedef struct { + rtc_hour_format_t hour_format; /**< Hours format */ + uint32_t asynch_pre_div; /**< Asynchronous predivider value */ + uint32_t synch_pre_div; /**< Synchronous predivider value */ + rtc_output_select_t output; /**< Output signal type */ + rtc_output_polarity_t output_polarity; /**< Output polarity */ +} rtc_init_t; + +/** + * @brief Source select + */ +typedef enum { + RTC_SOURCE_LOSC = 0x0U, /**< LOSC */ + RTC_SOURCE_LRC = 0x1U, /**< LRC */ + RTC_SOURCE_HRC_DIV_1M = 0x2U, /**< HRC divide to 1MHz */ + RTC_SOURCE_HOSC_DIV_1M = 0x3U, /**< HOSC divide to 1MHz */ +} rtc_source_sel_t; + +/** + * @brief Time structure + */ +typedef struct { + uint8_t hour; /**< Hours */ + uint8_t minute; /**< Minutes */ + uint8_t second; /**< Seconds */ + uint16_t sub_sec; /**< Sub-seconds */ +} rtc_time_t; + +/** + * @brief Date structure + */ +typedef struct { + uint8_t week; /**< Weeks */ + uint8_t day; /**< days */ + uint8_t month; /**< months */ + uint8_t year; /**< years */ +} rtc_date_t; + +/** + * @brief Data format + */ +typedef enum { + RTC_FORMAT_DEC = 0U, /**< Decimal */ + RTC_FORMAT_BCD = 1U, /**< BSD */ +} rtc_format_t; + +/** + * @brief Index of alarm + */ +typedef enum { + RTC_ALARM_A = 0x0U, /**< Alarm-A */ + RTC_ALARM_B = 0x1U, /**< Alarm-B */ +} rtc_alarm_idx_t; + +/** + * @brief Alarm mask + */ +typedef enum { + RTC_ALARM_MASK_NONE = 0x0U, /**< Mask is disable */ + RTC_ALARM_MASK_WEEK_DAY = (1U << 30), /**< Mask week or day */ + RTC_ALARM_MASK_HOUR = (1U << 23), /**< Mask hour */ + RTC_ALARM_MASK_MINUTE = (1U << 15), /**< Mask minute */ + RTC_ALARM_MASK_SECOND = (1U << 7), /**< Mask second */ + RTC_ALARM_MASK_ALL = 0x40808080U, /**< Mask all */ +} rtc_alarm_mask_t; + +/** + * @brief Alarm sub-second mask + */ +typedef enum { + RTC_ALARM_SS_MASK_NONE = 0xFU, /**< Mask is disable */ + RTC_ALARM_SS_MASK_14_1 = 0x1U, /**< Mask bit(1-14) */ + RTC_ALARM_SS_MASK_14_2 = 0x2U, /**< Mask bit(2-14) */ + RTC_ALARM_SS_MASK_14_3 = 0x3U, /**< Mask bit(3-14) */ + RTC_ALARM_SS_MASK_14_4 = 0x4U, /**< Mask bit(4-14) */ + RTC_ALARM_SS_MASK_14_5 = 0x5U, /**< Mask bit(5-14) */ + RTC_ALARM_SS_MASK_14_6 = 0x6U, /**< Mask bit(6-14) */ + RTC_ALARM_SS_MASK_14_7 = 0x7U, /**< Mask bit(7-14) */ + RTC_ALARM_SS_MASK_14_8 = 0x8U, /**< Mask bit(8-14) */ + RTC_ALARM_SS_MASK_14_9 = 0x9U, /**< Mask bit(9-14) */ + RTC_ALARM_SS_MASK_14_10 = 0xAU, /**< Mask bit(10-14) */ + RTC_ALARM_SS_MASK_14_11 = 0xBU, /**< Mask bit(11-14) */ + RTC_ALARM_SS_MASK_14_12 = 0xCU, /**< Mask bit(12-14) */ + RTC_ALARM_SS_MASK_14_13 = 0xDU, /**< Mask bit(13-14) */ + RTC_ALARM_SS_MASK_14 = 0xEU, /**< Mask bit14 */ + RTC_ALARM_SS_MASK_ALL = 0x0U, /**< Mask bit(0-14) */ +} rtc_sub_second_mask_t; + +/** + * @brief Alarm select week or day */ +typedef enum { + RTC_SELECT_DAY = 0x0U, /**< Alarm select day */ + RTC_SELECT_WEEK = 0x1U, /**< Alarm select week */ +} rtc_week_day_sel_t; + +/** + * @brief Alarm structure + */ +typedef struct { + rtc_alarm_idx_t idx; /**< Index of alarm */ + rtc_time_t time; /**< Time structure */ + uint32_t mask; /**< Alarm mask */ + rtc_sub_second_mask_t ss_mask; /**< Alarm sub-second mask */ + rtc_week_day_sel_t sel; /**< Select week or day */ + + union { + uint8_t week; /**< Alarm select week */ + uint8_t day; /**< Alarm select day */ + }; +} rtc_alarm_t; + +/** + * @brief Time stamp signel select + */ +typedef enum { + RTC_TS_SIGNAL_SEL_TAMPER0 = 0U, /**< Select tamper0 */ + RTC_TS_SIGNAL_SEL_TAMPER1 = 1U, /**< Select tamper1 */ +} rtc_ts_signal_sel_t; + +/** + * @brief Time stamp trigger style + */ +typedef enum { + RTC_TS_RISING_EDGE = 0U, /**< Rising edge */ + RTC_TS_FALLING_EDGE = 1U, /**< Falling edge */ +} rtc_ts_trigger_style_t; + +/** + * @brief Index of tamper + */ +typedef enum { + RTC_TAMPER_0 = 0U, /**< Tamper0 */ + RTC_TAMPER_1 = 1U, /**< Tamper1 */ +} rtc_tamper_idx_t; + +/** + * @brief Tamper trigger type + */ +typedef enum { + RTC_TAMPER_TRIGGER_LOW = 0U, /**< High trigger */ + RTC_TAMPER_TRIGGER_HIGH = 1U, /**< Low trigger */ +} rtc_tamper_trigger_t; + +/** + * @brief Tamper sampling frequency + */ +typedef enum { + RTC_TAMPER_SAMPLING_FREQ_32768 = 0U, /**< RTCCLK / 32768 */ + RTC_TAMPER_SAMPLING_FREQ_16384 = 1U, /**< RTCCLK / 16384 */ + RTC_TAMPER_SAMPLING_FREQ_8192 = 2U, /**< RTCCLK / 8192 */ + RTC_TAMPER_SAMPLING_FREQ_4096 = 3U, /**< RTCCLK / 4096 */ + RTC_TAMPER_SAMPLING_FREQ_2048 = 4U, /**< RTCCLK / 2048 */ + RTC_TAMPER_SAMPLING_FREQ_1024 = 5U, /**< RTCCLK / 1024 */ + RTC_TAMPER_SAMPLING_FREQ_512 = 6U, /**< RTCCLK / 512 */ + RTC_TAMPER_SAMPLING_FREQ_256 = 7U, /**< RTCCLK / 256 */ +} rtc_tamper_sampling_freq_t; + +/** + * @brief Tamper filter time + */ +typedef enum { + RTC_TAMPER_DURATION_1 = 0U, /**< Duration 1 sampling */ + RTC_TAMPER_DURATION_2 = 1U, /**< Duration 2 sampling */ + RTC_TAMPER_DURATION_4 = 2U, /**< Duration 4 sampling */ + RTC_TAMPER_DURATION_8 = 3U, /**< Duration 8 sampling */ +} rtc_tamper_duration_t; + +/** + * @brief Tamper structure + */ +typedef struct { + rtc_tamper_idx_t idx; /**< Index of tamper */ + rtc_tamper_trigger_t trig; /**< Trigger type */ + rtc_tamper_sampling_freq_t freq; /**< Sampling frequency */ + rtc_tamper_duration_t dur; /**< Filter time */ + type_func_t ts; /**< Enable/Disable trigger time stamp event */ +} rtc_tamper_t; + +/** + * @brief Wake-up clock + */ +typedef enum { + RTC_WAKEUP_CLOCK_DIV_16 = 0U, /**< RTCCLK / 16 */ + RTC_WAKEUP_CLOCK_DIV_8 = 1U, /**< RTCCLK / 8 */ + RTC_WAKEUP_CLOCK_DIV_4 = 2U, /**< RTCCLK / 4 */ + RTC_WAKEUP_CLOCK_DIV_2 = 3U, /**< RTCCLK / 2 */ + RTC_WAKEUP_CLOCK_1HZ = 4U, /**< 1Hz */ + RTC_WAKEUP_CLOCK_1HZ_PULS = 6U, /**< 1Hz and WUT + 65536 */ +} rtc_wakeup_clock_t; + +/** + * @brief RTC clock output type + */ +typedef enum { + RTC_CLOCK_OUTPUT_32768 = 0U, /**< 32768Hz */ + RTC_CLOCK_OUTPUT_1024 = 1U, /**< 1024Hz */ + RTC_CLOCK_OUTPUT_32 = 2U, /**< 32Hz */ + RTC_CLOCK_OUTPUT_1 = 3U, /**< 1Hz */ + RTC_CLOCK_OUTPUT_CAL_1 = 4U, /**< 1Hz after calibration */ + RTC_CLOCK_OUTPUT_EXA_1 = 5U, /**< Exact 1Hz */ +} rtc_clock_output_t; + +/** + * @ Calibration frequency + */ +typedef enum { + RTC_CALI_FREQ_10_SEC = 0U, /**< Calibrate every 10 seconds */ + RTC_CALI_FREQ_20_SEC = 1U, /**< Calibrate every 20 seconds */ + RTC_CALI_FREQ_1_MIN = 2U, /**< Calibrate every 1 minute */ + RTC_CALI_FREQ_2_MIN = 3U, /**< Calibrate every 2 minutes */ + RTC_CALI_FREQ_5_MIN = 4U, /**< Calibrate every 5 minutes */ + RTC_CALI_FREQ_10_MIN = 5U, /**< Calibrate every 10 minutes */ + RTC_CALI_FREQ_20_MIN = 6U, /**< Calibrate every 20 minutes */ + RTC_CALI_FREQ_1_SEC = 7U, /**< Calibrate every 1 second */ +} rtc_cali_freq_t; + +/** + * @brief Temperature compensate type + */ +typedef enum { + RTC_CALI_TC_NONE = 0U, /**< Temperature compensate disable */ + RTC_CALI_TC_AUTO_BY_HW = 1U, /**< Temperature compensate by hardware */ + RTC_CALI_TC_AUTO_BY_SF = 2U, /**< Temperature compensate by software */ + RTC_CALI_TC_AUTO_BY_HW_SF = 3U, /**< Temperature compensate by hardware, trigger by software */ +} rtc_cali_tc_t; + +/** + * @ Calculate frequency + */ +typedef enum { + RTC_CALI_CALC_FREQ_10_SEC = 0U, /**< Calculate every 10 seconds */ + RTC_CALI_CALC_FREQ_20_SEC = 1U, /**< Calculate every 20 seconds */ + RTC_CALI_CALC_FREQ_1_MIN = 2U, /**< Calculate every 1 minute */ + RTC_CALI_CALC_FREQ_2_MIN = 3U, /**< Calculate every 2 minutes */ + RTC_CALI_CALC_FREQ_5_MIN = 4U, /**< Calculate every 5 minutes */ + RTC_CALI_CALC_FREQ_10_MIN = 5U, /**< Calculate every 10 minutes */ + RTC_CALI_CALC_FREQ_20_MIN = 6U, /**< Calculate every 20 minutes */ + RTC_CALI_CALC_FREQ_1_HOUR = 7U, /**< Calculate every 1 hour */ +} rtc_cali_calc_freq_t; + +/** + * @brief Calibration algorithm + */ +typedef enum { + RTC_CALI_CALC_4 = 0U, /**< 4-polynomial */ + RTC_CALI_CALC_2 = 1U, /**< 2-parabola */ +} rtc_cali_calc_t; + +/** + * @brief Calibration structure + */ +typedef struct { + rtc_cali_freq_t cali_freq; /**< calibrate frequency */ + rtc_cali_tc_t tc; /**< Temperature compensate type */ + rtc_cali_calc_freq_t calc_freq; /**< Calculate frequency */ + rtc_cali_calc_t calc; /**< algorithm */ + type_func_t acc; /**< Enable/Disable decimal accumulate */ +} rtc_cali_t; + +/** + * @brief Interrupt type + */ +typedef enum { + RTC_IT_SEC = (1U << 0), /**< Second */ + RTC_IT_MIN = (1U << 1), /**< Minute */ + RTC_IT_HR = (1U << 2), /**< Hour */ + RTC_IT_DAY = (1U << 3), /**< Day */ + RTC_IT_MON = (1U << 4), /**< Month */ + RTC_IT_YR = (1U << 5), /**< Year */ + RTC_IT_ALMA = (1U << 8), /**< Alarm-A */ + RTC_IT_ALMB = (1U << 9), /**< Alarm-B */ + RTC_IT_TS = (1U << 10), /**< Time stamp */ + RTC_IT_TSOV = (1U << 11), /**< Time stamp overflow */ + RTC_IT_TP0 = (1U << 12), /**< Tamper-0 */ + RTC_IT_TP1 = (1U << 13), /**< Tamper-1 */ + RTC_IT_RSC = (1U << 16), /**< Synchronous complete */ + RTC_IT_SFC = (1U << 17), /**< Shift complete */ + RTC_IT_WU = (1U << 18), /**< Wake-up */ + RTC_IT_TCC = (1U << 24), /**< Temperature compensate complete */ + RTC_IT_TCE = (1U << 25), /**< Temperature compensate error */ +} rtc_it_t; + +/** + * @brief Interrupt flag + */ +typedef enum { + RTC_IF_SEC = (1U << 0), /**< Second */ + RTC_IF_MIN = (1U << 1), /**< Minute */ + RTC_IF_HR = (1U << 2), /**< Hour */ + RTC_IF_DAY = (1U << 3), /**< Day */ + RTC_IF_MON = (1U << 4), /**< Month */ + RTC_IF_YR = (1U << 5), /**< Year */ + RTC_IF_ALMA = (1U << 8), /**< Alarm-A */ + RTC_IF_ALMB = (1U << 9), /**< Alarm-B */ + RTC_IF_TS = (1U << 10), /**< Time stamp */ + RTC_IF_TSOV = (1U << 11), /**< Time stamp overflow */ + RTC_IF_TP0 = (1U << 12), /**< Tamper-0 */ + RTC_IF_TP1 = (1U << 13), /**< Tamper-1 */ + RTC_IF_RSC = (1U << 16), /**< Synchronous complete */ + RTC_IF_SFC = (1U << 17), /**< Shift complete */ + RTC_IF_WU = (1U << 18), /**< Wake-up */ + RTC_IF_TCC = (1U << 24), /**< Temperature compensate complete */ + RTC_IF_TCE = (1U << 25), /**< Temperature compensate error */ +} rtc_flag_t; +/** + * @} + */ + +/** @defgroup RTC_Public_Macro RTC Public Macros + * @{ + */ +#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55U)) +#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0U)) +#define RTC_BY_PASS_ENABLE() \ +do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ + RTC_LOCK(); \ +} while (0) +#define RTC_BY_PASS_DISABLE() \ +do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \ + RTC_LOCK(); \ +} while (0) +#define RTC_SUMMER_TIME_ENABLE() \ +do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ + RTC_LOCK(); \ +} while (0) +#define RTC_SUMMER_TIME_DISABLE() \ +do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \ + RTC_LOCK(); \ +} while (0) +#define RTC_WINTER_TIME_ENABLE() \ +do { \ + RTC_UNLOCK(); \ + SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ + RTC_LOCK(); \ +} while (0) +#define RTC_WINTER_TIME_DISABLE() \ +do { \ + RTC_UNLOCK(); \ + CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \ + RTC_LOCK(); \ +} while (0) +/** + * @} + */ + +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ +#define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AAU)) +#define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0U)) +#define ALARM_MASK_ALL 0x40808080 +#define RTC_TIMEOUT_VALUE 100 + +#define IS_SHIFT_SUB_SS(x) ((x) < (1U << 15)) +#define IS_RTC_HOUR_FORMAT(x) (((x) == RTC_HOUR_FORMAT_24) || \ + ((x) == RTC_HOUR_FORMAT_12)) +#define IS_RTC_OUTPUT_SEL(x) (((x) == RTC_OUTPUT_DISABLE) || \ + ((x) == RTC_OUTPUT_ALARM_A) || \ + ((x) == RTC_OUTPUT_ALARM_B) || \ + ((x) == RTC_OUTPUT_WAKEUP)) +#define IS_RTC_OUTPUT_POLARITY(x) (((x) == RTC_OUTPUT_POLARITY_HIGH) || \ + ((x) == RTC_OUTPUT_POLARITY_LOW)) +#define IS_RTC_SOURCE_SEL(x) (((x) == RTC_SOURCE_LOSC) || \ + ((x) == RTC_SOURCE_LRC) || \ + ((x) == RTC_SOURCE_HRC_DIV_1M ) || \ + ((x) == RTC_SOURCE_HOSC_DIV_1M)) +#define IS_RTC_ALARM(x) (((x) == RTC_ALARM_A) || \ + ((x) == RTC_ALARM_B)) +#define IS_RTC_ALARM_SEL(x) (((x) == RTC_SELECT_DAY) || \ + ((x) == RTC_SELECT_WEEK)) +#define IS_RTC_ALARM_MASK(x) (((x) == RTC_ALARM_MASK_NONE) || \ + ((x) == RTC_ALARM_MASK_WEEK_DAY) || \ + ((x) == RTC_ALARM_MASK_HOUR) || \ + ((x) == RTC_ALARM_MASK_MINUTE) || \ + ((x) == RTC_ALARM_MASK_SECOND) || \ + ((x) == RTC_ALARM_MASK_ALL)) +#define IS_RTC_ALARM_SS_MASK(x) (((x) == RTC_ALARM_SS_MASK_NONE) || \ + ((x) == RTC_ALARM_SS_MASK_14_1) || \ + ((x) == RTC_ALARM_SS_MASK_14_2) || \ + ((x) == RTC_ALARM_SS_MASK_14_3) || \ + ((x) == RTC_ALARM_SS_MASK_14_4) || \ + ((x) == RTC_ALARM_SS_MASK_14_5) || \ + ((x) == RTC_ALARM_SS_MASK_14_6) || \ + ((x) == RTC_ALARM_SS_MASK_14_7) || \ + ((x) == RTC_ALARM_SS_MASK_14_8) || \ + ((x) == RTC_ALARM_SS_MASK_14_9) || \ + ((x) == RTC_ALARM_SS_MASK_14_10) || \ + ((x) == RTC_ALARM_SS_MASK_14_11) || \ + ((x) == RTC_ALARM_SS_MASK_14_12) || \ + ((x) == RTC_ALARM_SS_MASK_14_13) || \ + ((x) == RTC_ALARM_SS_MASK_14) || \ + ((x) == RTC_ALARM_SS_MASK_ALL)) +#define IS_RTC_TS_SIGNAL(x) (((x) == RTC_TS_SIGNAL_SEL_TAMPER0) || \ + ((x) == RTC_TS_SIGNAL_SEL_TAMPER1)) +#define IS_RTC_TS_STYLE(x) (((x) == RTC_TS_RISING_EDGE) || \ + ((x) == RTC_TS_FALLING_EDGE)) +#define IS_RTC_FORMAT(x) (((x) == RTC_FORMAT_DEC) || \ + ((x) == RTC_FORMAT_BCD)) +#define IS_RTC_TAMPER(x) (((x) == RTC_TAMPER_0) || \ + ((x) == RTC_TAMPER_1)) +#define IS_RTC_TAMPER_TRIGGER(x) (((x) == RTC_TAMPER_TRIGGER_LOW) || \ + ((x) == RTC_TAMPER_TRIGGER_HIGH)) +#define IS_RTC_TAMPER_SAMPLING_FREQ(x) (((x) == RTC_TAMPER_SAMPLING_FREQ_32768) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_8192) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_4096) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_2048) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_1024) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_512) || \ + ((x) == RTC_TAMPER_SAMPLING_FREQ_256)) +#define IS_RTC_TAMPER_DURATION(x) (((x) == RTC_TAMPER_DURATION_1) || \ + ((x) == RTC_TAMPER_DURATION_2) || \ + ((x) == RTC_TAMPER_DURATION_4) || \ + ((x) == RTC_TAMPER_DURATION_8)) +#define IS_RTC_WAKEUP_CLOCK(x) (((x) == RTC_WAKEUP_CLOCK_DIV_16) || \ + ((x) == RTC_WAKEUP_CLOCK_DIV_8) || \ + ((x) == RTC_WAKEUP_CLOCK_DIV_4) || \ + ((x) == RTC_WAKEUP_CLOCK_DIV_2) || \ + ((x) == RTC_WAKEUP_CLOCK_1HZ) || \ + ((x) == RTC_WAKEUP_CLOCK_1HZ_PULS)) +#define IS_RTC_CLOCK_OUTPUT(x) (((x) == RTC_CLOCK_OUTPUT_32768) || \ + ((x) == RTC_CLOCK_OUTPUT_1024) || \ + ((x) == RTC_CLOCK_OUTPUT_32) || \ + ((x) == RTC_CLOCK_OUTPUT_1) || \ + ((x) == RTC_CLOCK_OUTPUT_CAL_1) || \ + ((x) == RTC_CLOCK_OUTPUT_EXA_1)) +#define IS_RTC_CALI_FREQ(x) (((x) == RTC_CALI_FREQ_10_SEC) || \ + ((x) == RTC_CALI_FREQ_20_SEC) || \ + ((x) == RTC_CALI_FREQ_1_MIN) || \ + ((x) == RTC_CALI_FREQ_2_MIN) || \ + ((x) == RTC_CALI_FREQ_5_MIN) || \ + ((x) == RTC_CALI_FREQ_10_MIN) || \ + ((x) == RTC_CALI_FREQ_20_MIN) || \ + ((x) == RTC_CALI_FREQ_1_SEC)) +#define IS_RTC_CALI_TC(x) (((x) == RTC_CALI_TC_NONE) || \ + ((x) == RTC_CALI_TC_AUTO_BY_HW) || \ + ((x) == RTC_CALI_TC_AUTO_BY_SF) || \ + ((x) == RTC_CALI_TC_AUTO_BY_HW_SF)) +#define IS_RTC_CALC_FREQ(x) (((x) == RTC_CALI_CALC_FREQ_10_SEC) || \ + ((x) == RTC_CALI_CALC_FREQ_20_SEC) || \ + ((x) == RTC_CALI_CALC_FREQ_1_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_2_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_5_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_10_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_20_MIN) || \ + ((x) == RTC_CALI_CALC_FREQ_1_HOUR)) +#define IS_RTC_CALI_CALC(x) (((x) == RTC_CALI_CALC_4) || \ + ((x) == RTC_CALI_CALC_2)) +#define IS_RTC_IT(x) (((x) == RTC_IT_SEC) || \ + ((x) == RTC_IT_MIN) || \ + ((x) == RTC_IT_HR) || \ + ((x) == RTC_IT_DAY) || \ + ((x) == RTC_IT_MON) || \ + ((x) == RTC_IT_YR) || \ + ((x) == RTC_IT_ALMA) || \ + ((x) == RTC_IT_ALMB) || \ + ((x) == RTC_IT_TS) || \ + ((x) == RTC_IT_TSOV) || \ + ((x) == RTC_IT_TP0) || \ + ((x) == RTC_IT_TP1) || \ + ((x) == RTC_IT_RSC) || \ + ((x) == RTC_IT_SFC) || \ + ((x) == RTC_IT_WU) || \ + ((x) == RTC_IT_TCC) || \ + ((x) == RTC_IT_TCE)) +#define IS_RTC_IF(x) (((x) == RTC_IF_SEC) || \ + ((x) == RTC_IF_MIN) || \ + ((x) == RTC_IF_HR) || \ + ((x) == RTC_IF_DAY) || \ + ((x) == RTC_IF_MON) || \ + ((x) == RTC_IF_YR) || \ + ((x) == RTC_IF_ALMA) || \ + ((x) == RTC_IF_ALMB) || \ + ((x) == RTC_IF_TS) || \ + ((x) == RTC_IF_TSOV) || \ + ((x) == RTC_IF_TP0) || \ + ((x) == RTC_IF_TP1) || \ + ((x) == RTC_IF_RSC) || \ + ((x) == RTC_IF_SFC) || \ + ((x) == RTC_IF_WU) || \ + ((x) == RTC_IF_TCC) || \ + ((x) == RTC_IF_TCE)) +#define IS_RTC_SECOND(x) ((x) < 60) +#define IS_RTC_MINUTE(x) ((x) < 60) +#define IS_RTC_HOUR(x) ((x) < 24) +#define IS_RTC_DAY(x) (((x) > 0) && ((x) < 32)) +#define IS_RTC_MONTH(x) (((x) > 0) && ((x) < 13)) +#define IS_RTC_YEAR(x) ((x) < 100) +/** + * @} + */ + +/** @addtogroup RTC_Public_Functions + * @{ + */ + +/** @addtogroup RTC_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void ald_rtc_reset(void); +void ald_rtc_init(rtc_init_t *init); +void ald_rtc_source_select(rtc_source_sel_t sel); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group2 + * @{ + */ +/* Time and date operation functions */ +ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format); +ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format); +void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format); +void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format); +int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group3 + * @{ + */ +/* Alarm functions */ +void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format); +void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group4 + * @{ + */ +/* Time stamp functions */ +void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style); +void ald_rtc_cancel_time_stamp(void); +void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group5 + * @{ + */ +/* Tamper functions */ +void ald_rtc_set_tamper(rtc_tamper_t *tamper); +void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group6 + * @{ + */ +/* Wakeup functions */ +void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value); +void ald_rtc_cancel_wakeup(void); +uint16_t ald_rtc_get_wakeup_timer_value(void); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group7 + * @{ + */ +/* Clock output functions */ +ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock); +void ald_rtc_cancel_clock_output(void); +/** + * @} + */ +/** @addtogroup RTC_Public_Functions_Group8 + * @{ + */ +/* Control functions */ +void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state); +void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state); +ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss); +void ald_rtc_set_cali(rtc_cali_t *config); +void ald_rtc_cancel_cali(void); +ald_status_t ald_rtc_get_cali_status(void); +void ald_rtc_write_temp(uint16_t temp); +it_status_t ald_rtc_get_it_status(rtc_it_t it); +flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag); +void ald_rtc_clear_flag_status(rtc_flag_t flag); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_rtchw.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_rtchw.h new file mode 100644 index 00000000..36099e7a --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_rtchw.h @@ -0,0 +1,160 @@ +/** + ****************************************************************************** + * @file ald_rtchw.h + * @brief Header file of RTCHW Module driver. + * + * @version V1.0 + * @date 16 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 16 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_RTCHW_H__ +#define __ALD_RTCHW_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup RTCHW + * @{ + */ + +/** @defgroup RTCHW_Public_Types RTCHW Public Types + * @{ + */ +/** + * @brief Hardware calibration algorithm + */ +typedef enum { + RTC_CALI_MODE_NORMAL = 0U, /**< Normal mode */ + RTC_CALI_MODE_SLEEP = 1U, /**< Low power mode */ +} rtc_hw_cali_mode_t; + +/** + * @brief the parameters table of rtc calibration + */ +typedef struct { + uint32_t MODE_CALI; /**< Calibration Mode */ + uint32_t RTC_CALCR; /**< CALCR */ + uint32_t RTC_TEMPBDR; /**< TEMPBDR */ + uint32_t TEMP_TBDR; /**< TBDR */ + uint32_t RTC_LTAXR; /**< LTAXR */ + uint32_t RTC_HTAXR; /**< HTAXR */ + uint32_t RTC_LTCAR; /**< LTCAR */ + uint32_t RTC_LTCBR; /**< LTCBR */ + uint32_t RTC_LTCCR; /**< LTCCR */ + uint32_t RTC_LTCDR; /**< LTCDR */ + uint32_t RTC_HTCAR; /**< HTCAR */ + uint32_t RTC_HTCBR; /**< HTCBR */ + uint32_t RTC_HTCCR; /**< HTCCR */ + uint32_t RTC_HTCDR; /**< HTCDR */ + uint32_t TEMP_LTGR; /**< LTGR */ + uint32_t TEMP_HTGR; /**< HTGR */ + uint32_t TEMP_CR; /**< CR */ + uint32_t rsv0; /**< Reserved */ + uint32_t RTC_LTCER; /**< LTCER */ + uint32_t RTC_HTCER; /**< HTCER */ + uint32_t TEMP_PEAK; /**< PEAK */ + uint32_t FREQ_PEAK; /**< PEAK */ + uint32_t TEMP_CALI; /**< CALI */ + uint32_t TEMP_CALI_AFTER; /**< AFTER */ + uint32_t TEMP_TCALBDR; /**< TCALBDR */ + uint32_t TEMP_TCALBDR_MINUS; /**< TCALBDR_MINUS */ + uint32_t rsv1[4]; /**< Reserved */ + uint32_t SUM; /**< SUM */ + uint32_t SUM_MINUS; /**< SUM_MINUS */ +} RTCINFO_TypeDef; + +/** + * @brief Hardware calibration structure + */ +typedef struct { + int16_t offset_rtc_bdr; /**< offset:0x00 */ + int16_t offset_temp_bdr; /**< offset:0x02 */ + int16_t offset_ltaxr; /**< offset:0x04 */ + int16_t offset_htaxr; /**< offset:0x06 */ + int16_t offset_ltcar; /**< offset:0x08 */ + int16_t offset_ltcbr; /**< offset:0x0A */ + int16_t offset_ltccr; /**< offset:0x0C */ + int16_t offset_ltcdr; /**< offset:0x0E */ + int16_t offset_htcar; /**< offset:0x10 */ + int16_t offset_htcbr; /**< offset:0x12 */ + int16_t offset_htccr; /**< offset:0x14 */ + int16_t offset_htcdr; /**< offset:0x16 */ + int16_t offset_ltgr; /**< offset:0x18 */ + int16_t offset_htgr; /**< offset:0x1A */ + int16_t offset_ltcer; /**< offset:0x1C */ + int16_t offset_htcer; /**< offset:0x1E */ + int16_t offset_temp_peak; /**< offset:0x20 */ + int16_t offset_freq_peak; /**< offset:0x22 */ + int16_t offset_tcalbdr; /**< offset:0x24 */ + int16_t crc; /**< offset:0x26 */ + int16_t rsv[8]; +} rtc_hw_cali_offset_t; +/** + * @} + */ +/** @defgroup RTCHW_Private_Macros RTCHW Private Macros + * @{ + */ +#ifndef RTC_LOCK +#define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0U)) +#define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55U)) +#endif + +#ifndef TSENSE_LOCK +#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U)) +#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U)) +#endif + +#define RTCINFO ((RTCINFO_TypeDef *)0x81000U) +/** + * @} + */ + +/** @addtogroup RTCHW_Public_Functions + * @{ + */ +/* Calibration functions */ +void ald_rtc_hw_auto_cali(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_spi.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_spi.h new file mode 100644 index 00000000..6efda0fb --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_spi.h @@ -0,0 +1,450 @@ +/** + ********************************************************************************* + * + * @file ald_spi.c + * @brief Header file of SPI module driver. + * + * @version V1.0 + * @date 13 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 13 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_SPI_H__ +#define __ALD_SPI_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Public_Types SPI Public Types + * @{ + */ + +/** + * @brief clock phase + */ +typedef enum { + SPI_CPHA_FIRST = 0U, /**< Transiting data in the first edge */ + SPI_CPHA_SECOND = 1U, /**< Transiting data in the seconde edge */ +} spi_cpha_t; + +/** + * @brief clock polarity + */ +typedef enum { + SPI_CPOL_LOW = 0U, /**< Polarity hold low when spi-bus is idle */ + SPI_CPOL_HIGH = 1U, /**< Polarity hold high when spi-bus is idle */ +} spi_cpol_t; + +/** + * @brief master selection + */ +typedef enum { + SPI_MODE_SLAVER = 0U, /**< Slave mode */ + SPI_MODE_MASTER = 1U, /**< Master mode */ +} spi_mode_t; + +/** + * @brief baud rate control + */ +typedef enum { + SPI_BAUD_2 = 0U, /**< fpclk/2 */ + SPI_BAUD_4 = 1U, /**< fpclk/4 */ + SPI_BAUD_8 = 2U, /**< fpclk/8 */ + SPI_BAUD_16 = 3U, /**< fpclk/16 */ + SPI_BAUD_32 = 4U, /**< fpclk/32 */ + SPI_BAUD_64 = 5U, /**< fpclk/64 */ + SPI_BAUD_128 = 6U, /**< fpclk/128 */ + SPI_BAUD_256 = 7U, /**< fpclk/256 */ +} spi_baud_t; + +/** + * @brief frame format + */ +typedef enum { + SPI_FIRSTBIT_MSB = 0U, /**< MSB transmitted first */ + SPI_FIRSTBIT_LSB = 1U, /**< LSB transmitted first */ +} spi_firstbit_t; + +/** + * @brief data frame format + */ +typedef enum { + SPI_DATA_SIZE_8 = 0U, /**< 8-bit data frame format is selected for transmission/reception */ + SPI_DATA_SIZE_16 = 1U, /**< 16-bit data frame format is selected for transmission/reception */ +} spi_datasize_t; + +/** + * @brief SPI error status + */ +typedef enum { + SPI_ERROR_NONE = 0U, /**< none */ + SPI_ERROR_MODF = 1U, /**< mode fault */ + SPI_ERROR_CRC = 2U, /**< crc error */ + SPI_ERROR_FRE = 4U, /**< frame error */ + SPI_ERROR_RXOV = 8U, /**< receive over error */ + SPI_ERROR_TXOV = 0x10U, /**< dma error */ + SPI_ERROR_FLAG = 0x20U, /**< interrupt flag error */ +} spi_error_t; + +/** + * @brief interrupt control + */ +typedef enum { + SPI_IT_TXE = (1U << 0), /**< Transmit fifo empty interrupt */ + SPI_IT_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt */ + SPI_IT_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt */ + SPI_IT_TXTH = (1U << 4), /**< Transmit fifo under threshold interrupt */ + SPI_IT_RXF = (1U << 9), /**< Receive fifo full interrupt */ + SPI_IT_RXOV = (1U << 10), /**< Receive fifo overflow interrupt */ + SPI_IT_RXUD = (1U << 11), /**< Receive fifo underflow interrupt */ + SPI_IT_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt */ + SPI_IT_CRCERR = (1U << 16), /**< Crc error interrupt */ + SPI_IT_MODF = (1U << 17), /**< Mode error interrupt */ + SPI_IT_FRE = (1U << 18), /**< Frame error interrupt */ +} spi_it_t; + +/** + * @brief interrupt flag + */ +typedef enum { + SPI_IF_TXE = (1U << 0), /**< Transmit fifo empty interrupt flag */ + SPI_IF_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt flag */ + SPI_IF_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt flag */ + SPI_IF_TXTH = (1U << 4), /**< Transmit fifo under threshold interrupt flag */ + SPI_IF_RXF = (1U << 9), /**< Receive fifo full interrupt flag */ + SPI_IF_RXOV = (1U << 10), /**< Receive fifo overflow interrupt flag */ + SPI_IF_RXUD = (1U << 11), /**< Receive fifo underflow interrupt flag */ + SPI_IF_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt flag */ + SPI_IF_CRCERR = (1U << 16), /**< Crc error interrupt flag */ + SPI_IF_MODF = (1U << 17), /**< Mode error interrupt flag */ + SPI_IF_FRE = (1U << 18), /**< Frame error interrupt flag */ +} spi_flag_t; + +/** + * @brief SPI state structures definition + */ +typedef enum { + SPI_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + SPI_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + SPI_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + SPI_STATE_BUSY_TX = 0x11U, /**< transmit is ongoing */ + SPI_STATE_BUSY_RX = 0x21U, /**< receive is ongoing */ + SPI_STATE_BUSY_TX_RX = 0x31U, /**< transmit and receive are ongoing */ + SPI_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + SPI_STATE_ERROR = 0x04U, /**< Error */ +} spi_state_t; + + +/** + * @brief SPI direction definition + */ +typedef enum { + SPI_DIRECTION_2LINES = 0U, /**< 2 lines */ + SPI_DIRECTION_2LINES_RXONLY = 1U, /**< 2 lines only rx */ + SPI_DIRECTION_1LINE = 2U, /**< 1 line */ + SPI_DIRECTION_1LINE_RX = 3U, /**< 1 line only rx */ +} spi_direction_t; + +/** + * @brief SPI dma request definition + */ +typedef enum { + SPI_DMA_REQ_TX = 0U, /**< TX dma request */ + SPI_DMA_REQ_RX = 1U, /**< RX dma request */ +} spi_dma_req_t; + +/** + * @brief SPI crc length definition + */ +typedef enum { + SPI_FRAME_MOTOROLA = 0U, /**< SPI motorola mode */ + SPI_FRAME_TI = 1U, /**< SPI TI mode */ +} spi_frame_t; + +/** + * @brief SPI status definition + */ +typedef enum { + SPI_STATUS_TXE = (1U << 0), /**< Transmit fifo empty status */ + SPI_STATUS_TXF = (1U << 1), /**< Transmit fifo full status */ + SPI_STATUS_TXOV = (1U << 2), /**< Transmit fifo overflow status */ + SPI_STATUS_TXUD = (1U << 3), /**< Transmit fifo underflow status */ + SPI_STATUS_TXTH = (1U << 4), /**< Transmit fifo under threshold status */ + SPI_STATUS_RXE = (1U << 8), /**< Receive fifo empty status */ + SPI_STATUS_RXF = (1U << 9), /**< Receive fifo full status */ + SPI_STATUS_RXOV = (1U << 10), /**< Receive fifo overflow status */ + SPI_STATUS_RXUD = (1U << 11), /**< Receive fifo underflow status */ + SPI_STATUS_RXTH = (1U << 12), /**< Receive fifo under threshold status */ + SPI_STATUS_BUSY = (1U << 15), /**< BUSY status */ +} spi_status_t; + +/** + * @brief SPI TXE/RXNE status definition + */ +typedef enum { + SPI_SR_TXE = 0U, /**< SR.TXE set */ + SPI_SR_RXNE = 1U, /**< SR.RXTH set */ + SPI_SR_TXE_RXNE = 2U, /**< SR.TXE and SR.RXNE set */ +} spi_sr_status_t; + + +/** + * @brief SPI init structure definition + */ +typedef struct { + spi_mode_t mode; /**< SPI mode */ + spi_direction_t dir; /**< SPI direction */ + spi_datasize_t data_size; /**< SPI data size */ + spi_baud_t baud; /**< SPI baudrate prescaler */ + spi_cpha_t phase; /**< SPI clock phase */ + spi_cpol_t polarity; /**< SPI clock polarity */ + spi_firstbit_t first_bit; /**< SPI first bit */ + type_func_t ss_en; /**< SPI ssm enable or disable */ + type_func_t crc_calc; /**< SPI crc calculation */ + spi_frame_t frame; /**< SPI frame format */ + uint16_t crc_poly; /**< SPI crc polynomial */ +} spi_init_t; + +/** + * @brief SPI handle structure definition + */ +typedef struct spi_handle_s { + SPI_I2S_TypeDef *perh; /**< SPI registers base address */ + spi_init_t init; /**< SPI communication parameters */ + uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */ + uint16_t tx_size; /**< SPI Tx transfer size */ + uint16_t tx_count; /**< SPI Tx transfer counter */ + uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */ + uint16_t rx_size; /**< SPI Rx Transfer size */ + uint16_t rx_count; /**< SPI Rx Transfer Counter */ + + dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */ + dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */ + + lock_state_t lock; /**< Locking object */ + spi_state_t state; /**< SPI communication state */ + uint32_t err_code; /**< SPI error code */ + + void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */ + void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */ + void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */ +} spi_handle_t; +/** + * @} + */ + +/** @defgroup SPI_Public_Macros SPI Public Macros + * @{ + */ +#define SPI_RESET_HANDLE_STATE(x) ((x)->state = SPI_STATE_RESET) +#define SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS)) +#define SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS)) +#define SPI_CRC_RESET(x) \ +do { \ + CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ + SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \ +} while (0) +#define SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) +#define SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK)) +#define SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) +#define SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK)) +#define SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) +#define SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK)) +#define SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) +#define SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK)) +#define SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) +#define SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK)) +/** + * @} + */ + +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ +#define IS_SPI(x) (((x) == SPI0) || \ + ((x) == SPI1) || \ + ((x) == SPI2)) +#define IS_SPI_CPHA(x) (((x) == SPI_CPHA_FIRST) || \ + ((x) == SPI_CPHA_SECOND)) +#define IS_SPI_CPOL(x) (((x) == SPI_CPOL_LOW) || \ + ((x) == SPI_CPOL_HIGH)) +#define IS_SPI_MODE(x) (((x) == SPI_MODE_SLAVER) || \ + ((x) == SPI_MODE_MASTER)) +#define IS_SPI_FIRBIT(x) (((x) == SPI_FIRSTBIT_MSB) || \ + ((x) == SPI_FIRSTBIT_LSB)) +#define IS_SPI_BAUD(x) (((x) == SPI_BAUD_2) || \ + ((x) == SPI_BAUD_4) || \ + ((x) == SPI_BAUD_8) || \ + ((x) == SPI_BAUD_16) || \ + ((x) == SPI_BAUD_32) || \ + ((x) == SPI_BAUD_64) || \ + ((x) == SPI_BAUD_128) || \ + ((x) == SPI_BAUD_256)) +#define IS_SPI_DATASIZE(x) (((x) == SPI_DATA_SIZE_8) || \ + ((x) == SPI_DATA_SIZE_16)) +#define IS_SPI_BIDOE(x) (((x) == SPI_BID_RX) || \ + ((x) == SPI_BID_TX)) +#define IS_SPI_BIDMODE(x) (((x) == SPI_BIDMODE_DUAL) || \ + ((x) == SPI_BIDMODE_SOLE)) +#define IS_SPI_DIRECTION(x) (((x) == SPI_DIRECTION_2LINES) || \ + ((x) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((x) == SPI_DIRECTION_1LINE) || \ + ((x) == SPI_DIRECTION_1LINE_RX)) +#define IS_SPI_DMA_REQ(x) (((x) == SPI_DMA_REQ_TX) || \ + ((x) == SPI_DMA_REQ_RX)) +#define IS_SPI_STATUS(x) (((x) == SPI_STATUS_TXE) || \ + ((x) == SPI_STATUS_TXF) || \ + ((x) == SPI_STATUS_TXOV) || \ + ((x) == SPI_STATUS_TXUD) || \ + ((x) == SPI_STATUS_TXTH) || \ + ((x) == SPI_STATUS_RXE) || \ + ((x) == SPI_STATUS_RXF) || \ + ((x) == SPI_STATUS_RXOV) || \ + ((x) == SPI_STATUS_RXUD) || \ + ((x) == SPI_STATUS_RXTH) || \ + ((x) == SPI_STATUS_BUSY)) +#define IS_SPI_IT(x) (((x) == SPI_IT_TXE) || \ + ((x) == SPI_IT_TXOV) || \ + ((x) == SPI_IT_TXUD) || \ + ((x) == SPI_IT_TXTH) || \ + ((x) == SPI_IT_RXF) || \ + ((x) == SPI_IT_RXOV) || \ + ((x) == SPI_IT_RXUD) || \ + ((x) == SPI_IT_RXTH) || \ + ((x) == SPI_IT_CRCERR) || \ + ((x) == SPI_IT_MODF) || \ + ((x) == SPI_IT_FRE)) +#define IS_SPI_IF(x) (((x) == SPI_IF_TXE) || \ + ((x) == SPI_IF_TXOV) || \ + ((x) == SPI_IF_TXUD) || \ + ((x) == SPI_IF_TXTH) || \ + ((x) == SPI_IF_RXF) || \ + ((x) == SPI_IF_RXOV) || \ + ((x) == SPI_IF_RXUD) || \ + ((x) == SPI_IF_RXTH) || \ + ((x) == SPI_IF_CRCERR) || \ + ((x) == SPI_IF_MODF) || \ + ((x) == SPI_IF_FRE)) +#define IS_SPI_FRAME(x) (((x) == SPI_FRAME_MOTOROLA) || \ + ((x) == SPI_FRAME_TI) ) +/** + * @} + */ + +/** @addtogroup SPI_Public_Functions + * @{ + */ + +/** @addtogroup SPI_Public_Functions_Group1 + * @{ + */ + +ald_status_t ald_spi_init(spi_handle_t *hperh); +void ald_spi_reset(spi_handle_t *hperh); +/** + * @} + */ +/** @addtogroup SPI_Public_Functions_Group2 + * @{ + */ +int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data); +int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data); +uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh, int *status); +ald_status_t ald_spi_send_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_spi_master_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size); +ald_status_t ald_spi_slave_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_spi_send_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +ald_status_t ald_spi_master_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size); +ald_status_t ald_spi_slave_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout); +/** + * @} + */ +/** @addtogroup SPI_Public_Functions_Group3 + * @{ + */ +ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout); +ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size); + +ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel); +ald_status_t ald_spi_dma_pause(spi_handle_t *hperh); +ald_status_t ald_spi_dma_resume(spi_handle_t *hperh); +ald_status_t ald_spi_dma_stop(spi_handle_t *hperh); + +/** + * @} + */ +/** @addtogroup SPI_Public_Functions_Group4 + * @{ + */ +void ald_spi_irq_handler(spi_handle_t *hperh); +void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state); +void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed); +void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state); +it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it); +flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status); +flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag); +void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag); +/** + * @} + */ +/** @addtogroup SPI_Public_Functions_Group5 + * @{ + */ +spi_state_t ald_spi_get_state(spi_handle_t *hperh); +uint32_t ald_spi_get_error(spi_handle_t *hperh); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_sram.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_sram.h new file mode 100644 index 00000000..247160fe --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_sram.h @@ -0,0 +1,142 @@ +/** + ********************************************************************************* + * + * @file ald_sram.h + * @brief Header file of EBI_SRAM driver + * + * @version V1.0 + * @date 07 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_SRAM_H__ +#define __ALD_SRAM_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ald_ebi.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup SRAM + * @{ + */ + +/** @defgroup SRAM_Public_Types SRAM Public Types + * @{ + */ + +/** + * @brief ALD SRAM State structures definition + */ +typedef enum { + ALD_SRAM_STATE_RESET = 0x00U, /**< SRAM not yet initialized or disabled */ + ALD_SRAM_STATE_READY = 0x01U, /**< SRAM initialized and ready for use */ + ALD_SRAM_STATE_BUSY = 0x02U, /**< SRAM internal process is ongoing */ + ALD_SRAM_STATE_ERROR = 0x03U, /**< SRAM error state */ + ALD_SRAM_STATE_PROTECTED = 0x04U /**< SRAM peripheral NORSRAM device write protected */ +} ald_sram_state_t; + +/** + * @brief SRAM handle Structure definition + */ +typedef struct { + EBI_NOR_SRAM_TypeDef *instance; /**< Register base address */ + EBI_NOR_SRAM_EXTENDED_TypeDef *ext; /**< Extended mode register base address */ + ald_ebi_nor_sram_init_t init; /**< SRAM device control configuration parameters */ + lock_state_t lock; /**< SRAM locking object */ + __IO ald_sram_state_t state; /**< SRAM device access state */ + + dma_handle_t hdma; /**< SRAM DMA Handle parameters */ + void(*cplt_cbk)(void *arg); /**< DMA transmit completely callback function */ + +} sram_handle_t; +/** + * @} + */ + +/** @addtogroup SRAM_Public_Functions + * @{ + */ +/** @addtogroup SRAM_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +ald_status_t ald_sram_init(sram_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing); +ald_status_t ald_sram_deinit(sram_handle_t *hperh); +/** + * @} + */ +/** @addtogroup SRAM_Public_Functions_Group2 + * @{ + */ +/* I/O operation functions */ +ald_status_t ald_sram_read_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size); +ald_status_t ald_sram_write_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size); +ald_status_t ald_sram_read_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size); +ald_status_t ald_sram_write_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size); +ald_status_t ald_sram_read_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size); +ald_status_t ald_sram_write_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size); +#ifdef ALD_DMA +ald_status_t ald_sram_read_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch); +ald_status_t ald_sram_write_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch); +#endif +/** + * @} + */ +/** @addtogroup SRAM_Public_Functions_Group3 + * @{ + */ +/* Control functions */ +ald_status_t ald_sram_write_enable(sram_handle_t *hperh); +ald_status_t ald_sram_write_disable(sram_handle_t *hperh); +/** + * @} + */ +/** @addtogroup SRAM_Public_Functions_Group4 + * @{ + */ +/* State functions */ +ald_sram_state_t ald_sram_get_state(sram_handle_t *hperh); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif +#endif /* __ALD_SRAM_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_syscfg.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_syscfg.h new file mode 100644 index 00000000..3cc93859 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_syscfg.h @@ -0,0 +1,93 @@ +/** + ********************************************************************************* + * + * @file ald_syscfg.h + * @brief SYSCFG module driver. + * + * @version V1.0 + * @date 04 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 04 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_SYSCFG_H__ +#define __ALD_SYSCFG_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup SYSCFG SYSCFG + * @brief SYSCFG module driver + * @{ + */ + +/** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros + * @{ + */ +#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0U) +#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996U) +#define GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK) + +#define SYSCFG_BOOTFLASH_MAPPING_ENABLE() SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK) +#define SYSCFG_BOOTFLASH_MAPPING_DISABLE() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK) +/** + * @} + */ + +/** @defgroup SYSCFG_Public_Functions SYSCFG Public Functions + * @{ + */ +/** + * @brief Set the offset of the interrup vector map + * @param offset: Offset of the interrup vector map + * @param status: ENABLE/DISABLE + * @retval None + */ +__STATIC_INLINE__ void ald_vtor_config(uint32_t offset, type_func_t status) +{ + SCB->VTOR = status ? (offset & ~0x3FU) : 0; + return; +} +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_timer.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_timer.h new file mode 100644 index 00000000..8f9afa89 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_timer.h @@ -0,0 +1,1230 @@ +/** + ********************************************************************************* + * + * @file ald_timer.h + * @brief TIMER module driver. + * This is the common part of the TIMER initialization + * + * @version V1.0 + * @date 06 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 06 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_TIMER_H__ +#define __ALD_TIMER_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup TIMER + * @{ + */ + +/** @defgroup TIMER_Public_Types TIMER Public Types + * @{ + */ + +/** + * @brief TIMER counter mode + */ +typedef enum { + TIMER_CNT_MODE_UP = 0U, /**< Counter mode up */ + TIMER_CNT_MODE_DOWN = 1U, /**< Counter mode down */ + TIMER_CNT_MODE_CENTER1 = 2U, /**< Counter mode center1 */ + TIMER_CNT_MODE_CENTER2 = 3U, /**< Counter mode center2 */ + TIMER_CNT_MODE_CENTER3 = 4U, /**< Counter mode center3 */ +} timer_cnt_mode_t; + +/** + * @brief TIMER clock division + */ +typedef enum { + TIMER_CLOCK_DIV1 = 0U, /**< No prescaler is used */ + TIMER_CLOCK_DIV2 = 1U, /** Clock is divided by 2 */ + TIMER_CLOCK_DIV4 = 2U, /** Clock is divided by 4 */ +} timer_clock_division_t; + +/** + * @brief TIMER output compare and PWM modes + */ +typedef enum { + TIMER_OC_MODE_TIMERING = 0U, /**< Output compare mode is timering */ + TIMER_OC_MODE_ACTIVE = 1U, /**< Output compare mode is active */ + TIMER_OC_MODE_INACTIVE = 2U, /**< Output compare mode is inactive */ + TIMER_OC_MODE_TOGGLE = 3U, /**< Output compare mode is toggle */ + TIMER_OC_MODE_FORCE_INACTIVE = 4U, /**< Output compare mode is force inactive */ + TIMER_OC_MODE_FORCE_ACTIVE = 5U, /**< Output compare mode is force active */ + TIMER_OC_MODE_PWM1 = 6U, /**< Output compare mode is pwm1 */ + TIMER_OC_MODE_PWM2 = 7U, /**< Output compare mode is pwm2 */ +} timer_oc_mode_t; + +/** + * @brief TIMER output compare polarity + */ +typedef enum { + TIMER_OC_POLARITY_HIGH = 0U, /**< Output compare polarity is high */ + TIMER_OC_POLARITY_LOW = 1U, /**< Output compare polarity is low */ +} timer_oc_polarity_t; + +/** + * @brief TIMER complementary output compare polarity + */ +typedef enum { + TIMER_OCN_POLARITY_HIGH = 0U, /**< Complementary output compare polarity is high */ + TIMER_OCN_POLARITY_LOW = 1U, /**< Complementary output compare polarity is low */ +} timer_ocn_polarity_t; + +/** + * @brief TIMER output compare idle state + */ +typedef enum { + TIMER_OC_IDLE_RESET = 0U, /**< Output compare idle state is reset */ + TIMER_OC_IDLE_SET = 1U, /**< Output compare idle state is set */ +} timer_oc_idle_t; + +/** + * @brief TIMER complementary output compare idle state + */ +typedef enum { + TIMER_OCN_IDLE_RESET = 0U, /**< Complementary output compare idle state is reset */ + TIMER_OCN_IDLE_SET = 1U, /**< Complementary output compare idle state is set */ +} timer_ocn_idle_t; + +/** + * @brief TIMER channel + */ +typedef enum { + TIMER_CHANNEL_1 = 0U, /**< Channel 1 */ + TIMER_CHANNEL_2 = 1U, /**< Channel 2 */ + TIMER_CHANNEL_3 = 2U, /**< Channel 3 */ + TIMER_CHANNEL_4 = 3U, /**< Channel 4 */ + TIMER_CHANNEL_ALL = 0xFU, /**< All channel */ +} timer_channel_t; + +/** + * @brief TIMER one pulse mode + */ +typedef enum { + TIMER_OP_MODE_REPEAT = 0U, /**< Repetitive */ + TIMER_OP_MODE_SINGLE = 1U, /**< single */ +} timer_op_mode_t; + +/** + * @brief TIMER one pulse output channel + */ +typedef enum { + TIMER_OP_OUTPUT_CHANNEL_1 = 0U, /**< One pulse output channal 1 */ + TIMER_OP_OUTPUT_CHANNEL_2 = 1U, /**< One pulse output channal 2 */ +} timer_op_output_channel_t; + +/** + * @brief TIMER time base configuration structure definition + */ +typedef struct { + uint32_t prescaler; /**< Specifies the prescaler value used to divide the TIMER clock. */ + timer_cnt_mode_t mode; /**< Specifies the counter mode. */ + uint32_t period; /**< Specifies the period value to be loaded into ARR at the next update event. */ + timer_clock_division_t clk_div; /**< Specifies the clock division.*/ + uint32_t re_cnt; /**< Specifies the repetition counter value. */ +} timer_base_init_t; + +/** + * @brief TIMER output compare configuration structure definition + */ +typedef struct { + timer_oc_mode_t oc_mode; /**< Specifies the TIMER mode. */ + uint32_t pulse; /**< Specifies the pulse value to be loaded into the Capture Compare Register. */ + timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity. */ + timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity. */ + type_func_t oc_fast_en; /**< Specifies the Fast mode state. */ + timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ + timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state. */ +} timer_oc_init_t; + +/** + * @brief State structures definition + */ +typedef enum { + TIMER_STATE_RESET = 0x00U, /**< Peripheral not yet initialized or disabled */ + TIMER_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + TIMER_STATE_BUSY = 0x02U, /**< An internal process is ongoing */ + TIMER_STATE_TIMEREOUT = 0x03U, /**< Timeout state */ + TIMER_STATE_ERROR = 0x04U, /**< Reception process is ongoing */ +} timer_state_t; + +/** + * @brief Active channel structures definition + */ +typedef enum { + TIMER_ACTIVE_CHANNEL_1 = 0x01U, /**< The active channel is 1 */ + TIMER_ACTIVE_CHANNEL_2 = 0x02U, /**< The active channel is 2 */ + TIMER_ACTIVE_CHANNEL_3 = 0x04U, /**< The active channel is 3 */ + TIMER_ACTIVE_CHANNEL_4 = 0x08U, /**< The active channel is 4 */ + TIMER_ACTIVE_CHANNEL_CLEARED = 0x00U, /**< All active channels cleared */ +} timer_active_channel_t; + +/** + * @brief TIMER time base handle structure definition + */ +typedef struct timer_handle_s { + TIMER_TypeDef *perh; /**< Register base address */ + timer_base_init_t init; /**< TIMER Time Base required parameters */ + timer_active_channel_t ch; /**< Active channel */ + lock_state_t lock; /**< Locking object */ + timer_state_t state; /**< TIMER operation state */ + + dma_handle_t hdma1; /**< Timer DMA handle parameters */ + dma_handle_t hdma2; + + void (*period_elapse_cbk)(struct timer_handle_s *arg); /**< Period elapse callback */ + void (*delay_elapse_cbk)(struct timer_handle_s *arg); /**< Delay_elapse callback */ + void (*capture_cbk)(struct timer_handle_s *arg); /**< Capture callback */ + void (*pwm_pulse_finish_cbk)(struct timer_handle_s *arg); /**< PWM_pulse_finish callback */ + void (*trigger_cbk)(struct timer_handle_s *arg); /**< Trigger callback */ + void (*break_cbk)(struct timer_handle_s *arg); /**< Break callback */ + void (*com_cbk)(struct timer_handle_s *arg); /**< commutation callback */ + void (*error_cbk)(struct timer_handle_s *arg); /**< Error callback */ +} timer_handle_t; + + +/** + * @brief TIMER encoder mode + */ +typedef enum { + TIMER_ENC_MODE_TI1 = 1U, /**< encoder mode 1 */ + TIMER_ENC_MODE_TI2 = 2U, /**< encoder mode 2 */ + TIMER_ENC_MODE_TI12 = 3U, /**< encoder mode 3 */ +} timer_encoder_mode_t; + +/** + * @brief TIMER input capture polarity + */ +typedef enum { + TIMER_IC_POLARITY_RISE = 0U, /**< Input capture polarity rising */ + TIMER_IC_POLARITY_FALL = 1U, /**< Input capture polarity falling */ +} timer_ic_polarity_t; + +/** + *@brief TIMER input capture selection + */ +typedef enum { + TIMER_IC_SEL_DIRECT = 1U, /**< IC1 -- TI1 */ + TIMER_IC_SEL_INDIRECT = 2U, /**< IC1 -- TI2 */ + TIMER_IC_SEL_TRC = 3U, /**< IC1 -- TRC */ +} timer_ic_select_t; + +/** + * @brief TIMER input capture prescaler + */ +typedef enum { + TIMER_IC_PSC_DIV1 = 0U, /**< Capture performed once every 1 events */ + TIMER_IC_PSC_DIV2 = 1U, /**< Capture performed once every 2 events */ + TIMER_IC_PSC_DIV4 = 2U, /**< Capture performed once every 4 events */ + TIMER_IC_PSC_DIV8 = 3U, /**< Capture performed once every 4 events */ +} timer_ic_prescaler_t; + +/** + * @brief TIMER encoder configuration structure definition + */ +typedef struct { + timer_encoder_mode_t mode; /**< Specifies the encoder mode */ + timer_ic_polarity_t ic1_polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t ic1_sel; /**< Specifies the input */ + timer_ic_prescaler_t ic1_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic1_filter; /**< Specifies the input capture filter */ + timer_ic_polarity_t ic2_polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t ic2_sel; /**< Specifies the input */ + timer_ic_prescaler_t ic2_psc; /**< Specifies the Input Capture Prescaler */ + uint32_t ic2_filter; /**< Specifies the input capture filter */ +} timer_encoder_init_t; + +/** + * @brief TIMER input capture configuration structure definition + */ +typedef struct { + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t sel; /**< Specifies the input */ + timer_ic_prescaler_t psc; /**< Specifies the Input Capture Prescaler */ + uint32_t filter; /**< Specifies the input capture filter */ +} timer_ic_init_t; + +/** + * @brief TIMER one pulse mode configuration structure definition + */ +typedef struct { + timer_oc_mode_t mode; /**< Specifies the TIMER mode */ + uint16_t pulse; /**< Specifies the pulse value */ + timer_oc_polarity_t oc_polarity; /**< Specifies the output polarity */ + timer_ocn_polarity_t ocn_polarity; /**< Specifies the complementary output polarity */ + timer_oc_idle_t oc_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + timer_ocn_idle_t ocn_idle; /**< Specifies the TIMER Output Compare pin state during Idle state */ + timer_ic_polarity_t polarity; /**< Specifies the active edge of the input signal */ + timer_ic_select_t sel; /**< Specifies the input */ + uint32_t filter; /**< Specifies the input capture filter */ +} timer_one_pulse_init_t; + +/** @brief TIMER clear input source + */ +typedef enum { + TIMER_INPUT_NONE = 0U, /**< Clear input none */ + TIMER_INPUT_ETR = 1U, /**< Clear input etr */ +} timer_clear_input_source_t; + +/** @brief TIMER clear input polarity + */ +typedef enum { + TIMER_POLARITY_NO_INV = 0U, /**< Polarity for ETRx pin */ + TIMER_POLARITY_INV = 1U, /**< Polarity for ETRx pin */ +} timer_clear_input_polarity_t; + +/** @brief TIMER clear input polarity + */ +typedef enum { + TIMER_ETR_PSC_DIV1 = 0U, /**< No prescaler is used */ + TIMER_ETR_PSC_DIV2 = 1U, /**< ETR input source is divided by 2 */ + TIMER_ETR_PSC_DIV4 = 2U, /**< ETR input source is divided by 4 */ + TIMER_ETR_PSC_DIV8 = 3U, /**< ETR input source is divided by 8 */ +} timer_etr_psc_t; + +/** @brief TIMER CHnREF Clear Select + */ +typedef enum { + TIMER_CHNREF_CLR_CMP_IN = 0U, /**< Comparator CMP_IN */ + TIMER_CHNREF_CLR_ETF = 1U, /**< External Trigger Signal ETF */ +}timer_chnref_clr_sel_t;/** + * @brief TIMER clear input configuration handle structure definition + */ +typedef struct { + type_func_t state; /**< TIMER clear Input state */ + timer_clear_input_source_t source; /**< TIMER clear Input sources */ + timer_clear_input_polarity_t polarity; /**< TIMER Clear Input polarity */ + timer_etr_psc_t psc; /**< TIMER Clear Input prescaler */ + timer_chnref_clr_sel_t clrsel; /**state = TIMER_STATE_RESET) + +/** + * @brief Enable the TIMER peripheral. + */ +#define TIMER_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK)) + +/** + * @brief Enable the TIMER main output. + */ +#define TIMER_MOE_ENABLE(hperh) (SET_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK)) + +/** + * @brief Disable the TIMER peripheral. + */ +#define TIMER_DISABLE(hperh) \ +do { \ + if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \ +} while (0) + +/** + * @brief Disable the TIMER main output. + * @note The Main Output Enable of a timer instance is disabled only if + * all the CCx and CCxN channels have been disabled + */ +#define TIMER_MOE_DISABLE(hperh) \ +do { \ + if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \ + && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \ + CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \ +} while (0) + +/** + * @brief Sets the TIMER autoreload register value on runtime without calling + * another time any Init function. + */ +#define TIMER_SET_AUTORELOAD(handle, AUTORELOAD) \ +do { \ + (handle)->perh->AR = (AUTORELOAD); \ + (handle)->init.period = (AUTORELOAD); \ +} while (0) + +/** + * @brief Gets the TIMER autoreload register value on runtime + */ +#define TIMER_GET_AUTORELOAD(handle) ((handle)->perh->AR) + +/** + * @brief Gets the TIMER count register value on runtime + */ +#define TIMER_GET_CNT(handle) ((handle)->perh->COUNT) + +/** + * @brief Gets the TIMER count direction value on runtime + */ +#define TIMER_GET_DIR(handle) (READ_BITS((handle)->perh->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS)) + +/** + * @brief CCx DMA request sent when CCx event occurs + */ +#define TIMER_CCx_DMA_REQ_CCx(handle) (CLEAR_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) + +/** + * @brief CCx DMA request sent when update event occurs + */ +#define TIMER_CCx_DMA_REQ_UPDATE(handle) (SET_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK)) + +/** + * @brief Enable channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + * TIMER_CHANNEL_4 + */ +#define TIMER_CCx_ENABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ +(SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2)))))) + +/** + * @brief Disable channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + * TIMER_CHANNEL_4 + */ +#define TIMER_CCx_DISABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \ +(CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2)))) + +/** + * @brief Enable complementary channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + */ +#define TIMER_CCxN_ENABLE(handle, ch) ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2))) + +/** + * @brief Disable complementary channel + * @param handle: TIMER handle + * @param ch: Must be one of this: + * TIMER_CHANNEL_1 + * TIMER_CHANNEL_2 + * TIMER_CHANNEL_3 + */ +#define TIMER_CCxN_DISABLE(handle, ch) ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2))) +/** + * @} + */ + +/** @defgroup TIMER_Private_Macros TIMER Private Macros + * @{ + */ + +#if defined(ES32F36xx) +#define IS_TIMER_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == AD16C4T1) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1) || \ + ((x) == BS16T0) || \ + ((x) == BS16T1) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C4T1)) +#define IS_ADTIMER_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == AD16C4T1)) +#define IS_TIMER_XOR_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == AD16C4T1) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T0) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1)) +#define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == AD16C4T1) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T0) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1)) +#define IS_TIMER_CC2_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == AD16C4T1) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1)) +#define IS_TIMER_CC4_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == AD16C4T1) || \ + ((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1)) +#define IS_TIMER_BREAK_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == AD16C4T1)) +#define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == AD16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP32C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP32C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == AD16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2)))) +#define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == AD16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == AD16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP32C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP32C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4)))) +#define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == AD16C4T0) || \ + ((x) == AD16C4T1)) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) +#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == AD16C4T0) || \ + ((x) == AD16C4T1)) +#define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) + +#endif + +#if defined(ES32F39xx) || defined(ES32F336x) +#define IS_TIMER_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1) || \ + ((x) == BS16T0) || \ + ((x) == BS16T1) || \ + ((x) == GP16C4T2) || \ + ((x) == GP16C4T3)) +#define IS_TIMER_XOR_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T2) || \ + ((x) == GP16C4T3) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1)) +#define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP32C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T2) || \ + ((x) == GP16C4T3) || \ + ((x) == GP32C4T1)) +#define IS_TIMER_CC2_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1) || \ + ((x) == GP16C4T2) || \ + ((x) == GP16C4T2) || \ + ((x) == GP16C4T3)) +#define IS_TIMER_CC4_INSTANCE(x) (((x) == GP16C4T0) || \ + ((x) == GP16C4T1) || \ + ((x) == GP16C4T2) || \ + ((x) == GP16C4T3) || \ + ((x) == GP32C4T0) || \ + ((x) == GP32C4T1)) +#define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == GP16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP32C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP32C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T3) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T2) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2)))) +#define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == GP16C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) || \ + (((x) == GP32C4T0) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP32C4T1) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2))) || \ + (((x) == GP16C4T2) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4)))) + +#define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == NULL)) && \ + (((y) == TIMER_CHANNEL_1) || \ + ((y) == TIMER_CHANNEL_2) || \ + ((y) == TIMER_CHANNEL_3) || \ + ((y) == TIMER_CHANNEL_4))) + +#define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == NULL)) + +#define IS_TIMER_BREAK_INSTANCE(x) (((x) == NULL)) + +#define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x) + +#endif + +#define IS_TIMER_COUNTER_MODE(x) (((x) == TIMER_CNT_MODE_UP) || \ + ((x) == TIMER_CNT_MODE_DOWN) || \ + ((x) == TIMER_CNT_MODE_CENTER1) || \ + ((x) == TIMER_CNT_MODE_CENTER2) || \ + ((x) == TIMER_CNT_MODE_CENTER3)) +#define IS_TIMER_CLOCK_DIVISION(x) (((x) == TIMER_CLOCK_DIV1) || \ + ((x) == TIMER_CLOCK_DIV2) || \ + ((x) == TIMER_CLOCK_DIV4)) +#define IS_TIMER_PWM_MODE(x) (((x) == TIMER_OC_MODE_PWM1) || \ + ((x) == TIMER_OC_MODE_PWM2)) +#define IS_TIMER_OC_MODE(x) (((x) == TIMER_OC_MODE_TIMERING) || \ + ((x) == TIMER_OC_MODE_ACTIVE) || \ + ((x) == TIMER_OC_MODE_INACTIVE) || \ + ((x) == TIMER_OC_MODE_TOGGLE) || \ + ((x) == TIMER_OC_MODE_FORCE_ACTIVE) || \ + ((x) == TIMER_OC_MODE_FORCE_INACTIVE) || \ + ((x) == TIMER_OC_MODE_PWM1) || \ + ((x) == TIMER_OC_MODE_PWM2)) +#define IS_TIMER_OC_POLARITY(x) (((x) == TIMER_OC_POLARITY_HIGH) || \ + ((x) == TIMER_OC_POLARITY_LOW)) +#define IS_TIMER_OCN_POLARITY(x) (((x) == TIMER_OCN_POLARITY_HIGH) || \ + ((x) == TIMER_OCN_POLARITY_LOW)) +#define IS_TIMER_OCIDLE_STATE(x) (((x) == TIMER_OC_IDLE_RESET) || \ + ((x) == TIMER_OC_IDLE_SET)) +#define IS_TIMER_OCNIDLE_STATE(x) (((x) == TIMER_OCN_IDLE_RESET) || \ + ((x) == TIMER_OCN_IDLE_SET)) +#define IS_TIMER_CHANNELS(x) (((x) == TIMER_CHANNEL_1) || \ + ((x) == TIMER_CHANNEL_2) || \ + ((x) == TIMER_CHANNEL_3) || \ + ((x) == TIMER_CHANNEL_4) || \ + ((x) == TIMER_CHANNEL_ALL)) +#define IS_TIMER_OP_MODE(x) (((x) == TIMER_OP_MODE_REPEAT) || \ + ((x) == TIMER_OP_MODE_SINGLE)) +#define IS_TIMER_OP_OUTPUT_CH(x) (((x) == TIMER_OP_OUTPUT_CHANNEL_1) || \ + ((x) == TIMER_OP_OUTPUT_CHANNEL_2)) +#define IS_TIMER_ENCODER_MODE(x) (((x) == TIMER_ENC_MODE_TI1) || \ + ((x) == TIMER_ENC_MODE_TI2) || \ + ((x) == TIMER_ENC_MODE_TI12)) +#define IS_TIMER_IC_POLARITY(x) (((x) == TIMER_IC_POLARITY_RISE) || \ + ((x) == TIMER_IC_POLARITY_FALL)) +#define IS_TIMER_IC_SELECT(x) (((x) == TIMER_IC_SEL_DIRECT) || \ + ((x) == TIMER_IC_SEL_INDIRECT) || \ + ((x) == TIMER_IC_SEL_TRC)) +#define IS_TIMER_IC_PSC(x) (((x) == TIMER_IC_PSC_DIV1) || \ + ((x) == TIMER_IC_PSC_DIV2) || \ + ((x) == TIMER_IC_PSC_DIV4) || \ + ((x) == TIMER_IC_PSC_DIV8)) +#define IS_TIMER_IC_FILTER(x) ((x) <= 0xF) +#define IS_TIMER_DEAD_TIMERE(x) ((x) <= 0xFF) +#define IS_TIMER_CLEAR_INPUT_SOURCE(x) (((x) == TIMER_INPUT_NONE) || \ + ((x) == TIMER_INPUT_ETR)) +#define IS_TIMER_CLEAR_INPUT_POLARITY(x) (((x) == TIMER_POLARITY_NO_INV) || \ + ((x) == TIMER_POLARITY_INV)) +#define IS_TIMER_ETR_PSC(x) (((x) == TIMER_ETR_PSC_DIV1) || \ + ((x) == TIMER_ETR_PSC_DIV2) || \ + ((x) == TIMER_ETR_PSC_DIV4) || \ + ((x) == TIMER_ETR_PSC_DIV8)) +#define IS_TIMER_CHNREF_CLEAR(X) (((X) == TIMER_CHNREF_CLR_CMP_IN) || \ + ((X) == TIMER_CHNREF_CLR_ETF)) +#define IS_TIMER_CLOCK_SOURCE(x) (((x) == TIMER_SRC_ETRMODE2) || \ + ((x) == TIMER_SRC_INTER) || \ + ((x) == TIMER_SRC_ITR0) || \ + ((x) == TIMER_SRC_ITR1) || \ + ((x) == TIMER_SRC_ITR2) || \ + ((x) == TIMER_SRC_ITR3) || \ + ((x) == TIMER_SRC_TI1ED) || \ + ((x) == TIMER_SRC_TI1) || \ + ((x) == TIMER_SRC_TI2) || \ + ((x) == TIMER_SRC_ETRMODE1)) +#define IS_TIMER_CLOCK_POLARITY(x) (((x) == TIMER_CLK_POLARITY_INV) || \ + ((x) == TIMER_CLK_POLARITY_NO_INV) || \ + ((x) == TIMER_CLK_POLARITY_RISE) || \ + ((x) == TIMER_CLK_POLARITY_FALL) || \ + ((x) == TIMER_CLK_POLARITY_BOTH)) +#define IS_TIMER_SLAVE_MODE(x) (((x) == TIMER_MODE_DISABLE) || \ + ((x) == TIMER_MODE_ENC1) || \ + ((x) == TIMER_MODE_ENC2) || \ + ((x) == TIMER_MODE_ENC3) || \ + ((x) == TIMER_MODE_RESET) || \ + ((x) == TIMER_MODE_GATED) || \ + ((x) == TIMER_MODE_TRIG) || \ + ((x) == TIMER_MODE_EXTERNAL1)) +#define IS_TIMER_EVENT_SOURCE(x) (((x) == TIMER_SRC_UPDATE) || \ + ((x) == TIMER_SRC_CC1) || \ + ((x) == TIMER_SRC_CC2) || \ + ((x) == TIMER_SRC_CC3) || \ + ((x) == TIMER_SRC_CC4) || \ + ((x) == TIMER_SRC_COM) || \ + ((x) == TIMER_SRC_TRIG) || \ + ((x) == TIMER_SRC_BREAK)) +#define IS_TIMER_TS(x) (((x) == TIMER_TS_ITR0) || \ + ((x) == TIMER_TS_ITR1) || \ + ((x) == TIMER_TS_ITR2) || \ + ((x) == TIMER_TS_ITR3) || \ + ((x) == TIMER_TS_TI1F_ED) || \ + ((x) == TIMER_TS_TI1FP1) || \ + ((x) == TIMER_TS_TI2FP2) || \ + ((x) == TIMER_TS_ETRF)) +#define IS_TIMER_CLOCK_LEVEL(x) (((x) == TIMER_LOCK_LEVEL_OFF) || \ + ((x) == TIMER_LOCK_LEVEL_1) || \ + ((x) == TIMER_LOCK_LEVEL_2) || \ + ((x) == TIMER_LOCK_LEVEL_3)) +#define IS_TIMER_BREAK_POLARITY(x) (((x) == TIMER_BREAK_POLARITY_LOW) || \ + ((x) == TIMER_BREAK_POLARITY_HIGH)) +#define IS_TIMER_MASTER_MODE_SEL(x) (((x) == TIMER_TRGO_RESET) || \ + ((x) == TIMER_TRGO_ENABLE) || \ + ((x) == TIMER_TRGO_UPDATE) || \ + ((x) == TIMER_TRGO_OC1) || \ + ((x) == TIMER_TRGO_OC1REF) || \ + ((x) == TIMER_TRGO_OC2REF) || \ + ((x) == TIMER_TRGO_OC3REF) || \ + ((x) == TIMER_TRGO_OC4REF)) +#define IS_TIMER_IT(x) (((x) == TIMER_IT_UPDATE) || \ + ((x) == TIMER_IT_CC1) || \ + ((x) == TIMER_IT_CC2) || \ + ((x) == TIMER_IT_CC3) || \ + ((x) == TIMER_IT_CC4) || \ + ((x) == TIMER_IT_COM) || \ + ((x) == TIMER_IT_TRIGGER) || \ + ((x) == TIMER_IT_BREAK)) +#define IS_TIMER_DMA_REQ(x) (((x) == TIMER_DMA_UPDATE) || \ + ((x) == TIMER_DMA_CC1) || \ + ((x) == TIMER_DMA_CC2) || \ + ((x) == TIMER_DMA_CC3) || \ + ((x) == TIMER_DMA_CC4) || \ + ((x) == TIMER_DMA_COM) || \ + ((x) == TIMER_DMA_TRIGGER)) +#define IS_TIMER_FLAG(x) (((x) == TIMER_FLAG_UPDATE) || \ + ((x) == TIMER_FLAG_CC1) || \ + ((x) == TIMER_FLAG_CC2) || \ + ((x) == TIMER_FLAG_CC3) || \ + ((x) == TIMER_FLAG_CC4) || \ + ((x) == TIMER_FLAG_COM) || \ + ((x) == TIMER_FLAG_TRIGGER) || \ + ((x) == TIMER_FLAG_BREAK) || \ + ((x) == TIMER_FLAG_CC1OF) || \ + ((x) == TIMER_FLAG_CC2OF) || \ + ((x) == TIMER_FLAG_CC3OF) || \ + ((x) == TIMER_FLAG_CC4OF)) +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions + * @{ + */ +/** @addtogroup TIMER_Public_Functions_Group1 + * @{ + */ +/* Time Base functions */ +ald_status_t ald_timer_base_init(timer_handle_t *hperh); +void ald_timer_base_reset(timer_handle_t *hperh); +void ald_timer_base_start(timer_handle_t *hperh); +void ald_timer_base_stop(timer_handle_t *hperh); +void ald_timer_base_start_by_it(timer_handle_t *hperh); +void ald_timer_base_stop_by_it(timer_handle_t *hperh); + +ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_base_stop_by_dma(timer_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group2 + * @{ + */ +/* Timer Output Compare functions */ +ald_status_t ald_timer_oc_init(timer_handle_t *hperh); +void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); + +ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group3 + * @{ + */ +/* Timer PWM functions */ +ald_status_t ald_timer_pwm_init(timer_handle_t *hperh); +void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint32_t freq); +void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty); +void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch); + +ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group4 + * @{ + */ +/* Timer Input Capture functions */ +ald_status_t ald_timer_ic_init(timer_handle_t *hperh); +void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); + +ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group5 + * @{ + */ +/* Timer One Pulse functions */ +ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode); +void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch); +void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch); +void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch); +void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group6 + * @{ + */ +/* Timer encoder functions */ +ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config); +void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); + +ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + uint16_t *buf1, uint16_t *buf2, uint32_t len, + uint8_t dma_ch1, uint8_t dma_ch2); +void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group7 + * @{ + */ +/* Timer hall sensor functions */ +ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config); +void ald_timer_hall_sensor_start(timer_handle_t *hperh); +void ald_timer_hall_sensor_stop(timer_handle_t *hperh); +void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh); +void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh); + +ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group8 + * @{ + */ +/* Timer complementary output compare functions */ +void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); + +ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group9 + * @{ + */ +/* Timer complementary PWM functions */ +void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); + +ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch); +void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch); + +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group10 + * @{ + */ +/* Timer complementary one pulse functions */ +void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group11 + * @{ + */ +/* Control functions */ +ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t* config, timer_channel_t ch); +ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t* config, timer_channel_t ch); +ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, + timer_channel_t ch_out, timer_channel_t ch_in); +ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch); +ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config); +ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select); +ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config); +ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config); +ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_t event); +uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch); +void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch); +void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config); +void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi); +void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi); +void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config); +void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config); +void ald_timer_irq_handler(timer_handle_t *hperh); +void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state); +void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state); +it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it); +flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag); +void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag); +/** + * @} + */ + +/** @addtogroup TIMER_Public_Functions_Group12 + * @{ + */ +/* State functions */ +timer_state_t ald_timer_get_state(timer_handle_t *hperh); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_TIMER_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_trng.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_trng.h new file mode 100644 index 00000000..39aca7eb --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_trng.h @@ -0,0 +1,217 @@ +/** + ********************************************************************************* + * + * @file ald_trng.h + * @brief Header file of TRNG module driver. + * + * @version V1.0 + * @date 26 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 26 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_TRNG_H__ +#define __ALD_TRNG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup TRNG + * @{ + */ + +/** @defgroup TRNG_Public_Types TRNG Public Types + * @{ + */ +/** + * @brief Data width + */ +typedef enum { + TRNG_DSEL_1B = 0x0U, /**< 1-bit */ + TRNG_DSEL_8B = 0x1U, /**< 8-bits */ + TRNG_DSEL_16B = 0x2U, /**< 16-bits */ + TRNG_DSEL_32B = 0x3U, /**< 32-bits */ +} trng_data_width_t; + +/** + * @brief seed type + */ +typedef enum { + TRNG_SEED_TYPE_0 = 0x0U, /**< Using 0 as seed */ + TRNG_SEED_TYPE_1 = 0x1U, /**< Using 1 as seed */ + TRNG_SEED_TYPE_LAST = 0x2U, /**< Using last seed */ + TRNG_SEED_TYPE_SEED = 0x3U, /**< Using value of register */ +} trng_seed_type_t; + +/** + * @brief TRNG init structure definition + */ +typedef struct { + trng_data_width_t data_width; /**< The width of data */ + trng_seed_type_t seed_type; /**< The seed type */ + uint32_t seed; /**< The value of seed */ + uint16_t t_start; /**< T(start) = T(trng) * 2 ^ (t_start + 1), T(start) > 1ms */ + uint8_t adjc; /**< Adjust parameter */ + type_func_t posten; /**< Data back handle function */ +} trng_init_t; + +/** + * @brief TRNG state structures definition + */ +typedef enum { + TRNG_STATE_RESET = 0x0U, /**< Peripheral is not initialized */ + TRNG_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */ + TRNG_STATE_BUSY = 0x2U, /**< An internal process is ongoing */ + TRNG_STATE_ERROR = 0x4U, /**< Error */ +} trng_state_t; + +/** + * @brief State type + */ +typedef enum { + TRNG_STATUS_START = (1U << 0), /**< Start state */ + TRNG_STATUS_DAVLD = (1U << 1), /**< Data valid state */ + TRNG_STATUS_SERR = (1U << 2), /**< Error state */ +} trng_status_t; + +/** + * @brief Interrupt type + */ +typedef enum { + TRNG_IT_START = (1U << 0), /**< Start */ + TRNG_IT_DAVLD = (1U << 1), /**< Data valid */ + TRNG_IT_SERR = (1U << 2), /**< Error */ +} trng_it_t; + +/** + * @brief Interrupt flag type + */ +typedef enum { + TRNG_IF_START = (1U << 0), /**< Start */ + TRNG_IF_DAVLD = (1U << 1), /**< Data valid */ + TRNG_IF_SERR = (1U << 2), /**< Error */ +} trng_flag_t; + +/** + * @brief TRNG Handle Structure definition + */ +typedef struct trng_handle_s { + TRNG_TypeDef *perh; /**< Register base address */ + trng_init_t init; /**< TRNG required parameters */ + uint32_t data; /**< result data */ + lock_state_t lock; /**< Locking object */ + trng_state_t state; /**< TRNG operation state */ + + void (*trng_cplt_cbk)(struct trng_handle_s *arg); /**< Trng completed callback */ + void (*err_cplt_cbk)(struct trng_handle_s *arg); /**< Trng error callback */ + void (*init_cplt_cbk)(struct trng_handle_s *arg); /**< Trng init completed callback */ +} trng_handle_t; +/** + * @} + */ + +/** @defgroup TRNG_Public_Macros TRNG Public Macros + * @{ + */ +#define TRNG_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK)) +#define TRNG_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK)) +#define TRNG_ADJM_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK)) +#define TRNG_ADJM_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK)) +/** + * @} + */ + +/** + * @defgroup TRNG_Private_Macros TRNG Private Macros + * @{ + */ +#define IS_TRNG_DATA_WIDTH(x) (((x) == TRNG_DSEL_1B) || \ + ((x) == TRNG_DSEL_8B) || \ + ((x) == TRNG_DSEL_16B) || \ + ((x) == TRNG_DSEL_32B)) +#define IS_TRNG_SEED_TYPE(x) (((x) == TRNG_SEED_TYPE_0) || \ + ((x) == TRNG_SEED_TYPE_1) || \ + ((x) == TRNG_SEED_TYPE_LAST) || \ + ((x) == TRNG_SEED_TYPE_SEED)) +#define IS_TRNG_STATUS(x) (((x) == TRNG_STATUS_START) || \ + ((x) == TRNG_STATUS_DAVLD) || \ + ((x) == TRNG_STATUS_SERR)) +#define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \ + ((x) == TRNG_IT_DAVLD) || \ + ((x) == TRNG_IT_SERR)) +#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \ + ((x) == TRNG_IF_DAVLD) || \ + ((x) == TRNG_IF_SERR)) +#define IS_TRNG_ADJC(x) ((x) < 4) +#define IS_TRNG_T_START(x) ((x) < 8) +/** + * @} + */ + +/** @addtogroup TRNG_Public_Functions + * @{ + */ +/** @addtogroup TRNG_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +extern ald_status_t ald_trng_init(trng_handle_t *hperh); +/** + * @} + */ +/** @addtogroup TRNG_Public_Functions_Group2 + * @{ + */ +/* Control functions */ +extern uint32_t ald_trng_get_result(trng_handle_t *hperh); +extern void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state); +extern flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status); +extern it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it); +extern flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag); +extern void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag); +extern void ald_trng_irq_handler(trng_handle_t *hperh); +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_TRNG_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_tsense.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_tsense.h new file mode 100644 index 00000000..39e69b03 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_tsense.h @@ -0,0 +1,215 @@ +/** + ********************************************************************************* + * + * @file ald_tsense.h + * @brief Header file of TSENSE module driver. + * + * @version V1.0 + * @date 26 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 26 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_TSENSE_H__ +#define __ALD_TSENSE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup TSENSE + * @{ + */ + +/** @defgroup TSENSE_Public_Macros TSENSE Public Macros + * @{ + */ +#define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U)) +#define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U)) +#define TSENSE_ENABLE() \ +do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_DISABLE() \ +do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_REQ_ENABLE() \ +do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_REQ_DISABLE() \ +do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_CTN_ENABLE() \ +do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_CTN_DISABLE() \ +do { \ + TSENSE_UNLOCK(); \ + CLEAR_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_RESET() \ +do { \ + TSENSE_UNLOCK(); \ + SET_BIT(TSENSE->CR, TSENSE_CR_RST_MSK); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_LTGR_WR(data) \ +do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->LTGR, (data)); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_HTGR_WR(data) \ +do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->HTGR, (data)); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_TBDR_WR(data) \ +do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->TBDR, (data)); \ + TSENSE_LOCK(); \ +} while (0) +#define TSENSE_TCALBDR_WR(data) \ +do { \ + TSENSE_UNLOCK(); \ + WRITE_REG(TSENSE->TCALBDR, (data)); \ + TSENSE_LOCK(); \ +} while (0) +/** + * @} + */ + +/** @defgroup TSENSE_Public_Types TSENSE Public Types + * @{ + */ +/** + * @brief Temperature update time + */ +typedef enum { + TSENSE_UPDATE_CYCLE_3 = 0x3U, /**< 3 Cycles */ + TSENSE_UPDATE_CYCLE_4 = 0x4U, /**< 4 Cycles */ + TSENSE_UPDATE_CYCLE_5 = 0x5U, /**< 5 Cycles */ + TSENSE_UPDATE_CYCLE_6 = 0x6U, /**< 6 Cycles */ + TSENSE_UPDATE_CYCLE_7 = 0x7U, /**< 7 Cycles */ +} tsense_update_cycle_t; + +/** + * @brief Temperature output mode + */ +typedef enum { + TSENSE_OUTPUT_MODE_200 = 0x0U, /**< 200 cycles update one temperature */ + TSENSE_OUTPUT_MODE_400 = 0x1U, /**< 400 cycles update one temperature */ + TSENSE_OUTPUT_MODE_800 = 0x2U, /**< 800 cycles update one temperature */ + TSENSE_OUTPUT_MODE_1600 = 0x3U, /**< 1600 cycles update one temperature */ + TSENSE_OUTPUT_MODE_3200 = 0x4U, /**< 3200 cycles update one temperature */ +} tsense_output_mode_t; + +/** + * @brief Source select + */ +typedef enum { + TSENSE_SOURCE_LOSC = 0x0U, /**< LOSC */ + TSENSE_SOURCE_LRC = 0x1U, /**< LRC */ +} tsense_source_sel_t; + + +/** + * @brief Define callback function type + */ +typedef void (*tsense_cbk)(uint16_t value, ald_status_t status); +/** + * @} + */ + +/** + * @defgroup TSENSE_Private_Macros TSENSE Private Macros + * @{ + */ +#define IS_TSENSE_SOURCE_SEL(x) (((x) == TSENSE_SOURCE_LOSC) || \ + ((x) == TSENSE_SOURCE_LRC)) +/** + * @} + */ + +/** @addtogroup TSENSE_Public_Functions + * @{ + */ +/** @addtogroup TSENSE_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +extern void ald_tsense_init(void); +extern void ald_tsense_source_select(tsense_source_sel_t sel); +/** + * @} + */ +/** @addtogroup TSENSE_Public_Functions_Group2 + * @{ + */ +/* Control functions */ +extern ald_status_t ald_tsense_get_value(uint16_t *tsense); +extern void ald_tsense_get_value_by_it(tsense_cbk cbk); +extern void ald_tsense_irq_handler(void); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_TSENSE_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_uart.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_uart.h new file mode 100644 index 00000000..62cefb8a --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_uart.h @@ -0,0 +1,551 @@ +/** + ********************************************************************************* + * + * @file ald_uart.h + * @brief Header file of UART module library. + * + * @version V1.0 + * @date 21 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 21 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_UART_H__ +#define __ALD_UART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" +#include "ald_dma.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/** + * @defgroup UART_Public_Macros UART Public Macros + * @{ + */ +#define UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK)) +#define UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK)) +#define UART_TX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK)) +#define UART_TX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK)) +#define UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK)) +#define UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK)) +#define UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK)) +#define UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK)) +#define UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK)) +#define UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK)) +#define UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK)) +#define UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK)) +#define UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK)) +#define UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK)) +#define UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK)) +#define UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK)) +#define UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK)) +#define UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK)) +#define UART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FCON, UART_FCON_TFRST_MSK)) +#define UART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FCON, UART_FCON_RFRST_MSK)) +#define UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK)) +#define UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK)) +#define UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK)) +#define UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK)) +#define UART_AUTOBR_REPT(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABRREPT_MSK)) +#define UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR)) +#define UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS)) +#define UART_ENABLE_SCARD_CLK(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK)) +#define UART_DISABLE_SCARD_CLK(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK)) +#define UART_ENABLE_SCARD_NACK(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK)) +#define UART_DISABLE_SCARD_NACK(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK)) +#define UART_SCARD_ENABLE(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK)) +#define UART_SCARD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK)) +/** + * @} + */ + +/** @defgroup UART_Public_Types UART Public Types + * @{ + */ +/** + * @brief UART word length + */ +typedef enum { + UART_WORD_LENGTH_8B = 0x0U, /**< 8-bits */ + UART_WORD_LENGTH_7B = 0x1U, /**< 7-bits */ + UART_WORD_LENGTH_6B = 0x2U, /**< 6-bits */ + UART_WORD_LENGTH_5B = 0x3U, /**< 5-bits */ +} uart_word_length_t; + +/** + * @brief UART stop bits + */ +typedef enum { + UART_STOP_BITS_1 = 0x0U, /**< 1-bits */ + UART_STOP_BITS_2 = 0x1U, /**< 2-bits */ + UART_STOP_BITS_0_5 = 0x0U, /**< 0.5-bits, using smartcard mode */ + UART_STOP_BITS_1_5 = 0x1U, /**< 1.5-bits, using smartcard mode */ +} uart_stop_bits_t; + +/** + * @brief UART parity + */ +typedef enum { + UART_PARITY_NONE = 0x0U, /**< Not parity */ + UART_PARITY_ODD = 0x1U, /**< Odd parity */ + UART_PARITY_EVEN = 0x3U, /**< Even parity */ +} uart_parity_t; + +/** + * @brief UART mode + */ +typedef enum { + UART_MODE_UART = 0x0U, /**< UART */ + UART_MODE_LIN = 0x1U, /**< LIN */ + UART_MODE_IrDA = 0x2U, /**< IrDA */ + UART_MODE_RS485 = 0x3U, /**< RS485 */ + UART_MODE_HDSEL = 0x4U, /**< Single-wire half-duplex */ + UART_MODE_SCARD = 0x5U, /**< Smart card */ +} uart_mode_t; + +/** + * @brief UART hardware flow control + */ +typedef enum { + UART_HW_FLOW_CTL_DISABLE = 0x0U, /**< Auto-flow-control disable */ + UART_HW_FLOW_CTL_ENABLE = 0x1U, /**< Auto-flow-control enable */ +} uart_hw_flow_ctl_t; + +/** + * @brief ALD UART state + */ +typedef enum { + UART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */ + UART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */ + UART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */ + UART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */ + UART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */ + UART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */ + UART_STATE_TIMEOUT = 0x03U, /**< Timeout state */ + UART_STATE_ERROR = 0x04U, /**< Error */ +} uart_state_t; + +/** + * @brief UART error codes + */ +typedef enum { + UART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */ + UART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */ + UART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */ + UART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */ + UART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */ + UART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */ +} uart_error_t; + +/** + * @brief UART init structure definition + */ +typedef struct { + uint32_t baud; /**< Specifies the uart communication baud rate */ + uart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */ + uart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */ + uart_parity_t parity; /**< Specifies the parity mode */ + uart_mode_t mode; /**< Specifies uart mode */ + uart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */ +} uart_init_t; + +/** + * @brief UART handle structure definition + */ +typedef struct uart_handle_s { + UART_TypeDef *perh; /**< UART registers base address */ + uart_init_t init; /**< UART communication parameters */ + uint8_t *tx_buf; /**< Pointer to UART Tx transfer Buffer */ + uint16_t tx_size; /**< UART Tx Transfer size */ + uint16_t tx_count; /**< UART Tx Transfer Counter */ + uint8_t *rx_buf; /**< Pointer to UART Rx transfer Buffer */ + uint16_t rx_size; /**< UART Rx Transfer size */ + uint16_t rx_count; /**< UART Rx Transfer Counter */ + + dma_handle_t hdmatx; /**< UART Tx DMA Handle parameters */ + dma_handle_t hdmarx; /**< UART Rx DMA Handle parameters */ + + lock_state_t lock; /**< Locking object */ + uart_state_t state; /**< UART communication state */ + uart_error_t err_code; /**< UART Error code */ + + void (*tx_cplt_cbk)(struct uart_handle_s *arg); /**< Tx completed callback */ + void (*rx_cplt_cbk)(struct uart_handle_s *arg); /**< Rx completed callback */ + void (*error_cbk)(struct uart_handle_s *arg); /**< error callback */ +} uart_handle_t; + +/** + * @brief UART RS485 configure structure definition + */ +typedef struct { + type_func_t normal; /**< Normal mode */ + type_func_t dir; /**< Auto-direction mode */ + type_func_t invert; /**< Address detection invert */ + uint8_t addr; /**< Address for compare */ +} uart_rs485_config_t; + +/** + * @brief Smart_card Rx/Tx handle retry time + */ +typedef enum { + SCARD_RETRY_CNT0 = 0x0U, /**< retry time 0 */ + SCARD_RETRY_CNT1 = 0x1U, /**< retry time 1 */ + SCARD_RETRY_CNT2 = 0x2U, /**< retry time 2 */ + SCARD_RETRY_CNT3 = 0x3U, /**< retry time 3 */ + SCARD_RETRY_CNT4 = 0x4U, /**< retry time 4 */ + SCARD_RETRY_CNT5 = 0x5U, /**< retry time 5 */ + SCARD_RETRY_CNT6 = 0x6U, /**< retry time 6 */ + SCARD_RETRY_CNT7 = 0x7U, /**< retry time 7 */ +} scard_retry_t; + +/** + * @brief UART Smart card configure structure definition + */ +typedef struct { + uint8_t block_len; /**< Specifies the data block length.*/ + uint8_t pt; /**< Specifies the protect time*/ + scard_retry_t retry; /**< Specifies retry time.*/ + uint8_t clk_div; /**< Specifies the clock division.*/ + type_func_t clk_out; /**< Specifies the clock out */ +} uart_scard_config_t; + +/** + * @brief LIN detection break length + */ +typedef enum { + LIN_BREAK_LEN_10B = 0x0U, /**< 10-bit break */ + LIN_BREAK_LEN_11B = 0x1U, /**< 11-bit break */ +} uart_lin_break_len_t; + +/** + * @brief UART TXFIFO size + */ +typedef enum { + UART_TXFIFO_EMPTY = 0x0U, /**< Empty */ + UART_TXFIFO_2BYTE = 0x1U, /**< 2-Bytes */ + UART_TXFIFO_4BYTE = 0x2U, /**< 4-Bytes */ + UART_TXFIFO_8BYTE = 0x3U, /**< 8-Bytes */ +} uart_txfifo_t; + +/** + * @brief UART RXFIFO size + */ +typedef enum { + UART_RXFIFO_1BYTE = 0x0U, /**< 1-Byte */ + UART_RXFIFO_4BYTE = 0x1U, /**< 4-Bytes */ + UART_RXFIFO_8BYTE = 0x2U, /**< 8-Bytes */ + UART_RXFIFO_14BYTE = 0x3U, /**< 14-Bytes */ +} uart_rxfifo_t; + +/** + * @brief UART auto-baud mode + */ +typedef enum { + UART_ABRMOD_1_TO_0 = 0x0U, /**< Detect bit0:1, bit1:0 */ + UART_ABRMOD_1 = 0x1U, /**< Detect bit0:1 */ + UART_ABRMOD_0_TO_1 = 0x2U, /**< Detect bit0:0, bit1:1 */ +} uart_auto_baud_mode_t; + +/** + * @brief UART DMA Requests + */ +typedef enum { + UART_DMA_REQ_TX = 0x0U, /**< TX dma */ + UART_DMA_REQ_RX = 0x1U, /**< RX dma */ +} uart_dma_req_t; + +/** + * @brief UART status types + */ +typedef enum { + UART_STATUS_PERR = (1U << 0), /**< Parity error */ + UART_STATUS_FERR = (1U << 1), /**< Framing error */ + UART_STATUS_BKERR = (1U << 2), /**< Break error */ + UART_STATUS_CTSSTA = (1U << 3), /**< Clear to send status */ + UART_STATUS_RSBUSY = (1U << 8), /**< Receive shif register busy */ + UART_STATUS_RFTH = (1U << 9), /**< Receive FIFO trigger threshold */ + UART_STATUS_RFEMPTY = (1U << 10), /**< Receive FIFO empty */ + UART_STATUS_RFFULL = (1U << 11), /**< Receive FIFO full */ + UART_STATUS_RFOERR = (1U << 12), /**< Reveive FIFO overrun error */ + UART_STATUS_RFUERR = (1U << 13), /**< Receive FIFO underrun error */ + UART_STATUS_TSBUSY = (1U << 14), /**< Transmit shit register busy */ + UART_STATUS_TFTH = (1U << 15), /**< Transmit FIFO trigger threshold */ + UART_STATUS_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */ + UART_STATUS_TFFULL = (1U << 17), /**< Transmit FIFO full */ + UART_STATUS_TFOERR = (1U << 18), /**< Transmit FIFO overrun error */ +} uart_status_t; + +/** + * @brief UART interrupt types + */ +typedef enum { + UART_IT_RXBERR = (1U << 0), /**< Receiver byte error */ + UART_IT_ABEND = (1U << 1), /**< Auto-Baud rate detection end */ + UART_IT_ABTO = (1U << 2), /**< Auto-Baud rate detection timeout */ + UART_IT_DCTS = (1U << 3), /**< Delta CTS status */ + UART_IT_RXTO = (1U << 4), /**< Receiver timeout */ + UART_IT_ADDRM = (1U << 5), /**< Addredd match */ + UART_IT_LINBK = (1U << 6), /**< Lin break detection */ + UART_IT_EOB = (1U << 7), /**< End of block */ + UART_IT_NOISE = (1U << 8), /**< Start bit noise detection */ + UART_IT_RFTH = (1U << 9), /**< Receive FIFO trigger threshold */ + UART_IT_RFFULL = (1U << 11), /**< Receive FIFO full */ + UART_IT_RFOERR = (1U << 12), /**< Receive FIFO overrun */ + UART_IT_RFUERR = (1U << 13), /**< Reveive FIFO underrun */ + UART_IT_TBC = (1U << 14), /**< Transmit shift register empty */ + UART_IT_TFTH = (1U << 15), /**< Transmit FIFO trigger threshold */ + UART_IT_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */ + UART_IT_TFOVER = (1U << 18), /**< Transmit FIFO overrun */ +} uart_it_t; + +/** + * @brief UART flags types + */ +typedef enum { + UART_IF_RXBERR = (1U << 0), /**< Receiver byte error */ + UART_IF_ABEND = (1U << 1), /**< Auto-Baud rate detection end */ + UART_IF_ABTO = (1U << 2), /**< Auto-Baud rate detection timeout */ + UART_IF_DCTS = (1U << 3), /**< Delta CTS status */ + UART_IF_RXTO = (1U << 4), /**< Receiver timeout */ + UART_IF_ADDRM = (1U << 5), /**< Addredd match */ + UART_IF_LINBK = (1U << 6), /**< Lin break detection */ + UART_IF_EOB = (1U << 7), /**< End of block */ + UART_IF_NOISE = (1U << 8), /**< Start bit noise detection */ + UART_IF_RFTH = (1U << 9), /**< Receive FIFO trigger threshold */ + UART_IF_RFFULL = (1U << 11), /**< Receive FIFO full */ + UART_IF_RFOERR = (1U << 12), /**< Receive FIFO overrun */ + UART_IF_RFUERR = (1U << 13), /**< Reveive FIFO underrun */ + UART_IF_TBC = (1U << 14), /**< Transmit shift register empty */ + UART_IF_TFTH = (1U << 15), /**< Transmit FIFO trigger threshold */ + UART_IF_TFEMPTY = (1U << 16), /**< Transmit FIFO empty */ + UART_IF_TFOVER = (1U << 18), /**< Transmit FIFO overrun */ +} uart_flag_t; +/** + * @} + */ + +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +#define IS_UART_SCARD(x)(((x) == UART4) || \ + ((x) == UART5)) +#define IS_UART_ALL(x) (((x) == UART0) || \ + ((x) == UART1) || \ + ((x) == UART2) || \ + ((x) == UART3) || \ + ((x) == UART4) || \ + ((x) == UART5)) +#define IS_UART_WORD_LENGTH(x) (((x) == UART_WORD_LENGTH_5B) || \ + ((x) == UART_WORD_LENGTH_6B) || \ + ((x) == UART_WORD_LENGTH_7B) || \ + ((x) == UART_WORD_LENGTH_8B)) +#define IS_UART_STOPBITS(x) (((x) == UART_STOP_BITS_1) || \ + ((x) == UART_STOP_BITS_2) || \ + ((x) == UART_STOP_BITS_0_5) || \ + ((x) == UART_STOP_BITS_1_5)) +#define IS_UART_PARITY(x) (((x) == UART_PARITY_NONE) || \ + ((x) == UART_PARITY_ODD) || \ + ((x) == UART_PARITY_EVEN)) +#define IS_UART_MODE(x) (((x) == UART_MODE_UART) || \ + ((x) == UART_MODE_LIN) || \ + ((x) == UART_MODE_IrDA) || \ + ((x) == UART_MODE_HDSEL) || \ + ((x) == UART_MODE_SCARD) || \ + ((x) == UART_MODE_RS485)) +#define IS_UART_HARDWARE_FLOW_CONTROL(x) \ + (((x) == UART_HW_FLOW_CTL_DISABLE) || \ + ((x) == UART_HW_FLOW_CTL_ENABLE)) +#define IS_UART_LIN_BREAK_LEN(x) (((x) == LIN_BREAK_LEN_10B) || \ + ((x) == LIN_BREAK_LEN_11B)) +#define IS_UART_TXFIFO_TYPE(x) (((x) == UART_TXFIFO_EMPTY) || \ + ((x) == UART_TXFIFO_2BYTE) || \ + ((x) == UART_TXFIFO_4BYTE) || \ + ((x) == UART_TXFIFO_8BYTE)) +#define IS_UART_RXFIFO_TYPE(x) (((x) == UART_RXFIFO_1BYTE) || \ + ((x) == UART_RXFIFO_4BYTE) || \ + ((x) == UART_RXFIFO_8BYTE) || \ + ((x) == UART_RXFIFO_14BYTE)) +#define IS_UART_AUTO_BAUD_MODE(x) (((x) == UART_ABRMOD_1_TO_0) || \ + ((x) == UART_ABRMOD_1) || \ + ((x) == UART_ABRMOD_0_TO_1)) +#define IS_UART_DMA_REQ(x) (((x) == UART_DMA_REQ_TX) || \ + ((x) == UART_DMA_REQ_RX)) +#define IS_UART_STATUS(x) (((x) == UART_STATUS_PERR) || \ + ((x) == UART_STATUS_FERR) || \ + ((x) == UART_STATUS_BKERR) || \ + ((x) == UART_STATUS_CTSSTA) || \ + ((x) == UART_STATUS_RSBUSY) || \ + ((x) == UART_STATUS_RFEMPTY) || \ + ((x) == UART_STATUS_RFFULL) || \ + ((x) == UART_STATUS_RFOERR) || \ + ((x) == UART_STATUS_RFUERR) || \ + ((x) == UART_STATUS_TSBUSY) || \ + ((x) == UART_STATUS_RFTH) || \ + ((x) == UART_STATUS_TFTH) || \ + ((x) == UART_STATUS_TFEMPTY) || \ + ((x) == UART_STATUS_TFFULL) || \ + ((x) == UART_STATUS_TFOERR)) +#define IS_UART_IT(x) (((x) == UART_IT_RXBERR) || \ + ((x) == UART_IT_ABEND) || \ + ((x) == UART_IT_ABTO) || \ + ((x) == UART_IT_DCTS) || \ + ((x) == UART_IT_RXTO) || \ + ((x) == UART_IT_ADDRM) || \ + ((x) == UART_IT_LINBK) || \ + ((x) == UART_IT_EOB) || \ + ((x) == UART_IT_NOISE) || \ + ((x) == UART_IT_RFTH) || \ + ((x) == UART_IT_RFFULL) || \ + ((x) == UART_IT_RFOERR) || \ + ((x) == UART_IT_RFUERR) || \ + ((x) == UART_IT_TBC) || \ + ((x) == UART_IT_TFTH) || \ + ((x) == UART_IT_TFEMPTY) || \ + ((x) == UART_IT_TFOVER)) +#define IS_UART_IF(x) (((x) == UART_IF_RXBERR) || \ + ((x) == UART_IF_ABEND) || \ + ((x) == UART_IF_ABTO) || \ + ((x) == UART_IF_DCTS) || \ + ((x) == UART_IF_RXTO) || \ + ((x) == UART_IF_ADDRM) || \ + ((x) == UART_IF_LINBK) || \ + ((x) == UART_IF_EOB) || \ + ((x) == UART_IF_NOISE) || \ + ((x) == UART_IF_RFTH) || \ + ((x) == UART_IF_RFFULL) || \ + ((x) == UART_IF_RFOERR) || \ + ((x) == UART_IF_RFUERR) || \ + ((x) == UART_IF_TBC) || \ + ((x) == UART_IF_TFTH) || \ + ((x) == UART_IF_TFEMPTY) || \ + ((x) == UART_IF_TFOVER)) +#define IS_UART_SCARD_CLK(x) (((x) <= 0x1F)) +#define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21)) +#define IS_UART_DATA(x) ((x) <= 0x1FF) + +#define UART_STATE_TX_MASK (1U << 4) +#define UART_STATE_RX_MASK (1U << 5) +/** + * @} + */ + +/** @addtogroup UART_Public_Functions + * @{ + */ + +/** @addtogroup UART_Public_Functions_Group1 + * @{ + */ +/* Initialization functions */ +void ald_uart_init(uart_handle_t *hperh); +void ald_uart_reset(uart_handle_t *hperh); +void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config); +void ald_uart_scard_config(uart_handle_t *hperh, uart_scard_config_t *config); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group2 + * @{ + */ +/* IO operation functions */ +ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_send_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_recv_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout); +ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size); +ald_status_t ald_uart_recv_frame_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out); + +ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel); +ald_status_t ald_uart_dma_pause(uart_handle_t *hperh); +ald_status_t ald_uart_dma_resume(uart_handle_t *hperh); +ald_status_t ald_uart_dma_stop(uart_handle_t *hperh); + +void ald_uart_irq_handler(uart_handle_t *hperh); +void ald_uart_irq_handler_fast(uart_handle_t *hperh); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group3 + * @{ + */ +/* Peripheral Control functions */ +void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state); +void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state); +void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config); +void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config); +void uart_lin_break_detect_irq(uart_handle_t *hperh, type_func_t status); +void ald_uart_lin_send_break(uart_handle_t *hperh); +void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len); +void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode); +ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout); +it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it); +flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status); +flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag); +flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag); +void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag); +/** + * @} + */ + +/** @addtogroup UART_Public_Functions_Group4 + * @{ + */ +/* Peripheral State and Errors functions */ +uart_state_t ald_uart_get_state(uart_handle_t *hperh); +uint32_t ald_uart_get_error(uart_handle_t *hperh); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_UART_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_usb.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_usb.h new file mode 100644 index 00000000..0f125170 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_usb.h @@ -0,0 +1,618 @@ +/** + ********************************************************************************* + * + * @file ald_usb.h + * @brief Header file of USB module driver. + * + * @version V1.0 + * @date 25 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 25 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_USB_H__ +#define __ALD_USB_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "utils.h" +#include "ald_rmu.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup USB + * @{ + */ + +/** @defgroup USB_Public_Macros USB Public Macros + * @{ + */ + +#define USB_POWER_ISOUP 0x00000080U +#define USB_POWER_SOFTCONN 0x00000040U +#define USB_POWER_HS_EN 0x00000020U +#define USB_POWER_HS_M 0x00000010U +#define USB_POWER_RESET 0x00000008U +#define USB_POWER_RESUME 0x00000004U +#define USB_POWER_SUSPEND 0x00000002U +#define USB_POWER_PWRDNPHY 0x00000001U + +#define USB_DEVCTL_DEV 0x00000080U +#define USB_DEVCTL_FSDEV 0x00000040U +#define USB_DEVCTL_LSDEV 0x00000020U +#define USB_DEVCTL_VBUS_M 0x00000018U +#define USB_DEVCTL_VBUS_NONE 0x00000000U +#define USB_DEVCTL_VBUS_SEND 0x00000008U +#define USB_DEVCTL_VBUS_AVALID 0x00000010U +#define USB_DEVCTL_VBUS_VALID 0x00000018U +#define USB_DEVCTL_HOST 0x00000004U +#define USB_DEVCTL_HOSTREQ 0x00000002U +#define USB_DEVCTL_SESSION 0x00000001U + +#define USB_RXCSRH1_AUTOCL 0x00000080U +#define USB_RXCSRH1_AUTORQ 0x00000040U +#define USB_RXCSRH1_ISO 0x00000040U +#define USB_RXCSRH1_DMAEN 0x00000020U +#define USB_RXCSRH1_DISNYET 0x00000010U +#define USB_RXCSRH1_PIDERR 0x00000010U +#define USB_RXCSRH1_DMAMOD 0x00000008U +#define USB_RXCSRH1_DTWE 0x00000004U +#define USB_RXCSRH1_DT 0x00000002U +#define USB_RXCSRH1_INCOMPRX 0x00000001U + +#define USB_CSRH0_DISPING 0x00000008U +#define USB_CSRH0_DTWE 0x00000004U +#define USB_CSRH0_DT 0x00000002U +#define USB_CSRH0_FLUSH 0x00000001U + +#define USB_TXCSRH1_AUTOSET 0x00000080U +#define USB_TXCSRH1_ISO 0x00000040U +#define USB_TXCSRH1_MODE 0x00000020U +#define USB_TXCSRH1_DMAEN 0x00000010U +#define USB_TXCSRH1_FDT 0x00000008U +#define USB_TXCSRH1_DMAMOD 0x00000004U +#define USB_TXCSRH1_DTWE 0x00000002U +#define USB_TXCSRH1_DT 0x00000001U + +#define USB_TXCSRL1_NAKTO 0x00000080U +#define USB_TXCSRL1_CLRDT 0x00000040U +#define USB_TXCSRL1_STALLED 0x00000020U +#define USB_TXCSRL1_STALL 0x00000010U +#define USB_TXCSRL1_SETUP 0x00000010U +#define USB_TXCSRL1_FLUSH 0x00000008U +#define USB_TXCSRL1_ERROR 0x00000004U +#define USB_TXCSRL1_UNDRN 0x00000004U +#define USB_TXCSRL1_FIFONE 0x00000002U +#define USB_TXCSRL1_TXRDY 0x00000001U + +#define USB_RXCSRL1_CLRDT 0x00000080U +#define USB_RXCSRL1_STALLED 0x00000040U +#define USB_RXCSRL1_STALL 0x00000020U +#define USB_RXCSRL1_REQPKT 0x00000020U +#define USB_RXCSRL1_FLUSH 0x00000010U +#define USB_RXCSRL1_DATAERR 0x00000008U +#define USB_RXCSRL1_NAKTO 0x00000008U +#define USB_RXCSRL1_OVER 0x00000004U +#define USB_RXCSRL1_ERROR 0x00000004U +#define USB_RXCSRL1_FULL 0x00000002U +#define USB_RXCSRL1_RXRDY 0x00000001U + +#define USB_CSRL0_NAKTO 0x00000080U +#define USB_CSRL0_SETENDC 0x00000080U +#define USB_CSRL0_STATUS 0x00000040U +#define USB_CSRL0_RXRDYC 0x00000040U +#define USB_CSRL0_REQPKT 0x00000020U +#define USB_CSRL0_STALL 0x00000020U +#define USB_CSRL0_SETEND 0x00000010U +#define USB_CSRL0_ERROR 0x00000010U +#define USB_CSRL0_DATAEND 0x00000008U +#define USB_CSRL0_SETUP 0x00000008U +#define USB_CSRL0_STALLED 0x00000004U +#define USB_CSRL0_TXRDY 0x00000002U +#define USB_CSRL0_RXRDY 0x00000001U + +#define USB_TYPE0_SPEED_M 0x000000C0U +#define USB_TYPE0_SPEED_HIGH 0x00000040U +#define USB_TYPE0_SPEED_FULL 0x00000080U +#define USB_TYPE0_SPEED_LOW 0x000000C0U + +#define USB_TXTYPE1_SPEED_M 0x000000C0U +#define USB_TXTYPE1_SPEED_DFLT 0x00000000U +#define USB_TXTYPE1_SPEED_HIGH 0x00000040U +#define USB_TXTYPE1_SPEED_FULL 0x00000080U +#define USB_TXTYPE1_SPEED_LOW 0x000000C0U +#define USB_TXTYPE1_PROTO_M 0x00000030U +#define USB_TXTYPE1_PROTO_CTRL 0x00000000U +#define USB_TXTYPE1_PROTO_ISOC 0x00000010U +#define USB_TXTYPE1_PROTO_BULK 0x00000020U +#define USB_TXTYPE1_PROTO_INT 0x00000030U +#define USB_TXTYPE1_TEP_M 0x0000000FU +#define USB_TXTYPE1_TEP_S 0U + +#define USB_LPMATTR_ENDPT_M 0x0000F000U +#define USB_LPMATTR_RMTWAK 0x00000100U +#define USB_LPMATTR_HIRD_M 0x000000F0U +#define USB_LPMATTR_LS_M 0x0000000FU +#define USB_LPMATTR_LS_L1 0x00000001U +#define USB_LPMATTR_ENDPT_S 12U +#define USB_LPMATTR_HIRD_S 4U + +#define USB_LPMCNTRL_LPMRES 0x00000002U +#define USB_LPMCNTRL_LPMXMT 0x00000001U +#define USB_LPMCNTRL_ENABLE 0x00000006U +#define USB_LPMCNTRL_DISABLE 0x00000000U + +#define USB_INTCTRL_ALL 0x000003FFU +#define USB_INTCTRL_STATUS 0x000000FFU +#define USB_INTCTRL_VBUS_ERR 0x00000080U +#define USB_INTCTRL_SESSION 0x00000040U +#define USB_INTCTRL_SESSION_END 0x00000040U +#define USB_INTCTRL_DISCONNECT 0x00000020U +#define USB_INTCTRL_CONNECT 0x00000010U +#define USB_INTCTRL_SOF 0x00000008U +#define USB_INTCTRL_BABBLE 0x00000004U +#define USB_INTCTRL_RESET 0x00000004U +#define USB_INTCTRL_RESUME 0x00000002U +#define USB_INTCTRL_SUSPEND 0x00000001U +#define USB_INTCTRL_MODE_DETECT 0x00000200U +#define USB_INTCTRL_POWER_FAULT 0x00000100U + +#define USB_INTEP_ALL 0xFFFFFFFFU +#define USB_INTEP_HOST_IN 0xFFFE0000U +#define USB_INTEP_HOST_IN_15 0x80000000U +#define USB_INTEP_HOST_IN_14 0x40000000U +#define USB_INTEP_HOST_IN_13 0x20000000U +#define USB_INTEP_HOST_IN_12 0x10000000U +#define USB_INTEP_HOST_IN_11 0x08000000U +#define USB_INTEP_HOST_IN_10 0x04000000U +#define USB_INTEP_HOST_IN_9 0x02000000U +#define USB_INTEP_HOST_IN_8 0x01000000U +#define USB_INTEP_HOST_IN_7 0x00800000U +#define USB_INTEP_HOST_IN_6 0x00400000U +#define USB_INTEP_HOST_IN_5 0x00200000U +#define USB_INTEP_HOST_IN_4 0x00100000U +#define USB_INTEP_HOST_IN_3 0x00080000U +#define USB_INTEP_HOST_IN_2 0x00040000U +#define USB_INTEP_HOST_IN_1 0x00020000U + +#define USB_INTEP_DEV_OUT 0xFFFE0000U +#define USB_INTEP_DEV_OUT_15 0x80000000U +#define USB_INTEP_DEV_OUT_14 0x40000000U +#define USB_INTEP_DEV_OUT_13 0x20000000U +#define USB_INTEP_DEV_OUT_12 0x10000000U +#define USB_INTEP_DEV_OUT_11 0x08000000U +#define USB_INTEP_DEV_OUT_10 0x04000000U +#define USB_INTEP_DEV_OUT_9 0x02000000U +#define USB_INTEP_DEV_OUT_8 0x01000000U +#define USB_INTEP_DEV_OUT_7 0x00800000U +#define USB_INTEP_DEV_OUT_6 0x00400000U +#define USB_INTEP_DEV_OUT_5 0x00200000U +#define USB_INTEP_DEV_OUT_4 0x00100000U +#define USB_INTEP_DEV_OUT_3 0x00080000U +#define USB_INTEP_DEV_OUT_2 0x00040000U +#define USB_INTEP_DEV_OUT_1 0x00020000U + +#define USB_INTEP_HOST_OUT 0x0000FFFEU +#define USB_INTEP_HOST_OUT_15 0x00008000U +#define USB_INTEP_HOST_OUT_14 0x00004000U +#define USB_INTEP_HOST_OUT_13 0x00002000U +#define USB_INTEP_HOST_OUT_12 0x00001000U +#define USB_INTEP_HOST_OUT_11 0x00000800U +#define USB_INTEP_HOST_OUT_10 0x00000400U +#define USB_INTEP_HOST_OUT_9 0x00000200U +#define USB_INTEP_HOST_OUT_8 0x00000100U +#define USB_INTEP_HOST_OUT_7 0x00000080U +#define USB_INTEP_HOST_OUT_6 0x00000040U +#define USB_INTEP_HOST_OUT_5 0x00000020U +#define USB_INTEP_HOST_OUT_4 0x00000010U +#define USB_INTEP_HOST_OUT_3 0x00000008U +#define USB_INTEP_HOST_OUT_2 0x00000004U +#define USB_INTEP_HOST_OUT_1 0x00000002U + +#define USB_INTEP_DEV_IN 0x0000FFFEU +#define USB_INTEP_DEV_IN_15 0x00008000U +#define USB_INTEP_DEV_IN_14 0x00004000U +#define USB_INTEP_DEV_IN_13 0x00002000U +#define USB_INTEP_DEV_IN_12 0x00001000U +#define USB_INTEP_DEV_IN_11 0x00000800U +#define USB_INTEP_DEV_IN_10 0x00000400U +#define USB_INTEP_DEV_IN_9 0x00000200U +#define USB_INTEP_DEV_IN_8 0x00000100U +#define USB_INTEP_DEV_IN_7 0x00000080U +#define USB_INTEP_DEV_IN_6 0x00000040U +#define USB_INTEP_DEV_IN_5 0x00000020U +#define USB_INTEP_DEV_IN_4 0x00000010U +#define USB_INTEP_DEV_IN_3 0x00000008U +#define USB_INTEP_DEV_IN_2 0x00000004U +#define USB_INTEP_DEV_IN_1 0x00000002U + +#define USB_INTEP_0 0x00000001U + +#define USB_UNDEF_SPEED 0x80000000U +#define USB_HIGH_SPEED 0x00000002U +#define USB_FULL_SPEED 0x00000001U +#define USB_LOW_SPEED 0x00000000U + +#define USB_HOST_IN_STATUS 0x114F0000U +#define USB_HOST_IN_PID_ERROR 0x10000000U +#define USB_HOST_IN_NOT_COMP 0x01000000U +#define USB_HOST_IN_STALL 0x00400000U +#define USB_HOST_IN_DATA_ERROR 0x00080000U + +#define USB_HOST_IN_NAK_TO 0x00080000U + +#define USB_HOST_IN_ERROR 0x00040000U + +#define USB_HOST_IN_FIFO_FULL 0x00020000U +#define USB_HOST_IN_PKTRDY 0x00010000U +#define USB_HOST_OUT_STATUS 0x000000A7U +#define USB_HOST_OUT_NAK_TO 0x00000080U + +#define USB_HOST_OUT_NOT_COMP 0x00000080U + +#define USB_HOST_OUT_STALL 0x00000020U +#define USB_HOST_OUT_ERROR 0x00000004U + +#define USB_HOST_OUT_FIFO_NE 0x00000002U +#define USB_HOST_OUT_PKTPEND 0x00000001U +#define USB_HOST_EP0_NAK_TO 0x00000080U + +#define USB_HOST_EP0_STATUS 0x00000040U +#define USB_HOST_EP0_ERROR 0x00000010U + +#define USB_HOST_EP0_RX_STALL 0x00000004U +#define USB_HOST_EP0_RXPKTRDY 0x00000001U +#define USB_DEV_RX_PID_ERROR 0x01000000U + +#define USB_DEV_RX_SENT_STALL 0x00400000U +#define USB_DEV_RX_DATA_ERROR 0x00080000U +#define USB_DEV_RX_OVERRUN 0x00040000U + +#define USB_DEV_RX_FIFO_FULL 0x00020000U +#define USB_DEV_RX_PKT_RDY 0x00010000U +#define USB_DEV_TX_NOT_COMP 0x00000080U + +#define USB_DEV_TX_SENT_STALL 0x00000020U +#define USB_DEV_TX_UNDERRUN 0x00000004U +#define USB_DEV_TX_FIFO_NE 0x00000002U +#define USB_DEV_TX_TXPKTRDY 0x00000001U +#define USB_DEV_EP0_SETUP_END 0x00000010U + +#define USB_DEV_EP0_SENT_STALL 0x00000004U +#define USB_DEV_EP0_IN_PKTPEND 0x00000002U +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001U + +#define USB_EP_AUTO_SET 0x00000001U +#define USB_EP_AUTO_REQUEST 0x00000002U +#define USB_EP_AUTO_CLEAR 0x00000004U +#define USB_EP_DMA_MODE_0 0x00000008U +#define USB_EP_DMA_MODE_1 0x00000010U +#define USB_EP_DIS_NYET 0x00000020U + + +#define USB_EP_MODE_ISOC 0x00000000U +#define USB_EP_MODE_BULK 0x00000100U +#define USB_EP_MODE_INT 0x00000200U +#define USB_EP_MODE_CTRL 0x00000300U +#define USB_EP_MODE_MASK 0x00000300U +#define USB_EP_SPEED_LOW 0x00000000U +#define USB_EP_SPEED_FULL 0x00001000U +#define USB_EP_SPEED_HIGH 0x00004000U +#define USB_EP_HOST_IN 0x00000000U +#define USB_EP_HOST_OUT 0x00002000U +#define USB_EP_DEV_IN 0x00002000U +#define USB_EP_DEV_OUT 0x00000000U + +#define USB_HOST_PWRFLT_LOW 0x00000010U +#define USB_HOST_PWRFLT_HIGH 0x00000030U +#define USB_HOST_PWRFLT_EP_NONE 0x00000000U +#define USB_HOST_PWRFLT_EP_TRI 0x00000140U +#define USB_HOST_PWRFLT_EP_LOW 0x00000240U +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340U +#define USB_HOST_PWREN_MAN_LOW 0x00000000U +#define USB_HOST_PWREN_MAN_HIGH 0x00000001U +#define USB_HOST_PWREN_AUTOLOW 0x00000002U +#define USB_HOST_PWREN_AUTOHIGH 0x00000003U +#define USB_HOST_PWREN_FILTER 0x00010000U + +#define USB_HOST_LPM_RMTWAKE 0x00000100U +#define USB_HOST_LPM_L1 0x00000001U +#define USB_DEV_LPM_NAK 0x00000010U +#define USB_DEV_LPM_NONE 0x00000000U +#define USB_DEV_LPM_EN 0x0000000cU +#define USB_DEV_LPM_EXTONLY 0x00000004U +#define USB_DEV_LPM_LS_RMTWAKE 0x00000100U +#define USB_DEV_LPM_LS_L1 0x00000001U +#define USB_INTLPM_ERROR 0x00000020U +#define USB_INTLPM_RESUME 0x00000010U +#define USB_INTLPM_INCOMPLETE 0x00000008U +#define USB_INTLPM_ACK 0x00000004U +#define USB_INTLPM_NYET 0x00000002U +#define USB_INTLPM_STALL 0x00000001U + +#define MAX_NAK_LIMIT 31U +#define DISABLE_NAK_LIMIT 0U + +#define MAX_PACKET_SIZE_EP0 64U +#define USB_EP_0 0U +#define USB_EP_1 1U +#define USB_EP_2 2U +#define USB_EP_3 3U +#define USB_EP_4 4U +#define USB_EP_5 5U +#define NUM_USB_EP 6U +#define IndexToUSBEP(x) ((x)) +#define USBEPToIndex(x) ((x)) + +#define USB_FIFO_SZ_8 0x00000000U +#define USB_FIFO_SZ_16 0x00000001U +#define USB_FIFO_SZ_32 0x00000002U +#define USB_FIFO_SZ_64 0x00000003U +#define USB_FIFO_SZ_128 0x00000004U +#define USB_FIFO_SZ_256 0x00000005U +#define USB_FIFO_SZ_512 0x00000006U +#define USB_FIFO_SZ_1024 0x00000007U +#define USB_FIFO_SZ_2048 0x00000008U +#define USBFIFOSizeToBytes(x) (8 << (x)) + +#define USB_TRANS_OUT 0x00000102U +#define USB_TRANS_IN 0x00000102U +#define USB_TRANS_IN_LAST 0x0000010aU +#define USB_TRANS_SETUP 0x0000110aU +#define USB_TRANS_STATUS 0x00000142U + +#define USB_DUAL_MODE_HOST 0x00000001U +#define USB_DUAL_MODE_DEVICE 0x00000081U +#define USB_DUAL_MODE_NONE 0x00000080U +#define USB_OTG_MODE_ASIDE_HOST 0x0000001dU +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001U +#define USB_OTG_MODE_ASIDE_SESS 0x00000009U +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011U +#define USB_OTG_MODE_ASIDE_DEV 0x00000019U +#define USB_OTG_MODE_BSIDE_HOST 0x0000009dU +#define USB_OTG_MODE_BSIDE_DEV 0x00000099U +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081U +#define USB_OTG_MODE_NONE 0x00000080U + +#define USB_DMA_INT_CH8 0x00000080U +#define USB_DMA_INT_CH7 0x00000040U +#define USB_DMA_INT_CH6 0x00000020U +#define USB_DMA_INT_CH5 0x00000010U +#define USB_DMA_INT_CH4 0x00000008U +#define USB_DMA_INT_CH3 0x00000004U +#define USB_DMA_INT_CH2 0x00000002U +#define USB_DMA_INT_CH1 0x00000001U +#define USB_DMA_EP_CFG_TX 0x00000001U +#define USB_DMA_EP_CFG_RX_DEV 0x00000002U +#define USB_DMA_EP_CFG_RX_HOST 0x00000004U +#define USB_DMA_EP_TX_MSK 0x94U +#define USB_DMA_EP_RX_DEV_MSK 0xA8U +#define USB_DMA_EP_RX_HOST_MSK 0xE8U +#define USB_DMA_STATUS_ERROR 0x00000100U + +#define USB_MODE_HOST_VBUS 0x00000004U +#define USB_MODE_HOST 0x00000002U +#define USB_MODE_DEV_VBUS 0x00000005U +#define USB_MODE_DEV 0x00000003U +#define USB_MODE_OTG 0x00000000U + +#define USB_RX_EPSTATUS_SHIFT 16U +#define USB_INTEP_RX_SHIFT 16U + +#define USB_DMA_CFG_START 0x00000001U +#define USB_DMA_CFG_START_NO 0x00000000U +#define USB_DMA_CFG_DIR_WR 0x00000000U +#define USB_DMA_CFG_DIR_RD 0x00000002U +#define USB_DMA_CFG_MODE_0 0x00000000U +#define USB_DMA_CFG_MODE_1 0x00000004U +#define USB_DMA_CFG_IE_DIS 0x00000000U +#define USB_DMA_CFG_IE_EN 0x00000008U +#define USB_DMA_CFG_EP_1 0x00000010U +#define USB_DMA_CFG_EP_2 0x00000020U +#define USB_DMA_CFG_EP_3 0x00000030U +#define USB_DMA_CFG_EP_4 0x00000040U +#define USB_DMA_CFG_EP_5 0x00000050U +#define USB_DMA_CFG_BURST_NONE 0x00000000U +#define USB_DMA_CFG_BURST_4 0x00000200U +#define USB_DMA_CFG_BURST_8 0x00000400U +#define USB_DMA_CFG_BURST_16 0x00000600U +#define USB_DMA_CFG_MODE_MSK 0x00000004U +#define USB_DMA_CFG_EP_POS 0x00000004U +#define USB_DMA_CFG_EP_MSK 0x000000F0U +#define USB_DMA_CH_ERR_MSK 0x100U +/** + * @} + */ + +/** @addtogroup USB_Public_Functions + * @{ + */ + +/** @addtogroup USB_Public_Functions_Group1 + * @{ + */ +/* Base functions */ +extern uint32_t ald_usb_frame_number_get(void); +extern void ald_usb_otg_session_request(bool start); +extern uint32_t ald_usb_mode_get(void); +extern void ald_usb_high_speed_enable(bool enable); +extern uint32_t ald_usb_device_speed_get(void); +extern uint32_t ald_usb_num_ep_get( void); +extern void ald_usb_control_reset(void); +extern void ald_usb_clock_output(void); +extern int ald_usb_eye_diagram_start(uint8_t *buf, uint16_t len); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group2 + * @{ + */ +/* Device functions */ +extern uint8_t ald_usb_dev_get_addr(void); +extern void ald_usb_dev_set_addr(uint8_t addr); +extern void ald_usb_dev_connect(void); +extern void ald_usb_dev_disconnect(void); +extern void ald_usb_dev_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t flags); +extern void ald_usb_dev_ep_get_config(uint32_t ep_idx, uint32_t *p_max, uint32_t *flags); +extern void ald_usb_dev_ep_data_ack(uint32_t ep_idx, bool last); +extern void ald_usb_dev_ep_stall(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_dev_ep_stall_clear(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_dev_ep_status_clear(uint32_t ep_idx, uint32_t flags); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group3 + * @{ + */ +/* Host functions */ +extern uint32_t ald_usb_host_addr_get(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_host_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags); +extern void ald_usb_host_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags); +extern void ald_usb_host_ep_data_ack(uint32_t ep_idx); +extern void ald_usb_host_ep_data_toggle(uint32_t ep_idx, bool toggle, uint32_t flags); +extern void ald_usb_host_ep_status_clear(uint32_t ep_idx, uint32_t flags); +extern uint32_t ald_usb_host_hub_addr_get(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_host_hub_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags); +extern void ald_usb_host_pwr_disable(void); +extern void ald_usb_host_pwr_enable(void); +extern void ald_usb_host_pwr_config(uint32_t flags); +extern void ald_usb_host_pwr_fault_disable(void); +extern void ald_usb_host_pwr_fault_enable(void); +extern void ald_usb_host_request_in(uint32_t ep_idx); +extern void ald_usb_host_request_in_clear(uint32_t ep_idx); +extern void ald_usb_host_request_status(void); +extern void ald_usb_host_reset(bool start); +extern void ald_usb_host_resume(bool start); +extern void ald_usb_host_suspend(void); +extern uint32_t ald_usb_host_speed_get(void); +extern void ald_usb_host_ep_speed_set(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_host_ep_ping(uint32_t ep_idx, bool enable); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group4 + * @{ + */ +/* Endpoint functions */ +extern uint32_t ald_usb_ep_data_avail(uint32_t ep_idx); +extern int32_t ald_usb_ep_data_get(uint32_t ep_idx, uint8_t *data, uint32_t *size); +extern int32_t ald_usb_ep_data_put(uint32_t ep_idx, uint8_t *data, uint32_t size); +extern int32_t ald_usb_ep_data_send(uint32_t ep_idx, uint32_t tx_type); +extern void ald_usb_ep_data_toggle_clear(uint32_t ep_idx, uint32_t flags); +extern void ald_usb_ep_req_packet_count(uint32_t ep_idx, uint32_t count); +extern uint32_t ald_usb_ep_status(uint32_t ep_idx); +extern void ald_usb_ep_dma_config(uint32_t ep_idx, uint32_t flag, type_func_t en); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group5 + * @{ + */ +/* FIFO functions */ +extern uint32_t ald_usb_fifo_addr_get(uint32_t ep_idx); +extern void ald_usb_fifo_config_get(uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags); +extern void ald_usb_fifo_config_set(uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags); +extern void ald_usb_fifo_flush(uint32_t ep_idx, uint32_t flags); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group6 + * @{ + */ +/* Interrupt functions */ +extern void ald_usb_int_disable(uint32_t flags); +extern void ald_usb_int_enable(uint32_t flags); +extern uint32_t ald_usb_int_status_get(void); +extern void ald_usb_int_disable_ep(uint32_t flags); +extern void ald_usb_int_enable_ep(uint32_t flags); +extern uint32_t ald_usb_int_status_ep_get(void); +extern void ald_usb_int_register(void); +extern void ald_usb_int_unregister(void); +extern uint32_t ald_usb_int_num_get(void); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group7 + * @{ + */ +/* DMA functions */ +extern void ald_usb_dma_channel_config(uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl); +extern void ald_usb_dma_mult_recv_start(uint32_t ep_idx); +extern void ald_usb_dma_channel_start(uint8_t ch); +extern void ald_usb_dma_channel_stop(uint8_t ch); +extern uint32_t ald_usb_dma_get_interrupt_flag(void); +extern uint32_t ald_usb_dma_get_channel_error(uint8_t ch); +extern void ald_usb_dma_clear_channel_error(uint8_t ch); +/** + * @} + */ + +/** @addtogroup USB_Public_Functions_Group8 + * @{ + */ +/* LPM functions */ +extern void ald_usb_host_lpm_send(uint32_t addr, uint32_t ep_idx); +extern void ald_usb_host_lpm_config(uint32_t resume_time, uint32_t config); +extern uint32_t ald_usb_lpm_remote_wake_is_enable(void); +extern void ald_usb_host_lpm_resume(void); +extern void ald_usb_dev_lpm_remote_wake(void); +extern void ald_usb_dev_lpm_config(uint32_t config); +extern void ald_usb_dev_lpm_enable(void); +extern void ald_usb_dev_lpm_disable(void); +extern uint32_t ald_usb_lpm_link_status_get(void); +extern uint32_t ald_usb_lpm_ep_get(void); +extern uint32_t ald_usb_lpm_int_status_get(void); +extern void ald_usb_lpm_int_disable(uint32_t ints); +extern void ald_usb_lpm_int_enable(uint32_t ints); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_wdt.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_wdt.h new file mode 100644 index 00000000..376cc6f3 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/ald_wdt.h @@ -0,0 +1,132 @@ +/** + ********************************************************************************* + * + * @file ald_wdt.h + * @brief Header file of WDT module driver. + * + * @version V1.0 + * @date 18 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 18 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ALD_WDT_H__ +#define __ALD_WDT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "utils.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup WDT + * @{ + */ + +/** @defgroup WDT_Public_Types WDT Public Types + * @{ + */ + +/** + * @brief Wwdt no dog window + */ +typedef enum { + WWDT_WIN_25 = 0x0U, /**< No dog window size: 25% */ + WWDT_WIN_50 = 0x1U, /**< No dog window size: 50% */ + WWDT_WIN_75 = 0x2U, /**< No dog window size: 75% */ + WWDT_WIN_00 = 0x3U, /**< No dog window size: 0% */ +} wwdt_win_t; + +/** + * @} + */ + +/** + * @defgroup WDT_Private_Macros WDT Private Macros + * @{ + */ +#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);} +#define WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);} +#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);} +#define IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);} + +/** + * @} + */ + +/** + * @addtogroup WDT_Private_Macros WDT Private Macros + * @{ + */ +#define IS_WWDT_WIN_TYPE(x) ((x == WWDT_WIN_25) || \ + (x == WWDT_WIN_50) || \ + (x == WWDT_WIN_75) || \ + (x == WWDT_WIN_00)) +#define IS_FUNC_STATE(x) (((x) == DISABLE) || \ + ((x) == ENABLE)) +/** + * @} + */ + +/** @addtogroup WWDT_Public_Functions + * @{ + */ +void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt); +void ald_wwdt_start(void); +uint32_t ald_wwdt_get_value(void); +it_status_t ald_wwdt_get_flag_status(void); +void ald_wwdt_clear_flag_status(void); +void ald_wwdt_feed_dog(void); +/** + * @} + */ + +/** @addtogroup IWDT_Public_Functions + * @{ + */ +void ald_iwdt_init(uint32_t load, type_func_t interrupt); +void ald_iwdt_start(void); +uint32_t ald_iwdt_get_value(void); +it_status_t ald_iwdt_get_flag_status(void); +void ald_iwdt_clear_flag_status(void); +void ald_iwdt_feed_dog(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __ALD_WDT_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/type.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/type.h new file mode 100644 index 00000000..39f0ca97 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/type.h @@ -0,0 +1,138 @@ +/** + ********************************************************************************* + * + * @file type.h + * @brief define type + * + * @version V1.0 + * @date 17 Apr 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 17 Apr 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __TYPE_H__ +#define __TYPE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#if defined (__CC_ARM) +#define __INLINE__ __inline +#define __STATIC_INLINE__ static __inline +#else +#define __INLINE__ inline +#define __STATIC_INLINE__ static inline +#endif + +#define __isr__ + +typedef enum { + RESET = 0x0U, + SET = 0x1U, +} flag_status_t, it_status_t; + +typedef enum { + BIT_RESET = 0x0U, + BIT_SET = 0x1U, +} bit_status_t; + +typedef enum { + DISABLE = 0x0U, + ENABLE = 0x1U, +} type_func_t; +#define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE)) + +typedef enum { + FALSE = 0x0U, + TRUE = 0x1U, +} type_bool_t; + +typedef enum { + UNLOCK = 0x0U, + LOCK = 0x1U, +} lock_state_t; +#define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK)) + + +#define BIT(x) ((1U << (x))) +#define BITS(s, e) ((0xffffffffU << (s)) & (0xffffffffU >> (31 - (e)))) +#define SET_BIT(reg, bit) ((reg) |= (bit)) +#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit)) +#define READ_BIT(reg, bit) ((reg) & (bit)) +#define READ_BITS(reg, msk, s) (((reg) & (msk)) >> (s)) +#define CLEAR_REG(reg) ((reg) = (0x0)) +#define WRITE_REG(reg, val) ((reg) = (val)) +#define READ_REG(reg) ((reg)) +#define MODIFY_REG(reg, clearmask, setmask) \ + WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask))) +#define UNUSED(x) ((void)(x)) + +#ifdef USE_ASSERT +#define assert_param(x) \ +do { \ + if (!(x)) { \ + __disable_irq(); \ + while (1) \ + ; \ + } \ +} while (0) +#else +#define assert_param(x) +#endif + + +#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /* PER base address */ +#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /* RAM base address */ +#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /* Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /* SRAM Address Space bit-band area */ + +__STATIC_INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val) +{ + uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; +} + +__STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val) +{ + uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2); + *((volatile uint32_t *)tmp) = (uint32_t)val; +} + +#if defined ( __GNUC__ ) + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __TYPE_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Include/utils.h b/demo/es32/Drivers/ALD/ES32F36xx/Include/utils.h new file mode 100644 index 00000000..3af657d4 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Include/utils.h @@ -0,0 +1,208 @@ +/** + ********************************************************************************* + * + * @file utils.h + * @brief This file contains the Utilities functions/types for the driver. + * + * @version V1.0 + * @date 07 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __UTILS_H__ +#define __UTILS_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include +#include "type.h" +#ifdef ES32F36xx +#include "es32f36xx.h" +#elif ES32F39xx +#include "es32f39xx.h" +#elif ES32F336x +#include "es32f336x.h" +#endif + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup UTILS + * @{ + */ + +/** @defgroup ALD_Public_Types Public Types + * @{ + */ +/** + * @brief SysTick interval + */ +extern uint32_t __systick_interval; + +/** + * @brief ALD Status structures definition + */ +typedef enum { + OK = 0x0U, /**< OK */ + ERROR = 0x1U, /**< ERROR */ + BUSY = 0x2U, /**< BUSY */ + TIMEOUT = 0x3U, /**< TIMEOUT */ +} ald_status_t; + +/** + * @brief NVIC Preemption Priority Group + */ +typedef enum { + NVIC_PRIORITY_GROUP_0 = 0x7U, /**< 0-bits for pre-emption priority 4-bits for subpriority */ + NVIC_PRIORITY_GROUP_1 = 0x6U, /**< 1-bits for pre-emption priority 3-bits for subpriority */ + NVIC_PRIORITY_GROUP_2 = 0x5U, /**< 2-bits for pre-emption priority 2-bits for subpriority */ + NVIC_PRIORITY_GROUP_3 = 0x4U, /**< 3-bits for pre-emption priority 1-bits for subpriority */ + NVIC_PRIORITY_GROUP_4 = 0x3U, /**< 4-bits for pre-emption priority 0-bits for subpriority */ +} nvic_priority_group_t; + +/** + * @brief SysTick interval definition + */ +typedef enum { + SYSTICK_INTERVAL_1MS = 1000U, /**< Interval is 1ms */ + SYSTICK_INTERVAL_10MS = 100U, /**< Interval is 10ms */ + SYSTICK_INTERVAL_100MS = 10U, /**< Interval is 100ms */ + SYSTICK_INTERVAL_1000MS = 1U, /**< Interval is 1s */ +} systick_interval_t; +/** + * @} + */ + +/** @defgroup ALD_Public_Macros Public Macros + * @{ + */ +#define ALD_MAX_DELAY 0xFFFFFFFFU +#define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET) +#define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET) +#define RESET_HANDLE_STATE(x) ((x)->state = 0) +#define __LOCK(x) \ +do { \ + if ((x)->lock == LOCK) { \ + return BUSY; \ + } \ + else { \ + (x)->lock = LOCK; \ + } \ +} while (0) +#define __UNLOCK(x) \ +do { \ + (x)->lock = UNLOCK; \ +} while (0) +#define ALD_PANIC() \ +do { \ + while (1) \ + ; \ +} while (0) +/** + * @} + */ + +/** @defgroup ALD_Private_Macros Private Macros + * @{ + */ +#define MCU_UID0_ADDR 0x000803E0U +#define MCU_UID1_ADDR 0x000803E8U +#define MCU_UID2_ADDR 0x000803ECU +#define MCU_CHIPID_ADDR 0x000803F8U +#define DWT_CR *(uint32_t *)0xE0001000U +#define DWT_CYCCNT *(volatile uint32_t *)0xE0001004U +#define DEM_CR *(uint32_t *)0xE000EDFCU +#define DEM_CR_TRCENA (1U << 24) +#define DWT_CR_CYCCNTEA (1U << 0) +#define IS_PREEMPT_PRIO(x) ((x) < 16) +#define IS_SUB_PRIO(x) ((x) < 16) +#define IS_SYSTICK_INTERVAL(x) (((x) == SYSTICK_INTERVAL_1MS) || \ + ((x) == SYSTICK_INTERVAL_10MS) || \ + ((x) == SYSTICK_INTERVAL_100MS) || \ + ((x) == SYSTICK_INTERVAL_1000MS)) +/** + * @} + */ + +/** @addtogroup ALD_Public_Functions + * @{ + */ + +/** @addtogroup ALD_Public_Functions_Group1 + * @{ + */ + +/* Initialization functions */ +void ald_cmu_init(void); +void ald_tick_init(uint32_t prio); +void ald_systick_interval_select(systick_interval_t value); + +/** + * @} + */ + +/** @addtogroup ALD_Public_Functions_Group2 + * @{ + */ +/* Peripheral Control functions */ +void ald_inc_tick(void); +void ald_systick_irq_cbk(void); +void ald_delay_ms(__IO uint32_t delay); +void ald_delay_us(__IO uint32_t delay); +uint32_t ald_get_tick(void); +void ald_suspend_tick(void); +void ald_resume_tick(void); +uint32_t ald_get_ald_version(void); +void ald_flash_wait_config(uint8_t cycle); +ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout); +void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status); +void ald_mcu_timestamp_init(void); +uint32_t ald_mcu_get_timestamp(void); +uint32_t ald_mcu_get_cpu_id(void); +void ald_mcu_get_uid(uint8_t *buf); +uint32_t ald_mcu_get_chipid(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __UTILS_H__ */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/ReleaseNote.html b/demo/es32/Drivers/ALD/ES32F36xx/ReleaseNote.html new file mode 100644 index 00000000..ff69250b --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/ReleaseNote.html @@ -0,0 +1,50 @@ + + + + +ReleaseNote +

ES32F36xx ALD Release Note

+

V1.00 2019-12-16

+
    +
  1. First release
    2. + +
+

V1.01 2020-05-07

+
    +
  1. Delete invalid member variables in can_filter_t->bank_number
    2. +
  2. Support FIFO0/FIFO1 receiving in CAN module
    3. +
  3. Add parameter check in ald_trng_init()
    4. +
  4. Add ping-pong, scatter-gather modes in DMA module
    5. +
  5. Add automatic control function of flash read waiting cycle
    6. + +
+

V1.02 2020-05-20

+
    +
  1. Modify the ADC module structure member variables
    2. +
  2. Update ADC module driver
    3. +
  3. Support ADC1 in PIS module
    4. +
  4. Add get_hclk2_clock() API in ald_cmu.h
    5. + +
+

V1.03 2020-08-24

+
    +
  1. Add API: ald_cmu_current_clock_source_get()
    2. +
  2. Add "Set/Read HCLK2 Bus Frequency Division" interface
    3. +
  3. Modify the API related to DMA in the TIMER module
    4. +
  4. Optimize the control logic of the discontinuous-scan-mode in ADC module
    5. +
  5. Optimize FIFO function in UART module
    6. +
  6. Add API: ald_dma_descriptor_cplt_get() in DMA module
    7. +
  7. Optimize ald_dma_config_sg_per() in DMA module
    8. +
  8. Fixed bug in md_usart_set_smartcard_psc()
    9. +
  9. Add API to get UID/CHIPID in utils.h
    10. +
  10. Add LDO12/LDO18 configure function in PMU module
    11. +
  11. Delete the operation of writing SSEC register in RTC module
    12. +
  12. Make the code comply with "C-STAT(STDCHECKS)" specification
    13. +
  13. Fixed a bug in ald_can.c
    14. +
  14. Fixed a bug in ald_uart.c
    15. +
  15. Optimize I2S module library functions
    16. + +
+

 

+ + \ No newline at end of file diff --git a/demo/es32/Drivers/ALD/ES32F36xx/ReleaseNote.md b/demo/es32/Drivers/ALD/ES32F36xx/ReleaseNote.md new file mode 100644 index 00000000..0762f26c --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/ReleaseNote.md @@ -0,0 +1,39 @@ +# ES32F36xx ALD Release Note + +## V1.00 2019-12-16 + +1. First release + +## V1.01 2020-05-07 + +1. Delete invalid member variables in can_filter_t->bank_number +2. Support FIFO0/FIFO1 receiving in CAN module +3. Add parameter check in ald_trng_init() +4. Add ping-pong, scatter-gather modes in DMA module +5. Add automatic control function of flash read waiting cycle + +## V1.02 2020-05-20 + +1. Modify the ADC module structure member variables +2. Update ADC module driver +3. Support ADC1 in PIS module +4. Add get_hclk2_clock() API in ald_cmu.h + +## V1.03 2020-08-24 + +1. Add API: ald_cmu_current_clock_source_get() +2. Add "Set/Read HCLK2 Bus Frequency Division" interface +3. Modify the API related to DMA in the TIMER module +4. Optimize the control logic of the discontinuous-scan-mode in ADC module +5. Optimize FIFO function in UART module +6. Add API: ald_dma_descriptor_cplt_get() in DMA module +7. Optimize ald_dma_config_sg_per() in DMA module +8. Fixed bug in md_usart_set_smartcard_psc() +9. Add API to get UID/CHIPID in utils.h +10. Add LDO12/LDO18 configure function in PMU module +11. Delete the operation of writing SSEC register in RTC module +12. Make the code comply with "C-STAT(STDCHECKS)" specification +13. Fixed a bug in ald_can.c +14. Fixed a bug in ald_uart.c +15. Optimize I2S module library functions + diff --git a/demo/es32/Drivers/ALD/ES32F36xx/SConscript b/demo/es32/Drivers/ALD/ES32F36xx/SConscript new file mode 100644 index 00000000..2fa305e9 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/SConscript @@ -0,0 +1,34 @@ +Import('ES32_SDK_ROOT') +from building import * +Import('esconfig') + +#目的1：首先生成group_ald（对应project里面的ald） +cwd = GetCurrentDir() +src =[] + +#获取Source中.c文件后将其转换成字符串 +clist=Glob('Source/*.c') +cstr="" +for i in clist: + cstr=cstr.__add__(str(i)) + + +#判断conf内的.h文件在Source中有没有对应的.c文件，有.c则添加，没有.c则不添加 +if esconfig.ald_lib_src: + for i in set(esconfig.ald_lib_src): + if i in cstr: + src.append('Source/' + i) +else: + src = Glob('Source/*.c') + +#将md_.c添加进md中，将所有md_.h都include在魔法棒c/c++里面的include paths里，将USE_ASSERT加入到魔法棒c/c++里面的define中 +include_path = [cwd + '/Include'] +group_ald = DefineGroup('ald', src, depend = [''], CPPPATH = include_path,CPPDEFINES = ['USE_ASSERT','ES32F36xx']) + + +#2.生成group_bsp（对应project里面的bsp） +srcb=[] +group_bsp = DefineGroup('bsp', srcb, depend = ['']) + +#返回group_bsp，group_ald +Return('group_ald','group_bsp') diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_acmp.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_acmp.c new file mode 100644 index 00000000..a13b2927 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_acmp.c @@ -0,0 +1,336 @@ +/** + ********************************************************************************* + * + * @file ald_acmp.c + * @brief ACMP module driver. + * + * @version V1.0 + * @date 26 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 26 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_conf.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup ACMP ACMP + * @brief ACMP module driver + * @{ + */ +#ifdef ALD_ACMP + +/** @defgroup ACMP_Public_Functions ACMP Public Functions + * @{ + */ + +/** @defgroup ACMP_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Initializes the ACMP mode according to the specified parameters in + * the acmp_init_t and create the associated handle. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_acmp_init(acmp_handle_t *hperh) +{ + uint32_t tmp = 0; + + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_MODE_TYPE(hperh->init.mode)); + assert_param(IS_ACMP_WARM_UP_TIME_TYPE(hperh->init.warm_time)); + assert_param(IS_ACMP_HYSTSEL_TYPE(hperh->init.hystsel)); + assert_param(IS_ACMP_POS_INPUT_TYPE(hperh->init.p_port)); + assert_param(IS_ACMP_NEG_INPUT_TYPE(hperh->init.n_port)); + assert_param(IS_ACMP_INACTVAL_TYPE(hperh->init.inactval)); + assert_param(IS_FUNC_STATE(hperh->init.out_inv)); + assert_param(IS_ACMP_EDGE_TYPE(hperh->init.edge)); + assert_param(hperh->init.vdd_level < 64); + + __LOCK(hperh); + tmp = ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) | + (hperh->init.inactval << ACMP_CON_INACTV_POS) | (hperh->init.hystsel << ACMP_CON_HYSTSEL_POSS)); + + hperh->perh->CON = tmp; + + tmp |= ((hperh->init.p_port << ACMP_INPUTSEL_PSEL_POSS) | (hperh->init.n_port << ACMP_INPUTSEL_NSEL_POSS) | + (hperh->init.vdd_level << ACMP_INPUTSEL_VDDLVL_POSS)); + hperh->perh->INPUTSEL = tmp; + + if (hperh->init.out_inv) + SET_BIT(hperh->perh->CON, ACMP_CON_OUTINV_MSK); + else + CLEAR_BIT(hperh->perh->CON, ACMP_CON_OUTINV_MSK); + + switch (hperh->init.edge) { + case ACMP_EDGE_NONE: + CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + case ACMP_EDGE_FALL: + SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + case ACMP_EDGE_RISE: + CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + case ACMP_EDGE_ALL: + SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK); + SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK); + break; + + default: + break; + } + + SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK); + + tmp = 0; + while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0) { + if (tmp++ >= 600000) { + __UNLOCK(hperh); + return ERROR; + } + } + + __UNLOCK(hperh); + return OK; +} +/** + * @} + */ + +/** @defgroup ACMP_Public_Functions_Group2 Interrupt operation functions + * @brief ACMP Interrupt operation functions + * @{ + */ + +/** + * @brief Enables or disables the specified ACMP interrupts. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param it: Specifies the ACMP interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref acmp_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + hperh->perh->IES = it; + else + hperh->perh->IEC = it; + + return; +} + +/** + * @brief Checks whether the specified ACMP interrupt has set or not. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param it: Specifies the ACMP interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref acmp_it_t. + * @retval it_status_t + * - SET + * - RESET + */ +it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_IT_TYPE(it)); + + if (hperh->perh->IEV & it) + return SET; + + return RESET; +} + +/** + * @brief Checks whether the specified ACMP interrupt has occurred or not. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param flag: Specifies the ACMP interrupt source to check. + * This parameter can be one of the @ref acmp_flag_t. + * @retval flag_status_t + * - SET + * - RESET + */ +flag_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_FLAG_TYPE(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** + * @brief Get the status of interrupt flag and interupt source. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP. + * @param flag: Specifies the ACMP interrupt flag. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_acmp_get_mask_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_FLAG_TYPE(flag)); + + if (hperh->perh->IFM & flag) + return SET; + + return RESET; +} + +/** @brief Clear the specified ACMP it flags. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param flag: specifies the it flag. + * This parameter can be one of the @ref acmp_flag_t. + * @retval None + */ +void ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_FLAG_TYPE(flag)); + + hperh->perh->IFC = flag; + return; +} +/** + * @} + */ +/** @defgroup ACMP_Public_Functions_Group3 Output value functions + * @brief ACMP Output value functions + * @{ + */ +/** + * @brief This function handles ACMP interrupt request. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @retval None + */ +void ald_acmp_irq_handler(acmp_handle_t *hperh) +{ + if ((ald_acmp_get_mask_flag_status(hperh, ACMP_FLAG_WARMUP)) == SET) { + ald_acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP); + + if (hperh->acmp_warmup_cplt_cbk) + hperh->acmp_warmup_cplt_cbk(hperh); + } + + if ((ald_acmp_get_mask_flag_status(hperh, ACMP_FLAG_EDGE)) == SET) { + ald_acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE); + + if (hperh->acmp_edge_cplt_cbk) + hperh->acmp_edge_cplt_cbk(hperh); + } + + return; +} + +/** + * @brief This function config acmp output. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param state: ENABLE/DISABLE. + * @retval None + */ +void ald_acmp_out_config(acmp_handle_t *hperh, type_func_t state) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + SET_BIT(hperh->perh->PORT, ACMP_PORT_PEN_MSK); + else + CLEAR_BIT(hperh->perh->PORT, ACMP_PORT_PEN_MSK); + + return; +} + +/** + * @brief This function output acmp result. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @retval output value. + */ +uint8_t ald_acmp_out_result(acmp_handle_t *hperh) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + + return (READ_BIT(hperh->perh->STAT, ACMP_STAT_OUT_MSK) >> ACMP_STAT_OUT_POS); +} + +/** @brief Check whether the specified ACMP flag is set or not. + * @param hperh: Pointer to a acmp_handle_t structure that contains + * the configuration information for the specified ACMP module. + * @param status: specifies the status to check. + * This parameter can be one of the @ref acmp_status_t. + * @retval flag_status_t + * - SET + * - RESET + */ +flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status) +{ + assert_param(IS_ACMP_TYPE(hperh->perh)); + assert_param(IS_ACMP_STATUS_TYPE(status)); + + if (hperh->perh->STAT & status) + return SET; + + return RESET; +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_ACMP */ +/** + * @} + */ +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_adc.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_adc.c new file mode 100644 index 00000000..38246e53 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_adc.c @@ -0,0 +1,1217 @@ +/** + ****************************************************************************** + * @file ald_adc.c + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) + * peripheral: + * + Initialization functions + * ++ Initialization and Configuration of ADC + * + Operation functions + * ++ Start, stop, get result of conversions of normal + * group, using 3 possible modes: polling, interruption or DMA. + * + Control functions + * ++ Channels configuration on normal group + * ++ Channels configuration on insert group + * ++ Analog Watchdog configuration + * + State functions + * ++ ADC state machine management + * ++ Interrupts and flags management + * + * @version V1.0 + * @date 28 Jun 2019 + * @author AE Team. + * @note + * Change Logs: + * Date Author Notes + * 28 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + + +#include "ald_conf.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC module driver + * @{ + */ + +#ifdef ALD_ADC + +#define INFO_ADC0DA *(uint32_t*)0x000802C0 +#define INFO_ADC1DA *(uint32_t*)0x000802C8 +#define CFG_ADC0DA *(uint32_t*)0x40083C60 +#define CFG_ADC1DA *(uint32_t*)0x40083C64 + +/** @addtogroup ADC_Private_Functions + * @{ + */ +#ifdef ALD_DMA +static void adc_dma_normal_conv_cplt(void *arg); +static void adc_dma_error(void *arg); +#endif +/** + * @} + */ + +/** @defgroup ADC_Public_Functions ADC Public Functions + * @{ + */ + +/** @defgroup ADC_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Initializes the ADC peripheral and normal group according to + * parameters specified in structure "adc_handle_t". + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_init(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_DATA_ALIGN_TYPE(hperh->init.align)); + assert_param(IS_FUNC_STATE(hperh->init.scan)); + assert_param(IS_ADC_CLK_DIV_TYPE(hperh->init.div)); + assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.n_ref)); + assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.p_ref)); + assert_param(IS_ADC_CONV_BIT_TYPE(hperh->init.data_bit)); + assert_param(IS_ADC_NCH_NR_TYPE(hperh->init.nch_nr)); + assert_param(IS_ADC_DISC_NR_TYPE(hperh->init.disc_nr)); + assert_param(IS_FUNC_STATE(hperh->init.cont)); + assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_sel)); + + if (hperh->state == ADC_STATE_RESET ) { + hperh->error_code = ADC_ERROR_NONE; + hperh->lock = UNLOCK; + } + + ADC_DISABLE(hperh); + ald_adc_reset(hperh); + hperh->state = ADC_STATE_BUSY; + MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.align << ADC_CON1_ALIGN_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.data_bit << ADC_CON0_RSEL_POSS); + + /* Enable discontinuous mode only if continuous mode is disable */ + if (hperh->init.disc == ADC_NCH_DISC_EN) { + hperh->init.scan = ENABLE; + hperh->init.cont = DISABLE; + SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS); + } + else if (hperh->init.disc == ADC_ICH_DISC_EN) { + hperh->init.scan = ENABLE; + hperh->init.cont = DISABLE; + SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS); + } + else { + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + } + + if ((hperh->init.scan == ENABLE) || (hperh->init.disc == ADC_NCH_DISC_EN)) + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.nch_nr << ADC_CHSL_NSL_POSS); + + MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.cont << ADC_CON1_CM_POS); + MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan << ADC_CON0_SCANEN_POS); + + ADC0->CCR = 0; + MODIFY_REG(ADC0->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS); + /* if the ADC clock less than 1MHz,PWRMOD should be disable*/ + MODIFY_REG(ADC0->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS); + + if (hperh->perh == ADC1) + ADC1->CCR = ADC0->CCR; + + MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS); + MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.div << ADC_CCR_CKDIV_POSS); + /* Enable adc calibration */ + SET_BIT(ADC0->CCR, ADC_CCR_TRMEN_MSK); + SET_BIT(ADC1->CCR, ADC_CCR_TRMEN_MSK); + + MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS); + ald_adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE); + ADC_ENABLE(hperh); + + hperh->error_code = ADC_ERROR_NONE; + hperh->state = ADC_STATE_READY; + return OK; +} + +/** + * @brief Deinitialize the ADC peripheral registers to their default reset + * values. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_reset(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ADC_DISABLE(hperh); + WRITE_REG(hperh->perh->CLR, 0x30F); + WRITE_REG(hperh->perh->CON0, 0x0); + WRITE_REG(hperh->perh->CON1, 0x0); + WRITE_REG(hperh->perh->CCR, 0x0); + WRITE_REG(hperh->perh->WDTH, 0xFFF); + WRITE_REG(hperh->perh->WDTL, 0x0); + WRITE_REG(hperh->perh->ICHOFF1, 0x0); + WRITE_REG(hperh->perh->ICHOFF2, 0x0); + WRITE_REG(hperh->perh->ICHOFF3, 0x0); + WRITE_REG(hperh->perh->ICHOFF4, 0x0); + WRITE_REG(hperh->perh->ICHS, 0x0); + WRITE_REG(hperh->perh->NCHS1, 0x0); + WRITE_REG(hperh->perh->NCHS2, 0x0); + WRITE_REG(hperh->perh->NCHS3, 0x0); + WRITE_REG(hperh->perh->NCHS4, 0x0); + WRITE_REG(hperh->perh->SMPT1, 0x0); + WRITE_REG(hperh->perh->SMPT2, 0x0); + WRITE_REG(hperh->perh->CHSL, 0x0); + + hperh->state = ADC_STATE_RESET; + hperh->error_code = ADC_ERROR_NONE; + return OK; +} +/** + * @} + */ + +/** @defgroup ADC_Public_Functions_Group2 IO operation functions + * @brief Input and Output operation functions + * @{ + */ + +/** + * @brief Enables ADC, starts conversion of normal group. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_start(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + return OK; +} + +/** + * @brief Stop ADC conversion of normal group (and insert channels in + * case of auto_injection mode), disable ADC peripheral. + * @note: ADC peripheral disable is forcing stop of potential + * conversion on insert group. If insert group is under use, it + * should be preliminarily stopped using ald_adc_insert_stop function. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_stop(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ADC_DISABLE(hperh); + hperh->state = ADC_STATE_READY; + + return OK; +} + +/** + * @brief Wait for normal group conversion to be completed. + * @note This function cannot be used in a particular setup: ADC configured in DMA mode. + * In this case, DMA resets the flag EOC and polling cannot be performed on each conversion. + * @note When use this function,you should be pay attention to the hperh->init.reocs_mode, + * if it is ADC_REOCS_MODE_ALL, it means the function will wait all normal rank conversion finished. + * if it is ADC_REOCS_MODE_ONE, it means the funcion will wait every normal rank conversion finished. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param timeout: Timeout value in millisecond. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) +{ + uint32_t _tick; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + _tick = ald_get_tick(); + while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK))) { + if (timeout != ALD_MAX_DELAY ) { + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { + hperh->state = ADC_STATE_TIMEOUT; + return TIMEOUT; + } + } + } + + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCHS | ADC_FLAG_NCH); + return OK; +} + +/** + * @brief Poll for conversion event. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param event_type: the ADC event type. + * This parameter can be one of the following values: + * ADC_awd_event: ADC Analog watchdog event. + * @param timeout: Timeout value in millisecond. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout) +{ + uint32_t _tick; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_EVENT_TYPE(event_type)); + + _tick = ald_get_tick(); + while (ald_adc_get_flag_status(hperh, (adc_flag_t)event_type) == RESET) { + if (timeout != ALD_MAX_DELAY ) { + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { + hperh->state = ADC_STATE_TIMEOUT; + return TIMEOUT; + } + } + } + + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_WDG); + return OK; +} + +/** + * @brief Enables ADC, starts conversion of normal group with interruption. + * Interruptions enabled in this function: + * - REOC (end of conversion of normal group) + * Each of these interruptions has its dedicated callback function. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + SET_BIT(hperh->state, ADC_STATE_BUSY_N); + ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH); + ald_adc_interrupt_config(hperh, ADC_IT_NCH, ENABLE); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + return OK; +} + +/** + * @brief Stop ADC conversion of normal group (and insert group in + * case of auto_injection mode), disable interrution of + * end-of-conversion, disable ADC peripheral. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ADC_DISABLE(hperh); + ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N); + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Enables ADC, starts conversion of normal group and transfers result + * through DMA. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param buf: The destination Buffer address. + * @param size: The length of data to be transferred from ADC peripheral to memory. + * @param channel: The DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel) +{ + if ((buf == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + SET_BIT(hperh->state, ADC_STATE_BUSY_N); + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; + + hperh->hdma.cplt_cbk = adc_dma_normal_conv_cplt; + hperh->hdma.cplt_arg = hperh; + hperh->hdma.err_cbk = adc_dma_error; + hperh->hdma.err_arg = hperh; + + ald_dma_config_struct(&hperh->hdma.config); + hperh->hdma.config.src = (void *)&hperh->perh->NCHDR; + hperh->hdma.config.dst = (void *)buf; + hperh->hdma.config.size = size; + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.msel = hperh->perh == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1; + hperh->hdma.config.msigsel = DMA_MSIGSEL_ADC; + hperh->hdma.config.burst = ENABLE; + hperh->hdma.config.channel = channel; + ald_dma_config_basic(&hperh->hdma); + + ADC_ENABLE(hperh); + SET_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK); + SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK); + + return OK; +} + +/** + * @brief Stop ADC conversion of normal group (and insert group in + * case of auto_insert mode), disable ADC DMA transfer, disable + * ADC peripheral. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param channel: The DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ADC_DISABLE(hperh); + CLEAR_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK); + ald_dma_channel_config(hperh->hdma.perh, channel, DISABLE); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N); + + return OK; +} + +/** + * @brief DMA transfer complete callback. + * @param arg: argument of the call back. + * @retval None + */ +static void adc_dma_timer_trigger_cplt(void *arg) +{ + adc_timer_config_t *hperh = (adc_timer_config_t *)arg; + + ald_timer_base_stop(&hperh->h_timer); + CLEAR_BIT(hperh->h_adc.perh->CON1, ADC_CON1_DMA_MSK); + ADC_DISABLE(&hperh->h_adc); + ald_dma_channel_config(hperh->h_dma.perh, hperh->dma_ch, DISABLE); + CLEAR_BIT(hperh->h_adc.state, ADC_STATE_BUSY_N); + + if (hperh->h_adc.normal_cplt_cbk) + hperh->h_adc.normal_cplt_cbk(&hperh->h_adc); + + return; +} + +/** + * @brief Config timer trigger adc insert channel conversion. + * @param config: Pointer to a adc_timer_config_t structure that + * contains the configuration information for the specified function. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_timer_trigger_insert(adc_timer_config_t *config) +{ + config->h_pis.perh = PIS; + config->h_pis.init.producer_clk = PIS_CLK_PCLK1; + config->h_pis.init.producer_edge = PIS_EDGE_NONE; + config->h_pis.init.consumer_clk = PIS_CLK_PCLK2; + + #if defined(ES32F36xx) + if (config->p_timer == AD16C4T0) + config->h_pis.init.producer_src = PIS_TIMER0_UPDATA; + else if (config->p_timer == AD16C4T1) + config->h_pis.init.producer_src = PIS_TIMER1_UPDATA; + else if (config->p_timer == GP32C4T0) + config->h_pis.init.producer_src = PIS_TIMER2_UPDATA; + else if (config->p_timer == GP32C4T1) + config->h_pis.init.producer_src = PIS_TIMER3_UPDATA; + else + return ERROR; + #elif defined(ES32F39xx) || defined(ES32F336x) + if (config->p_timer == GP16C4T0) + config->h_pis.init.producer_src = PIS_TIMER0_UPDATA; + else if (config->p_timer == GP16C4T1) + config->h_pis.init.producer_src = PIS_TIMER1_UPDATA; + else if (config->p_timer == GP32C4T0) + config->h_pis.init.producer_src = PIS_TIMER2_UPDATA; + else if (config->p_timer == GP32C4T1) + config->h_pis.init.producer_src = PIS_TIMER3_UPDATA; + else + return ERROR; + #endif + + if (config->p_adc == ADC0) + config->h_pis.init.consumer_trig = PIS_CH7_ADC0_INSERT; + else + return ERROR; + + ald_pis_create(&config->h_pis); + + /* Initialize TIMER */ + config->h_timer.perh = config->p_timer; + config->h_timer.init.prescaler = 0; + config->h_timer.init.mode = TIMER_CNT_MODE_UP; + config->h_timer.init.period = ((ald_cmu_get_pclk1_clock() / 1000000) * config->time); + config->h_timer.init.clk_div = TIMER_CLOCK_DIV1; + config->h_timer.init.re_cnt = 0; + ald_timer_base_init(&config->h_timer); + + config->h_adc.perh = config->p_adc; + config->h_adc.init.align = ADC_DATAALIGN_RIGHT; + config->h_adc.init.scan = DISABLE; + config->h_adc.init.cont = DISABLE; + config->h_adc.init.ich_nr = ADC_ICH_NR_1; + config->h_adc.init.disc = ADC_ALL_DISABLE; + config->h_adc.init.disc_nr = ADC_DISC_NR_1; + config->h_adc.init.data_bit = ADC_CONV_BIT_12; + config->h_adc.init.div = ADC_CKDIV_128; + config->h_adc.init.nche_sel = ADC_NCHESEL_MODE_ONE; + config->h_adc.init.n_ref = config->n_ref; + config->h_adc.init.p_ref = config->p_ref; + config->h_adc.normal_cplt_cbk = config->cplt_cbk; + config->h_adc.insert_cplt_cbk = NULL; + config->h_adc.wdg_cbk = NULL; + config->h_adc.error_cbk = NULL; + config->h_adc.ovr_cbk = NULL; + ald_adc_init(&config->h_adc); + + config->h_adc.perh->CON1 |= 0x00100000; /* rising edge trigger insert channel convert */ + config->i_config.ch = config->adc_ch; + config->i_config.idx = ADC_ICH_IDX_1; + config->i_config.samp = ADC_SAMPLETIME_4; + config->i_config.nr = ADC_ICH_NR_1; + config->i_config.auto_m = DISABLE; + ald_adc_insert_channel_config(&config->h_adc, &config->i_config); + + ADC_ENABLE(&config->h_adc); + ald_timer_base_start(&config->h_timer); + + return OK; +} + + + +/** + * @brief Config Timer trigger adc function + * @param config: Pointer to a adc_timer_config_t structure that + * contains the configuration information for the specified function. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config) +{ + config->h_pis.perh = PIS; + config->h_pis.init.producer_clk = PIS_CLK_PCLK1; + config->h_pis.init.producer_edge = PIS_EDGE_NONE; + config->h_pis.init.consumer_clk = PIS_CLK_PCLK2; + + #if defined(ES32F36xx) + if (config->p_timer == AD16C4T0) + config->h_pis.init.producer_src = PIS_TIMER0_UPDATA; + else if (config->p_timer == AD16C4T1) + config->h_pis.init.producer_src = PIS_TIMER1_UPDATA; + else if (config->p_timer == GP32C4T0) + config->h_pis.init.producer_src = PIS_TIMER2_UPDATA; + else if (config->p_timer == GP32C4T1) + config->h_pis.init.producer_src = PIS_TIMER3_UPDATA; + else + return ERROR; + #elif defined(ES32F39xx) || defined(ES32F336x) + if (config->p_timer == GP16C4T0) + config->h_pis.init.producer_src = PIS_TIMER0_UPDATA; + else if (config->p_timer == GP16C4T1) + config->h_pis.init.producer_src = PIS_TIMER1_UPDATA; + else if (config->p_timer == GP32C4T0) + config->h_pis.init.producer_src = PIS_TIMER2_UPDATA; + else if (config->p_timer == GP32C4T1) + config->h_pis.init.producer_src = PIS_TIMER3_UPDATA; + else + return ERROR; + #endif + + if (config->p_adc == ADC0) + config->h_pis.init.consumer_trig = PIS_CH6_ADC0_NORMAL; + else + return ERROR; + + ald_pis_create(&config->h_pis); + + /* Initialize TIMER */ + config->h_timer.perh = config->p_timer; + config->h_timer.init.prescaler = 0; + config->h_timer.init.mode = TIMER_CNT_MODE_UP; + config->h_timer.init.period = ((ald_cmu_get_pclk1_clock() / 1000000) * config->time); + config->h_timer.init.clk_div = TIMER_CLOCK_DIV1; + config->h_timer.init.re_cnt = 0; + ald_timer_base_init(&config->h_timer); + + config->h_adc.perh = config->p_adc; + config->h_adc.init.align = ADC_DATAALIGN_RIGHT; + config->h_adc.init.scan = DISABLE; + config->h_adc.init.cont = DISABLE; + config->h_adc.init.nch_nr = ADC_NCH_NR_1; + config->h_adc.init.disc = ADC_ALL_DISABLE; + config->h_adc.init.disc_nr = ADC_DISC_NR_1; + config->h_adc.init.data_bit = ADC_CONV_BIT_12; + config->h_adc.init.div = ADC_CKDIV_128; + config->h_adc.init.nche_sel = ADC_NCHESEL_MODE_ONE; + config->h_adc.init.n_ref = config->n_ref; + config->h_adc.init.p_ref = config->p_ref; + config->h_adc.normal_cplt_cbk = config->cplt_cbk; + config->h_adc.insert_cplt_cbk = NULL; + config->h_adc.wdg_cbk = NULL; + config->h_adc.error_cbk = NULL; + config->h_adc.ovr_cbk = NULL; + ald_adc_init(&config->h_adc); + + config->h_adc.perh->CON1 |= 0x10000000; + config->config.ch = config->adc_ch; + config->config.idx = ADC_NCH_IDX_1; + config->config.samp = ADC_SAMPLETIME_4; + ald_adc_normal_channel_config(&config->h_adc, &config->config); + + config->h_dma.cplt_cbk = adc_dma_timer_trigger_cplt; + config->h_dma.cplt_arg = config; + config->h_dma.err_cbk = adc_dma_error; + config->h_dma.err_arg = &config->h_adc; + + ald_dma_config_struct(&config->h_dma.config); + config->h_dma.perh = DMA0; + config->h_dma.config.src = (void *)&config->h_adc.perh->NCHDR; + config->h_dma.config.dst = (void *)config->buf; + config->h_dma.config.size = config->size; + config->h_dma.config.data_width = DMA_DATA_SIZE_HALFWORD; + config->h_dma.config.src_inc = DMA_DATA_INC_NONE; + config->h_dma.config.dst_inc = DMA_DATA_INC_HALFWORD; + config->h_dma.config.msel = config->p_adc == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1; + config->h_dma.config.msigsel = DMA_MSIGSEL_ADC; + config->h_dma.config.burst = ENABLE; + config->h_dma.config.channel = config->dma_ch; + ald_dma_config_basic(&config->h_dma); + + SET_BIT(config->h_adc.perh->CON1, ADC_CON1_DMA_MSK); + ADC_ENABLE(&config->h_adc); + ald_timer_base_start(&config->h_timer); + + return OK; +} +#endif + +/** + * @brief Get ADC normal group conversion result. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval ADC group normal conversion data + */ +uint32_t ald_adc_normal_get_value(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + return hperh->perh->NCHDR; +} + +/** + * @brief Enables ADC, starts conversion of insert group. + * Interruptions enabled in this function: None. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_insert_start(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICH); + + if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); + + return OK; +} + +/** + * @brief Stop conversion of insert channels. Disable ADC peripheral if + * no normal conversion is on going. + * @note If ADC must be disabled and if conversion is on going on + * normal group, function ald_adc_normal_stop must be used to stop both + * insert and normal groups, and disable the ADC. + * @note If insert group mode auto-injection is enabled, + * function ald_adc_normal_stop must be used. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_insert_stop(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + ADC_DISABLE(hperh); + hperh->state = ADC_STATE_READY; + return OK; +} + +/** + * @brief Wait for insert group conversion to be completed. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param timeout: Timeout value in millisecond. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout) +{ + uint32_t _tick; + + assert_param(IS_ADC_TYPE(hperh->perh)); + + _tick = ald_get_tick(); + + while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_ICHE_MSK))) { + if (timeout != ALD_MAX_DELAY) { + if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) { + hperh->state |= ADC_STATE_TIMEOUT; + return TIMEOUT; + } + } + } + + WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICHS | ADC_FLAG_ICH); + return OK; +} + +/** + * @brief Enables ADC, starts conversion of insert group with interruption. + * - JEOC (end of conversion of insert group) + * Each of these interruptions has its dedicated callback function. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval Status, see @ref ald_status_t.. + */ +ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + SET_BIT(hperh->state, ADC_STATE_BUSY_I); + ADC_ENABLE(hperh); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICHS | ADC_FLAG_ICH); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, ENABLE); + + if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK))) + SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK); + + return OK; +} + +/** + * @brief Stop conversion of insert channels, disable interruption of + * end-of-conversion. Disable ADC peripheral if no normal conversion + * is on going. + * @note If ADC must be disabled and if conversion is on going on + * normal group, function ald_adc_normal_stop must be used to stop both + * insert and normal groups, and disable the ADC. + * @note If insert group mode auto-injection is enabled, + * function ald_adc_normal_stop must be used. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval None + */ +ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_I); + ADC_DISABLE(hperh); + ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE); + return OK; +} + +/** + * @brief Get ADC insert group conversion result. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param idx: Index of converted ADC insert channel. + * @retval ADC group insert conversion data + */ +uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t idx) +{ + uint32_t tmp; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_ICH_IDX_TYPE(idx)); + + switch (idx) { + case ADC_ICH_IDX_1: + tmp = hperh->perh->ICHDR1; + break; + case ADC_ICH_IDX_2: + tmp = hperh->perh->ICHDR2; + break; + case ADC_ICH_IDX_3: + tmp = hperh->perh->ICHDR3; + break; + case ADC_ICH_IDX_4: + tmp = hperh->perh->ICHDR4; + break; + default: + tmp = hperh->perh->ICHDR1; + break; + } + + return tmp; +} + +/** + * @brief Handles ADC interrupt request + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval None + */ +void ald_adc_irq_handler(adc_handle_t *hperh) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + + if (ald_adc_get_it_status(hperh, ADC_IT_NCH) && ald_adc_get_flag_status(hperh, ADC_FLAG_NCH)) { + WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N); + + if (hperh->normal_cplt_cbk) + hperh->normal_cplt_cbk(hperh); + } + + if (ald_adc_get_it_status(hperh, ADC_IT_ICH) && ald_adc_get_flag_status(hperh, ADC_FLAG_ICH)) { + WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICH | ADC_FLAG_ICHS); + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_I); + + if (hperh->insert_cplt_cbk) + hperh->insert_cplt_cbk(hperh); + } + + if (ald_adc_get_it_status(hperh, ADC_IT_AWD) && ald_adc_get_flag_status(hperh, ADC_FLAG_AWD)) { + CLEAR_BIT(hperh->state, ADC_STATE_BUSY_WDG); + WRITE_REG(hperh->perh->CLR, ADC_FLAG_AWD); + + if (hperh->wdg_cbk) + hperh->wdg_cbk(hperh); + } + + if (ald_adc_get_it_status(hperh, ADC_IT_OVR) && ald_adc_get_flag_status(hperh, ADC_FLAG_OVR)) { + WRITE_REG(hperh->perh->CLR, ADC_FLAG_OVR); + hperh->error_code |= ADC_ERROR_OVR; + hperh->state |= ADC_STATE_ERROR; + + if (hperh->ovr_cbk) + hperh->ovr_cbk(hperh); + } +} + +/** + * @} + */ + +/** @defgroup ADC_Public_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ + +/** + * @brief Configures the the selected channel to be linked to the normal + * group. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param config: Structure of ADC channel for normal group. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + assert_param(IS_ADC_NCH_IDX_TYPE(config->idx)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp)); + + if (config->idx <= ADC_NCH_IDX_4 ) { + hperh->perh->NCHS1 &= ~(0x1f << (uint32_t)((config->idx - 1) << 3)); + hperh->perh->NCHS1 |= (config->ch << (uint32_t)((config->idx - 1) << 3)); + } + else if (config->idx <= ADC_NCH_IDX_8) { + hperh->perh->NCHS2 &= ~(0x1f << (uint32_t)((config->idx - 5) << 3)); + hperh->perh->NCHS2 |= (config->ch << (uint32_t)((config->idx - 5) << 3)); + } + else if (config->idx <= ADC_NCH_IDX_12) { + hperh->perh->NCHS3 &= ~(0x1f << (uint32_t)((config->idx - 9) << 3)); + hperh->perh->NCHS3 |= (config->ch << (uint32_t)((config->idx - 9) << 3)); + } + else { + hperh->perh->NCHS4 &= ~(0x1f << (uint32_t)((config->idx - 13) << 3)); + hperh->perh->NCHS4 |= (config->ch << (uint32_t)((config->idx - 13) << 3)); + } + + if (config->ch < 8) { + hperh->perh->SMPT1 &= ~(0x0f << (uint32_t)(config->ch << 2)); + hperh->perh->SMPT1 |= config->samp << (uint32_t)(config->ch << 2); + } + else if (config->ch < 16) { + hperh->perh->SMPT2 &= ~(0x0f << (uint32_t)((config->ch - 8) << 2)); + hperh->perh->SMPT2 |= config->samp << (uint32_t)((config->ch - 8) << 2); + } + else { + hperh->perh->SMPT3 &= ~(0x0f << (uint32_t)((config->ch - 16) << 2)); + hperh->perh->SMPT3 |= config->samp << (uint32_t)((config->ch - 16) << 2); + } + + return OK; +} + +/** + * @brief Configures the the selected channel to be linked to the insert + * group. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param config: Structure of ADC channel for insert group. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config) +{ + ald_status_t tmp_status = OK; + + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + assert_param(IS_ADC_ICH_IDX_TYPE(config->idx)); + assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp)); + assert_param(IS_ADC_IST_OFFSET_TYPE(config->offset)); + assert_param(IS_ADC_ICH_NR_TYPE(config->nr)); + assert_param(IS_FUNC_STATE(config->auto_m)); + + MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nr << ADC_CHSL_ISL_POSS); + hperh->perh->ICHS &= ~(0x1f << (uint32_t)((config->idx - 1) << 3)); + hperh->perh->ICHS |= config->ch << (uint32_t)((config->idx - 1) << 3); + + if (config->auto_m == ENABLE) + SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); + else + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK); + + if (hperh->init.disc == ADC_ICH_DISC_EN) { + if (config->auto_m == DISABLE) { + SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK); + } + else { + hperh->state |= ADC_STATE_ERROR; + hperh->error_code |= ADC_ERROR_INTERNAL; + tmp_status = ERROR; + } + } + + if (config->ch < 8) { + hperh->perh->SMPT1 &= ~(0x0f << (uint32_t)(config->ch << 2)); + hperh->perh->SMPT1 |= config->samp << (uint32_t)(config->ch << 2); + } + else if (config->ch < 16) { + hperh->perh->SMPT2 &= ~(0x0f << (uint32_t)((config->ch - 8) << 2)); + hperh->perh->SMPT2 |= config->samp << (uint32_t)((config->ch - 8) << 2); + } + else { + hperh->perh->SMPT3 &= ~(0x0f << (uint32_t)((config->ch - 16) << 2)); + hperh->perh->SMPT3 |= config->samp << (uint32_t)((config->ch - 16) << 2); + } + + switch (config->idx) { + case ADC_ICH_IDX_1: + hperh->perh->ICHOFF1 = config->offset; + break; + case ADC_ICH_IDX_2: + hperh->perh->ICHOFF2 = config->offset; + break; + case ADC_ICH_IDX_3: + hperh->perh->ICHOFF3 = config->offset; + break; + case ADC_ICH_IDX_4: + hperh->perh->ICHOFF4 = config->offset; + break; + default: + break; + } + + return tmp_status; +} + +/** + * @brief Configures the analog watchdog. + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @param config: Structure of ADC analog watchdog configuration + * @retval ALD status + */ +ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_ANALOG_WTD_MODE_TYPE(config->mode)); + assert_param(IS_FUNC_STATE(config->interrupt)); + assert_param(IS_HTR_TYPE(config->high_thrd)); + assert_param(IS_LTR_TYPE(config->low_thrd)); + + if ((config->mode == ADC_ANAWTD_SING_NM) + || (config->mode == ADC_ANAWTD_SING_IST) + || (config->mode == ADC_ANAWTD_SING_NMIST)) + assert_param(IS_ADC_CHANNELS_TYPE(config->ch)); + + if (config->interrupt == DISABLE) + ald_adc_interrupt_config(hperh, ADC_IT_AWD, DISABLE); + else + ald_adc_interrupt_config(hperh, ADC_IT_AWD, ENABLE); + + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHWDTEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHWDEN_MSK); + CLEAR_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK); + hperh->perh->CON0 |= config->mode; + + if (READ_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK)) + MODIFY_REG(hperh->perh->CON0, ADC_CON0_AWDCH_MSK, config->ch << ADC_CON0_AWDCH_POSS); + + WRITE_REG(hperh->perh->WDTL, config->low_thrd); + WRITE_REG(hperh->perh->WDTH, config->high_thrd); + SET_BIT(hperh->state, ADC_STATE_BUSY_WDG); + + return OK; +} + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param hperh: Pointer to a adc_handle_t structure. + * @param it: Specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref adc_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_IT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->CON0, it); + else + CLEAR_BIT(hperh->perh->CON0, it); + + return; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param hperh: Pointer to a adc_handle_t structure. + * @param it: Specifies the ADC interrupt source to check. + * This parameter can be one of the @ref adc_it_t. + * @retval Status + * - SET + * - RESET + */ +it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_IT_TYPE(it)); + + if (READ_BIT(hperh->perh->CON0, it)) + return SET; + + return RESET; +} + +/** @brief Check whether the specified ADC flag is set or not. + * @param hperh: Pointer to a adc_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref adc_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_FLAGS_TYPE(flag)); + + if (READ_BIT(hperh->perh->STAT, flag)) + return SET; + + return RESET; +} + +/** @brief Clear the specified ADC pending flags. + * @param hperh: Pointer to a adc_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref adc_flag_t. + * @retval None + */ +void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag) +{ + assert_param(IS_ADC_TYPE(hperh->perh)); + assert_param(IS_ADC_FLAGS_TYPE(flag)); + + WRITE_REG(hperh->perh->CLR, flag); + return; +} +/** + * @} + */ + +/** @defgroup ADC_Public_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ + +/** + * @brief return the ADC state + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval state + */ +uint32_t ald_adc_get_state(adc_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the ADC error code + * @param hperh: Pointer to a adc_handle_t structure that contains + * the configuration information for the specified ADC module. + * @retval ADC Error Code + */ +uint32_t ald_adc_get_error(adc_handle_t *hperh) +{ + return hperh->error_code; +} + + +/** + * @brief Adc offset adjust + * @param refmv: ADC reference voltage, unit: mV. + * @retval None + */ +void ald_adc_offset_adjust(uint32_t refmv) +{ + uint32_t tmp = 0, os = 0; + + if (refmv == 0) return; + + *((volatile uint32_t *)(0x40080000)) = 0x55AA6996; + *((volatile uint32_t *)(0x40080100)) = 0x5A962814; + *((volatile uint32_t *)(0x40080100)) = 0xE7CB69A5; + + tmp = INFO_ADC0DA; + os = tmp & 0x7F; + os = (uint32_t)((os * 5000) / refmv + 0.5); + tmp = tmp & 0xFF80; + tmp |= os; + tmp |= 0x55AA0000; + CFG_ADC0DA = tmp; + + tmp = INFO_ADC1DA; + os = tmp & 0x7F; + os = (uint32_t)((os * 5000) / refmv + 0.5); + tmp = tmp & 0xFF80; + tmp |= os; + tmp |= 0x55AA0000; + CFG_ADC1DA = tmp; + + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080000)) = 0x123456; +} + +/** + *@} + */ + +/** + *@} + */ + +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +#ifdef ALD_DMA +/** + * @brief DMA transfer complete callback. + * @param arg: argument of the call back. + * @retval None + */ +static void adc_dma_normal_conv_cplt(void *arg) +{ + adc_handle_t *hperh = (adc_handle_t *)arg; + + CLEAR_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK); + + if (hperh->normal_cplt_cbk) + hperh->normal_cplt_cbk(hperh); + +} + +/** + * @brief DMA error callback + * @param arg: argument of the call back. + * @retval None + */ +static void adc_dma_error(void *arg) +{ + adc_handle_t *hperh = (adc_handle_t *)arg; + hperh->state |= ADC_STATE_ERROR; + hperh->error_code |= ADC_ERROR_DMA; + + if (hperh->error_cbk) + hperh->error_cbk(hperh); +} +#endif +/** + *@} + */ + +#endif /* ALD_ADC */ + +/** + *@} + */ + +/** + *@} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_bkpc.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_bkpc.c new file mode 100644 index 00000000..459f54e4 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_bkpc.c @@ -0,0 +1,185 @@ +/** + ********************************************************************************* + * + * @file ald_bkpc.c + * @brief BKPC module driver. + * + * @version V1.0 + * @date 15 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 15 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_conf.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup BKPC BKPC + * @brief BKPC module driver + * @{ + */ +#ifdef ALD_BKPC + +/** @defgroup BKPC_Public_Functions BKPC Public Functions + * @{ + */ + +/** @addtogroup BKPC_Public_Functions_Group1 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) ald_bkpc_standby_wakeup_config() API can configure STANDBY wakeup. + (+) ald_bkpc_rtc_clock_config() API can configure RTC clock. + (+) ald_bkpc_tsense_clock_config() API can configure Tsense clock. + + @endverbatim + * @{ + */ + +/** + * @brief Configure standby wakeup in backup field + * @param port: Wakeup port + * @param level: HIGH/LOW. + * @retval None + */ +void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level) +{ + assert_param(IS_BKPC_WAKEUP_PORT(port)); + assert_param(IS_BKPC_WAKEUP_LEVEL(level)); + + if (port == PMU_STANDBY_PORT_SEL_NONE) { + BKPC_UNLOCK(); + CLEAR_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK); + SET_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK); + BKPC_LOCK(); + return; + } + + BKPC_UNLOCK(); + SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK | BKPC_CR_MRST_WKPEN_MSK); + MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS); + MODIFY_REG(BKPC->CR, BKPC_CR_WKPOL_MSK, level << BKPC_CR_WKPOL_POS); + BKPC_LOCK(); + + return; +} + +/** + * @brief Configure rtc clock in backup field + * @param clock: Clock + * @retval None + */ +void ald_bkpc_rtc_clock_config(bkpc_preh_clk_t clock) +{ + assert_param(IS_BKPC_PREH_CLOCK(clock)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, clock << BKPC_PCCR_RTCCS_POSS); + BKPC_LOCK(); + + return; +} + +/** + * @brief Configure tsense clock in backup field + * @param clock: Clock + * @retval None + */ +void ald_bkpc_tsense_clock_config(bkpc_preh_clk_t clock) +{ + assert_param(IS_BKPC_PREH_CLOCK(clock)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, clock << BKPC_PCCR_TSENSECS_POSS); + BKPC_LOCK(); + + return; +} +/** + * @} + */ + +/** @addtogroup BKPC_Public_Functions_Group2 IO operation functions + * @brief IO operation functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) ald_bkpc_write_ram() API can write data in backup ram. + (+) ald_bkpc_read_ram() API can read data from backup ram. + + @endverbatim + * @{ + */ + +/** + * @brief Write data into backup ram. + * @param idx: Index of backup word. + * @param value: Value which will be written to backup ram. + * @retval None + */ +void ald_bkpc_write_ram(uint8_t idx, uint32_t value) +{ + assert_param(IS_BKPC_RAM_IDX(idx)); + + RTC_UNLOCK(); + WRITE_REG(RTC->BKPR[idx], value); + RTC_LOCK(); + + return; +} + +/** + * @brief Read data from backup ram. + * @param idx: Index of backup word. + * @retval The data. + */ +uint32_t ald_bkpc_read_ram(uint8_t idx) +{ + assert_param(IS_BKPC_RAM_IDX(idx)); + + return READ_REG(RTC->BKPR[idx]); +} +/** + * @} + */ + +/** + * @} + */ +#endif /* ALD_BKPC */ +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_calc.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_calc.c new file mode 100644 index 00000000..6eafabf8 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_calc.c @@ -0,0 +1,81 @@ +/** + ********************************************************************************* + * + * @file ald_calc.c + * @brief CALC module driver. + * + * @version V1.0 + * @date 26 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 26 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup CALC CALC + * @brief CALC module driver + * @{ + */ +#ifdef ALD_CALC + +/** @defgroup CALC_Public_Functions CALC Public Functions + * @brief Accelerating calculate functions + * + * @verbatim + ============================================================================== + ##### Accelerating calculate functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Square root operation. + + @endverbatim + * @{ + */ + +/** + * @brief Square root operation. + * @param data: The radicand. + * @retval The value of square root. + */ +uint32_t ald_calc_sqrt(uint32_t data) +{ + WRITE_REG(CALC->RDCND, data); + while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK)); + + return READ_REG(CALC->SQRTRES); +} +/** + * @} + */ +#endif /* ALD_CALC */ +/** + * @} + */ +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_can.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_can.c new file mode 100644 index 00000000..ad856834 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_can.c @@ -0,0 +1,1121 @@ +/** + ****************************************************************************** + * @file ald_can.c + * @brief CAN module driver. + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * @version V1.0 + * @date 25 Apr 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 25 Apr 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the CAN controller interface clock. + (#) CAN pins configuration + (++) Enable the clock for the CAN GPIOs; + (++) Connect and configure the involved CAN pins using the + following function ald_gpio_init(); + (#) Initialise and configure the CAN using ald_can_init() function. + (#) Transmit the CAN frame using ald_can_send()/ald_can_send_by_it() function. + (#) Receive a CAN frame using ald_can_recv()/ald_can_recv_by_it function. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the CAN peripheral transmission and wait the end of this operation + using ald_can_send(), at this stage user can specify the value of timeout + according to his end application. + (+) Start the CAN peripheral reception and wait the end of this operation + using ald_can_recv(), at this stage user can specify the value of timeout + according to his end application + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the CAN peripheral transmission using ald_can_send_by_it() + (+) Start the CAN peripheral reception using ald_can_recv_by_it() + (+) Use ald_can_irq_handler() called under the used CAN Interrupt subroutine + (+) At CAN end of transmission pherh->tx_cplt_cbk() function is executed and user can + add his own code by customization of function pointer pherh->tx_cplt_cbk() + (+) In case of CAN Error, pherh->rx_cplt_cbk() function is executed and user can + add his own code by customization of function pointer pherh->rx_cplt_cbk() + + *** CAN ALD driver macros list *** + ============================================= + [..] + Below the list of most used macros in CAN driver. + + (+) CAN_RESET_HANDLE_STATE(): Reset CAN handle state. + (+) CAN_RX_MSG_PENDING(): Return the number of pending received messages. + (+) CAN_DBG_FREEZE(): Enable or disables the DBG Freeze for CAN. + + [..] + (@) You can refer to the CAN driver header file for used the macros + + @endverbatim + ****************************************************************************** + */ + +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup CAN CAN + * @brief CAN module driver + * @{ + */ +#ifdef ALD_CAN + +/** @addtogroup CAN_Private_Functions CAN Private Functions + * @{ + */ +static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num); +static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err); +static ald_status_t __can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num); +static int __can_rx_check(can_handle_t *hperh, can_rx_fifo_t num); +/** + * @} + */ + +/** @defgroup CAN_Public_Functions CAN Public Functions + * @{ + */ + +/** @defgroup CAN_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + * @verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the CAN. + (+) Configures the CAN reception filter. + (+) Reset the CAN. + + @endverbatim + * @{ + */ + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_init_t. + * @param hperh: pointer to a can_handle_t structure that contains + * the configuration information for the specified CAN. + * @retval Status, see ald_status_t. + */ +ald_status_t ald_can_init(can_handle_t *hperh) +{ + uint32_t tickstart = 0; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_FUNC_STATE(hperh->init.ttcm)); + assert_param(IS_FUNC_STATE(hperh->init.abom)); + assert_param(IS_FUNC_STATE(hperh->init.awk)); + assert_param(IS_FUNC_STATE(hperh->init.artx)); + assert_param(IS_FUNC_STATE(hperh->init.rfom)); + assert_param(IS_FUNC_STATE(hperh->init.txmp)); + assert_param(IS_CAN_MODE(hperh->init.mode)); + assert_param(IS_CAN_SJW(hperh->init.sjw)); + assert_param(IS_CAN_BS1(hperh->init.seg1)); + assert_param(IS_CAN_BS2(hperh->init.seg2)); + assert_param(IS_CAN_PRESCALER(hperh->init.psc)); + + if (hperh->state == CAN_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = CAN_STATE_BUSY; + tickstart = ald_get_tick(); + + CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); + SET_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); + + while (!READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) { + if ((ald_get_tick() - tickstart) > CAN_TIMEOUT_VALUE) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + + return TIMEOUT; + } + } + + MODIFY_REG(hperh->perh->CON, CAN_CON_TTCEN_MSK, hperh->init.ttcm << CAN_CON_TTCEN_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_ABOFFEN_MSK, hperh->init.abom << CAN_CON_ABOFFEN_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_AWKEN_MSK, hperh->init.awk << CAN_CON_AWKEN_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_ARTXDIS_MSK, hperh->init.artx << CAN_CON_ARTXDIS_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_RXFOPM_MSK, hperh->init.rfom << CAN_CON_RXFOPM_POS); + MODIFY_REG(hperh->perh->CON, CAN_CON_TXMP_MSK, hperh->init.txmp << CAN_CON_TXMP_POS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_LOOP_MSK, (hperh->init.mode & 0x1) << CAN_BTIME_LOOP_POS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SILENT_MSK, ((hperh->init.mode >> 1) & 0x1) << CAN_BTIME_SILENT_POS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_RESJW_MSK, hperh->init.sjw << CAN_BTIME_RESJW_POSS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SEG1_MSK, hperh->init.seg1 << CAN_BTIME_SEG1_POSS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SEG2_MSK, hperh->init.seg2 << CAN_BTIME_SEG2_POSS); + MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_BPSC_MSK, (hperh->init.psc - 1) << CAN_BTIME_BPSC_POSS); + + CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); + tickstart = ald_get_tick(); + + while (READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) { + if ((ald_get_tick() - tickstart) > CAN_TIMEOUT_VALUE) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + + return TIMEOUT; + } + } + + hperh->err = CAN_ERROR_NONE; + hperh->state = CAN_STATE_READY; + + return OK; +} + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the can_filter_t. + * @param hperh: pointer to a can_handle_t structure. + * @param config: pointer to a can_filter_t structure that + * contains the filter configuration information. + * @retval Status, see ald_status_t. + */ +ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config) +{ + uint32_t pos; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_FILTER_NUMBER(config->number)); + assert_param(IS_CAN_FILTER_MODE(config->mode)); + assert_param(IS_CAN_FILTER_SCALE(config->scale)); + assert_param(IS_CAN_FILTER_FIFO(config->fifo)); + assert_param(IS_FUNC_STATE(config->active)); + + pos = 1 << config->number; + SET_BIT(hperh->perh->FLTCON, CAN_FLTCON_FLTINI_MSK); + CLEAR_BIT(hperh->perh->FLTGO, pos); + + if (config->scale == CAN_FILTER_SCALE_16) { + CLEAR_BIT(hperh->perh->FLTWS, pos); + hperh->perh->Filter[config->number].FLT1 = + ((0xFFFF & config->mask_id_low) << 16) | + (0xFFFF & config->id_low); + + hperh->perh->Filter[config->number].FLT2 = + ((0xFFFF & config->mask_id_high) << 16) | + (0xFFFF & config->id_high); + } + + if (config->scale == CAN_FILTER_SCALE_32) { + SET_BIT(hperh->perh->FLTWS, pos); + hperh->perh->Filter[config->number].FLT1 = + ((0xFFFF & config->id_high) << 16) | + (0xFFFF & config->id_low); + hperh->perh->Filter[config->number].FLT2 = + ((0xFFFF & config->mask_id_high) << 16) | + (0xFFFF & config->mask_id_low); + } + + MODIFY_REG(hperh->perh->FLTM, pos, config->mode << config->number); + MODIFY_REG(hperh->perh->FLTAS, pos, config->fifo << config->number); + MODIFY_REG(hperh->perh->FLTGO, pos, config->active << config->number); + CLEAR_BIT(hperh->perh->FLTCON, CAN_FLTCON_FLTINI_MSK); + + return OK; +} + +/** + * @brief Reset the CAN peripheral. + * @param hperh: pointer to a can_handle_t structure. + * @retval None + */ +void ald_can_reset(can_handle_t *hperh) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + + hperh->state = CAN_STATE_RESET; + __UNLOCK(hperh); + + return; +} + +/** + * @} + */ + +/** @defgroup CAN_Public_Functions_Group2 IO operation functions + * @brief I/O operation functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Send a CAN frame message. + (+) Send a CAN frame message using interrupt. + (+) Receive a CAN frame message. + (+) Receive a CAN frame message using interrupt. + + *@endverbatim + * @{ + */ + +/** + * @brief Send a CAN frame message. + * @param hperh: pointer to a can_handle_t structure. + * @param msg: message which will be sent. + * @param timeout: specify Timeout value + * @retval Status, see ald_status_t. + */ +ald_status_t ald_can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout) +{ + uint32_t tick; + can_tx_mailbox_t idx; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_IDTYPE(msg->type)); + assert_param(IS_CAN_RTR(msg->rtr)); + assert_param(IS_CAN_DATA_LEN(msg->len)); + + __LOCK(hperh); + SET_BIT(hperh->state, CAN_STATE_TX_MASK); + + if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) + idx = CAN_TX_MAILBOX_0; + else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) + idx = CAN_TX_MAILBOX_1; + else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) + idx = CAN_TX_MAILBOX_2; + else + idx = CAN_TX_MAILBOX_NONE; + + if (idx == CAN_TX_MAILBOX_NONE) { + hperh->state = CAN_STATE_ERROR; + __UNLOCK(hperh); + return ERROR; + } + + CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_IDE_MSK, msg->type << CAN_TXID0_IDE_POS); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_RTR_MSK, msg->rtr << CAN_TXID0_RTR_POS); + + if (msg->type == CAN_ID_STD) { + assert_param(IS_CAN_STDID(msg->std)); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, msg->std << CAN_TXID0_STDID_POSS); + CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK); + } + else { + assert_param(IS_CAN_EXTID(msg->ext)); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, ((msg->ext >> 18) & 0x7FF) << CAN_TXID0_STDID_POSS); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK, (msg->ext & 0x3FFFF) << CAN_TXID0_EXID_POSS); + } + MODIFY_REG(hperh->perh->TxMailBox[idx].TXFCON, CAN_TXFCON0_DLEN_MSK, (msg->len & 0xF) << CAN_TXFCON0_DLEN_POSS); + WRITE_REG(hperh->perh->TxMailBox[idx].TXDL, msg->data[0] | (msg->data[1] << 8) | (msg->data[2] << 16) | (msg->data[3] << 24)); + WRITE_REG(hperh->perh->TxMailBox[idx].TXDH, msg->data[4] | (msg->data[5] << 8) | (msg->data[6] << 16) | (msg->data[7] << 24)); + SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); + tick = ald_get_tick(); + + while (!(ald_can_get_tx_status(hperh, idx))) { + if ((timeout == 0) || ((ald_get_tick() - tick) > timeout)) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + + CLEAR_BIT(hperh->state, CAN_STATE_TX_MASK); + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Send a CAN frame message using interrupt. + * @param hperh: pointer to a can_handle_t structure. + * @param msg: message which will be sent. + * @retval Status, see ald_status_t. + */ +ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg) +{ + uint8_t idx = CAN_TX_MAILBOX_NONE; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_IDTYPE(msg->type)); + assert_param(IS_CAN_RTR(msg->rtr)); + assert_param(IS_CAN_DATA_LEN(msg->len)); + + if ((hperh->state & CAN_STATE_TX_MASK) || ((hperh->state & 0xF) != CAN_STATE_READY)) + return BUSY; + + if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) + idx = CAN_TX_MAILBOX_0; + else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) + idx = CAN_TX_MAILBOX_1; + else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) + idx = CAN_TX_MAILBOX_2; + else + idx = CAN_TX_MAILBOX_NONE; + + if (idx == CAN_TX_MAILBOX_NONE) + return BUSY; + + CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_IDE_MSK, msg->type << CAN_TXID0_IDE_POS); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_RTR_MSK, msg->rtr << CAN_TXID0_RTR_POS); + + if (msg->type == CAN_ID_STD) { + assert_param(IS_CAN_STDID(msg->std)); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, msg->std << CAN_TXID0_STDID_POSS); + CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK); + } + else { + assert_param(IS_CAN_EXTID(msg->ext)); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, ((msg->ext >> 18) & 0x7FF) << CAN_TXID0_STDID_POSS); + MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK, (msg->ext & 0x3FFFF) << CAN_TXID0_EXID_POSS); + } + + MODIFY_REG(hperh->perh->TxMailBox[idx].TXFCON, CAN_TXFCON0_DLEN_MSK, (msg->len & 0xF) << CAN_TXFCON0_DLEN_POSS); + WRITE_REG(hperh->perh->TxMailBox[idx].TXDL, msg->data[0] | (msg->data[1] << 8) | (msg->data[2] << 16) | (msg->data[3] << 24)); + WRITE_REG(hperh->perh->TxMailBox[idx].TXDH, msg->data[4] | (msg->data[5] << 8) | (msg->data[6] << 16) | (msg->data[7] << 24)); + + SET_BIT(hperh->state, CAN_STATE_TX_MASK); + + ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_TXM, ENABLE); + + SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK); + return OK; +} + +/** + * @brief Receives a correct CAN frame. + * @param hperh: pointer to a can_handle_t structure. + * @param num: Receive fifo number, CAN_RX_FIFO0 or CAN_RX_FIFO1 + * @param msg: Storing message. + * @param timeout: Specify timeout value + * @retval Status, see ald_status_t. + */ +ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout) +{ + uint32_t tick, stid, exid; + + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_FIFO(num)); + assert_param(msg != NULL); + + __LOCK(hperh); + SET_BIT(hperh->state, num == CAN_RX_FIFO0 ? CAN_STATE_RX0_MASK : CAN_STATE_RX1_MASK); + tick = ald_get_tick(); + + while (CAN_RX_MSG_PENDING(hperh, num) == 0) { + if ((timeout == 0) || ((ald_get_tick() - tick) > timeout)) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + + if (__can_rx_check(hperh, num)) + return ERROR; + + stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS); + exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS); + msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS); + + if (msg->type == CAN_ID_STD) + msg->std = stid; + else + msg->ext = (stid << 18) | exid; + + msg->rtr = (can_remote_req_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_RTR_MSK, CAN_RXF0ID_RTR_POS); + msg->len = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_DLEN_MSK, CAN_RXF0INF_DLEN_POSS); + msg->fmi = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_FLTIDX_MSK, CAN_RXF0INF_FLTIDX_POSS); + msg->data[0] = hperh->perh->RxFIFO[num].RXFDL & 0xFF; + msg->data[1] = (hperh->perh->RxFIFO[num].RXFDL >> 8) & 0xFF; + msg->data[2] = (hperh->perh->RxFIFO[num].RXFDL >> 16) & 0xFF; + msg->data[3] = (hperh->perh->RxFIFO[num].RXFDL >> 24) & 0xFF; + msg->data[4] = hperh->perh->RxFIFO[num].RXFDH & 0xFF; + msg->data[5] = (hperh->perh->RxFIFO[num].RXFDH >> 8) & 0xFF; + msg->data[6] = (hperh->perh->RxFIFO[num].RXFDH >> 16) & 0xFF; + msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF; + + can_rx_fifo_release(hperh, num); + CLEAR_BIT(hperh->state, num == CAN_RX_FIFO0 ? CAN_STATE_RX0_MASK : CAN_STATE_RX1_MASK); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receives a correct CAN frame using interrupt. + * @param hperh: pointer to a can_handle_t structure. + * @param num: Specify the FIFO number + * @param msg: Storing message. + * @retval Status, see ald_status_t. + */ +ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_FIFO(num)); + assert_param(msg != NULL); + + if (num == CAN_RX_FIFO0) { + if ((hperh->state & CAN_STATE_RX0_MASK) || ((hperh->state & 0xF) != CAN_STATE_READY)) + return BUSY; + + SET_BIT(hperh->state, CAN_STATE_RX0_MASK); + hperh->rx0_msg = msg; + } + else { + if ((hperh->state & CAN_STATE_RX1_MASK) || ((hperh->state & 0xF) != CAN_STATE_READY)) + return BUSY; + + SET_BIT(hperh->state, CAN_STATE_RX1_MASK); + hperh->rx1_msg = msg; + } + + ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, ENABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, ENABLE); + + if (num == CAN_RX_FIFO0) + ald_can_interrupt_config(hperh, CAN_IT_FP0, ENABLE); + else + ald_can_interrupt_config(hperh, CAN_IT_FP1, ENABLE); + + return OK; +} +/** + * @} + */ + +/** @defgroup CAN_Public_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure CAN sleep. + (+) Configure CAN wakeup. + (+) CAN cancel send message. + (+) Handle CAN interrupt. + (+) Get CAN transmit status. + (+) Configure CAN interrupt ENABLE/DISABLE. + (+) Get CAN interrupt source status. + (+) Get CAN interrupt flag status. + (+) Clear CAN interrupt flag. + + * @endverbatim + * @{ + */ + +/** + * @brief Enters the Sleep(low power) mode. + * @param hperh: pointer to a can_handle_t. + * @retval Status, see ald_status_t. + */ +ald_status_t ald_can_sleep(can_handle_t *hperh) +{ + uint32_t tick; + + assert_param(IS_CAN_ALL(hperh->perh)); + + __LOCK(hperh); + hperh->state = CAN_STATE_BUSY; + + CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK); + SET_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); + tick = ald_get_tick(); + + while ((!(READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK))) || READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) { + if ((ald_get_tick() - tick) > CAN_TIMEOUT_VALUE) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + + hperh->state = CAN_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral + * is in the normal mode. + * @param hperh: pointer to a can_handle_t structure. + * @retval Status, see ald_status_t. + */ +ald_status_t ald_can_wake_up(can_handle_t *hperh) +{ + uint32_t tick; + + assert_param(IS_CAN_ALL(hperh->perh)); + + __LOCK(hperh); + hperh->state = CAN_STATE_BUSY; + + CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK); + tick = ald_get_tick(); + + while (READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK)) { + if ((ald_get_tick() - tick) > CAN_TIMEOUT_VALUE) { + hperh->state = CAN_STATE_TIMEOUT; + __UNLOCK(hperh); + return TIMEOUT; + } + } + + hperh->state = CAN_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Handles CAN interrupt request + * @param hperh: pointer to a can_handle_t structure. + * @retval None + */ +void ald_can_irq_handler(can_handle_t* hperh) +{ + if (ald_can_get_it_status(hperh, CAN_IT_TXM)) { + if ((ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_0)) + || (ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_1)) + || (ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_2))) + __can_send_by_it(hperh, 0); + if (hperh->perh->TXSTAT & CAN_TXSTAT_M0TXERR_MSK) { + SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M0REQC_MSK); + __can_send_by_it(hperh, 1); + } + if (hperh->perh->TXSTAT & CAN_TXSTAT_M1TXERR_MSK) { + SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M1REQC_MSK); + __can_send_by_it(hperh, 1); + } + if (hperh->perh->TXSTAT & CAN_TXSTAT_M2TXERR_MSK) { + SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M2REQC_MSK); + __can_send_by_it(hperh, 1); + } + } + + if ((ald_can_get_it_status(hperh, CAN_IT_FP0)) + && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO0) != 0)) + __can_recv_by_it(hperh, CAN_RX_FIFO0); + + if ((ald_can_get_it_status(hperh, CAN_IT_FP1)) + && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO1) != 0)) + __can_recv_by_it(hperh, CAN_RX_FIFO1); + + if ((ald_can_get_flag_status(hperh, CAN_FLAG_WARN)) + && (ald_can_get_it_status(hperh, CAN_IT_WARN)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) + hperh->err |= CAN_ERROR_EWG; + + if ((ald_can_get_flag_status(hperh, CAN_FLAG_PERR)) + && (ald_can_get_it_status(hperh, CAN_IT_PERR)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) + hperh->err |= CAN_ERROR_EPV; + + if ((ald_can_get_flag_status(hperh, CAN_FLAG_BOF)) + && (ald_can_get_it_status(hperh, CAN_IT_BOF)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) + hperh->err |= CAN_ERROR_BOF; + + if (READ_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK) + && (ald_can_get_it_status(hperh, CAN_IT_PRERR)) + && (ald_can_get_it_status(hperh, CAN_IT_ERR))) { + + switch (READ_BITS(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK, CAN_ERRSTAT_PRERRF_POSS)) { + case(1): + hperh->err |= CAN_ERROR_STF; + break; + case(2): + hperh->err |= CAN_ERROR_FOR; + break; + case(3): + hperh->err |= CAN_ERROR_ACK; + break; + case(4): + hperh->err |= CAN_ERROR_BR; + break; + case(5): + hperh->err |= CAN_ERROR_BD; + break; + case(6): + hperh->err |= CAN_ERROR_CRC; + break; + default: + break; + } + + CLEAR_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK); + + if (READ_BIT(hperh->perh->IE, CAN_IE_TXMEIE_MSK)) + ald_can_interrupt_config(hperh, CAN_IT_TXM, DISABLE); + + if (READ_BIT(hperh->perh->IE, CAN_IE_F0PIE_MSK)) + ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE); + + if (READ_BIT(hperh->perh->IE, CAN_IE_F1PIE_MSK)) + ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE); + } + + if ((ald_can_get_flag_status(hperh, CAN_FLAG_ERR)) && (hperh->err == CAN_ERROR_NONE)) + hperh->err = CAN_ERROR_UNK; + + if (hperh->err != CAN_ERROR_NONE) { + SET_BIT(hperh->perh->IFC, CAN_IFC_ERRIFC_MSK); + hperh->state = CAN_STATE_READY; + + if (hperh->error_cbk != NULL) + hperh->error_cbk(hperh); + } +} + +/** + * @brief Check the transmission status of a CAN Frame. + * @param hperh: pointer to a can_handle_t structure. + * @param box: the index of the mailbox that is used for transmission. + * @retval The new status of transmission(TRUE or FALSE). + */ +type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_TX_MAILBOX(box)); + + switch (box) { + case CAN_TX_MAILBOX_0: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0REQC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0TXC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK)) + return FALSE; + + return TRUE; + + case CAN_TX_MAILBOX_1: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1REQC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1TXC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK)) + return FALSE; + + return TRUE; + + case CAN_TX_MAILBOX_2: + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2REQC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2TXC_MSK)) + return FALSE; + if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK)) + return FALSE; + + return TRUE; + + default: + break; + } + + return FALSE; +} + +/** + * @brief Cancel transmission. + * @param hperh: pointer to a can_handle_t structure. + * @param box: the index of the mailbox that is used for transmission. + * @retval None + */ +void ald_can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_TX_MAILBOX(box)); + + switch (box) { + case CAN_TX_MAILBOX_0: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0STPREQ_MSK); + break; + case CAN_TX_MAILBOX_1: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1STPREQ_MSK); + break; + case CAN_TX_MAILBOX_2: + SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2STPREQ_MSK); + break; + default: + break; + } + + return; +} + +/** + * @brief Enable/disable the specified CAN interrupts. + * @param hperh: Pointer to a can_handle_t structure. + * @param it: Specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref can_it_t. + * @param state: New state of the specified CAN interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->IE, it); + else + CLEAR_BIT(hperh->perh->IE, it); + + return; +} + +/** + * @brief Get the status of CAN interrupt source. + * @param hperh: Pointer to a can_handle_t structure. + * @param it: Specifies the CAN interrupt source. + * This parameter can be one of the @ref can_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it) +{ + assert_param(IS_CAN_ALL(hperh->perh)); + assert_param(IS_CAN_IT(it)); + + if (READ_BIT(hperh->perh->IE, it)) + return SET; + + return RESET; +} + +/** + * @brief Get the status of CAN interrupt flag. + * @param hperh: Pointer to a can_handle_t structure. + * @param flag: Specifies the CAN interrupt flag. + * This parameter can be one of the @ref can_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag) +{ + uint32_t idx = (flag >> 20) & 0x7; + uint32_t _flag = flag & 0xFF8FFFFF; + + assert_param(IS_CAN_GET_FLAG(flag)); + + switch (idx) { + case 0: + if (READ_BIT(hperh->perh->STAT, _flag)) + return SET; + + break; + case 1: + if (READ_BIT(hperh->perh->TXSTAT, _flag)) + return SET; + + break; + case 2: + if (READ_BIT(hperh->perh->RXF0, _flag)) + return SET; + + break; + case 3: + if (READ_BIT(hperh->perh->RXF1, _flag)) + return SET; + + break; + case 4: + if (READ_BIT(hperh->perh->ERRSTAT, _flag)) + return SET; + + break; + default: + break; + } + + return RESET; +} + +/** @brief Clear the specified CAN pending flag. + * @param hperh: pointer to a can_handle_t structure. + * @param flag: specifies the flag to check. + * @retval None. + */ +void ald_can_clear_flag_status(can_handle_t *hperh, can_flag_t flag) +{ + uint32_t idx = ((uint32_t)flag >> 20) & 0x7; + uint32_t _flag = flag & 0xFF8FFFFFU; + + assert_param(IS_CAN_CLEAR_FLAG(flag)); + + switch (idx) { + case 0: + WRITE_REG(hperh->perh->IFC, _flag); + break; + case 1: + WRITE_REG(hperh->perh->TXSTATC, _flag); + break; + case 2: + WRITE_REG(hperh->perh->RXF0C, _flag); + break; + case 3: + WRITE_REG(hperh->perh->RXF1C, _flag); + break; + default: + break; + } + + return; +} +/** + * @} + */ + +/** @defgroup CAN_Public_Functions_Group4 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * + * @verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to: + (+) Check the CAN state. + (+) Check CAN Errors detected during interrupt process + + * @endverbatim + * @{ + */ +/** + * @brief return the CAN state + * @param hperh: pointer to a can_handle_t structure. + * @retval Status, see can_state_t. + */ +can_state_t ald_can_get_state(can_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the CAN error code + * @param hperh: pointer to a can_handle_t structure. + * @retval CAN Error Code + */ +can_error_t ald_can_get_error(can_handle_t *hperh) +{ + return hperh->err; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Functions CAN Private Functions + * @{ + */ + +/** + * @brief Release rx FIFO + * @param hperh: pointer to a can_handle_t structure. + * @param num: Receive fifo number, CAN_RX_FIFO0 or CAN_RX_FIFO1 + * @retval None + */ +static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num) +{ + if (num == CAN_RX_FIFO0) + SET_BIT(hperh->perh->RXF0, CAN_RXF0_FREE_MSK); + else + SET_BIT(hperh->perh->RXF1, CAN_RXF1_FREE_MSK); +} + + +/** + * @brief transmits a CAN frame message using interrupt. + * @param hperh: pointer to a can_handle_t structure. + * @param err: Error code, 0 - success, 1 - error. + * @retval Status, see ald_status_t. + */ +static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err) +{ + ald_can_interrupt_config(hperh, CAN_IT_TXM, DISABLE); + + if (hperh->state == CAN_STATE_BUSY_TX) { + ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); + } + + CLEAR_BIT(hperh->state, CAN_STATE_TX_MASK); + + if ((err == 0) && (hperh->tx_cplt_cbk)) + hperh->tx_cplt_cbk(hperh); + + if ((err) && (hperh->error_cbk != NULL)) { + hperh->err = CAN_ERROR_UNK; + hperh->error_cbk(hperh); + } + + return OK; +} + +/** + * @brief Check whether the data in the mailbox is contaminated. + * @param hperh: Pointer to a can_handle_t structure. + * @param num: Specify the FIFO number + * @retval status: + * - 0: Data is valid + * - 1: Data is invalid + */ +static int __can_rx_check(can_handle_t *hperh, can_rx_fifo_t num) +{ + int i; + + if (!(hperh->perh->RESERVED0[0] & 0x200000U)) + return 0; + + if (num == CAN_RX_FIFO0) { + for (i = 0; i < 3; ++i) { + if (hperh->perh->RXF0 & 0x3) + SET_BIT(hperh->perh->RXF0, CAN_RXF0_FREE_MSK); + else + break; + } + } + else { + for (i = 0; i < 3; ++i) { + if (hperh->perh->RXF1 & 0x3) + SET_BIT(hperh->perh->RXF1, CAN_RXF1_FREE_MSK); + else + break; + } + } + + hperh->perh->RESERVED0[0] |= 0x200000U; + return 1; +} + +/** + * @brief Receives a correct CAN frame using interrupt. + * @param hperh: Pointer to a can_handle_t structure. + * @param num: Specify the FIFO number + * @retval Status, see ald_status_t. + */ +static ald_status_t __can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num) +{ + uint32_t stid, exid; + can_rx_msg_t *_msg; + + if (__can_rx_check(hperh, num)) + return ERROR; + + stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS); + exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS); + + _msg = num == CAN_RX_FIFO0 ? hperh->rx0_msg : hperh->rx1_msg; + _msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS); + + if (_msg->type == CAN_ID_STD) + _msg->std = stid; + else + _msg->ext = (stid << 18) | exid; + + _msg->rtr = (can_remote_req_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_RTR_MSK, CAN_RXF0ID_RTR_POS); + _msg->len = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_DLEN_MSK, CAN_RXF0INF_DLEN_POSS); + _msg->fmi = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_FLTIDX_MSK, CAN_RXF0INF_FLTIDX_POSS); + _msg->data[0] = hperh->perh->RxFIFO[num].RXFDL & 0xFF; + _msg->data[1] = (hperh->perh->RxFIFO[num].RXFDL >> 8) & 0xFF; + _msg->data[2] = (hperh->perh->RxFIFO[num].RXFDL >> 16) & 0xFF; + _msg->data[3] = (hperh->perh->RxFIFO[num].RXFDL >> 24) & 0xFF; + _msg->data[4] = hperh->perh->RxFIFO[num].RXFDH & 0xFF; + _msg->data[5] = (hperh->perh->RxFIFO[num].RXFDH >> 8) & 0xFF; + _msg->data[6] = (hperh->perh->RxFIFO[num].RXFDH >> 16) & 0xFF; + _msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF; + + if (num == CAN_RX_FIFO0) { + can_rx_fifo_release(hperh, CAN_RX_FIFO0); + ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE); + CLEAR_BIT(hperh->state, CAN_STATE_RX0_MASK); + } + else { + can_rx_fifo_release(hperh, CAN_RX_FIFO1); + ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE); + CLEAR_BIT(hperh->state, CAN_STATE_RX1_MASK); + } + + if (hperh->state == CAN_STATE_READY) { + ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_PRERR, DISABLE); + ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE); + } + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh, num); + + return OK; +} +/** + * @} + */ + +#endif /* ALD_CAN */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_cmu.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_cmu.c new file mode 100644 index 00000000..07c3fe61 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_cmu.c @@ -0,0 +1,1180 @@ +/** + ********************************************************************************* + * + * @file ald_cmu.c + * @brief CMU module driver. + * + * @version V1.0 + * @date 22 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 22 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + *** System clock configure *** + ================================= + [..] + (+) If you don't change system clock, you can using ald_cmu_clock_config_default() API. + It will select HRC as system clock. The system clock is 24MHz. + (+) If you want to change system clock, you can using ald_cmu_clock_config() API. + You can select one of the following as system clock: + @ref CMU_CLOCK_HRC 2MHz or 24MHz + @ref CMU_CLOCK_LRC 32768Hz + @ref CMU_CLOCK_LOSC 32768Hz + @ref CMU_CLOCK_PLL1 36MHz/48MHz/72MHz/96MHz + @ref CMU_CLOCK_HOSC 1MHz -- 24MHz + (+) If you select CMU_CLOCK_PLL1 as system clock, it must config the PLL1 + using ald_cmu_pll1_config() API. The input of clock must be 4MHz. + (+) If you get current clock, you can using ald_cmu_get_clock() API. + + *** BUS division control *** + =================================== + + MCLK sys_clk + -------DIV_SYS-----------+--------------------------System(Core, DMA, Systick ... etc.) + | + | hclk1 + +------DIV_AHB1------------Peripheral(GPIO, CRC, ... etc.) + | + | hclk2 + +------DIV_AHB2------------Peripheral(EBI, QSPI, ... etc.) + | + | pclk1 + +------DIV_APB1------------Peripheral(TIM, UART, ... etc.) + | + | pclk2 + +------DIV_APB2------------Peripheral(ADC, WWDT, ... etc.) + + [..] + (+) Configure the division using ald_cmu_div_config() API. + (+) Get sys_clk using ald_cmu_get_sys_clock() API. + (+) Get hclk1 using ald_cmu_get_hclk1_clock() API. + (+) Get pclk1 using ald_cmu_get_pclk1_clock() API. + (+) Get pclk2 using ald_cmu_get_pclk2_clock() API. + + *** Clock safe configure *** + =================================== + [..] + (+) If you select CMU_CLOCK_HOSC as system clock, you need enable + clock safe using ald_cmu_hosc_safe_config() API. It will change + CMU_CLOCK_HRC as system clock, when the outer crystal stoped. + (+) If you select CMU_CLOCK_LOSC as system clock, you need enable + clock safe using ald_cmu_losc_safe_config() API. It will change + CMU_CLOCK_LRC as system clock, when the outer crystal stoped. + (+) If you select CMU_CLOCK_PLL1 as system clock, you need enable + clock safe using ald_cmu_pll_safe_config() API. It will change + CMU_CLOCK_HRC as system clock, when the pll1 is lose. + (+) The ald_cmu_irq_cbk() will be invoked, when CMU interrupt has + been occurred. You can overwrite this function in application. + + *** Clock output configure *** + =================================== + [..] + (+) Output high-speed clock using ald_cmu_output_high_clock_config() API. + (+) Output low-speed clock using ald_cmu_output_low_clock_config() API. + + *** Peripheral clock configure *** + =================================== + [..] + (+) Configure buzz clock using ald_cmu_buzz_config() API. + (+) Selected lptim0 clock using ald_cmu_lptim0_clock_select() API. + (+) Selected lpuart clock using ald_cmu_lpuart0_clock_select() API. + (+) Selected lcd clock using ald_cmu_lcd_clock_select() API. + (+) Selected qspi clock using ald_cmu_qspi_clock_select() API. + (+) Configure usb clock using ald_cmu_usb_clock_config() API. + (+) Enable/Disable peripheral clock using ald_cmu_perh_clock_config() API. + (+) Selected stop1 clock using ald_cmu_stop1_clock_sel() API. + + *** CMU ALD driver macros list *** + ============================================= + [..] + Below the list of most used macros in CMU driver. + + (+) CMU_HRC_SEL_BY_SW(): HRC clock config by software. + (+) CMU_HRC_SEL_BY_CFGW(): HRC clock config by CFG Word. + (+) CMU_HRC_DIV_1MHZ_ENABLE(): Enable HRC divider to 1MHz. + (+) CMU_HRC_DIV_1MHZ_DISABLE(): Disable HRC divider to 1MHz. + (+) CMU_HOSC_DIV_1MHZ_ENABLE(): Enable HOSC divider to 1MHz. + (+) CMU_HOSC_DIV_1MHZ_DISABLE(): Disable HOSC divider to 1MHz. + (+) CMU_LOSC_ENABLE(): Enable outer low crystal(32768Hz). + (+) CMU_LOSC_DISABLE(): Disable outer low crystal(32768Hz). + (+) CMU_LRC_ENABLE(): Enable LRC(32768Hz). + (+) CMU_LRC_DISABLE(): Disable LRC(32768Hz). + (+) CMU_ULRC_ENABLE(): Enable ULRC(10KHz). + (+) CMU_ULRC_DISABLE(): Disable ULRC(10KHz). + (+) CMU_LP_LRC_ENABLE(): Enable low power LRC(32768Hz). + (+) CMU_LP_LRC_DISABLE(): Disable low power LRC(32768Hz). + (+) CMU_LP_LOSC_ENABLE(): Enable low power LOSC(32768Hz). + (+) CMU_LP_LOSC_DISABLE(): Disable low power LOSC(32768Hz). + (+) CMU_LP_HRC_ENABLE(): Enable low power HRC(2MHz or 24MHz). + (+) CMU_LP_HRC_DISABLE(): Disable low power HRC(2MHz OR 24MHz). + (+) CMU_LP_HOSC_ENABLE(): Enable low power HOSC(1MHz -- 24MHz). + (+) CMU_LP_HOSC_DISABLE(): Disable low power HOSC(1MHz -- 24MHz). + + [..] + (@) You can refer to the CMU driver header file for used the macros + + @endverbatim + ****************************************************************************** + */ + +#include "ald_conf.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup CMU CMU + * @brief CMU module driver + * @{ + */ + +/** + * @defgroup CMU_Private_Variables CMU Private Variables + * @{ + */ +uint32_t __system_clock = 24000000U; +/** + * @} + */ + +/** @defgroup CMU_Private_Functions CMU Private Functions + * @{ + */ + +/** + * @brief Update the current system clock. This function + * will be invoked, when system clock has changed. + * @param clock: The new clock. + * @retval None + */ + +static void cmu_clock_update(uint32_t clock) +{ + __system_clock = clock; + + if (clock > 1000000) + ald_tick_init(TICK_INT_PRIORITY); + + return; +} + +/** + * @brief CMU module interrupt handler + * @retval None + */ +void ald_cmu_irq_handler(void) +{ + /* HOSC stop */ + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); + SYSCFG_LOCK(); + + if ((READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) + || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) + cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); + ald_cmu_irq_cbk(CMU_HOSC_STOP); + } + + /* HOSC start */ + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK); + SYSCFG_LOCK(); + + if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK)) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))) + cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 1000000); + ald_cmu_irq_cbk(CMU_HOSC_START); + } + + /* LOSC stop */ + if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); + SYSCFG_LOCK(); + ald_cmu_irq_cbk(CMU_LOSC_STOP); + } + + /* LOSC start */ + if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK); + SYSCFG_LOCK(); + ald_cmu_irq_cbk(CMU_LOSC_START); + } + + /* PLL1 lose */ + if (READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK) && READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK)) { + SYSCFG_UNLOCK(); + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); + SYSCFG_LOCK(); + + if (READ_BIT(CMU->PULMCR, CMU_PULMCR_CLKS_MSK) + && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1) + || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))) + cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000); + ald_cmu_irq_cbk(CMU_PLL1_UNLOCK); + } + + return; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions CMU Public Functions + * @{ + */ + +/** @defgroup CMU_Public_Functions_Group1 System clock configuration + * @brief System clock configuration functions + * + * @verbatim + ============================================================================== + ##### System clock Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure system clock using default parameters. + (+) Configure system clock using specified parameters. + (+) Configure PLL1 using specified parameters. + (+) Get system clock. + + @endverbatim + * @{ + */ + +/** + * @brief Configure system clock using default. + * Select CMU_CLOCK_HRC(24MHz) as system clock and + * enable CMU_CLOCK_LRC(32768Hz). + * @retval The status of ALD. + */ +ald_status_t ald_cmu_clock_config_default(void) +{ + uint32_t cnt = 4000, tmp; + + SYSCFG_UNLOCK(); + + /* Select HRC */ + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); + + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) { + SYSCFG_LOCK(); + return ERROR; + } + + WRITE_REG(CMU->CFGR, 0x4000000); /* Select 24MHz */ + + tmp = READ_REG(CMU->CLKENR); + /* Enable HRC/LRC */ + SET_BIT(tmp, CMU_CLKENR_HRCEN_MSK | CMU_CLKENR_LRCEN_MSK); + WRITE_REG(CMU->CLKENR, tmp); + /* Reset LRC */ + for (cnt = 0; cnt < 10000; ++cnt); + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); + + SYSCFG_LOCK(); + return OK; +} + +/** + * @brief Configure system clock using specified parameters + * @param clk: The parameter can be one of the following: + * @arg @ref CMU_CLOCK_HRC 2MHz or 24MHz + * @arg @ref CMU_CLOCK_LRC 32768Hz + * @arg @ref CMU_CLOCK_LOSC 32768Hz + * @arg @ref CMU_CLOCK_PLL1 One of @ref cmu_pll1_output_t + * @arg @ref CMU_CLOCK_HOSC 1MHz -- 24MHz + * @param clock: The clock which will be set. the value depends + * on the parameter of clk. + * @retval The status of ALD. + */ +ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock) +{ + uint32_t cnt = 4000; + + assert_param(IS_CMU_CLOCK(clk)); + SYSCFG_UNLOCK(); + + switch (clk) { + case CMU_CLOCK_HRC: + assert_param(clock == 24000000 || clock == 2000000); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) { + SYSCFG_LOCK(); + return ERROR; + } + + if (clock == 24000000) + CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); + else + SET_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK); + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); + + for (cnt = 4000; cnt; --cnt); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCRDY_MSK))) && (--cnt)); + + cmu_clock_update(clock); + break; + + case CMU_CLOCK_LRC: + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC) { + SYSCFG_LOCK(); + return ERROR; + } + + SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); + + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt)); + + cmu_clock_update(32768); + break; + + case CMU_CLOCK_LOSC: + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LOSC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC) { + SYSCFG_LOCK(); + return ERROR; + } + + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); + + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCRDY_MSK))) && (--cnt)); + + cmu_clock_update(32768); + break; + + case CMU_CLOCK_PLL1: + for (cnt = 0; cnt < 5000; ++cnt); + MODIFY_REG(CMU->CSR, CMU_CSR_CFT_CMD_MSK, 0xAA << CMU_CSR_CFT_CMD_POSS); + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1) { + SYSCFG_LOCK(); + return ERROR; + } + + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); + + for (cnt = 0; cnt < 5000; ++cnt); + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1ACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); + + if (clock == 96000000) { + ald_cmu_div_config(CMU_HCLK_1, CMU_DIV_2); + ald_cmu_div_config(CMU_HCLK_2, CMU_DIV_2); + ald_cmu_div_config(CMU_PCLK_1, CMU_DIV_2); + ald_cmu_div_config(CMU_PCLK_2, CMU_DIV_4); + for (cnt = 0; cnt < 20000; ++cnt); + } + if (clock == 72000000) { + ald_cmu_div_config(CMU_PCLK_2, CMU_DIV_4); + } + if ((clock == 48000000) || (clock == 36000000)) { + ald_cmu_div_config(CMU_PCLK_2, CMU_DIV_2); + } + + cmu_clock_update(clock); + break; + + case CMU_CLOCK_HOSC: + assert_param(clock <= 24000000); + + MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS); + while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt)); + + if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC) { + SYSCFG_LOCK(); + return ERROR; + } + + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1); + + for (cnt = 8000; cnt; --cnt); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); + + cmu_clock_update(clock); + break; + + default: + break; + } + + SYSCFG_LOCK(); + return OK; +} + + + +/** + * @brief Configure PLL1 using specified parameters. + * @param input: The input clock type. + * @param output: The output clock which can be 36MHz/48MHz/72MHz/96MHz. + * When input = CMU_PLL1_INPUT_PLL2; then output must be + * CMU_PLL1_OUTPUT_36M, and then the real clock is (32768x1024)Hz. + * @retval None + */ +void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output) +{ + uint32_t cnt = 4000; + + assert_param(IS_CMU_PLL1_INPUT(input)); + assert_param(IS_CMU_PLL1_OUTPUT(output)); + + SYSCFG_UNLOCK(); + + if (input == CMU_PLL1_INPUT_HRC_6) { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK); + } + else if (input == CMU_PLL1_INPUT_PLL2) { + SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); + CLEAR_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2RFS_MSK); + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + } + else { + SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK); + for (cnt = 0; cnt < 10000; ++cnt); + cnt = 20000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt)); + } + + MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1RFS_MSK, input << CMU_PLLCFG_PLL1RFS_POSS); + MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1OS_MSK, output << CMU_PLLCFG_PLL1OS_POSS); + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK); + + for (cnt = 0; cnt < 4000; ++cnt); + while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL1LCKN_MSK)) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt)); + + SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 0x3 << CMU_PULMCR_MODE_POSS); + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Gets current system clock. + * @retval The value of system clock. + */ +uint32_t ald_cmu_get_clock(void) +{ + return __system_clock; +} + +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group2 BUS division control + * @brief BUS division control functions + * + * @verbatim + ============================================================================== + ##### BUS division control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure the bus division. + (+) Get ahb1 clock. + (+) Get sys bus clock. + (+) Get apb1 clock. + (+) Get apb2 clock. + + @endverbatim + * @{ + */ + +/** + * @brief Configure the bus division. + * @param bus: The type of bus: + * @arg CMU_HCLK_1 + * @arg CMU_SYS + * @arg CMU_PCLK_1 + * @arg CMU_PCLK_2 + * @param div: The value of divider. + * @retval None + */ +void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div) +{ + assert_param(IS_CMU_BUS(bus)); + assert_param(IS_CMU_DIV(div)); + + SYSCFG_UNLOCK(); + + switch (bus) { + case CMU_HCLK_1: + MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS); + break; + + case CMU_HCLK_2: + MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK2DIV_MSK, div << CMU_CFGR_HCLK2DIV_POSS); + break; + + case CMU_SYS: + MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); + + if ((__system_clock >> div) <= 1000000) { + /* Close SysTick interrupt in lower clock */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + } + else { + ald_tick_init(TICK_INT_PRIORITY); + } + + break; + + case CMU_PCLK_1: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS); + break; + + case CMU_PCLK_2: + MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, div << CMU_CFGR_PCLK2DIV_POSS); + break; + + default: + break; + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Get AHB1 clock. + * @retval The value of AHB1 clock. + */ +uint32_t ald_cmu_get_hclk1_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, CMU_CFGR_HCLK1DIV_POSS); + + return (__system_clock >> sys_div) >> ahb_div; +} + +/** + * @brief Get AHB2 clock. + * @retval The value of AHB2 clock. + */ +uint32_t ald_cmu_get_hclk2_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK2DIV_MSK, CMU_CFGR_HCLK2DIV_POSS); + + return (__system_clock >> sys_div) >> ahb_div; +} + +/** + * @brief Get SYS clock + * @retval The value of SYS clock + */ +uint32_t ald_cmu_get_sys_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + + return __system_clock >> sys_div; +} + +/** + * @brief Get APB1 clock. + * @retval The value of APB1 clock. + */ +uint32_t ald_cmu_get_pclk1_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t apb1_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, CMU_CFGR_PCLK1DIV_POSS); + + return (__system_clock >> sys_div) >> apb1_div; +} + +/** + * @brief Get APB2 clock. + * @retval The value of APB2 clock. + */ +uint32_t ald_cmu_get_pclk2_clock(void) +{ + uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS); + uint32_t apb2_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, CMU_CFGR_PCLK2DIV_POSS); + + return (__system_clock >> sys_div) >> apb2_div; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group3 Clock safe configure + * @brief Clock safe configure functions + * + * @verbatim + ============================================================================== + ##### Clock safe configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable outer high crystal safe mode. + (+) Enable/Disable outer low crystal safe mode. + (+) Enable/Disable PLL1 safe mode. + (+) Interrupt callback function. + + @endverbatim + * @{ + */ + +/** + * @brief Enable/Disable outer high crystal safe mode. + * @param clock: the value of outer crystal frequency. + * @param status: The new status. + * @retval None + */ +void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status) +{ + assert_param(IS_CMU_HOSC_RANGE(clock)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) { + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK); + MODIFY_REG(CMU->HOSMCR, CMU_HOSMCR_FRQS_MSK, clock << CMU_HOSMCR_FRQS_POSS); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); + SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); + + ald_mcu_irq_config(CMU_IRQn, 3, 3, ENABLE); + } + else { + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK); + CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK); + + if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) + ald_mcu_irq_config(CMU_IRQn, 3, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Enable/Disable outer low crystal safe mode. + * @param status: The new status. + * @retval None + */ +void ald_cmu_losc_safe_config(type_func_t status) +{ + assert_param(IS_FUNC_STATE(status)); + SYSCFG_UNLOCK(); + + if (status) { + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); + SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); + + ald_mcu_irq_config(CMU_IRQn, 3, 3, ENABLE); + } + else { + CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK); + CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK); + + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0) + ald_mcu_irq_config(CMU_IRQn, 3, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Enable/Disable PLL1 safe mode. + * @param status: The new status. + * @retval None + */ +void ald_cmu_pll_safe_config(type_func_t status) +{ + assert_param(IS_FUNC_STATE(status)); + SYSCFG_UNLOCK(); + + if (status) { + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK); + MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS); + SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); + + ald_mcu_irq_config(CMU_IRQn, 3, 3, ENABLE); + } + else { + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK); + CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK); + + if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0) + ald_mcu_irq_config(CMU_IRQn, 3, 3, DISABLE); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Get current clock source. + * @param type: Type of source: HOSC/LOSC/PLL. + * @retval Status: + * - 0: Current clock is HOSC, LOSC or PLL + * - 1: Current clock is HRC, LRC or HRC + */ +uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type) +{ + assert_param(IS_CMU_SAFE_CLOCK_TYPE(type)); + + if (type == CMU_SAFE_CLK_HOSC) + return READ_BITS(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK, CMU_HOSMCR_CLKS_POS); + else if (type == CMU_SAFE_CLK_LOSC) + return READ_BITS(CMU->LOSMCR, CMU_LOSMCR_CLKS_MSK, CMU_LOSMCR_CLKS_POS); + else + return READ_BITS(CMU->PULMCR, CMU_PULMCR_CLKS_MSK, CMU_PULMCR_CLKS_POS); +} + +/** + * @brief Get clock state. + * @param sr: The state type, see @ref cmu_clock_state_t. + * @retval SET/RESET + */ +flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr) +{ + assert_param(IS_CMU_CLOCK_STATE(sr)); + + if (READ_BIT(CMU->CLKSR, sr)) + return SET; + + return RESET; +} + +/** + * @brief Interrupt callback function. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void ald_cmu_irq_cbk(cmu_security_t se) +{ + return; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group4 Clock output configure + * @brief Clock output configure functions + * + * @verbatim + ============================================================================== + ##### Clock output configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure the high-speed clock output. + (+) Configure the low-speed clock output. + + @endverbatim + * @{ + */ + +/** + * @brief Configure the high-speed clock output. + * @param sel: Select the source: + * @arg CMU_OUTPUT_HIGH_SEL_HOSC + * @arg CMU_OUTPUT_HIGH_SEL_LOSC + * @arg CMU_OUTPUT_HIGH_SEL_HRC + * @arg CMU_OUTPUT_HIGH_SEL_LRC + * @arg CMU_OUTPUT_HIGH_SEL_HOSM + * @arg CMU_OUTPUT_HIGH_SEL_PLL1 + * @arg CMU_OUTPUT_HIGH_SEL_PLL2 + * @arg CMU_OUTPUT_HIGH_SEL_SYSCLK + * @param div: The value of divider: + * @arg CMU_OUTPUT_DIV_1 + * @arg CMU_OUTPUT_DIV_2 + * @arg CMU_OUTPUT_DIV_4 + * @arg CMU_OUTPUT_DIV_8 + * @arg CMU_OUTPUT_DIV_16 + * @arg CMU_OUTPUT_DIV_32 + * @arg CMU_OUTPUT_DIV_64 + * @arg CMU_OUTPUT_DIV_128 + * @param status: The new status. + * @retval None + */ +void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, + cmu_output_high_div_t div, type_func_t status) +{ + assert_param(IS_CMU_OUTPUT_HIGH_SEL(sel)); + assert_param(IS_CMU_OUTPUT_HIGH_DIV(div)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) { + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCOS_MSK, sel << CMU_CLKOCR_HSCOS_POSS); + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCODIV_MSK, div << CMU_CLKOCR_HSCODIV_POSS); + SET_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); + } + else { + CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Configure the low-speed clock output. + * @param sel: Select the source: + * @arg CMU_OUTPUT_LOW_SEL_LOSC + * @arg CMU_OUTPUT_LOW_SEL_LRC + * @arg CMU_OUTPUT_LOW_SEL_LOSM + * @arg CMU_OUTPUT_LOW_SEL_BUZZ + * @arg CMU_OUTPUT_LOW_SEL_ULRC + * @param status: The new status. + * @retval None + */ +void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status) +{ + assert_param(IS_CMU_OUTPUT_LOW_SEL(sel)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) { + MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_LSCOS_MSK, sel << CMU_CLKOCR_LSCOS_POSS); + SET_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); + } + else { + CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK); + } + + SYSCFG_LOCK(); + return; +} +/** + * @} + */ + +/** @defgroup CMU_Public_Functions_Group5 Peripheral Clock configure + * @brief Peripheral clock configure functions + * + * @verbatim + ============================================================================== + ##### Peripheral clock configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure buzz clock. + (+) Select lptim0 clock source. + (+) Select lpuart0 clock source. + (+) Select lcd clock source. + (+) Enable/Disable peripheral clock. + + @endverbatim + * @{ + */ + +/** + * @brief Configure buzz clock. + * freq = sysclk / (2^(div + 1) * (dat + 1)) + * @param div: The value of divider. + * @param dat: The value of coefficient. + * @param status: The new status. + * @retval None + */ +void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status) +{ + assert_param(IS_CMU_BUZZ_DIV(div)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (status) { + MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS); + MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, dat << CMU_BUZZCR_DAT_POSS); + SET_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); + } + else { + CLEAR_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Select lptim0 clock source. + * @param clock: The clock source: + * @arg CMU_LP_PERH_CLOCK_SEL_PCLK2 + * @arg CMU_LP_PERH_CLOCK_SEL_PLL1 + * @arg CMU_LP_PERH_CLOCK_SEL_PLL2 + * @arg CMU_LP_PERH_CLOCK_SEL_HRC + * @arg CMU_LP_PERH_CLOCK_SEL_HOSC + * @arg CMU_LP_PERH_CLOCK_SEL_LRC + * @arg CMU_LP_PERH_CLOCK_SEL_LOSC + * @arg CMU_LP_PERH_CLOCK_SEL_ULRC + * @arg CMU_LP_PERH_CLOCK_SEL_HRC_1M + * @arg CMU_LP_PERH_CLOCK_SEL_HOSC_1M + * @arg CMU_LP_PERH_CLOCK_SEL_LOSM + * @arg CMU_LP_PERH_CLOCK_SEL_HOSM + * @retval None + */ +void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock) +{ + assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); + + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_LPTIM0_MSK, clock << CMU_PERICR_LPTIM0_POSS); + SYSCFG_LOCK(); + + return; +} + +/** + * @brief Select lpuart0 clock source. + * @param clock: The clock source: + * @arg CMU_LP_PERH_CLOCK_SEL_PCLK2 + * @arg CMU_LP_PERH_CLOCK_SEL_PLL1 + * @arg CMU_LP_PERH_CLOCK_SEL_PLL2 + * @arg CMU_LP_PERH_CLOCK_SEL_HRC + * @arg CMU_LP_PERH_CLOCK_SEL_HOSC + * @arg CMU_LP_PERH_CLOCK_SEL_LRC + * @arg CMU_LP_PERH_CLOCK_SEL_LOSC + * @arg CMU_LP_PERH_CLOCK_SEL_ULRC + * @arg CMU_LP_PERH_CLOCK_SEL_HRC_1M + * @arg CMU_LP_PERH_CLOCK_SEL_HOSC_1M + * @arg CMU_LP_PERH_CLOCK_SEL_LOSM + * @arg CMU_LP_PERH_CLOCK_SEL_HOSM + * @retval None + */ +void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock) +{ + assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock)); + + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_LPUART0_MSK, clock << CMU_PERICR_LPUART0_POSS); + SYSCFG_LOCK(); + + return; +} + +/** + * @brief Select lcd clock source. + * @param clock: The clock source: + * @arg CMU_LCD_SEL_LOSM + * @arg CMU_LCD_SEL_LOSC + * @arg CMU_LCD_SEL_LRC + * @arg CMU_LCD_SEL_ULRC + * @arg CMU_LCD_SEL_HRC_1M + * @arg CMU_LCD_SEL_HOSC_1M + * @retval None + */ +void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock) +{ + assert_param(IS_CMU_LCD_CLOCK_SEL(clock)); + + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_LCD_MSK, clock << CMU_PERICR_LCD_POSS); + SYSCFG_LOCK(); + + return; +} + +/** + * @brief Select QSPI clock source. + * @param clock: The clock source, see @ref cmu_qspi_clock_sel_t. + * @retval None + */ +void ald_cmu_qspi_clock_select(cmu_qspi_clock_sel_t clock) +{ + assert_param(IS_CMU_QSPI_CLOCK_SEL(clock)); + + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->PERICR, CMU_PERICR_QSPICS_MSK, clock << CMU_PERICR_QSPICS_POSS); + SYSCFG_LOCK(); + + return; +} + +/** + * @brief Configure USB clock source. + * @param clock: The clock source, see @ref cmu_usb_clock_sel_t. + * @param div: The clock division, see @ref cmu_usb_div_t. + * @retval None + */ +void ald_cmu_usb_clock_config(cmu_usb_clock_sel_t clock, cmu_usb_div_t div) +{ + assert_param(IS_CMU_USB_CLOCK_SEL(clock)); + assert_param(IS_CMU_USB_DIV(div)); + + SYSCFG_UNLOCK(); + + if (clock == CMU_USB_CLOCK_SEL_HRC) + SET_BIT(SYSCFG->USBCFG, SYSCFG_USBCFG_CLKRDYBP_MSK); + else + CLEAR_BIT(SYSCFG->USBCFG, SYSCFG_USBCFG_CLKRDYBP_MSK); + + MODIFY_REG(CMU->PERICR, CMU_PERICR_USBPHYCS_MSK, clock << CMU_PERICR_USBPHYCS_POSS); + MODIFY_REG(CMU->PERIDIVR, CMU_PERIDIVR_USBPHYDIV_MSK, div << CMU_PERIDIVR_USBPHYDIV_POSS); + SYSCFG_LOCK(); + + return; +} + +/** + * @brief Enable/Disable peripheral clock. + * @param perh: The type of peripheral, you can see @ref cmu_perh_t + * @param status: The new status. + * @retval None + */ +void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status) +{ + uint32_t idx, pos; + + assert_param(IS_CMU_PERH(perh)); + assert_param(IS_FUNC_STATE(status)); + + SYSCFG_UNLOCK(); + + if (perh == CMU_PERH_ALL) { + if (status) { + WRITE_REG(CMU->AHB1ENR, ~0); + WRITE_REG(CMU->APB1ENR, ~0); + WRITE_REG(CMU->APB2ENR, ~0); + } + else { + WRITE_REG(CMU->AHB1ENR, 0); + WRITE_REG(CMU->APB1ENR, 0); + WRITE_REG(CMU->APB2ENR, 0); + } + + SYSCFG_LOCK(); + return; + } + + idx = (uint32_t)(perh >> 27) & 0x3; + pos = perh & ~(0x3 << 27); + + if (status) { + switch (idx) { + case 0: + SET_BIT(CMU->AHB1ENR, pos); + break; + + case 1: + SET_BIT(CMU->APB1ENR, pos); + break; + + case 2: + SET_BIT(CMU->APB2ENR, pos); + break; + + default: + break; + } + } + else { + switch (idx) { + case 0: + CLEAR_BIT(CMU->AHB1ENR, pos); + break; + + case 1: + CLEAR_BIT(CMU->APB1ENR, pos); + break; + + case 2: + CLEAR_BIT(CMU->APB2ENR, pos); + break; + + default: + break; + } + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Select stop1 clock. + * @param clock: See @ref cmu_stop1_clock_t + * @retval None + */ +void ald_cmu_stop1_clock_sel(cmu_stop1_clock_t clock) +{ + assert_param(IS_CMU_STOP1_CLOCK(clock)); + + SYSCFG_UNLOCK(); + MODIFY_REG(CMU->LPENR, CMU_LPENR_STOP1CS_MSK, clock << CMU_LPENR_STOP1CS_POSS); + SYSCFG_LOCK(); + return; +} +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_crc.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_crc.c new file mode 100644 index 00000000..2ebdecb5 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_crc.c @@ -0,0 +1,535 @@ +/** + ********************************************************************************* + * + * @file ald_crc.c + * @brief CRC module driver. + * + * @version V1.0 + * @date 18 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 18 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_conf.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC module driver + * @{ + */ +#ifdef ALD_CRC + +/** @addtogroup CRC_Private_Functions CRC Private Functions + * @{ + */ +void ald_crc_reset(crc_handle_t *hperh); +#ifdef ALD_DMA +static void crc_dma_calculate_cplt(void *arg); +static void crc_dma_error(void *arg); +#endif +/** + * @} + */ + + +/** @defgroup CRC_Public_Functions CRC Public Functions + * @{ + */ + +/** @defgroup CRC_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Initializes the CRC mode according to the specified parameters in + * the crc_handle_t and create the associated handle. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_init(crc_handle_t *hperh) +{ + uint32_t tmp = 0; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_CRC(hperh->perh)); + assert_param(IS_CRC_MODE(hperh->init.mode)); + assert_param(IS_FUNC_STATE(hperh->init.chs_rev)); + assert_param(IS_FUNC_STATE(hperh->init.data_inv)); + assert_param(IS_FUNC_STATE(hperh->init.data_rev)); + assert_param(IS_FUNC_STATE(hperh->init.chs_inv)); + + ald_crc_reset(hperh); + __LOCK(hperh); + + CRC_ENABLE(hperh); + + tmp = hperh->perh->CR; + + tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATINV_POS) | + (hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) | + (CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) | + (0 << CRC_CR_BYTORD_POS)); + + hperh->perh->CR = tmp; + hperh->perh->SEED = hperh->init.seed; + CRC_RESET(hperh); + + hperh->state = CRC_STATE_READY; + + __UNLOCK(hperh); + return OK; +} + +/** + * @} + */ + +/** @defgroup CRC_Public_Functions_Group2 Calculate functions + * @brief Calculate functions + * @{ + */ + +/** + * @brief Calculate the crc value of data by byte. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate + * @retval result, the result of a amount data + */ +uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); + hperh->state = CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + *((volatile uint8_t *)&(hperh->perh->DATA)) = buf[i]; + + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} + +/** + * @brief Calculate the crc value of data by halfword. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate,width is 2 bytes. + * @retval result, the result of a amount data + */ +uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); + hperh->state = CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + *((volatile uint16_t *)&(hperh->perh->DATA)) = buf[i]; + + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} + +/** + * @brief Calculate the crc value of data by word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param size: The size of data to be calculate,width is 4 bytes + * @retval result, the result of a amount data + */ +uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size) +{ + uint32_t i; + uint32_t ret; + + assert_param(IS_CRC(hperh->perh)); + + if (buf == NULL || size == 0) + return 0; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); + hperh->state = CRC_STATE_BUSY; + + for (i = 0; i < size; i++) + CRC->DATA = buf[i]; + + for (i = 0; i < 3; i++); + + ret = CRC->CHECKSUM; + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); + + return ret; +} + +/** + * @} + */ + +#ifdef ALD_DMA +/** @defgroup CRC_Public_Functions_Group3 DMA operation functions + * @brief DMA operation functions + * @{ + */ + +/** + * @brief Calculate an amount of data used dma channel + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to data buffer + * @param res: Pointer to result + * @param size: Amount of data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != CRC_STATE_READY) + return BUSY; + + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS); + + hperh->state = CRC_STATE_BUSY; + + hperh->cal_buf = buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; + + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; + + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + hperh->hdma.config.burst = ENABLE; + ald_dma_config_basic(&(hperh->hdma)); + + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); + + return OK; +} + +/** + * @brief Calculate an amount of data used dma channel,data width is half-word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to half_word data buffer + * @param res: Pointer to result + * @param size: Amount of half_word data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != CRC_STATE_READY) + return BUSY; + + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS); + + hperh->state = CRC_STATE_BUSY; + + hperh->cal_buf = (uint8_t *)buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; + + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; + + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + hperh->hdma.config.burst = ENABLE; + ald_dma_config_basic(&(hperh->hdma)); + + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); + + return OK; +} + +/** + * @brief Calculate an amount of data used dma channel,data width is word. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @param buf: Pointer to word data buffer + * @param res: Pointer to result + * @param size: Amount of word data to be Calculate + * @param channel: DMA channel as CRC transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel) +{ + if (hperh->state != CRC_STATE_READY) + return BUSY; + + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS); + + hperh->state = CRC_STATE_BUSY; + + hperh->cal_buf = (uint8_t *)buf; + hperh->cal_res = res; + + if (hperh->hdma.perh == NULL) + hperh->hdma.perh = DMA0; + + hperh->hdma.cplt_arg = (void *)hperh; + hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt; + hperh->hdma.err_arg = (void *)hperh; + hperh->hdma.err_cbk = &crc_dma_error; + + ald_dma_config_struct(&(hperh->hdma.config)); + hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)&hperh->perh->DATA; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_CRC; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = channel; + hperh->hdma.config.burst = ENABLE; + ald_dma_config_basic(&(hperh->hdma)); + + __UNLOCK(hperh); + CRC_DMA_ENABLE(hperh); + + return OK; +} + + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_dma_pause(crc_handle_t *hperh) +{ + __LOCK(hperh); + CRC_DMA_DISABLE(hperh); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_dma_resume(crc_handle_t *hperh) +{ + __LOCK(hperh); + CRC_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crc_dma_stop(crc_handle_t *hperh) +{ + __LOCK(hperh); + CRC_DMA_DISABLE(hperh); + __UNLOCK(hperh); + + hperh->state = CRC_STATE_READY; + return OK; +} + +/** + * @} + */ +#endif + +/** @defgroup CRC_Public_Functions_Group4 Peripheral State and Errors functions + * @brief CRC State and Errors functions + * @{ + */ + +/** + * @brief Returns the CRC state. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval CRC state + */ +crc_state_t ald_crc_get_state(crc_handle_t *hperh) +{ + assert_param(IS_CRC(hperh->perh)); + + return hperh->state; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Functions CRC Private Functions + * @brief CRC Private functions + * @{ + */ + +/** + * @brief Reset the CRC peripheral. + * @param hperh: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval None + */ +void ald_crc_reset(crc_handle_t *hperh) +{ + hperh->perh->DATA = 0x0; + hperh->perh->CR = 0x2; + hperh->perh->SEED = 0xFFFFFFFF; + + hperh->state = CRC_STATE_READY; + __UNLOCK(hperh); + return; +} + +#ifdef ALD_DMA +/** + * @brief DMA CRC calculate process complete callback. + * @param arg: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval None + */ +static void crc_dma_calculate_cplt(void *arg) +{ + crc_handle_t *hperh = (crc_handle_t *)arg; + + *(hperh->cal_res) = CRC->CHECKSUM; + CRC_DMA_DISABLE(hperh); + + hperh->state = CRC_STATE_READY; + + if (hperh->cal_cplt_cbk) + hperh->cal_cplt_cbk(hperh); +} + +/** + * @brief DMA CRC communication error callback. + * @param arg: Pointer to a crc_handle_t structure that contains + * the configuration information for the specified CRC module. + * @retval None + */ +static void crc_dma_error(void *arg) +{ + crc_handle_t *hperh = (crc_handle_t *)arg; + + CRC_CLEAR_ERROR_FLAG(hperh); + CRC_DMA_DISABLE(hperh); + + hperh->state = CRC_STATE_READY; + + if (hperh->err_cplt_cbk) + hperh->err_cplt_cbk(hperh); +} +#endif +/** + * @} + */ +#endif /* ALD_CRC */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_crypt.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_crypt.c new file mode 100644 index 00000000..0365c189 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_crypt.c @@ -0,0 +1,1165 @@ +/** + ********************************************************************************* + * + * @file ald_crypt.c + * @brief CRYPT module driver. + * This is the common part of the CRYPT initialization + * + * @version V1.0 + * @date 19 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 19 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + + +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup CRYPT CRYPT + * @brief CRYPT module driver + * @{ + */ +#ifdef ALD_CRYPT + +/** @addtogroup CRYPT_Private_Functions CRYPT Private Functions + * @{ + */ +void crypt_reset(crypt_handle_t *hperh); +#ifdef ALD_DMA +static void crypt_dma_crypt_cplt(void *arg); +static void crypt_dma_error(void *arg); +#endif +/** + * @} + */ + + +/** @defgroup CRYPT_Public_Functions CRYPT Public Functions + * @{ + */ + +/** @defgroup CRYPT_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Initializes the CRYPT mode according to the specified parameters in + * the crypt_init_t and create the associated handle. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_init(crypt_handle_t *hperh) +{ + uint32_t tmp = 0; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_MODE(hperh->init.mode)); + assert_param(IS_CRYPT_KS(hperh->init.key)); + + if ((hperh->init.key == CRYPT_DES_KEYS_1 || hperh->init.key == CRYPT_DES_KEYS_2 || hperh->init.key == CRYPT_DES_KEYS_3) + && (hperh->init.mode == CRYPT_MODE_CTR)) { + return ERROR; + } + + __LOCK(hperh); + crypt_reset(hperh); + + if (hperh->state == CRYPT_STATE_RESET) + __UNLOCK(hperh); + + tmp = hperh->perh->CON; + switch (hperh->init.key) { + case CRYPT_AES_BITS_128: + tmp |= ((CRYPT_CRYSEL_AES << CRYPT_CON_CRYSEL_POS) | \ + (CRYPT_BITS_128 << CRYPT_CON_AESKS_POSS)); + hperh->step = 4; + break; + + case CRYPT_AES_BITS_192: + tmp |= ((CRYPT_CRYSEL_AES << CRYPT_CON_CRYSEL_POS) | \ + (CRYPT_BITS_192 << CRYPT_CON_AESKS_POSS)); + hperh->step = 4; + break; + + case CRYPT_AES_BITS_256: + tmp |= ((CRYPT_CRYSEL_AES << CRYPT_CON_CRYSEL_POS) | \ + (CRYPT_BITS_256 << CRYPT_CON_AESKS_POSS)); + hperh->step = 4; + break; + + case CRYPT_DES_KEYS_1: + SET_BIT(tmp, CRYPT_CON_CRYSEL_MSK); + hperh->step = 2; + break; + + case CRYPT_DES_KEYS_2: + SET_BIT(tmp, CRYPT_CON_CRYSEL_MSK); + tmp |= ((1 << CRYPT_CON_TDES_POS) | (CRYPT_KEYS_2 << CRYPT_CON_DESKS_POS)); + hperh->step = 2; + break; + + case CRYPT_DES_KEYS_3: + SET_BIT(tmp, CRYPT_CON_CRYSEL_MSK); + tmp |= ((1 << CRYPT_CON_TDES_POS) | (CRYPT_KEYS_3 << CRYPT_CON_DESKS_POS)); + hperh->step = 2; + break; + + default: + hperh->state = CRYPT_STATE_ERROR; + __UNLOCK(hperh); + return ERROR; + } + + tmp |= ((1 << CRYPT_CON_FIFOODR_POS) | (hperh->init.mode << CRYPT_CON_MODE_POSS) | \ + (hperh->init.type << CRYPT_CON_TYPE_POSS) | (1 << CRYPT_CON_FIFOEN_POS)); + hperh->perh->CON = tmp; + + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Write the Content of KEY. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param key: Pointer to key data buffer + * @param len: The length of key(32 bits) + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t * key, crypt_key_len_t len) +{ + uint32_t *temp = key; + uint32_t i; + + if ((hperh == NULL) || (key == NULL)) + return ERROR; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; + + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_KEY_LEN(len)); + + if ((hperh->init.key & 0xF) != len) + return ERROR; + + switch (len) { + case KEY_8_LEN: + hperh->perh->KEY[7] = *temp++; + hperh->perh->KEY[6] = *temp++; + hperh->perh->KEY[5] = *temp++; + hperh->perh->KEY[4] = *temp++; + hperh->perh->KEY[3] = *temp++; + hperh->perh->KEY[2] = *temp++; + hperh->perh->KEY[1] = *temp++; + hperh->perh->KEY[0] = *temp; + break; + + case KEY_6_LEN: + hperh->perh->KEY[5] = *temp++; + hperh->perh->KEY[4] = *temp++; + hperh->perh->KEY[3] = *temp++; + hperh->perh->KEY[2] = *temp++; + hperh->perh->KEY[1] = *temp++; + hperh->perh->KEY[0] = *temp; + break; + + case KEY_4_LEN: + hperh->perh->KEY[3] = *temp++; + hperh->perh->KEY[2] = *temp++; + hperh->perh->KEY[1] = *temp++; + hperh->perh->KEY[0] = *temp; + break; + + case KEY_2_LEN: + hperh->perh->KEY[1] = *temp++; + hperh->perh->KEY[0] = *temp; + break; + + default: + break; + } + + for (i = 0; i < len; i++) + hperh->key[i] = *key++; + + hperh->key_size = len; + + return OK; +} + +/** + * @brief Read the Content of KEY. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param key: Pointer to key data buffer + * @param len: The length of key(32 bits) + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t * key, crypt_key_len_t len) +{ + uint32_t *temp = key; + + if ((hperh == NULL) || (key == NULL)) + return ERROR; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; + + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_KEY_LEN(len)); + + switch (len) { + case KEY_8_LEN: + *temp++ = hperh->perh->KEY[7]; + *temp++ = hperh->perh->KEY[6]; + *temp++ = hperh->perh->KEY[5]; + *temp++ = hperh->perh->KEY[4]; + *temp++ = hperh->perh->KEY[3]; + *temp++ = hperh->perh->KEY[2]; + *temp++ = hperh->perh->KEY[1]; + *temp = hperh->perh->KEY[0]; + break; + + case KEY_6_LEN: + *temp++ = hperh->perh->KEY[5]; + *temp++ = hperh->perh->KEY[4]; + *temp++ = hperh->perh->KEY[3]; + *temp++ = hperh->perh->KEY[2]; + *temp++ = hperh->perh->KEY[1]; + *temp = hperh->perh->KEY[0]; + break; + + case KEY_4_LEN: + *temp++ = hperh->perh->KEY[3]; + *temp++ = hperh->perh->KEY[2]; + *temp++ = hperh->perh->KEY[1]; + *temp = hperh->perh->KEY[0]; + break; + + case KEY_2_LEN: + *temp++ = hperh->perh->KEY[1]; + *temp = hperh->perh->KEY[0]; + break; + + default: + break; + } + + return OK; +} + +/** + * @brief Write the Content of IV if you use CBC mode + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param iv: Pointer to iv data buffer + * @param len: the length of iv(32 bits) + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t * iv, crypt_ivr_len_t len) +{ + uint32_t *temp = iv; + uint32_t i; + + if ((hperh == NULL) || (iv == NULL)) + return ERROR; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; + + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_IV_LEN(len)); + + switch (len) { + case IV_4_LEN: + hperh->perh->IV[3] = *temp++; + hperh->perh->IV[2] = *temp++; + hperh->perh->IV[1] = *temp++; + hperh->perh->IV[0] = *temp; + break; + + case IV_2_LEN: + hperh->perh->IV[1] = *temp++; + hperh->perh->IV[0] = *temp; + break; + + default: + break; + } + + for (i = 0; i < len; i++) + hperh->iv[i] = *iv++; + + hperh->iv_size = len; + + CRYPT_IVEN_ENABLE(hperh); + return OK; +} + +/** + * @brief Read the Content of IV. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param iv: Pointer to iv data buffer + * @param len: the length of iv(32 bits) + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv, crypt_ivr_len_t len) +{ + uint32_t *temp = iv; + + if ((hperh == NULL) || (iv == NULL)) + return ERROR; + if (hperh->state == CRYPT_STATE_BUSY) + return BUSY; + + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_IV_LEN(len)); + + switch (len) { + case IV_4_LEN: + *temp++ = hperh->perh->IV[3]; + *temp++ = hperh->perh->IV[2]; + *temp++ = hperh->perh->IV[1]; + *temp = hperh->perh->IV[0]; + break; + + case IV_2_LEN: + *temp++ = hperh->perh->IV[1]; + *temp = hperh->perh->IV[0]; + break; + + default: + break; + } + + return OK; +} + +/** + * @} + */ + +/** @defgroup CRYPT_Public_Functions_Group2 Encrypt or Decrypt functions + * @brief Encrypt or Decrypt functions + * @{ + */ + +/** + * @brief Encrypt an amount of data in blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param plain_text: Pointer to plain data buffer + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of plain data + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 8(des) or 16(ase) + */ +ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t * plain_text, uint8_t * cipher_text, uint32_t size) +{ + uint32_t count = 0; + uint32_t i; + uint32_t *plain_buf = (uint32_t *)plain_text; + uint32_t *cipher_buf = (uint32_t *)cipher_text; + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); + count = size / (4 * hperh->step); + + while (count--) { + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *plain_buf); + plain_buf++; + } + + while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); + + for (i = 0; i < hperh->step; i++) + *cipher_buf++ = CRYPT_READ_FIFO(hperh); + } + + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Decrypt an amount of data in blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param cipher_text: Pointer to cipher data buffer + * @param plain_text: Pointer to plain data buffer + * @param size: Amount of cipher data + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 8(des) or 16(ase) + */ +ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) +{ + uint32_t count = 0; + uint32_t i; + uint32_t *plain_buf = (uint32_t*)plain_text; + uint32_t *cipher_buf = (uint32_t*)cipher_text; + + if (hperh->init.mode == CRYPT_MODE_CTR) { + return ald_crypt_encrypt(hperh, cipher_text, plain_text, size); + } + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_DECRYPT); + count = size / (4 * hperh->step); + + while (count--) { + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *cipher_buf); + cipher_buf++; + } + + while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET); + + for (i = 0; i < hperh->step; i++) + *plain_buf++ = CRYPT_READ_FIFO(hperh); + } + + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +void gcm_mul(uint32_t *res, uint32_t *data, uint32_t *iv) +{ + CRYPT->CON = 0; + CRYPT->DATA[0] = data[3]; + CRYPT->DATA[1] = data[2]; + CRYPT->DATA[2] = data[1]; + CRYPT->DATA[3] = data[0]; + CRYPT->IV[0] = iv[3]; + CRYPT->IV[1] = iv[2]; + CRYPT->IV[2] = iv[1]; + CRYPT->IV[3] = iv[0]; + CRYPT->CON |= ((1 << CRYPT_CON_RESCLR_POS) | (3 << CRYPT_CON_MODE_POSS) | \ + (1 << CRYPT_CON_GO_POS)); + + while (READ_BIT(CRYPT->IF, CRYPT_IF_MULTHIF_MSK) == 0); + + res[3] = CRYPT->RES[0]; + res[2] = CRYPT->RES[1]; + res[1] = CRYPT->RES[2]; + res[0] = CRYPT->RES[3]; + + SET_BIT(CRYPT->IFC, CRYPT_IFC_MULTHIFC_MSK); + return; +} + +/** + * @brief verify an amount of data in gcm mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of cipher data + * @param aadata: Pointer to additional authenticated data buffer + * @param alen: Amount of additional authenticated data + * @param tag: Pointer to authentication tag buffer + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag) +{ + uint8_t GCM_HASH_in[0x60] = {0} ; + uint8_t ecb[16] = {0} ; + uint32_t x_temp[4]; + uint64_t u, v; + uint32_t len = 0; + uint32_t j, i, k; + uint32_t *tag_temp, *cipher_text_temp; + + /* calculate u and v */ + u = 128 * ((size % 16) ? (size / 16 + 1) : size / 16) - size * 8; + v = 128 * ((alen % 16) ? (alen / 16 + 1): alen / 16) - alen * 8; + + /* get the input of GHASH algorithm,the input:A||0^v||C||0^u||[len(A)]_64||[len(C)]_64 */ + for (i = 0; i < alen; i++) { + GCM_HASH_in [i] = * (aadata + i); + } + len += alen; + for (i = 0; i < v / 8; i++) { + GCM_HASH_in[i + len] = 0; + } + len += v / 8; + for (i = 0; i < size; i++) { + GCM_HASH_in[i + len] = * (cipher_text + i); + } + len += size; + for (i = 0; i < u / 8; i++) { + GCM_HASH_in[i + len] = 0; + } + len += u / 8; + + for (i = 0; i < 4; i++) { + GCM_HASH_in[i + len] = 0; + } + len += 4; + + for (i = 0; i < 4; i++) { + GCM_HASH_in[i + len] = ((alen * 8) >> (8 * i)) & 0xFF; + } + len += 4; + + for (i = 0; i < 4; i++) { + GCM_HASH_in[i + len] = 0; + } + len += 4; + + for (i = 0; i < 4; i++) { + GCM_HASH_in[i + len] = ((size * 8) >> (8 * i)) & 0xFF; + } + len += 4; + + CRYPT->CON &= ~(3U << CRYPT_CON_MODE_POSS); + CRYPT->CON |= (CRYPT_MODE_ECB << CRYPT_CON_MODE_POSS); + + ald_crypt_encrypt(hperh, ecb, ecb, 16); + + k = len / 16; + for (i = 0; i < 16; i++) { + tag[i] = 0; + } + + cipher_text_temp = (uint32_t *)GCM_HASH_in; + tag_temp = (uint32_t *)tag; + for (i = 0; i < k; i++) { + for (j = 0; j < 4; j++) { + x_temp[j] = (*cipher_text_temp) ^ tag_temp[j]; + ++cipher_text_temp; + } + + gcm_mul((uint32_t *)tag_temp, x_temp, (uint32_t *)ecb); + } + + /* calculate the authentication tag T, + * T = CIPH_K(J0)^S,J0=IV||0^31||1,CIPH_K is the algorithm of AES in ECB mode + */ + tag_temp = (uint32_t *)tag; + ald_crypt_init(hperh); + CRYPT->CON &= ~(3U << CRYPT_CON_MODE_POSS); + CRYPT->CON |= (CRYPT_MODE_CTR << CRYPT_CON_MODE_POSS); + ald_crypt_write_key(hperh, hperh->key, KEY_4_LEN); + hperh->iv[3] = 1; + ald_crypt_write_ivr(hperh, hperh->iv, IV_4_LEN); + ald_crypt_encrypt(hperh, tag, tag, 16); + + return OK; +} + +/** + * @brief Encrypt an amount of data in non-blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param plain_text: Pointer to plain data buffer + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of plain data + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 8(des) or 16(ase) + */ +ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t * plain_text, uint8_t *cipher_text, uint32_t size) +{ + uint32_t i; + uint32_t *plain_buf = (uint32_t *)plain_text; + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); + hperh->count = hperh->step; + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); + + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *plain_buf); + ++plain_buf; + } + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Decrypt an amount of data in non-blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param plain_text: Pointer to plain data buffer + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of cipher data + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 8(des) or 16(ase) + */ +ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size) +{ + uint32_t i; + uint32_t *cipher_buf = (uint32_t*)cipher_text; + + if (hperh->init.mode == CRYPT_MODE_CTR) { + return ald_crypt_decrypt_by_it(hperh, cipher_text, plain_text, size); + } + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0)) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + CRYPT_SETDIR(hperh, CRYPT_DECRYPT); + hperh->count = hperh->step; + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE); + + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *cipher_buf); + cipher_buf ++; + } + + __UNLOCK(hperh); + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Encrypt an amount of data in non-blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param plain_text: Pointer to plain data buffer + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of plain data + * @param channel_m2p: Memory to Crypt module DMA channel + * @param channel_p2m: Crypt module to Memory DMA channel + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 8(des) or 16(ase) + */ +ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t * plain_text, + uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) +{ + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + + if (plain_text == NULL || cipher_text == NULL || size == 0) + return ERROR; + + assert_param(IS_CRYPT(hperh->perh)); + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + hperh->count = size; + + if (hperh->hdma_m2p.perh == NULL) + hperh->hdma_m2p.perh = DMA0; + if (hperh->hdma_p2m.perh == NULL) + hperh->hdma_p2m.perh = DMA0; + + hperh->hdma_m2p.cplt_arg = NULL; + hperh->hdma_m2p.cplt_cbk = NULL; + hperh->hdma_m2p.err_arg = NULL; + hperh->hdma_m2p.err_cbk = NULL; + + hperh->hdma_p2m.cplt_arg = (void *)hperh; + hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt; + hperh->hdma_p2m.err_arg = (void *)hperh; + hperh->hdma_p2m.err_cbk = &crypt_dma_error; + + CRYPT_SETDIR(hperh, CRYPT_ENCRYPT); + + ald_dma_config_struct(&hperh->hdma_m2p.config); + hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_m2p.config.src = (void *)hperh->plain_text; + hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; + hperh->hdma_m2p.config.size = size / 4; + hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; + hperh->hdma_m2p.config.burst = ENABLE; + hperh->hdma_m2p.config.channel = channel_m2p; + ald_dma_config_basic(&(hperh->hdma_m2p)); + + ald_dma_config_struct(&hperh->hdma_p2m.config); + hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; + hperh->hdma_p2m.config.dst = (void *)hperh->cipher_text; + hperh->hdma_p2m.config.size = size / 4; + hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD; + hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; + hperh->hdma_p2m.config.burst = ENABLE; + hperh->hdma_p2m.config.channel = channel_p2m; + ald_dma_config_basic(&(hperh->hdma_p2m)); + + CRYPT_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Decrypt an amount of data in non-blocking mode. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param plain_text: Pointer to plain data buffer + * @param cipher_text: Pointer to cipher data buffer + * @param size: Amount of cipher data + * @param channel_m2p: Memory to Crypt module DMA channel + * @param channel_p2m: Crypt module to Memory DMA channel + * @retval Status, see @ref ald_status_t. + * @note the size is multiple of 8(des) or 16(ase) + */ +ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t * cipher_text, + uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m) +{ + if (hperh->init.mode == CRYPT_MODE_CTR) + return ald_crypt_decrypt_by_dma(hperh, cipher_text, plain_text, size, channel_m2p, channel_p2m); + + if (hperh->state != CRYPT_STATE_READY) + return ERROR; + if (plain_text == NULL || cipher_text == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = CRYPT_STATE_BUSY; + + hperh->plain_text = plain_text; + hperh->cipher_text = cipher_text; + hperh->size = size; + hperh->count = size; + + if (hperh->hdma_m2p.perh == NULL) + hperh->hdma_m2p.perh = DMA0; + if (hperh->hdma_p2m.perh == NULL) + hperh->hdma_p2m.perh = DMA0; + + + hperh->hdma_m2p.cplt_arg = NULL; + hperh->hdma_m2p.cplt_cbk = NULL; + hperh->hdma_m2p.err_arg = NULL; + hperh->hdma_m2p.err_cbk = NULL; + + hperh->hdma_p2m.cplt_arg = (void *)hperh; + hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt; + hperh->hdma_p2m.err_arg = (void *)hperh; + hperh->hdma_p2m.err_cbk = &crypt_dma_error; + + CRYPT_SETDIR(hperh, CRYPT_DECRYPT); + + ald_dma_config_struct(&hperh->hdma_m2p.config); + hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_m2p.config.src = (void *)hperh->cipher_text; + hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO; + hperh->hdma_m2p.config.size = size / 4; + hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE; + hperh->hdma_m2p.config.burst = ENABLE; + hperh->hdma_m2p.config.channel = channel_m2p; + ald_dma_config_basic(&(hperh->hdma_m2p)); + + ald_dma_config_struct(&hperh->hdma_p2m.config); + hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO; + hperh->hdma_p2m.config.dst = (void *)hperh->plain_text; + hperh->hdma_p2m.config.size = size / 4; + hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD; + hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT; + hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ; + hperh->hdma_m2p.config.burst = ENABLE; + hperh->hdma_p2m.config.channel = channel_p2m; + ald_dma_config_basic(&(hperh->hdma_p2m)); + + CRYPT_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return OK; +} + +/** + * @} + */ + +/** @defgroup CRYPT_Public_Functions_Group3 DMA operation functions + * @brief DMA operation functions + * @{ + */ + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh) +{ + __LOCK(hperh); + CRYPT_DMA_DISABLE(hperh); + __UNLOCK(hperh); + + return OK; + +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh) +{ + __LOCK(hperh); + CRYPT_DMA_ENABLE(hperh); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh) +{ + __LOCK(hperh); + CRYPT_DMA_DISABLE(hperh); + __UNLOCK(hperh); + + hperh->state = CRYPT_STATE_READY; + return OK; +} +#endif + +/** + * @brief This function handles CRYPT interrupt request. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval None + */ +void ald_crypt_irq_handler(crypt_handle_t *hperh) +{ + uint32_t i; + uint32_t *in_buf = (uint32_t *)hperh->cipher_text; + uint32_t *out_buf = (uint32_t *)hperh->plain_text; + + if (READ_BIT(hperh->perh->CON, CRYPT_CON_ENCS_MSK) == (CRYPT_DECRYPT << CRYPT_CON_ENCS_POS)) { + in_buf = (uint32_t *)hperh->cipher_text + hperh->count; + out_buf = (uint32_t *)hperh->plain_text + hperh->count - hperh->step; + } + else { + in_buf = (uint32_t *)hperh->plain_text + hperh->count; + out_buf = (uint32_t *)hperh->cipher_text + hperh->count - hperh->step; + } + + if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET) { + ald_crypt_clear_flag_status(hperh, CRYPT_FLAG_AESIF); + } + + if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DESIF) == SET) { + ald_crypt_clear_flag_status(hperh, CRYPT_FLAG_DESIF); + } + + for (i = 0; i < hperh->step; i++) + *out_buf++ = CRYPT_READ_FIFO(hperh); + + hperh->count = hperh->count + hperh->step; + if (hperh->count > (hperh->size / 4)) { + hperh->count = 0; + hperh->state = CRYPT_STATE_READY; + hperh->crypt_cplt_cbk(hperh); + } + else { + for (i = 0; i < hperh->step; i++) { + CRYPT_WRITE_FIFO(hperh, *in_buf); + ++in_buf; + } + } +} +/** + * @} + */ + +/** @defgroup CRYPT_Public_Functions_Group4 Peripheral Control functions + * @brief CRYPT control functions + * @{ + */ + +/** + * @brief Enables or disables the specified CRYPT interrupts. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param it: Specifies the CRYPT interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg crypt_it_t: CRYPT interrupt + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state) +{ + assert_param(IS_CRYPT(hperh->perh)); + + if (it == CRYPT_IT_IT) { + CLEAR_BIT(CRYPT->CON, CRYPT_CON_IE_MSK); + CRYPT->CON |= (state << CRYPT_CON_IE_POS); + } + + return; +} + +/** @brief Check whether the specified CRYPT flag is set or not. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref crypt_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) +{ + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_FLAG(flag)); + + if (CRYPT->IF & flag) + return SET; + + return RESET; +} + +/** @brief Clear the specified CRYPT pending flags. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param flag: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg CRYPT_FLAG_AESIF: AES encrypt or decrypt Complete flag. + * @arg CRYPT_FLAG_DESIF: AES encrypt or decrypt Complete flag. + * @arg CRYPT_FLAG_DONE: encrypt or decrypt Complete flag. + * @retval None + */ +void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag) +{ + assert_param(IS_CRYPT(hperh->perh)); + assert_param(IS_CRYPT_FLAG(flag)); + + CRYPT->IFC = (uint32_t)flag; + return; +} + +/** + * @brief Checks whether the specified CRYPT interrupt has occurred or not. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @param it: Specifies the CRYPT interrupt source to check. + * This parameter can be one of the following values: + * @arg crypt_it_t: CRYPT interrupt + * @retval Status + * - SET + * - RESET + */ +it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it) +{ + assert_param(IS_CRYPT_IT(it)); + + if (READ_BIT(CRYPT->CON, CRYPT_CON_IE_MSK)) + return SET; + + return RESET; +} + + +/** + * @} + */ + +/** @defgroup CRYPT_Public_Functions_Group5 Peripheral State and Errors functions + * @brief State and Errors functions + * @{ + */ + +/** + * @brief Returns the CRYPT state. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval CRYPT state + */ +crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh) +{ + assert_param(IS_CRYPT(hperh->perh)); + + return hperh->state; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CRYPT_Private_Functions CRYPT Private Functions + * @brief CRYPT Private functions + * @{ + */ + +/** + * @brief Reset the CRYPT peripheral. + * @param hperh: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval None + */ +void crypt_reset(crypt_handle_t *hperh) +{ + hperh->perh->DATA[0] = 0x0; + hperh->perh->DATA[1] = 0x0; + hperh->perh->DATA[2] = 0x0; + hperh->perh->DATA[3] = 0x0; + hperh->perh->KEY[0] = 0x0; + hperh->perh->KEY[1] = 0x0; + hperh->perh->KEY[2] = 0x0; + hperh->perh->KEY[3] = 0x0; + hperh->perh->KEY[4] = 0x0; + hperh->perh->KEY[5] = 0x0; + hperh->perh->KEY[6] = 0x0; + hperh->perh->KEY[7] = 0x0; + hperh->perh->IV[0] = 0x0; + hperh->perh->IV[1] = 0x0; + hperh->perh->IV[2] = 0x0; + hperh->perh->IV[3] = 0x0; + hperh->perh->CON = 0x0; + + hperh->state = CRYPT_STATE_READY; + __UNLOCK(hperh); +} + +#ifdef ALD_DMA +/** + * @brief DMA CRYPT encrypt or decrypt process complete callback. + * @param arg: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval None + */ +static void crypt_dma_crypt_cplt(void *arg) +{ + crypt_handle_t *hperh = (crypt_handle_t *)arg; + + CRYPT_DMA_DISABLE(hperh); + hperh->count = 0; + hperh->plain_text = NULL; + hperh->cipher_text = NULL; + hperh->size = 0; + + hperh->state = CRYPT_STATE_READY; + + if (hperh->crypt_cplt_cbk) + hperh->crypt_cplt_cbk(hperh); +} + +/** + * @brief DMA CRYPT communication error callback. + * @param arg: Pointer to a crypt_handle_t structure that contains + * the configuration information for the specified CRYPT module. + * @retval None + */ +static void crypt_dma_error(void *arg) +{ + crypt_handle_t *hperh = (crypt_handle_t *)arg; + CRYPT_DMA_DISABLE(hperh); + + hperh->count = 0; + hperh->plain_text = NULL; + hperh->cipher_text = NULL; + hperh->size = 0; + + hperh->state = CRYPT_STATE_READY; + + if (hperh->err_cplt_cbk) + hperh->err_cplt_cbk(hperh); +} +#endif +/** + * @} + */ + +#endif /* ALD_CRYPT */ +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_dac.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_dac.c new file mode 100644 index 00000000..35a52658 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_dac.c @@ -0,0 +1,349 @@ +/** + ****************************************************************************** + * @file ald_dac.c + * @brief DAC module driver. + * + * @version V1.0 + * @date 28 Jun 2019 + * @author AE Team. + * @note + * Change Logs: + * Date Author Notes + * 28 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup DAC DAC + * @brief DAC module driver + * @{ + */ +#ifdef ALD_DAC + +/** @defgroup DAC_Public_Functions DAC Public Functions + * @{ + */ +/** + * @brief Reset the dac mode. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_dac_reset(dac_handle_t *hperh) +{ + assert_param(IS_DAC_TYPE(hperh->perh)); + + hperh->perh->CON = 0; + hperh->perh->CH0CTRL = 0; + hperh->perh->CH1CTRL = 0; + hperh->perh->IES = 0; + hperh->perh->IEC = 0xFF; + hperh->perh->IFC = 0xFF; + hperh->perh->CAL = 0; + + return OK; +} + +/** + * @brief Initializes the DAC peripheral. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_dac_init(dac_handle_t *hperh) +{ + uint32_t tmp; + + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_DAC_CONVERT_TYPE(hperh->init.conv_mode)); + assert_param(IS_DAC_OUTPUT_TYPE(hperh->init.out_mode)); + assert_param(IS_DAC_NEG_REFRESH_TYPE(hperh->init.n_ref)); + assert_param(IS_DAC_POS_REFRESH_TYPE(hperh->init.p_ref)); + assert_param(IS_DAC_REFRESH_TYPE(hperh->init.refresh)); + assert_param(IS_DAC_PRESCALE_TYPE(hperh->init.div)); + assert_param(IS_FUNC_STATE(hperh->init.ch0_reset)); + assert_param(IS_FUNC_STATE(hperh->init.o_ctrl_pis)); + assert_param(IS_FUNC_STATE(hperh->init.sine)); + assert_param(IS_FUNC_STATE(hperh->init.diff)); + + __LOCK(hperh); + ald_dac_reset(hperh); + DAC_CH0_DISABLE(); + DAC_CH1_DISABLE(); + + MODIFY_REG(ADC0->CCR, ADC_CCR_VREFEN_MSK, 1 << ADC_CCR_VREFEN_POS); + + if (hperh->init.p_ref == DAC_POS_REF_VREEFP_BUF || hperh->init.p_ref == DAC_POS_REF_2V) + SET_BIT(ADC0->CCR, (ADC_CCR_IREFEN_MSK | ADC_CCR_VRBUFEN_MSK | ADC_CCR_VCMBUFEN_MSK)); + + MODIFY_REG(ADC0->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS); + MODIFY_REG(ADC0->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS); + + tmp = ((hperh->init.refresh << DAC_CON_RCYCLSEL_POSS) | (hperh->init.div << DAC_CON_PRES_POSS) | + (hperh->init.ch0_reset << DAC_CON_CH0PRESRST_POS) | ( hperh->init.o_ctrl_pis << DAC_CON_OUTENPIS_POS) | + (hperh->init.out_mode << DAC_CON_OUTMD_POSS) | (hperh->init.conv_mode << DAC_CON_CONVMD_POSS) | + (hperh->init.sine << DAC_CON_SINEMD_POS) | (hperh->init.diff << DAC_CON_DIFEN_POS)); + hperh->perh->CON = tmp; + + /* Automatic calibration */ + SET_BIT(hperh->perh->CAL, DAC_CAL_SELF_CALEN_MSK); + for (tmp = 0; tmp < 1000; ++tmp); + CLEAR_BIT(hperh->perh->CAL, DAC_CAL_SELF_CALEN_MSK); + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Configure dac channel. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC module. + * @param config: Pointer to a dac_channel_config_t structure that contains + * the configutation information for dac channel. + * @param ch: Specifies which dac channel to be config. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_dac_channel_config(dac_handle_t *hperh, dac_channel_config_t *config, dac_channel_t ch) +{ + uint32_t tmp; + + if ((hperh == NULL) || (config == NULL)) + return ERROR; + + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->enable)); + assert_param(IS_DAC_TRIGGER_TYPE(config->trigger)); + assert_param(IS_FUNC_STATE(config->refresh_en)); + assert_param(IS_DAC_PISSEL_CH_TYPE(config->pis_ch)); + + __LOCK(hperh); + tmp = ((config->pis_ch << DAC_CH0CTRL_PISSEL_POSS) | (config->trigger << DAC_CH0CTRL_PISEN_POS) | + (config->refresh_en << DAC_CH0CTRL_RCYCLEN_POS) | (config->enable << DAC_CH0CTRL_EN_POS)); + + switch (ch) { + case DAC_CHANNEL_0: + hperh->perh->CH0CTRL = tmp; + break; + + case DAC_CHANNEL_1: + hperh->perh->CH1CTRL = tmp; + break; + + default: + break; + } + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Set dac channel output value. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC module. + * @param ch: Specifies which dac channel to be set. + * @param value: The value be converted,and the valid value is low 12 bit. + * @retval None + */ +void ald_dac_output_set(dac_handle_t *hperh, dac_channel_t ch, uint32_t value) +{ + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_DAC_CHANNEL_TYPE(ch)); + + switch (ch) { + case DAC_CHANNEL_0: + hperh->perh->CH0DATA = value; + break; + + case DAC_CHANNEL_1: + hperh->perh->CH1DATA = value; + break; + + case DAC_CHANNEL_COMB: + hperh->perh->COMBDATA = value; + break; + + default: + break; + } + + return; +} + +/** + * @brief Checks whether the specified DAC flag is set or not. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified dac. + * @param status: Specifies the flag to check. + * @retval The new state. + */ +flag_status_t ald_dac_get_status(dac_handle_t *hperh, dac_status_t status) +{ + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_DAC_STATUS_TYPE(status)); + + return hperh->perh->STAT & status ? SET : RESET; +} + +/** + * @brief Enable or disable the specified interrupt + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC. + * @param it: Specifies the interrupt type to be enabled or disabled + * @arg @ref DAC_IT_CH0 Channel 0 conversion complete interrupt + * @arg @ref DAC_IT_CH1 Channel 1 conversion complete interrupt + * @arg @ref DAC_IT_CH0_UF Channel 0 data underflow interrupt + * @arg @ref DAC_IT_CH1_UF Channel 1 data underflow interrupt + * @param state: New state of the specified interrupt. + * This parameter can be: ENABLE or DISABLE + * @retval Status, see @ref ald_status_t. + */ +void ald_dac_interrupt_config(dac_handle_t *hperh, dac_it_t it, type_func_t state) +{ + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_DAC_INTERRUPT_TYPE(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + hperh->perh->IES |= it; + else + hperh->perh->IEC = it; + + return; +} + +/** + * @brief Get the status of DAC interrupt source. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC. + * @param it: Specifies the DAC interrupt source. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_dac_get_it_status(dac_handle_t *hperh, dac_it_t it) +{ + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_DAC_INTERRUPT_TYPE(it)); + + return hperh->perh->IEV & it ? SET : RESET; +} + +/** + * @brief Checks whether the specified interrupt has occurred or not. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC. + * @param flag: Specifies the interrupt type to check. + * @retval The new state. + */ +flag_status_t ald_dac_get_flag_status(dac_handle_t *hperh, dac_flag_t flag) +{ + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_DAC_FLAG_TYPE(flag)); + + return hperh->perh->RIF & flag ? SET : RESET; +} + +/** + * @brief Get the status of interrupt flag and interupt source. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC. + * @param flag: Specifies the DAC interrupt flag. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_dac_get_mask_flag_status(dac_handle_t *hperh, dac_flag_t flag) +{ + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_DAC_FLAG_TYPE(flag)); + + return hperh->perh->IFM & flag ? SET : RESET; +} + +/** + * @brief Clear interrupt state flag + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC. + * @param flag: Specifies the interrupt type to clear + * @retval None + */ +void ald_dac_clear_flag_status(dac_handle_t *hperh, dac_flag_t flag) +{ + assert_param(IS_DAC_TYPE(hperh->perh)); + assert_param(IS_DAC_FLAG_TYPE(flag)); + + hperh->perh->IFC = flag; + return; +} + +/** + * @brief This function handles DAC event interrupt request. + * @param hperh: Pointer to a dac_handle_t structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +void ald_dac_irq_handler(dac_handle_t *hperh) +{ + if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH0)) { + ald_dac_clear_flag_status(hperh, DAC_FLAG_CH0); + + if (hperh->cbk) + hperh->cbk(hperh, DAC_EVENT_CH0_CPLT); + } + + if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH1)) { + ald_dac_clear_flag_status(hperh, DAC_FLAG_CH1); + + if (hperh->cbk) + hperh->cbk(hperh, DAC_EVENT_CH1_CPLT); + } + + if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH0_UF)) { + ald_dac_clear_flag_status(hperh, DAC_FLAG_CH0_UF); + + if (hperh->cbk) + hperh->cbk(hperh, DAC_EVENT_CH0_UF); + } + + if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH1_UF)) { + ald_dac_clear_flag_status(hperh, DAC_FLAG_CH1_UF); + + if (hperh->cbk) + hperh->cbk(hperh, DAC_EVENT_CH1_UF); + } + + return; +} +/** + *@} + */ +#endif /* ALD_DAC */ +/** + *@} + */ +/** + *@} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_dma.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_dma.c new file mode 100644 index 00000000..2024a498 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_dma.c @@ -0,0 +1,1032 @@ +/** + ********************************************************************************* + * + * @file ald_dma.c + * @brief DMA module driver. + * + * @version V1.0 + * @date 09 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 09 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA driver can be used as follows: + + (#) System initialization invokes ald_dma_init(), ald_cmu_init() --> ald_dma_init(). + + (#) Declare a dma_handle_t handle structure. + + (#) Configure the dma_handle_t structure, you can configure the + dma_config_t structure with the help of ald_dma_config_struct(). + + (#) Enable the DMA Configure: + (##) Memory -- memory: call ald_dma_config_auto(). + (##) Peripheral -- memory: call ald_dma_config_basic(). + (##) If you want use the dma easily, you can do this: + (+++) Memory -- memory: call ald_dma_config_auto_easy(). + (+++) Peripheral -- memory: call ald_dma_config_basic_easy(). + + (#) Enable the DMA request signal: + (##) Memory -- memory: the DMA request signal is request automatic. + (##) Peripheral -- memory: you need enable peripheral request signal. + + (#) If you enable DMA interrupt, the callback will be invoked: + (##) When DMA transfer is completed, the cplt_cbk() will be invoked. + (##) When DMA bus occurs error, the err_cbk() will be invoked. + + (#) If you don't enable the DMA interrupt, you need do this: + (##) Polling the ald_dma_get_flag_status(), this function's parameter is channel + or DMA_ERR. + (+++) When the function's Parameter is channel, if retval is SET, it means + the DMA transfer is completed. at this moment, you can do something, + and then, you need invoke ald_dma_clear_flag_status() to clear flag. + + (+++) When the function's Parameter is DMA_ERR, if retval is SET, it means + the DMA bus occurs error. at this moment, you can do something, + and then, you need invoke ald_dma_clear_flag_status() to clear flag. + + @endverbatim + */ + +#include +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA module driver + * @{ + */ + +#ifdef ALD_DMA +/** @defgroup DMA_Private_Variables DMA Private Variables + * @{ + */ +dma_descriptor_t dma0_ctrl_base[28] __attribute__ ((aligned(512))); +dma_call_back_t dma0_cbk[12]; +/** + * @} + */ + +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ + +/** + * @brief Configure DMA channel using dma_config_t structure + * @param DMAx: Pointer to DMA peripheral + * @param mode: DMA transfer mode. see @ref dma_cycle_ctrl_t + * @param p: Pointer to dma_cycle_ctrl_t which contains + * DMA channel parameter. see @ref dma_config_t + * @retval None + */ +static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config_t *p) +{ + dma_descriptor_t *descr; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_CYCLECTRL_TYPE(mode)); + assert_param(p->src != NULL); + assert_param(p->dst != NULL); + assert_param(IS_DMA_DATA_SIZE(p->size)); + assert_param(IS_DMA_DATASIZE_TYPE(p->data_width)); + assert_param(IS_DMA_DATAINC_TYPE(p->src_inc)); + assert_param(IS_DMA_DATAINC_TYPE(p->dst_inc)); + assert_param(IS_DMA_ARBITERCONFIG_TYPE(p->R_power)); + assert_param(IS_FUNC_STATE(p->primary)); + assert_param(IS_FUNC_STATE(p->burst)); + assert_param(IS_FUNC_STATE(p->high_prio)); + assert_param(IS_FUNC_STATE(p->interrupt)); + assert_param(IS_DMA_MSEL_TYPE(p->msel)); + assert_param(IS_DMA_MSIGSEL_TYPE(p->msigsel)); + assert_param(IS_DMA_CHANNEL(p->channel)); + + if (p->primary) + descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + p->channel; + else + descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + p->channel; + + if (p->src_inc == DMA_DATA_INC_NONE) + descr->src = p->src; + else + descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << (uint32_t)p->src_inc)); + + if (p->dst_inc == DMA_DATA_INC_NONE) + descr->dst = p->dst; + else + descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << (uint32_t)p->dst_inc)); + + descr->ctrl.cycle_ctrl = mode; + descr->ctrl.next_useburst = 0; + descr->ctrl.n_minus_1 = p->size - 1; + descr->ctrl.R_power = p->R_power; + descr->ctrl.src_prot_ctrl = 0, + descr->ctrl.dst_prot_ctrl = 0, + descr->ctrl.src_size = p->data_width; + descr->ctrl.src_inc = p->src_inc; + descr->ctrl.dst_size = p->data_width; + descr->ctrl.dst_inc = p->dst_inc; + + if (p->primary) + WRITE_REG(DMAx->CHPRIALTCLR, (1 << p->channel)); + else + WRITE_REG(DMAx->CHPRIALTSET, (1 << p->channel)); + + if (p->burst) + WRITE_REG(DMAx->CHUSEBURSTSET, (1 << p->channel)); + else + WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << p->channel)); + + if (p->high_prio) + WRITE_REG(DMAx->CHPRSET, (1 << p->channel)); + else + WRITE_REG(DMAx->CHPRCLR, (1 << p->channel)); + + if (p->interrupt) + SET_BIT(DMAx->IER, (1 << p->channel)); + else + CLEAR_BIT(DMAx->IER, (1 << p->channel)); + + MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSEL_MSK, p->msel << DMA_CH0_SELCON_MSEL_POSS); + MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSIGSEL_MSK, p->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); + return; +} + +/** + * @brief Handle DMA interrupt + * @retval None + */ +void ald_dma_irq_handler(void) +{ + uint32_t i, reg; + dma_descriptor_t *descr0, *descr1; + uint32_t p_addr, a_addr; + + reg = DMA0->IFLAG; + p_addr = DMA0->CTRLBASE; + a_addr = DMA0->ALTCTRLBASE; + + for (i = 0; i < DMA_CH_COUNT; ++i) { + if (READ_BIT(reg, (1U << i))) { + if (dma0_cbk[i].cplt_cbk != NULL) + dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg); + + DMA0->ICFR = (1U << i); + descr0 = (dma_descriptor_t *)(p_addr) + i; + descr1 = (dma_descriptor_t *)(a_addr) + i; + + if ((descr0->ctrl.cycle_ctrl == DMA_CYCLE_CTRL_NONE) + && (descr1->ctrl.cycle_ctrl == DMA_CYCLE_CTRL_NONE)) + DMA0->CHENCLR = (1U << i); + } + } + + if (READ_BIT(reg, (1U << DMA_ERR))) { + DMA0->ICFR = (1U << DMA_ERR); + + for (i = 0; i < DMA_CH_COUNT; ++i) { + if (dma0_cbk[i].err_cbk != NULL) + dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg); + } + } + + return; +} +/** + * @} + */ + +/** @defgroup DMA_Public_Functions DMA Public Functions + * @{ + */ + +/** @defgroup DMA_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * + * @verbatim + =================================================================== + + #### Initialization functions #### + + =================================================================== + [..] + This subsection provides two functions to Initilizate DMA: + (+) ald_dma_reset(): Reset the DMA register. + + (+) ald_dma_init(): Initializate the DMA module. this function is + invoked by ald_cmu_init(). + this function do this: + (++) Initializte private variable dma_ctrl_base and dma_cbk. + (++) Reset DMA register. + (++) Set DMA interrupt priority: preempt_prio=1, sub_priority=1 + (++) Enable DMA interrupt. + (++) Enable DMA bus error interrupt. + (++) Configure CTRLBASE resigter. + (++) Enable DMA module. + + (+) ald_dma_config_struct(): Configure dma_config_t + structure using default parameter. + + (+) ald_dma_config_sg_alt_desc(): Configure dma_descriptor_t + structure using specified parameter. This function used + in scatter-gather mode(memory or peripheral). + + @endverbatim + * @{ + */ + +/** + * @brief Reset the DMA register + * @param DMAx: Pointer to DMA peripheral + * @retval None + */ +void ald_dma_reset(DMA_TypeDef *DMAx) +{ + uint32_t i; + + assert_param(IS_DMA(DMAx)); + + WRITE_REG(DMAx->CFG, 0x0); + WRITE_REG(DMAx->CHUSEBURSTCLR, 0xFFF); + WRITE_REG(DMAx->CHREQMASKCLR, 0xFFF); + WRITE_REG(DMAx->CHENCLR, 0xFFF); + WRITE_REG(DMAx->CHPRIALTCLR, 0xFFF); + WRITE_REG(DMAx->CHPRCLR, 0xFFF); + WRITE_REG(DMAx->ERRCLR, 0x1); + WRITE_REG(DMAx->IER, 0x0); + WRITE_REG(DMAx->ICFR, 0x80000FFF); + + for (i = 0; i < DMA_CH_COUNT; ++i) + WRITE_REG(DMAx->CH_SELCON[i], 0x0); + + return; +} + +/** + * @brief DMA module initialization, this function + * is invoked by ald_cmu_init(). + * @param DMAx: Pointer to DMA peripheral + * @retval None + */ +void ald_dma_init(DMA_TypeDef *DMAx) +{ + assert_param(IS_DMA(DMAx)); + + memset(dma0_ctrl_base, 0x0, sizeof(dma0_ctrl_base)); + memset(dma0_cbk, 0x0, sizeof(dma0_cbk)); + + ald_dma_reset(DMAx); + NVIC_SetPriority(DMA_IRQn, 2); + NVIC_EnableIRQ(DMA_IRQn); + SET_BIT(DMAx->IER, DMA_IER_DMAERRIE_MSK); + + WRITE_REG(DMAx->CTRLBASE, (uint32_t)&dma0_ctrl_base); + SET_BIT(DMAx->CFG, DMA_CFG_MASTER_ENABLE_MSK); + + return; +} + +/** + * @brief Configure dma_config_t structure using default parameter. + * User can invoked this function, before configure dma_config_t + * @param p: Pointer to dma_config_t structure, see @ref dma_config_t + * @retval None + */ +void ald_dma_config_struct(dma_config_t *p) +{ + p->data_width = DMA_DATA_SIZE_BYTE; + p->src_inc = DMA_DATA_INC_BYTE; + p->dst_inc = DMA_DATA_INC_BYTE; + p->R_power = DMA_R_POWER_1; + p->primary = ENABLE; + p->burst = DISABLE; + p->high_prio = DISABLE; + p->interrupt = ENABLE; + + return; +} + +/** + * @brief Configure dma_descriptor_t structure using specified parameter. + * @note This function used in scatter-gather mode(memory or peripheral). + * @param desc: Address of the alternate descriptor. + * @param config: Pointer to the dma_config_t structure. + * @param memory: Memory or peripheral scatter-gather. + * @retval None + */ +void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory) +{ + if ((desc == NULL) || (config == NULL)) + return; + + if (config->src_inc == DMA_DATA_INC_NONE) + desc->src = config->src; + else + desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width)); + + if (config->dst_inc == DMA_DATA_INC_NONE) + desc->dst = config->dst; + else + desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width)); + + desc->ctrl.cycle_ctrl = memory ? DMA_CYCLE_CTRL_MEM_SG_ALTERNATE : DMA_CYCLE_CTRL_PER_SG_ALTERNATE; + desc->ctrl.next_useburst = memory ? 0 : 1; + desc->ctrl.n_minus_1 = config->size - 1; + desc->ctrl.R_power = config->R_power; + desc->ctrl.src_prot_ctrl = 0; + desc->ctrl.dst_prot_ctrl = 0; + desc->ctrl.src_size = config->data_width; + desc->ctrl.src_inc = config->src_inc; + desc->ctrl.dst_size = config->data_width; + desc->ctrl.dst_inc = config->dst_inc; + + return; +} + +/** + * @} + */ + +/** @defgroup DMA_Public_Functions_Group2 Configure DMA channel functions + * @brief Configure DMA channel functions + * + * @verbatim + =================================================================== + + #### Configure DMA channel functions #### + + =================================================================== + [..] + This subsection provides some functions allowing to configure + DMA channel. Include two type DMA transfer: + (+) Carry data from memory to memory, this mode APIs are: + (++) ald_dma_config_auto(): Configure DMA channel according to + the specified parameter in the dma_handle_t structure. + (++) ald_dma_restart_auto(): Restart DMA transmitted. + (++) ald_dma_config_auto_easy(): Configure DMA channel according + to the specified parameter. If you want use the dma easily, + you can invoke this function. + (++) ald_dma_config_sg_mem(): Carry data used scatter-gather mode. + (+) Carry data from peripheral to memory or from memory to peripheral, + this mode APIs are: + (++) ald_dma_config_basic(): Configure DMA channel according to + the specified parameter in the dma_handle_t structure. + (++) ald_dma_restart_basic(): Restart DMA transmitted. + (++) ald_dma_config_basic_easy(): Configure DMA channel according + to the specified parameter. If you want use the dma easily, + you can invoke this function. + (++) ald_dma_ping_pong(): Carry data used ping-pong mode. + (++) ald_dma_config_sg_per(): Carry data used scatter-gather mode. + + @endverbatim + * @{ + */ + +/** + * @brief Configure DMA channel according to the specified parameter + * in the dma_handle_t structure. The DMA mode is automatic. + * This mode is used to carry data from memory to memory. + * @param hperh: Pointer to DMA_handle_t structure that contains + * configuration information for specified DMA channel. + * @retval None + */ +void ald_dma_config_auto(dma_handle_t *hperh) +{ + dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; + dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; + dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; + dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; + dma_config_base(hperh->perh, DMA_CYCLE_CTRL_AUTO, &hperh->config); + + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); + + return; +} + +/** + * @brief Restart DMA transmitted. The DMA mode is automatic. + * The other parameters have not changed except 'size' and 'addr'. + * @param hperh: Pointer to DMA_handle_t structure that contains + * configuration information for specified DMA channel. + * @param src: Source data begin pointer + * @param dst: Destination data begin pointer + * @param size: Size. + * @retval None + */ +void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size) +{ + dma_descriptor_t *descr; + + if (hperh->config.primary) + descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel; + else + descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel; + + if (src) { + if (hperh->config.src_inc == DMA_DATA_INC_NONE) + descr->src = src; + else + descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width)); + } + + if (dst) { + if (hperh->config.dst_inc == DMA_DATA_INC_NONE) + descr->dst = dst; + else + descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width)); + } + + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); + descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO; + descr->ctrl.n_minus_1 = size - 1; + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel)); + return; +} + + + +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is automatic. This mode is used to carry data + * from memory to memory. If User want use the dma easily, + * they can invoke this function. + * @param DMAx: Pointer to DMA peripheral + * @param src: Source data begin pointer + * @param dst: Destination data begin pointer + * @param size: The total number of DMA transfers that DMA cycle contains + * @param channel: Channel index which will be used. + * @param cbk: DMA complete callback function + * + * @retval None + */ +void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, + uint16_t size, uint8_t channel, void (*cbk)(void *arg)) +{ + dma_handle_t hperh; + + assert_param(IS_DMA(DMAx)); + + ald_dma_config_struct(&hperh.config); + hperh.config.src = src; + hperh.config.dst = dst; + hperh.config.size = size; + hperh.config.msel = DMA_MSEL_NONE; + hperh.config.msigsel = DMA_MSIGSEL_NONE; + hperh.config.channel = channel; + + hperh.perh = DMAx; + hperh.cplt_cbk = cbk; + hperh.cplt_arg = NULL; + hperh.err_cbk = NULL; + + ald_dma_clear_flag_status(DMAx, channel); + ald_dma_config_auto(&hperh); + + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter + * in the dma_handle_t structure. The DMA mode is basic. + * This mode is used to carry data from peripheral to memory + * or from memory to peripheral. + * @param hperh: Pointer to dma_handle_t structure that contains + * configuration information for specified DMA channel. + * @retval None + */ +void ald_dma_config_basic(dma_handle_t *hperh) +{ + dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk; + dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk; + dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg; + dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg; + + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); + dma_config_base(hperh->perh, DMA_CYCLE_CTRL_BASIC, &hperh->config); + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + + return; +} + +/** + * @brief Restart DMA transmitted. The DMA mode is basic. + * The other parameters have not changed except 'size' and 'addr'. + * @param hperh: Pointer to DMA_handle_t structure that contains + * configuration information for specified DMA channel. + * @param src: Source data begin pointer + * @param dst: Destination data begin pointer + * @param size: Size. + * @retval None + */ +void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size) +{ + dma_descriptor_t *descr; + + if (hperh->config.primary) + descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel; + else + descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel; + + if (src) { + if (hperh->config.src_inc == DMA_DATA_INC_NONE) + descr->src = src; + else + descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width)); + } + + if (dst) { + if (hperh->config.dst_inc == DMA_DATA_INC_NONE) + descr->dst = dst; + else + descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width)); + } + + ald_dma_clear_flag_status(hperh->perh, hperh->config.channel); + descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC; + descr->ctrl.n_minus_1 = size - 1; + WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel)); + + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is basic. This mode is used to carry data + * from peripheral to memory or negative direction. If user want + * use the dma easily, they can invoke this function. + * @param DMAx: Pointer to DMA peripheral + * @param src: Source data begin pointer + * @param dst: Destination data begin pointer + * @param size: The total number of DMA transfers that DMA cycle contains + * @param msel: Input source to DMA channel @ref dma_msel_t + * @param msigsel: Input signal to DMA channel @ref dma_msigsel_t + * @param channel: Channel index which will be used + * @param cbk: DMA complete callback function + * + * @retval None + * + */ +void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, + dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) +{ + dma_handle_t hperh; + + assert_param(IS_DMA(DMAx)); + ald_dma_config_struct(&hperh.config); + + if (((uint32_t)src) >= 0x40000000) + hperh.config.src_inc = DMA_DATA_INC_NONE; + + if (((uint32_t)dst) >= 0x40000000) + hperh.config.dst_inc = DMA_DATA_INC_NONE; + + hperh.config.src = src; + hperh.config.dst = dst; + hperh.config.size = size; + hperh.config.msel = msel; + hperh.config.msigsel = msigsel; + hperh.config.channel = channel; + + hperh.perh = DMAx; + hperh.cplt_cbk = cbk; + hperh.cplt_arg = NULL; + hperh.err_cbk = NULL; + + ald_dma_clear_flag_status(DMAx, channel); + ald_dma_config_basic(&hperh); + + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is ping-pong. + * @note The ping-pong mode does not support memory to memory. + * @param DMAx: Pointer to DMA peripheral. + * @param config: Pointer to the dma_config_t structure which contains + * the specified parameters. + * @param first: Whether it is the first transmission. 1-first, 0-not first. + * @param cbk: DMA complete callback function. + * @retval None + */ +void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config, + uint8_t first, void (*cbk)(void *arg)) +{ + dma_descriptor_t *desc; + + assert_param(IS_DMA(DMAx)); + assert_param(config->src != NULL); + assert_param(config->dst != NULL); + assert_param(IS_DMA_DATA_SIZE(config->size)); + assert_param(IS_DMA_DATASIZE_TYPE(config->data_width)); + assert_param(IS_DMA_DATAINC_TYPE(config->src_inc)); + assert_param(IS_DMA_DATAINC_TYPE(config->dst_inc)); + assert_param(IS_DMA_ARBITERCONFIG_TYPE(config->R_power)); + assert_param(IS_FUNC_STATE(config->primary)); + assert_param(IS_FUNC_STATE(config->burst)); + assert_param(IS_FUNC_STATE(config->high_prio)); + assert_param(IS_FUNC_STATE(config->interrupt)); + assert_param(IS_DMA_MSEL_TYPE(config->msel)); + assert_param(IS_DMA_MSIGSEL_TYPE(config->msigsel)); + assert_param(IS_DMA_CHANNEL(config->channel)); + + dma0_cbk[config->channel].cplt_cbk = cbk; + dma0_cbk[config->channel].err_cbk = NULL; + dma0_cbk[config->channel].cplt_arg = NULL; + dma0_cbk[config->channel].err_arg = NULL; + + if (config->primary) + desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + config->channel; + else + desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + config->channel; + + if (config->src_inc == DMA_DATA_INC_NONE) + desc->src = config->src; + else + desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width)); + + if (config->dst_inc == DMA_DATA_INC_NONE) + desc->dst = config->dst; + else + desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width)); + + desc->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_PINGPONG; + desc->ctrl.next_useburst = 0; + desc->ctrl.n_minus_1 = config->size - 1; + desc->ctrl.R_power = config->R_power; + desc->ctrl.src_prot_ctrl = 0, + desc->ctrl.dst_prot_ctrl = 0, + desc->ctrl.src_size = config->data_width; + desc->ctrl.src_inc = config->src_inc; + desc->ctrl.dst_size = config->data_width; + desc->ctrl.dst_inc = config->dst_inc; + + if (!first) + return; + + if (config->primary) + WRITE_REG(DMAx->CHPRIALTCLR, (1 << config->channel)); + else + WRITE_REG(DMAx->CHPRIALTSET, (1 << config->channel)); + + if (config->burst) + WRITE_REG(DMAx->CHUSEBURSTSET, (1 << config->channel)); + else + WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << config->channel)); + + if (config->high_prio) + WRITE_REG(DMAx->CHPRSET, (1 << config->channel)); + else + WRITE_REG(DMAx->CHPRCLR, (1 << config->channel)); + + if (config->interrupt) + SET_BIT(DMAx->IER, (1 << config->channel)); + else + CLEAR_BIT(DMAx->IER, (1 << config->channel)); + + MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSEL_MSK, config->msel << DMA_CH0_SELCON_MSEL_POSS); + MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSIGSEL_MSK, config->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); + + WRITE_REG(DMAx->ICFR, (1 << config->channel)); + WRITE_REG(DMAx->CHENSET, (1 << config->channel)); + + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is memory scatter-gather. + * @param DMAx: Pointer to DMA peripheral. + * @param desc: Pointer to first alternate descriptor. + * @param nr: Number of the alternate descriptor. + * @param channel: Channel index which will be used. + * @param cbk: DMA complete callback function. + * @retval None + */ +void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, + uint8_t channel, void (*cbk)(void *arg)) +{ + dma_descriptor_t *tmp = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_CHANNEL(channel)); + + if ((desc == NULL) || (nr == 0)) + return; + + dma0_cbk[channel].cplt_cbk = cbk; + dma0_cbk[channel].err_cbk = NULL; + dma0_cbk[channel].cplt_arg = NULL; + dma0_cbk[channel].err_arg = NULL; + + tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD)); + tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD)); + tmp->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_MEM_SG_PRIMARY; + tmp->ctrl.next_useburst = 0; + tmp->ctrl.n_minus_1 = (nr << 2) - 1; + tmp->ctrl.R_power = DMA_R_POWER_4; + tmp->ctrl.src_prot_ctrl = 0, + tmp->ctrl.dst_prot_ctrl = 0, + tmp->ctrl.src_size = DMA_DATA_SIZE_WORD; + tmp->ctrl.src_inc = DMA_DATA_INC_WORD; + tmp->ctrl.dst_size = DMA_DATA_SIZE_WORD; + tmp->ctrl.dst_inc = DMA_DATA_INC_WORD; + + desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO; + WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel)); + WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << channel)); + WRITE_REG(DMAx->CHPRCLR, (1 << channel)); + + WRITE_REG(DMAx->ICFR, (1 << channel)); + SET_BIT(DMAx->IER, (1 << channel)); + WRITE_REG(DMAx->CHENSET, (1 << channel)); + SET_BIT(DMAx->CHSWREQ, (1 << channel)); + + return; +} + +/** + * @brief Configure DMA channel according to the specified parameter. + * The DMA mode is peripheral scatter-gather. + * @note The size of the first transmission must be 5. + * @param DMAx: Pointer to DMA peripheral. + * @param desc: Pointer to first alternate descriptor. + * @param nr: Number of the alternate descriptor. + * @param burst: 1-Enable burst, 0-Disable burst. + * @param msel: Input source to DMA channel @ref dma_msel_t + * @param msigsel: Input signal to DMA channel @ref dma_msigsel_t + * @param channel: Channel index which will be used. + * @param cbk: DMA complete callback function. + * @retval None + */ +void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst, + dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg)) +{ + dma_descriptor_t *tmp = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_MSEL_TYPE(msel)); + assert_param(IS_DMA_MSIGSEL_TYPE(msigsel)); + assert_param(IS_DMA_CHANNEL(channel)); + + if ((desc == NULL) || (nr == 0)) + return; + + dma0_cbk[channel].cplt_cbk = cbk; + dma0_cbk[channel].err_cbk = NULL; + dma0_cbk[channel].cplt_arg = NULL; + dma0_cbk[channel].err_arg = NULL; + + tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD)); + tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD)); + tmp->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_PER_SG_PRIMARY; + tmp->ctrl.next_useburst = 0; + tmp->ctrl.n_minus_1 = (nr << 2) - 1; + tmp->ctrl.R_power = DMA_R_POWER_4; + tmp->ctrl.src_prot_ctrl = 0, + tmp->ctrl.dst_prot_ctrl = 0, + tmp->ctrl.src_size = DMA_DATA_SIZE_WORD; + tmp->ctrl.src_inc = DMA_DATA_INC_WORD; + tmp->ctrl.dst_size = DMA_DATA_SIZE_WORD; + tmp->ctrl.dst_inc = DMA_DATA_INC_WORD; + + desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC; + WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel)); + burst ? (DMAx->CHUSEBURSTSET = (1 << channel)) : (DMAx->CHUSEBURSTCLR, (1 << channel)); + WRITE_REG(DMAx->CHPRCLR, (1 << channel)); + + MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSEL_MSK, msel << DMA_CH0_SELCON_MSEL_POSS); + MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSIGSEL_MSK, msigsel << DMA_CH0_SELCON_MSIGSEL_POSS); + + WRITE_REG(DMAx->ICFR, (1 << channel)); + SET_BIT(DMAx->IER, (1 << channel)); + WRITE_REG(DMAx->CHENSET, (1 << channel)); + + return; +} +/** + * @} + */ + +/** @defgroup DMA_Public_Functions_Group3 DMA Control functions + * @brief DMA control functions + * + * @verbatim + =================================================================== + + #### DMA control functions #### + + =================================================================== + [..] + This subsection provides some functions allowing to control DMA: + (+) ald_dma_channel_config(): Control DMA channel ENABLE/DISABLE. + (+) ald_dma_interrupt_config(): Control DMA channel interrupt ENABLE or + DISABLE. + (+) ald_dma_get_it_status(): Check whether the specified channel + interrupt is SET or RESET. + (+) ald_dma_get_flag_status(): Check whether the specified channel + flag is SET or RESET. + (+) ald_dma_clear_flag_status(): Clear the specified channel + pending flag + + @endverbatim + * @{ + */ + +/** + * @brief Configure channel enable or disable. It will unbind descriptor with + * channel, when channel has been disable. + * @param DMAx: Pointer to DMA peripheral + * @param channel: channel index + * @param state: status of channel: + * @arg ENABLE: Enable the channel + * @arg DISABLE: Disable the channel + * @retval None + */ +void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) +{ + dma_descriptor_t *descr, *alt_descr; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_CHANNEL(channel)); + assert_param(IS_FUNC_STATE(state)); + + descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + alt_descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + + if (state) { + WRITE_REG(DMAx->CHENSET, (1 << channel)); + } + else { + memset(descr, 0x00, sizeof(dma_descriptor_t)); + memset(alt_descr, 0x00, sizeof(dma_descriptor_t)); + WRITE_REG(DMAx->CH_SELCON[channel], 0x0); + WRITE_REG(DMAx->CHENCLR, (1 << channel)); + } + + return; +} + +/** + * @brief Configure the interrupt enable or disable + * @param DMAx: Pointer to DMA peripheral + * @param channel: Channel index or DMA_ERR. + * @arg 0~11: Channel index + * @arg DMA_ERR: DMA bus error + * @param state: status of channel: + * @arg ENABLE: Enable the channel + * @arg DISABLE: Disable the channel + * + * @retval None + */ +void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state) +{ + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + SET_BIT(DMAx->IER, (1 << channel)); + else + CLEAR_BIT(DMAx->IER, (1 << channel)); + + return; +} + +/** + * @brief Check whether the specified channel interrupt + * is set or reset + * @param DMAx: Pointer to DMA peripheral + * @param channel: Channel index or DMA_ERR + * @arg 0~11: Channel index + * @arg DMA_ERR: DMA bus error + * @retval Status: + * - SET: Channel interrupt is set + * - RESET: Channel interrupt is reset + */ +it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel) +{ + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + + if (READ_BIT(DMAx->IER, (1 << channel))) + return SET; + + return RESET; +} + +/** + * @brief Check whether the specified channel flag + * is set or reset + * @param DMAx: Pointer to DMA peripheral + * @param channel: Channel index or DMA_ERR + * @arg 0~11: Channel index + * @arg DMA_ERR: DMA bus error + * @retval Status: + * - SET: Channel flag is set + * - RESET: Channel flag is reset + */ +flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel) +{ + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + + if (READ_BIT(DMAx->IFLAG, (1 << channel))) + return SET; + + return RESET; +} + +/** + * @brief Clear the specified channel pending flag + * @param DMAx: Pointer to DMA peripheral + * @param channel: Channel index or DMA_ERR + * @arg 0~11: Channel index + * @arg DMA_ERR: DMA bus error + * @retval None + */ +void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel) +{ + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + + WRITE_REG(DMAx->ICFR, (1 << channel)); + return; +} + +/** + * @brief Get the completion status of the descriptor + * @param DMAx: Pointer to DMA peripheral + * @param channel: Channel index + * @retval Completion status: + * - DMA_DESCP_CPLT_PRI: Primary descriptor has been completed + * - DMA_DESCP_CPLT_ALT: Alternate descriptor has been completed + * - DMA_DESCP_CPLT_ALL: Both primary and alternate descriptors have been completed + */ +dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel) +{ + uint8_t pri, alt; + dma_descriptor_t *desc; + + assert_param(IS_DMA(DMAx)); + assert_param(IS_DMA_IT_TYPE(channel)); + + desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel; + pri = desc->ctrl.cycle_ctrl; + desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel; + alt = desc->ctrl.cycle_ctrl; + + if ((pri == 0) && (alt == 0)) + return DMA_DESCP_CPLT_ALL; + + if (pri == 0) + return DMA_DESCP_CPLT_PRI; + else + return DMA_DESCP_CPLT_ALT; +} +/** + * @} + */ + +/** + * @} + */ +#endif /* ALD_DMA */ +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_ebi.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_ebi.c new file mode 100644 index 00000000..a680cee8 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_ebi.c @@ -0,0 +1,693 @@ +/** + ********************************************************************************* + * + * @file ald_ebi.c + * @brief EBI module driver. + * + * @version V1.0 + * @date 20 Jan 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 20 Jan 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_conf.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup EBI EBI + * @brief EBI module driver + * @{ + */ +#ifdef ALD_EBI + +/** @defgroup EBI_Public_Functions EBI Public Functions + * @{ + */ + +/** @defgroup EBI_Public_Functions_Group1 NOR-FLASH SRAM initialize functions + * @brief NOR-FLASH SRAM initialize functions + * @{ + */ +/** + * @brief Initialize the EBI_NOR_SRAM device according to the specified + * control parameters in the EBI_NOR_SRAM_InitTypeDef + * @param dev: Pointer to NOR_SRAM device instance + * @param init: Pointer to NOR_SRAM Initialization structure + * @retval None + */ +void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init) +{ + assert_param(IS_EBI_NORSRAM_DEVICE(dev)); + assert_param(IS_EBI_NORSRAM_BANK(init->bank)); + assert_param(IS_EBI_MUX(init->mux)); + assert_param(IS_EBI_MEMORY(init->type)); + assert_param(IS_EBI_NORSRAM_MEMORY_WIDTH(init->width)); + assert_param(IS_EBI_BURSTMODE(init->acc_mode)); + assert_param(IS_EBI_WAIT_POLARITY(init->polarity)); + assert_param(IS_EBI_WRAP_MODE(init->wrap_mode)); + assert_param(IS_EBI_WAIT_SIGNAL_ACTIVE(init->active)); + assert_param(IS_EBI_WRITE_OPERATION(init->write)); + assert_param(IS_EBI_WAITE_SIGNAL(init->signal)); + assert_param(IS_EBI_EXTENDED_MODE(init->ext_mode)); + assert_param(IS_EBI_ASYNWAIT(init->wait)); + assert_param(IS_EBI_WRITE_BURST(init->burst)); + + /* Disable NORSRAM device */ + ald_ebi_nor_sram_disable(dev, init->bank); + + /* Set NORSRAM device control parameters */ + if (init->type == EBI_MEMORY_TYPE_NOR) { + MODIFY_REG(dev->BTCR[init->bank], BCTRLR_CLEAR_MASK, (uint32_t)((uint32_t)EBI_NORSRAM_FLASH_ACCESS_ENABLE + | (uint32_t)init->mux + | (uint32_t)init->type + | (uint32_t)init->width + | (uint32_t)init->acc_mode + | (uint32_t)init->polarity + | (uint32_t)init->wrap_mode + | (uint32_t)init->active + | (uint32_t)init->write + | (uint32_t)init->signal + | (uint32_t)init->ext_mode + | (uint32_t)init->wait + | (uint32_t)init->burst)); + } + else { + MODIFY_REG(dev->BTCR[init->bank], BCTRLR_CLEAR_MASK, (uint32_t)(EBI_NORSRAM_FLASH_ACCESS_DISABLE + | (uint32_t)init->mux + | (uint32_t)init->type + | (uint32_t)init->width + | (uint32_t)init->acc_mode + | (uint32_t)init->polarity + | (uint32_t)init->wrap_mode + | (uint32_t)init->active + | (uint32_t)init->write + | (uint32_t)init->signal + | (uint32_t)init->ext_mode + | (uint32_t)init->wait + | (uint32_t)init->burst)); + } +} + +/** + * @brief Initialize the EBI_NOR_SRAM Timing according to the specified + * parameters in the EBI_NOR_SRAM_TimingTypeDef + * @param dev: Pointer to NOR_SRAM device instance + * @param timing: Pointer to NOR_SRAM Timing structure + * @param bank: NOR_SRAM bank number + * @retval None + */ +void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank) +{ + assert_param(IS_EBI_NORSRAM_DEVICE(dev)); + assert_param(IS_EBI_ADDRESS_SETUP_TIME(timing->addr_setup)); + assert_param(IS_EBI_ADDRESS_HOLD_TIME(timing->addr_hold)); + assert_param(IS_EBI_DATASETUP_TIME(timing->data_setup)); + assert_param(IS_EBI_TURNAROUND_TIME(timing->bus_dur)); + assert_param(IS_EBI_DATA_LATENCY(timing->latency)); + assert_param(IS_EBI_ACCESS_MODE(timing->mode)); + assert_param(IS_EBI_NORSRAM_BANK(bank)); + + /* Set EBI_NORSRAM device timing parameters */ + MODIFY_REG(dev->BTCR[bank + 1U], BTR_CLEAR_MASK, \ + (uint32_t)(timing->addr_setup | \ + ((timing->addr_hold) << EBI_BTRx_ADDHOLD_POSS) | \ + ((timing->data_setup) << EBI_BTRx_DATAHOLD_POSS) | \ + ((timing->bus_dur) << EBI_BTRx_BUSTURN_POSS) | \ + (((timing->div) - 1U) << EBI_BTRx_CLKDIV_POSS) | \ + (((timing->latency) - 1U) << EBI_BTRx_DATALAT_POSS) | \ + (timing->mode))); +} + +/** + * @brief Initialize the EBI_NOR_SRAM Extended mode Timing according to the specified + * parameters in the EBI_NOR_SRAM_TimingTypeDef + * @param dev: Pointer to NOR_SRAM device instance + * @param timing: Pointer to NOR_SRAM Timing structure + * @param bank: NOR_SRAM bank number + * @param mode EBI Extended Mode + * This parameter can be one of the following values: + * @arg EBI_EXTENDED_MODE_DISABLE + * @arg EBI_EXTENDED_MODE_ENABLE + * @retval None + */ +void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode) +{ + assert_param(IS_EBI_EXTENDED_MODE(mode)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + if (mode == EBI_EXTENDED_MODE_ENABLE) { + assert_param(IS_EBI_NORSRAM_EXTENDED_DEVICE(dev)); + assert_param(IS_EBI_ADDRESS_SETUP_TIME(timing->addr_setup)); + assert_param(IS_EBI_ADDRESS_HOLD_TIME(timing->addr_hold)); + assert_param(IS_EBI_DATASETUP_TIME(timing->data_setup)); + assert_param(IS_EBI_TURNAROUND_TIME(timing->bus_dur)); + assert_param(IS_EBI_ACCESS_MODE(timing->mode)); + assert_param(IS_EBI_NORSRAM_BANK(bank)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + MODIFY_REG(dev->BWTR[bank], BWTR_CLEAR_MASK, \ + (uint32_t)(timing->addr_setup | \ + ((timing->addr_hold) << EBI_BWRTRx_ADDHOLD_POSS) | \ + ((timing->data_setup) << EBI_BWRTRx_DATAHOLD_POSS) | \ + timing->mode | \ + ((timing->bus_dur) << EBI_BWRTRx_BUSTURN_POSS))); + } + else { + dev->BWTR[bank] = 0x0FFFFFFFU; + } +} + +/** + * @brief DeInitialize the EBI_NOR_SRAM peripheral + * @param dev: Pointer to NOR_SRAM device instance + * @param e_dev: Pointer to NOR_SRAM extended mode device instance + * @param bank: NOR_SRAM bank number + * @retval ald status + */ +ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank) +{ + assert_param(IS_EBI_NORSRAM_DEVICE(dev)); + assert_param(IS_EBI_NORSRAM_EXTENDED_DEVICE(e_dev)); + assert_param(IS_EBI_NORSRAM_BANK(bank)); + + /* Disable the EBI_NOR/SRAM device */ + ald_ebi_nor_sram_disable(dev, bank); + + /* De-initialize the EBI_NOR/SRAM device */ + if (bank == EBI_NORSRAM_BANK1) + dev->BTCR[bank] = 0x000030DBU; + else + dev->BTCR[bank] = 0x000030D2U; + + dev->BTCR[bank + 1U] = 0x0FFFFFFFU; + e_dev->BWTR[bank] = 0x0FFFFFFFU; + + return OK; +} +/** + * @} + */ + +/** @defgroup EBI_Public_Functions_Group2 NOR-FLASH SRAM control functions + * @brief NOR-FLASH SRAM control functions + * @{ + */ +/** + * @brief Enable the NOR/SRAM device access. + * @param dev: NOR/SRAM Instance + * @param bank: NOR/SRAM Bank + * @retval none + */ +void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NORSRAM_DEVICE(dev)); + assert_param(IS_EBI_NORSRAM_BANK(bank)); + + SET_BIT(dev->BTCR[bank], EBI_BCTRLRx_MEMBKEN_MSK); +} + +/** + * @brief Disable the NORSRAM device access. + * @param dev: EBI_NORSRAM Instance + * @param bank: EBI_NORSRAM Bank + * @retval none + */ +void ald_ebi_nor_sram_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NORSRAM_DEVICE(dev)); + assert_param(IS_EBI_NORSRAM_BANK(bank)); + + CLEAR_BIT(dev->BTCR[bank], EBI_BCTRLRx_MEMBKEN_MSK); +} + +/** + * @brief Enables dynamically NOR-FLASH/SRAM write operation. + * @param dev: Pointer to NOR/SRAM device instance + * @param bank: NOR/SRAM bank number + * @retval void + */ +void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NORSRAM_DEVICE(dev)); + assert_param(IS_EBI_NORSRAM_BANK(bank)); + + /* Enable write operation */ + SET_BIT(dev->BTCR[bank], EBI_WRITE_OPERATION_ENABLE); +} + +/** + * @brief Disables dynamically EBI_NORSRAM write operation. + * @param dev: Pointer to NORSRAM device instance + * @param bank: NORSRAM bank number + * @retval None + */ +void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NORSRAM_DEVICE(dev)); + assert_param(IS_EBI_NORSRAM_BANK(bank)); + + /* Disable write operation */ + CLEAR_BIT(dev->BTCR[bank], EBI_WRITE_OPERATION_ENABLE); +} +/** + * @} + */ + +/** @defgroup EBI_Public_Functions_Group3 NAND-FLASH initialize functions + * @brief NAND-FLASH initialize functions + * @{ + */ +/** + * @brief Initializes the EBI_NAND device according to the specified + * control parameters in the EBI_NAND_HandleTypeDef + * @param dev: Pointer to NAND device instance + * @param init: Pointer to NAND Initialization structure + * @retval None + */ +void ald_ebi_nand_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(init->bank)); + assert_param(IS_EBI_WAIT_FEATURE(init->wait)); + assert_param(IS_EBI_NAND_MEMORY_WIDTH(init->width)); + assert_param(IS_EBI_ECC_STATE(init->ecc)); + assert_param(IS_EBI_ECCPAGE_SIZE(init->size)); + assert_param(IS_EBI_TCLR_TIME(init->cle_time)); + assert_param(IS_EBI_TAR_TIME(init->ale_time)); + + /* Set NAND device control parameters */ + if (init->bank == EBI_NAND_BANK2) { + MODIFY_REG(dev->PCTRLR2, PCTRLR_CLEAR_MASK, ((uint32_t)init->wait | + (uint32_t)EBI_PCTRLR_MEMORY_TYPE_NAND | + (uint32_t)init->width | + (uint32_t)init->ecc | + (uint32_t)init->size | + (uint32_t)((init->cle_time) << EBI_PCTRLRx_CRDLY_POSS) | + (uint32_t)((init->ale_time) << EBI_PCTRLRx_ARDLY_POSS))); + } + else { + MODIFY_REG(dev->PCTRLR3, PCTRLR_CLEAR_MASK, ((uint32_t)init->wait | + (uint32_t)EBI_PCTRLR_MEMORY_TYPE_NAND | + (uint32_t)init->width | + (uint32_t)init->ecc | + (uint32_t)init->size | + (uint32_t)((init->cle_time) << EBI_PCTRLRx_CRDLY_POSS) | + (uint32_t)((init->ale_time) << EBI_PCTRLRx_ARDLY_POSS))); + } +} + +/** + * @brief Initializes the EBI_NAND Common space Timing according to the specified + * parameters in the EBI_NAND_TimingTypeDef + * @param dev: Pointer to NAND device instance + * @param timing: Pointer to NAND timing structure + * @param bank: NAND bank number + * @retval None + */ +void ald_ebi_nand_comm_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_SETUP_TIME(timing->time)); + assert_param(IS_EBI_WAIT_TIME(timing->wait_time)); + assert_param(IS_EBI_HOLD_TIME(timing->hold_time)); + assert_param(IS_EBI_HIZ_TIME(timing->hiz_time)); + assert_param(IS_EBI_NAND_BANK(bank)); + + /* Set EBI_NAND device timing parameters */ + if (bank == EBI_NAND_BANK2) { + MODIFY_REG(dev->PMEMR2, PMEMR_CLEAR_MASK, (timing->time | \ + ((timing->wait_time) << EBI_PMEMRx_MEMWAIT_POSS) | \ + ((timing->hold_time) << EBI_PMEMRx_MEMHOLD_POSS) | \ + ((timing->hiz_time) << EBI_PMEMRx_MEMHIZT_POSS))); + } + else { + MODIFY_REG(dev->PMEMR3, PMEMR_CLEAR_MASK, (timing->time | \ + ((timing->wait_time) << EBI_PMEMRx_MEMWAIT_POSS) | \ + ((timing->hold_time) << EBI_PMEMRx_MEMHOLD_POSS) | \ + ((timing->hiz_time) << EBI_PMEMRx_MEMHIZT_POSS))); + } +} + +/** + * @brief Initializes the EBI_NAND Attribute space Timing according to the specified + * parameters in the EBI_NAND_TimingTypeDef + * @param dev: Pointer to NAND device instance + * @param timing: Pointer to NAND timing structure + * @param bank: NAND bank number + * @retval None + */ +void ald_ebi_nand_attr_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_SETUP_TIME(timing->time)); + assert_param(IS_EBI_WAIT_TIME(timing->wait_time)); + assert_param(IS_EBI_HOLD_TIME(timing->hold_time)); + assert_param(IS_EBI_HIZ_TIME(timing->hiz_time)); + assert_param(IS_EBI_NAND_BANK(bank)); + + /* Set FMC_NAND device timing parameters */ + if (bank == EBI_NAND_BANK2) { + MODIFY_REG(dev->PATTR2, PATTR_CLEAR_MASK, (timing->time | \ + ((timing->wait_time) << EBI_PATTRx_ATTWAIT_POSS) | \ + ((timing->hold_time) << EBI_PATTRx_ATTHOLD_POSS) | \ + ((timing->hiz_time) << EBI_PATTRx_ATTHIZT_POSS))); + } + else { + MODIFY_REG(dev->PATTR3, PATTR_CLEAR_MASK, (timing->time | \ + ((timing->wait_time) << EBI_PATTRx_ATTWAIT_POSS) | \ + ((timing->hold_time) << EBI_PATTRx_ATTHOLD_POSS) | \ + ((timing->hiz_time) << EBI_PATTRx_ATTHIZT_POSS))); + } +} + +/** + * @brief DeInitializes the EBI_NAND device + * @param dev: Pointer to NAND device instance + * @param bank: NAND bank number + * @retval None + */ +void ald_ebi_nand_deinit(EBI_NAND_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + /* Disable the NAND Bank */ + ald_ebi_nand_disable(dev, bank); + + /* De-initialize the NAND Bank */ + if (bank == EBI_NAND_BANK2) { + /* Set the EBI_NAND_BANK2 registers to their reset values */ + WRITE_REG(dev->PCTRLR2, 0x00000018U); + WRITE_REG(dev->STAR2, 0x00000040U); + WRITE_REG(dev->PMEMR2, 0xFCFCFCFCU); + WRITE_REG(dev->PATTR2, 0xFCFCFCFCU); + } + /* EBI_Bank3_NAND */ + else { + /* Set the EBI_NAND_BANK3 registers to their reset values */ + WRITE_REG(dev->PCTRLR3, 0x00000018U); + WRITE_REG(dev->STAR3, 0x00000040U); + WRITE_REG(dev->PMEMR3, 0xFCFCFCFCU); + WRITE_REG(dev->PATTR3, 0xFCFCFCFCU); + } +} +/** + * @} + */ + +/** @defgroup EBI_Public_Functions_Group4 NAND-FLASH control functions + * @brief NAND-FLASH control functions + * @{ + */ +/** + * @brief Enable the NAND device access + * @param dev: EBI_NAND Instance + * @param bank: EBI_NAND Bank + * @retval None + */ +void ald_ebi_nand_enable(EBI_NAND_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + if (bank == EBI_NAND_BANK2) + SET_BIT(dev->PCTRLR2, EBI_PCTRLRx_MEMBKEN_MSK); + else + SET_BIT(dev->PCTRLR3, EBI_PCTRLRx_MEMBKEN_MSK); +} + +/** + * @brief Disable the NAND device access. + * @param dev: EBI_NAND Instance + * @param bank: EBI_NAND Bank + * @retval None + */ +void ald_ebi_nand_disable(EBI_NAND_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + if (bank == EBI_NAND_BANK2) + CLEAR_BIT(dev->PCTRLR2, EBI_PCTRLRx_MEMBKEN_MSK); + else + CLEAR_BIT(dev->PCTRLR3, EBI_PCTRLRx_MEMBKEN_MSK); +} + +/** + * @brief Enable the NAND device interrupt. + * @param dev: EBI_NAND Instance + * @param bank: EBI_NAND Bank + * @param it: EBI_NAND interrupt + * This parameter can be any combination of the following values: + * @arg EBI_IT_RISING_EDGE: Interrupt rising edge. + * @arg EBI_IT_LEVEL: Interrupt level. + * @arg EBI_IT_FALLING_EDGE: Interrupt falling edge. + * @retval None + */ +void ald_ebi_nand_enable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + if (bank == EBI_NAND_BANK2) + SET_BIT(dev->STAR2, it); + else + SET_BIT(dev->STAR3, it); +} + +/** + * @brief Disable the NAND device interrupt. + * @param dev: EBI_NAND Instance + * @param bank: EBI_NAND Bank + * @param it: EBI_NAND interrupt + * This parameter can be any combination of the following values: + * @arg EBI_IT_RISING_EDGE: Interrupt rising edge. + * @arg EBI_IT_LEVEL: Interrupt level. + * @arg EBI_IT_FALLING_EDGE: Interrupt falling edge. + * @retval None + */ +void ald_ebi_nand_disable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + if (bank == EBI_NAND_BANK2) + CLEAR_BIT(dev->STAR2, it); + else + CLEAR_BIT(dev->STAR3, it); +} + +/** + * @brief Enables dynamically EBI_NAND ECC feature. + * @param dev: Pointer to NAND device instance + * @param bank: NAND bank number + * @retval None + */ +void ald_ebi_nand_ecc_enable(EBI_NAND_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + /* Enable ECC feature */ + if (bank == EBI_NAND_BANK2) + SET_BIT(dev->PCTRLR2, EBI_PCTRLRx_ECCEN_MSK); + else + SET_BIT(dev->PCTRLR3, EBI_PCTRLRx_ECCEN_MSK); +} + +/** + * @brief Disables dynamically EBI_NAND ECC feature. + * @param dev: Pointer to NAND device instance + * @param bank: NAND bank number + * @retval None + */ +void ald_ebi_nand_ecc_disable(EBI_NAND_TypeDef *dev, uint32_t bank) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + /* Disable ECC feature */ + if (bank == EBI_NAND_BANK2) + CLEAR_BIT(dev->PCTRLR2, EBI_PCTRLRx_ECCEN_MSK); + else + CLEAR_BIT(dev->PCTRLR3, EBI_PCTRLRx_ECCEN_MSK); +} + +/** + * @brief Disables dynamically EBI_NAND ECC feature. + * @param dev: Pointer to NAND device instance + * @param val: Pointer to ECC value + * @param bank: NAND bank number + * @param timeout: Timeout wait value + * @retval ALD status + */ +ald_status_t ald_ebi_nand_get_ecc(EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout) +{ + uint32_t tick; + + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + tick = ald_get_tick(); + + /* Wait until FIFO is empty */ + while (ald_ebi_nand_get_flag(dev, bank, EBI_FLAG_FEMPT) == RESET) { + if (timeout != ALD_MAX_DELAY) { + if ((timeout == 0U) || ((ald_get_tick() - tick) > timeout)) + return TIMEOUT; + } + } + + if (bank == EBI_NAND_BANK2) + *val = (uint32_t)dev->ECCRESULT2; + else + *val = (uint32_t)dev->ECCRESULT3; + + return OK; +} + +/** + * @brief Get flag status of the NAND device. + * @param dev: EBI_NAND Instance + * @param bank : EBI_NAND Bank + * @param flag : EBI_NAND flag + * This parameter can be any combination of the following values: + * @arg EBI_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg EBI_FLAG_LEVEL: Interrupt level edge flag. + * @arg EBI_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg EBI_FLAG_FEMPT: FIFO empty flag. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_ebi_nand_get_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + if (bank == EBI_NAND_BANK2) { + if (dev->STAR2 & flag) + return SET; + } else { + if (dev->STAR3 & flag) + return SET; + } + + return RESET; +} + +/** + * @brief Clear flag status of the NAND device. + * @param dev: EBI_NAND Instance + * @param bank: EBI_NAND Bank + * @param flag: EBI_NAND flag + * This parameter can be any combination of the following values: + * @arg EBI_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg EBI_FLAG_LEVEL: Interrupt level edge flag. + * @arg EBI_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg EBI_FLAG_FEMPT: FIFO empty flag. + * @retval None + */ +void ald_ebi_nand_clear_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag) +{ + assert_param(IS_EBI_NAND_DEVICE(dev)); + assert_param(IS_EBI_NAND_BANK(bank)); + + /* Enable ECC feature */ + if (bank == EBI_NAND_BANK2) + CLEAR_BIT(dev->STAR2, flag); + else + CLEAR_BIT(dev->STAR3, flag); +} +/** + * @} + */ + +/** @defgroup EBI_Public_Functions_Group5 LCD initialize functions + * @brief LCD initialize functions + * @{ + */ +/** + * @brief Initializes the EBI_LCD device according to the specified + * control parameters in the nor_lcd_handle_t + * @param hlcd: Pointer to LCD device instance + * @retval None + */ +void ald_ebi_lcd_init(ebi_lcd_handle_t *hlcd) +{ + assert_param(IS_EBI_LCD_DEVICE(hlcd->inst)); + assert_param(IS_EBI_BANK_NUMBER(hlcd->init.bank)); + assert_param(IS_EBI_HORIZONTAL_SYNCH(hlcd->init.h_polarity)); + assert_param(IS_EBI_VERTICAL_SYNCH(hlcd->init.v_polarity)); + assert_param(IS_EBI_DATA_ENABLE(hlcd->init.data_polarity)); + assert_param(IS_EBI_LCD_ENABLE(hlcd->init.enable)); + assert_param(IS_EBI_DATA_CLOCK(hlcd->init.clk_polarity)); + assert_param(IS_EBI_LCD_DATASETUP_TIME(hlcd->init.setup)); + assert_param(IS_EBI_HYSNC_PULSE_WIDTH(hlcd->init.h_width)); + assert_param(IS_EBI_VSYNC_PULSE_WIDTH(hlcd->init.v_width)); + assert_param(IS_EBI_FRAME_LINE_NUMBER(hlcd->init.nr_line)); + assert_param(IS_EBI_FRAME_PIXEL_NUMBER(hlcd->init.nr_pixel)); + + MODIFY_REG(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4], LCDCTRL_CLEAR_MASK, + ((uint32_t)hlcd->init.h_polarity | + (uint32_t)hlcd->init.v_polarity | + hlcd->init.data_polarity | + hlcd->init.enable | + hlcd->init.clk_polarity | + hlcd->init.setup << EBI_LCDCTRLx_DATASETUP_POSS | + hlcd->init.h_width << EBI_LCDCTRLx_VSYNCWID_POSS | + hlcd->init.v_width << EBI_LCDCTRLx_HSYNCWID_POSS)); + + WRITE_REG(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4 + 1], + (hlcd->init.nr_line << EBI_LCDSTx_LINECNT_POSS | + hlcd->init.nr_pixel << EBI_LCDSTx_PXLCNT_POSS)); +} + +/** + * @brief Reset the EBI_LCD + * @param hlcd: Pointer to LCD device instance + * @retval None + */ +void ald_ebi_lcd_reset(ebi_lcd_handle_t *hlcd) +{ + assert_param(IS_EBI_LCD_RESET(hlcd->init.reset)); + assert_param(IS_EBI_BANK_NUMBER(hlcd->init.bank)); + + SET_BIT(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4], hlcd->init.reset); +} + +/** + * @} + */ +/** + * @} + */ +#endif +/** + * @} + */ +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_flash.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_flash.c new file mode 100644 index 00000000..7a4ed86e --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_flash.c @@ -0,0 +1,243 @@ +/** + ********************************************************************************* + * + * @file ald_flash.c + * @brief FLASH module driver. + * + * @version V1.0 + * @date 17 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 17 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + * @verbatim + ============================================================================== + ##### FLASH Peripheral features ##### + ============================================================================== + [..] + Base address is 0x00000000 + + [..] + FLASH have just one programme mode , word programme. + word programme can programme 8 bytes once ; + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provide private functions for ald_flash_ext.c to use + @endverbatim + */ + +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH module driver + * @{ + */ + +#ifdef ALD_FLASH + +#if defined ( __ICCARM__ ) +#define __RAMFUNC __ramfunc +#else +#define __RAMFUNC +#endif + +/** @defgroup Flash_Private_Variables Flash Private Variables + * @{ + */ +/* global variable*/ +static op_cmd_type OP_CMD = OP_FLASH; +/** + * @} + */ + +/** @defgroup Flash_Private_Functions Flash Private Functions + * @brief Flash Private functions + * @{ + */ +/** + * @brief Unlock the flash. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC static ald_status_t flash_unlock(void) +{ + uint16_t i; + uint16_t op_cmd = OP_CMD; + + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + return ERROR; + + FLASH_REG_UNLOCK(); + FLASH_IAP_ENABLE(); + FLASH_REQ(); + + for (i = 0; i < 0xFFFF; i++) { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)) + break; + } + + return i == 0xFFFF ? ERROR : OK; +} + +/** + * @brief Lock the flash. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC static ald_status_t flash_lock(void) +{ + uint16_t i; + uint16_t op_cmd = OP_CMD; + + FLASH_REG_UNLOCK(); + WRITE_REG(MSC->FLASHCR, 0x0); + + for (i = 0; i < 0xFFFF; i++) { + if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))) + break; + } + + return i == 0xFFFF ? ERROR : OK; +} + +/** + * @brief Erase one page. + * @param addr: The erased page's address + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC ald_status_t flash_page_erase(uint32_t addr) +{ + uint32_t i; + uint16_t op_cmd = OP_CMD; + + if (flash_unlock() != OK) + goto end; + + if (op_cmd == OP_FLASH) { + CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); + } + else { + SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS); + } + + WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE); + + for (i = 0; i < 0xFFFF; i++) { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + continue; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK)) + goto end; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK)) + goto end; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK)) + break; + } + + if (i == 0xFFFF) + goto end; + + if (flash_lock() == ERROR) + goto end; + + return OK; +end: + flash_lock(); + return ERROR; +} + +/** + * @brief Programme a word. + * @param addr: The word's address, it is must word align. + * @param data: The 8 bytes data be write. + * @param len: The number of data be write. + * @param fifo: Choose if use fifo. + * @retval Status, see @ref ald_status_t. + */ +__RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo) +{ + uint16_t i = 0; + uint16_t prog_len; + uint32_t *p_data = data; + uint16_t op_cmd = OP_CMD; + + if (flash_unlock() != OK) + goto end; + + if (op_cmd == OP_FLASH) + CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + else + SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK); + + MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS); + MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS); + + for (prog_len = 0; prog_len < len; prog_len++) { + if (fifo) { + WRITE_REG(MSC->FLASHFIFO, p_data[0]); + WRITE_REG(MSC->FLASHFIFO, p_data[1]); + } + else { + WRITE_REG(MSC->FLASHDL, p_data[0]); + WRITE_REG(MSC->FLASHDH, p_data[1]); + WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP); + } + + p_data += 2; + + for (i = 0; i < 0xFFFF; i++) { + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK)) + continue; + if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK)) + break; + } + } + if (i == 0xFFFF) + goto end; + + if (flash_lock() == ERROR) + goto end; + + return OK; +end: + flash_lock(); + return ERROR; +} +/** + * @} + */ + +#endif + +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_flash_ext.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_flash_ext.c new file mode 100644 index 00000000..d08b0e19 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_flash_ext.c @@ -0,0 +1,343 @@ +/** + ********************************************************************************* + * + * @file ald_flash_ext.c + * @brief FLASH extra module driver. + * + * @version V1.0 + * @date 17 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 17 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + * @verbatim + ============================================================================== + ##### FLASH Peripheral features ##### + ============================================================================== + [..] + Base address is 0x00000000 + + [..] + FLASH have just one programme mode , word programme. + word programme can programme 8 bytes once ; + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) programme flash using ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len) + (++) call the function and supply all the three paraments is needs, addr means + the first address to write in this operation, buf is a pointer to the data which + need writing to flash. + + (#) erase flash using ald_flash_erase(uint32_t addr, uint16_t len) + (++) call the function and supply two paraments, addr is the first address to erase, + len is the length to erase + + (#) read flash using ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) + (++) read the flash and save to a buffer, ram_addr is the buffer's first address, + addr is the start reading address in flash, len is the length need read + + @endverbatim + */ + + +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +#ifdef ALD_FLASH + +/** @addtogroup Flash_Private_Variables + * @{ + */ +/* opration buffer*/ +static uint8_t write_buf[FLASH_PAGE_SIZE]; +/** + * @} + */ + +/** @addtogroup Flash_Private_Functions + * @{ + */ + +/** + * @brief Check whether the flash between the given address section + * have been writen, if it have been writen, return TRUE, else + * return FALSE. + * @param begin_addr: The begin address. + * @param end_addr: The end address. + * @retval The check result + * - TRUE + * - FALSE + */ +static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr) +{ + uint8_t* addr_to_read; + uint8_t value; + uint32_t index; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(begin_addr)); + assert_param(IS_FLASH_ADDRESS(end_addr)); + + addr_to_read = (uint8_t *)begin_addr; + index = begin_addr; + value = 0xFF; + + if (begin_addr > end_addr) + return FALSE; + + while (index++ <= end_addr) { + value = *addr_to_read++; + + if (value != 0xFF) + break; + } + + return value == 0xFF ? FALSE : TRUE; +} +/** + * @} + */ + +/** @defgroup Flash_Public_Functions Flash Public Functions + * @verbatim + =============================================================================== + ##### Flash operation functions ##### + =============================================================================== + [..] + This section provides functions allowing to operate flash, such as read and write. + + @endverbatim + * @{ + */ + +/** + * @brief read the specified length bytes from flash, and store to the specified area. + * @param ram_addr: the specified area to store the reading bytes. + * @param addr: the start address. + * @param len: the length to read. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len) +{ + uint32_t i; + uint32_t temp; + + assert_param(IS_4BYTES_ALIGN(ram_addr)); + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + + temp = (uint32_t)ram_addr; + + if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0)) + return ERROR; + + for (i = 0; i < len; i++) + ram_addr[i] = ((uint32_t *)addr)[i]; + + return OK; +} + +/** + * @brief Write the give bytes to the given address section. + * @param addr: The start address to write. + * @param buf: The bytes' address. + * @param len: The length to write,and multiple of 2. + * @retval Status, see @ref ald_status_t. + */ + +ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len) +{ + uint32_t index = 0; + uint32_t para = 0; + uint32_t index2 = 0; + uint32_t start_write_addr; + uint32_t end_write_addr; + uint32_t start_word_addr; + uint32_t end_word_addr; + uint16_t len_to_write; + uint32_t len_index; + type_bool_t need_erase_page; + + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + + len_to_write = len; + + __disable_irq(); + while (len_to_write > 0) { + need_erase_page = FALSE; + + for (index = 0; index < FLASH_PAGE_SIZE; index++) + write_buf[index] = 0xFF; + + start_write_addr = addr + (len - len_to_write); + end_write_addr = addr + len - 1; + end_write_addr = FLASH_PAGE_ADDR(start_write_addr) == FLASH_PAGE_ADDR(end_write_addr) + ? end_write_addr : FLASH_PAGEEND_ADDR(start_write_addr); + need_erase_page = page_have_writen(FLASH_WORD_ADDR(start_write_addr), + FLASH_WORDEND_ADDR(end_write_addr)); + + if (need_erase_page) { + if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr), + FLASH_PAGE_SIZE >> 2)) { + __enable_irq(); + return ERROR; + } + + if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr))) { + __enable_irq(); + return ERROR; + } + + para = end_write_addr & (FLASH_PAGE_SIZE - 1); + index = start_write_addr & (FLASH_PAGE_SIZE - 1); + index2 = len - len_to_write; + + while (index <= para) + write_buf[index++] = buf[index2++]; + + index2 = 0; + index = FLASH_PAGE_ADDR(start_write_addr); + len_index = FLASH_PAGE_SIZE; + } + else { + para = end_write_addr & (FLASH_PAGE_SIZE - 1); + index = start_write_addr & (FLASH_PAGE_SIZE - 1); + index2 = len - len_to_write; + + while (index <= para) + write_buf[index++] = buf[index2++]; + + start_word_addr = FLASH_WORD_ADDR(start_write_addr); + end_word_addr = FLASH_WORDEND_ADDR(end_write_addr); + index2 = (FLASH_WORD_ADDR(start_word_addr) - FLASH_PAGE_ADDR(start_word_addr)); + index = start_word_addr; + len_index = end_word_addr - start_word_addr + 1; + } + + if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO)) { + __enable_irq(); + return ERROR; + } + + len_to_write = len_to_write - (end_write_addr - start_write_addr + 1); + } + + __enable_irq(); + return OK; +} + +/** + * @brief erase The flash between the given address section. + * @param addr: The start address to erase. + * @param len: The length to erase. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_flash_erase(uint32_t addr, uint16_t len) +{ + uint32_t index; + int32_t para; + int32_t start_erase_addr; + int32_t end_erase_addr; + uint16_t len_not_erase; + uint32_t len_index; + type_bool_t page_need_save; + + assert_param(IS_FLASH_ADDRESS(addr)); + assert_param(IS_FLASH_ADDRESS(addr + len - 1)); + + len_not_erase = len; + + __disable_irq(); + while (len_not_erase > 0) { + page_need_save = FALSE; + + start_erase_addr = addr + len - len_not_erase; + end_erase_addr = addr + len - 1; + end_erase_addr = (FLASH_PAGE_ADDR(start_erase_addr) == FLASH_PAGE_ADDR(end_erase_addr)) + ? end_erase_addr : FLASH_PAGEEND_ADDR(start_erase_addr); + + if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr)) { + if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1))) + page_need_save = TRUE; + } + if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) { + if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr))) + page_need_save = TRUE; + } + + if (page_need_save) { + if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr), + FLASH_PAGE_SIZE >> 2)) { + __enable_irq(); + return ERROR; + } + } + + if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr))) { + __enable_irq(); + return ERROR; + } + + if (page_need_save) { + para = end_erase_addr & (FLASH_PAGE_SIZE - 1); + index = start_erase_addr & (FLASH_PAGE_SIZE - 1); + + while (index <= para) + write_buf[index++] = 0xFF; + + index = FLASH_PAGE_ADDR(start_erase_addr); + len_index = FLASH_PAGE_SIZE; + if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) { + __enable_irq(); + return ERROR; + } + } + len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1); + } + + __enable_irq(); + return OK; +} +/** + * @} + */ + + +#endif + +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_gpio.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_gpio.c new file mode 100644 index 00000000..0e742055 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_gpio.c @@ -0,0 +1,644 @@ +/** + ********************************************************************************* + * + * @file ald_gpio.c + * @brief GPIO module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization functions + * + IO operation functions + * + Control functions + * + * @version V1.0 + * @date 07 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + * @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each + port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software + in several modes: + (+) Input mode + (+) Analog mode + (+) Output mode + (+) External interrupt/event lines + + [..] + During and just after reset, the external interrupt lines are not active and + the I/O ports are configured Analog mode. + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + [..] + In Output mode, each IO can be configured on open-drain or push-pull + type and the Output driver can be selected depending on ODRV register. + + [..] + In Input mode, each IO can select filter function. + + [..] + Each IO can select TTL or SMIT type. + + [..] + Each IO have up to eight functions, user can configure the functions depend + on the user's environment. + + [..] + Each IO can be locked. Once locked, uesr can only change the output data. + Only when the CPU reset to unlock the GPIO port. + + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + Each input line can be independently configured to select the type (event or interrupt) and + the corresponding trigger event (rising or falling). Each line can also masked + independently. A pending register maintains the status line of the interrupt requests. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO clock. + + (#) Configure the GPIO pin(s) using ald_gpio_init(). + (++) Configure the IO mode using "mode" member from gpio_init_t structure + (++) Activate Pull-up, Pull-down resistor using "pupd" member from gpio_init_t + structure. + (++) In Output mode, configured on open-drain or push-pull using "odos" + member from gpio_init_t structure. + (++) In Output mode, configured output driver using "odrv" member + from gpio_init_t structure. + (++) In Input mode, configured filter function using "flt" member + from gpio_init_t structure. + (++) Configured type using "type" member from gpio_init_t structure. + (++) Configured functions using "func" member from gpio_init_t structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + + (#) Configure the GPIO pin(s) using ald_gpio_init_default(). + (++) Configure GPIO pin using default param: + init.mode = GPIO_MODE_OUTPUT; + init.odos = GPIO_PUSH_PULL; + init.pupd = GPIO_PUSH_UP; + init.podrv = GPIO_OUT_DRIVE_6; + init.nodrv = GPIO_OUT_DRIVE_6; + init.flt = GPIO_FILTER_DISABLE; + init.type = GPIO_TYPE_CMOS; + init.func = GPIO_FUNC_1; + + (#) In case of external interrupt/event mode selection, user need invoke + ald_gpio_exti_init() to configure some param. And then invoke + ald_gpio_exti_interrupt_config() to enable/disable external interrupt/event. + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using NVIC_SetPriority() and enable it using + NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use GPIO_read_pin(). + + (#) To set/reset the level of a pin configured in output mode use + ald_gpio_write_pin()/ald_gpio_toggle_pin(). + + (#) To lock pin configuration until next reset use ald_gpio_lock_pin(). + + (#) Configure external interrupt mode and enable/disable using + ald_gpio_exti_interrupt_config(). + + (#) Get external interrupt flag status using ald_gpio_exti_get_flag_status(). + + (#) Clear pending external interrupt flag status using + ald_gpio_exti_clear_flag_status(). + + @endverbatim + */ + +#include "ald_conf.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO module driver + * @{ + */ + +#ifdef ALD_GPIO + +/** @defgroup GPIO_Public_Functions GPIO Public Functions + * @{ + */ + +/** @defgroup GPIO_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the GPIOs or external + interrupt to be ready for use. + + @endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified + * parameters in the gpio_init_t. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: The pin which need to initialize. + * @param init: Pointer to a gpio_init_t structure that can contains + * the configuration information for the specified parameters. + * @retval None + */ +void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init) +{ + uint32_t i, pos, mask, tmp; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_GPIO_MODE(init->mode)); + assert_param(IS_GPIO_ODOS(init->odos)); + assert_param(IS_GPIO_PUPD(init->pupd)); + assert_param(IS_GPIO_ODRV(init->podrv)); + assert_param(IS_GPIO_ODRV(init->nodrv)); + assert_param(IS_GPIO_FLT(init->flt)); + assert_param(IS_GPIO_TYPE(init->type)); + assert_param(IS_GPIO_FUNC(init->func)); + + for (i = 0; i < 16; ++i) { + if (((pin >> i) & 0x1) == 0) + continue; + + /* Get position and 2-bits mask */ + pos = i << 1; + mask = 0x3 << pos; + + /* Set PIN mode */ + tmp = READ_REG(GPIOx->MODE); + tmp &= ~mask; + tmp |= (init->mode << pos); + WRITE_REG(GPIOx->MODE, tmp); + + /* Set PIN open-drain or push-pull */ + tmp = READ_REG(GPIOx->ODOS); + tmp &= ~mask; + tmp |= (init->odos << pos); + WRITE_REG(GPIOx->ODOS, tmp); + + /* Set PIN push-up or/and push-down */ + tmp = READ_REG(GPIOx->PUPD); + tmp &= ~mask; + tmp |= (init->pupd << pos); + WRITE_REG(GPIOx->PUPD, tmp); + + /* Set PIN output P-MOS driver */ + tmp = READ_REG(GPIOx->PODRV); + tmp &= ~mask; + tmp |= (init->podrv << pos); + WRITE_REG(GPIOx->PODRV, tmp); + + /* Set PIN output N-MOS driver */ + tmp = READ_REG(GPIOx->NODRV); + tmp &= ~mask; + tmp |= (init->nodrv << pos); + WRITE_REG(GPIOx->NODRV, tmp); + + /* Get position and 1-bit mask */ + pos = i; + mask = 0x1 << pos; + + /* Set PIN filter enable or disable */ + tmp = READ_REG(GPIOx->FLT); + tmp &= ~mask; + tmp |= (init->flt << pos); + WRITE_REG(GPIOx->FLT, tmp); + + /* Set PIN type ttl or smit */ + tmp = READ_REG(GPIOx->TYPE); + tmp &= ~mask; + tmp |= (init->type << pos); + WRITE_REG(GPIOx->TYPE, tmp); + + /* Configure PIN function */ + pos = i < 8 ? (i << 2) : ((i - 8) << 2); + mask = 0xF << pos; + tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1); + tmp &= ~mask; + tmp |= (init->func << pos); + i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp); + } + + return; +} + +/** + * @brief Initialize the GPIOx peripheral using the default parameters. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: The pin which need to initialize. + * @retval None + */ +void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + gpio_init_t init; + + /* Fill GPIO_init_t structure with default parameter */ + init.mode = GPIO_MODE_OUTPUT; + init.odos = GPIO_PUSH_PULL; + init.pupd = GPIO_PUSH_UP; + init.podrv = GPIO_OUT_DRIVE_6; + init.nodrv = GPIO_OUT_DRIVE_6; + init.flt = GPIO_FILTER_DISABLE; + init.type = GPIO_TYPE_CMOS; + init.func = GPIO_FUNC_1; + + ald_gpio_init(GPIOx, pin, &init); + return; +} + +/** + * @brief Sets GPIO function to default(func0). + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @retval None + */ +void ald_gpio_func_default(GPIO_TypeDef *GPIOx) +{ + WRITE_REG(GPIOx->FUNC0, 0x00); + WRITE_REG(GPIOx->FUNC1, 0x00); + + return; +} + +/** + * @brief Initialize the external interrupt according to the specified + * parameters in the exti_init_t. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: The pin which need to initialize. + * @param init: Pointer to a exti_init_t structure that can contains + * the configuration information for the specified parameters. + * @retval None + */ +void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init) +{ + uint8_t i; + uint8_t port; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_FUNC_STATE(init->filter)); + assert_param(IS_EXTI_FLTCKS_TYPE(init->cks)); + + /* Get GPIO port */ + if (GPIOx == GPIOA) + port = 0x0; + else if (GPIOx == GPIOB) + port = 0x1; + else if (GPIOx == GPIOC) + port = 2; + else if (GPIOx == GPIOD) + port = 3; + else if (GPIOx == GPIOE) + port = 4; + else if (GPIOx == GPIOF) + port = 5; + else if (GPIOx == GPIOG) + port = 6; + else if (GPIOx == GPIOH) + port = 7; + else + port = 0; + + /* Get Pin index */ + for (i = 0; i < 16; ++i) { + if (((pin >> i) & 0x1) == 0x1) + break; + } + + /* Select external interrupt line */ + if (i <= 7) { + EXTI->EXTIPSR0 &= ~(0x7U << (i * 4)); + EXTI->EXTIPSR0 |= (port << (i * 4)); + } + else { + i -= 8; + EXTI->EXTIPSR1 &= ~(0x7U << (i * 4)); + EXTI->EXTIPSR1 |= (port << (i * 4)); + } + + /* Configure filter parameter */ + if (init->filter == ENABLE) { + SET_BIT(EXTI->EXTIFLTCR, pin); + MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTCKS_MSK, init->cks << GPIO_EXTIFLTCR_FLTCKS_POSS); + MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS); + } + else { + CLEAR_BIT(EXTI->EXTIFLTCR, pin); + } + + return; +} +/** + * @} + */ + +/** @defgroup GPIO_Public_Functions_Group2 IO operation functions + * @brief GPIO Read and Write + * + @verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the GPIOs. + + @endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: Specifies the pin to read. + * @retval The input pin value + */ +uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + if (READ_BIT(GPIOx->DIN, pin)) + return 1; + else + return 0; +} + +/** + * @brief Set or clear the select Pin data. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: The specified pin to be written. + * @param val: The specifies value to be written. + * @retval None + */ +void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + if ((val & (0x01)) == 0x00) + GPIOx->BSRR = pin << 16U; + else + GPIOx->BSRR = pin; + + return; +} + +/** + * @brief Turn over the select data. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: Specifies the pin to turn over. + * @retval None + */ +void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + WRITE_REG(GPIOx->BIR, pin); + return; +} + +/** + * @brief Turn over the direction. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: Specifies the pin to turn over. + * @retval None + */ +void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + uint32_t i, pos, mask, tmp, value; + + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + for (i = 0; i < 16; ++i) { + if (((pin >> i) & 0x1) == 0) + continue; + + /* Get position and 2-bits mask */ + pos = i << 1; + mask = 0x3 << pos; + + /* Get the new direction */ + tmp = READ_REG(GPIOx->MODE); + value = (tmp >> pos) & 0x3; + + if ((value == 2) || (value == 3)) + value = 1; + else if (value == 1) { + value = 2; + } + else { + continue; /* do nothing */ + } + + /* Set PIN mode */ + tmp &= ~mask; + tmp |= (value << pos); + WRITE_REG(GPIOx->MODE, tmp); + } + + return; +} + +/** + * @brief Lock the GPIO prot. Once locked, can + * only change the output data. Only when the CPU + * reset to unlock the GPIO port. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param pin: The specified Pin to be written. + * @retval None + */ +void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + assert_param(IS_GPIO_PIN(pin)); + + MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, UNLOCK_KEY << GPIO_LOCK_KEY_POSS); + WRITE_REG(GPIOx->LOCK, pin); + + return; +} + +/** + * @brief Read the specified input port pin. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @retval The value; + */ +uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + + return READ_REG(GPIOx->DIN); +} + +/** + * @brief Set or clear the select Pin data. + * @param GPIOx: Where x can be (A--H) to select the GPIO peripheral. + * @param val: The specifies value to be written. + * @retval None + */ +void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val) +{ + assert_param(IS_GPIO_PORT(GPIOx)); + + WRITE_REG(GPIOx->DOUT, val); + return; +} +/** + * @} + */ + +/** @defgroup GPIO_Public_Functions_Group3 Control functions + * @brief EXTI Control functions + * + @verbatim + =============================================================================== + ##### Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to + control external interrupt. + + @endverbatim + * @{ + */ + +/** + * @brief Configure the interrupt according to the specified parameter. + * @param pin: The Pin which need to configure. + * @param style: External interrupt trigger style. + * @param status: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status) +{ + assert_param(IS_GPIO_PIN(pin)); + assert_param(IS_TRIGGER_STYLE(style)); + assert_param(IS_FUNC_STATE(status)); + + if (status == ENABLE) { + if (style == EXTI_TRIGGER_RISING_EDGE) { + SET_BIT(EXTI->EXTIRER, pin); + } + else if (style == EXTI_TRIGGER_TRAILING_EDGE) { + SET_BIT(EXTI->EXTIFER, pin); + } + else if (style == EXTI_TRIGGER_BOTH_EDGE) { + SET_BIT(EXTI->EXTIRER, pin); + SET_BIT(EXTI->EXTIFER, pin); + } + else { + ; /* do nothing */ + } + + WRITE_REG(EXTI->EXTICFR, 0xffff); + SET_BIT(EXTI->EXTIEN, pin); + } + else { + if (style == EXTI_TRIGGER_RISING_EDGE) { + CLEAR_BIT(EXTI->EXTIRER, pin); + } + else if (style == EXTI_TRIGGER_TRAILING_EDGE) { + CLEAR_BIT(EXTI->EXTIFER, pin); + } + else if (style == EXTI_TRIGGER_BOTH_EDGE) { + CLEAR_BIT(EXTI->EXTIRER, pin); + CLEAR_BIT(EXTI->EXTIFER, pin); + } + else { + ; /* do nothing */ + } + + CLEAR_BIT(EXTI->EXTIEN, pin); + } + + return; +} + +/** + * @brief Get the Flag about external interrupt. + * @param pin: The pin which belong to external interrupt. + * @retval Flag status + * - SET + * - RESET + */ +flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin) +{ + assert_param(IS_GPIO_PIN(pin)); + + if (READ_BIT(EXTI->EXTIFLAG, pin)) + return SET; + + return RESET; +} + +/** + * @brief Clear the external interrupt flag. + * @param pin: The pin which belong to external interrupt. + * @retval None + */ +void ald_gpio_exti_clear_flag_status(uint16_t pin) +{ + assert_param(IS_GPIO_PIN(pin)); + + WRITE_REG(EXTI->EXTICFR, pin); + return; +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* ALD_GPIO */ +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_i2c.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_i2c.c new file mode 100644 index 00000000..fa32ce32 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_i2c.c @@ -0,0 +1,2769 @@ +/** + ********************************************************************************* + * + * @file ald_i2c.c + * @brief I2C module driver. + * + * @version V1.0 + * @date 15 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 15 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The I2C driver can be used as follows: + + (#) Declare a i2c_handle_t handle structure, for example: + i2c_handle_t hperh; + + (#) Configure the Communication Speed, Addressing mode, Own Address1, + Dual Addressing mode, Own Address2, General call and Nostretch mode in the hperh init structure. + + (#) Initialize the I2C registers by calling the ald_i2c_init(). + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using ald_i2c_master_send() + (+) Receive in master mode an amount of data in blocking mode using ald_i2c_master_recv() + (+) Transmit in slave mode an amount of data in blocking mode using ald_i2c_slave_send() + (+) Receive in slave mode an amount of data in blocking mode using ald_i2c_slave_recv() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using ald_i2c_mem_write() + (+) Read an amount of data in blocking mode from a specific memory address using ald_i2c_mem_read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) The I2C interrupts should have the highest priority in the application in order + to make them uninterruptible. + (+) Transmit in master mode an amount of data in non-blocking mode using ald_i2c_master_send_by_it() + (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_tx_cplt_cbk() + (+) Receive in master mode an amount of data in non-blocking mode using ald_i2c_master_recv_by_it() + (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_rx_cplt_cbk() + (+) Transmit in slave mode an amount of data in non-blocking mode using ald_i2c_slave_send_by_it() + (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_tx_cplt_cbk() + (+) Receive in slave mode an amount of data in non-blocking mode using ald_i2c_slave_recv_by_it() + (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) The I2C interrupts should have the highest priority in the application in order + to make them uninterruptible. + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + ald_i2c_mem_write_by_it() + (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_tx_cplt_cbk() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + ald_i2c_mem_read_by_it() + (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + ald_i2c_master_send_by_dma() + (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_tx_cplt_cbk() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + ald_i2c_master_recv_by_dma() + (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->master_rx_cplt_cbk() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + ald_i2c_slave_send_by_dma() + (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_tx_cplt_cbk() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + ald_i2c_slave_recv_by_dma() + (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->slave_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + ald_i2c_mem_write_by_dma() + (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_tx_cplt_cbk() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + ald_i2c_mem_read_by_dma() + (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->mem_rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_callback() function is executed and user can + add his own code by customization of function pointer hperh->error_callback() + + + *** I2C ald_status_t driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C ald_status_t driver. + + (+) __I2C_ENABLE: Enable the I2C peripheral + (+) __I2C_DISABLE: Disable the I2C peripheral + (+) I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) I2C_DISABLE_IT: Disable the specified I2C interrupt + (@) You can refer to the I2C ald_status_t driver header file for more useful macros + + *** I2C Workarounds linked to Silicon Limitation *** + ==================================================== + [..] + Below the list of all silicon limitations implemented for library on our product. + (@) See ErrataSheet to know full silicon limitation list of your product. + + (#) Workarounds Implemented inside I2C library + (##) Wrong data read into data register (Polling and Interrupt mode) + (##) Start cannot be generated after a misplaced Stop + (##) Some software events must be managed before the current byte is being transferred: + Workaround: Use DMA in general, except when the Master is receiving a single byte. + For Interupt mode, I2C should have the highest priority in the application. + (##) Mismatch on the "Setup time for a repeated Start condition" timing parameter: + Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if + supported by the slave. + (##) Data valid time (tVD;DAT) violated without the OVR flag being set: + Workaround: If the slave device allows it, use the clock stretching mechanism + by programming no_stretch = I2C_NOSTRETCH_DISABLE in ald_i2c_init. + + @endverbatim + ********************************************************************************* + */ + +#include "ald_conf.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C module driver + * @{ + */ + +#ifdef ALD_I2C + +/** @addtogroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +#define I2C_TIMEOUT_FLAG (10) +#define I2C_TIMEOUT_ADDR_SLAVE (10) +#define I2C_TIMEOUT_BUSY_FLAG (10) +#define I2C_MAX_DELAY 0xFFFFFFFF + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions I2C Private Functions + * @{ + */ + +#ifdef ALD_DMA +static void i2c_dma_master_send_cplt(void *argv); +static void i2c_dma_master_recv_cplt(void *argv); +static void i2c_dma_slave_send_cplt(void *argv); +static void i2c_dma_slave_recv_cplt(void *argv); +static void i2c_dma_mem_send_cplt(void *argv); +static void i2c_dma_mem_recv_cplt(void *argv); +static void i2c_dma_error(void *argv); +static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + uint16_t add_size, uint32_t timeout); +#endif +static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout); +static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout); +static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + uint16_t add_size, uint32_t timeout); +static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, + flag_status_t status, uint32_t timeout); +static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, uint32_t flag, uint32_t timeout); +static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout); +static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout); +static ald_status_t i2c_master_send_tc(i2c_handle_t *hperh); +static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh); +static ald_status_t i2c_master_recv_tc(i2c_handle_t *hperh); +static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh); +static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh); +static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh); +static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh); + +/** + * @} + */ + +/** @defgroup I2C_Public_Functions I2C Public functions + * @{ + */ + +/** @defgroup I2C_Public_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialiaze the I2Cx peripheral: + + (+) Call the function ald_i2c_init() to configure the selected device with + the selected configuration: + (++) Communication Speed + (++) Addressing mode + (++) Own Address 1 + (++) Dual Addressing mode + (++) Own Address 2 + (++) General call mode + (++) Nostretch mode + + (+) Call the function ald_i2c_reset() to restore the default configuration + of the selected I2Cx periperal. + +@endverbatim + * @{ + */ + +/** + * @brief I2C Configuration Speed function. + * @param hperh: Pointer to a i2c_handle_t structure that contains. + * the configuration information for the I2C speed. + * @param clk: I2C Peripheral bus clock + * @retval Status, see @ref ald_status_t. + */ +ald_status_t i2c_speed_init(i2c_handle_t *hperh, uint32_t clk) +{ + int32_t t_scl, t_pre, tmp; + + if (hperh->init.module == I2C_MODULE_SLAVE) { + hperh->init.clk_speed = 450000UL; + } + + if (hperh->init.clk_speed <= 100000UL) { + tmp = clk / 4000000UL; + clk = (tmp >= 16UL) ? (clk >> 4UL) : 4000000UL; + } + else { + tmp = clk / 8000000UL; + clk = (tmp >= 16UL) ? (clk >> 4UL) : 8000000UL; + } + + tmp = tmp >= 16UL ? 15UL : tmp; + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_PRESC_MSK, tmp << I2C_TIMINGR_PRESC_POSS); + + t_scl = 1000000000 / hperh->init.clk_speed; + t_pre = 1000000000 / clk; + + tmp = (t_scl * 10) / (t_pre << 1UL); + tmp = (tmp % 10) >= 5 ? (tmp / 10 + 1) : tmp / 10; + tmp = tmp >= 255UL ? 255UL : tmp; + /* SCLDEL+1+SDADEL+0+SCLH+1 */ + if ((long)(t_scl - ((tmp + 3UL) * t_pre)) < 0) + return ERROR; + + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLL_MSK, (tmp - 1UL) << I2C_TIMINGR_SCLL_POSS); + if (hperh->init.clk_speed > 100000UL) { + if ((tmp - 1UL) > 3UL) { + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, ((tmp - 1UL) / 3UL) << I2C_TIMINGR_SCLDEL_POSS); + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SDADEL_MSK, ((((tmp - 1UL) / 3UL) >= 3) ? 3 : (((tmp - 1UL) / 3UL) % 3)) << I2C_TIMINGR_SDADEL_POSS); + } + else { + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, 1UL << I2C_TIMINGR_SCLDEL_POSS); + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SDADEL_MSK, 1UL << I2C_TIMINGR_SDADEL_POSS); + } + } + else { + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SDADEL_MSK, 2UL << I2C_TIMINGR_SDADEL_POSS); + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, 4UL << I2C_TIMINGR_SCLDEL_POSS); + } + + tmp = t_scl - (tmp + READ_BITS(hperh->perh->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, I2C_TIMINGR_SCLDEL_POSS) + \ + READ_BITS(hperh->perh->TIMINGR, I2C_TIMINGR_SDADEL_MSK, I2C_TIMINGR_SDADEL_POSS) + 1UL) * t_pre; + if (tmp < 0) + return ERROR; + + tmp = (tmp * 10) / t_pre; + tmp = (tmp % 10) >= 5 ? (tmp / 10 + 1) : tmp / 10; + tmp = tmp >= 255UL ? 255UL : tmp; + /* tscll >= 3*tsclh */ + tmp = (tmp - 1) <= (READ_BITS(hperh->perh->TIMINGR, I2C_TIMINGR_SCLL_MSK, I2C_TIMINGR_SCLL_POSS) / 3) ? (READ_BITS(hperh->perh->TIMINGR, I2C_TIMINGR_SCLL_MSK, I2C_TIMINGR_SCLL_POSS) / 3) + 1: tmp; + MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLH_MSK, (tmp - 1UL) << I2C_TIMINGR_SCLH_POSS); + + return OK; +} +/** + * @brief Initializes the I2C according to the specified parameters + * in the i2c_init_t and initialize the associated handle. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_init(i2c_handle_t *hperh) +{ + uint32_t freqrange = ald_cmu_get_pclk1_clock(); + + if (hperh == NULL) + return ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_CLOCK_SPEED(hperh->init.clk_speed)); + assert_param(IS_I2C_ADDRESSING_MODE(hperh->init.addr_mode)); + assert_param(IS_I2C_GENERAL_CALL(hperh->init.general_call)); + assert_param(IS_I2C_NO_STRETCH(hperh->init.no_stretch)); + assert_param(IS_I2C_MODULE(hperh->init.module)); + + if (hperh->state == I2C_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = I2C_STATE_BUSY; + + I2C_DISABLE(hperh); + + if (OK != i2c_speed_init(hperh, freqrange)) + return ERROR; + + MODIFY_REG(hperh->perh->CON1, I2C_CON1_NOSTRETCH_MSK, (hperh->init.no_stretch) << I2C_CON1_NOSTRETCH_POS); + MODIFY_REG(hperh->perh->CON1, I2C_CON1_GCEN_MSK, (hperh->init.general_call) << I2C_CON1_GCEN_POS); + + if (hperh->init.dual_addr == I2C_DUALADDR_ENABLE) { + CLEAR_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK); + MODIFY_REG(hperh->perh->ADDR1, I2C_ADDR1_OA1_MSK, (hperh->init.own_addr1 & 0x3FF) << I2C_ADDR1_OA1_POSS); + SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK); + + CLEAR_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK); + MODIFY_REG(hperh->perh->ADDR2, I2C_ADDR2_OA2_MSK, (hperh->init.own_addr2 & 0x7F) << I2C_ADDR2_OA2_POSS); + SET_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK); + } else { + if (hperh->init.addr_mode == I2C_ADDR_10BIT) { + CLEAR_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK); + SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1MODE_MSK); + MODIFY_REG(hperh->perh->ADDR1, I2C_ADDR1_OA1_MSK, (hperh->init.own_addr1 & 0x3FF) << I2C_ADDR1_OA1_POSS); + SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK); + } + else { + CLEAR_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK); + MODIFY_REG(hperh->perh->ADDR2, I2C_ADDR2_OA2_MSK, (hperh->init.own_addr2 & 0x7F) << I2C_ADDR2_OA2_POSS); + SET_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK); + } + } + + I2C_ENABLE(hperh); + + hperh->error_code = I2C_ERROR_NONE; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + return OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_reset(i2c_handle_t *hperh) +{ + if (hperh == NULL) + return ERROR; + + I2C_DISABLE(hperh); + + hperh->error_code = I2C_ERROR_NONE; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + + __UNLOCK(hperh); + + WRITE_REG(hperh->perh->CON1, 0); + WRITE_REG(hperh->perh->CON2, 0); + WRITE_REG(hperh->perh->ADDR1, 0); + WRITE_REG(hperh->perh->ADDR2, 0); + WRITE_REG(hperh->perh->TIMINGR, 0); + WRITE_REG(hperh->perh->TIMEOUTR, 0); + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + WRITE_REG(hperh->perh->IDR, I2C_FLAG_MASK); + WRITE_REG(hperh->perh->ICR, I2C_FLAG_MASK); + + I2C_ENABLE(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup I2C_Public_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) ald_i2c_master_send() + (++) ald_i2c_master_recv() + (++) ald_i2c_slave_send() + (++) ald_i2c_slave_recv() + (++) ald_i2c_mem_write() + (++) ald_i2c_mem_read() + + (#) No-Blocking mode functions with Interrupt are : + (++) ald_i2c_master_send_by_it() + (++) ald_i2c_master_recv_by_it() + (++) ald_i2c_slave_send_by_it() + (++) ald_i2c_slave_recv_by_it() + (++) ald_i2c_mem_write_by_it() + (++) ald_i2c_mem_read_by_it() + + (#) No-Blocking mode functions with DMA are : + (++) ald_i2c_master_send_by_dma() + (++) ald_i2c_master_recv_by_dma() + (++) ald_i2c_slave_send_by_dma() + (++) ald_i2c_slave_recv_by_dma() + (++) ald_i2c_mem_write_by_dma() + (++) ald_i2c_mem_read_by_dma() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) hperh->mem_tx_cplt_cbk() + (++) hperh->mem_rx_cplt_cbk() + (++) hperh->master_tx_cplt_cbk() + (++) hperh->master_rx_cplt_cbk() + (++) hperh->slave_tx_cplt_cbk() + (++) hperh->slave_rx_cplt_cbk() + (++) hperh->error_callback() + +@endverbatim + * @{ + */ +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint32_t size, uint32_t timeout) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_write(hperh, dev_addr, timeout); + + if (size <= 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + while (size > 0) { + hperh->perh->TXDATA = (*buf++); + size--; + hperh->xfer_count++; + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) + goto ERROR; + + if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) { + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == OK) { + if (size > 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else { + goto ERROR; + } + } + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == SET) + goto SUCCESS; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == OK) { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + } + else { + goto ERROR; + } + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + +SUCCESS: + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t + */ + ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint32_t size, uint32_t timeout) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_read(hperh, dev_addr, timeout); + + if (size <= 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + while (size > 0) { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) + goto ERROR; + + (*buf++) = hperh->perh->RXDATA; + size--; + hperh->xfer_count++; + + if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) { + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == OK) { + if (size > 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else { + goto ERROR; + } + } + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK)) + goto SUCCESS; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + +SUCCESS: + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint8_t i = 0; + + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + MODIFY_REG(hperh->perh->FCON, I2C_FCON_TXFTH_MSK, 0x03 << I2C_FCON_TXFTH_POSS); + + for (i = 0; i < 16; i++) { + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TXF, SET, timeout) != OK) + goto ERROR; + + hperh->perh->TXDATA = (*buf++); + --size; + hperh->xfer_count++; + + if (size == 0) + break; + } + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_IT_ADDR, timeout) == ERROR) + goto ERROR; + + while (size > 0) { + if (i2c_wait_txe_to_timeout(hperh, timeout) == ERROR) + goto ERROR; + + for (i = 0; i < 8; i++) { + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TXF, SET, timeout) != OK) + goto ERROR; + + hperh->perh->TXDATA = (*buf++); + --size; + hperh->xfer_count++; + + if (size == 0) + break; + } + } + + goto SUCCESS; + +ERROR: + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + +SUCCESS: + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_count = 0; + hperh->xfer_size = size; + + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_IT_ADDR, timeout) == ERROR) + goto ERROR; + + while (size > 0) { + if (i2c_wait_rxne_to_timeout(hperh, timeout) == ERROR) + goto ERROR; + + SET_BIT(hperh->perh->CON2, I2C_CON2_ACK_UPD_MSK); + (*buf++) = hperh->perh->RXDATA; + --size; + hperh->xfer_count++; + } + + goto SUCCESS; + +ERROR: + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + +SUCCESS: + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG); + + if (size <= 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + + I2C_CLEAR_IT(hperh , I2C_IT_TXTH); + I2C_CLEAR_IT(hperh , I2C_IT_NACK); + I2C_CLEAR_IT(hperh , I2C_IT_TC); + I2C_CLEAR_IT(hperh , I2C_IT_TCR); + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + I2C_DISABLE_IT(hperh, I2C_FLAG_MASK); + I2C_ENABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK | I2C_IT_TC | I2C_IT_TCR); + + return OK; +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) ; + + if (size <= 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + + I2C_CLEAR_IT(hperh , I2C_IT_RXTH); + I2C_CLEAR_IT(hperh , I2C_IT_TCR); + I2C_CLEAR_IT(hperh , I2C_IT_TC); + + I2C_DISABLE_IT(hperh, I2C_FLAG_MASK); + I2C_ENABLE_IT(hperh, I2C_IT_RXTH | I2C_IT_TCR | I2C_IT_TC); + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + return OK; +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + + I2C_CLEAR_IT(hperh , I2C_IT_TXTH); + I2C_CLEAR_IT(hperh , I2C_IT_ADDR); + I2C_CLEAR_IT(hperh , I2C_IT_NACK); + I2C_CLEAR_IT(hperh , I2C_IT_STOP); + + I2C_DISABLE_IT(hperh, I2C_FLAG_MASK); + I2C_ENABLE_IT(hperh, I2C_IT_ADDR | I2C_IT_NACK | I2C_IT_STOP | I2C_IT_TXTH); + + return OK; +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + + I2C_CLEAR_IT(hperh , I2C_IT_RXTH); + I2C_CLEAR_IT(hperh , I2C_IT_ADDR); + I2C_CLEAR_IT(hperh , I2C_IT_STOP); + + I2C_DISABLE_IT(hperh, I2C_FLAG_MASK); + I2C_ENABLE_IT(hperh, I2C_IT_RXTH | I2C_IT_ADDR | I2C_IT_STOP); + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @note The maximum amount of data to be sent is 0xFF. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent (maximum is 0xFF) + * @param channel: DMA channel as I2C transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint8_t size, uint8_t channel) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + if (size >= 0xFF) + size = 0xFF; + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = i2c_dma_master_send_cplt; + hperh->hdmatx.cplt_arg = hperh; + hperh->hdmatx.err_cbk = i2c_dma_error; + hperh->hdmatx.err_arg = hperh; + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + hperh->hdmatx.config.size = size; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.src = (void *)hperh->p_buff; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG); + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2C receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, + uint8_t size, uint8_t channel) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + if (size >= 0xFF) + size = 0xFF; + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = i2c_dma_master_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2c_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + hperh->hdmarx.config.size = size; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG); + + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + return OK; +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2C Transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (size >= 0xFF) + size = 0xFF; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = i2c_dma_slave_send_cplt; + hperh->hdmatx.cplt_arg = hperh; + hperh->hdmatx.err_cbk = i2c_dma_error; + hperh->hdmatx.err_arg = hperh; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_IT_ADDR, I2C_TIMEOUT_ADDR_SLAVE) == ERROR) { + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + } + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + return OK; +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2C receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel) +{ + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_SLAVE; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + if (size >= 0xFF) + size = 0xFF; + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = i2c_dma_slave_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2c_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + if (i2c_wait_master_addr_to_timeout(hperh, I2C_IT_ADDR, I2C_TIMEOUT_ADDR_SLAVE) == ERROR) { + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + } + + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + return OK; +} +#endif + +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t nbyte = 0; + + assert_param(IS_I2C_MEMADD_size(add_size)); + + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + nbyte = (add_size == I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, timeout) != OK) + goto ERROR; + + if (size <= 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + while (size > 0) { + hperh->perh->TXDATA = (*buf++); + --size; + hperh->xfer_count++; + + if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) { + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == OK) { + if (size > 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else { + goto ERROR; + } + } + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) + goto ERROR; + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK)) + goto SUCCESS; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, timeout)) + goto ERROR; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + +SUCCESS: + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t nbyte = 0; + + assert_param(IS_I2C_MEMADD_size(add_size)); + + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->xfer_count = 0; + hperh->xfer_size = size; + + nbyte = (add_size == I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, timeout) != OK) + return ERROR; + + if (size <= 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + while (size > 0) { + if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK) + goto ERROR; + + (*buf++) = hperh->perh->RXDATA; + size--; + hperh->xfer_count++; + + if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) { + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, timeout) == OK) { + if (size > 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + } + else { + goto ERROR; + } + } + } + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK)) + goto SUCCESS; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + goto SUCCESS; + +ERROR: + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + +SUCCESS: + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint32_t size) +{ + uint32_t nbyte = 0; + + assert_param(IS_I2C_MEMADD_size(add_size)); + + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + nbyte = (add_size == I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + } + + if (size <= 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + I2C_CLEAR_IT(hperh , I2C_IT_TXTH); + I2C_CLEAR_IT(hperh , I2C_IT_NACK); + I2C_CLEAR_IT(hperh , I2C_IT_TC); + I2C_CLEAR_IT(hperh , I2C_IT_TCR); + + hperh->perh->TXDATA = (*hperh->p_buff++); + hperh->xfer_count++; + + I2C_DISABLE_IT(hperh, I2C_FLAG_MASK); + I2C_ENABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK | I2C_IT_TC | I2C_IT_TCR); + + return OK; +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, + i2c_addr_size_t add_size, uint8_t *buf, uint32_t size) +{ + uint32_t nbyte = 0; + + assert_param(IS_I2C_MEMADD_size(add_size)); + + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_TYPE(hperh->perh)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + nbyte = (add_size == I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + } + + if (size <= 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + I2C_CLEAR_IT(hperh , I2C_IT_RXTH); + I2C_CLEAR_IT(hperh , I2C_IT_TC); + I2C_CLEAR_IT(hperh , I2C_IT_TCR); + + I2C_ENABLE_IT(hperh, I2C_IT_RXTH | I2C_IT_TC | I2C_IT_TCR); + + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + return OK; +} + +#ifdef ALD_DMA + +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address(Maxsiz 0xFF) + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint8_t size, uint8_t channel) +{ + uint32_t nbyte = 0; + + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_MEMADD_size(add_size)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_TX; + hperh->mode = I2C_MODE_MASTER; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = 0; + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + + nbyte = (add_size == I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + return ERROR; + } + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_cbk = i2c_dma_mem_send_cplt; + hperh->hdmatx.cplt_arg = hperh; + hperh->hdmatx.err_cbk = i2c_dma_error; + hperh->hdmatx.err_arg = hperh; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.src = (void *)hperh->p_buff; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY; + hperh->hdmatx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmatx); + + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + return OK; +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param buf: Pointer to data buffer + * @param size: Amount of data to be read + * @param channel: DMA channel + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, + uint8_t *buf, uint8_t size, uint8_t channel) +{ + uint32_t nbyte = 0; + + if (hperh->state != I2C_STATE_READY) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK) + return BUSY; + + assert_param(IS_I2C_MEMADD_size(add_size)); + __LOCK(hperh); + + hperh->state = I2C_STATE_BUSY_RX; + hperh->mode = I2C_MODE_MEM; + hperh->error_code = I2C_ERROR_NONE; + hperh->p_buff = buf; + hperh->xfer_size = size; + hperh->xfer_count = size; + + SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK); + SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK); + + nbyte = (add_size == I2C_MEMADD_SIZE_8BIT) ? 1 : 2; + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) { + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + } + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_cbk = i2c_dma_mem_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2c_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1; + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&hperh->hdmarx); + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + __UNLOCK(hperh); + + return OK; +} + +#endif + +/** + * @} + */ + +/** @defgroup I2C_Public_Functions_Group3 Peripheral state and Errors functions + * @brief Peripheral state and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral state and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval ald_status_t state + */ +i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the I2C error code. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t ald_i2c_get_error(i2c_handle_t *hperh) +{ + return hperh->error_code; +} +/** + * @} + */ + +/** @defgroup I2C_Public_Functions_Group4 IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void ald_i2c_ev_irq_handler(i2c_handle_t *hperh) +{ + uint32_t size = hperh->xfer_size - hperh->xfer_count; + + /**< Transmit FIFO threshold interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TXTH) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_TXTH); + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) { + i2c_master_send_txe(hperh); + } + else if (hperh->mode == I2C_MODE_SLAVE) { + i2c_slave_send_txe(hperh); + } + } + + /**< Receive FIFO threshold interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_RXTH) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_RXTH); + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) { + i2c_master_recv_rxne(hperh); + } + else if (hperh->mode == I2C_MODE_SLAVE) { + i2c_slave_recv_rxne(hperh); + } + } + + /**< Transmit completed interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TC) == SET) { + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) { + if (I2C_MASTER_GET_DIR(hperh) == RESET) { + i2c_master_send_tc(hperh); + } + else { + i2c_master_recv_tc(hperh); + } + } + + ald_i2c_clear_flag_status(hperh, I2C_IT_TC); + } + + /**< Transmit and reload completed interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TCR) == SET) { + if (size > 0xFF) { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS); + } + else { + MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + } + + ald_i2c_clear_flag_status(hperh, I2C_IT_TCR); + } + /**< Transmit FIFO empty interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TXE) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_TXE); + } + + /**< Receive FIFO full interrupt*/ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_RXF) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_RXF); + } + + /**< Address matching interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_ADDR) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_ADDR); + } + + /**< Stop detection interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_STOP) == SET) { + i2c_slave_stopf(hperh); + ald_i2c_clear_flag_status(hperh, I2C_IT_STOP); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hperh: pointer to a i2c_handle_t structure that contains + * the configuration information for I2C module + * @retval NONE + */ +void ald_i2c_er_irq_handler(i2c_handle_t *hperh) +{ + /**< Transmit FIFO overrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TXOV) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_TXOV); + hperh->error_code |= I2C_ERROR_TOV; + } + /**< Transmit FIFO underrun */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TXUD) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_TXUD); + hperh->error_code |= I2C_ERROR_TUD; + } + + /**< Receive FIFO overrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_RXOV) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_RXOV); + hperh->error_code |= I2C_ERROR_ROV; + } + + /**< Receive FIFO underrun interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_RXUD) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_RXUD); + hperh->error_code |= I2C_ERROR_RUD; + } + + /**< NACK interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_NACK) == SET) { + if (hperh->xfer_count != hperh->xfer_size) { + hperh->state |= I2C_ERROR_AF; + } + else { + I2C_DISABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK); + ald_i2c_clear_flag_status(hperh, I2C_IT_NACK); + return; + } + + if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + + I2C_DISABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK); + ald_i2c_clear_flag_status(hperh, I2C_IT_NACK); + } + + /**< Bus error interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_BERR) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_BERR); + hperh->state |= I2C_ERROR_BERR; + } + + /**< Arbitration loss interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_ARLO) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_ARLO); + hperh->state |= I2C_ERROR_ARLO; + } + + /**< PEC error interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_PECE) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_PECE); + } + + /**< Timeout interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TOUT) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_TOUT); + hperh->state |= I2C_ERROR_TIMEOUT; + } + + /**< SMBus Alert interrupt */ + if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_ALERT) == SET) { + ald_i2c_clear_flag_status(hperh, I2C_IT_ALERT); + } + + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); +} + +/** + * @brief Enable/disable the specified I2C interrupts. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param it: Specifies the i2c interrupt sources to be enabled or disabled. + * @param state: New state of the specified I2C interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IER = it; + else + hperh->perh->IDR = it; + + return; +} + +/** + * @brief Get the status of I2C interrupt source. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param it: Specifies the I2C interrupt source. + * This parameter can be one of the @ref i2c_interrupt_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it) +{ + it_status_t status = RESET; + + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(it)); + + if (hperh->perh->IVS & it) + status = SET; + + return status; +} + +/** + * @brief Get the status of I2C interrupt flag. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param flag: Specifies the I2C interrupt flag. + * This parameter can be one of the @ref i2c_interrupt_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + + +/** + * @brief Get the status of interrupt flag and interupt source. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param flag: Specifies the I2C interrupt flag. + * This parameter can be one of the @ref i2c_interrupt_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_i2c_get_mask_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(flag)); + + if (hperh->perh->IFM & flag) + return SET; + + return RESET; +} + +/** + * @brief Clear the I2C interrupt flag. + * @param hperh: Pointer to a i2c_handle_t structure. + * @param flag: Specifies the I2C interrupt flag. + * @retval None + */ +void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag) +{ + assert_param(IS_I2C_TYPE(hperh->perh)); + assert_param(IS_I2C_IT(flag)); + + hperh->perh->ICR = flag; + return; +} + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Handle transmit complete flag for Master Transmit mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_send_tc(i2c_handle_t *hperh) +{ + I2C_DISABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK | I2C_IT_TC | I2C_IT_TCR); + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == RESET) + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + + __UNLOCK(hperh); + hperh->state = I2C_STATE_READY; + + if (hperh->mode == I2C_MODE_MEM) { + if (hperh->mem_tx_cplt_cbk) + hperh->mem_tx_cplt_cbk(hperh); + } + else { + if (hperh->master_tx_cplt_cbk) + hperh->master_tx_cplt_cbk(hperh); + } + + return OK; +} + + +/** + * @brief Handle transmit empty flag for Master Transmit mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh) +{ + if (hperh->xfer_count != hperh->xfer_size) { + while(hperh->perh->STAT & (0x1 << 1)); + hperh->perh->TXDATA = (*hperh->p_buff++); + hperh->xfer_count++; + } + + return OK; +} + +/** + * @brief Handle receive complete for Master Receive mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_recv_tc(i2c_handle_t *hperh) +{ + I2C_DISABLE_IT(hperh, I2C_IT_RXTH | I2C_IT_TCR | I2C_IT_TC); + + if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == RESET) + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + + __UNLOCK(hperh); + hperh->state = I2C_STATE_READY; + + if (hperh->mode == I2C_MODE_MEM) { + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } + else { + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } + + return OK; +} +/** + * @brief Handle receive not empty for Master Receive mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh) +{ + while (READ_BITS(hperh->perh->FCON, I2C_FCON_RXFLV_MSK, I2C_FCON_RXFLV_POSS) > 0) { + if (hperh->xfer_size - hperh->xfer_count > 0) { + (*hperh->p_buff++) = hperh->perh->RXDATA; + hperh->xfer_count++; + } + else { + return OK; + } + } + + return OK; +} + +/** + * @brief Handle TXE flag for Slave Transmit mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh) +{ + if (hperh->xfer_size > hperh->xfer_count) { + while(hperh->perh->STAT & (0x1 << 1)); + hperh->perh->TXDATA = (*hperh->p_buff++); + hperh->xfer_count++; + } + + return OK; +} + +/** + * @brief Handle RXNE flag for Slave Receive mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh) +{ + while (READ_BITS(hperh->perh->FCON, I2C_FCON_RXFLV_MSK, I2C_FCON_RXFLV_POSS) > 0) { + if (hperh->xfer_size > hperh->xfer_count) { + (*hperh->p_buff++) = hperh->perh->RXDATA; + hperh->xfer_count++; + } + else { + return OK; + } + } + + return OK; +} + +/** + * @brief Handle STOPF flag for Slave mode + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh) +{ + I2C_DISABLE_IT(hperh, I2C_IT_ADDR | I2C_IT_NACK | I2C_IT_RXTH | I2C_IT_TXTH | I2C_IT_STOP); + + hperh->mode = I2C_MODE_NONE; + hperh->error_code = I2C_ERROR_NONE; + __UNLOCK(hperh); + + if (hperh->state == I2C_STATE_BUSY_TX) { + hperh->state = I2C_STATE_READY; + if ((hperh->slave_tx_cplt_cbk) && (hperh->xfer_count != 0)) + hperh->slave_tx_cplt_cbk(hperh); + } + else if (hperh->state == I2C_STATE_BUSY_RX) { + hperh->state = I2C_STATE_READY; + if ((hperh->slave_rx_cplt_cbk) && (hperh->xfer_count != 0)) + hperh->slave_rx_cplt_cbk(hperh); + } + + return OK; +} + + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout) +{ + if (hperh->init.addr_mode == I2C_ADDR_7BIT) { + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + } + else { + SET_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + } + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_SADD_MSK, dev_addr << I2C_CON2_SADD_POSS); + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + + return OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout) +{ + if (hperh->init.addr_mode == I2C_ADDR_7BIT) { + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + } + else { + SET_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK); + } + + MODIFY_REG(hperh->perh->CON2, I2C_CON2_SADD_MSK, dev_addr << I2C_CON2_SADD_POSS); + SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK); + + return OK; +} +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ + +static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout) +{ + i2c_master_req_write(hperh, dev_addr, timeout); + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + if (add_size == I2C_MEMADD_SIZE_8BIT) { + while(hperh->perh->STAT & (0x1 << 1)); + hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); + } + else { + while(hperh->perh->STAT & (0x1 << 1)); + hperh->perh->TXDATA = I2C_MEM_ADD_MSB(mem_addr); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) + return ERROR; + + while(hperh->perh->STAT & (0x1 << 1)); + hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); + } + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, timeout) != OK) { + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + ald_i2c_clear_flag_status(hperh, I2C_IT_TCR); + return ERROR; + } + + CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK); + ald_i2c_clear_flag_status(hperh, I2C_IT_TCR); + + return OK; +} +#ifdef ALD_DMA +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param dev_addr: Target device address + * @param mem_addr: Internal memory address + * @param add_size: size of internal memory address + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout) +{ + uint32_t tim_count = 0; + + if (i2c_master_req_write(hperh, dev_addr, timeout) != OK) { + __UNLOCK(hperh); + return ERROR; + } + + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + + if (add_size == I2C_MEMADD_SIZE_8BIT) { + while(hperh->perh->STAT & (0x1 << 1)); + hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); + } + else { + while(hperh->perh->STAT & (0x1 << 1)); + hperh->perh->TXDATA = I2C_MEM_ADD_MSB(mem_addr); + + if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) { + if (hperh->error_code == I2C_ERROR_AF) { + SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK); + return ERROR; + } + else { + return TIMEOUT; + } + } + while(hperh->perh->STAT & (0x1 << 1)); + hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr); + } + + while (!I2C_GET_FLAG(hperh, I2C_STAT_TXE)) { + tim_count++; + + if (tim_count > 0xFFFF) + return TIMEOUT; + } + + return OK; +} + + +/** +* @brief DMA I2C master transmit process complete callback. +* @param argv: I2C handle +* @retval None +*/ +static void i2c_dma_master_send_cplt(void *argv) +{ + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ERROR) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->master_tx_cplt_cbk) + hperh->master_tx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_slave_send_cplt(void *argv) +{ + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->slave_tx_cplt_cbk) + hperh->slave_tx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C master receive process complete callback + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_master_recv_cplt(void *argv) +{ + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ERROR) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->master_rx_cplt_cbk) + hperh->master_rx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_slave_recv_cplt(void *argv) +{ + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->slave_rx_cplt_cbk) + hperh->slave_rx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C Memory Write process complete callback + * @param argv: I2C handle + * @retval None + */uint32_t ccct = 0; +static void i2c_dma_mem_send_cplt(void *argv) +{ + uint32_t cnt = 0xFFFFFF; + + i2c_handle_t* hperh = (i2c_handle_t*)argv; +ccct++;ccct = ccct; + while (cnt--) { + if ((hperh->perh->STAT & I2C_STAT_TC) != 0) + break; + } + + if (cnt == 0) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->mem_tx_cplt_cbk) + hperh->mem_tx_cplt_cbk(hperh); + } +} + +/** + * @brief DMA I2C Memory Read process complete callback + * @param argv: I2C handle + * @retval None + */ +static void i2c_dma_mem_recv_cplt(void *argv) +{ + uint32_t cnt = 0xFFFFF; + + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + while (cnt--) { + if ((hperh->perh->STAT & I2C_STAT_TC) != 0) + break; + } + + if (cnt == 0) + hperh->error_code |= I2C_ERROR_TIMEOUT; + + SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK); + CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK); + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + __UNLOCK(hperh); + + if (hperh->error_code != I2C_ERROR_NONE) { + if (hperh->error_callback) + hperh->error_callback(hperh); + } + else { + if (hperh->mem_rx_cplt_cbk) + hperh->mem_rx_cplt_cbk(hperh); + } +} + +/** +* @brief DMA I2C communication error callback. +* @param argv: I2C handle +* @retval None +*/ +static void i2c_dma_error(void *argv) +{ + i2c_handle_t* hperh = (i2c_handle_t*)argv; + + hperh->xfer_count = 0; + hperh->state = I2C_STATE_READY; + hperh->mode = I2C_MODE_NONE; + hperh->error_code |= I2C_ERROR_DMA; + __UNLOCK(hperh); + + if (hperh->error_callback) + hperh->error_callback(hperh); +} +#endif + +/** + * @brief This function handles I2C Communication timeout. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param flag: specifies the I2C flag to check. + * @param status: The checked flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tickstart = 0; + + tickstart = ald_get_tick(); + if (status == RESET) { + while (I2C_GET_FLAG(hperh, flag) == RESET) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) { + hperh->error_code |= I2C_ERROR_TIMEOUT; + return TIMEOUT; + } + } + } + else { + while (I2C_GET_FLAG(hperh, flag) != RESET) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) { + hperh->error_code |= I2C_ERROR_TIMEOUT; + return TIMEOUT; + } + } + } + + return OK; +} + +/** + * @brief This function handles I2C Communication timeout for Master addressing phase. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param flag: specifies the I2C flag to check. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, uint32_t flag, uint32_t timeout) +{ + uint32_t tickstart = ald_get_tick(); + + while (I2C_GET_IT_FLAG(hperh, flag) == RESET) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) { + hperh->error_code = I2C_ERROR_TIMEOUT; + + return ERROR; + } + } + + return OK; +} + +/** + * @brief This function handles I2C Communication timeout for specific usage of TXE flag. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart = ald_get_tick(); + + while (I2C_GET_FLAG(hperh, I2C_STAT_THTH) == RESET) { + if (I2C_GET_IT_FLAG(hperh, I2C_IT_ARLO)) { + hperh->error_code |= I2C_ERROR_ARLO; + return ERROR; + } + + if (I2C_GET_IT_FLAG(hperh, I2C_IT_NACK) == SET) { + hperh->error_code |= I2C_ERROR_AF; + return ERROR; + } + + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + hperh->error_code |= I2C_ERROR_TIMEOUT; + return ERROR; + } + } + + return OK; +} + +/** + * @brief This function handles I2C Communication timeout for specific usage of RXNE flag. + * @param hperh: Pointer to a i2c_handle_t structure that contains + * the configuration information for the specified I2C. + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout) +{ + uint32_t tickstart = ald_get_tick(); + + while (I2C_GET_FLAG(hperh, I2C_STAT_RXTH) == RESET) { + if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) { + hperh->error_code |= I2C_ERROR_TIMEOUT; + return ERROR; + } + } + + return OK; +} + +/** + * @} + */ + +#endif /* ALD_I2C */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_i2s.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_i2s.c new file mode 100644 index 00000000..89e62994 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_i2s.c @@ -0,0 +1,1077 @@ +/** + ********************************************************************************* + * + * @file ald_I2S.c + * @brief I2S module driver. + * This file provides firmware functions to manage the following + * functionalities of I2S peripheral: + * + Initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + * @version V1.0 + * @date 13 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 13 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2S driver can be used as follows: + + (#) Declare a i2s_handle_t structure, for example: + i2s_handle_t hperh; + + (#) Initialize the I2S low level resources: + (##) Enable the I2Sx interface clock + (##) I2S pins configuration + (+++) Enable the clock for the I2S GPIOs + (+++) Configure these I2S pins as push-pull + (##) NVIC configuration if you need to use interrupt process + by implementing the ald_mcu_irq_config() API. + Invoked ald_i2s_irq_handler() function in I2S-IRQ function + (##) DMA Configuration if you need to use DMA process + (+++) Define ALD_DMA in ald_conf.h + (+++) Enable the DMAx clock + + (#) Program the Channel length, Data length, Polarity, Standard, Pcm frame, + external clock and Main clock output, Odd factor and Divide clock in the i2s_init_t structure. + + (#) Initialize the I2S module by invoking the ald_i2s_init() API. + + [..] + Circular mode restriction: + (#) When the I2S DMA Pause/Stop features are used, we must use the following APIs + the ald_i2s_dma_pause()/ ald_i2s_dma_stop(). + + * @endverbatim + */ + +#include "ald_conf.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup I2S I2S + * @brief I2S module driver + * @{ + */ +#ifdef ALD_I2S + +/** @addtogroup I2S_Private_Functions I2S Private Functions + * @{ + */ + +static ald_status_t i2s_wait_status(i2s_handle_t *hperh, i2s_status_t state, flag_status_t status, uint32_t timeout); +static void __i2s_send_by_it(i2s_handle_t *hperh); +static void __i2s_recv_by_it(i2s_handle_t *hperh); +static void __i2s_tx_recv_by_it(i2s_handle_t *hperh); +#ifdef ALD_DMA +static void i2s_dma_send_cplt(void *arg); +static void i2s_dma_recv_cplt(void *arg); +static void i2s_dma_error(void *arg); +#endif +/** + * @} + */ + +/** @defgroup I2S_Public_Functions I2S Public Functions + * @{ + */ + +/** @defgroup I2S_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + * @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + reset the I2Sx peripheral: + + (+) User must configure all related peripherals resources + (CLOCK, GPIO, DMA, NVIC). + + (+) Call the function ald_i2s_init() to configure the selected device with + the selected configuration: + (++) Channel length + (++) Data length + (++) Polarity + (++) Standard + (++) Pcm frame + (++) External clock + (++) Main clock output function + (++) Odd factor + (++) Divide clock + + (+) Call the function ald_i2s_reset() to reset the selected I2Sx periperal. + + @endverbatim + * @{ + */ + +/** + * @brief Reset the I2S peripheral. + * @param hperh: Pointer to a i2s_handle_t structure that contains + * the configuration information for the specified I2S module. + * @retval None + */ +void ald_i2s_reset(i2s_handle_t *hperh) +{ + hperh->perh->I2SCFG = 0x0; + hperh->perh->I2SPR = 0x0; + + I2S_RESET_HANDLE_STATE(hperh); + __UNLOCK(hperh); + + return; +} + +/** + * @brief Initializes the I2S mode according to the specified parameters in + * the i2s_init_t and create the associated handle. + * @param hperh: Pointer to a i2s_handle_t structure that contains + * the configuration information for the specified SPI module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_init(i2s_handle_t *hperh) +{ + uint32_t tmp = 0, clk, _div; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_CH_LEN(hperh->init.ch_len)); + assert_param(IS_I2S_DATE_LEN(hperh->init.data_len)); + assert_param(IS_I2S_CPOL(hperh->init.polarity)); + assert_param(IS_I2S_STANDARD(hperh->init.standard)); + assert_param(IS_FUNC_STATE(hperh->init.ext_clk_en)); + assert_param(IS_FUNC_STATE(hperh->init.mck_en)); + assert_param(IS_I2S_PCMS(hperh->init.pcm_frame)); + + ald_i2s_reset(hperh); + + tmp |= (hperh->init.ext_clk_en << SPI_I2SPR_EXTCKEN_POS); + + /* Get I2S clock */ + if (hperh->init.ext_clk_en) + clk = hperh->init.ext_clk; + else + clk = ald_cmu_get_pclk1_clock(); + + if (hperh->init.mck_en) { + _div = ((clk / hperh->init.sampling) >> 8); + } + else { + if (hperh->init.ch_len == I2S_WIDE_16) + _div = ((clk / hperh->init.sampling) >> 5); + else + _div = ((clk / hperh->init.sampling) >> 6); + } + + if (_div & 0x1) { + SET_BIT(tmp, SPI_I2SPR_ODD_MSK); + --_div; + } + else { + CLEAR_BIT(tmp, SPI_I2SPR_ODD_MSK); + } + + if (hperh->init.standard != I2S_STD_PCM) + MODIFY_REG(tmp, SPI_I2SPR_I2SDIV_MSK, (_div >> 1) << SPI_I2SPR_I2SDIV_POSS); + else + MODIFY_REG(tmp, SPI_I2SPR_I2SDIV_MSK, _div << SPI_I2SPR_I2SDIV_POSS); + + hperh->perh->I2SPR = tmp; + + tmp = hperh->perh->I2SCFG; + tmp |= ((hperh->init.ch_len << SPI_I2SCFG_CHLEN_POS) | (hperh->init.data_len << SPI_I2SCFG_DATLEN_POSS) | + (hperh->init.polarity << SPI_I2SCFG_CKPOL_POS) | (hperh->init.standard << SPI_I2SCFG_I2SSTD_POSS) | + (1 << SPI_I2SCFG_I2SMOD_POS)); + hperh->perh->I2SCFG = tmp; + + if (hperh->init.standard == I2S_STD_PCM) + hperh->perh->I2SCFG |= (hperh->init.pcm_frame << SPI_I2SCFG_PCMSYNC_POS); + + hperh->err_code = I2S_ERROR_NONE; + hperh->state = I2S_STATE_READY; + + return OK; +} +/** + * @} + */ + +/** @defgroup I2S_Public_Functions_Group2 IO operation functions + * @brief I2S Transmit and Receive functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the I2S + data transfers. + + [..] The I2S supports master or slave mode: + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The ALD status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the ALD status. + The end of the data processing will be indicated through the + dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The hperh->err_cbk() user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA). + + * @endverbatim + * @{ + */ + +/** + * @brief Master mode transmit an amount of data in blocking mode. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_send(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + hperh->state = I2S_STATE_BUSY_TX; + hperh->err_code = I2S_ERROR_NONE; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + while (size > 0) { + if (i2s_wait_status(hperh, I2S_STATUS_TXE, SET, timeout) != OK) { + I2S_DISABLE(hperh); + + hperh->state = I2S_STATE_READY; + return TIMEOUT; + } + + hperh->side = READ_BITS(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK, SPI_STAT_CHSIDE_POS); + hperh->perh->DATA = *buf++; + --size; + } + + if ((i2s_wait_status(hperh, I2S_STATUS_TXE, SET, timeout) != OK) + || (i2s_wait_status(hperh, I2S_STATUS_BUSY, RESET, timeout) != OK)) { + I2S_DISABLE(hperh); + hperh->state = I2S_STATE_READY; + return TIMEOUT; + } + + I2S_DISABLE(hperh); + hperh->state = I2S_STATE_READY; + + return OK; +} + +/** + * @brief Master mode receive an amount of data in blocking mode. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_recv(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + hperh->state = I2S_STATE_BUSY_RX; + hperh->err_code = I2S_ERROR_NONE; + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + while (size > 0) { + hperh->perh->DATA = 0xffff; + if (i2s_wait_status(hperh, I2S_STATUS_RXE, RESET, timeout) != OK) { + I2S_DISABLE(hperh); + hperh->state = I2S_STATE_READY; + return TIMEOUT; + } + + *buf++ = hperh->perh->DATA; + --size; + } + + hperh->state = I2S_STATE_READY; + return OK; +} + +/** + * @brief Wraps up master mode transmission in non blocking mode. + * @param hperh: pointer to a i2s_handle_t structure. + * @param buf: Pointer to data transmitted buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + hperh->state = I2S_STATE_BUSY_TX; + hperh->err_code = I2S_ERROR_NONE; + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + WRITE_REG(hperh->perh->ICR, 0xffffffff); + + I2S_DISABLE(hperh); + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + ald_i2s_interrupt_config(hperh, I2S_IT_TXE, ENABLE); + return OK; +} + +/** + * @brief Master mode receives an amount of data in non blocking mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + hperh->state = I2S_STATE_BUSY_TX_RX; + hperh->err_code = I2S_ERROR_NONE; + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = 0; + hperh->tx_size = size; + hperh->tx_count = size; + + WRITE_REG(hperh->perh->ICR, 0xffffffff); + + I2S_DISABLE(hperh); + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, ENABLE); + ald_i2s_interrupt_config(hperh, I2S_IT_TXE, ENABLE); + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Master mode transmit an amount of data used dma channel + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as I2S transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + hperh->state = I2S_STATE_BUSY_TX; + hperh->err_code = I2S_ERROR_NONE; + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + WRITE_REG(hperh->perh->ICR, 0xffffffff); + + I2S_DISABLE(hperh); + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.cplt_cbk = i2s_dma_send_cplt; + hperh->hdmatx.err_arg = (void *)hperh; + hperh->hdmatx.err_cbk = i2s_dma_error; + + /* Configure I2S DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.perh = DMA0; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = channel; + hperh->hdmatx.config.burst = ENABLE; + ald_dma_config_basic(&(hperh->hdmatx)); + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, ENABLE); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + return OK; +} + +/** + * @brief Master mode receive an amount of data used dma channel + * @param hperh: Pointer to a i2s_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param dma_ch: DMA channel for I2S receive + * @param _dma_ch: DMA channel for sending clock + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_i2s_master_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch) +{ + assert_param(IS_I2S(hperh->perh)); + + if (hperh->state != I2S_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + hperh->state = I2S_STATE_BUSY_RX; + hperh->err_code = I2S_ERROR_NONE; + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + buf[size - 1] = 0xFFFF; + + WRITE_REG(hperh->perh->ICR, 0xffffffff); + + I2S_DISABLE(hperh); + + MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS); + + if (hperh->init.mck_en) + MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS); + + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.cplt_cbk = i2s_dma_send_cplt; + hperh->hdmatx.err_arg = (void *)hperh; + hperh->hdmatx.err_cbk = i2s_dma_error; + + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.perh = DMA0; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)&buf[size - 1]; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.channel = _dma_ch; + ald_dma_config_basic(&(hperh->hdmatx)); + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, ENABLE); + + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.cplt_cbk = i2s_dma_recv_cplt; + hperh->hdmarx.err_arg = (void *)hperh; + hperh->hdmarx.err_cbk = i2s_dma_error; + + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.perh = DMA0; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; + hperh->hdmarx.config.channel = dma_ch; + hperh->hdmarx.config.burst = ENABLE; + ald_dma_config_basic(&(hperh->hdmarx)); + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, ENABLE); + + if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0) + I2S_ENABLE(hperh); + + return OK; +} + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval Status + */ +ald_status_t ald_i2s_dma_pause(i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE); + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE); + + return OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval Status + */ +ald_status_t ald_i2s_dma_resume(i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, ENABLE); + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, ENABLE); + + return OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval Status + */ +ald_status_t ald_i2s_dma_stop(i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE); + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE); + + hperh->state = I2S_STATE_READY; + return OK; +} +#endif +/** + * @} + */ + +/** @defgroup I2S_Public_Functions_Group3 Control functions + * @brief I2S Control functions + * + * @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the I2S. + (+) Handle interrupt about I2S module. The ald_i2s_irq_handler() function must + be invoked by I2S-IRQ function. + (+) Configure the interrupt DISABLE/ENABLE. + (+) Configure the DMA request. + (+) Get interrupt source status. + (+) Get interrupt flag status. + (+) Clear interrupt flag + + @endverbatim + * @{ + */ + +/** + * @brief This function handles I2S interrupt request. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval None + */ +void ald_i2s_irq_handler(i2s_handle_t *hperh) +{ + if (ald_i2s_get_mask_flag_status(hperh, I2S_IF_RXTH) == SET) { + ald_i2s_clear_flag_status(hperh, I2S_IF_RXTH); + if ((hperh->state == I2S_STATE_BUSY_TX_RX) || (hperh->state == I2S_STATE_BUSY_RX)) + __i2s_recv_by_it(hperh); + } + + if (ald_i2s_get_mask_flag_status(hperh, I2S_IF_TXE) == SET) { + ald_i2s_clear_flag_status(hperh, I2S_IF_TXE); + if (hperh->state == I2S_STATE_BUSY_TX) + __i2s_send_by_it(hperh); + else if (hperh->state == I2S_STATE_BUSY_TX_RX) + __i2s_tx_recv_by_it(hperh); + + } + + if (hperh->err_code != I2S_ERROR_NONE) { + ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE); + ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE); + hperh->state = I2S_STATE_READY; + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief Enables or disables the specified I2S interrupts. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param it: Specifies the I2S interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref i2s_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IER = (uint32_t)it; + else + hperh->perh->IDR = (uint32_t)it; + + return; +} + +/** + * @brief Enables or disables the dma request. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param req: Specifies the I2S dma request sources to be enabled or disabled. + * This parameter can be one of the @ref i2s_dma_req_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) { + if (req == I2S_DMA_REQ_TX) + SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + else { + if (req == I2S_DMA_REQ_TX) + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + + return; +} + +/** @brief Check whether the specified I2S flag is set or not. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param status: specifies the flag to check. + * This parameter can be one of the @ref i2s_status_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_i2s_get_status(i2s_handle_t *hperh, i2s_status_t status) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_STATUS(status)); + + if (hperh->perh->STAT & status) + return SET; + + return RESET; +} + +/** + * @brief Checks whether the specified I2S interrupt has occurred or not. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param it: Specifies the I2S interrupt source to check. + * This parameter can be one of the @ref i2s_it_t. + * @retval Status + * - SET + * - RESET + */ +it_status_t ald_i2s_get_it_status(i2s_handle_t *hperh, i2s_it_t it) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IT(it)); + + if (hperh->perh->IVS & it) + return SET; + + return RESET; +} + +/** @brief Check whether the specified I2S interrupt flag is set or not. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref i2s_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_i2s_get_flag_status(i2s_handle_t *hperh, i2s_flag_t flag) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IF(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** @brief Check whether the specified I2S interrupt flag is set or not. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref i2s_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_i2s_get_mask_flag_status(i2s_handle_t *hperh, i2s_flag_t flag) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IF(flag)); + + if (hperh->perh->IFM & flag) + return SET; + + return RESET; +} + +/** @brief Clear the specified I2S interrupt flags. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref i2s_flag_t. + * @retval None + */ +void ald_i2s_clear_flag_status(i2s_handle_t *hperh, i2s_flag_t flag) +{ + assert_param(IS_I2S(hperh->perh)); + assert_param(IS_I2S_IF(flag)); + + hperh->perh->ICR = flag; + return; +} +/** + * @} + */ + +/** @defgroup I2S_Public_Functions_Group4 Peripheral State and Errors functions + * @brief I2S State and Errors functions + * + * @verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the I2S. + (+) ald_i2s_get_state() API can check in run-time the state of the I2S peripheral + (+) ald_i2s_get_error() check in run-time Errors occurring during communication + + @endverbatim + * @{ + */ + +/** + * @brief Returns the I2S state. + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval Status, see @ref i2s_state_t. + */ +i2s_state_t ald_i2s_get_state(i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + return hperh->state; +} + +/** + * @brief Return the I2S error code + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval I2S Error Code + */ +uint32_t ald_i2s_get_error(i2s_handle_t *hperh) +{ + assert_param(IS_I2S(hperh->perh)); + return hperh->err_code; +} +/** + * @} + */ +/** + * @} + */ + +/** @defgroup I2S_Private_Functions I2S Private Functions + * @brief I2S Private functions + * @{ + */ +/** + * @brief This function wait I2S status until timeout. + * @param hperh: Pointer to a i2s_handle_t structure. + * @param flag: specifies the I2S flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t i2s_wait_status(i2s_handle_t *hperh, i2s_status_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick = ald_get_tick(); + + assert_param(timeout > 0); + + while ((ald_i2s_get_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) { + ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE); + ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE); + return TIMEOUT; + } + } + + return OK; +} + +/** + * @brief handle program when an tx empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval None. + */ +static void __i2s_send_by_it(i2s_handle_t *hperh) +{ + int cnt = 8000; + + if (hperh->tx_count == 0) { + ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE); + hperh->state = I2S_STATE_READY; + + while ((hperh->perh->STAT & SPI_STAT_BUSY_MSK) && (--cnt)); + if (cnt == 0) { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE); + return; + } + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return; + } + + hperh->side = READ_BITS(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK, SPI_STAT_CHSIDE_POS); + hperh->perh->DATA = *hperh->tx_buf++; + --hperh->tx_count; + + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval None. + */ +static void __i2s_recv_by_it(i2s_handle_t *hperh) +{ + while (READ_BITS(hperh->perh->STAT, SPI_STAT_RXFLV_MSK, SPI_STAT_RXFLV_POSS)) { + *(hperh->rx_buf++) = hperh->perh->DATA; + --hperh->rx_count; + } + + if (hperh->rx_count == 0) { + ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE); + hperh->state = I2S_STATE_READY; + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a i2s_handle_t structure. + * @retval None. + */ +static void __i2s_tx_recv_by_it(i2s_handle_t *hperh) +{ + if (hperh->tx_count != 0) { + ald_i2s_clear_flag_status(hperh, I2S_IF_TXE); + hperh->perh->DATA = 0xffff; + --hperh->tx_count; + if (hperh->tx_count == 0) + ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE); + } +} + +#ifdef ALD_DMA +/** + * @brief DMA I2S transmit process complete callback. + * @param arg: Pointer to a void structure. + * @retval None + */ +static void i2s_dma_send_cplt(void *arg) +{ + int cnt = 8000; + i2s_handle_t *hperh = (i2s_handle_t *)arg; + + hperh->tx_count = 0; + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE); + hperh->state = I2S_STATE_READY; + + while ((hperh->perh->STAT & SPI_STAT_BUSY_MSK) && (--cnt)); + if (cnt == 0) + hperh->err_code |= I2S_ERROR_FLAG; + + if (hperh->err_code == I2S_ERROR_NONE) { + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA I2S receive process complete callback. + * @param arg: Pointer to a void structure. + * @retval None + */ +static void i2s_dma_recv_cplt(void *arg) +{ + i2s_handle_t *hperh = (i2s_handle_t *)arg; + + hperh->rx_count = 0; + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE); + hperh->state = I2S_STATE_READY; + + if (hperh->err_code == I2S_ERROR_NONE) { + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA I2S communication error callback. + * @param arg: Pointer to a void structure. + * @retval None + */ +static void i2s_dma_error(void *arg) +{ + i2s_handle_t *hperh = (i2s_handle_t *)arg; + + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE); + ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE); + SET_BIT(hperh->err_code, I2S_ERROR_DMA); + + hperh->tx_count = 0; + hperh->rx_count = 0; + hperh->state = I2S_STATE_READY; + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; +} + +#endif +/** + * @} + */ +#endif +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_iap.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_iap.c new file mode 100644 index 00000000..4ce975ce --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_iap.c @@ -0,0 +1,259 @@ +/** + ********************************************************************************* + * + * @file ald_iap.c + * @brief IAP module driver. + * + * @version V1.0 + * @date 04 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 04 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup IAP IAP + * @brief IAP module driver + * @{ + */ +#ifdef ALD_IAP + + +/** @defgroup IAP_Public_Functions IAP Public Functions + * + * @verbatim + ============================================================================== + ##### Erase and Program flash functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Erase flash. + (+) Program flash. + + @endverbatim + * @{ + */ + +/** + * @brief Erases a specified page. + * @param addr: The beginning address of the page to be erased. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t ald_iap_erase_page(uint32_t addr) +{ + uint32_t status; + IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR); + + __disable_irq(); + status = (*iap_pe)(addr); + __enable_irq(); + + return !status; +} + +/** + * @brief Programs a word at a specified address. + * @param addr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param data: Specifies the data to be programmed. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t ald_iap_program_word(uint32_t addr, uint32_t data) +{ + uint32_t status; + IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR); + + if (addr & 0x3) + return 1; + + __disable_irq(); + status = (*iap_wp)(addr, data); + __enable_irq(); + + return !status; +} + +/** + * @brief Programs double words at a specified address. + * @param addr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param data_l: Specifies the LSB data to be programmed. + * @param data_h: Specifies the MSB data to be programmed. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h) +{ + uint32_t status; + IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR); + + if (addr & 0x3) + return 1; + + __disable_irq(); + status = (*iap_dwp)(addr, data_l, data_h); + __enable_irq(); + + return !status; +} + +/** + * @brief Programs datas at a specified address. + * @param addr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param data: Specifies the data to be programmed. + * @param len: Specifies the data length to be programmed. + * Bit0-1 must be zero. + * @param erase: Erase page flag before programming. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase) +{ + uint32_t status; + IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR); + + if ((addr & 0x3) || (len & 0x3)) + return 1; + + __disable_irq(); + status = (*iap_wsp)(addr, data, len, erase); + __enable_irq(); + + return !status; +} + +/** + * @brief Erases a specified page of dataflash. + * @param addr: The beginning address of the page to be erased. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t ald_iap_erase_page_df(uint32_t addr) +{ + uint32_t status; + IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PageErase_DF); + + __disable_irq(); + status = (*iap_pe)(addr); + __enable_irq(); + + return !status; +} + +/** + * @brief Programs a word at a specified address of dataflash. + * @param addr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param data: Specifies the data to be programmed. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t ald_iap_program_word_df(uint32_t addr, uint32_t data) +{ + uint32_t status; + IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WordProgram_DF); + + if (addr & 0x3) + return 1; + + __disable_irq(); + status = (*iap_wp)(addr, data); + __enable_irq(); + + return !status; +} + +/** + * @brief Programs double words at a specified address of dataflash. + * @param addr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param data_l: Specifies the LSB data to be programmed. + * @param data_h: Specifies the MSB data to be programmed. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t ald_iap_program_dword_df(uint32_t addr, uint32_t data_l, uint32_t data_h) +{ + uint32_t status; + IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWordProgram_DF); + + if (addr & 0x3) + return 1; + + __disable_irq(); + status = (*iap_dwp)(addr, data_l, data_h); + __enable_irq(); + + return !status; +} + +/** + * @brief Programs datas at a specified address of dataflash. + * @param addr: Specifies the address to be programmed. + * Bit0-1 must be zero. + * @param data: Specifies the data to be programmed. + * @param len: Specifies the data length to be programmed. + * Bit0-1 must be zero. + * @param erase: Erase page flag before programming. + * @retval The result: + * - 0: SUCCESS + * - 1: ERROR + */ +uint32_t ald_iap_program_words_df(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase) +{ + uint32_t status; + IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WordsProgram_DF); + + if ((addr & 0x3) || (len & 0x3)) + return 1; + + __disable_irq(); + status = (*iap_wsp)(addr, data, len, erase); + __enable_irq(); + + return !status; +} +/** + * @} + */ +#endif /* ALD_IAP */ +/** + * @} + */ +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_nand.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_nand.c new file mode 100644 index 00000000..45ecc6e9 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_nand.c @@ -0,0 +1,1272 @@ +/** + ********************************************************************************* + * + * @file ald_nand.c + * @brief NAND module driver. + * + * @version V1.0 + * @date 18 Mar 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 18 Mar 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is used as follows: + (#) NAND flash memory configuration sequence using the function ald_nand_init() + with control and timing parameters for both common and attribute spaces. + (#) Read NAND flash memory maker and device IDs using the function + ald_nand_read_id(). The read information is stored in the nand_id_typedef + structure declared by the function caller. + (#) Access NAND flash memory by read/write operations using the functions + ald_nand_read_page_8b()/nand_read_SpareArea_8b(), + ald_nand_write_page_8b()/ald_nand_write_sparearea_8b(), + ald_nand_read_page_16b()/ald_nand_read_sparearea_16b(), + ald_nand_write_page_16b()/ald_nand_write_sparearea_16b() + to read/write page(s)/spare area(s). + (#) Perform NAND flash Reset chip operation using the function ald_nand_reset(). + (#) Perform NAND flash erase block operation using the function ald_nand_erase_block(). + (#) Read the NAND flash status operation using the function ald_nand_read_status(). + (#) You can also control the NAND device by calling the control APIs ald_nand_ecc_enable()/ + ald_nand_ecc_disable() to respectively enable/disable the ECC code correction + feature or the function ald_nand_get_ecc() to get the ECC correction code. + + @endverbatim + ****************************************************************************** + */ + +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup NAND NAND + * @brief NAND driver modules + * @{ + */ +#ifdef ALD_NAND + +/** @defgroup Nand_Public_Functions NAND Public Functions + * @brief NAND Public functions + * @{ + */ +/** @defgroup Nand_Public_Functions_Group1 Initialization functions + * @brief NAND Initialization functions + * @{ + */ +/** + * @brief Perform NAND memory initialization sequence + * @param hperh: pointer to a nand_handle_t structure + * @param ctiming: pointer to common space timing structure + * @param atiming: pointer to attribute space timing structure + * @retval ald status + */ +ald_status_t ald_nand_init(nand_handle_t *hperh, ald_ebi_nand_timing_t *ctiming, ald_ebi_nand_timing_t *atiming) +{ + if (hperh == NULL) + return ERROR; + if (hperh->state == ALD_NAND_STATE_RESET) + hperh->lock = UNLOCK; + + ald_ebi_nand_init(hperh->instance, &(hperh->init)); + ald_ebi_nand_comm_timing_init(hperh->instance, ctiming, hperh->init.bank); + ald_ebi_nand_attr_timing_init(hperh->instance, atiming, hperh->init.bank); + ald_ebi_nand_enable(hperh->instance, hperh->init.bank); + hperh->state = ALD_NAND_STATE_READY; + + return OK; +} + +/** + * @brief Perform NAND memory De-Initialization sequence + * @param hperh: pointer to a nand_handle_t structure + * @retval ald status + */ +ald_status_t ald_nand_deinit(nand_handle_t *hperh) +{ + ald_ebi_nand_deinit(hperh->instance, hperh->init.bank); + hperh->state = ALD_NAND_STATE_RESET; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief NAND memory reset + * @param hperh: pointer to a nand_handle_t structure + * @retval ald status + */ +ald_status_t ald_nand_reset(nand_handle_t *hperh) +{ + uint32_t deviceaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + hperh->state = ALD_NAND_STATE_BUSY; + + /* Send NAND reset command */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = 0xFF; + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief configure the device: Enter the physical parameters of the device + * @param hperh: pointer to a nand_handle_t structure + * @param pdcfg : pointer to nand_device_cfg_t structure + * @retval ald status + */ +void nand_config_device(nand_handle_t *hperh, nand_device_cfg_t *pdcfg) +{ + hperh->config.page_size = pdcfg->page_size; + hperh->config.spare_size = pdcfg->spare_size; + hperh->config.block_size = pdcfg->block_size; + hperh->config.block_nbr = pdcfg->block_nbr; + hperh->config.plane_size = pdcfg->plane_size; + hperh->config.plane_nbr = pdcfg->plane_nbr; + hperh->config.extra_cmd = pdcfg->extra_cmd; +} +/** + * @} + */ +/** @defgroup Nand_Public_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/** + * @brief Read the NAND memory electronic signature + * @param hperh: pointer to a nand_handle_t structure + * @param id: NAND ID structure + * @retval ald status + */ +ald_status_t ald_nand_read_id(nand_handle_t *hperh, nand_id_t *id) +{ + __IO uint32_t data = 0; + __IO uint32_t data1 = 0; + uint32_t deviceaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + hperh->state = ALD_NAND_STATE_BUSY; + + /* Send Read ID command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_READID; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + + if (hperh->init.width == EBI_NAND_MEM_BUS_WIDTH_8) { + data = *(__IO uint32_t *)deviceaddr; + + id->maker_id = ADDR_1ST_CYCLE(data); + id->device_id = ADDR_2ND_CYCLE(data); + id->third_id = ADDR_3RD_CYCLE(data); + id->fourth_id = ADDR_4TH_CYCLE(data); + } + else { + data = *(__IO uint32_t *)deviceaddr; + data1 = *((__IO uint32_t *)deviceaddr + 4); + + /* Return the data read */ + id->maker_id = ADDR_1ST_CYCLE(data); + id->device_id = ADDR_3RD_CYCLE(data); + id->third_id = ADDR_1ST_CYCLE(data1); + id->fourth_id = ADDR_3RD_CYCLE(data1); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Read page(s) from NAND memory block (8-bits addressing) + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @param buf: pointer to destination read buffer + * @param nr: number of pages to read from block + * @retval ald status + */ +ald_status_t ald_nand_read_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + hperh->state = ALD_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandaddr = ARRAY_ADDRESS(addr, hperh); + + /* Page(s) read loop */ + while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) { + /* update the buffer size */ + size = (hperh->config.page_size) + ((hperh->config.page_size) * num); + + /* Send read page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A; + + /* Cards with page size <= 512 bytes */ + if ((hperh->config.page_size) <= 512U) { + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65536U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else { /* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65536 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + else { /* (hperh->config.page_size) > 512 */ + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65536U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65536 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + + /* Check if an extra command is needed for reading pages */ + if (hperh->config.extra_cmd == ENABLE) { + /* Get tick */ + tickstart = ald_get_tick(); + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) + return TIMEOUT; + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00); + } + + /*延时25us,nand flash 手册中的最大值*/ + ald_delay_us(25); + + /* Get Data into Buffer */ + for (; index < size; index++) { + *(uint8_t *)buf++ = *(uint8_t *)deviceaddr; + } + + num++; + nr--; + nandaddr = (uint32_t)(nandaddr + 1U); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Write page(s) to NAND memory block (8-bits addressing) + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @param buf: pointer to source buffer to write + * @param nr: number of pages to write to block + * @retval ald status + */ +ald_status_t ald_nand_write_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + /* Update the NAND controller state */ + hperh->state = ALD_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandaddr = ARRAY_ADDRESS(addr, hperh); + + /* Page(s) write loop */ + while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) { + /* update the buffer size */ + size = hperh->config.page_size + ((hperh->config.page_size) * num); + + /* Send write page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0; + + /* Cards with page size <= 512 bytes */ + if ((hperh->config.page_size) <= 512U) { + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65536U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65536 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + else {/* (hperh->config.page_size) > 512 */ + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65536U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65536 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + + /* Write data to memory */ + for (; index < size; index++) + *(__IO uint8_t *)deviceaddr = *(uint8_t *)buf++; + + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + /* Get tick */ + tickstart = ald_get_tick(); + + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) + return TIMEOUT; + } + + num++; + nr--; + nandaddr = (uint32_t)(nandaddr + 1U); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Read spare area(s) from NAND memory (8-bits addressing) + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @param buf: pointer to source buffer to write + * @param nr: Number of spare area to read + * @retval ald status +*/ +ald_status_t ald_nand_read_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0, columnaddr = 0; + + /* Process Locked */ + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + /* Update the NAND controller state */ + hperh->state = ALD_NAND_STATE_BUSY; + /* NAND raw address calculation */ + nandaddr = ARRAY_ADDRESS(addr, hperh); + /* Column in page address */ + columnaddr = COLUMN_ADDRESS(hperh); + + /* Spare area(s) read loop */ + while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) { + /* update the buffer size */ + size = (hperh->config.spare_size) + ((hperh->config.spare_size) * num); + + /* Cards with page size <= 512 bytes */ + if ((hperh->config.page_size) <= 512U) { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_C; + + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65536U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65536 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + else {/* (hperh->config.page_size) > 512 */ + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A; + + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65536U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65536 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + + if (hperh->config.extra_cmd == ENABLE) { + /* Get tick */ + tickstart = ald_get_tick(); + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) + return TIMEOUT; + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00); + } + + /* Get Data into Buffer */ + for (; index < size; index++) + *(uint8_t *)buf++ = *(uint8_t *)deviceaddr; + + num++; + nr--; + nandaddr = (uint32_t)(nandaddr + 1U); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Write spare area(s) to NAND memory (8-bits addressing) + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @param buf: pointer to source buffer to write + * @param nr: number of spare areas to write to block + * @retval ald status + */ +ald_status_t ald_nand_write_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0, columnaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + /* Update the FSMC_NAND controller state */ + hperh->state = ALD_NAND_STATE_BUSY; + /* Page address calculation */ + nandaddr = ARRAY_ADDRESS(addr, hperh); + /* Column in page address */ + columnaddr = COLUMN_ADDRESS(hperh); + + /* Spare area(s) write loop */ + while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) { + /* update the buffer size */ + size = (hperh->config.spare_size) + ((hperh->config.spare_size) * num); + + /* Cards with page size <= 512 bytes */ + if ((hperh->config.page_size) <= 512U) { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0; + + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65536U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65536 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + else {/* (hperh->config.page_size) > 512 */ + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0; + + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65536U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65536 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + + /* Write data to memory */ + for (; index < size; index++) + *(__IO uint8_t *)deviceaddr = *(uint8_t *)buf++; + + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + tickstart = ald_get_tick(); + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) + return TIMEOUT; + } + + num++; + nr--; + nandaddr = (uint32_t)(nandaddr + 1U); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Read page(s) from NAND memory block (16-bits addressing) + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @param buf: pointer to destination read buffer + * @param nr: number of pages to read from block + * @retval ald status + */ +ald_status_t ald_nand_read_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + hperh->state = ALD_NAND_STATE_BUSY; + nandaddr = ARRAY_ADDRESS(addr, hperh); + + /* Page(s) read loop */ + while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) { + /* update the buffer size */ + size = (hperh->config.page_size) + ((hperh->config.page_size) * num); + + /* Send read page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A; + + /* Cards with page size <= 512 bytes */ + if ((hperh->config.page_size) <= 512U) { + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65536U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65536 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + else {/* (hperh->config.page_size) > 512 */ + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65536U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65536 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + + if (hperh->config.extra_cmd == ENABLE) { + /* Get tick */ + tickstart = ald_get_tick(); + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) + return TIMEOUT; + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00); + } + + /* Get Data into Buffer */ + for (; index < size; index++) + *(uint16_t *)buf++ = *(uint16_t *)deviceaddr; + + num++; + nr--; + nandaddr = (uint32_t)(nandaddr + 1U); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Write page(s) to NAND memory block (16-bits addressing) + * @param hperh: pointer to a nand_handle_t structure + * @param addr : pointer to NAND address structure + * @param buf : pointer to source buffer to write. pbuffer should be 16bits aligned + * @param nr : number of pages to write to block + * @retval ald status + */ +ald_status_t ald_nand_write_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + hperh->state = ALD_NAND_STATE_BUSY; + /* NAND raw address calculation */ + nandaddr = ARRAY_ADDRESS(addr, hperh); + + /* Page(s) write loop */ + while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) { + /* update the buffer size */ + size = (hperh->config.page_size) + ((hperh->config.page_size) * num); + + /* Send write page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0; + + /* Cards with page size <= 512 bytes */ + if ((hperh->config.page_size) <= 512U) { + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65536U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else { /* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65536 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + else { /* (hperh->config.page_size) > 512 */ + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65536U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else { /* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65536 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + + /* Write data to memory */ + for (; index < size; index++) + *(__IO uint16_t *)deviceaddr = *(uint16_t *)buf++; + + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + /* Get tick */ + tickstart = ald_get_tick(); + + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) + return TIMEOUT; + } + + num++; + nr--; + nandaddr = (uint32_t)(nandaddr + 1U); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + + + +/** + * @brief Read spare area(s) from NAND memory (16-bits addressing) + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @param buf: pointer to source buffer to write. pbuffer should be 16bits aligned. + * @param nr: Number of spare area to read + * @retval ald status +*/ +ald_status_t ald_nand_read_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0, columnaddr = 0; + + __LOCK(hperh); + + /* Check the NAND controller state */ + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + /* Update the NAND controller state */ + hperh->state = ALD_NAND_STATE_BUSY; + /* NAND raw address calculation */ + nandaddr = ARRAY_ADDRESS(addr, hperh); + /* Column in page address */ + columnaddr = (uint32_t)(COLUMN_ADDRESS(hperh) * 2U); + + /* Spare area(s) read loop */ + while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) { + /* update the buffer size */ + size = (hperh->config.spare_size) + ((hperh->config.spare_size) * num); + + /* Cards with page size <= 512 bytes */ + if ((hperh->config.page_size) <= 512U) { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_C; + + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65536U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65536 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + else {/* (hperh->config.page_size) > 512 */ + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A; + + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65536U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65536 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + + if (hperh->config.extra_cmd == ENABLE) { + /* Get tick */ + tickstart = ald_get_tick(); + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) + return TIMEOUT; + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00); + } + + /* Get Data into Buffer */ + for (; index < size; index++) + *(uint16_t *)buf++ = *(uint16_t *)deviceaddr; + + num++; + nr--; + nandaddr = (uint32_t)(nandaddr + 1U); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + + +/** + * @brief Write spare area(s) to NAND memory (16-bits addressing) + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @param buf: pointer to source buffer to write. pbuffer should be 16bits aligned. + * @param nr: number of spare areas to write to block + * @retval ald status + */ +ald_status_t ald_nand_write_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr) +{ + __IO uint32_t index = 0; + uint32_t tickstart = 0; + uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0, columnaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + /* Update the FSMC_NAND controller state */ + hperh->state = ALD_NAND_STATE_BUSY; + /* NAND raw address calculation */ + nandaddr = ARRAY_ADDRESS(addr, hperh); + /* Column in page address */ + columnaddr = (uint32_t)(COLUMN_ADDRESS(hperh) * 2); + + /* Spare area(s) write loop */ + while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) { + /* update the buffer size */ + size = (hperh->config.spare_size) + ((hperh->config.spare_size) * num); + + /* Cards with page size <= 512 bytes */ + if ((hperh->config.page_size) <= 512U) { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0; + + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65536U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65536 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + else {/* (hperh->config.page_size) > 512 */ + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0; + + if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65536U) { + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + } + else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65536 */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr); + } + } + + /* Write data to memory */ + for (; index < size; index++) + *(__IO uint16_t *)deviceaddr = *(uint16_t *)buf++; + + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + /* Get tick */ + tickstart = ald_get_tick(); + + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) + return TIMEOUT; + } + + num++; + nr--; + nandaddr = (uint32_t)(nandaddr + 1U); + } + + hperh->state = ALD_NAND_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief NAND memory Block erase + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @retval ald status + */ +ald_status_t ald_nand_erase_block(nand_handle_t *hperh, nand_address_t *addr) +{ + uint32_t deviceaddr = 0; + uint32_t tickstart = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + deviceaddr = NAND_DEVICE1; + else + deviceaddr = NAND_DEVICE2; + + /* Update the NAND controller state */ + hperh->state = ALD_NAND_STATE_BUSY; + + /* Send Erase block command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_ERASE0; + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(addr, hperh)); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(addr, hperh)); + *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(addr, hperh)); + *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_ERASE1; + + /* Update the NAND controller state */ + hperh->state = ALD_NAND_STATE_READY; + /* Get tick */ + tickstart = ald_get_tick(); + + /* Read status until NAND is ready */ + while (ald_nand_read_status(hperh) != NAND_READY) { + if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) { + __UNLOCK(hperh); + + return TIMEOUT; + } + } + + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup Nand_Public_Functions_Group3 NAND Control functions + * @brief NAND Control functions + * @{ + */ +/** + * @brief This function handles NAND device interrupt request. + * @param hperh: pointer to a nand_handle_t structure + * @retval ald status +*/ +void ald_nand_irq_handler(nand_handle_t *hperh) +{ + /* Check NAND interrupt Rising edge flag */ + if (ald_ebi_nand_get_flag(hperh->instance, hperh->init.bank, EBI_FLAG_RISING_EDGE)) { + ald_nand_irq_cbk(hperh); + ald_ebi_nand_clear_flag(hperh->instance, hperh->init.bank, EBI_FLAG_RISING_EDGE); + } + + /* Check NAND interrupt Level flag */ + if (ald_ebi_nand_get_flag(hperh->instance, hperh->init.bank, EBI_FLAG_LEVEL)) { + ald_nand_irq_cbk(hperh); + ald_ebi_nand_clear_flag(hperh->instance, hperh->init.bank, EBI_FLAG_LEVEL); + } + + if (ald_ebi_nand_get_flag(hperh->instance, hperh->init.bank, EBI_FLAG_FALLING_EDGE)) { + /* NAND interrupt callback*/ + ald_nand_irq_cbk(hperh); + ald_ebi_nand_clear_flag(hperh->instance, hperh->init.bank, EBI_FLAG_FALLING_EDGE); + } + + /* Check NAND interrupt FIFO empty flag */ + if (ald_ebi_nand_get_flag(hperh->instance, hperh->init.bank, EBI_FLAG_FEMPT)) { + ald_nand_irq_cbk(hperh); + ald_ebi_nand_clear_flag(hperh->instance, hperh->init.bank, EBI_FLAG_FEMPT); + } +} + +/** + * @brief NAND interrupt feature callback + * @param hperh: pointer to a nand_handle_t structure + * @retval None + */ +__weak void ald_nand_irq_cbk(nand_handle_t *hperh) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hperh); +} + +/** + * @brief Increment the NAND memory address + * @param hperh: pointer to a nand_handle_t structure + * @param addr: pointer to NAND address structure + * @retval The new status of the increment address operation. It can be: + * - NAND_VALID_ADDRESS: When the new address is valid address + * - NAND_INVALID_ADDRESS: When the new address is invalid address + */ +uint32_t ald_nand_address_inc(nand_handle_t *hperh, nand_address_t *addr) +{ + uint32_t status = NAND_VALID_ADDRESS; + + addr->page++; + + /* Check NAND address is valid */ + if (addr->page == hperh->config.block_size) { + addr->page = 0; + addr->block++; + + if (addr->block == hperh->config.plane_size) { + addr->block = 0; + addr->plane++; + + if (addr->plane == (hperh->config.plane_nbr)) + status = NAND_INVALID_ADDRESS; + } + } + + return status; +} + +/** + * @brief NAND memory read status + * @param hperh: pointer to a nand_handle_t structure + * @retval NAND status + */ +uint32_t ald_nand_read_status(nand_handle_t *hperh) +{ + uint32_t data = 0; + uint32_t addr = 0; + + /* Identify the device address */ + if (hperh->init.bank == EBI_NAND_BANK2) + addr = NAND_DEVICE1; + else + addr = NAND_DEVICE2; + + /* Send Read status operation command */ + *(__IO uint8_t *)((uint32_t)(addr | CMD_AREA)) = NAND_CMD_STATUS; + /* Read status register data */ + data = *(__IO uint8_t *)addr; + + /* Return the status */ + if ((data & NAND_ERROR) == NAND_ERROR) + return NAND_ERROR; + else if ((data & NAND_READY) == NAND_READY) + return NAND_READY; + + return NAND_BUSY; +} + +/** + * @brief return the NAND state + * @param hperh: pointer to a nand_handle_t structure + * @retval ald state + */ +ald_nand_state_t ald_nand_get_state(nand_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Enables dynamically NAND ECC feature. + * @param hperh: pointer to a nand_handle_t structure + * @retval ald status + */ +ald_status_t ald_nand_ecc_enable(nand_handle_t *hperh) +{ + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Update the NAND state */ + hperh->state = ALD_NAND_STATE_BUSY; + /* Enable ECC feature */ + ald_ebi_nand_ecc_enable(hperh->instance, hperh->init.bank); + /* Update the NAND state */ + hperh->state = ALD_NAND_STATE_READY; + + return OK; +} + +/** + * @brief Disables dynamically FSMC_NAND ECC feature. + * @param hperh: pointer to a nand_handle_t structure + * @retval ald status + */ +ald_status_t ald_nand_ecc_disable(nand_handle_t *hperh) +{ + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + /* Update the NAND state */ + hperh->state = ALD_NAND_STATE_BUSY; + /* Disable ECC feature */ + ald_ebi_nand_ecc_disable(hperh->instance, hperh->init.bank); + hperh->state = ALD_NAND_STATE_READY; + + return OK; +} + +/** + * @brief Disables dynamically NAND ECC feature. + * @param hperh: pointer to a nand_handle_t structure + * @param val: pointer to ECC value + * @param timeout: maximum timeout to wait + * @retval ald status + */ +ald_status_t ald_nand_get_ecc(nand_handle_t *hperh, uint32_t *val, uint32_t timeout) +{ + ald_status_t status = OK; + + if (hperh->state == ALD_NAND_STATE_BUSY) + return BUSY; + + hperh->state = ALD_NAND_STATE_BUSY; + status = ald_ebi_nand_get_ecc(hperh->instance, val, hperh->init.bank, timeout); + hperh->state = ALD_NAND_STATE_READY; + + return status; +} +/** + * @} + */ +/** + * @} + */ +#endif +/** + * @} + */ +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_nor_lcd.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_nor_lcd.c new file mode 100644 index 00000000..5ad3ee35 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_nor_lcd.c @@ -0,0 +1,610 @@ +/** + ********************************************************************************* + * + * @file ald_nor_lcd.c + * @brief EBI_NOR_LCD module driver. + * + * @version V1.0 + * @date 25 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 25 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup NOR_LCD NOR_LCD + * @brief NOR_LCD driver modules + * @{ + */ +#ifdef ALD_NOR + +/** @defgroup NOR_LCD_Private_Variables NOR_LCD Private Variables + * @{ + */ +static uint32_t NORMEMDATWIDTH = NOR_MEMORY_8B; +/** + * @} + */ + +/** @defgroup NOR_LCD_Public_Functions NOR_LCD Public Functions + * @brief NOR_LCD public functions + * @{ + */ +/** @defgroup NOR_LCD_Public_Functions_Group1 Initialization functions + * @brief NOR_LCD Initialization functions + * @{ + */ +/** + * @brief Perform the NOR memory Initialization sequence + * @param hperh: pointer to a nor_handle_t structure + * @param timing: pointer to NOR control timing structure + * @param ext_timing: pointer to NOR extended mode timing structure + * @retval ald status + */ +ald_status_t ald_nor_init(nor_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing) +{ + if (hperh == NULL) + return ERROR; + if (hperh->state == ALD_NOR_STATE_RESET) + hperh->lock = UNLOCK; + + /* Initialize NOR control Interface */ + ald_ebi_nor_sram_init(hperh->instance, &(hperh->init)); + /* Initialize NOR timing Interface */ + ald_ebi_nor_sram_timing_init(hperh->instance, timing, hperh->init.bank); + /* Initialize NOR extended mode timing Interface */ + ald_ebi_nor_sram_ext_timing_init(hperh->ext, ext_timing, hperh->init.bank, hperh->init.ext_mode); + /* Enable the NORSRAM device */ + ald_ebi_nor_sram_enable(hperh->instance, hperh->init.bank); + + /* Initialize NOR Memory Data Width*/ + if (hperh->init.width == EBI_NORSRAM_MEM_BUS_WIDTH_8) + NORMEMDATWIDTH = NOR_MEMORY_8B; + else + NORMEMDATWIDTH = NOR_MEMORY_16B; + + hperh->state = ALD_NOR_STATE_READY; + return OK; +} + +/** + * @brief Perform NOR memory De-Initialization sequence + * @param hperh: pointer to a nor_handle_t structure + * @retval ald status + */ +ald_status_t ald_nor_deinit(nor_handle_t *hperh) +{ + ald_ebi_nor_sram_deinit(hperh->instance, hperh->ext, hperh->init.bank); + hperh->state = ALD_NOR_STATE_RESET; + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup NOR_LCD_Public_Functions_Group2 I/O operation functions + * @brief NOR_LCD I/O operation functions + * @{ + */ +/** + * @brief Read NOR flash IDs + * @param hperh: pointer to a nor_handle_t structure + * @param id : pointer to NOR ID structure + * @retval ald status + */ +ald_status_t ald_nor_read_id(nor_handle_t *hperh, nor_id_t *id) +{ + uint32_t devaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + /* Select the NOR device address */ + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else + devaddr = NOR_MEMORY_ADRESS4; + + hperh->state = ALD_NOR_STATE_BUSY; + + /* Send read ID command */ + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); + + /* Read the NOR IDs */ + id->m_code = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, MC_ADDRESS); + id->device_code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE1_ADDR); + id->device_code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE2_ADDR); + id->device_code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE3_ADDR); + + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Returns the NOR memory to Read mode. + * @param hperh: pointer to a nor_handle_t structure + * @retval ald status + */ +ald_status_t ald_nor_return_readmode(nor_handle_t *hperh) +{ + uint32_t devaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + /* Select the NOR device address */ + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else + devaddr = NOR_MEMORY_ADRESS4; + + NOR_WRITE(devaddr, NOR_CMD_DATA_READ_RESET); + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Read data from NOR memory + * @param hperh: pointer to a nor_handle_t structure + * @param addr: pointer to Device address + * @param data: pointer to read data + * @retval ald status + */ +ald_status_t ald_nor_read(nor_handle_t *hperh, uint32_t *addr, uint16_t *data) +{ + uint32_t devaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else + devaddr = NOR_MEMORY_ADRESS4; + + hperh->state = ALD_NOR_STATE_BUSY; + + /* Send read data command */ + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE((uint32_t)addr, NOR_CMD_DATA_READ_RESET); + + *data = *(__IO uint32_t *)(uint32_t)addr; + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Program data to NOR memory + * @param hperh: pointer to a nor_handle_t structure + * @param addr: device address + * @param data: pointer to the data to write + * @retval ald status + */ +ald_status_t ald_nor_program(nor_handle_t *hperh, uint32_t *addr, uint16_t *data) +{ + uint32_t devaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + /* Select the NOR device address */ + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else /* EBI_NORSRAM_BANK4 */ + devaddr = NOR_MEMORY_ADRESS4; + + hperh->state = ALD_NOR_STATE_BUSY; + + /* Send program data command */ + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + + /* Write the data */ + NOR_WRITE(addr, *data); + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Reads a block of data from the EBI NOR memory + * @param hperh: pointer to a nor_handle_t structure + * @param addr: nor memory internal address to read from + * @param data: pointer to the buffer that receives the data read from the + * NOR memory + * @param size : number of Half word to read + * @retval ald status + */ +ald_status_t ald_nor_read_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size) +{ + uint32_t devaddr = 0; + + /* Process Locked */ + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else + devaddr = NOR_MEMORY_ADRESS4; + + hperh->state = ALD_NOR_STATE_BUSY; + + /* Send read data command */ + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(addr, NOR_CMD_DATA_READ_RESET); + + /* Read buffer */ + while (size > 0) { + *data++ = *(__IO uint16_t *)addr; + addr += 2U; + size--; + } + + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Writes a half-word buffer to the EBI NOR memory + * @param hperh: pointer to a nor_handle_t structure + * @param addr: nor memory internal address from which the data + * @param data: pointer to source data buffer + * @param size: number of Half words to write + * @retval ald status + */ +ald_status_t ald_nor_program_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size) +{ + uint16_t * p_currentaddr = (uint16_t *)NULL; + uint16_t * p_endaddr = (uint16_t *)NULL; + uint32_t lastloadedaddr = 0, devaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else + devaddr = NOR_MEMORY_ADRESS4; + + hperh->state = ALD_NOR_STATE_BUSY; + + /* Initialize variables */ + p_currentaddr = (uint16_t*)((uint32_t)(addr)); + p_endaddr = p_currentaddr + (size - 1U); + lastloadedaddr = (uint32_t)(addr); + + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + /* Write Buffer Load Command */ + NOR_WRITE((uint32_t)(p_currentaddr), NOR_CMD_DATA_BUFFER_AND_PROG); + NOR_WRITE((uint32_t)(p_currentaddr), (size - 1U)); + + /* Load Data into NOR Buffer */ + while (p_currentaddr <= p_endaddr) { + lastloadedaddr = (uint32_t)p_currentaddr; + NOR_WRITE(p_currentaddr, *data++); + p_currentaddr++; + } + + NOR_WRITE((uint32_t)(lastloadedaddr), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Erase the specified block of the NOR memory + * @param hperh: pointer to a nor_handle_t structure + * @param blkaddr : block to erase address + * @param addr: device address + * @retval ald status + */ +ald_status_t ald_nor_erase_block(nor_handle_t *hperh, uint32_t blkaddr, uint32_t addr) +{ + uint32_t devaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else + devaddr = NOR_MEMORY_ADRESS4; + + hperh->state = ALD_NOR_STATE_BUSY; + + /* Send block erase command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE((uint32_t)(blkaddr + addr), NOR_CMD_DATA_BLOCK_ERASE); + + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; + +} + +/** + * @brief Erase the entire NOR chip. + * @param hperh: pointer to a nor_handle_t structure + * @retval ald status + */ +ald_status_t ald_nor_erase_chip(nor_handle_t *hperh) +{ + uint32_t devaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + /* Select the NOR device address */ + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else + devaddr = NOR_MEMORY_ADRESS4; + + hperh->state = ALD_NOR_STATE_BUSY; + + /* Send NOR chip erase command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); + + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Read NOR flash CFI IDs + * @param hperh: pointer to a nor_handle_t structure + * @param cfi: pointer to NOR CFI IDs structure + * @retval ald status + */ +ald_status_t ald_nor_read_cfi(nor_handle_t *hperh, nor_cfi_t *cfi) +{ + uint32_t devaddr = 0; + + __LOCK(hperh); + + if (hperh->state == ALD_NOR_STATE_BUSY) + return BUSY; + + /* Select the NOR device address */ + if (hperh->init.bank == EBI_NORSRAM_BANK1) + devaddr = NOR_MEMORY_ADRESS1; + else if (hperh->init.bank == EBI_NORSRAM_BANK2) + devaddr = NOR_MEMORY_ADRESS2; + else if (hperh->init.bank == EBI_NORSRAM_BANK3) + devaddr = NOR_MEMORY_ADRESS3; + else + devaddr = NOR_MEMORY_ADRESS4; + + hperh->state = ALD_NOR_STATE_BUSY; + NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + + cfi->cfi_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI1_ADDRESS); + cfi->cfi_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI2_ADDRESS); + cfi->cfi_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI3_ADDRESS); + cfi->cfi_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI4_ADDRESS); + + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup NOR_LCD_Public_Functions_Group3 Control functions + * @brief NOR_LCD Control functions + * @{ + */ +/** + * @brief Enables dynamically NOR write operation. + * @param hperh: pointer to a nor_handle_t structure + * @retval ald status + */ +ald_status_t ald_nor_write_enable(nor_handle_t *hperh) +{ + __LOCK(hperh); + /* Enable write operation */ + ald_ebi_nor_sram_write_enable(hperh->instance, hperh->init.bank); + hperh->state = ALD_NOR_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Disables dynamically NOR write operation. + * @param hperh: pointer to a nor_handle_t structure + * @retval ald status + */ +ald_status_t ald_nor_write_disable(nor_handle_t *hperh) +{ + __LOCK(hperh); + hperh->state = ALD_NOR_STATE_BUSY; + /* Disable write operation */ + ald_ebi_nor_sram_write_disable(hperh->instance, hperh->init.bank); + hperh->state = ALD_NOR_STATE_PROTECTED; + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup NOR_LCD_Public_Functions_Group4 State functions + * @brief NOR_LCD State functions + * @{ + */ +/** + * @brief return the NOR controller state + * @param hperh: pointer to a nor_handle_t structure + * @retval nor controller state + */ +ald_nor_state_t ald_nor_get_state(nor_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Returns the NOR operation status. + * @param hperh: pointer to a nor_handle_t structure + * @param addr: device address + * @param timeout: nor progamming timeout + * @retval nor status + */ +nor_status_t ald_nor_get_status(nor_handle_t *hperh, uint32_t addr, uint32_t timeout) +{ + nor_status_t status = ALD_NOR_STATUS_ONGOING; + uint16_t tmp_sr1 = 0, tmp_sr2 = 0; + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = ald_get_tick(); + while ((status != ALD_NOR_STATUS_SUCCESS) && (status != ALD_NOR_STATUS_TIMEOUT)) { + /* Check for the Timeout */ + if (timeout != ALD_MAX_DELAY) { + if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) + status = ALD_NOR_STATUS_TIMEOUT; + } + + /* Read NOR status register (DQ6 and DQ5) */ + tmp_sr1 = *(__IO uint16_t *)addr; + tmp_sr2 = *(__IO uint16_t *)addr; + + /* If DQ6 did not toggle between the two reads then return NOR_Success */ + if ((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6)) + return ALD_NOR_STATUS_SUCCESS; + + if ((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5) + status = ALD_NOR_STATUS_ONGOING; + + tmp_sr1 = *(__IO uint16_t *)addr; + tmp_sr2 = *(__IO uint16_t *)addr; + + /* If DQ6 did not toggle between the two reads then return NOR_Success */ + if ((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6)) + return ALD_NOR_STATUS_SUCCESS; + else if ((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + return ALD_NOR_STATUS_ERROR; + } + + return status; +} +/** + * @} + */ +/** + * @} + */ +#endif +/** + * @} + */ +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_pis.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_pis.c new file mode 100644 index 00000000..e569fc5f --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_pis.c @@ -0,0 +1,323 @@ +/** + ********************************************************************************* + * + * @file ald_pis.c + * @brief PIS module driver. + * + * @version V1.0 + * @date 27 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 27 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_conf.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup PIS PIS + * @brief PIS module driver + * @{ + */ +#ifdef ALD_PIS + +/** @defgroup PIS_Public_Functions PIS Public Functions + * @{ + */ + +/** @defgroup PIS_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/** + * @brief Create the PIS mode according to the specified parameters in + * the pis_handle_t and create the associated handle. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_create(pis_handle_t *hperh) +{ + if (hperh == NULL) + return ERROR; + + assert_param(IS_PIS_SRC(hperh->init.producer_src)); + assert_param(IS_PIS_TRIG(hperh->init.consumer_trig)); + assert_param(IS_PIS_CLOCK(hperh->init.producer_clk)); + assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk)); + assert_param(IS_PIS_EDGE(hperh->init.producer_edge)); + assert_param(IS_PIS_SIGNAL_MODE(hperh->init.producer_signal)); + + __LOCK(hperh); + hperh->perh = PIS; + + /* get location of consumer in channel and position of con0/con1 + * accord to comsumer_trig information */ + hperh->consumer_ch = (pis_ch_t)(hperh->init.consumer_trig & 0x0F); + hperh->consumer_con = (pis_con_t)((hperh->init.consumer_trig >> 4) & 0x0F); + hperh->consumer_pos = (1U << (uint32_t)((hperh->init.consumer_trig >> 8) & 0xFF)); + + if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) { + __UNLOCK(hperh); + return BUSY; + } + + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS); + + if (hperh->init.producer_clk == hperh->init.consumer_clk) { + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_DIRECT << PIS_CH0_CON_SYNCSEL_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, (hperh->init.consumer_clk) << PIS_CH0_CON_PULCK_POSS); + } + else { + if (hperh->init.producer_signal == PIS_OUT_LEVEL) { + if (hperh->init.consumer_clk == PIS_CLK_PCLK1) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_APB1 << PIS_CH0_CON_SYNCSEL_POSS); + if (hperh->init.consumer_clk == PIS_CLK_PCLK2) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_APB2 << PIS_CH0_CON_SYNCSEL_POSS); + if (hperh->init.consumer_clk == PIS_CLK_SYS) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS); + } + + if (hperh->init.producer_signal == PIS_OUT_PULSE) { + if (hperh->init.consumer_clk == PIS_CLK_PCLK1) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_APB1 << PIS_CH0_CON_SYNCSEL_POSS); + if (hperh->init.consumer_clk == PIS_CLK_PCLK2) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_APB2 << PIS_CH0_CON_SYNCSEL_POSS); + if (hperh->init.consumer_clk == PIS_CLK_SYS) + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS); + } + } + + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS); + MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS); + hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch]; + + /* enable consumer bit, switch pin of consumer */ + if (hperh->init.input_chan == PIS_CHAN_INPUT) { + switch (hperh->consumer_con) { + case PIS_CON_0: + PIS->TAR_CON0 |= hperh->consumer_pos; + break; + case PIS_CON_1: + PIS->TAR_CON1 |= hperh->consumer_pos; + break; + default: + break; + } + } + + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Destroy the PIS mode according to the specified parameters in + * the pis_init_t and create the associated handle. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_destroy(pis_handle_t *hperh) +{ + assert_param(IS_PIS(hperh->perh)); + + if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch]) + return ERROR; + + __LOCK(hperh); + + CLEAR_BIT(PIS->CH_OER, (1U << (uint32_t)hperh->consumer_ch)); + WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0); + + switch (hperh->consumer_con) { + case PIS_CON_0: + PIS->TAR_CON0 &= ~(hperh->consumer_pos); + break; + case PIS_CON_1: + PIS->TAR_CON1 &= ~(hperh->consumer_pos); + break; + default: + break; + } + + hperh->state = PIS_STATE_RESET; + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup PIS_Public_Functions_Group2 Operation functions + * @brief PIS output enable or disable functions + * @{ + */ + +/** + * @brief Start the PIS output function. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @param ch: The PIS channel enable output + * This parameter can be one of the following values: + * @arg PIS_OUT_CH_0 + * @arg PIS_OUT_CH_1 + * @arg PIS_OUT_CH_2 + * @arg PIS_OUT_CH_3 + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch) +{ + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_OUPUT_CH(ch)); + __LOCK(hperh); + SET_BIT(PIS->CH_OER, (1 << (uint32_t)ch)); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Stop the PIS output function. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @param ch: The PIS channel disable output + * This parameter can be one of the following values: + * @arg PIS_OUT_CH_0 + * @arg PIS_OUT_CH_1 + * @arg PIS_OUT_CH_2 + * @arg PIS_OUT_CH_3 + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch) +{ + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_OUPUT_CH(ch)); + __LOCK(hperh); + CLEAR_BIT(PIS->CH_OER, (1 << (uint32_t)ch)); + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup PIS_Public_Functions_Group3 Peripheral State and Errors functions + * @brief PIS State and Errors functions + * @{ + */ + +/** + * @brief Returns the PIS state. + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @retval ALD state + */ +pis_state_t ald_pis_get_state(pis_handle_t *hperh) +{ + assert_param(IS_PIS(hperh->perh)); + return hperh->state; +} + +/** + * @} + */ + +/** @defgroup PIS_Public_Functions_Group4 modulate output functions + * @brief PIS modulate output signal functions + * @{ + */ + +/** + * @brief Config the PIS modulate signal function + * @param hperh: Pointer to a pis_handle_t structure that contains + * the configuration information for the specified PIS module. + * @param config: Pointer to a pis_modulate_config_t structure that + * contains the selected target (UART0,UART1,UART2,UART3 or + * LPUART0) how to modulate the target output signal. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config) +{ + assert_param(IS_PIS(hperh->perh)); + assert_param(IS_PIS_MODU_TARGET(config->target)); + assert_param(IS_PIS_MODU_LEVEL(config->level)); + assert_param(IS_PIS_MODU_SRC(config->src)); + assert_param(IS_PIS_MODU_CHANNEL(config->channel)); + __LOCK(hperh); + + switch (config->target) { + case PIS_UART0_TX: + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMLVLS_MSK, config->level << PIS_UART0_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMSS_MSK, config->src << PIS_UART0_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXSIGS_MSK, config->channel << PIS_UART0_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART1_TX: + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMLVLS_MSK, config->level << PIS_UART1_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMSS_MSK, config->src << PIS_UART1_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXSIGS_MSK, config->channel << PIS_UART1_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART2_TX: + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMLVLS_MSK, config->level << PIS_UART2_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMSS_MSK, config->src << PIS_UART2_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXSIGS_MSK, config->channel << PIS_UART2_TXMCR_TXSIGS_POSS); + break; + + case PIS_UART3_TX: + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMLVLS_MSK, config->level << PIS_UART3_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMSS_MSK, config->src << PIS_UART3_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXSIGS_MSK, config->channel << PIS_UART3_TXMCR_TXSIGS_POSS); + break; + + case PIS_LPUART0_TX: + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXMLVLS_MSK, config->level << PIS_LPUART0_TXMCR_TXMLVLS_POS); + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXMSS_MSK, config->src << PIS_LPUART0_TXMCR_TXMSS_POSS); + MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXSIGS_MSK, config->channel << PIS_LPUART0_TXMCR_TXSIGS_POSS); + break; + + default: + break; + } + + __UNLOCK(hperh); + return OK; +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_PIS */ +/** + * @} + */ +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_pmu.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_pmu.c new file mode 100644 index 00000000..be1f6f87 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_pmu.c @@ -0,0 +1,356 @@ +/** + ********************************************************************************* + * + * @file ald_pmu.c + * @brief PMU module driver. + * + * @version V1.0 + * @date 04 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 04 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup PMU PMU + * @brief PMU module driver + * @{ + */ +#ifdef ALD_PMU + + +/** @defgroup PMU_Private_Functions PMU Private Functions + * @{ + */ + +/** + * @brief PMU module interrupt handler + * @retval None + */ +void ald_lvd_irq_handler(void) +{ + SYSCFG_UNLOCK(); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + SYSCFG_LOCK(); + + return; +} +/** + * @} + */ + +/** @defgroup PMU_Public_Functions PMU Public Functions + * @{ + */ + +/** @addtogroup PMU_Public_Functions_Group1 Low Power Mode + * @brief Low power mode select functions + * + * @verbatim + ============================================================================== + ##### Low power mode select functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Enter stop1 mode. + (+) Enter stop2 mode. + (+) Enter standby mode. + (+) Get wakeup status. + (+) Clear wakeup status. + + @endverbatim + * @{ + */ + +/** + * @brief Enter stop1 mode + * @retval None + */ +void ald_pmu_stop1_enter(void) +{ + int cnt = 4000; + + SYSCFG_UNLOCK(); + + CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); +#ifdef ES32F336x /* MCU Series: ES32F336x */ + SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); +#endif + MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, PMU_LDO_18_HOLD << PMU_CR1_LDO18MOD_POSS); + MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STOP1 << PMU_CR0_LPM_POSS); + SYSCFG_LOCK(); + + while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + + return; +} + +/** + * @brief Enter stop2 mode + * @retval None + */ +void ald_pmu_stop2_enter(void) +{ + int cnt = 4000; + + SYSCFG_UNLOCK(); + + SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); +#ifdef ES32F336x /* MCU Series: ES32F336x */ + SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); +#endif + MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, PMU_LDO_18_HOLD << PMU_CR1_LDO18MOD_POSS); + MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STOP2 << PMU_CR0_LPM_POSS); + SYSCFG_LOCK(); + + while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + + return; +} + +/** + * @brief Enter standby mode + * @param port: The port whick wake up the standby mode. + * @param level: Wakeup level. + * @retval None + */ +void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level) +{ + ald_bkpc_standby_wakeup_config(port, level); + + SYSCFG_UNLOCK(); + MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STANDBY << PMU_CR0_LPM_POSS); + SYSCFG_LOCK(); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + + return; +} + +/** + * @brief Enable/Disable LDO(1.2V) hold mode. It must be disabled in STOP1. + * @param state: Enable/Disable + * @retval None + */ +void ald_pmu_ldo_12_config(type_func_t state) +{ + assert_param(IS_FUNC_STATE(state)); + SYSCFG_UNLOCK(); + + if (state) + SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); + else + CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Configure LDO(1.8V) mode + * @param mode: Mode of the LDO(1.8V) + * @retval None + */ +void ald_pmu_ldo_18_config(pmu_ldo_18_mode_t mode) +{ + uint32_t cnt = 4000; + + assert_param(IS_PMU_LDO18_MODE(mode)); + + SYSCFG_UNLOCK(); + MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, mode << PMU_CR1_LDO18MOD_POSS); + SYSCFG_LOCK(); + + while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--)); + return; +} + +#ifdef ES32F336x /* MCU Series: ES32F336x */ + +/** + * @brief Configures low power mode. The system clock must + * be less than 2MHz. Such as: LOSC or LRC. + * @param vol: LDO output voltage select in low power mode. + * @param state: New state, ENABLE/DISABLE; + * @retval None + */ +void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state) +{ + assert_param(IS_FUNC_STATE(state)); + SYSCFG_UNLOCK(); + + if (state) { + assert_param(IS_PMU_LDO_LPMODE_OUTPUT(vol)); + + MODIFY_REG(PMU->CR0, PMU_CR0_LPVS_MSK, vol << PMU_CR0_LPVS_POSS); + SET_BIT(PMU->CR0, PMU_CR0_LPRUN_MSK); + } + else { + CLEAR_BIT(PMU->CR0, PMU_CR0_LPRUN_MSK); + } + + SYSCFG_LOCK(); + return; +} +#endif + +/** + * @brief Get wakup status. + * @param sr: Status bit. + * @retval Status. + */ +flag_status_t ald_pmu_get_status(pmu_status_t sr) +{ + assert_param(IS_PMU_STATUS(sr)); + + if (READ_BIT(PMU->SR, sr)) + return SET; + + return RESET; +} + +/** + * @brief Clear wakup status. + * @param sr: Status bit. + * @retval None + */ +void ald_pmu_clear_status(pmu_status_t sr) +{ + assert_param(IS_PMU_STATUS(sr)); + SYSCFG_UNLOCK(); + + if (sr == PMU_SR_WUF) + SET_BIT(PMU->CR0, PMU_CR0_CWUF_MSK); + else if (sr == PMU_SR_STANDBYF) + SET_BIT(PMU->CR0, PMU_CR0_CSTANDBYF_MSK); + else + ;/* do nothing */ + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Configure peripheral power + * @param perh: The peripheral + * @param state: ENABLE/DISABLE + * @retval None + */ +void ald_pmu_perh_power_config(pmu_perh_power_t perh, type_func_t state) +{ + assert_param(IS_PMU_PERH_POWER(perh)); + assert_param(IS_FUNC_STATE(state)); + + SYSCFG_UNLOCK(); + + if (state) + SET_BIT(PMU->PWRCR, perh); + else + CLEAR_BIT(PMU->PWRCR, perh); + + SYSCFG_LOCK(); + return; +} +/** + * @} + */ + +/** @addtogroup PMU_Public_Functions_Group2 LVD Configure + * @brief LVD configure functions + * + * @verbatim + ============================================================================== + ##### LVD configure functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure lvd parameters. + + @endverbatim + * @{ + */ + +/** + * @brief Configure lvd using specified parameters. + * @param sel: LVD threshold voltage. + * @param mode: LVD trigger mode. + * @param state: New state, ENABLE/DISABLE; + * @retval None + */ +void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state) +{ + assert_param(IS_FUNC_STATE(state)); + SYSCFG_UNLOCK(); + + if (state) { + assert_param(IS_PMU_LVD_VOL_SEL(sel)); + assert_param(IS_PMU_LVD_TRIGGER_MODE(mode)); + + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS); + MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); + } + else { + SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK); + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK); + CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK); + } + + SYSCFG_LOCK(); + return; +} +/** + * @} + */ + + +/** + * @} + */ +#endif /* ALD_PMU */ +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_qspi.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_qspi.c new file mode 100644 index 00000000..d4ad0f23 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_qspi.c @@ -0,0 +1,1116 @@ +/** + ********************************************************************************* + * + * @file ald_qspi.c + * @brief QSPI module driver. + * + * @version V1.0 + * @date 09 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 09 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup QSPI QSPI + * @brief QSPI module driver + * @{ + */ + +#ifdef ALD_QSPI + +/** @defgroup QSPI_Private_Functions QSPI Private Functions + * @brief QSPI Private functions + * @{ + */ + +/** + * @brief Wait for a flag state until timeout. + * @param hperh: QSPI handle + * @param timeout: Duration of the time out + * @param tickstart: tick start value + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t qspi_wait_for_idle(qspi_handle_t *hperh, uint32_t tickstart, uint32_t timeout) +{ + /* Wait until flag is in expected state */ + while (READ_BIT(hperh->perh->CR, QSPI_CR_IDLES_MSK) != QSPI_CR_IDLES_MSK) { + /* Check for the Timeout */ + if (timeout != ALD_MAX_DELAY) { + if ((timeout == 0U) || ((ald_get_tick() - tickstart) > timeout)) { + return ERROR; + } + } + } + return OK; +} + +/** + * @brief Get indirect read status. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param status: Indirect status. + * @retval Status, see @ref ald_status_t. + */ +static flag_status_t qspi_indrd_get_status(qspi_handle_t *hperh, qspi_indrd_flag_t status) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_INDIRECT_READ_STATUS(status)); + + if (hperh->perh->IRTR & status) + return SET; + + return RESET; +} + +/** + * @} + */ + +/** @defgroup QSPI_Public_Functions QSPI Public Functions + * @brief QSPI Public Functions + * @{ + */ +/** @defgroup QSPI_Public_Functions_Group1 Basic execution functions + * @brief QSPI basic execution functions + * @{ + */ +/** + * @brief Initializes the QSPI basic parameters. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @retval None. + */ +void ald_qspi_init(qspi_handle_t *hperh) +{ + assert_param(IS_QSPI_CLOCK_PRESCALER(hperh->init.clkdiv)); + assert_param(IS_QSPI_CLOCK_PHASE(hperh->init.chpa)); + assert_param(IS_QSPI_CLOCK_POLARITY(hperh->init.cpol)); + + MODIFY_REG(hperh->perh->CR, QSPI_CR_BAUD_MSK | QSPI_CR_CPOL_MSK | QSPI_CR_CPHA_MSK | \ + QSPI_CR_PSL_MSK | QSPI_CR_SWPP_MSK , (hperh->init.clkdiv << QSPI_CR_BAUD_POSS) | \ + (hperh->init.cpol << QSPI_CR_CPOL_POS) | \ + (hperh->init.chpa << QSPI_CR_CPHA_POS) | \ + (hperh->init.chipsel << QSPI_CR_PSL_POSS) | \ + (hperh->init.wrppin << QSPI_CR_SWPP_POS)); +} + +/** + * @brief DAC read. + * @param addr: address. + * @retval value + */ +uint32_t ald_qspi_dac_rd(uint32_t addr) +{ + return ((*(volatile uint32_t *)(addr))); +} + +/** + * @brief DAC write . + * @param addr: address. + * @param dat: data. + * @retval None + */ +void ald_qspi_dac_wr(uint32_t addr, uint32_t dat) +{ + (*(volatile uint32_t *)(addr)) = dat; +} + +/** + * @brief Configure Read Operations. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param rdcfg: Pointer to configuration structure for QSPI read operations. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_read_config(qspi_handle_t * hperh, const qspi_read_cfg_t * rdcfg) +{ + ald_status_t status = ERROR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_RD_OPCODE(rdcfg->rdcde)); + assert_param(IS_QSPI_DCYLES(rdcfg->dcyles)); + assert_param(IS_QSPI_XFER_TYPE(rdcfg->datxfer)); + assert_param(IS_QSPI_XFER_TYPE(rdcfg->addxfer)); + assert_param(IS_QSPI_XFER_TYPE(rdcfg->instxfer)); + + status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE); + + if (status != OK) + return status; + + MODIFY_REG(hperh->perh->DRIR, QSPI_DRIR_RINST_MSK | QSPI_DRIR_MBEN_MSK | \ + QSPI_DRIR_DCYC_MSK | QSPI_DRIR_ADMODE_MSK | \ + QSPI_DRIR_DMODE_MSK | QSPI_DRIR_IMODE_MSK | \ + QSPI_DRIR_DDRM_MSK, \ + (rdcfg->rdcde | (rdcfg->dcyles << 24) | \ + (rdcfg->addxfer << 12) | (rdcfg->instxfer << 8) | \ + (rdcfg->ddrbit << QSPI_DRIR_DDRM_POS) | (rdcfg->modebit << QSPI_DRIR_MBEN_POS)) | \ + (rdcfg->datxfer << QSPI_DRIR_DMODE_POSS)); + + if (rdcfg->modebit) + MODIFY_REG(hperh->perh->MBR, QSPI_MBR_MODEB_MSK, rdcfg->mbitval); + + return status; +} + +/** + * @brief Configure Write Operations. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param wrcfg: Pointer to configuration structure for QSPI write operations. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_write_config(qspi_handle_t * hperh, const qspi_write_cfg_t * wrcfg) +{ + ald_status_t status = ERROR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_WR_OPCODE(wrcfg->wrcde)); + assert_param(IS_QSPI_DCYLES(wrcfg->dcyles)); + assert_param(IS_QSPI_XFER_TYPE(wrcfg->datxfer)); + assert_param(IS_QSPI_XFER_TYPE(wrcfg->addxfer)); + + status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE); + + if (status != OK) + return status; + + MODIFY_REG(hperh->perh->DWIR, QSPI_DWIR_WINST_MSK | QSPI_DWIR_DCYC_MSK | \ + QSPI_DWIR_ADMODE_MSK | QSPI_DWIR_DMODE_MSK, + wrcfg->wrcde | \ + (wrcfg->addxfer << 12) | \ + (wrcfg->datxfer << 16) | \ + (wrcfg->dcyles << 24)); + if (wrcfg->autowel) + CLEAR_BIT(hperh->perh->DWIR, QSPI_DWIR_WELD_MSK); + else + SET_BIT(hperh->perh->DWIR, QSPI_DWIR_WELD_MSK); + + return status; +} + +/** + * @brief QSPI Device Delay Configuration. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param dlycfg: Device delay configuration structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_device_delay_config(qspi_handle_t * hperh, qspi_dly_cfg_t *dlycfg) +{ + ald_status_t status = ERROR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_DEVICE_DELAY_CCSOT(dlycfg->ccsot)); + assert_param(IS_QSPI_DEVICE_DELAY_CSEOT(dlycfg->cseot)); + assert_param(IS_QSPI_DEVICE_DELAY_CSDADS(dlycfg->csdads)); + assert_param(IS_QSPI_DEVICE_DELAY_CSDA(dlycfg->csda)); + + status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE); + + if (status != OK) + return status; + + MODIFY_REG(hperh->perh->DDLR, QSPI_DDLR_CSSOT_MSK | QSPI_DDLR_CSEOT_MSK | QSPI_DDLR_CSDADS_MSK | QSPI_DDLR_CSDA_MSK, \ + dlycfg->ccsot | (dlycfg->cseot << 8) | (dlycfg->csdads << 16) | (dlycfg->csda << 24)); + return status; +} + +/** + * @brief QSPI Read Data Capture Configuration. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param dtcptcfg: Data capture configuration structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_read_data_capture_config(qspi_handle_t * hperh, qspi_data_capture_cfg_t *dtcptcfg) +{ + ald_status_t status = ERROR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_READ_DATA_CAPTURE_DELAY_READ(dtcptcfg->dlydcl)); + assert_param(IS_QSPI_READ_DATA_SAMPLE_EDGE(dtcptcfg->smpledge)); + assert_param(IS_QSPI_READ_DATA_DELAY_TRANSMIT(dtcptcfg->dlytd)); + + status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE); + + if (status != OK) + return status; + + MODIFY_REG(hperh->perh->RDCR, QSPI_RDCR_BYLPC_MSK | QSPI_RDCR_DLYR_MSK | QSPI_RDCR_SMES_MSK | QSPI_RDCR_DLYT_MSK, \ + 0x1U | (dtcptcfg->dlydcl << 1) | (dtcptcfg->smpledge << 5) | (dtcptcfg->dlytd << 16)); + return status; +} + +/** + * @brief QSPI Flash memory Configuration. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param devcfg: flash parameter configuration structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_device_size_config(qspi_handle_t *hperh, qspi_device_size_t * devcfg) +{ + ald_status_t status = ERROR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_ADDR_SIZE(devcfg->addr)); + assert_param(IS_QSPI_PAGE_SIZE(devcfg->page)); + assert_param(IS_QSPI_BLOCK_SIZE(devcfg->blk)); + assert_param(IS_QSPI_NSS_SIZE(devcfg->cs0)); + assert_param(IS_QSPI_NSS_SIZE(devcfg->cs1)); + assert_param(IS_QSPI_NSS_SIZE(devcfg->cs2)); + assert_param(IS_QSPI_NSS_SIZE(devcfg->cs3)); + + status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE); + + if (status != OK) + return status; + + MODIFY_REG(hperh->perh->DSCR, QSPI_DSCR_ADSIZE_MSK | QSPI_DSCR_PASIZE_MSK | QSPI_DSCR_BKSIZE_MSK | QSPI_DSCR_CS0SIZE_MSK | \ + QSPI_DSCR_CS1SIZE_MSK | QSPI_DSCR_CS2SIZE_MSK | QSPI_DSCR_CS3SIZE_MSK, \ + (devcfg->addr << QSPI_DSCR_ADSIZE_POSS) | \ + (devcfg->page << QSPI_DSCR_PASIZE_POSS) | \ + (devcfg->blk << QSPI_DSCR_BKSIZE_POSS) | \ + (devcfg->cs0 << QSPI_DSCR_CS0SIZE_POSS) | \ + (devcfg->cs1 << QSPI_DSCR_CS1SIZE_POSS) | \ + (devcfg->cs2 << QSPI_DSCR_CS2SIZE_POSS) | \ + (devcfg->cs3 << QSPI_DSCR_CS3SIZE_POSS)); + return OK; +} + +/** + * @brief Initializes the QSPI direct access according to the specified parameters + * in the associated handle. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param dcfg : structure that contains the indirect read command configuration information. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t qspi_dac_config(qspi_handle_t * hperh, qspi_dac_cfg_t * dcfg) +{ + ald_status_t status = ERROR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_WR_OPCODE(dcfg->wrinit.wrcde)); + assert_param(IS_QSPI_DCYLES(dcfg->wrinit.dcyles)); + assert_param(IS_QSPI_XFER_TYPE(dcfg->wrinit.datxfer)); + assert_param(IS_QSPI_XFER_TYPE(dcfg->wrinit.addxfer)); + assert_param(IS_QSPI_XFER_TYPE(dcfg->wrinit.instxfer)); + + status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE); + + if (status != OK) + return status; + + QSPI_DISABLE(hperh); + ald_qspi_init(hperh); + + if (ald_qspi_write_config(hperh, &dcfg->wrinit) != OK) + return ERROR; + if (ald_qspi_read_config(hperh, &dcfg->rdinit) != OK) + return ERROR; + + if (dcfg->addrremap) + MODIFY_REG(hperh->perh->RAR, QSPI_RAR_READDR_MSK, dcfg->remapaddr); + + MODIFY_REG(hperh->perh->CR, QSPI_CR_DTRM_MSK | QSPI_CR_ADEN_MSK | QSPI_CR_XIPIM_MSK | \ + QSPI_CR_XIPNX_MSK | QSPI_CR_AREN_MSK | QSPI_CR_DMAEN_MSK, \ + dcfg->dtrprtcol << 24 | dcfg->ahbdecoder << 23); + QSPI_ENABLE(hperh); + return OK; +} + +/** + * @} + */ + +/** @defgroup QSPI_Public_Functions_Group2 Indirect and stig access execution functions + * @brief QSPI indirect and stig access execution functions + * @{ + */ +/** + * @brief Initializes the QSPI indirect access according to the specified parameters + * in the associated handle. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param indcfg: Pointer to indirect access initialization structure qspi_indac_config_t. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_indac_config(qspi_handle_t * hperh, qspi_indac_cfg_t *indcfg) +{ + ald_status_t status = ERROR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_SRAM_PARTITION(indcfg->srampt)); + assert_param(IS_QSPI_INDIRECT_TRIGGER_RANGE(indcfg->trgrng)); + assert_param(IS_QSPI_INDIRECT_READ_WATERMARK(indcfg->rdwmark)); + + status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE); + + if (status != OK) + return status; + + QSPI_DISABLE(hperh); + + MODIFY_REG(hperh->perh->SPR, QSPI_SPR_SRAMPS_MSK, indcfg->srampt); + MODIFY_REG(hperh->perh->IATR, QSPI_IATR_INDTAD_MSK, indcfg->trgaddr); + MODIFY_REG(hperh->perh->ITARR, QSPI_ITARR_RNGW_MSK, indcfg->trgrng); + MODIFY_REG(hperh->perh->IWTWR, QSPI_IWTWR_VAULE_MSK, indcfg->wrwmark); + MODIFY_REG(hperh->perh->IRTWR, QSPI_IRTWR_VAULE_MSK, indcfg->rdwmark); + + QSPI_ENABLE(hperh); + + return OK; +} + +/** + * @brief QSPI write data by interrupt. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param saddr: Write start address. + * @param psrc: Pointer to source data buffer. + * @param size : Write bytes number. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_indac_transmit_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size) +{ + uint32_t i = 0; + uint32_t tmp = 0, pgsize = 0; + assert_param(IS_QSPI_ALL(hperh->perh)); + + if ((psrc == NULL) || (size == 0)) + return ERROR; + + hperh->state = QSPI_STATE_BUSY_TX; + hperh->rx_buf = NULL; + hperh->rx_cnt = 0; + hperh->rx_size = 0; + hperh->tx_buf = psrc; + hperh->tx_cnt = 0; + hperh->tx_size = size; + + tmp = READ_REG(hperh->perh->DSCR); + pgsize = (tmp & 0xfff0) >> 4; + + if (size >= pgsize) + tmp = pgsize; + else + tmp = size; + + hperh->tx_cnt += tmp; + + ald_qspi_clear_it_flag(hperh, QSPI_IF_INDCF); + MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, saddr); + MODIFY_REG(hperh->perh->IWTNR, QSPI_IWTNR_NUM_MSK, size); + ald_qspi_interrupt_config(hperh, QSPI_IT_INDTWF, ENABLE); + ald_qspi_interrupt_config(hperh, QSPI_IT_INDCF, ENABLE); + + /* Trigger indirect write */ + SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK); + + for (i = 0; i < (tmp / 4); ++i) + *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(psrc + 4 * i)); + + return OK; +} + +/** + * @brief Transmit data to flash by poll. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param saddr: Write start address. + * @param psrc: Pointer to source data buffer. + * @param size: Write bytes number. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_indac_transmit_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size) +{ + uint32_t i, j = 0, cnt = 0; + uint32_t tmp = 0; + uint32_t idx = 0, txsm = 0; + assert_param(IS_QSPI_ALL(hperh->perh)); + + if ((psrc == NULL) || (size == 0)) + return ERROR; + + MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, saddr); + MODIFY_REG(hperh->perh->IWTNR, QSPI_IWTNR_NUM_MSK, size); + + /* Counter write times totally */ + if (size % 4) + cnt = (size / 4) + 1; + else + cnt = size / 4; + /* Get transmit SRAM partition (unit:4bytes)*/ + tmp = READ_REG(hperh->perh->SPR); + txsm = QSPI_SRAM_SIZE - tmp; + if (txsm == 0) return ERROR; + if (cnt <= txsm) { + /* Trigger indirect write */ + SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK); + for (i = 0; i < cnt; ++i) + *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(psrc + 4 *i)); + } else { + SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK); + for (j = 0; j < (cnt / txsm); ++j) { + for (i = 0; i < txsm; ++i) { + *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(psrc + idx + 4 *i)); + } + idx += txsm * 4; + do { + tmp = READ_REG(hperh->perh->SFLR); + tmp = (tmp >> 16) & 0xffff; + } while (tmp != 0); + } + + for (j = 0; j < (cnt % txsm); ++j) + *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(psrc + idx + 4 *j)); + } + /* Wait for indirect read operation completely */ + do { + tmp = READ_REG(hperh->perh->IWTR); + } while ( tmp & 0x4); + + return OK; +} + +/** + * @brief Read data from flash by poll. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param saddr: Read start address. + * @param desbuf: Pointer to data buffer. + * @param size: Read bytes number. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_indac_read_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size) +{ + + uint32_t i = 0, j = 0, cnt = 0; + uint32_t tmp = 0; + uint32_t idx = 0, rxsm = 1; + + assert_param(IS_QSPI_ALL(hperh->perh)); + + if ((desbuf == NULL) || (size == 0)) + return ERROR; + + MODIFY_REG(hperh->perh->IRTSAR, QSPI_IRTSAR_ADDR_MSK, saddr); + MODIFY_REG(hperh->perh->IRTNR, QSPI_IRTNR_NUM_MSK, size); + /* Counter read times totally */ + if (size % 4) + cnt = (size / 4) + 1; + else + cnt = size / 4; + /* Get read SRAM partition (unit: 4bytes)*/ + rxsm = READ_REG(hperh->perh->SPR) + 1; + if (cnt <= rxsm) { + SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK); + do { + tmp = READ_REG(hperh->perh->SFLR); + tmp = tmp & 0x0000ffffU; + } while (tmp != cnt); + for (i = 0; i < cnt; ++i) + *(uint32_t *)(desbuf + 4 * i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS; + } else { + SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK); + for (j = 0; j < (cnt / rxsm); ++j) { + do { + tmp = READ_REG(hperh->perh->SFLR); + tmp = tmp & 0x0000ffffU; + } while (tmp != rxsm); + for (i = 0; i < rxsm; ++i) { + *(uint32_t *)(desbuf + idx + 4 * i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS; + } + idx += rxsm * 4; + } + do { + tmp = READ_REG(hperh->perh->SFLR); + tmp = tmp & 0x0000ffffU; + } while ( tmp != (cnt % rxsm)); + + for (j = 0; j < (cnt % rxsm); ++j) { + *(uint32_t *)(desbuf + idx + 4 * i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS; + } + } + /* Wait for indirect read operation completely */ + do { + tmp = READ_REG(hperh->perh->IRTR); + } while (tmp & 0x04); + + return OK; +} + +/** + * @brief QSPI read data by interrupt. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param saddr: Read start address. + * @param desbuf: Pointer to destination data buffer. + * @param size: Read bytes length. + * @retval Status, see @ref ald_status_t. + */ + +ald_status_t ald_qspi_indac_read_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + + if ((desbuf == NULL) || (size == 0)) + return ERROR; + + hperh->state = QSPI_STATE_BUSY_RX; + hperh->rx_buf = desbuf; + hperh->rx_cnt = 0; + hperh->rx_size = size; + hperh->tx_buf = NULL; + hperh->tx_cnt = 0; + hperh->tx_size = 0; + + ald_qspi_clear_it_flag(hperh, QSPI_IF_INDCF); + MODIFY_REG(hperh->perh->IRTSAR, QSPI_IRTSAR_ADDR_MSK, saddr); + MODIFY_REG(hperh->perh->IRTNR, QSPI_IRTNR_NUM_MSK, size); + ald_qspi_interrupt_config(hperh, QSPI_IT_INDTWF, ENABLE); + ald_qspi_interrupt_config(hperh, QSPI_IT_INDCF, ENABLE); + SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK); + + return OK; +} + +/** + * @brief Execute a STIG command. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param stigcmd: Pointer to a structure that describes the STIG command. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_execute_stig_cmd(qspi_handle_t * hperh, const qspi_stig_cmd_t * stigcmd) +{ + uint32_t i; + ald_status_t status = ERROR; + uint32_t tickstart = ald_get_tick(); + + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(stigcmd->addr_len <= 4); + assert_param(stigcmd->wr_len <= 8); + assert_param(stigcmd->rd_len <= 8); + assert_param(stigcmd->d_sycle < 32); + + if (stigcmd->wr_len) + assert_param(stigcmd->wr_buf); + if (stigcmd->rd_len) + assert_param(stigcmd->rd_buf); + + /* wait for Flash idle */ + status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE); + + if (status != OK) + return ERROR; + + MODIFY_REG(hperh->perh->FCR, QSPI_FCR_OPCODE_MSK | QSPI_FCR_DUMNUM_MSK , ((stigcmd->code << 24) | (stigcmd->d_sycle << 7))); + + if (stigcmd->wr_len) { + uint32_t buffer[2] = {0, 0}; + uint8_t * dst = (uint8_t *) buffer; + uint8_t * src = stigcmd->wr_buf; + + MODIFY_REG(hperh->perh->FCR, QSPI_FCR_WDNUM_MSK, (stigcmd->wr_len - 1) << QSPI_FCR_WDNUM_POSS); + SET_BIT(hperh->perh->FCR, QSPI_FCR_WREN_MSK); + + for (i = 0; i < stigcmd->wr_len; i++) + dst[i] = src[i]; + + hperh->perh->FCWLR = buffer[0]; + hperh->perh->FCWHR = buffer[1]; + } else { + CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_WDNUM_MSK); + CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_WREN_MSK); + } + + if (stigcmd->addr_len) { + SET_BIT(hperh->perh->FCR, QSPI_FCR_ADDREN_MSK); + + MODIFY_REG(hperh->perh->FCR, QSPI_FCR_ADNUM_MSK, (stigcmd->addr_len - 1) << QSPI_FCR_ADNUM_POSS); + MODIFY_REG(hperh->perh->FCAR, QSPI_FCAR_CMDADR_MSK, stigcmd->addr); + } else { + CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_ADDREN_MSK); + CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_ADNUM_MSK); + CLEAR_BIT(hperh->perh->FCAR, QSPI_FCAR_CMDADR_MSK); + } + + if (stigcmd->mode_bit) { + SET_BIT(hperh->perh->FCR, QSPI_FCR_MODBEN_MSK); + MODIFY_REG(hperh->perh->MBR, QSPI_MBR_MODEB_MSK, stigcmd->val); + } else { + CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_MODBEN_MSK); + CLEAR_BIT(hperh->perh->MBR, QSPI_MBR_MODEB_MSK); + } + + if (stigcmd->rd_len) { + SET_BIT(hperh->perh->FCR, QSPI_FCR_RDEN_MSK); + MODIFY_REG(hperh->perh->FCR, QSPI_FCR_RDNUM_MSK, (stigcmd->rd_len - 1) << QSPI_FCR_RDNUM_POSS); + } else { + CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_RDEN_MSK); + CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_RDNUM_MSK); + } + + /* Start command execution */ + SET_BIT(hperh->perh->FCR, QSPI_FCR_CMDT_MSK); + + while (hperh->perh->FCR & QSPI_FCR_CMDS_MSK); + + /* Read data if any */ + if (stigcmd->rd_len) { + uint32_t buffer[2] = { 0, 0 }; + const uint8_t * src = (const uint8_t *)buffer; + uint8_t * dst = stigcmd->rd_buf; + + buffer[0] = hperh->perh->FCRLR; + buffer[1] = hperh->perh->FCRHR; + + for (i = 0; i < stigcmd->rd_len; i++) { + dst[i] = src[i]; + } + } + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Sends an amount of data with DMA. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param addr: Write start address. + * @param psrc: Pointer to data buffer. + * @param size: Write data bytes. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_indac_transmit_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *psrc, uint16_t size) +{ + uint16_t cnt = 0; + uint32_t *tmp = (uint32_t*)psrc; + /* Get Indirect Read Trigger Address */ + __IO uint32_t *data_reg = (uint32_t *)hperh->perh->IATR; + + assert_param(IS_QSPI_ALL(hperh->perh)); + + if ((psrc == NULL) || (size == 0)) + return ERROR; + + MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, addr); + MODIFY_REG(hperh->perh->IWTNR, QSPI_IWTNR_NUM_MSK, size); + QSPI_DMA_ENABLE(hperh); + if (size % 4) + cnt = (size / 4) + 1; + else + cnt = size / 4; + + __LOCK(hperh); + + hperh->hdma.perh = DMA0; + hperh->hdma.cplt_cbk = NULL; + ald_dma_config_struct(&hperh->hdma.config); + + hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma.config.src = (void *)tmp; + hperh->hdma.config.dst = (void *)data_reg; + hperh->hdma.config.size = cnt; + hperh->hdma.config.src_inc = DMA_DATA_INC_WORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.msel = DMA_MSEL_QSPI; + hperh->hdma.config.msigsel = DMA_MSIGSEL_QSPI_WRITE; + hperh->hdma.config.channel = 0; + hperh->hdma.config.R_power = DMA_R_POWER_4; + hperh->hdma.config.burst = ENABLE; + ald_dma_config_basic(&hperh->hdma); + + /* Trigger indirect write */ + SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receive an amount of data with DMA. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param addr: Read start address. + * @param pdbuf: Pointer to data buffer. + * @param size: Read data bytes. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_qspi_indac_read_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *pdbuf, uint16_t size) +{ + uint16_t cnt = 0; + ald_status_t status = OK; + uint32_t *tmp = (uint32_t *)pdbuf; + /* Get Indirect Read Trigger Address */ + __IO uint32_t *data_reg = (uint32_t *)hperh->perh->IATR; + + assert_param(IS_QSPI_ALL(hperh->perh)); + + if ((pdbuf == NULL) || (size == 0)) + return ERROR; + + MODIFY_REG(hperh->perh->IRTSAR, QSPI_IRTSAR_ADDR_MSK, addr); + MODIFY_REG(hperh->perh->IRTNR, QSPI_IRTNR_NUM_MSK, size); + + QSPI_DMA_ENABLE(hperh); + + if (size % 4) + cnt = (size / 4) + 1; + else + cnt = size / 4; + + __LOCK(hperh); + + hperh->hdma.perh = DMA0; + hperh->hdma.cplt_cbk = NULL; + ald_dma_config_struct(&hperh->hdma.config); + + hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD; + hperh->hdma.config.src = (void *)data_reg; + hperh->hdma.config.dst = (void *)tmp; + hperh->hdma.config.size = cnt; + hperh->hdma.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma.config.dst_inc = DMA_DATA_INC_WORD; + hperh->hdma.config.msel = DMA_MSEL_QSPI; + hperh->hdma.config.msigsel = DMA_MSIGSEL_QSPI_READ; + hperh->hdma.config.channel = 0; + hperh->hdma.config.R_power = DMA_R_POWER_4; + hperh->hdma.config.burst = ENABLE; + ald_dma_config_basic(&hperh->hdma); + + /* Trigger indirect write */ + SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK); + __UNLOCK(hperh); + + return status; +} +#endif + +/** + * @} + */ + +/** @defgroup QSPI_Public_Functions_Group3 Status functions + * @brief QSPI status functions + * @{ + */ +/** + * @brief Get the status of QSPI interrupt flag. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param flag: Specifies the QSPI interrupt flag. + * This parameter can be one of the @ref qspi_flag_t. + * @retval Status, see @ref flag_status_t. + */ +flag_status_t qspi_get_flag_status(qspi_handle_t *hperh, qspi_flag_t flag) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_IF(flag)); + + if (hperh->perh->IFR & flag) + return SET; + + return RESET; +} + +/** + * @brief Clear the QSPI interrupt flag. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param flag: Specifies the QSPI interrupt flag. + * This parameter can be one of the @ref qspi_flag_t. + * @retval None + */ +void ald_qspi_clear_it_flag(qspi_handle_t *hperh, qspi_flag_t flag) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_IF(flag)); + + hperh->perh->IFR = flag; + + return; +} + +/** + * @brief Read QSPI SRAM fill level. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param srt: QSPI embeded SRAM type,the value can be one of @ref qspi_sram_t. + * @retval sram fill level value. + */ +uint16_t qspi_read_sram_fill_level(qspi_handle_t * hperh, qspi_sram_t srt) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_INDIRECT_SRAM_FILL_TYPE(srt)); + + if (srt == QSPI_SRAM_RD) + return READ_BITS(hperh->perh->SFLR, QSPI_SFLR_INDRSFL_MSK, QSPI_SFLR_INDRSFL_POSS); + + return READ_BITS(hperh->perh->SFLR, QSPI_SFLR_INDWSFL_MSK, QSPI_SFLR_INDWSFL_POSS); +} + +/** + * @brief QSPI Write Protect Configuration. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param wpcfg: Pointer to the QSPI write protect configuration structer. + * @retval None. + */ +void ald_qspi_write_proect_config(qspi_handle_t * hperh, qspi_wr_protect_t * wpcfg) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + + MODIFY_REG(hperh->perh->WPLR, QSPI_WPLR_LBLKNUM_MSK, wpcfg->lowblk); + MODIFY_REG(hperh->perh->WPHR, QSPI_WPHR_HBLKNUM_MSK, wpcfg->upblk); + QSPI_WRITE_PROTECT_ENABLE(hperh); + + return; +} + +/** + * @brief QSPI Write Protect Inversion. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param state: SRAM protect inversion state. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None. + */ +void ald_qspi_write_proect_inverse(qspi_handle_t * hperh, type_func_t state) +{ + assert_param(IS_FUNC_STATE(state)); + assert_param(IS_QSPI_ALL(hperh->perh)); + + if (state) { + QSPI_WRITE_PROTECT_DISABLE(hperh); + SET_BIT(hperh->perh->WPCR, QSPI_WPCR_WPINV_MSK); + QSPI_WRITE_PROTECT_ENABLE(hperh); + } + else { + QSPI_WRITE_PROTECT_DISABLE(hperh); + SET_BIT(hperh->perh->WPCR, QSPI_WPCR_WPINV_MSK); + QSPI_WRITE_PROTECT_ENABLE(hperh); + } + + return; +} + +/** + * @brief QSPI interrupt handler + * @retval None + */ +void ald_qspi_irq_handler(qspi_handle_t *hperh) +{ + uint32_t regs = 0; + uint32_t tmp = 0, i = 0; + + regs = READ_REG(hperh->perh->DSCR); + regs = (regs & 0x0000fff0) >> 4; + + // indirect transmit + if (hperh->state == QSPI_STATE_BUSY_TX) { + + //QSPI indirect transmit(xfer length longer than watermark value) + if (qspi_get_flag_status(hperh, QSPI_IF_INDTWF) == SET) { + ald_qspi_clear_it_flag(hperh, QSPI_IF_INDTWF); + tmp = hperh->tx_size - hperh->tx_cnt; + if (tmp > regs) { + for (i = 0; i < (regs / 4); ++i) { + *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(hperh->tx_buf + hperh->tx_cnt + 4 * i)); + } + hperh->tx_cnt += regs; + } else { + for (i = 0; i < (tmp / 4); ++i) { + *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(hperh->tx_buf + hperh->tx_cnt + 4 * i)); + } + hperh->tx_cnt += tmp; + } + } + //QSPI indirect transmit completely + if (qspi_get_flag_status(hperh, QSPI_IF_INDCF) == SET) { + ald_qspi_clear_it_flag(hperh, QSPI_IF_INDCF); + ald_qspi_interrupt_config(hperh, QSPI_IT_INDTWF, DISABLE); + //transmit completely callback + } + + } + + // indirect receive + if (hperh->state == QSPI_STATE_BUSY_RX) { + if (qspi_get_flag_status(hperh, QSPI_IF_INDTWF) == SET) { + ald_qspi_clear_it_flag(hperh, QSPI_IF_INDTWF); + tmp = READ_REG(hperh->perh->SFLR); + tmp = tmp & 0xffff; + + for (i = 0; i < tmp; ++i) { + *(uint32_t *)(hperh->rx_buf + hperh->rx_cnt + i*4) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS; + } + hperh->rx_cnt += tmp*4; + } + + if (qspi_get_flag_status(hperh, QSPI_IF_INDCF) == SET) { + ald_qspi_clear_it_flag(hperh, QSPI_IF_INDCF); + ald_qspi_interrupt_config(hperh, QSPI_IT_INDTWF, DISABLE); + + tmp = READ_REG(hperh->perh->SFLR); + tmp = tmp & 0xffff; + + for (i = 0; i < tmp; ++i) { + *(uint32_t *)(hperh->rx_buf + hperh->rx_cnt + i*4) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS; + } + } + } +} + +/** + * @brief Enable/disable the specified QSPI interrupts. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param it: Specifies the QSPI interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref qspi_it_t. + * @param state: New state of the specified QSPI interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_qspi_interrupt_config(qspi_handle_t *hperh, qspi_it_t it, type_func_t state) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IMR |= (uint32_t)it; + else + hperh->perh->IMR &= (uint32_t)(~it); + + return; +} + +/** + * @brief Configure the QSPI legacy . + * @param hperh: Pointer to a qspi_handle_t structure. + * @param config: structure that contains the legacy configuration information. + * @retval None + */ +void ald_qspi_legacy_config(qspi_handle_t* hperh, const qspi_legacy_cfg_t *config) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + + MODIFY_REG(hperh->perh->TXHR, QSPI_TXHR_TXTH_MSK, config->tx_thrd); + MODIFY_REG(hperh->perh->RXHR, QSPI_RXHR_RXTH_MSK, config->rx_thrd); + QSPI_LEGACY_SPI_ENABLE(hperh); + + return; +} + +/** + * @brief Get QSPI indirect write access status. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param status: qspi indirect write status. + * @retval Status, see @ref ald_status_t. + */ +flag_status_t qspi_indwr_get_status(qspi_handle_t *hperh, qspi_indwr_status_t status) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_INDIRECT_WRITE_STATUS(status)); + + if (hperh->perh->IWTR & status) + return SET; + + return RESET; +} + +/** + * @brief Wait indirect wriet a flag state until time out. + * @param hperh: Pointer to the QSPI qspi_handle_t structure. + * @param flag: Flag checked,the parameter can be one of @ref qspi_indwr_status_t. + * @param status: Value of the flag expected,the parameter can be one of @ref flag_status_t. + * @param timeout: Duration of the time out. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t qspi_indwr_wait_flag(qspi_handle_t *hperh, qspi_indwr_status_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick; + + if (timeout == 0) + return ERROR; + + tick = ald_get_tick(); + + /* Waiting for flag */ + while ((qspi_indwr_get_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + + return OK; +} + +/** + * @brief QSPI Indirect read operation wait for specified status. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param flag: specifies the qspi flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t qspi_indrd_wait_flag(qspi_handle_t *hperh, qspi_indrd_flag_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick; + + if (timeout == 0) + return ERROR; + + tick = ald_get_tick(); + + /* Waiting for flag */ + while ((qspi_indrd_get_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + return OK; +} + +/** + * @brief Clear the QSPI interrupt flag. + * @param hperh: Pointer to a qspi_handle_t structure. + * @param flag: Specifies the QSPI interrupt flag. + * This parameter can be one of the @ref qspi_flag_t. + * @retval None + */ +void qspi_clear_flag_status(qspi_handle_t *hperh, qspi_flag_t flag) +{ + assert_param(IS_QSPI_ALL(hperh->perh)); + assert_param(IS_QSPI_IF(flag)); + + hperh->perh->IFR = flag; + return; +} + +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_QSPI */ +/** + * @} + */ +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_rmu.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_rmu.c new file mode 100644 index 00000000..38134a66 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_rmu.c @@ -0,0 +1,161 @@ +/** + ********************************************************************************* + * + * @file ald_rmu.c + * @brief RMU module driver. + * + * @version V1.0 + * @date 04 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 04 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_conf.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup RMU RMU + * @brief RMU module driver + * @{ + */ +#ifdef ALD_RMU + +/** @defgroup RMU_Public_Functions RMU Public Functions + * @{ + */ + +/** + * @brief Configure BOR parameters. + * @param flt: filter time. + * @param vol: The voltage. + * @param state: The new status: ENABLE/DISABLE. + * @retval None + */ +void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state) +{ + assert_param(IS_FUNC_STATE(state)); + + SYSCFG_UNLOCK(); + + if (state) { + assert_param(IS_RMU_BORFLT(flt)); + assert_param(IS_RMU_BORVOL(vol)); + + MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS); + MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS); + SET_BIT(RMU->CR, RMU_CR_BOREN_MSK); + } + else { + CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK); + } + + SYSCFG_LOCK(); + return; +} + +/** + * @brief Get specified reset status + * @param state: Speicifies the type of the reset, + * @retval The status. + */ +uint32_t ald_rmu_get_reset_status(rmu_state_t state) +{ + assert_param(IS_RMU_STATE(state)); + + if (state == RMU_RST_ALL) + return RMU->RSTSR; + + if (READ_BIT(RMU->RSTSR, state)) + return SET; + + return RESET; +} + +/** + * @brief Clear the specified reset status + * @param state: Specifies the type of the reset, + * @retval None + */ +void ald_rmu_clear_reset_status(rmu_state_t state) +{ + assert_param(IS_RMU_STATE_CLEAR(state)); + + SYSCFG_UNLOCK(); + WRITE_REG(RMU->CRSTSR, state); + SYSCFG_LOCK(); + + return; +} +/** + * @brief Reset peripheral device + * @param perh: The peripheral device, + * @retval None + */ +void ald_rmu_reset_periperal(rmu_peripheral_t perh) +{ + uint32_t idx, pos; + + assert_param(IS_RMU_PERH(perh)); + + idx = ((uint32_t)perh >> 27) & 0x7; + pos = perh & ~(0x7 << 27); + SYSCFG_UNLOCK(); + + switch (idx) { + case 0: + WRITE_REG(RMU->AHB1RSTR, pos); + break; + + case 1: + WRITE_REG(RMU->AHB2RSTR, pos); + break; + + case 2: + WRITE_REG(RMU->APB1RSTR, pos); + break; + + case 4: + WRITE_REG(RMU->APB2RSTR, pos); + break; + + default: + break; + } + + SYSCFG_LOCK(); + return; +} + +/** + * @} + */ +#endif /* ALD_RMU */ +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_rtc.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_rtc.c new file mode 100644 index 00000000..65e9cfda --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_rtc.c @@ -0,0 +1,1206 @@ +/** + ****************************************************************************** + * @file ald_rtc.c + * @brief RTC module driver. + * This file provides firmware functions to manage the following + * functionalities of the RTC peripheral: + * + Initialization functions + * + Time and date functions + * + Alarm functions + * + Time stamp functions + * + Tamper functions + * + Wake-up functions + * + Clock output functions + * + Peripheral Control functions + * @version V1.0 + * @date 25 Apr 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 25 Apr 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (+) Enable the RTC controller interface clock. + (+) Select the RTC source clock(default LOSC). + (+) Configure the RTC asynchronous prescaler, synchronous prescaler and hour + format using the ald_rtc_init() function. + + *** Time and date operation *** + ================================= + [..] + (+) To configure the time use the ald_rtc_set_time() function. + (+) To configure the date use the ald_rtc_set_date() function. + (+) To read the time use the ald_rtc_get_time() function. + (+) To read the date use the ald_rtc_get_date() function. + + *** Alarm operation *** + =================================== + [..] + (+) To configure the alarm use ald_rtc_set_alarm() function + (+) To read the alarm use ald_rtc_get_alarm() function + (+) To cancel the alarm use ald_rtc_alarm_cmd() function + + *** Time stamp operation *** + =================================== + [..] + (+) To configure the time stamp use ald_rtc_set_time_stamp() function + (+) To read the time stamp use ald_rtc_get_time_stamp() function + (+) To cancel the time stamp use ald_rtc_cancel_time_stamp() function + + *** Tamper operation *** + =================================== + [..] + (+) To configure the tamper use ald_rtc_set_tamper() function + (+) To cancel the tamper use ald_rtc_alarm_cmd() function + + *** Wake-up operation *** + =================================== + [..] + (+) To configure the wake-up parameters use ald_rtc_set_wakeup() function + (+) To read the re-load register value use ald_rtc_get_wakeup_timer_value() function + (+) To cancel the wake-up use ald_rtc_cancel_wakeup() function + + *** Output clock operation *** + =================================== + [..] + (+) To configure the clock output type use ald_rtc_set_clock_output() function + (+) To cancel the clock output use ald_rtc_cancel_clock_output() function + + *** Control functions *** + =================================== + [..] + (+) Configure interrupt enable/disable. + (+) Enable/disable alarm. + (+) Configure rtc shift. + (+) Calibrate time. + (+) Get interrupt source status. + (+) Get interrupt flag status. + (+) Clear interrupt flag. + + ================================================================== + ##### RTC and low power modes ##### + ================================================================== + [..] The MCU can be woken up from a low power mode by an RTC alternate function. + [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), + RTC wake-up, RTC tamper event detection and RTC time stamp event detection. + These RTC alternate functions can wake up the system from the Stop and + Standby low power modes. + [..] The system can also wake up from low power modes without depending + on an external interrupt (Auto-wake-up mode), by using the RTC alarm + or the RTC wake-up events. + [..] The RTC provides a programmable time base for waking up from the Stop or + Standby mode at regular intervals. Wake-up from STOP and STANDBY modes + is possible only when the RTC clock source is LSE or LSI. + + *** RTC driver macros list *** + ============================================= + [..] + Below the list of most used macros in RTC driver. + + (+) RTC_UNLOCK() Disable the protect. + (+) RTC_LOCK() Enable the protect. + (+) RTC_BY_PASS_ENABLE() Enable the by-pass shadow register. + (+) RTC_BY_PASS_DISABLE() Disable the by-pass shadow register. + (+) RTC_SUMMER_TIME_ENABLE() Enable summer time. + (+) RTC_SUMMER_TIME_DISABLE() Disable summer time. + (+) RTC_WINTER_TIME_ENABLE() Enable winter time. + (+) RTC_WINTER_TIME_DISABLE() Disable winter time. + [..] + (@) You can refer to the RTC driver header file for used the macros + + @endverbatim + ****************************************************************************** + */ + +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup RTC RTC + * @brief RTC module driver + * @{ + */ +#ifdef ALD_RTC + +/** @addtogroup RTC_Private_Functions RTC Private Functions + * @{ + */ +/** + * @brief Converts form 2 digit BCD to Binary. + * @param bcd: BCD value to be converted. + * @retval Converted word. + */ +static uint32_t bcd_to_dec(uint32_t bcd) +{ + return ((bcd & 0xF) + ((bcd >> 4) & 0xF) * 10); +} + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param dec: Byte to be converted. + * @retval Converted byte. + */ +static uint32_t dec_to_bcd(uint32_t dec) +{ + return (((dec / 10) << 4) | (dec % 10)); +} + +/** + * @brief Time and Date consistency check. + * @param t_last: Last time. + * @param d_last: Last date. + * @param time: Current time. + * @param date: Current time. + * @retval status: + * 0 - Not consistency + * 1 - Consistency + */ +static int32_t rtc_consistency_check(rtc_time_t *t_last, + rtc_date_t *d_last, rtc_time_t *time, rtc_date_t *date) +{ + if (t_last->second != time->second) + return 0; + if (t_last->minute != time->minute) + return 0; + if (t_last->hour != time->hour) + return 0; + if (d_last->day != date->day) + return 0; + if (d_last->month != date->month) + return 0; + if (d_last->year != date->year) + return 0; + + return 1; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions RTC Public Functions + * @{ + */ + +/** @defgroup RTC_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * + * @verbatim + =============================================================================== + ##### Initialization function ##### + =============================================================================== + [..] This section provides functions allowing to initialize and configure the + RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + RTC registers Write protection. + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + It is split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize power consumption. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register. + + @endverbatim + * @{ + */ + +/** + * @brief Reset RTC register. + * @retval None + */ +void ald_rtc_reset(void) +{ + RTC_UNLOCK(); + + WRITE_REG(RTC->CON, 0x0); + WRITE_REG(RTC->TAMPCON, 0x0); + WRITE_REG(RTC->WUMAT, 0x0); + WRITE_REG(RTC->IER, 0x0); + WRITE_REG(RTC->IFCR, ~0x0); + + RTC_LOCK(); + return; +} + +/** + * @brief Initialize the RTC module. + * @param init: Pointer to rtc_init_t structure which contains + * the configuration parameters. + * @retval None + */ +void ald_rtc_init(rtc_init_t *init) +{ + assert_param(IS_RTC_HOUR_FORMAT(init->hour_format)); + assert_param(IS_RTC_OUTPUT_SEL(init->output)); + assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity)); + + ald_rtc_reset(); + RTC_UNLOCK(); + + MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS); + MODIFY_REG(RTC->CON, RTC_CON_EOS_MSK, init->output << RTC_CON_EOS_POSS); + MODIFY_REG(RTC->CON, RTC_CON_POL_MSK, init->output_polarity << RTC_CON_POL_POS); + MODIFY_REG(RTC->PSR, RTC_PSR_SPRS_MSK, init->synch_pre_div << RTC_PSR_SPRS_POSS); + MODIFY_REG(RTC->PSR, RTC_PSR_APRS_MSK, init->asynch_pre_div << RTC_PSR_APRS_POSS); + SET_BIT(RTC->CON, RTC_CON_GO_MSK); + + RTC_LOCK(); + return; +} + +/** + * @brief Configure the RTC source. + * @param sel: RTC source type. + * @retval None + */ +void ald_rtc_source_select(rtc_source_sel_t sel) +{ + assert_param(IS_RTC_SOURCE_SEL(sel)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, sel << BKPC_PCCR_RTCCS_POSS); + + if (sel == RTC_SOURCE_LOSC) { + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); + } + else if (sel == RTC_SOURCE_LRC) { + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); + } + else { + ; /* do nothing */ + } + + BKPC_LOCK(); + return; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group2 Time and Date functions + * @brief RTC Time and Date functions + * + * @verbatim + =============================================================================== + ##### Time and Date functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the time use the ald_rtc_set_time() function. + (+) To configure the date use the ald_rtc_set_date() function. + (+) To read the time use the ald_rtc_get_time() function. + (+) To read the date use the ald_rtc_get_date() function. + + @endverbatim + * @{ + */ + +/** + * @brief Set specified time. + * @param time: pointer to a rtc_time_t structure. + * @param format: Data format. + * @retval ALD status. + */ +ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format) +{ + uint32_t tmp; + + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) { + assert_param(IS_RTC_SECOND(time->second)); + assert_param(IS_RTC_MINUTE(time->minute)); + assert_param(IS_RTC_HOUR(time->hour)); + + tmp = (dec_to_bcd(time->second)) | + (dec_to_bcd(time->minute) << 8) | + (dec_to_bcd(time->hour) << 16); + } + else { + assert_param(IS_RTC_SECOND(bcd_to_dec(time->second))); + assert_param(IS_RTC_MINUTE(bcd_to_dec(time->minute))); + assert_param(IS_RTC_HOUR(bcd_to_dec(time->hour))); + + tmp = time->second | (time->minute << 8) | (time->hour << 16); + } + + RTC_UNLOCK(); + WRITE_REG(RTC->TIME, tmp); + RTC_LOCK(); + + tmp = ald_get_tick(); + + while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) { + if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) + return TIMEOUT; + } + + return OK; +} + +/** + * @brief Set specified date. + * @param date: pointer to a rtc_date_t structure. + * @param format: Data format. + * @retval ALD status. + */ +ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format) +{ + uint32_t tmp; + + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) { + assert_param(IS_RTC_DAY(date->day)); + assert_param(IS_RTC_MONTH(date->month)); + assert_param(IS_RTC_YEAR(date->year)); + + tmp = (dec_to_bcd(date->day)) | + (dec_to_bcd(date->month) << 8) | + (dec_to_bcd(date->year) << 16) | + (dec_to_bcd(date->week) << 24); + } + else { + assert_param(IS_RTC_DAY(bcd_to_dec(date->day))); + assert_param(IS_RTC_MONTH(bcd_to_dec(date->month))); + assert_param(IS_RTC_YEAR(bcd_to_dec(date->year))); + + tmp = date->day | (date->month << 8) | + (date->year << 16) | (date->week << 24); + } + + RTC_UNLOCK(); + WRITE_REG(RTC->DATE, tmp); + RTC_LOCK(); + + tmp = ald_get_tick(); + + while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) { + if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE) + return TIMEOUT; + } + + return OK; +} + +/** + * @brief Get current time. + * @param time: pointer to a rtc_time_t structure. + * @param format: Data format. + * @retval None + */ +void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format) +{ + uint32_t tmp; + + assert_param(time != NULL); + assert_param(IS_RTC_FORMAT(format)); + + time->sub_sec = RTC->SSEC & 0xFFFF; + tmp = RTC->TIME; + + if (format == RTC_FORMAT_DEC) { + time->second = bcd_to_dec(tmp & 0x7F); + time->minute = bcd_to_dec((tmp >> 8) & 0x7F); + time->hour = bcd_to_dec((tmp >> 16) & 0x7F); + } + else { + time->second = tmp & 0x7F; + time->minute = (tmp >> 8) & 0x7F; + time->hour = (tmp >> 16) & 0x7F; + } + + return; +} + +/** + * @brief Get current date. + * @param date: pointer to a rtc_date_t structure. + * @param format: Data format. + * @retval None + */ +void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format) +{ + uint32_t tmp = RTC->DATE; + + assert_param(date != NULL); + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) { + date->day = bcd_to_dec(tmp & 0x3F); + date->month = bcd_to_dec((tmp >> 8) & 0x1F); + date->year = bcd_to_dec((tmp >> 16) & 0xFF); + date->week = bcd_to_dec((tmp >> 24) & 0x7); + } + else { + date->day = tmp & 0x3F; + date->month = (tmp >> 8) & 0x1F; + date->year = (tmp >> 16) & 0xFF; + date->week = (tmp >> 24) & 0x7; + } + + return; +} + +/** + * @brief Get time and date consistency. + * @param date: pointer to a rtc_date_t structure. + * @param time: pointer to a rtc_time_t structure. + * @param format: Data format. + * @retval Status: + * 0 - Consistency + * -1 - Not consistency + */ +int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format) +{ + int32_t nr = 3; + rtc_date_t d_last; + rtc_time_t t_last; + + while (nr--) { + ald_rtc_get_time(&t_last, format); + ald_rtc_get_date(&d_last, format); + ald_rtc_get_time(time, format); + ald_rtc_get_date(date, format); + + if (rtc_consistency_check(&t_last, &d_last, time, date)) + return 0; + } + + return -1; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group3 Alarm functions + * @brief RTC alarm functions + * + * @verbatim + =============================================================================== + ##### Alarm functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the alarm use ald_rtc_set_alarm() function + (+) To read the alarm use ald_rtc_get_alarm() function + + @endverbatim + * @{ + */ + +/** + * @brief Set alarm. + * @param alarm: pointer to rtc_alarm_t struct. + * @param format: Data format. + * @retval None + */ +void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format) +{ + unsigned int tmp, ss_tmp; + + assert_param(IS_RTC_ALARM(alarm->idx)); + assert_param(IS_RTC_ALARM_SEL(alarm->sel)); + assert_param(IS_RTC_ALARM_SS_MASK(alarm->ss_mask)); + assert_param(IS_RTC_FORMAT(format)); + + if (format == RTC_FORMAT_DEC) { + assert_param(IS_RTC_SECOND(alarm->time.second)); + assert_param(IS_RTC_MINUTE(alarm->time.minute)); + assert_param(IS_RTC_HOUR(alarm->time.hour)); + + tmp = (dec_to_bcd(alarm->time.second)) | + (dec_to_bcd(alarm->time.minute) << 8) | + (dec_to_bcd(alarm->time.hour) << 16) | + alarm->mask; + + if (alarm->sel == RTC_SELECT_DAY) { + assert_param(IS_RTC_DAY(alarm->day)); + + tmp |= (dec_to_bcd(alarm->day) << 24); + tmp &= 0x7FFFFFFF; /* Reset bit31 */ + } + else { + tmp |= (1 << (alarm->week + 24)); + tmp |= 0x80000000; /* Set bit31 */ + } + } + else { + assert_param(IS_RTC_SECOND(bcd_to_dec(alarm->time.second))); + assert_param(IS_RTC_MINUTE(bcd_to_dec(alarm->time.minute))); + assert_param(IS_RTC_HOUR(bcd_to_dec(alarm->time.hour))); + + tmp = alarm->time.second | + (alarm->time.minute << 8) | + (alarm->time.hour << 16) | + alarm->mask; + + if (alarm->sel == RTC_SELECT_DAY) { + assert_param(IS_RTC_DAY(bcd_to_dec(alarm->day))); + + tmp |= (alarm->day << 24); + tmp &= 0x7FFFFFFF; /* Reset bit31 */ + } + else { + tmp |= (1 << (alarm->week + 24)); + tmp |= 0x80000000; /* Set bit31 */ + } + } + + ss_tmp = (alarm->time.sub_sec & 0x7F) | + (alarm->ss_mask << 24); + + RTC_UNLOCK(); + + if (alarm->idx == RTC_ALARM_A) { + WRITE_REG(RTC->ALMA, tmp); + WRITE_REG(RTC->ALMASSEC, ss_tmp); + SET_BIT(RTC->CON, RTC_CON_ALMAEN_MSK); + } + else { + WRITE_REG(RTC->ALMB, tmp); + WRITE_REG(RTC->ALMBSSEC, ss_tmp); + SET_BIT(RTC->CON, RTC_CON_ALMBEN_MSK); + } + + RTC_LOCK(); + return; +} + +/** + * @brief Get alarm parameters. + * @param alarm: pointer to rtc_alarm_t struct. + * @param format: Data format. + * @retval None + */ +void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format) +{ + uint8_t week; + uint32_t tmp, ss_tmp; + + assert_param(alarm != NULL); + assert_param(IS_RTC_FORMAT(format)); + + if (alarm->idx == RTC_ALARM_A) { + tmp = RTC->ALMA; + ss_tmp = RTC->ALMASSEC; + } + else { + tmp = RTC->ALMB; + ss_tmp = RTC->ALMBSSEC; + } + + if ((tmp >> 31) & 0x1) { + alarm->sel = RTC_SELECT_WEEK; + week = ((tmp >> 24) & 0x7F); + + switch (week) { + case 1: + alarm->week = 0; + break; + case 2: + alarm->week = 1; + break; + case 4: + alarm->week = 2; + break; + case 8: + alarm->week = 3; + break; + case 16: + alarm->week = 4; + break; + case 32: + alarm->week = 5; + break; + case 64: + alarm->week = 6; + break; + default: + break; + } + } + else { + alarm->sel = RTC_SELECT_DAY; + + if (format == RTC_FORMAT_DEC) + alarm->day = bcd_to_dec((tmp >> 24) & 0x3F); + else + alarm->day = (tmp >> 24) & 0x3F; + } + + if (format == RTC_FORMAT_DEC) { + alarm->time.second = bcd_to_dec(tmp & 0x7F); + alarm->time.minute = bcd_to_dec((tmp >> 8) & 0x7F); + alarm->time.hour = bcd_to_dec((tmp >> 16) & 0x3F); + } + else { + alarm->time.second = tmp & 0x7F; + alarm->time.minute = (tmp >> 8) & 0x7F; + alarm->time.hour = (tmp >> 16) & 0x3F; + } + + alarm->time.sub_sec = ss_tmp & 0x7FFF; + alarm->ss_mask = (rtc_sub_second_mask_t)((ss_tmp >> 24) & 0xF); + alarm->mask = tmp & ALARM_MASK_ALL; + + return; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group4 Time stamp functions + * @brief RTC time stamp functions + * + * @verbatim + =============================================================================== + ##### Time stamp functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the time stamp use ald_rtc_set_time_stamp() function + (+) To read the time stamp use ald_rtc_get_time_stamp() function + (+) To cancel the time stamp use ald_rtc_cancel_time_stamp() function + + @endverbatim + * @{ + */ + +/** + * @brief Set time stamp. + * @param sel: time stamp signal select: + * @arg RTC_TS_SIGNAL_SEL_TAMPER0 + * @arg RTC_TS_SIGNAL_SEL_TAMPER1 + * @param style: time stamp trigger style: + * @arg RTC_TS_RISING_EDGE + * @arg RTC_TS_FALLING_EDGE + * @retval None + */ +void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style) +{ + assert_param(IS_RTC_TS_SIGNAL(sel)); + assert_param(IS_RTC_TS_STYLE(style)); + + RTC_UNLOCK(); + + CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); + MODIFY_REG(RTC->CON, RTC_CON_TSSEL_MSK, style << RTC_CON_TSSEL_POS); + MODIFY_REG(RTC->CON, RTC_CON_TSPIN_MSK, sel << RTC_CON_TSPIN_POS); + SET_BIT(RTC->CON, RTC_CON_TSEN_MSK); + + RTC_LOCK(); + return; +} + +/** + * @brief Cancel time stamp. + * @retval None + */ +void ald_rtc_cancel_time_stamp(void) +{ + RTC_UNLOCK(); + CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK); + RTC_LOCK(); + + return; +} + +/** + * @brief Get time stamp value. + * @param ts_time: pointer to rtc_time_t structure. + * @param ts_date: pointer to rtc_date_t structure. + * @param format: Data format. + * @retval None + */ +void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format) +{ + uint32_t tmp0, tmp1; + + assert_param(ts_time != NULL); + assert_param(ts_date != NULL); + assert_param(IS_RTC_FORMAT(format)); + + ts_time->sub_sec = RTC->TSSSEC & 0xFFFF; + tmp0 = RTC->TSTIME; + tmp1 = RTC->TSDATE; + + if (format == RTC_FORMAT_DEC) { + ts_time->second = bcd_to_dec(tmp0 & 0x7F); + ts_time->minute = bcd_to_dec((tmp0 >> 8) & 0x7F); + ts_time->hour = bcd_to_dec((tmp0 >> 16) & 0x3F); + ts_date->day = bcd_to_dec(tmp1 & 0x3F); + ts_date->month = bcd_to_dec((tmp1 >> 8) & 0x1F); + ts_date->year = bcd_to_dec((tmp1 >> 16) & 0xFF); + ts_date->week = bcd_to_dec((tmp1 >> 24) & 0x7); + } + else { + ts_time->second = tmp0 & 0x7F; + ts_time->minute = (tmp0 >> 8) & 0x7F; + ts_time->hour = (tmp0 >> 16) & 0x3F; + ts_date->day = tmp1 & 0x3F; + ts_date->month = (tmp1 >> 8) & 0x1F; + ts_date->year = (tmp1 >> 16) & 0xFF; + ts_date->week = (tmp1 >> 24) & 0x7; + } + + return; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group5 Tamper functions + * @brief RTC tamper functions + * + * @verbatim + =============================================================================== + ##### Tamper functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the tamper use ald_rtc_set_tamper() function + (+) To cancel the tamper use ald_rtc_alarm_cmd() function + + @endverbatim + * @{ + */ +/** + * @brief Set tamper parameters. + * @param tamper: pointer to rtc_tamper_t structure. + * @retval None + */ +void ald_rtc_set_tamper(rtc_tamper_t *tamper) +{ + assert_param(IS_RTC_TAMPER(tamper->idx)); + assert_param(IS_RTC_TAMPER_TRIGGER(tamper->trig)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(tamper->freq)); + assert_param(IS_RTC_TAMPER_DURATION(tamper->dur)); + assert_param(IS_FUNC_STATE(tamper->ts)); + + RTC_UNLOCK(); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPTS_MSK, tamper->ts << RTC_TAMPCON_TAMPTS_POS); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPCKS_MSK, tamper->freq << RTC_TAMPCON_TAMPCKS_POSS); + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPFLT_MSK, tamper->dur << RTC_TAMPCON_TAMPFLT_POSS); + + if (tamper->idx == RTC_TAMPER_0) { + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP0LV_MSK, tamper->trig << RTC_TAMPCON_TAMP0LV_POS); + SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP0EN_MSK); + } + else { + MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP1LV_MSK, tamper->trig << RTC_TAMPCON_TAMP1LV_POS); + SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); + } + + RTC_LOCK(); + return; +} + +/** + * @brief Cancel tamper. + * @param idx: index of tamper: + * @arg RTC_TAMPER_0 + * @arg RTC_TAMPER_1 + * @retval None + */ +void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx) +{ + assert_param(IS_RTC_TAMPER(idx)); + + RTC_UNLOCK(); + + if (idx == RTC_TAMPER_0) + CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP0EN_MSK); + else + CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK); + + RTC_LOCK(); + return; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group6 Wake-up functions + * @brief RTC wake-up functions + * + * @verbatim + =============================================================================== + ##### Wake-up functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the wake-up parameters use ald_rtc_set_wakeup() function + (+) To read the re-load register value use ald_rtc_get_wakeup_timer_value() function + (+) To cancel the wake-up use ald_rtc_cancel_wakeup() function + + @endverbatim + * @{ + */ +/** + * @brief Set wake-up parameters. + * @param clock: pointer to rtc_wakeup_clock_t structure. + * @param value: re-load value. + * @retval None + */ +void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value) +{ + assert_param(IS_RTC_WAKEUP_CLOCK(clock)); + + RTC_UNLOCK(); + MODIFY_REG(RTC->CON, RTC_CON_WUCKS_MSK, clock << RTC_CON_WUCKS_POSS); + WRITE_REG(RTC->WUMAT, value & 0xFFFF); + SET_BIT(RTC->CON, RTC_CON_WUTE_MSK); + RTC_LOCK(); + + return; +} + +/** + * @brief Cancel wake-up. + * @retval None + */ +void ald_rtc_cancel_wakeup(void) +{ + RTC_UNLOCK(); + CLEAR_BIT(RTC->CON, RTC_CON_WUTE_MSK); + RTC_LOCK(); + + return; +} + +/** + * @brief Get wake-up re-load register value. + * @retval Value of re-load register. + */ +uint16_t ald_rtc_get_wakeup_timer_value(void) +{ + return RTC->WUMAT & 0xFFFF; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group7 Clock output functions + * @brief RTC clock output functions + * + * @verbatim + =============================================================================== + ##### Clock output functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) To configure the clock output type use ald_rtc_set_clock_output() function + (+) To cancel the clock output use ald_rtc_cancel_clock_output() function + + @endverbatim + * @{ + */ +/** + * @brief Set clock output parameters. + * @param clock: pointer to rtc_clock_output_t structure. + * @retval ALD status. + */ +ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock) +{ + uint32_t cnt = 4000; + assert_param(IS_RTC_CLOCK_OUTPUT(clock)); + + SYSCFG_UNLOCK(); + + if (clock == RTC_CLOCK_OUTPUT_EXA_1) { + SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2LCKN_MSK)) && (--cnt)); + cnt = 4000; + while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL2RDY_MSK))) && (--cnt)); + } + else { + CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK); + } + + SYSCFG_LOCK(); + RTC_UNLOCK(); + MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, clock << RTC_CON_CKOS_POSS); + SET_BIT(RTC->CON, RTC_CON_CKOE_MSK); + RTC_LOCK(); + + return OK; +} + +/** + * @brief Cancel clock output. + * @retval None + */ +void ald_rtc_cancel_clock_output(void) +{ + RTC_UNLOCK(); + CLEAR_BIT(RTC->CON, RTC_CON_CKOE_MSK); + RTC_LOCK(); + + return; +} +/** + * @} + */ + +/** @defgroup RTC_Public_Functions_Group8 Control functions + * @brief RTC control functions + * + * @verbatim + =============================================================================== + ##### Control functions ##### + =============================================================================== + + [..] This section provides functions allowing: + [#] + (+) Configure interrupt enable/disable. + (+) Enable/disable alarm. + (+) Configure rtc shift. + (+) Calibrate time. + (+) Get interrupt source status. + (+) Get interrupt flag status. + (+) Clear interrupt flag. + + @endverbatim + * @{ + */ +/** + * @brief Enable/disable the specified RTC interrupts. + * @param it: Specifies the RTC interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref rtc_it_t. + * @param state: New state of the specified RTC interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state) +{ + assert_param(IS_RTC_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + RTC_UNLOCK(); + + if (state == ENABLE) + SET_BIT(RTC->IER, it); + else + CLEAR_BIT(RTC->IER, it); + + RTC_LOCK(); + return; +} + +/** + * @brief Enable/Disable alarm. + * @param idx: index of alarm: + * @arg RTC_ALARM_A + * @arg RTC_ALARM_B + * @param state: New status of the specified alarm: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state) +{ + assert_param(IS_RTC_ALARM(idx)); + assert_param(IS_FUNC_STATE(state)); + + RTC_UNLOCK(); + + if (idx == RTC_ALARM_A) + MODIFY_REG(RTC->CON, RTC_CON_ALMAEN_MSK, state << RTC_CON_ALMAEN_POS); + else + MODIFY_REG(RTC->CON, RTC_CON_ALMBEN_MSK, state << RTC_CON_ALMBEN_POS); + + RTC_LOCK(); + return; +} + +/** + * @brief Set shift parameters. + * @param add_1s: Enable/Disable added 1 second. + * @param sub_ss: value of sub-sconde. + * @retval ALD status. + */ +ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss) +{ + uint32_t tick; + + assert_param(IS_FUNC_STATE(add_1s)); + assert_param(IS_SHIFT_SUB_SS(sub_ss)); + + RTC_UNLOCK(); + MODIFY_REG(RTC->SSECTR, RTC_SSECTR_TRIM_MSK, sub_ss << RTC_SSECTR_TRIM_POSS); + MODIFY_REG(RTC->SSECTR, RTC_SSECTR_INC_MSK, add_1s << RTC_SSECTR_INC_POS); + RTC_LOCK(); + + tick = ald_get_tick(); + + while (READ_BIT(RTC->CON, RTC_CON_SSEC_MSK)) { + if ((ald_get_tick() - tick) > RTC_TIMEOUT_VALUE) + return TIMEOUT; + } + + return OK; +} + +/** + * @brief Set calibation + * @param config: pointer to rtc_cali_t structure. + * @retval None + */ +void ald_rtc_set_cali(rtc_cali_t *config) +{ + assert_param(IS_RTC_CALI_FREQ(config->cali_freq)); + assert_param(IS_RTC_CALI_TC(config->tc)); + assert_param(IS_RTC_CALC_FREQ(config->calc_freq)); + assert_param(IS_RTC_CALI_CALC(config->calc)); + assert_param(IS_FUNC_STATE(config->acc)); + + RTC_UNLOCK(); + RTC_CALI_UNLOCK(); + + MODIFY_REG(RTC->CALCON, RTC_CALCON_CALP_MSK, config->cali_freq << RTC_CALCON_CALP_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, config->tc << RTC_CALCON_TCM_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCP_MSK, config->calc_freq << RTC_CALCON_TCP_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_ALG_MSK, config->calc << RTC_CALCON_ALG_POS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_DCMACC_MSK, config->acc << RTC_CALCON_DCMACC_POS); + SET_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); + + RTC_CALI_LOCK(); + RTC_LOCK(); + + return; +} + +/** + * @brief Cancel calibration + * @retval None + */ +void ald_rtc_cancel_cali(void) +{ + RTC_CALI_UNLOCK(); + CLEAR_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK); + RTC_CALI_LOCK(); + + return; +} + +/** + * @brief Get calibration status. + * @retval ALD status. + */ +ald_status_t ald_rtc_get_cali_status(void) +{ + if (READ_BIT(RTC->CALCON, RTC_CALCON_ERR_MSK)) + return ERROR; + else + return OK; +} + +/** + * @brief Write temperature value. + * @param temp: the value of temperature. + * @retval None + */ +void ald_rtc_write_temp(uint16_t temp) +{ + RTC_CALI_UNLOCK(); + MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, temp << RTC_TEMPR_VAL_POSS); + RTC_CALI_LOCK(); + + return; +} + +/** + * @brief Get the status of RTC interrupt source. + * @param it: Specifies the RTC interrupt source. + * This parameter can be one of the @ref rtc_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_rtc_get_it_status(rtc_it_t it) +{ + assert_param(IS_RTC_IT(it)); + + if (READ_BIT(RTC->IER, it)) + return SET; + + return RESET; +} + +/** + * @brief Get the status of RTC interrupt flag. + * @param flag: Specifies the RTC interrupt flag. + * This parameter can be one of the @ref rtc_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag) +{ + assert_param(IS_RTC_IF(flag)); + + if ((READ_BIT(RTC->IER, flag)) && (READ_BIT(RTC->ISR, flag))) + return SET; + + return RESET; +} + +/** @brief Clear the specified RTC pending flag. + * @param flag: specifies the flag to check. + * @retval None. + */ +void ald_rtc_clear_flag_status(rtc_flag_t flag) +{ + assert_param(IS_RTC_IF(flag)); + + RTC_UNLOCK(); + WRITE_REG(RTC->IFCR, flag); + RTC_LOCK(); + + return; +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_RTC */ +/** + * @} + */ +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_rtchw.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_rtchw.c new file mode 100644 index 00000000..64e91792 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_rtchw.c @@ -0,0 +1,224 @@ +/** + ****************************************************************************** + * @file ald_rtchw.c + * @brief RTCHW module driver. + * This file provides firmware functions to manage the following + * functionalities of the RTC peripheral: + * + Calibration functions + * @version V1.0 + * @date 25 Apr 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 25 Apr 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_conf.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup RTCHW RTCHW + * @brief RTCHW module driver + * @{ + */ +#ifdef ALD_RTC + +/** @addtogroup RTCHW_Private_Functions RTCHW Private Functions + * @{ + */ +/** + * @brief delay losc clock + * @param u: clock numbers. + * @retval None. + */ +static void delay_losc_clk(uint16_t u) +{ + uint16_t i, j; + + for (i = 0; i < u; i++) { + for (j = 0; j < 60; j++) { + __ASM volatile ("nop"); + } + } +} + +/** + * @brief Check parameter for calibation + * @param config: pointer to rtc_hw_cali_offset_t structure. + * @param mode: Running mode, see @ref rtc_hw_cali_mode_t. + * @retval Status. + */ +static uint8_t rtc_hw_auto_check(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode) +{ + uint8_t tom = READ_BITS(TSENSE->CR, TSENSE_CR_TOM_MSK, TSENSE_CR_TOM_POSS); + uint8_t shift[8] = {0, 2, 4, 6, 8, 8, 8, 8}; + + if (mode == RTC_CALI_MODE_NORMAL) { + if ((RTC->CALCON & 0x1F3000F) != (RTCINFO->RTC_CALCR & 0x1F3000F)) + return 1; + } + else { + if ((RTC->CALCON & 0x183000F) != (RTCINFO->RTC_CALCR & 0x183000F)) + return 1; + + if (READ_BITS(RTC->CALCON, RTC_CALCON_TCP_MSK, RTC_CALCON_TCP_POSS) != 7) /* when sleep mode */ + return 1; + } + + if ((TSENSE->CR & 0x7702) != (RTCINFO->TEMP_CR & 0x7702)) + return 1; + if (RTC->TEMPBDR != RTCINFO->RTC_TEMPBDR + config->offset_rtc_bdr) + return 1; + if (RTC->LTAXR != RTCINFO->RTC_LTAXR + config->offset_ltaxr) + return 1; + if (RTC->HTAXR != RTCINFO->RTC_HTAXR + config->offset_htaxr) + return 1; + if (RTC->HTAXR != RTCINFO->RTC_HTCAR + config->offset_htcar) + return 1; + if (RTC->HTCBR != RTCINFO->RTC_HTCBR + config->offset_htcbr) + return 1; + if (RTC->HTCCR != RTCINFO->RTC_HTCCR + config->offset_htccr) + return 1; + if (RTC->HTCDR != RTCINFO->RTC_HTCDR + config->offset_htcdr) + return 1; + if (RTC->HTCER != RTCINFO->RTC_HTCER + config->offset_htcer) + return 1; + if (RTC->LTAXR != RTCINFO->RTC_LTCAR + config->offset_ltcar) + return 1; + if (RTC->LTCBR != RTCINFO->RTC_LTCBR + config->offset_ltcbr) + return 1; + if (RTC->LTCCR != RTCINFO->RTC_LTCCR + config->offset_ltccr) + return 1; + if (RTC->LTCDR != RTCINFO->RTC_LTCDR + config->offset_ltcdr) + return 1; + if (RTC->LTCER != RTCINFO->RTC_LTCER + config->offset_ltcer) + return 1; + if (TSENSE->TBDR != (RTCINFO->TEMP_TBDR & 0xFFFF) + config->offset_temp_bdr) + return 1; + if (TSENSE->LTGR != RTCINFO->TEMP_LTGR + config->offset_ltgr) + return 1; + if (TSENSE->HTGR != RTCINFO->TEMP_HTGR + config->offset_htgr) + return 1; + if (TSENSE->TCALBDR != (((RTCINFO->TEMP_TCALBDR & 0x1FFFFFF) >> shift[tom]) & 0x1FFFF) + + config->offset_tcalbdr) + return 1; + + return 0; +} +/** + * @} + */ + +/** @defgroup RTCHW_Public_Functions RTCHW Public Functions + * @{ + */ +/** + * @brief Hardware automatic calibate + * @param config: pointer to rtc_hw_cali_offset_t structure. + * @param mode: Running mode, see @ref rtc_hw_cali_mode_t + * @retval None + */ +void ald_rtc_hw_auto_cali(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode) +{ + uint8_t shift[8] = {0, 2, 4, 6, 8, 8, 8, 8}; + uint8_t tmp; + uint32_t v = 0; + uint16_t temp_calf; + + if (!(rtc_hw_auto_check(config, mode))) + return; + + RTC_UNLOCK(); + RTC_CALI_UNLOCK(); + TSENSE_UNLOCK(); + + temp_calf = (uint16_t)RTC->CALDR; + while ((READ_BITS(RTC->IFR, RTC_IFR_TCCF_MSK, RTC_IFR_TCCF_POS) == 1) && (v < 0x20000)) /* no usr trig */ + v++; + + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, 0 << RTC_CALCON_TCM_POSS); /* disable auto compensation */ + MODIFY_REG(TSENSE->CR, TSENSE_CR_REQEN_MSK, 0 << TSENSE_CR_REQEN_POS); /* disable temp */ + + RTC->CALDR = temp_calf; + delay_losc_clk(3); + + if (mode == RTC_CALI_MODE_NORMAL) { + v = RTC->CALCON & ~0x01F0000F; + RTC->CALCON = v | (RTCINFO->RTC_CALCR & 0x01F0000F); + } + else { + v = RTC->CALCON & ~0x0180000F; + RTC->CALCON = v | (RTCINFO->RTC_CALCR & 0x0180000F); + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCP_MSK, 7 << RTC_CALCON_TCP_POSS); // when sleep mode, caluate once in 1h + } + + RTC->TEMPBDR = RTCINFO->RTC_TEMPBDR + config->offset_rtc_bdr; + RTC->LTAXR = RTCINFO->RTC_LTAXR + config->offset_ltaxr; + RTC->HTAXR = RTCINFO->RTC_HTAXR + config->offset_htaxr; + RTC->LTCAR = RTCINFO->RTC_LTCAR + config->offset_ltcar; + RTC->LTCBR = RTCINFO->RTC_LTCBR + config->offset_ltcbr; + RTC->LTCCR = RTCINFO->RTC_LTCCR + config->offset_ltccr; + RTC->LTCDR = RTCINFO->RTC_LTCDR + config->offset_ltcdr; + RTC->LTCER = RTCINFO->RTC_LTCER + config->offset_ltcer; + RTC->HTCAR = RTCINFO->RTC_HTCAR + config->offset_htcar; + RTC->HTCBR = RTCINFO->RTC_HTCBR + config->offset_htcbr; + RTC->HTCCR = RTCINFO->RTC_HTCCR + config->offset_htccr; + RTC->HTCDR = RTCINFO->RTC_HTCDR + config->offset_htcdr; + RTC->HTCER = RTCINFO->RTC_HTCER + config->offset_htcer; + MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, 5 << RTC_CON_CKOS_POSS); /* output accuracy 1Hz */ + + v = TSENSE->CR & ~0x00007700; + TSENSE->CR = v | (RTCINFO->TEMP_CR & 0x00007700); + TSENSE->HTGR = RTCINFO->TEMP_HTGR + config->offset_htgr; + TSENSE->LTGR = RTCINFO->TEMP_LTGR + config->offset_ltgr; + tmp = READ_BITS(RTCINFO->TEMP_CR, TSENSE_CR_TOM_MSK, TSENSE_CR_TOM_POSS); + TSENSE->TCALBDR = ((RTCINFO->TEMP_TCALBDR & 0x1FFFFFF) >> shift[tmp]) + config->offset_tcalbdr; + TSENSE->TBDR = RTCINFO->TEMP_TBDR + config->offset_temp_bdr; + + delay_losc_clk(3); + tmp = READ_BITS(RTCINFO->TEMP_CR, TSENSE_CR_REQEN_MSK, TSENSE_CR_REQEN_POS); + MODIFY_REG(TSENSE->CR, TSENSE_CR_REQEN_MSK, tmp << TSENSE_CR_REQEN_POS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, 3 << RTC_CALCON_TCM_POSS); /* usr trig */ + + delay_losc_clk(3); + MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, 1 << RTC_TEMPR_VAL_POSS); /* trig immediate*/ + + delay_losc_clk(3); + tmp = READ_BITS(RTCINFO->RTC_CALCR, RTC_CALCON_TCM_MSK, RTC_CALCON_TCM_POSS); + MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, tmp << RTC_CALCON_TCM_POSS); + + RTC_CALI_LOCK(); + RTC_LOCK(); + TSENSE_LOCK(); + return; +} +/** + * @} + */ +#endif /* ALD_RTC */ +/** + * @} + */ +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_spi.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_spi.c new file mode 100644 index 00000000..594389db --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_spi.c @@ -0,0 +1,2022 @@ +/** + ********************************************************************************* + * + * @file ald_spi.c + * @brief SPI module driver. + * This file provides firmware functions to manage the following + * functionalities of SPI peripheral: + * + Initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + * @version V1.0 + * @date 13 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 13 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI driver can be used as follows: + + (#) Declare a spi_handle_t structure, for example: + spi_handle_t hperh; + + (#) Initialize the SPI low level resources: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as push-pull + (##) NVIC configuration if you need to use interrupt process + by implementing the ald_mcu_irq_config() API. + Invoked ald_spi_irq_handler() function in SPI-IRQ function + (##) DMA Configuration if you need to use DMA process + (+++) Define ALD_DMA in ald_conf.h + (+++) Enable the DMAx clock + + (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI module by invoking the ald_spi_init() API. + + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the ald_spi_dma_pause()/ ald_spi_dma_stop(). + + * @endverbatim + */ + +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI module driver + * @{ + */ +#ifdef ALD_SPI + +/** @addtogroup SPI_Private_Functions SPI Private Functions + * @{ + */ + +static void __spi_send_by_it(spi_handle_t *hperh); +static void __spi_recv_by_it(spi_handle_t *hperh); +static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status); +#ifdef ALD_DMA +static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout); +static void spi_dma_send_cplt(void *arg); +static void spi_dma_recv_cplt(void *arg); +static void spi_dma_send_recv_cplt(void *arg); +#endif +/** + * @} + */ + +/** @defgroup SPI_Public_Functions SPI Public Functions + * @{ + */ + +/** @defgroup SPI_Public_Functions_Group1 Initialization functions + * @brief Initialization and Configuration functions + * + * @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + reset the SPIx peripheral: + + (+) User must configure all related peripherals resources + (CLOCK, GPIO, DMA, NVIC). + + (+) Call the function ald_spi_init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + + (+) Call the function ald_spi_reset() to reset the selected SPIx periperal. + + @endverbatim + * @{ + */ + +/** + * @brief Reset the SPI peripheral. + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +void ald_spi_reset(spi_handle_t *hperh) +{ + SPI_DISABLE(hperh); + hperh->perh->CON1 = 0x0; + hperh->perh->CON2 = 0x0; + hperh->perh->CRCPOLY = 0x00000007; + + SPI_RESET_HANDLE_STATE(hperh); + __UNLOCK(hperh); + + return; +} + +/** + * @brief Initializes the SPI mode according to the specified parameters in + * the SPI_init_t and create the associated handle. + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_init(spi_handle_t *hperh) +{ + uint32_t tmp = 0; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_MODE(hperh->init.mode)); + assert_param(IS_SPI_DIRECTION(hperh->init.dir)); + assert_param(IS_SPI_BAUD(hperh->init.baud)); + assert_param(IS_SPI_FIRBIT(hperh->init.first_bit)); + assert_param(IS_FUNC_STATE(hperh->init.ss_en)); + assert_param(IS_FUNC_STATE(hperh->init.crc_calc)); + assert_param(IS_SPI_DATASIZE(hperh->init.data_size)); + assert_param(IS_SPI_CPHA(hperh->init.phase)); + assert_param(IS_SPI_CPOL(hperh->init.polarity)); + assert_param(IS_SPI_FRAME(hperh->init.frame)); + + ald_spi_reset(hperh); + tmp = hperh->perh->CON1; + + if (hperh->init.mode == SPI_MODE_MASTER) + tmp |= 1 << SPI_CON1_SSOUT_POS; + + tmp |= ((hperh->init.phase << SPI_CON1_CPHA_POS) | (hperh->init.polarity << SPI_CON1_CPOL_POS) | + (hperh->init.baud << SPI_CON1_BAUD_POSS) | (hperh->init.data_size << SPI_CON1_FLEN_POS) | + (hperh->init.mode << SPI_CON1_MSTREN_POS) | (hperh->init.ss_en << SPI_CON1_SSEN_POS) | + (hperh->init.first_bit << SPI_CON1_LSBFST_POS)); + + hperh->perh->CON1 = tmp; + + MODIFY_REG(hperh->perh->CON2, SPI_CON2_FRF_MSK, hperh->init.frame << SPI_CON2_FRF_POS); + + if (hperh->init.dir == SPI_DIRECTION_2LINES) { + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); + } + else if (hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) { + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + SET_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK); + } + else if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) { + SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDOEN_MSK); + } + else { + SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK); + SET_BIT(hperh->perh->CON1, SPI_CON1_BIDOEN_MSK); + } + + /* configure CRC */ + hperh->perh->CON1 |= (hperh->init.crc_calc << SPI_CON1_CRCEN_POS); + hperh->perh->CRCPOLY = hperh->init.crc_poly; + + hperh->err_code = SPI_ERROR_NONE; + hperh->state = SPI_STATE_READY; + + SPI_ENABLE(hperh); + return OK; +} + +/** + * @brief Config the fifo threshold + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @param threshold: The threshold value of fifo. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t spi_fifo_threshold_config(spi_handle_t *hperh, uint8_t threshold) +{ + assert_param(IS_SPI(hperh->perh)); + + MODIFY_REG(hperh->perh->CON2, SPI_CON2_RXFTH_MSK, threshold << SPI_CON2_RXFTH_POSS); + MODIFY_REG(hperh->perh->CON2, SPI_CON2_TXFTH_MSK, threshold << SPI_CON2_TXFTH_POSS); + + return OK; +} +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group2 IO fast functions + * @brief SPI Transmit and Receive functions + * + * @verbatim + ============================================================================== + ##### IO fast functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the SPI + data transfers fast. + + * @endverbatim + * @{ + */ + +/** + * @brief Transmit one byte fast in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param data: Data to be sent + * @retval status: + * - 0 Success + * - -1 Failed + */ +int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data) +{ + uint16_t cnt = 5000, temp; + + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = data; + while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt)); + + cnt = 5000; + while (((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) && (--cnt)); + temp = hperh->perh->DATA; + UNUSED(temp); + + return cnt == 0 ? -1 : 0; +} + +/** + * @brief Transmit one byte fast in blocking mode(1line). + * @param hperh: Pointer to a spi_handle_t structure. + * @param data: Data to be sent + * @retval status: + * - 0 Success + * - -1 Failed + */ +int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data) +{ + uint16_t cnt = 5000; + + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = data; + while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt)); + + return cnt == 0 ? -1 : 0; +} + +/** + * @brief Receive one byte fast in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param status: Status, success[0]/failed[-1] + * @retval Data. + */ +uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh, int *status) +{ + uint16_t cnt = 5000; + + if (hperh->init.mode == SPI_MODE_MASTER) { + hperh->perh->DATA = 0xFF; + while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt)); + } + + cnt = 5000; + while (((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) && (--cnt)); + *status = cnt == 0 ? - 1 : 0; + + return (uint8_t)hperh->perh->DATA; +} + +/** + * @brief Transmit some bytes fast in blocking mode. + * @note Bit width is 8-bits. Supports mode: Master/Slave. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be sent. + * @param size: Length of data. + * @param timeout: Timeout between two bytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_send_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t i, tmp = 0; + + while (size--) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *buf++; + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + } + + for (i = 0; i < 16; ++i) { + if ((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) + tmp = hperh->perh->DATA; + else + break; + } + + UNUSED(tmp); + return OK; +} + +/** + * @brief Receive some bytes fast in blocking mode. + * @note Bit width is 8-bits. Supports mode: Master. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be received. + * @param size: Length of data. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_master_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + uint16_t cnt = 8000; + + while (size--) { + hperh->perh->DATA = 0xFF; + cnt = 8000; + while (((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) && (--cnt)); + + if (cnt) + *buf++ = (uint8_t)hperh->perh->DATA; + else + return TIMEOUT; + } + + return OK; +} + +/** + * @brief Receive some bytes fast in blocking mode. + * @note Bit width is 8-bits. Supports mode: Slave. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be received. + * @param size: Length of data. + * @param timeout: Timeout between two bytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_slave_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t tick; + + while (size--) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + + *buf++ = (uint8_t)hperh->perh->DATA; + } + + return OK; +} + +/** + * @brief Transmit some double-bytes fast in blocking mode. + * @note Bit width is 16-bits. Supports mode: Master/Slave. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be sent. + * @param size: Length of data. Unit is double-bytes. + * @param timeout: Timeout between two dbytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_send_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t i, tmp = 0; + + while (size--) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)buf); + buf += 2; + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + } + + for (i = 0; i < 16; ++i) { + if ((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) + tmp = hperh->perh->DATA; + else + break; + } + + UNUSED(tmp); + return OK; +} + +/** + * @brief Receive some double-bytes fast in blocking mode. + * @note Bit width is 16-bits. Supports mode: Master. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be received. + * @param size: Length of data. Unit is double-bytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_master_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size) +{ + uint16_t cnt = 8000; + + while (size--) { + hperh->perh->DATA = 0xFFFF; + cnt = 8000; + while (((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) && (--cnt)); + + if (cnt) { + *(uint16_t *)buf = (uint16_t)hperh->perh->DATA; + buf += 2; + } + else { + return TIMEOUT; + } + } + + return OK; +} + +/** + * @brief Receive some double-bytes fast in blocking mode. + * @note Bit width is 16-bits. Supports mode: Slave. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Data to be received. + * @param size: Length of data. Unit is double-bytes. + * @param timeout: Timeout between two dbytes. + * @retval status: OK/TIMEOUT + */ +ald_status_t ald_spi_slave_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint32_t tick; + + while (size--) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + + *(uint16_t *)buf = (uint16_t)hperh->perh->DATA; + buf += 2; + } + + return OK; +} +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group3 IO operation functions + * @brief SPI Transmit and Receive functions + * + * @verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master or slave mode: + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The ALD status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the ALD status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() and hperh->tx_rx_cplt_cbk() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The hperh->err_cbk() user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + + * @endverbatim + * @{ + */ +/** + * @brief Transmit an amount of data in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t temp; + + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + hperh->state = SPI_STATE_BUSY_TX; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + while (size > 1) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *buf; + ++buf; + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)buf); + buf += 2; + } + + --size; + } + + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.crc_calc) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *buf; + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)buf); + } + + SPI_CRCNEXT_ENABLE(hperh); + } + else { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *buf; + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)buf); + } + } + + while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + while ((hperh->perh->STAT & SPI_STATUS_BUSY) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + while ((spi_get_status(hperh, SPI_STATUS_RXE)) == RESET) { + temp = hperh->perh->DATA; + UNUSED(temp); + } + + hperh->state = SPI_STATE_READY; + return OK; +timeout: + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + return TIMEOUT; +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t temp; + + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + if (hperh->init.mode == SPI_MODE_MASTER) + return ald_spi_send_recv(hperh, buf, buf, size, timeout); + + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + while (size > 0) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STATUS_RXE) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *buf = hperh->perh->DATA; + ++buf; + } + else { + *(uint16_t *)buf = hperh->perh->DATA; + buf += 2; + } + + --size; + } + + if (hperh->init.crc_calc) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STATUS_RXTH) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + temp = hperh->perh->DATA; + UNUSED(temp); + + if ((hperh->perh->RIF & SPI_IF_CRCERR) != RESET) { + hperh->err_code |= SPI_ERROR_CRC; + SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + hperh->state = SPI_STATE_READY; + + return ERROR; + } + } + + hperh->state = SPI_STATE_READY; + return OK; + +timeout: + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + return TIMEOUT; +} + +/** + * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). + * @param hperh: Pointer to a spi_handle_t structure. + * @param tx_buf: Pointer to data transmitted buffer + * @param rx_buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout) +{ + uint32_t tick; + uint16_t temp; + + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (hperh->init.dir != SPI_DIRECTION_2LINES) + return ERROR; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ERROR; + + hperh->state = SPI_STATE_BUSY_TX_RX; + hperh->err_code = SPI_ERROR_NONE; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + while (size > 1) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *tx_buf; + ++tx_buf; + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)tx_buf); + tx_buf += 2; + } + + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STATUS_RXE) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *rx_buf = (uint8_t)hperh->perh->DATA; + ++rx_buf; + } + else { + (*(uint16_t *)rx_buf) = hperh->perh->DATA; + rx_buf += 2; + } + + --size; + } + + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *tx_buf; + SPI_CRCNEXT_ENABLE(hperh); + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *tx_buf; + } + } + else { + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)tx_buf); + SPI_CRCNEXT_ENABLE(hperh); + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = (*(uint16_t *)tx_buf); + } + } + + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STATUS_RXE) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + if (hperh->init.data_size == SPI_DATA_SIZE_8) + *rx_buf = (uint8_t)hperh->perh->DATA; + else + (*(uint16_t *)rx_buf) = hperh->perh->DATA; + + if (hperh->init.crc_calc) { + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + tick = ald_get_tick(); + + while ((hperh->perh->STAT & SPI_STATUS_RXE) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + temp = hperh->perh->DATA; + UNUSED(temp); + + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) { + hperh->err_code |= SPI_ERROR_CRC; + SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + hperh->state = SPI_STATE_READY; + + return ERROR; + } + } + + while ((hperh->perh->STAT & SPI_STATUS_BUSY) != RESET) { + if (((ald_get_tick()) - tick) > timeout) + goto timeout; + } + + hperh->state = SPI_STATE_READY; + return OK; +timeout: + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + hperh->state = SPI_STATE_READY; + return TIMEOUT; +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param hperh: pointer to a spi_handle_t structure. + * @param buf: Pointer to data transmitted buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + __UNLOCK(hperh); + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + ald_spi_interrupt_config(hperh, SPI_IT_TXE, ENABLE); + + return OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + __UNLOCK(hperh); + + if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) + SPI_1LINE_RX(hperh); + + if (hperh->init.crc_calc == ENABLE) { + SPI_CRC_RESET(hperh); + ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, ENABLE); + } + + ald_spi_interrupt_config(hperh, SPI_IT_RXTH, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_MODF, ENABLE); + + if (hperh->init.data_size <= SPI_DATA_SIZE_8) { + *((uint8_t *)&(hperh->perh->DATA)) = 0xFF; + } + else { + *((uint16_t *)&(hperh->perh->DATA)) = 0xFFFF; + } + + return OK; +} + +/** + * @brief Transmit and Receives an amount of data in non blocking mode + * @param hperh: Pointer to a spi_handle_t structure that contains + * the configuration information for the specified SPI module. + * @param tx_buf: Pointer to data transmitted buffer + * @param rx_buf: Pointer to data received buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ERROR; + + if (hperh->init.mode == SPI_MODE_SLAVER) { + if ((spi_get_status(hperh, SPI_STATUS_TXE) == RESET) || (spi_get_status(hperh, SPI_STATUS_RXE) == RESET)) { + + if (hperh->perh == SPI0) + ald_rmu_reset_periperal(RMU_PERH_SPI0); + else if (hperh->perh == SPI1) + ald_rmu_reset_periperal(RMU_PERH_SPI1); + else if (hperh->perh == SPI2) + ald_rmu_reset_periperal(RMU_PERH_SPI2); + else + return ERROR; + + ald_spi_reset(hperh); + ald_spi_init(hperh); + } + } + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + __UNLOCK(hperh); + + if (hperh->init.crc_calc) { + SPI_CRC_RESET(hperh); + ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, ENABLE); + } + + if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) + SPI_ENABLE(hperh); + + ald_spi_interrupt_config(hperh, SPI_IT_RXTH, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_TXE, ENABLE); + ald_spi_interrupt_config(hperh, SPI_IT_MODF, ENABLE); + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Transmit an amount of data used dma channel + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as SPI transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_TX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = NULL; + hperh->rx_size = 0; + hperh->rx_count = 0; + + if (hperh->init.dir == SPI_DIRECTION_1LINE) + SPI_1LINE_TX(hperh); + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.cplt_cbk = spi_dma_send_cplt; + + /* Configure SPI DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.channel = channel; + hperh->hdmatx.config.burst = ENABLE; + ald_dma_config_basic(&(hperh->hdmatx)); + + __UNLOCK(hperh); + + if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0) + SPI_ENABLE(hperh); + + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + + return OK; +} + +/** + * @brief Receive an amount of data used dma channel + * @param hperh: Pointer to a spi_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as SPI transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + uint16_t tmp_rx = 0xB1B2; + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY) + return BUSY; + if (buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = size; + hperh->tx_buf = NULL; + hperh->tx_size = 0; + hperh->tx_count = 0; + + if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) + SPI_1LINE_RX(hperh); + if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) { + __UNLOCK(hperh); + return ERROR; + } + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.cplt_cbk = spi_dma_recv_cplt; + + /* Configure SPI DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)&tmp_rx; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.channel = 11; + ald_dma_config_basic(&(hperh->hdmatx)); + + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;; + hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmarx.config.channel = channel; + ald_dma_config_basic(&(hperh->hdmarx)); + + __UNLOCK(hperh); + + if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX)) + SPI_ENABLE(hperh); + + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + + return OK; +} + +/** + * @brief Transmit and Receive an amount of data used dma channel + * @param hperh: Pointer to a spi_handle_t structure. + * @param tx_buf: Pointer to data buffer + * @param rx_buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param tx_channel: DMA channel as SPI transmit + * @param rx_channel: DMA channel as SPI receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel) +{ + assert_param(IS_SPI(hperh->perh)); + + if (hperh->state != SPI_STATE_READY && hperh->state != SPI_STATE_BUSY_RX) + return BUSY; + if (tx_buf == NULL || rx_buf == NULL || size == 0) + return ERROR; + + __LOCK(hperh); + hperh->state = SPI_STATE_BUSY_RX; + hperh->err_code = SPI_ERROR_NONE; + + hperh->tx_buf = tx_buf; + hperh->tx_size = size; + hperh->tx_count = size; + hperh->rx_buf = rx_buf; + hperh->rx_size = size; + hperh->rx_count = size; + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + hperh->hdmatx.cplt_arg = NULL; + hperh->hdmatx.cplt_cbk = NULL; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.cplt_cbk = spi_dma_send_recv_cplt; + + if (hperh->init.crc_calc) + SPI_CRC_RESET(hperh); + + /* Configure SPI DMA transmit */ + ald_dma_config_struct(&(hperh->hdmatx.config)); + hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmatx.config.src = (void *)tx_buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY; + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.channel = tx_channel; + ald_dma_config_basic(&(hperh->hdmatx)); + + /* Configure DMA Receive */ + ald_dma_config_struct(&(hperh->hdmarx.config)); + hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD; + hperh->hdmarx.config.src = (void *)&hperh->perh->DATA; + hperh->hdmarx.config.dst = (void *)rx_buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;; + hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2); + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR; + hperh->hdmarx.config.burst = ENABLE; + hperh->hdmarx.config.channel = rx_channel; + ald_dma_config_basic(&(hperh->hdmarx)); + + __UNLOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + + return OK; +} + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status + */ +ald_status_t ald_spi_dma_pause(spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + + __LOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status + */ +ald_status_t ald_spi_dma_resume(spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + + __LOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status + */ +ald_status_t ald_spi_dma_stop(spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + + __LOCK(hperh); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + __UNLOCK(hperh); + + hperh->state = SPI_STATE_READY; + return OK; +} +#endif +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group4 Control functions + * @brief SPI Control functions + * + * @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) Handle interrupt about SPI module. The ald_spi_irq_handler() function must + be invoked by SPI-IRQ function. + (+) Configure the interrupt DISABLE/ENABLE. + (+) Configure the DMA request. + (+) Get interrupt source status. + (+) Get interrupt flag status. + (+) Clear interrupt flag + + @endverbatim + * @{ + */ + +/** + * @brief This function handles SPI interrupt request. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval None + */ +void ald_spi_irq_handler(spi_handle_t *hperh) +{ + if ((hperh->state == SPI_STATE_BUSY_RX) || (hperh->state == SPI_STATE_BUSY_TX)) { + if ((ald_spi_get_it_status(hperh, SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXTH) != RESET)) + __spi_recv_by_it(hperh); + + if ((ald_spi_get_it_status(hperh, SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXE) != RESET)) + __spi_send_by_it(hperh); + } + + else if (hperh->state == SPI_STATE_BUSY_TX_RX) { + if (hperh->init.mode == SPI_MODE_SLAVER) { + if ((ald_spi_get_it_status(hperh, SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXE) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_TXE); + if ((ald_spi_get_it_status(hperh, SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXTH) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_RXNE); + } + else { + if (hperh->rx_size == hperh->tx_count) { + if ((ald_spi_get_it_status(hperh, SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXE) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_TXE); + } + else { + if ((ald_spi_get_it_status(hperh, SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXE) != RESET) + && (ald_spi_get_it_status(hperh, SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXTH) != RESET)) + __spi_send_recv_by_it(hperh, SPI_SR_TXE_RXNE); + } + } + + } + + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) { + hperh->err_code |= SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + } + if (ald_spi_get_flag_status(hperh, SPI_IF_MODF) != RESET) { + hperh->err_code |= SPI_ERROR_MODF; + ald_spi_clear_flag_status(hperh, SPI_IF_MODF); + } + if (ald_spi_get_flag_status(hperh, SPI_IF_FRE) != RESET) { + hperh->err_code |= SPI_ERROR_FRE; + ald_spi_clear_flag_status(hperh, SPI_IF_FRE); + + } + if (ald_spi_get_flag_status(hperh, SPI_IF_TXOV) != RESET) { + if (hperh->state != SPI_STATE_BUSY_TX) { + hperh->err_code |= SPI_ERROR_TXOV; + ald_spi_clear_flag_status(hperh, SPI_IF_TXOV); + } + } + if (ald_spi_get_flag_status(hperh, SPI_IF_RXOV) != RESET) { + if (hperh->state != SPI_STATE_BUSY_RX) { + hperh->err_code |= SPI_ERROR_RXOV; + ald_spi_clear_flag_status(hperh, SPI_IF_RXOV); + } + } + + return; +} + +/** + * @brief Enables or disables the specified SPI interrupts. + * @param hperh: Pointer to a spi_handle_t structure. + * @param it: Specifies the SPI interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref spi_it_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IER |= (uint32_t)it; + else + hperh->perh->IDR |= (uint32_t)it; + + return; +} + +/** + * @brief Configure the specified SPI speed. + * @param hperh: Pointer to a spi_handle_t structure. + * @param speed: Specifies the SPI speed. + * This parameter can be one of the @ref spi_baud_t. + * @retval None + */ +void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed) +{ + uint32_t tmp = 0; + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_BAUD(speed)); + + tmp = hperh->perh->CON1; + tmp &= ~(0x7U << SPI_CON1_BAUD_POSS); + tmp |= (speed << SPI_CON1_BAUD_POSS); + hperh->perh->CON1 = tmp; + return; +} + +/** + * @brief Enables or disables the dma request. + * @param hperh: Pointer to a spi_handle_t structure. + * @param req: Specifies the SPI dma request sources to be enabled or disabled. + * This parameter can be one of the @ref spi_dma_req_t. + * @param state: New status + * - ENABLE + * - DISABLE + * @retval None + */ +void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) { + if (req == SPI_DMA_REQ_TX) + SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + else { + if (req == SPI_DMA_REQ_TX) + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK); + else + CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK); + } + + return; +} + +/** @brief Check whether the specified SPI state flag is set or not. + * @param hperh: Pointer to a spi_handle_t structure. + * @param status: specifies the flag to check. + * This parameter can be one of the @ref spi_status_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_STATUS(status)); + + if (hperh->perh->STAT & status) + return SET; + + return RESET; +} + +/** + * @brief Checks whether the specified SPI interrupt has occurred or not. + * @param hperh: Pointer to a spi_handle_t structure. + * @param it: Specifies the SPI interrupt source to check. + * This parameter can be one of the @ref spi_it_t. + * @retval Status + * - SET + * - RESET + */ +it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IT(it)); + + if (hperh->perh->IVS & it) + return SET; + + return RESET; +} + +/** @brief Check whether the specified SPI flag is set or not. + * @param hperh: Pointer to a spi_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref spi_flag_t. + * @retval Status + * - SET + * - RESET + */ +flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IF(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** @brief Clear the specified SPI pending flags. + * @param hperh: Pointer to a spi_handle_t structure. + * @param flag: specifies the flag to check. + * This parameter can be one of the @ref spi_flag_t. + * @retval None + */ +void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag) +{ + assert_param(IS_SPI(hperh->perh)); + assert_param(IS_SPI_IF(flag)); + + + hperh->perh->ICR |= flag; + return; +} + +#ifdef ALD_DMA +/** + * @brief This function handles SPI communication timeout in interrupt function. + * @param hperh: Pointer to a spi_handle_t structure. + * @param flag: specifies the SPI flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout) +{ + assert_param(timeout > 0); + + while (((ald_spi_get_flag_status(hperh, flag)) != status) && (--timeout)); + + if (timeout) + return OK; + + ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_MODF, DISABLE); + + return TIMEOUT; +} +#endif + +static ald_status_t spi_wait_bsy_flag(spi_handle_t *hperh, flag_status_t status, uint32_t timeout) +{ + assert_param(timeout > 0); + + while ((READ_BIT(hperh->perh->STAT, SPI_STAT_BUSY_MSK)) && (--timeout)); + + if (timeout) + return OK; + + ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_MODF, DISABLE); + + return TIMEOUT; +} + +/** + * @} + */ + +/** @defgroup SPI_Public_Functions_Group5 Peripheral State and Errors functions + * @brief SPI State and Errors functions + * + * @verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) ald_spi_get_state() API can check in run-time the state of the SPI peripheral + (+) ald_spi_get_error() check in run-time Errors occurring during communication + + @endverbatim + * @{ + */ + +/** + * @brief Returns the SPI state. + * @param hperh: Pointer to a spi_handle_t structure. + * @retval ALD state + */ +spi_state_t ald_spi_get_state(spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + return hperh->state; +} + +/** + * @brief Return the SPI error code + * @param hperh: Pointer to a spi_handle_t structure. + * @retval SPI Error Code + */ +uint32_t ald_spi_get_error(spi_handle_t *hperh) +{ + assert_param(IS_SPI(hperh->perh)); + return hperh->err_code; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Functions SPI Private Functions + * @brief SPI Private functions + * @{ + */ + +/** + * @brief handle program when an tx empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static void __spi_send_by_it(spi_handle_t *hperh) +{ + uint16_t temp; + + if (hperh->tx_count == 0) { + ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE); + hperh->state = SPI_STATE_READY; + + if (hperh->init.dir == SPI_DIRECTION_2LINES) { + ald_spi_clear_flag_status(hperh, SPI_IF_TXOV); + } + + if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != OK) { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + while ((spi_get_status(hperh, SPI_STATUS_RXE)) == RESET) { + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return; + } + + ald_spi_clear_flag_status(hperh, SPI_IF_TXE); + + if (hperh->tx_count == 1) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + SPI_CRCNEXT_ENABLE(hperh); + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + } + + ++hperh->tx_buf; + } + else { + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + SPI_CRCNEXT_ENABLE(hperh); + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + } + + hperh->tx_buf += 2; + } + } + else { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + } + + --hperh->tx_count; + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode + * @param hperh: Pointer to a spi_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static void __spi_recv_by_it(spi_handle_t *hperh) +{ + uint16_t temp; + + while (READ_BITS(hperh->perh->STAT, SPI_STAT_RXFLV_MSK, SPI_STAT_RXFLV_POSS)) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + } + + --hperh->rx_count; + } + + ald_spi_clear_flag_status(hperh, SPI_IF_RXTH); + + if (hperh->rx_count == 0) { + ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE); + hperh->state = SPI_STATE_READY; + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { + hperh->err_code |= SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->init.crc_calc) { + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + if (hperh->init.data_size <= SPI_DATA_SIZE_8) { + hperh->perh->DATA = 0xff; + } + else { + hperh->perh->DATA = 0xffff; + } + + return; +} + +/** + * @brief handle program when an rx no empty interrupt flag arrived in non block mode(2 lines) + * @param hperh: Pointer to a spi_handle_t structure. + * @param status: SR.TXE or SR.RXNE set. + * @retval Status, see @ref ald_status_t. + */ +static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status) +{ + if (hperh->rx_count != 0) { + if ((status == SPI_SR_RXNE) || (status == SPI_SR_TXE_RXNE)) { + ald_spi_clear_flag_status(hperh, SPI_IF_RXTH); + while (spi_get_status(hperh, SPI_STATUS_RXTH) != RESET) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + *hperh->rx_buf = hperh->perh->DATA; + ++hperh->rx_buf; + } + else { + *(uint16_t *)hperh->rx_buf = hperh->perh->DATA; + hperh->rx_buf += 2; + } + --hperh->rx_count; + } + } + } + + if (hperh->tx_count != 0) { + if ((status == SPI_SR_TXE) || (status == SPI_SR_TXE_RXNE)) { + ald_spi_clear_flag_status(hperh, SPI_IF_TXE); + if (hperh->tx_count == 1) { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + SPI_CRCNEXT_ENABLE(hperh); + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + } + + ++hperh->tx_buf; + } + else { + if (hperh->init.crc_calc) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + SPI_CRCNEXT_ENABLE(hperh); + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + } + + hperh->tx_buf += 2; + } + + --hperh->tx_count; + } + else { + if (hperh->init.data_size == SPI_DATA_SIZE_8) { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *hperh->tx_buf; + ++hperh->tx_buf; + } + else { + while(hperh->perh->STAT & SPI_STAT_TXF_MSK); + hperh->perh->DATA = *(uint16_t *)hperh->tx_buf; + hperh->tx_buf += 2; + } + + --hperh->tx_count; + } + } + } + + if (hperh->rx_count == 0) { + ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE); + ald_spi_interrupt_config(hperh, SPI_IT_MODF, DISABLE); + hperh->state = SPI_STATE_READY; + + if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) { + hperh->err_code |= SPI_ERROR_CRC; + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + + if (hperh->err_cbk) + hperh->err_cbk(hperh); + + return; + } + + if (hperh->tx_rx_cplt_cbk) + hperh->tx_rx_cplt_cbk(hperh); + } + + return; +} + +#ifdef ALD_DMA +/** + * @brief DMA SPI transmit process complete callback. + * @param arg: Pointer to a spi_handle_t structure. + * @retval None + */ +static void spi_dma_send_cplt(void *arg) +{ + uint16_t delay, temp; + spi_handle_t *hperh = (spi_handle_t *)arg; + + hperh->tx_count = 0; + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + hperh->state = SPI_STATE_READY; + + while ((spi_get_status(hperh, SPI_STATUS_RXE)) == RESET) { + temp = hperh->perh->DATA; + UNUSED(temp); + } + + if (hperh->init.dir == SPI_DIRECTION_2LINES) + ald_spi_clear_flag_status(hperh, SPI_IF_TXOV); + + if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + for (delay = 0; delay < 3000; delay++); + + if (hperh->err_code == SPI_ERROR_NONE) { + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA SPI receive process complete callback. + * @param arg: Pointer to a spi_handle_t structure. + * @retval None + */ +static void spi_dma_recv_cplt(void *arg) +{ + uint32_t tmp; + spi_handle_t *hperh = (spi_handle_t *)arg; + + hperh->rx_count = 0; + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + hperh->state = SPI_STATE_READY; + + if (hperh->init.crc_calc) { + if ((spi_wait_flag_irq(hperh, SPI_IF_RXTH, SET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + tmp = hperh->perh->DATA; + UNUSED(tmp); + + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) { + SET_BIT(hperh->err_code, SPI_ERROR_CRC); + SPI_CRC_RESET(hperh); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + } + } + + if (hperh->err_code == SPI_ERROR_NONE) { + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +/** + * @brief DMA SPI transmit and receive process complete callback. + * @param arg: Pointer to a SPI_handle_t structure. + * @retval None + */ +static void spi_dma_send_recv_cplt(void *arg) +{ + uint32_t tmp; + uint16_t delay; + spi_handle_t *hperh = (spi_handle_t *)arg; + + if (hperh->init.crc_calc) { + if ((spi_wait_flag_irq(hperh, SPI_IF_RXTH, SET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + tmp = hperh->perh->DATA; + UNUSED(tmp); + + if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) { + SET_BIT(hperh->err_code, SPI_ERROR_CRC); + ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR); + } + } + + if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != OK) + hperh->err_code |= SPI_ERROR_FLAG; + + for (delay = 0; delay < 3000; delay++); + + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE); + ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE); + hperh->tx_count = 0; + hperh->rx_count = 0; + hperh->state = SPI_STATE_READY; + + if (hperh->err_code == SPI_ERROR_NONE) { + if (hperh->tx_rx_cplt_cbk) + hperh->tx_rx_cplt_cbk(hperh); + } + else { + if (hperh->err_cbk) + hperh->err_cbk(hperh); + } + + return; +} + +#endif /* ALD_DMA */ +/** + * @} + */ +#endif /* ALD_SPI */ +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_sram.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_sram.c new file mode 100644 index 00000000..6eaf9fc3 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_sram.c @@ -0,0 +1,397 @@ +/** + ********************************************************************************* + * + * @file ald_sram.c + * @brief SRAM module driver. + * + * @version V1.0 + * @date 25 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 25 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ +#include "ald_conf.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup SRAM SRAM + * @brief SRAM module driver + * @{ + */ + +#ifdef ALD_SRAM + +/** @defgroup SRAM_Public_Functions SRAM Public Functions + * @{ + */ +/** @defgroup SRAM_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * @{ + */ +/** + * @brief Performs the SRAM device initialization sequence + * @param hperh: pointer to a sram_handle_t structure + * @param timing: Pointer to SRAM control timing structure + * @param ext_timing: Pointer to SRAM extended mode timing structure + * @retval ald status + */ +ald_status_t ald_sram_init(sram_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing) +{ + if (hperh == NULL) + return ERROR; + + if (hperh->state == ALD_SRAM_STATE_RESET) + hperh->lock = UNLOCK; + + /* Initialize SRAM control Interface */ + ald_ebi_nor_sram_init(hperh->instance, &(hperh->init)); + /* Initialize SRAM timing Interface */ + ald_ebi_nor_sram_timing_init(hperh->instance, timing, hperh->init.bank); + /* Initialize SRAM extended mode timing Interface */ + ald_ebi_nor_sram_ext_timing_init(hperh->ext, ext_timing, hperh->init.bank, hperh->init.ext_mode); + /* Enable the NORSRAM device */ + ald_ebi_nor_sram_enable(hperh->instance, hperh->init.bank); + + return OK; +} + +/** + * @brief Performs the SRAM device De-initialization sequence. + * @param hperh: pointer to a sram_handle_t structure + * @retval ald status + */ +ald_status_t ald_sram_deinit(sram_handle_t *hperh) +{ + ald_ebi_nor_sram_deinit(hperh->instance, hperh->ext, hperh->init.bank); + hperh->state = ALD_SRAM_STATE_RESET; + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @defgroup SRAM_Public_Functions_Group2 I/O operation functions + * @brief I/O operation functions + * @{ + */ +/** + * @brief Reads 8-bit buffer from SRAM memory. + * @param hperh: pointer to a sram_handle_t structure + * @param addr: Pointer to read start address + * @param buf: Pointer to destination buffer + * @param size: Size of the buffer to read from memory + * @retval ald status + */ +ald_status_t ald_sram_read_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size) +{ + __IO uint8_t * psramaddr = (uint8_t *)addr; + + __LOCK(hperh); + hperh->state = ALD_SRAM_STATE_BUSY; + + /* Read data from memory */ + for (; size != 0U; size--) + *buf++ = *(__IO uint8_t *)psramaddr++; + + hperh->state = ALD_SRAM_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Writes 8-bit buffer to SRAM memory. + * @param hperh: pointer to a sram_handle_t structure + * @param addr: Pointer to write start address + * @param buf: Pointer to source buffer to write + * @param size: Size of the buffer to write to memory + * @retval ald status + */ +ald_status_t ald_sram_write_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size) +{ + __IO uint8_t * psramaddr = (uint8_t *)addr; + + if (hperh->state == ALD_SRAM_STATE_PROTECTED) + return ERROR; + + __LOCK(hperh); + hperh->state = ALD_SRAM_STATE_BUSY; + + /* Write data to memory */ + for (; size != 0U; size--) + *(__IO uint8_t *)psramaddr++ = *buf++; + + hperh->state = ALD_SRAM_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Reads 16-bit buffer from SRAM memory. + * @param hperh: pointer to a sram_handle_t structure that contains + * the configuration information for SRAM module. + * @param addr: Pointer to read start address + * @param buf: Pointer to destination buffer + * @param size: Size of the buffer to read from memory + * @retval ald status + */ +ald_status_t ald_sram_read_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size) +{ + __IO uint16_t * psramaddr = (uint16_t *)addr; + + __LOCK(hperh); + hperh->state = ALD_SRAM_STATE_BUSY; + + /* Read data from memory */ + for (; size != 0U; size--) + *buf++ = *(__IO uint16_t *)psramaddr++; + + hperh->state = ALD_SRAM_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Writes 16-bit buffer to SRAM memory. + * @param hperh: pointer to a sram_handle_t structure that contains + * the configuration information for SRAM module. + * @param addr: Pointer to write start address + * @param buf: Pointer to source buffer to write + * @param size: Size of the buffer to write to memory + * @retval ald status + */ +ald_status_t ald_sram_write_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size) +{ + __IO uint16_t * psramaddr = (uint16_t *)addr; + + if (hperh->state == ALD_SRAM_STATE_PROTECTED) + return ERROR; + + __LOCK(hperh); + hperh->state = ALD_SRAM_STATE_BUSY; + + /* Write data to memory */ + for (; size != 0U; size--) + *(__IO uint16_t *)psramaddr++ = *buf++; + + hperh->state = ALD_SRAM_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Reads 32-bit buffer from SRAM memory. + * @param hperh: pointer to a sram_handle_t structure + * @param addr: Pointer to read start address + * @param buf: Pointer to destination buffer + * @param size: Size of the buffer to read from memory + * @retval ald status + */ +ald_status_t ald_sram_read_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size) +{ + __LOCK(hperh); + hperh->state = ALD_SRAM_STATE_BUSY; + + /* Read data from memory */ + for (; size != 0U; size--) + *buf++ = *(__IO uint32_t *)addr++; + + hperh->state = ALD_SRAM_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Writes 32-bit buffer to SRAM memory. + * @param hperh: pointer to a sram_handle_t structure that contains + * the configuration information for SRAM module. + * @param addr: Pointer to write start address + * @param buf: Pointer to source buffer to write + * @param size: Size of the buffer to write to memory + * @retval ald status + */ +ald_status_t ald_sram_write_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size) +{ + if (hperh->state == ALD_SRAM_STATE_PROTECTED) + return ERROR; + + __LOCK(hperh); + hperh->state = ALD_SRAM_STATE_BUSY; + + /* Write data to memory */ + for (; size != 0U; size--) + *(__IO uint32_t *)addr++ = *buf++; + + hperh->state = ALD_SRAM_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Reads a halfwords data from the SRAM memory using DMA transfer. + * @param hperh: pointer to a sram_handle_t structure that contains + * the configuration information for SRAM module. + * @param addr: Pointer to read start address + * @param buf: Pointer to destination buffer + * @param size: Size of the buffer to read from memory + * @param ch: Index of DMA channel + * @retval ald status + */ +ald_status_t ald_sram_read_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch) +{ + if (buf == NULL) + return ERROR; + + hperh->hdma.perh = DMA0; + hperh->hdma.cplt_cbk = hperh->cplt_cbk; + ald_dma_config_struct(&hperh->hdma.config); + + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src = (void *)addr; + hperh->hdma.config.dst = (void *)buf; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.msel = DMA_MSEL_NONE; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = ch; + hperh->hdma.config.R_power = DMA_R_POWER_4; + hperh->hdma.config.burst = ENABLE; + + ald_dma_config_auto(&hperh->hdma); + return OK; +} + +/** + * @brief Write a halfwords data to the SRAM memory using DMA transfer. + * @param hperh: pointer to a sram_handle_t structure that contains + * the configuration information for SRAM module. + * @param addr: Pointer to write start address + * @param buf: Pointer to destination buffer + * @param size: Size of the buffer to write from memory + * @param ch: Index of DMA channel + * @retval ald status + */ +ald_status_t ald_sram_write_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch) +{ + if (buf == NULL) + return ERROR; + ; + hperh->hdma.perh = DMA0; + hperh->hdma.cplt_cbk = hperh->cplt_cbk; + ald_dma_config_struct(&hperh->hdma.config); + + hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma.config.src = (void *)buf; + hperh->hdma.config.dst = (void *)addr; + hperh->hdma.config.size = size; + hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma.config.msel = DMA_MSEL_NONE; + hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE; + hperh->hdma.config.channel = ch; + hperh->hdma.config.R_power = DMA_R_POWER_4; + hperh->hdma.config.burst = ENABLE; + + ald_dma_config_auto(&hperh->hdma); + return OK; +} +#endif +/** + * @} + */ + +/** @defgroup SRAM_Public_Functions_Group3 Control functions + * @brief Control functions + * @{ + */ +/** + * @brief Enables dynamically SRAM write operation. + * @param hperh: pointer to a sram_handle_t structure + * @retval ald status + */ +ald_status_t ald_sram_write_enable(sram_handle_t *hperh) +{ + __LOCK(hperh); + ald_ebi_nor_sram_write_enable(hperh->instance, hperh->init.bank); + hperh->state = ALD_SRAM_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Disables dynamically SRAM write operation. + * @param hperh: pointer to a sram_handle_t structure + * @retval ald status + */ +ald_status_t ald_sram_write_disable(sram_handle_t *hperh) +{ + __LOCK(hperh); + hperh->state = ALD_SRAM_STATE_BUSY; + ald_ebi_nor_sram_write_disable(hperh->instance, hperh->init.bank); + hperh->state = ALD_SRAM_STATE_PROTECTED; + __UNLOCK(hperh); + + return OK; +} +/** + * @} + */ + +/** @addtogroup SRAM_Public_Functions_Group4 State functions + * @brief State functions + * @{ + */ +/** + * @brief Returns the SRAM controller state + * @param hperh: pointer to a SRAM_HandleTypeDef structure + * @retval ald state + */ +ald_sram_state_t ald_sram_get_state(sram_handle_t *hperh) +{ + return hperh->state; +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_SRAM */ + +/** + * @} + */ +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_timer.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_timer.c new file mode 100644 index 00000000..1101e8f2 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_timer.c @@ -0,0 +1,3705 @@ +/** + ********************************************************************************* + * + * @file ald_timer.c + * @brief TIMER module driver. + * This is the common part of the TIMER initialization + * + * @version V1.0 + * @date 06 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 06 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup TIMER TIMER + * @brief TIMER module driver + * @{ + */ +#ifdef ALD_TIMER + +/** @defgroup TIMER_Private_Functions TIMER Private Functions + * @{ + */ +static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init); +static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); +static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); +static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); +static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config); +static void timer_ccx_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state); +static void timer_ccxn_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state); +static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter); +static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter); +static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter); +static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter); +static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter); +static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter); +static void timer_etr_set_config(TIMER_TypeDef* TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter); +static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config); +#ifdef ALD_DMA +static void timer_dma_oc_cplt(void *arg); +static void timer_dma_capture_cplt(void *arg); +static void timer_dma_period_elapse_cplt(void *arg); +static void timer_dma_error(void *arg); +static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config); +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions TIMER Public Functions + * @{ + */ + +/** @defgroup TIMER_Public_Functions_Group1 TIMER Base functions + * @brief Time Base functions + * + * @verbatim + ============================================================================== + ##### Timer Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER base. + (+) Reset the TIMER base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Time base Unit according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER base handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_base_init(timer_handle_t *hperh) +{ + if (hperh == NULL) + return ERROR; + + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = TIMER_STATE_BUSY; + timer_base_set_config(hperh->perh, &hperh->init); + hperh->state = TIMER_STATE_READY; + + return OK; +} + +/** + * @brief Reset the TIMER base peripheral + * @param hperh: TIMER base handle + * @retval Status, see @ref ald_status_t. + */ +void ald_timer_base_reset(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + hperh->state = TIMER_STATE_BUSY; + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_RESET; + __UNLOCK(hperh); + + return; +} + +/** + * @brief Starts the TIMER Base generation. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_base_start(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + hperh->state = TIMER_STATE_BUSY; + TIMER_ENABLE(hperh); + hperh->state = TIMER_STATE_READY; + + return; +} + +/** + * @brief Stops the TIMER Base generation. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_base_stop(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + hperh->state = TIMER_STATE_BUSY; + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + + return; +} + +/** + * @brief Starts the TIMER Base generation in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_base_start_by_it(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, ENABLE); + TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER Base generation in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_base_stop_by_it(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, DISABLE); + TIMER_DISABLE(hperh); + + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER Base generation in DMA mode. + * @param hperh: TIMER handle + * @param buf: The source Buffer address. + * @param len: The length of buffer to be transferred from memory to TIMER peripheral + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. +*/ +ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ERROR; + } + + hperh->state = TIMER_STATE_BUSY; + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; + + hperh->hdma1.cplt_cbk = timer_dma_period_elapse_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.dst = (void *)&hperh->perh->AR; + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_UPDATE; + hperh->hdma1.config.channel = dma_ch; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, ENABLE); + TIMER_ENABLE(hperh); + + return OK; +} + +/** + * @brief Stops the TIMER Base generation in DMA mode. + * @param hperh: TIMER handle + * @retval None +*/ +void ald_timer_base_stop_by_dma(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, DISABLE); + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group2 TIMER Output Compare functions + * @brief Time Output Compare functions + * + * @verbatim + ============================================================================== + ##### Time Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Output Compare. + (+) Start the Time Output Compare. + (+) Stop the Time Output Compare. + (+) Start the Time Output Compare and enable interrupt. + (+) Stop the Time Output Compare and disable interrupt. + (+) Start the Time Output Compare and enable DMA transfer. + (+) Stop the Time Output Compare and disable DMA transfer. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Output Compare according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_oc_init(timer_handle_t *hperh) +{ + return ald_timer_base_init(hperh); +} + +/** + * @brief Starts the TIMER Output Compare signal generation. + * @param hperh: TIMER handle + * @param ch : TIMER Channel to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); + + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Output Compare signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} + +/** + * @brief Starts the TIMER Output Compare signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); + + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Output Compare signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} + + + + + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER Output Compare signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param buf: The source Buffer address. + * @param len: The length of buffer to be transferred from memory to TIMER peripheral + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ERROR; + } + + hperh->state = TIMER_STATE_BUSY; + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; + + hperh->hdma1.cplt_cbk = timer_dma_oc_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.channel = dma_ch; + + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + switch (ch) { + case TIMER_CHANNEL_1: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + case TIMER_CHANNEL_4: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL4; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); + + TIMER_ENABLE(hperh); + return OK; +} + +/** + * @brief Stops the TIMER Output Compare signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None +*/ +void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + + case TIMER_CHANNEL_4: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group3 TIMER PWM functions + * @brief TIMER PWM functions + * + * @verbatim + ============================================================================== + ##### Time PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER PWM. + (+) Start the Time PWM. + (+) Stop the Time PWM. + (+) Start the Time PWM and enable interrupt. + (+) Stop the Time PWM and disable interrupt. + (+) Start the Time PWM and enable DMA transfer. + (+) Stop the Time PWM and disable DMA transfer. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER PWM Time Base according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_pwm_init(timer_handle_t *hperh) +{ + return ald_timer_base_init(hperh); +} + +/** + * @brief Starts the PWM signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_oc_start(hperh, ch); + return; +} + +/** + * @brief Stops the PWM signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_oc_stop(hperh, ch); + return; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channel to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_oc_start_by_it(hperh, ch); + return; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_oc_stop_by_it(hperh, ch); + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER PWM signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param buf: The source Buffer address. + * @param len: The length of buffer to be transferred from memory to TIMER peripheral + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + return ald_timer_oc_start_by_dma(hperh, ch, buf, len, dma_ch); +} + +/** + * @brief Stops the TIMER PWM signal generation in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_oc_stop_by_dma(hperh, ch); + return; +} +#endif +/** + * @brief Set the PWM freq. + * @param hperh: TIMER handle + * @param freq: PWM freq to set + * @retval None + */ +void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint32_t freq) +{ + uint32_t _arr; + + if (freq == 0) + return; + + _arr = ald_cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1; + WRITE_REG(hperh->perh->AR, _arr); + hperh->init.period = _arr; +} + +/** + * @brief Set the PWM duty. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param duty: PWM duty to set [0, 100] + * @retval None + */ +void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty) +{ + uint32_t tmp = (hperh->init.period + 1) * duty / 100; + + if (ch == TIMER_CHANNEL_1) + WRITE_REG(hperh->perh->CCVAL1, tmp); + else if (ch == TIMER_CHANNEL_2) + WRITE_REG(hperh->perh->CCVAL2, tmp); + else if (ch == TIMER_CHANNEL_3) + WRITE_REG(hperh->perh->CCVAL3, tmp); + else if (ch == TIMER_CHANNEL_4) + WRITE_REG(hperh->perh->CCVAL4, tmp); + else { + ;/* do nothing */ + } +} + +/** + * @brief Set capture the PWM. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be captured the PWM + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_PWM_INPUT_INSTANCE(hperh->perh, ch)); + + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); + SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2EN_MSK); + + return; +} +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group4 TIMER Input Capture functions + * @brief Time Input Capture functions + * + * @verbatim + ============================================================================== + ##### Time Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Input Capture. + (+) Start the Time Input Capture. + (+) Stop the Time Input Capture. + (+) Start the Time Input Capture and enable interrupt. + (+) Stop the Time Input Capture and disable interrupt. + (+) Start the Time Input Capture and enable DMA transfer. + (+) Stop the Time Input Capture and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Input Capture Time base according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_ic_init(timer_handle_t *hperh) +{ + return ald_timer_base_init(hperh); +} + +/** + * @brief Starts the TIMER Input Capture measurement. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Input Capture measurement. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER Input Capture measurement in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE); + break; + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Input Capture measurement in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + case TIMER_CHANNEL_4: + ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE); + break; + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_DISABLE(hperh); + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER Input Capture measurement in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @param buf: The destination Buffer address. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ERROR; + } + + hperh->state = TIMER_STATE_BUSY; + + if (hperh->perh == NULL) + hperh->hdma1.perh = DMA0; + + hperh->hdma1.cplt_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.dst = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma1.config.channel = dma_ch; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + switch (ch) { + case TIMER_CHANNEL_1: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + case TIMER_CHANNEL_4: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL4; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH4; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_ENABLE(hperh); + return OK; +} + +/** + * @brief Stops the TIMER Input Capture measurement in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval None + */ +void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + case TIMER_CHANNEL_4: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE); + break; + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group5 TIMER One Pulse functions + * @brief Time One Pulse functions + * + * @verbatim + ============================================================================== + ##### Time One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER One Pulse. + (+) Start the Time One Pulse. + (+) Stop the Time One Pulse. + (+) Start the Time One Pulse and enable interrupt. + (+) Stop the Time One Pulse and disable interrupt. + (+) Start the Time One Pulse and enable DMA transfer. + (+) Stop the Time One Pulse and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER One Pulse Time Base according to the specified + * parameters in the timer_handle_t and create the associated handle. + * @param hperh: TIMER handle + * @param mode: Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIMER_OP_MODE_SINGLE: Only one pulse will be generated. + * @arg TIMER_OP_MODE_REPEAT: Repetitive pulses wil be generated. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode) +{ + if (hperh == NULL) + return ERROR; + + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + assert_param(IS_TIMER_OP_MODE(mode)); + + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = TIMER_STATE_BUSY; + timer_base_set_config(hperh->perh, &hperh->init); + MODIFY_REG(hperh->perh->CON1, TIMER_CON1_SPMEN_MSK, mode << TIMER_CON1_SPMEN_POS); + hperh->state = TIMER_STATE_READY; + + return OK; +} + +/** + * @brief Starts the TIMER One Pulse signal generation. + * @param hperh: TIMER One Pulse handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch) +{ + /* Enable the Capture compare and the Input Capture channels + * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) + * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and + * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output + * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together + */ + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER One Pulse signal generation. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch) +{ + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); + + TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER One Pulse signal generation in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) +{ + /* Enable the Capture compare and the Input Capture channels + * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2) + * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and + * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output + * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together + */ + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER One Pulse signal generation in interrupt mode. + * @param hperh : TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch) +{ + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + + if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET) + TIMER_MOE_DISABLE(hperh); + + TIMER_DISABLE(hperh); + return; +} +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group6 TIMER Encoder functions + * @brief TIMER Encoder functions + * + * @verbatim + ============================================================================== + ##### Time Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER Encoder. + (+) Start the Time Encoder. + (+) Stop the Time Encoder. + (+) Start the Time Encoder and enable interrupt. + (+) Stop the Time Encoder and disable interrupt. + (+) Start the Time Encoder and enable DMA transfer. + (+) Stop the Time Encoder and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Encoder Interface and create the associated handle. + * @param hperh: TIMER handle + * @param config: TIMER Encoder Interface configuration structure + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config) +{ + if (hperh == NULL) + return ERROR; + + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_ENCODER_MODE(config->mode)); + assert_param(IS_TIMER_IC_POLARITY(config->ic1_polarity)); + assert_param(IS_TIMER_IC_POLARITY(config->ic2_polarity)); + assert_param(IS_TIMER_IC_SELECT(config->ic1_sel)); + assert_param(IS_TIMER_IC_SELECT(config->ic2_sel)); + assert_param(IS_TIMER_IC_PSC(config->ic1_psc)); + assert_param(IS_TIMER_IC_PSC(config->ic2_psc)); + assert_param(IS_TIMER_IC_FILTER(config->ic1_filter)); + assert_param(IS_TIMER_IC_FILTER(config->ic2_filter)); + + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = TIMER_STATE_BUSY; + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + timer_base_set_config(hperh->perh, &hperh->init); + + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, config->ic1_sel << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, config->ic2_sel << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->ic1_psc << TIMER_CHMR1_IC1PRES_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->ic2_psc << TIMER_CHMR1_IC2PRES_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->ic1_filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I2FLT_MSK, config->ic2_filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, (config->ic1_polarity & 0x1) << TIMER_CCEP_CC1POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((config->ic1_polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, (config->ic2_polarity & 0x1) << TIMER_CCEP_CC2POL_POS); + MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((config->ic2_polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS); + + hperh->state = TIMER_STATE_READY; + return OK; +} + +/** + * @brief Starts the TIMER Encoder Interface. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + break; + } + + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Encoder Interface. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + break; + } + + TIMER_DISABLE(hperh); + return; +} + +/** + * @brief Starts the TIMER Encoder Interface in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + } + + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Stops the TIMER Encoder Interface in interrupt mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + } + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER Encoder Interface in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @param buf1: The destination Buffer address. Reading data from CCR1. + * @param buf2: The destination Buffer address. Reading data from CCR2. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch1: Channel of DMA. + * @param dma_ch2: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, + uint16_t *buf1, uint16_t *buf2, uint32_t len, + uint8_t dma_ch1, uint8_t dma_ch2) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf1 == 0) || ((uint32_t)buf2 == 0) || (len == 0)) + return ERROR; + } + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; + if (hperh->hdma2.perh == NULL) + hperh->hdma2.perh = DMA0; + + hperh->state = TIMER_STATE_BUSY; + hperh->hdma1.cplt_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + switch (ch) { + case TIMER_CHANNEL_1: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); + break; + + case TIMER_CHANNEL_2: + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.dst = (void *)buf2; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + hperh->hdma1.config.channel = dma_ch2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + TIMER_ENABLE(hperh); + break; + + default: + hperh->hdma2.cplt_cbk = timer_dma_capture_cplt; + hperh->hdma2.cplt_arg = (void *)hperh; + hperh->hdma2.err_cbk = timer_dma_error; + hperh->hdma2.err_arg = (void *)hperh; + memcpy(&hperh->hdma2.config, &hperh->hdma1.config, sizeof(dma_config_t)); + + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + + hperh->hdma2.config.src = (void *)&hperh->perh->CCVAL2; + hperh->hdma2.config.dst = (void *)buf2; + hperh->hdma2.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + hperh->hdma2.config.channel = dma_ch2; + ald_dma_config_basic(&hperh->hdma2); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE); + TIMER_ENABLE(hperh); + break; + } + + return OK; +} + +/** + * @brief Stops the TIMER Encoder Interface in DMA mode. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected + * @retval None + */ +void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + + switch (ch) { + case TIMER_CHANNEL_1: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + case TIMER_CHANNEL_2: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + default: + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + } + + TIMER_DISABLE(hperh); + hperh->state = TIMER_STATE_READY; + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group7 TIMER Hall Sensor functions + * @brief TIMER Hall Sensor functions + * + * @verbatim + ============================================================================== + ##### Time Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIMER hall sensor. + (+) Start the hall sensor. + (+) Stop the hall sensor. + (+) Start the hall sensor and enable interrupt. + (+) Stop the hall sensor and disable interrupt. + (+) Start the hall sensor and enable DMA transfer. + (+) Stop the hal sensor and disable DMA transfer. + + * @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Encoder Interface and create the associated handle. + * @param hperh: TIMER handle + * @param config: TIMER Encoder Interface configuration structure + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config) +{ + timer_oc_init_t oc; + + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (hperh->state == TIMER_STATE_RESET) + hperh->lock = UNLOCK; + + hperh->state = TIMER_STATE_READY; + timer_base_set_config(hperh->perh, &hperh->init); + timer_ti1_set_config(hperh->perh, config->polarity, TIMER_IC_SEL_TRC, config->filter); + + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); + SET_BIT(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS); + + oc.oc_mode = TIMER_OC_MODE_PWM2; + oc.pulse = config->delay; + oc.oc_polarity = TIMER_OC_POLARITY_HIGH; + oc.ocn_polarity = TIMER_OCN_POLARITY_HIGH; + oc.oc_fast_en = DISABLE; + oc.oc_idle = TIMER_OC_IDLE_RESET; + oc.ocn_idle = TIMER_OCN_IDLE_RESET; + timer_oc2_set_config(hperh->perh, &oc); + + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_TRGO_OC2REF << TIMER_SMCON_SMODS_POSS); + return OK; +} +/** + * @brief Starts the TIMER hall sensor interface. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_start(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER hall sensor interface. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_stop(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + TIMER_DISABLE(hperh); + + return; +} + +/** + * @brief Starts the TIMER hall sensor interface in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER hall sensor interface in interrupt mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + TIMER_DISABLE(hperh); + + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER hall sensor interface in DMA mode. + * @param hperh: TIMER handle + * @param buf: The destination Buffer address. Reading data from CCR1. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, + uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0) || (len == 0)) + return ERROR; + } + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; + + hperh->state = TIMER_STATE_BUSY; + hperh->hdma1.cplt_cbk = timer_dma_capture_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD; + + timer_dma_msel(hperh->perh, &hperh->hdma1.config); + + hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.dst = (void *)buf; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + hperh->hdma1.config.channel = dma_ch; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE); + TIMER_ENABLE(hperh); + + return OK; +} +/** + * @brief Stops the TIMER hall sensor interface in DMA mode. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh) +{ + assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh)); + + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE); + TIMER_DISABLE(hperh); + + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group8 TIMER complementary output compare functions + * @brief TIMER complementary output compare functions + * + * @verbatim + ============================================================================== + ##### Time complementary output compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary output compare. + (+) Stop the Time complementary output compare. + (+) Start the Time complementary output compare and enable interrupt. + (+) Stop the Time complementary output compare and disable interrupt. + (+) Start the Time complementary output compare and enable DMA transfer. + (+) Stop the Time complementary output compare and disable DMA transfer. + + * @endverbatim + * @{ + */ + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER output compare signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); + + return; +} + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE); + break; + default: + break; + } + + ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, ENABLE); + timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); + + return; +} + +/** + * @brief Stops the TIMER output compare signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE); + break; + default: + break; + } + + if ((!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1NEN_MSK))) + && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2NEN_MSK))) + && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC3NEN_MSK)))) { + ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, DISABLE); + } + + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); + + return; +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @param buf: The destination Buffer address. Reading data from CCRx. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval None + */ +ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + if ((hperh->state == TIMER_STATE_BUSY)) + return BUSY; + if ((hperh->state == TIMER_STATE_READY)) { + if (((uint32_t)buf == 0 ) || (len == 0)) + return ERROR; + } + + hperh->state = TIMER_STATE_BUSY; + + if (hperh->hdma1.perh == NULL) + hperh->hdma1.perh = DMA0; + + hperh->hdma1.cplt_cbk = timer_dma_oc_cplt; + hperh->hdma1.cplt_arg = (void *)hperh; + hperh->hdma1.err_cbk = timer_dma_error; + hperh->hdma1.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdma1.config); + hperh->hdma1.config.src = (void *)buf; + hperh->hdma1.config.size = len; + hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD; + hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE; + hperh->hdma1.config.channel = dma_ch; + hperh->hdma1.config.msel = DMA_MSEL_TIMER0; + + switch (ch) { + case TIMER_CHANNEL_1: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + break; + + case TIMER_CHANNEL_2: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + break; + + case TIMER_CHANNEL_3: + hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3; + hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3; + ald_dma_config_basic(&hperh->hdma1); + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + break; + + default: + break; + } + + timer_ccx_channel_cmd(hperh->perh, ch, ENABLE); + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); + + return OK; +} + +/** + * @brief Starts the TIMER output compare signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE); + break; + + case TIMER_CHANNEL_2: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE); + break; + + case TIMER_CHANNEL_3: + ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE); + break; + default: + break; + } + + timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE); + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); + + return; +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group9 TIMER complementary PWM functions + * @brief TIMER complementary PWM functions + * + * @verbatim + ============================================================================== + ##### Time complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary PWM. + (+) Stop the Time complementary PWM. + (+) Start the Time complementary PWM and enable interrupt. + (+) Stop the Time complementary PWM and disable interrupt. + (+) Start the Time complementary PWM and enable DMA transfer. + (+) Stop the Time complementary PWM and disable DMA transfer. + + * @endverbatim + * @{ + */ + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_start(hperh, ch); +} + +/** + * @brief Stops the TIMER PWM signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_stop(hperh, ch); +} + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_start_by_it(hperh, ch); +} + +/** + * @brief Stops the TIMER PWM signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_stop_by_it(hperh, ch); +} + +#ifdef ALD_DMA +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @param buf: The destination Buffer address. Reading data from CCRx. + * @param len: The length of buffer to be transferred TIMER peripheral to memory + * @param dma_ch: Channel of DMA. + * @retval None + */ +ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, + timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch) +{ + return ald_timer_ocn_start_by_dma(hperh, ch, buf, len, dma_ch); +} + +/** + * @brief Starts the TIMER PWM signal generation on the complementary output. + * in DMA mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @retval None + */ +void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_stop_by_dma(hperh, ch); +} +#endif +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group10 TIMER complementary one pulse functions + * @brief TIMER complementary one pulse functions + * + * @verbatim + ============================================================================== + ##### Time complementary one pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Time complementary one pulse. + (+) Stop the Time complementary one pulse. + (+) Start the Time complementary one pulse and enable interrupt. + (+) Stop the Time complementary one pulse and disable interrupt. + + * @endverbatim + * @{ + */ + +/** + * @brief Starts the TIMER one pulse signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_start(hperh, ch); +} + +/** + * @brief Stops the TIMER one pulse signal generation on the complementary output. + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_stop(hperh, ch); +} + +/** + * @brief Starts the TIMER one pulse signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_start_by_it(hperh, ch); +} + +/** + * @brief Stops the TIMER one pulse signal generation on the complementary output. + * in interrupt mode + * @param hperh: TIMER handle + * @param ch: TIMER Channels to be disabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval None + */ +void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch) +{ + ald_timer_ocn_stop_by_it(hperh, ch); +} +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group11 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead timere. + (+) Configure Master and the Slave synchronization. + (+) Handle TIMER interrupt. + (+) Get TIMER compare register's vale. + (+) Configure TIMER interrupt ENABLE/DISABLE. + (+) Get TIMER interrupt source status. + (+) Get TIMER interrupt flag status. + (+) Clear TIMER interrupt flag. + + @endverbatim + * @{ + */ +/** + * @brief Initializes the TIMER Output Compare Channels according to the specified + * parameters in the timer_oc_init_t. + * @param hperh: TIMER handle + * @param config: TIMER Output Compare configuration structure + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t* config, timer_channel_t ch) +{ + assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch)); + assert_param(IS_TIMER_OC_MODE(config->oc_mode)); + assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + switch (ch) { + case TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, config); + break; + + case TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, config); + break; + + case TIMER_CHANNEL_3: + timer_oc3_set_config(hperh->perh, config); + break; + + case TIMER_CHANNEL_4: + timer_oc4_set_config(hperh->perh, config); + break; + + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Initializes the TIMER Input Capture Channels according to the specified + * parameters in the timer_ic_init_t. + * @param hperh: TIMER handle + * @param config: TIMER Input Capture configuration structure + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3: TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4: TIMER Channel 4 selected + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t* config, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_SELECT(config->sel)); + assert_param(IS_TIMER_IC_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + switch (ch) { + case TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS); + break; + + case TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS); + break; + + case TIMER_CHANNEL_3: + timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS); + break; + + case TIMER_CHANNEL_4: + timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS); + break; + + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Initializes the TIMER One Pulse Channels according to the specified + * parameters in the timer_one_pulse_init_t. + * @param hperh: TIMER handle + * @param config: TIMER One Pulse configuration structure + * @param ch_out: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @param ch_in: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2: TIMER Channel 2 selected + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, + timer_channel_t ch_out, timer_channel_t ch_in) +{ + timer_oc_init_t tmp; + + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_OC_MODE(config->mode)); + assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity)); + assert_param(IS_TIMER_OCN_POLARITY(config->ocn_polarity)); + assert_param(IS_TIMER_OCIDLE_STATE(config->oc_idle)); + assert_param(IS_TIMER_OCNIDLE_STATE(config->ocn_idle)); + assert_param(IS_TIMER_IC_POLARITY(config->polarity)); + assert_param(IS_TIMER_IC_SELECT(config->sel)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (ch_out == ch_in) + return ERROR; + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + tmp.oc_mode = config->mode; + tmp.pulse = config->pulse; + tmp.oc_polarity = config->oc_polarity; + tmp.ocn_polarity = config->ocn_polarity; + tmp.oc_idle = config->oc_idle; + tmp.ocn_idle = config->ocn_idle; + + switch (ch_out) { + case TIMER_CHANNEL_1: + timer_oc1_set_config(hperh->perh, &tmp); + break; + case TIMER_CHANNEL_2: + timer_oc2_set_config(hperh->perh, &tmp); + break; + default: + break; + } + + switch (ch_in) { + case TIMER_CHANNEL_1: + timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_CHANNEL_2: + timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter); + CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param hperh: TIMER handle + * @param config: pointer to a TIMER_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIMER peripheral. + * @param ch: specifies the TIMER Channel + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @arg TIMER_CHANNEL_4: TIMER Channel 4 + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->state)); + assert_param(IS_TIMER_CLEAR_INPUT_SOURCE(config->source)); + assert_param(IS_TIMER_CLEAR_INPUT_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_CHNREF_CLEAR(config->clrsel)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + if (config->source == TIMER_INPUT_NONE) { + timer_etr_set_config(hperh->perh, TIMER_ETR_PSC_DIV1, TIMER_CLK_POLARITY_NO_INV, 0); + } + else { + timer_etr_set_config(hperh->perh, config->psc, + (timer_clock_polarity_t)config->polarity, config->filter); + } + + if (config->clrsel == TIMER_CHNREF_CLR_CMP_IN) { + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_CHCSEL_MASK); + } + else { + SET_BIT(hperh->perh->SMCON, TIMER_SMCON_CHCSEL_MASK); + } + + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS); + break; + + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS); + break; + + case TIMER_CHANNEL_3: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS); + break; + + case TIMER_CHANNEL_4: + assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh)); + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS); + break; + + default: + break; + } + + return OK; +} + +/** + * @brief Configures the clock source to be used + * @param hperh: TIMER handle + * @param config: pointer to a timer_clock_config_t structure that + * contains the clock source information for the TIMER peripheral. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_CLOCK_SOURCE(config->source)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + WRITE_REG(hperh->perh->SMCON, 0x0); + + switch (config->source) { + case TIMER_SRC_INTER: + CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK); + break; + + case TIMER_SRC_ETRMODE1: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ETRMODE2: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK); + break; + + case TIMER_SRC_TI1: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_TI2: + timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_TI1ED: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR0: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR1: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR2: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + + case TIMER_SRC_ITR3: + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS); + break; + default: + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param hperh: TIMER handle. + * @param ti1_select: Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg 0: The TIMERx_CH1 pin is connected to TI1 input + * @arg 1: The TIMERx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK, ti1_select << TIMER_CON2_I1FSEL_POS); + return OK; +} + +/** + * @brief Configures the TIMER in Slave mode + * @param hperh: TIMER handle. + * @param config: pointer to a timer_slave_config_t structure that + * contains the selected trigger (internal trigger input, filtered + * timerer input or external trigger input) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_SLAVE_MODE(config->mode)); + assert_param(IS_TIMER_TS(config->input)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + timer_slave_set_config(hperh, config); + ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, DISABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Configures the TIMER in Slave mode in interrupt mode + * @param hperh: TIMER handle. + * @param config: pointer to a timer_slave_config_t structure that + * contains the selected trigger (internal trigger input, filtered + * timerer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_SLAVE_MODE(config->mode)); + assert_param(IS_TIMER_TS(config->input)); + assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity)); + assert_param(IS_TIMER_ETR_PSC(config->psc)); + assert_param(IS_TIMER_IC_FILTER(config->filter)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + timer_slave_set_config(hperh, config); + ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, ENABLE); + ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE); + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return OK; +} + +/** + * @brief Generate a software event + * @param hperh: TIMER handle + * @param event: specifies the event source. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_t event) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_EVENT_SOURCE(event)); + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + WRITE_REG(hperh->perh->SGE, event); + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param hperh: TIMER handle. + * @param ch: TIMER Channels to be enabled + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1 : TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2 : TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3 : TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected + * @retval Captured value + */ +uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch) +{ + uint32_t tmp; + + __LOCK(hperh); + hperh->state = TIMER_STATE_BUSY; + + switch (ch) { + case TIMER_CHANNEL_1: + tmp = hperh->perh->CCVAL1; + break; + case TIMER_CHANNEL_2: + tmp = hperh->perh->CCVAL2; + break; + case TIMER_CHANNEL_3: + tmp = hperh->perh->CCVAL3; + break; + case TIMER_CHANNEL_4: + tmp = hperh->perh->CCVAL4; + break; + default: + tmp = hperh->perh->CCVAL1; + break; + } + + hperh->state = TIMER_STATE_READY; + __UNLOCK(hperh); + return tmp; +} + +/** + * @brief Sets TIMER output mode. + * @param hperh: TIMER handle. + * @param mode: TIMER output mode. + * @param ch: TIMER Channels. + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1 : TIMER Channel 1 selected + * @arg TIMER_CHANNEL_2 : TIMER Channel 2 selected + * @arg TIMER_CHANNEL_3 : TIMER Channel 3 selected + * @arg TIMER_CHANNEL_4 : TIMER Channel 4 selected + * @retval None + */ +void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch) +{ + assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_OC_MODE(mode)); + assert_param(IS_TIMER_CHANNELS(ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS); + break; + case TIMER_CHANNEL_2: + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS); + break; + case TIMER_CHANNEL_3: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS); + break; + case TIMER_CHANNEL_4: + MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS); + break; + default: + break; + } + + return; +} + +/** + * @brief Configure the channel in commutation event. + * @param hperh: TIMER handel + * @param config: Parameters of the channel. + * @retval None + */ +void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config) +{ + uint32_t cm1, cm2, cce; + + assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->ch[0].en)); + assert_param(IS_FUNC_STATE(config->ch[0].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[0].mode)); + assert_param(IS_FUNC_STATE(config->ch[1].en)); + assert_param(IS_FUNC_STATE(config->ch[1].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[1].mode)); + assert_param(IS_FUNC_STATE(config->ch[2].en)); + assert_param(IS_FUNC_STATE(config->ch[2].n_en)); + assert_param(IS_TIMER_OC_MODE(config->ch[2].mode)); + + TIMER_MOE_DISABLE(hperh); + TIMER_DISABLE(hperh); + + cm1 = hperh->perh->CHMR1; + cm2 = hperh->perh->CHMR2; + cce = hperh->perh->CCEP; + + MODIFY_REG(cm1, (0x7 << 4), (config->ch[0].mode << 4)); + MODIFY_REG(cm1, (0x7 << 12), (config->ch[1].mode << 12)); + MODIFY_REG(cm2, (0x7 << 4), (config->ch[2].mode << 4)); + MODIFY_REG(cce, (0x1 << 0), (config->ch[0].en << 0)); + MODIFY_REG(cce, (0x1 << 2), (config->ch[0].n_en << 2)); + MODIFY_REG(cce, (0x1 << 4), (config->ch[1].en << 4)); + MODIFY_REG(cce, (0x1 << 6), (config->ch[1].n_en << 6)); + MODIFY_REG(cce, (0x1 << 8), (config->ch[2].en << 8)); + MODIFY_REG(cce, (0x1 << 10), (config->ch[2].n_en << 10)); + + WRITE_REG(hperh->perh->CHMR1, cm1); + WRITE_REG(hperh->perh->CHMR2, cm2); + WRITE_REG(hperh->perh->CCEP, cce); + + TIMER_MOE_ENABLE(hperh); + TIMER_ENABLE(hperh); + return; +} + +/** + * @brief Configure the TIMER commutation event sequence. + * @param hperh: TIMER handel + * @param ts: the internal trigger corresponding to the timerer interfacing + * with the hall sensor. + * This parameter can be one of the following values: + * @arg TIMER_TS_ITR0 + * @arg TIMER_TS_ITR1 + * @arg TIMER_TS_ITR2 + * @arg TIMER_TS_ITR3 + * @param trgi: the commutation event source. + * This parameter can be one of the following values: + * @arg ENABLE: Commutation event source is TRGI + * @arg DISABLE: Commutation event source is set by software using the COMG bit + * @retval None + */ +void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) +{ + assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_TS(ts)); + assert_param(IS_FUNC_STATE(trgi)); + + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ts << TIMER_SMCON_TSSEL_POSS); + SET_BIT(hperh->perh->CON2, TIMER_CON2_CCPCEN_MSK); + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_CCUSEL_MSK, trgi << TIMER_CON2_CCUSEL_POS); + + return; +} + +/** + * @brief Configure the TIMER commutation event sequence with interrupt. + * @param hperh: TIMER handel + * @param ts: the internal trigger corresponding to the timerer interfacing + * with the hall sensor. + * This parameter can be one of the following values: + * @arg TIMER_TS_ITR0 + * @arg TIMER_TS_ITR1 + * @arg TIMER_TS_ITR2 + * @arg TIMER_TS_ITR3 + * @param trgi: the commutation event source. + * This parameter can be one of the following values: + * @arg ENABLE: Commutation event source is TRGI + * @arg DISABLE: Commutation event source is set by software using the COMG bit + * @retval None + */ +void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi) +{ + ald_timer_com_event_config(hperh, ts, trgi); + ald_timer_interrupt_config(hperh, TIMER_IT_COM, ENABLE); +} + +/** + * @brief Configure the break, dead timere, lock level state. + * @param hperh: TIMER handle + * @param config: Pointer to the timer_break_dead_timere_t structure. + * @retval None + */ +void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config) +{ + uint32_t tmp; + + assert_param(IS_TIMER_BREAK_INSTANCE(hperh->perh)); + assert_param(IS_FUNC_STATE(config->off_run)); + assert_param(IS_FUNC_STATE(config->off_idle)); + assert_param(IS_TIMER_CLOCK_LEVEL(config->lock_level)); + assert_param(IS_TIMER_DEAD_TIMERE(config->dead_time)); + assert_param(IS_FUNC_STATE(config->break_state)); + assert_param(IS_TIMER_BREAK_POLARITY(config->polarity)); + assert_param(IS_FUNC_STATE(config->auto_out)); + + tmp = READ_REG(hperh->perh->BDCFG); + MODIFY_REG(tmp, TIMER_BDCFG_OFFSSR_MSK, config->off_run << TIMER_BDCFG_OFFSSR_POS); + MODIFY_REG(tmp, TIMER_BDCFG_OFFSSI_MSK, config->off_idle << TIMER_BDCFG_OFFSSI_POS); + MODIFY_REG(tmp, TIMER_BDCFG_LOCKLVL_MSK, config->lock_level << TIMER_BDCFG_LOCKLVL_POSS); + MODIFY_REG(tmp, TIMER_BDCFG_DT_MSK, config->dead_time << TIMER_BDCFG_DT_POSS); + MODIFY_REG(tmp, TIMER_BDCFG_BRKEN_MSK, config->break_state << TIMER_BDCFG_BRKEN_POS); + MODIFY_REG(tmp, TIMER_BDCFG_BRKP_MSK, config->polarity << TIMER_BDCFG_BRKP_POS); + MODIFY_REG(tmp, TIMER_BDCFG_AOEN_MSK, config->auto_out << TIMER_BDCFG_AOEN_POS); + WRITE_REG(hperh->perh->BDCFG, tmp); + + hperh->state = TIMER_STATE_READY; + return; +} + +/** + * @brief Configure the master mode + * @param hperh: TIMER handle + * @param config: Pointer to the timer_master_config_t structure. + * @retval None + */ +void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_MASTER_MODE_SEL(config->sel)); + assert_param(IS_FUNC_STATE(config->master_en)); + + hperh->state = TIMER_STATE_BUSY; + MODIFY_REG(hperh->perh->CON2, TIMER_CON2_TRGOSEL_MSK, config->sel << TIMER_CON2_TRGOSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_MSCFG_MSK, config->master_en << TIMER_SMCON_MSCFG_POS); + hperh->state = TIMER_STATE_READY; + + return; +} + +/** + * @brief This function handles TIMER interrupts requests. + * @param hperh: TIMER handle + * @retval None + */ +void ald_timer_irq_handler(timer_handle_t *hperh) +{ + uint32_t reg = hperh->perh->IFM; + + /* Capture or compare 1 event */ + if (READ_BIT(reg, TIMER_FLAG_CC1)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC1); + hperh->ch = TIMER_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 2 event */ + if (READ_BIT(reg, TIMER_FLAG_CC2)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC2); + hperh->ch = TIMER_ACTIVE_CHANNEL_2; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 3 event */ + if (READ_BIT(reg, TIMER_FLAG_CC3)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC3); + hperh->ch = TIMER_ACTIVE_CHANNEL_3; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC3SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + /* Capture or compare 4 event */ + if (READ_BIT(reg, TIMER_FLAG_CC4)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC4); + hperh->ch = TIMER_ACTIVE_CHANNEL_4; + + /* Input capture event */ + if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC4SSEL_MSK)) { + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + } + else { /* Output compare event */ + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + } + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + } + + /* TIMER Update event */ + if (READ_BIT(reg, TIMER_FLAG_UPDATE)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_UPDATE); + + if (hperh->period_elapse_cbk) + hperh->period_elapse_cbk(hperh); + } + + /* TIMER Break input event */ + if (READ_BIT(reg, TIMER_FLAG_BREAK)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_BREAK); + + if (hperh->break_cbk) + hperh->break_cbk(hperh); + } + + /* TIMER Trigger detection event */ + if (READ_BIT(reg, TIMER_FLAG_TRIGGER)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_TRIGGER); + + if (hperh->trigger_cbk) + hperh->trigger_cbk(hperh); + } + + /* TIMER commutation event */ + if (READ_BIT(reg, TIMER_FLAG_COM)) { + ald_timer_clear_flag_status(hperh, TIMER_FLAG_COM); + + if (hperh->com_cbk) + hperh->com_cbk(hperh); + } + + return; +} + +/** + * @brief Configure DMA request source. + * @param hperh: TIMER handle + * @param req: DMA request source. + * @param state: New state of the specified DMA request. + * @retval None + */ +void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->DMAEN, req); + else + CLEAR_BIT(hperh->perh->DMAEN, req); + + return; +} + +/** + * @brief Enable/disable the specified TIMER interrupts. + * @param hperh: Pointer to a timer_handle_t structure. + * @param it: Specifies the timer interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref timer_it_t. + * @param state: New state of the specified TIMER interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + SET_BIT(hperh->perh->IER, it); + else + SET_BIT(hperh->perh->IDR, it); + + return; +} + +/** + * @brief Get the status of TIMER interrupt source. + * @param hperh: Pointer to a timer_handle_t structure. + * @param it: Specifies the TIMER interrupt source. + * This parameter can be one of the @ref timer_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_IT(it)); + + if (hperh->perh->IVS & it) + return SET; + + return RESET; +} + +/** + * @brief Get the status of TIMER interrupt flag. + * @param hperh: Pointer to a timer_handle_t structure. + * @param flag: Specifies the TIMER interrupt flag. + * This parameter can be one of the @ref timer_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_FLAG(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** + * @brief Clear the TIMER interrupt flag. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the TIMER interrupt flag. + * This parameter can be one of the @ref timer_flag_t. + * @retval None + */ +void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag) +{ + assert_param(IS_TIMER_INSTANCE(hperh->perh)); + assert_param(IS_TIMER_FLAG(flag)); + + hperh->perh->ICR = flag; + return; +} +/** + * @} + */ + +/** @defgroup TIMER_Public_Functions_Group12 Peripheral State functions + * @brief Peripheral State functions + * + * @verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permit to get in run-timere the status of the peripheral + and the data flow. + + @endverbatim + * @{ + */ + +/** + * @brief Return the TIMER Base state + * @param hperh: TIMER handle + * @retval TIMER peripheral state + */ +timer_state_t ald_timer_get_state(timer_handle_t *hperh) +{ + return hperh->state; +} +/** + * @} + */ +/** + * @} + */ + +/** @addtogroup TIMER_Private_Functions + * @{ + */ + +#ifdef ALD_DMA +/** + * @brief TIMER DMA out compare complete callback. + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_oc_cplt(void *arg) +{ + timer_handle_t *hperh = (timer_handle_t *)arg; + + if (hperh->delay_elapse_cbk) + hperh->delay_elapse_cbk(hperh); + + if (hperh->pwm_pulse_finish_cbk) + hperh->pwm_pulse_finish_cbk(hperh); + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + return; +} + +/** + * @brief TIMER DMA Capture complete callback. + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_capture_cplt(void *arg) +{ + timer_handle_t *hperh = (timer_handle_t *)arg; + + if (hperh->capture_cbk) + hperh->capture_cbk(hperh); + + hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED; + return; +} + +/** + * @brief TIMER DMA Period Elapse complete callback. + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_period_elapse_cplt(void *arg) +{ + timer_handle_t *hperh = (timer_handle_t *)arg; + + if (hperh->period_elapse_cbk) + hperh->period_elapse_cbk(hperh); + + hperh->state = TIMER_STATE_READY; + return; +} + +/** + * @brief TIMER DMA error callback + * @param arg: pointer to TIMER handle. + * @retval None + */ +void timer_dma_error(void *arg) +{ + timer_handle_t *hperh = (timer_handle_t *)arg; + + hperh->state = TIMER_STATE_READY; + if (hperh->error_cbk) + hperh->error_cbk(hperh); + + return; +} +#endif + +/** + * @brief Time Base configuration + * @param TIMERx: TIMER periheral + * @param init: TIMER Base configuration structure + * @retval None + */ +static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init) +{ + assert_param(IS_TIMER_COUNTER_MODE(init->mode)); + assert_param(IS_TIMER_CLOCK_DIVISION(init->clk_div)); + + if (init->mode == TIMER_CNT_MODE_UP || init->mode == TIMER_CNT_MODE_DOWN) { + CLEAR_BIT(TIMERx->CON1, TIMER_CON1_CMSEL_MSK); + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DIRSEL_MSK, init->mode << TIMER_CON1_DIRSEL_POS); + } + else { + MODIFY_REG(TIMERx->CON1, TIMER_CON1_CMSEL_MSK, (init->mode - 1) << TIMER_CON1_CMSEL_POSS); + } + + if (IS_TIMER_CLOCK_DIVISION_INSTANCE(TIMERx)) + MODIFY_REG(TIMERx->CON1, TIMER_CON1_DFCKSEL_MSK, init->clk_div << TIMER_CON1_DFCKSEL_POSS); + + WRITE_REG(TIMERx->AR, init->period); + WRITE_REG(TIMERx->PRES, init->prescaler); + + if (IS_TIMER_REPETITION_COUNTER_INSTANCE(TIMERx)) + WRITE_REG(TIMERx->REPAR, init->re_cnt); + + return; +} + +/** + * @brief Time Ouput Compare 1 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH1OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC1POL_POS); + + if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_1)) { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC1NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK); + } + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1_MSK, oc_config->oc_idle << TIMER_CON2_OISS1_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS1N_POS); + } + + WRITE_REG(TIMERx->CCVAL1, oc_config->pulse); +} + +/** + * @brief Time Ouput Compare 2 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH2OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC2POL_POS); + + if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_2)) { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC2NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK); + } + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2_MSK, oc_config->oc_idle << TIMER_CON2_OISS2_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS2N_POS); + } + + WRITE_REG(TIMERx->CCVAL2, oc_config->pulse); +} + +/** + * @brief Time Ouput Compare 3 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH3OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC3POL_POS); + + if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_3)) { + assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity)); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC3NPOL_POS); + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK); + } + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle)); + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3_MSK, oc_config->oc_idle << TIMER_CON2_OISS3_POS); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS3N_POS); + } + + WRITE_REG(TIMERx->CCVAL3, oc_config->pulse); +} + +/** + * @brief Time Ouput Compare 4 configuration + * @param TIMERx: Select the TIMER peripheral + * @param oc_config: The ouput configuration structure + * @retval None + */ +static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK); + CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH4OMOD_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC4POL_POS); + + if (IS_TIMER_BREAK_INSTANCE(TIMERx)) { + assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle)); + MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS4_MSK, oc_config->oc_idle << TIMER_CON2_OISS4_POS); + } + + WRITE_REG(TIMERx->CCVAL4, oc_config->pulse); +} + +/** + * @brief Enables or disables the TIMER Capture Compare Channel x. + * @param TIMERx: Select the TIMER peripheral + * @param ch: specifies the TIMER Channel + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @arg TIMER_CHANNEL_4: TIMER Channel 4 + * @param state: specifies the TIMER Channel CCxE bit new state. + * @retval None + */ +static void timer_ccx_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state) +{ + assert_param(IS_TIMER_CC2_INSTANCE(TIMERx)); + assert_param(IS_TIMER_CHANNELS(ch)); + + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS); + break; + + case TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS); + break; + + case TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS); + break; + + case TIMER_CHANNEL_4: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS); + break; + + default: + break; + } +} +/** + * @brief Enables or disables the TIMER Capture Compare Channel xN. + * @param TIMERx: Select the TIMER peripheral + * @param ch: specifies the TIMER Channel + * This parameter can be one of the following values: + * @arg TIMER_CHANNEL_1: TIMER Channel 1 + * @arg TIMER_CHANNEL_2: TIMER Channel 2 + * @arg TIMER_CHANNEL_3: TIMER Channel 3 + * @param state: specifies the TIMER Channel CCxNE bit new state. + * @retval None + */ +static void timer_ccxn_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state) +{ + switch (ch) { + case TIMER_CHANNEL_1: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK, state << TIMER_CCEP_CC1NEN_POS); + break; + + case TIMER_CHANNEL_2: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK, state << TIMER_CCEP_CC2NEN_POS); + break; + + case TIMER_CHANNEL_3: + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK, state << TIMER_CCEP_CC3NEN_POS); + break; + + default: + break; + } + +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, sel << TIMER_CHMR1_CC1SSEL_POSS); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); + + return; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS); + + return; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, sel << TIMER_CHMR1_CC2SSEL_POSS); + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); + + return; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter) +{ + MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS); + return; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, sel << TIMER_CHMR2_CC3SSEL_POSS); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, filter << TIMER_CHMR2_I3FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, polarity << TIMER_CCEP_CC3POL_POS); + + return; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMERx: Select the TIMER peripheral. + * @param polarity: The Input Polarity. + * @param sel: specifies the input to be used. + * @param filter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, + timer_ic_select_t sel, uint32_t filter) +{ + CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, sel << TIMER_CHMR2_CC4SSEL_POSS); + MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, filter << TIMER_CHMR2_I4FLT_POSS); + MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, polarity << TIMER_CCEP_CC4POL_POS); + return; +} + +/** + * @brief Configures the TIMERx External Trigger (ETR). + * @param TIMERx: Select the TIMER peripheral + * @param psc: The external Trigger Prescaler. + * @param polarity: The external Trigger Polarity. + * @param filter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +static void timer_etr_set_config(TIMER_TypeDef* TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter) +{ + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETFLT_MSK, filter << TIMER_SMCON_ETFLT_POSS); + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPSEL_MSK, psc << TIMER_SMCON_ETPSEL_POSS); + CLEAR_BIT(TIMERx->SMCON, TIMER_SMCON_ECM2EN_MSK); + MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPOL_MSK, polarity << TIMER_SMCON_ETPOL_POS); + return; +} + +/** + * @brief Time Slave configuration + * @param hperh: pointer to a timer_handle_t structure that contains + * the configuration information for TIMER module. + * @param config: The slave configuration structure + * @retval None + */ +static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config) +{ + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, config->input << TIMER_SMCON_TSSEL_POSS); + MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS); + + switch (config->input) { + case TIMER_TS_ETRF: + timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter); + break; + + case TIMER_TS_TI1F_ED: + CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK); + MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS); + break; + + case TIMER_TS_TI1FP1: + timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + break; + + case TIMER_TS_TI2FP2: + timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter); + break; + + default: + break; + } +} + +#ifdef ALD_DMA + +/** + * @brief Timer DMA msel signal configuration + * @param hperh: pointer to a timer_handle_t structure that contains + * the configuration information for TIMER module. + * @param config: DMA configuration structure + * @retval None + */ +static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config) +{ + #if defined (ES32F36xx) + if (hperh == AD16C4T0) + config->msel = DMA_MSEL_TIMER0; + if (hperh == AD16C4T1) + config->msel = DMA_MSEL_TIMER1; + if (hperh == GP32C4T0) + config->msel = DMA_MSEL_TIMER2; + if (hperh == GP32C4T1) + config->msel = DMA_MSEL_TIMER3; + if (hperh == BS16T0) + config->msel = DMA_MSEL_TIMER4; + if (hperh == BS16T1) + config->msel = DMA_MSEL_TIMER5; + if (hperh == GP32C4T0) + config->msel = DMA_MSEL_TIMER6; + if (hperh == GP32C4T1) + config->msel = DMA_MSEL_TIMER7; + #elif defined(ES32F39xx) || defined(ES32F336x) + if (hperh == GP16C4T0) + config->msel = DMA_MSEL_TIMER0; + if (hperh == GP16C4T1) + config->msel = DMA_MSEL_TIMER1; + if (hperh == GP32C4T0) + config->msel = DMA_MSEL_TIMER2; + if (hperh == GP32C4T1) + config->msel = DMA_MSEL_TIMER3; + if (hperh == BS16T0) + config->msel = DMA_MSEL_TIMER4; + if (hperh == BS16T1) + config->msel = DMA_MSEL_TIMER5; + if (hperh == GP16C4T2) + config->msel = DMA_MSEL_TIMER6; + if (hperh == GP16C4T3) + config->msel = DMA_MSEL_TIMER7; + #endif +} + +#endif + +/** + * @} + */ +#endif /* ALD_TIMER */ +/** + * @} + */ +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_trng.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_trng.c new file mode 100644 index 00000000..e524dafc --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_trng.c @@ -0,0 +1,323 @@ +/** + ********************************************************************************* + * + * @file ald_trng.c + * @brief TRNG module driver. + * + * @version V1.0 + * @date 26 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 26 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup TRNG TRNG + * @brief TRNG module driver + * @{ + */ +#ifdef ALD_TRNG + +/** @addtogroup CRYPT_Private_Functions CRYPT Private Functions + * @{ + */ +void trng_reset(trng_handle_t *hperh); +/** + * @} + */ + +/** @defgroup TRNG_Public_Functions TRNG Public Functions + * @{ + */ + +/** @addtogroup TRNG_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * + * @verbatim + ============================================================================== + ##### Initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to initialize the TRNG: + (+) This parameters can be configured: + (++) Word Width + (++) Seed Type + (++) Seed + (++) Start Time + (++) Adjust parameter + + @endverbatim + * @{ + */ + + +/** + * @brief Initializes the TRNG according to the specified + * parameters in the trng_init_t. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_trng_init(trng_handle_t *hperh) +{ + uint32_t tmp = 0; + + if (hperh == NULL) + return ERROR; + + assert_param(IS_TRNG_DATA_WIDTH(hperh->init.data_width)); + assert_param(IS_TRNG_SEED_TYPE(hperh->init.seed_type)); + assert_param(IS_TRNG_ADJC(hperh->init.adjc)); + assert_param(IS_FUNC_STATE(hperh->init.posten)); + assert_param(IS_TRNG_T_START(hperh->init.t_start)); + + __LOCK(hperh); + trng_reset(hperh); + + if (hperh->state == TRNG_STATE_RESET) + __UNLOCK(hperh); + + tmp = TRNG->CR; + + if (hperh->init.adjc == 0) + tmp = (0 << TRNG_CR_ADJM_POS); + else + tmp = (1 << TRNG_CR_ADJM_POS); + + tmp |= ((1 << TRNG_CR_TRNGSEL_POS) | (hperh->init.data_width << TRNG_CR_DSEL_POSS) | + (hperh->init.seed_type << TRNG_CR_SDSEL_POSS) | (hperh->init.adjc << TRNG_CR_ADJC_POSS) | + (hperh->init.posten << TRNG_CR_POSTEN_MSK)); + + TRNG->CR = tmp; + + WRITE_REG(TRNG->SEED, hperh->init.seed); + MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (hperh->init.t_start) << TRNG_CFGR_TSTART_POSS); + + hperh->state = TRNG_STATE_READY; + __UNLOCK(hperh); + return OK; +} +/** + * @} + */ + +/** @addtogroup TRNG_Public_Functions_Group2 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) ald_trng_get_result() API can Get the result. + (+) ald_trng_interrupt_config() API can be helpful to configure TRNG interrupt source. + (+) ald_trng_get_it_status() API can get the status of interrupt source. + (+) ald_trng_get_status() API can get the status of SR register. + (+) ald_trng_get_flag_status() API can get the status of interrupt flag. + (+) ald_trng_clear_flag_status() API can clear interrupt flag. + + @endverbatim + * @{ + */ + +/** + * @brief Get the result. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @retval The resultl + */ +uint32_t ald_trng_get_result(trng_handle_t *hperh) +{ + hperh->state = TRNG_STATE_READY; + hperh->data = hperh->perh->DR; + return (uint32_t)hperh->perh->DR; +} + +/** + * @brief Enable/disable the specified interrupts. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @param it: Specifies the interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref trng_it_t. + * @param state: New state of the specified interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state) +{ + assert_param(IS_TRNG_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state) + SET_BIT(hperh->perh->IER, it); + else + CLEAR_BIT(hperh->perh->IER, it); + + return; +} + +/** + * @brief Get the status of SR register. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @param status: Specifies the TRNG status type. + * This parameter can be one of the @ref trng_status_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status) +{ + assert_param(IS_TRNG_STATUS(status)); + + if (READ_BIT(hperh->perh->SR, status)) + return SET; + + return RESET; +} + +/** + * @brief Get the status of interrupt source. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @param it: Specifies the interrupt source. + * This parameter can be one of the @ref trng_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it) +{ + assert_param(IS_TRNG_IT(it)); + + if (READ_BIT(hperh->perh->IER, it)) + return SET; + + return RESET; +} + +/** + * @brief Get the status of interrupt flag. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @param flag: Specifies the interrupt flag. + * This parameter can be one of the @ref trng_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag) +{ + assert_param(IS_TRNG_FLAG(flag)); + + if (READ_BIT(hperh->perh->IFR, flag)) + return SET; + + return RESET; +} + +/** + * @brief Clear the interrupt flag. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @param flag: Specifies the interrupt flag. + * This parameter can be one of the @ref trng_flag_t. + * @retval None + */ +void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag) +{ + assert_param(IS_TRNG_FLAG(flag)); + WRITE_REG(hperh->perh->IFCR, flag); + + return; +} + +/** + * @brief Reset the TRNG peripheral. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @retval None + */ +void trng_reset(trng_handle_t *hperh) +{ + TRNG->CR = 0; + TRNG->SEED = 0; + TRNG->CFGR = 0x1FF0707; + TRNG->IER = 0; + TRNG->IFCR = 0xFFFFFFFF; + + hperh->state = TRNG_STATE_READY; + __UNLOCK(hperh); + return; +} + +/** + * @brief This function handles TRNG interrupt request. + * @param hperh: Pointer to a trng_handle_t structure that contains + * the configuration information for the specified TRNG module. + * @retval None + */ +void ald_trng_irq_handler(trng_handle_t *hperh) +{ + if (ald_trng_get_flag_status(hperh, TRNG_IF_SERR) == SET) { + hperh->state = TRNG_STATE_ERROR; + ald_trng_clear_flag_status(hperh, TRNG_IF_SERR); + if (hperh->err_cplt_cbk) + hperh->err_cplt_cbk(hperh); + return; + } + + if (ald_trng_get_flag_status(hperh, TRNG_IF_DAVLD) == SET) { + hperh->data = hperh->perh->DR; + hperh->state = TRNG_STATE_READY; + ald_trng_clear_flag_status(hperh, TRNG_IF_DAVLD); + if (hperh->trng_cplt_cbk) + hperh->trng_cplt_cbk(hperh); + } + + if (ald_trng_get_flag_status(hperh, TRNG_IF_START) == SET) { + hperh->state = TRNG_STATE_BUSY; + ald_trng_clear_flag_status(hperh, TRNG_IF_START); + if (hperh->init_cplt_cbk) + hperh->init_cplt_cbk(hperh); + } +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_TRNG */ +/** + * @} + */ +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_tsense.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_tsense.c new file mode 100644 index 00000000..30b64307 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_tsense.c @@ -0,0 +1,271 @@ +/** + ********************************************************************************* + * + * @file ald_tsense.c + * @brief TSENSE module driver. + * + * @version V1.0 + * @date 26 Jun 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 26 Jun 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup TSENSE TSENSE + * @brief TSENSE module driver + * @{ + */ +#ifdef ALD_TSENSE + + +/** @defgroup TSENSE_Private_Variables TSENSE Private Variables + * @{ + */ +tsense_cbk __tsense_cbk; +/** + * @} + */ + +/** @defgroup TSENSE_Public_Functions TSENSE Public Functions + * @{ + */ + +/** @addtogroup TSENSE_Public_Functions_Group1 Initialization functions + * @brief Initialization functions + * + * @verbatim + ============================================================================== + ##### Initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to initialize the TSENSE: + (+) This parameters can be configured: + (++) Update Cycle + (++) Output Mode + (++) Perscaler + (+) Select TSENSE source clock(default LOSC) + + @endverbatim + * @{ + */ + +/** + * @brief Initializes the TSENSE according to the specified + * @retval None + */ +void ald_tsense_init(void) +{ + uint16_t tempt, temptinv; + uint32_t tscic, tscicinv; + + TSENSE_UNLOCK(); + TSENSE->CR = 0; + + SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); + SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); + MODIFY_REG(TSENSE->CR, TSENSE_CR_TSU_MSK, 0x4 << TSENSE_CR_TSU_POSS); + MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, 0x3 << TSENSE_CR_TOM_POSS); + MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, 0x1 << TSENSE_PSR_PRS_POSS); + + TSENSE->HTGR = 0x8564F; + TSENSE->LTGR = 0x87037; + tempt = *(volatile uint16_t *)0x80348; + temptinv = *(volatile uint16_t *)0x8034A; + tscic = *(volatile uint32_t *)0x80350; + tscicinv = *(volatile uint32_t *)0x80358; + + if ((tempt == (uint16_t)(~temptinv)) && (tscic == (~tscicinv))) { + TSENSE->TBDR = tempt; + TSENSE->TCALBDR = (tscic & 0x1FFFFFF) >> 6; + } + else { + TSENSE->TBDR = 0x1E00; + TSENSE->TCALBDR = 0x1F849; + } + + TSENSE_LOCK(); + return; +} + +/** + * @brief Configure the TSENSE source. + * @param sel: TSENSE source type. + * @retval None + */ +void ald_tsense_source_select(tsense_source_sel_t sel) +{ + assert_param(IS_TSENSE_SOURCE_SEL(sel)); + + BKPC_UNLOCK(); + MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, sel << BKPC_PCCR_TSENSECS_POSS); + + if (sel == TSENSE_SOURCE_LOSC) { + SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); + } + else if (sel == TSENSE_SOURCE_LRC) { + SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); + } + else { + ; /* do nothing */ + } + + BKPC_LOCK(); + return; +} +/** + * @} + */ + +/** @addtogroup TSENSE_Public_Functions_Group2 Peripheral Control functions + * @brief Peripheral Control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) ald_tsense_get_value() API can get the current temperature. + (+) ald_tsense_get_value_by_it() API can get the current temperature by interrupt. + (+) ald_tsense_irq_handler() API can handle the interrupt request. + + @endverbatim + * @{ + */ + +/** + * @brief Get the current temperature + * @param tsense: The value of current temperature. + * @retval ALD status: + * @arg @ref OK The value is valid + * @arg @ref ERROR The value is invalid + */ +ald_status_t ald_tsense_get_value(uint16_t *tsense) +{ + uint32_t tmp = 0; + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + + while ((!(READ_BIT(TSENSE->IF, TSENSE_IF_TSENSE_MSK))) && (tmp++ < 1000000)); + + if (tmp >= 1000000) { + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + return TIMEOUT; + } + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + TSENSE_LOCK(); + + if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) { + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + return ERROR; + } + + *tsense = READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS); + + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + + return OK; +} + +/** + * @brief Get the current temperature by interrupt + * @param cbk: The callback function + * @retval None + */ +void ald_tsense_get_value_by_it(tsense_cbk cbk) +{ + __tsense_cbk = cbk; + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + SET_BIT(TSENSE->IE, TSENSE_IE_TSENSE_MSK); + SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + + return; +} + +/** + * @brief This function handles TSENSE interrupt request. + * @retval None + */ +void ald_tsense_irq_handler(void) +{ + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + TSENSE_LOCK(); + + if (__tsense_cbk == NULL) { + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + return; + } + + if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) { + TSENSE_UNLOCK(); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + __tsense_cbk(0, ERROR); + + return; + } + + __tsense_cbk(READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS), OK); + + TSENSE_UNLOCK(); + SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK); + CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); + TSENSE_LOCK(); + + return; +} +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_TSENSE */ +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_uart.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_uart.c new file mode 100644 index 00000000..e7f29707 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_uart.c @@ -0,0 +1,1543 @@ +/** + ********************************************************************************* + * + * @file ald_uart.c + * @brief UART module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + * + Initialization and Configuration functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + * @version V1.0 + * @date 21 Nov 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 21 Nov 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The UART driver can be used as follows: + + (#) Declare a uart_handle_t handle structure. + + (#) Initialize the UART low level resources: + (##) Enable the UARTx interface clock. + (##) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure the UART pins (TX as alternate function pull-up, RX as alternate function Input). + (##) NVIC configuration if you need to use interrupt process (ald_uart_send_by_it() + and ald_uart_recv_by_it() APIs): + (+++) Configure the uart interrupt priority. + (+++) Enable the NVIC UART IRQ handle. + (##) DMA Configuration if you need to use DMA process (ald_uart_send_by_dma() + and ald_uart_recv_by_dma() APIs): + (+++) Select the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) in the hperh Init structure. + + (#) Initialize the UART registers by calling the ald_uart_init() API. + + [..] + Three operation modes are available within this driver: + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using ald_uart_send() + (+) Receive an amount of data in blocking mode using ald_uart_recv() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using ald_uart_send_by_it() + (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->tx_cplt_cbk() + (+) Receive an amount of data in non blocking mode using ald_uart_recv_by_it() + (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_cbk() function is executed and user can + add his own code by customization of function pointer hperh->error_cbk() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using ald_uart_send_by_dma() + (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->tx_cplt_cbk() + (+) Receive an amount of data in non blocking mode (DMA) using ald_uart_recv_by_dma() + (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can + add his own code by customization of function pointer hperh->rx_cplt_cbk() + (+) In case of transfer Error, hperh->error_cbk() function is executed and user can + add his own code by customization of function pointer hperh->error_cbk() + (+) Pause the DMA Transfer using ald_uart_dma_pause() + (+) Resume the DMA Transfer using ald_uart_dma_resume() + (+) Stop the DMA Transfer using ald_uart_dma_stop() + + @endverbatim + ****************************************************************************** + */ + +#include "ald_conf.h" + + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup UART UART + * @brief UART module driver + * @{ + */ +#ifdef ALD_UART + +/** @defgroup UART_Private_Functions UART Private Functions + * @brief UART Private functions + * @{ + */ +#ifdef ALD_DMA +/** + * @brief DMA uart transmit process complete callback. + * @param arg: Pointer to a uart_handle_t structure. + * @retval None + */ +static void uart_dma_send_cplt(void *arg) +{ + uart_handle_t *hperh = (uart_handle_t *)arg; + hperh->tx_count = hperh->tx_size; + + ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE); + hperh->tx_count = 0; + ald_uart_interrupt_config(hperh, UART_IT_TBC, ENABLE); + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + + return; +} + +/** + * @brief DMA uart receive process complete callback. + * @param arg: Pointer to a uart_handle_t structure. + * @retval None + */ +static void uart_dma_recv_cplt(void *arg) +{ + uint32_t stat = 0; + + uart_handle_t *hperh = (uart_handle_t *)arg; + hperh->tx_count = hperh->tx_size; + + ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE); + hperh->rx_count = 0; + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + stat = hperh->perh->STAT; + + /* Handle parity error */ + if ((READ_BIT(stat, UART_STATUS_PERR)) != RESET) + hperh->err_code |= UART_ERROR_PE; + + /* Handle frame error */ + if ((READ_BIT(stat, UART_STATUS_FERR)) != RESET) + hperh->err_code |= UART_ERROR_FE; + + /* Handle rx overflow error */ + if ((READ_BIT(stat, UART_STATUS_RFOERR)) != RESET) { + hperh->err_code |= UART_ERROR_ORE; + UART_FIFO_RX_RESET(hperh); + } + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + + return; +} + +/** + * @brief DMA uart communication error callback. + * @param arg: Pointer to a uart_handle_t structure. + * @retval None + */ +static void uart_dma_error(void *arg) +{ + uart_handle_t *hperh = (uart_handle_t *)arg; + + hperh->rx_count = 0; + hperh->tx_count = 0; + hperh->state = UART_STATE_READY; + hperh->err_code |= UART_ERROR_DMA; + ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE); + ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE); + + if (hperh->error_cbk) + hperh->error_cbk(hperh); + + return; +} +#endif + +/** + * @brief This function handles uart Communication Timeout. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: specifies the uart flag to check. + * @param status: The new Flag status (SET or RESET). + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, flag_status_t status, uint32_t timeout) +{ + uint32_t tick; + + if (timeout == 0) + return ERROR; + + tick = ald_get_tick(); + + /* Waiting for flag */ + while ((ald_uart_get_status(hperh, flag)) != status) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + + return OK; +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __uart_send_by_it(uart_handle_t *hperh) +{ + if ((hperh->state & UART_STATE_TX_MASK) == 0x0) + return BUSY; + + while(hperh->perh->STAT & (0x1 << 17)); + hperh->perh->TXBUF = (uint8_t)(*hperh->tx_buf++ & 0x00FF); + hperh->tx_count++; + + if (hperh->tx_count >= hperh->tx_size) { + ald_uart_interrupt_config(hperh, UART_IT_TFTH, DISABLE); + ald_uart_interrupt_config(hperh, UART_IT_TBC, ENABLE); + } + + return OK; +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param hperh: pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __uart_end_send_by_it(uart_handle_t *hperh) +{ + uint32_t cnt = 0xFFFFFF; + + ald_uart_interrupt_config(hperh, UART_IT_TBC, DISABLE); + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + + while ((hperh->perh->STAT & UART_STATUS_TSBUSY) && (cnt--)); + ald_uart_clear_flag_status(hperh, UART_IF_TBC); + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + + return OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +static ald_status_t __uart_recv_by_it(uart_handle_t *hperh) +{ + if ((hperh->state & UART_STATE_RX_MASK) == 0x0) + return BUSY; + + while (READ_BITS(hperh->perh->FCON, UART_FCON_RXFL_MSK, UART_FCON_RXFL_POSS)) { + *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + hperh->rx_count++; + + if (hperh->rx_count >= hperh->rx_size) + break; + } + + if (hperh->rx_count >= hperh->rx_size) { + ald_uart_interrupt_config(hperh, UART_IT_RFTH, DISABLE); + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return OK; +} +/** + * @} + */ +/** @defgroup UART_Public_Functions UART Public Functions + * @{ + */ +/** @defgroup UART_Public_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * + * @verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the UARTx + and configure UARTx param. + (+) For the UARTx only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity + (++) Hardware flow control + (+) For RS485 mode, user also need configure some parameters by + ald_uart_rs485_config(): + (++) Enable/disable normal point mode + (++) Enable/disable auto-direction + (++) Enable/disable address detection invert + (++) Enable/disable address for compare + + @endverbatim + * @{ + */ + +/** + * @brief Reset UART peripheral + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified uart module. + * @retval None + */ +void ald_uart_reset(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + + WRITE_REG(hperh->perh->BRR, 0x0); + WRITE_REG(hperh->perh->LCON, 0x0); + WRITE_REG(hperh->perh->MCON, 0x0); + WRITE_REG(hperh->perh->RS485, 0x0); + WRITE_REG(hperh->perh->SCARD, 0x0); + WRITE_REG(hperh->perh->LIN, 0x0); + WRITE_REG(hperh->perh->RTOR, 0x0); + WRITE_REG(hperh->perh->FCON, 0x0); + WRITE_REG(hperh->perh->IDR, 0xFFF); + hperh->err_code = UART_ERROR_NONE; + hperh->state = UART_STATE_RESET; + + __UNLOCK(hperh); + return; +} + +/** + * @brief Initializes the UARTx according to the specified + * parameters in the uart_handle_t. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +void ald_uart_init(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_BAUDRATE(hperh->init.baud)); + assert_param(IS_UART_WORD_LENGTH(hperh->init.word_length)); + assert_param(IS_UART_STOPBITS(hperh->init.stop_bits)); + assert_param(IS_UART_PARITY(hperh->init.parity)); + assert_param(IS_UART_MODE(hperh->init.mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(hperh->init.fctl)); + + ald_uart_reset(hperh); + + MODIFY_REG(hperh->perh->LCON, UART_LCON_DLS_MSK, hperh->init.word_length << UART_LCON_DLS_POSS); + MODIFY_REG(hperh->perh->LCON, UART_LCON_STOP_MSK, hperh->init.stop_bits << UART_LCON_STOP_POS); + + if ((hperh->init.parity) != UART_PARITY_NONE) { + SET_BIT(hperh->perh->LCON, UART_LCON_PE_MSK); + + if ((hperh->init.parity) == UART_PARITY_ODD) + CLEAR_BIT(hperh->perh->LCON, UART_LCON_PS_MSK); + + if ((hperh->init.parity) == UART_PARITY_EVEN) + SET_BIT(hperh->perh->LCON, UART_LCON_PS_MSK); + } + + MODIFY_REG(hperh->perh->MCON, UART_MCON_AFCEN_MSK, hperh->init.fctl << UART_MCON_AFCEN_POS); + hperh->perh->BRR = (ald_cmu_get_pclk1_clock() + (hperh->init.baud >> 1)) / hperh->init.baud; + + if (hperh->init.mode == UART_MODE_LIN) + SET_BIT(hperh->perh->LIN, UART_LIN_LINEN_MSK); + else if (hperh->init.mode == UART_MODE_IrDA) + SET_BIT(hperh->perh->MCON, UART_MCON_IREN_MSK); + else if (hperh->init.mode == UART_MODE_RS485) + SET_BIT(hperh->perh->RS485, UART_RS485_AADEN_MSK); + else if (hperh->init.mode == UART_MODE_HDSEL) + SET_BIT(hperh->perh->MCON, UART_MCON_HDEN_MSK); + else if (hperh->init.mode == UART_MODE_SCARD) + SET_BIT(hperh->perh->SCARD, UART_SCARD_SCEN_MSK); + else + ; /* do nothing */ + + SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK); + SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK); + CLEAR_BIT(hperh->perh->FCON, UART_FCON_TXTH_MSK); + CLEAR_BIT(hperh->perh->FCON, UART_FCON_RXTH_MSK); + SET_BIT(hperh->perh->LCON, UART_LCON_RXEN_MSK); + SET_BIT(hperh->perh->LCON, UART_LCON_TXEN_MSK); + + hperh->state = UART_STATE_READY; + hperh->err_code = UART_ERROR_NONE; + return; +} + +/** + * @brief Configure the RS485 mode according to the specified + * parameters in the uart_rs485_config_t. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @param config: Specifies the RS485 parameters. + * @retval None + */ +void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_FUNC_STATE(config->normal)); + assert_param(IS_FUNC_STATE(config->dir)); + assert_param(IS_FUNC_STATE(config->invert)); + + MODIFY_REG(hperh->perh->RS485, UART_RS485_AADNEN_MSK, config->normal << UART_RS485_AADNEN_POS); + MODIFY_REG(hperh->perh->RS485, UART_RS485_AADACEN_MSK, config->dir << UART_RS485_AADACEN_POS); + MODIFY_REG(hperh->perh->RS485, UART_RS485_AADINV_MSK, config->invert << UART_RS485_AADINV_POS); + MODIFY_REG(hperh->perh->RS485, UART_RS485_ADDR_MSK, config->addr << UART_RS485_ADDR_POSS); + + return; +} + +/** + * @brief Configure the smart card mode according to the specified + * parameters in the uart_scard_config_t. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @param config: Specifies the scard parameters. + * @retval None + */ +void ald_uart_scard_config(uart_handle_t *hperh, uart_scard_config_t *config) +{ + assert_param(IS_UART_SCARD(hperh->perh)); + assert_param(IS_UART_SCARD_CLK(config->clk_div)); + + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_BLEN_MSK, config->block_len << UART_SCARD_BLEN_POSS); + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_GT_MSK, config->pt << UART_SCARD_GT_POSS); + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_SCCNT_MSK, config->retry << UART_SCARD_SCCNT_POSS); + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_PSC_MSK, config->clk_div << UART_SCARD_PSC_POSS); + MODIFY_REG(hperh->perh->SCARD, UART_SCARD_SCLKEN_MSK, config->clk_out << UART_SCARD_SCLKEN_POS); + + return; +} +/** + * @} + */ + +/** @defgroup UART_Public_Functions_Group2 IO operation functions + * @brief UART Transmit and Receive functions + * @verbatim + ============================================================================== + # IO operation functions # + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the UART data transfers. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The Status of all data processing is returned by the same function + after finishing transfer. + (++) Non blocking mode: The communication is performed using Interrupts + or DMA, these APIs return the Status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks + will be executed respectively at the end of the transmit or receive process. + The hperh->error_cbk() user callback will be executed when + a communication error is detected. + + (#) Blocking mode APIs are: + (++) ald_uart_send() + (++) ald_uart_recv() + + (#) Non Blocking mode APIs with Interrupt are: + (++) ald_uart_send_by_it() + (++) ald_uart_recv_by_it() + (++) ald_uart_irq_handler() + + (#) Non Blocking mode functions with DMA are: + (++) ald_uart_send_by_dma() + (++) ald_uart_recv_by_dma() + (++) ald_uart_dma_pause() + (++) ald_uart_dma_resume() + (++) ald_uart_dma_stop() + + (#) A set of transfer complete callbacks are provided in non blocking mode: + (++) hperh->tx_cplt_cbk() + (++) hperh->rx_cplt_cbk() + (++) hperh->error_cbk() + + @endverbatim + * @{ + */ + +/** + * @brief Sends an amount of data in blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); + + hperh->tx_size = size; + hperh->tx_count = 0; + SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK); + + while (size-- > 0) { + if (uart_wait_flag(hperh, UART_STATUS_TFTH, SET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + while(hperh->perh->STAT & (0x1 << 17)); + hperh->perh->TXBUF = (*buf++ & 0xFF); + hperh->tx_count++; + } + + if (uart_wait_flag(hperh, UART_STATUS_TSBUSY, RESET, timeout) != OK) { + __UNLOCK(hperh); + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + __UNLOCK(hperh); + + return OK; +} + +/** + * @brief Receives an amount of data in blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + uint32_t stat = 0; + uint32_t err = 0; + uint32_t tick = 0; + + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL) || (size == 0) || (timeout == 0)) + return ERROR; + + __LOCK(hperh); + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + + hperh->rx_size = size; + hperh->rx_count = 0; + SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK); + + err = (UART_STATUS_PERR | UART_STATUS_FERR | UART_STATUS_RFOERR); + + while (size-- > 0) { + tick = ald_get_tick(); + + /* Waiting for flag */ + while (1) { + stat = hperh->perh->STAT; + if (READ_BIT(stat, UART_STATUS_RFTH) != RESET) + break; + + if (((ald_get_tick()) - tick) > timeout) { + __UNLOCK(hperh); + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + } + if ((stat & err) == RESET) { + *buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + hperh->rx_count++; + } + else { + /* Handle parity error */ + if ((READ_BIT(stat, UART_STATUS_PERR)) != RESET) + hperh->err_code |= UART_ERROR_PE; + + /* Handle frame error */ + if ((READ_BIT(stat, UART_STATUS_FERR)) != RESET) + hperh->err_code |= UART_ERROR_FE; + + /* Handle rx overflow error */ + if ((READ_BIT(stat, UART_STATUS_RFOERR)) != RESET) { + hperh->err_code |= UART_ERROR_ORE; + UART_FIFO_RX_RESET(hperh); + } + + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + __UNLOCK(hperh); + + return ERROR; + } + } + + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + __UNLOCK(hperh); + + return OK; + +} + +/** + * @brief Sends an amount of data in blocking mode. + Don't care about device lock. This is for RTOS. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_send_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; + + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); + + hperh->tx_size = size; + hperh->tx_count = 0; + SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK); + + while (size-- > 0) { + if (uart_wait_flag(hperh, UART_STATUS_TFTH, SET, timeout) != OK) { + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + while(hperh->perh->STAT & (0x1 << 17)); + hperh->perh->TXBUF = (*buf++ & 0xFF); + hperh->tx_count++; + } + + if (uart_wait_flag(hperh, UART_STATUS_TSBUSY, RESET, timeout) != OK) { + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + return OK; +} + +/** + * @brief Receives an amount of data in blocking mode. + Don't care about device lock. This is for RTOS. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param timeout: Timeout duration + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; + if ((buf == NULL) || (size == 0)) + return ERROR; + + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + + hperh->rx_size = size; + hperh->rx_count = 0; + SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK); + + while (size-- > 0) { + if (uart_wait_flag(hperh, UART_STATUS_RFTH, SET, timeout) != OK) { + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + *buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + hperh->rx_count++; + } + + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + return OK; + +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = 0; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); + + __UNLOCK(hperh); + SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK); + SET_BIT(hperh->perh->ICR, UART_ICR_TFTH_MSK); + ald_uart_interrupt_config(hperh, UART_IT_TFTH, ENABLE); + + return OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = 0; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + + __UNLOCK(hperh); + SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK); + SET_BIT(hperh->perh->ICR, UART_ICR_RFTH_MSK); + ald_uart_interrupt_config(hperh, UART_IT_RFTH, ENABLE); + return OK; +} + + +/** + * @brief Receives an frame of data in non blocking mode + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Max length of frame. + * @param t_out: Timeout duration. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv_frame_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL ) || (t_out == 0) || (t_out > 0xFFFFFF) || (size == 0)) + return ERROR; + + __LOCK(hperh); + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->rx_count = 0; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + + __UNLOCK(hperh); + SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK); + SET_BIT(hperh->perh->ICR, UART_ICR_RFTH_MSK); + SET_BIT(hperh->perh->RTOR, UART_RTOR_RTOEN_MSK); + MODIFY_REG(hperh->perh->RTOR, UART_RTOR_RTO_MSK, t_out << UART_RTOR_RTO_POSS); + ald_uart_interrupt_config(hperh, UART_IT_RFTH, ENABLE); + ald_uart_interrupt_config(hperh, UART_IT_RXTO, ENABLE); + return OK; +} + +#ifdef ALD_DMA +/** + * @brief Sends an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be sent + * @param channel: DMA channel as UART transmit + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + + if ((buf == NULL ) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->tx_buf = buf; + hperh->tx_size = size; + hperh->tx_count = 0; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_TX_MASK); + + if (hperh->hdmatx.perh == NULL) + hperh->hdmatx.perh = DMA0; + + /* Set the dma parameters */ + hperh->hdmatx.cplt_cbk = uart_dma_send_cplt; + hperh->hdmatx.cplt_arg = (void *)hperh; + hperh->hdmatx.err_cbk = uart_dma_error; + hperh->hdmatx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmatx.config); + hperh->hdmatx.config.src = (void *)buf; + hperh->hdmatx.config.dst = (void *)&hperh->perh->TXBUF; + hperh->hdmatx.config.size = size; + hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE; + hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE; + if ((hperh->perh == UART4) || (hperh->perh == UART5)) { + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_UART45_TXEMPTY; + } else { + hperh->hdmatx.config.msigsel = DMA_MSIGSEL_UART_TXEMPTY; + } + hperh->hdmatx.config.burst = ENABLE; + hperh->hdmatx.config.channel = channel; + + if (hperh->init.mode == UART_MODE_RS485) { + hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + if (hperh->perh == UART0) + hperh->hdmatx.config.msel = DMA_MSEL_UART0; + else if (hperh->perh == UART1) + hperh->hdmatx.config.msel = DMA_MSEL_UART1; + else if (hperh->perh == UART2) + hperh->hdmatx.config.msel = DMA_MSEL_UART2; + else if (hperh->perh == UART3) + hperh->hdmatx.config.msel = DMA_MSEL_UART3; + else if (hperh->perh == UART4) + hperh->hdmatx.config.msel = DMA_MSEL_UART4; + else if (hperh->perh == UART5) + hperh->hdmatx.config.msel = DMA_MSEL_UART5; + else + ; /* do nothing */ + + ald_dma_config_basic(&hperh->hdmatx); + + __UNLOCK(hperh); + SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK); + ald_uart_clear_flag_status(hperh, UART_IF_TBC); + ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, ENABLE); + + + return OK; +} + +/** + * @brief Receives an amount of data in non blocking mode. + * @param hperh: Pointer to a uart_handle_t structure. + * @param buf: Pointer to data buffer + * @param size: Amount of data to be received + * @param channel: DMA channel as UART receive + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX)) + return BUSY; + + if ((buf == NULL) || (size == 0)) + return ERROR; + + __LOCK(hperh); + + hperh->rx_buf = buf; + hperh->rx_size = size; + hperh->err_code = UART_ERROR_NONE; + SET_BIT(hperh->state, UART_STATE_RX_MASK); + + if (hperh->hdmarx.perh == NULL) + hperh->hdmarx.perh = DMA0; + + /* Set the dma parameters */ + hperh->hdmarx.cplt_cbk = uart_dma_recv_cplt; + hperh->hdmarx.cplt_arg = (void *)hperh; + hperh->hdmarx.err_cbk = uart_dma_error; + hperh->hdmarx.err_arg = (void *)hperh; + + ald_dma_config_struct(&hperh->hdmarx.config); + hperh->hdmarx.config.src = (void *)&hperh->perh->RXBUF; + hperh->hdmarx.config.dst = (void *)buf; + hperh->hdmarx.config.size = size; + hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE; + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE; + if ((hperh->perh == UART4) || (hperh->perh == UART5)) { + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART45_RNR; + } else { + hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART_RNR; + } + + hperh->hdmarx.config.burst = ENABLE; + hperh->hdmarx.config.channel = channel; + + if (hperh->init.mode == UART_MODE_RS485) { + hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD; + hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD; + } + + if (hperh->perh == UART0) + hperh->hdmarx.config.msel = DMA_MSEL_UART0; + else if (hperh->perh == UART1) + hperh->hdmarx.config.msel = DMA_MSEL_UART1; + else if (hperh->perh == UART2) + hperh->hdmarx.config.msel = DMA_MSEL_UART2; + else if (hperh->perh == UART3) + hperh->hdmarx.config.msel = DMA_MSEL_UART3; + else if (hperh->perh == UART4) + hperh->hdmarx.config.msel = DMA_MSEL_UART4; + else if (hperh->perh == UART5) + hperh->hdmarx.config.msel = DMA_MSEL_UART5; + else + ; + + __UNLOCK(hperh); + ald_dma_config_basic(&hperh->hdmarx); + SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK); + ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, ENABLE); + + return OK; +} + +/** + * @brief Pauses the DMA Transfer. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_dma_pause(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE); + ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE); + return OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_dma_resume(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, ENABLE); + ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, ENABLE); + return OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_uart_dma_stop(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE); + ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE); + hperh->state = UART_STATE_READY; + return OK; +} +#endif + +/** + * @brief This function handles UART interrupt request. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval None + */ +void ald_uart_irq_handler(uart_handle_t *hperh) +{ + uint32_t stat = 0; + + assert_param(IS_UART_ALL(hperh->perh)); + + stat = hperh->perh->STAT; + + /* Handle parity error */ + if (((READ_BIT(stat, UART_STATUS_PERR)) != RESET) && \ + (ald_uart_get_state(hperh)) == UART_STATE_RX_MASK) + hperh->err_code |= UART_ERROR_PE; + + /* Handle frame error */ + if (((READ_BIT(stat, UART_STATUS_FERR)) != RESET) && \ + (ald_uart_get_state(hperh)) == UART_STATE_RX_MASK) + hperh->err_code |= UART_ERROR_FE; + + /* Handle rx overflow error */ + if (((READ_BIT(stat, UART_STATUS_RFOERR)) != RESET) && \ + (ald_uart_get_state(hperh)) == UART_STATE_RX_MASK) { + hperh->err_code |= UART_ERROR_ORE; + UART_FIFO_RX_RESET(hperh); + } + + /* Handle tx overflow error */ + if (((READ_BIT(stat, UART_STATUS_TFOERR)) != RESET) && \ + (ald_uart_get_state(hperh)) == UART_STATE_TX_MASK) { + hperh->err_code |= UART_ERROR_ORE; + UART_FIFO_TX_RESET(hperh); + } + + /* Receive */ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RFTH)) != RESET) { + ald_uart_clear_flag_status(hperh, UART_IF_RFTH); + __uart_recv_by_it(hperh); + } + + /* Transmit */ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TFTH)) != RESET) { + ald_uart_clear_flag_status(hperh, UART_IF_TFTH); + __uart_send_by_it(hperh); + } + + /* End Transmit */ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TBC)) != RESET) { + ald_uart_clear_flag_status(hperh, UART_IF_TBC); + __uart_end_send_by_it(hperh); + } + + /* Receive frame timeout*/ + if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RXTO)) != RESET) { + ald_uart_clear_flag_status(hperh, UART_IF_RXTO); + + ald_uart_interrupt_config(hperh, UART_IT_RXTO, DISABLE); + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + /* Handle error state */ + if (hperh->err_code != UART_ERROR_NONE) { + hperh->state = UART_STATE_READY; + + if (hperh->error_cbk) + hperh->error_cbk(hperh); + } +} + +/** + * @brief This function handles UART interrupt request. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval None + */ +void ald_uart_irq_handler_fast(uart_handle_t *hperh) +{ + volatile uint32_t tmp = hperh->perh->IFM; + + /* Transmit */ + if (tmp & 0x8000) { + hperh->perh->ICR = 0x8000; + while(hperh->perh->STAT & (0x1 << 17)); + hperh->perh->TXBUF = *hperh->tx_buf++; + ++hperh->tx_count; + + if (hperh->tx_count >= hperh->tx_size) { + hperh->perh->IDR = 0x8000; + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + } + /* End Transmit */ + if (tmp & 0x10000) { + hperh->perh->ICR = 0x10000; + hperh->perh->IDR = 0x10000; + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + + if (hperh->tx_cplt_cbk) + hperh->tx_cplt_cbk(hperh); + } + + /* Receive*/ + if (tmp & 0x200) { + hperh->perh->ICR = 0x200; + *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF); + ++hperh->rx_count; + + if (hperh->rx_count >= hperh->rx_size) { + hperh->perh->IDR = 0x200; + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + } + /* Receive frame */ + if (tmp & 0x10) { + hperh->perh->ICR = 0x10; + hperh->perh->IDR = 0x10; + CLEAR_BIT(hperh->state, UART_STATE_RX_MASK); + + if (hperh->rx_cplt_cbk) + hperh->rx_cplt_cbk(hperh); + } + + return; +} +/** + * @} + */ + +/** @defgroup UART_Public_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * + * @verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART: + (+) ald_uart_interrupt_config() API can be helpful to configure UART interrupt source. + (+) ald_uart_dma_req_config() API can be helpful to configure UART DMA request. + (+) ald_uart_tx_fifo_config() API can be helpful to configure UART TX FIFO paramters. + (+) ald_uart_rx_fifo_config() API can be helpful to configure UART RX FIFO paramters. + (+) ald_uart_lin_send_break() API can send a frame of break in LIN mode. + (+) ald_uart_lin_detect_break_len_config() API can be helpful to configure the length of break frame. + (+) ald_uart_auto_baud_config() API can be helpful to configure detection data mode. + (+) ald_uart_get_it_status() API can get the status of interrupt source. + (+) ald_uart_get_status() API can get the status of UART_SR register. + (+) ald_uart_get_flag_status() API can get the status of UART flag. + (+) ald_uart_get_mask_flag_status() API can get status os flag and interrupt source. + (+) ald_uart_clear_flag_status() API can clear UART flag. + + @endverbatim + * @{ + */ + +/** + * @brief Enable/disable the specified UART interrupts. + * @param hperh: Pointer to a uart_handle_t structure. + * @param it: Specifies the UART interrupt sources to be enabled or disabled. + * This parameter can be one of the @ref uart_it_t. + * @param state: New state of the specified UART interrupts. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IT(it)); + assert_param(IS_FUNC_STATE(state)); + + if (state == ENABLE) + hperh->perh->IER = it; + else + hperh->perh->IDR = it; + + return; +} + +/** + * @brief Configure UART DMA request. + * @param hperh: Pointer to a uart_handle_t structure. + * @param req: The type of DMA request. + * @param state: New state of the specified DMA request. + * This parameter can be: + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_DMA_REQ(req)); + assert_param(IS_FUNC_STATE(state)); + + if (req == UART_DMA_REQ_TX) { + if (state == ENABLE) + SET_BIT(hperh->perh->MCON, UART_MCON_TXDMAEN_MSK); + else + CLEAR_BIT(hperh->perh->MCON, UART_MCON_TXDMAEN_MSK); + } + else { + if (state == ENABLE) + SET_BIT(hperh->perh->MCON, UART_MCON_RXDMAEN_MSK); + else + CLEAR_BIT(hperh->perh->MCON, UART_MCON_RXDMAEN_MSK); + } + + return; +} + +/** + * @brief Configure transmit fifo parameters. + * @param hperh: Pointer to a uart_handle_t structure. + * @param config: Transmit fifo trigger level. + * @retval None + */ +void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_TXFIFO_TYPE(config)); + + SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK); + MODIFY_REG(hperh->perh->FCON, UART_FCON_TXTH_MSK, config << UART_FCON_TXTH_POSS); + + return; +} + +/** + * @brief Configure receive fifo parameters. + * @param hperh: Pointer to a uart_handle_t structure. + * @param config: Receive fifo trigger level. + * @retval None + */ +void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_RXFIFO_TYPE(config)); + + SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK); + MODIFY_REG(hperh->perh->FCON, UART_FCON_RXTH_MSK, config << UART_FCON_RXTH_POSS); + + return; +} + +/** + * @brief Enable/Disable break signal detect interrup. + * @param hperh: Pointer to a uart_handle_t structure. + * @param status: The new status. + * @retval None + */ +void uart_lin_break_detect_irq(uart_handle_t *hperh, type_func_t status) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if (status == ENABLE) { + SET_BIT(hperh->perh->IER, UART_IER_LINBK_MSK); + } + else { + CLEAR_BIT(hperh->perh->IER, UART_IER_LINBK_MSK); + } + + return; +} + +/** + * @brief request to send a frame of break. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval None + */ +void ald_uart_lin_send_break(uart_handle_t *hperh) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + SET_BIT(hperh->perh->LIN, UART_LIN_LINBKREQ_MSK); + while(hperh->perh->STAT & (0x1 << 17)); + hperh->perh->TXBUF = (0x55); + + return; +} + +/** + * @brief Configure the length of break frame to be detect. + * @param hperh: Pointer to a uart_handle_t structure. + * @param len: Length of break frame. + * @arg LIN_BREAK_LEN_10B + * @arg LIN_BREAK_LEN_11B + * @retval None + */ +void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_LIN_BREAK_LEN(len)); + + MODIFY_REG(hperh->perh->LIN, UART_LIN_LINBDL_MSK, len << UART_LIN_LINBDL_POS); + + return; +} + +/** + * @brief Configure the mode of auto-baud-rate detect. + * @param hperh: Pointer to a uart_handle_t structure. + * @param mode: The mode of auto-baud-rate detect. + * @arg UART_ABRMOD_1_TO_0 + * @arg UART_ABRMOD_1 + * @arg UART_ABRMOD_0_TO_1 + * @retval None + */ +void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_AUTO_BAUD_MODE(mode)); + + MODIFY_REG(hperh->perh->MCON, UART_MCON_ABRMOD_MSK, mode << UART_MCON_ABRMOD_POSS); + + return; +} + +/** + * @brief Send address in RS485 mode. + * @param hperh: Pointer to a uart_handle_t structure that contains + * the configuration information for the specified UART module. + * @param addr: the address of RS485 device. + * @param timeout: Timeout duration + * @retval The ALD status. + */ +ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout) +{ + assert_param(IS_UART_ALL(hperh->perh)); + + if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX)) + return BUSY; + + SET_BIT(hperh->state, UART_STATE_TX_MASK); + + if (uart_wait_flag(hperh, UART_STATUS_TFEMPTY, SET, timeout) != OK) { + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + while(hperh->perh->STAT & (0x1 << 17)); + WRITE_REG(hperh->perh->TXBUF, (addr | 0x100)); + + if (uart_wait_flag(hperh, UART_STATUS_TFEMPTY, SET, timeout) != OK) { + hperh->state = UART_STATE_READY; + return TIMEOUT; + } + + CLEAR_BIT(hperh->state, UART_STATE_TX_MASK); + + return OK; +} + +/** + * @brief Get the status of UART interrupt source. + * @param hperh: Pointer to a uart_handle_t structure. + * @param it: Specifies the UART interrupt source. + * This parameter can be one of the @ref uart_it_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it) +{ + it_status_t status = RESET; + + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IT(it)); + + if (hperh->perh->IVS & it) + status = SET; + + return status; +} + +/** + * @brief Get the status of UART_SR register. + * @param hperh: Pointer to a uart_handle_t structure. + * @param status: Specifies the UART status type. + * This parameter can be one of the @ref uart_status_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_STATUS(status)); + + if (hperh->perh->STAT & status) + return SET; + + return RESET; +} + + +/** + * @brief Get the status of UART interrupt flag. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the UART interrupt flag. + * This parameter can be one of the @ref uart_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); + + if (hperh->perh->RIF & flag) + return SET; + + return RESET; +} + +/** + * @brief Get the status of interrupt flag and interupt source. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the UART interrupt flag. + * This parameter can be one of the @ref uart_flag_t. + * @retval Status: + * - 0: RESET + * - 1: SET + */ +flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); + + if (hperh->perh->IFM & flag) + return SET; + + return RESET; +} + +/** + * @brief Clear the UART interrupt flag. + * @param hperh: Pointer to a uart_handle_t structure. + * @param flag: Specifies the UART interrupt flag. + * This parameter can be one of the @ref uart_flag_t. + * @retval None + */ +void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag) +{ + assert_param(IS_UART_ALL(hperh->perh)); + assert_param(IS_UART_IF(flag)); + + hperh->perh->ICR = flag; + return; +} +/** + * @} + */ + +/** @defgroup UART_Public_Functions_Group4 Peripheral State and Errors functions + * @brief UART State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + UART communication process, return Peripheral Errors occurred during communication + process + (+) ald_uart_get_state() API can be helpful to check in run-time the state of the UART peripheral. + (+) ald_uart_get_error() check in run-time errors that could be occurred during communication. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the UART state. + * @param hperh: Pointer to a uart_handle_t structure. + * @retval ALD state + */ +uart_state_t ald_uart_get_state(uart_handle_t *hperh) +{ + return hperh->state; +} + +/** + * @brief Return the UART error code + * @param hperh: Pointer to a uart_handle_t structure. + * @retval UART Error Code + */ +uint32_t ald_uart_get_error(uart_handle_t *hperh) +{ + return hperh->err_code; +} + +/** + * @} + */ +/** + * @} + */ +#endif /* ALD_UART */ +/** + * @} + */ +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_usb.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_usb.c new file mode 100644 index 00000000..01579330 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_usb.c @@ -0,0 +1,1402 @@ +/** + ********************************************************************************* + * + * @file ald_usb.c + * @brief USB module driver. + * + * @version V1.0 + * @date 25 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 25 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "ald_conf.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup USB USB + * @brief USB module driver + * @{ + */ +#ifdef ALD_USB +/** + * @defgroup USB_Public_Functions USB Public Function + * @{ + */ +/** @defgroup USB_Public_Functions_Group1 Base functions + * @brief Base functions + * @{ + */ + +/** + * @brief Gets the number of current frame. + * @retval Number of the frame. + */ +uint32_t ald_usb_frame_number_get(void) +{ + return USB0->FRAME; +} + +/** + * @brief Request the session. + * @param start: true/false. + * @retval None + */ +void ald_usb_otg_session_request(bool start) +{ + if (start) + USB0->DEVCTL |= USB_DEVCTL_SESSION; + else + USB0->DEVCTL &= ~(USB_DEVCTL_SESSION); +} + +/** + * @brief Gets the mode. + * @retval Mode + */ +uint32_t ald_usb_mode_get(void) +{ + return USB0->DEVCTL & (USB_DEVCTL_DEV | USB_DEVCTL_HOST + | USB_DEVCTL_SESSION | USB_DEVCTL_VBUS_M); +} + +/** + * @brief Enable/Disable the high mode. + * @param enable: ENABLE/DISABLE. + * @retval None + */ +void ald_usb_high_speed_enable(bool enable) +{ + if (enable) + USB0->POWER |= USB_POWER_HS_EN; + else + USB0->POWER &= ~(USB_POWER_HS_EN); +} + +/** + * @brief Gets the speed of the device. + * @retval Type of the speed. + */ +uint32_t ald_usb_device_speed_get(void) +{ + if (USB0->POWER & USB_POWER_HS_EN) + return USB_HIGH_SPEED; + + return USB_FULL_SPEED; +} + +/** + * @brief Gets the number of the endpoint. + * @retval Number of the endpoint. + */ +uint32_t ald_usb_num_ep_get( void) +{ + return NUM_USB_EP; +} + +/** + * @brief Reset USB Control. + * @retval None + */ +void ald_usb_control_reset(void) +{ + ald_rmu_reset_periperal(RMU_PERH_USB); +} + +/** + * @brief Output USB clock via PA15, 60MHz/256=234.375KHz. + * @retval None + */ +void ald_usb_clock_output(void) +{ + SYSCFG_UNLOCK(); + SYSCFG->TESTKEY = 0x5A962814; + SYSCFG->TESTKEY = 0xE7CB69A5; + SYSCFG->USBTEST = 0x43; + + return; +} + +/** + * @brief Starts eye diagram for high-speed host. + * @param buf: Buffer for eye diagram. + * @param len: Length of the buffer. + * @retval Status, 0 means success, other values means failure. + */ +int ald_usb_eye_diagram_start(uint8_t *buf, uint16_t len) +{ + if (len < 53) + return -1; + + ald_usb_ep_data_put(0, buf, 53); + USB0->TEST = 0x08 | 0x90; + ald_delay_ms(20); + USB0->CSR0L = USB_CSRL0_TXRDY; + + return 0; +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group2 Device functions + * @brief Device functions + * @{ + */ + +/** + * @brief Gets the address. + * @retval Address. + */ +uint8_t ald_usb_dev_get_addr(void) +{ + return USB0->FADDR; +} + +/** + * @brief Sets the address. + * @param addr: The address which will be set. + * @retval None + */ +void ald_usb_dev_set_addr(uint8_t addr) +{ + USB0->FADDR = addr; +} + +/** + * @brief Enable connection. + * @retval None + */ +void ald_usb_dev_connect(void) +{ + USB0->POWER |= USB_POWER_SOFTCONN; +} + +/** + * @brief Disable connection. + * @retval None + */ +void ald_usb_dev_disconnect(void) +{ + USB0->POWER &= ~(USB_POWER_SOFTCONN); +} + +/** + * @brief Configure the endpoint in device mode. + * @param ep_idx: Index of the endpoint + * @param p_max: Size of the maximum package. + * @param flags: Flags of the endpoint. + * @retval None + */ +void ald_usb_dev_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t flags) +{ + uint32_t tmp = 0; + + if (flags & USB_EP_DEV_IN) { + USB0->CSR[ep_idx - 1].TXxMAXP = p_max; + if (flags & USB_EP_AUTO_SET) + tmp |= USB_TXCSRH1_AUTOSET; + if ((flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + tmp |= USB_TXCSRH1_ISO; + + USB0->CSR[ep_idx - 1].TXxCSRH = (uint8_t)tmp; + USB0->CSR[ep_idx - 1].TXxCSRL = USB_TXCSRL1_CLRDT; + } + else { + USB0->CSR[ep_idx - 1].RXxMAXP = p_max; + if (flags & USB_EP_AUTO_CLEAR) + tmp = USB_RXCSRH1_AUTOCL; + if (flags & USB_EP_DIS_NYET) + tmp |= USB_RXCSRH1_DISNYET; + + if ((flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + tmp |= USB_RXCSRH1_ISO; + + USB0->CSR[ep_idx - 1].RXxCSRH = (uint8_t)tmp; + USB0->CSR[ep_idx - 1].RXxCSRL = USB_RXCSRL1_CLRDT; + } +} + +/** + * @brief Gets the parameters of the endpoint. + * @param ep_idx: Index of the endpoint + * @param p_max: Size of the maximum package. + * @param flags: Flags of the endpoint. + * @retval None + */ +void ald_usb_dev_ep_get_config(uint32_t ep_idx, uint32_t *p_max, uint32_t *flags) +{ + uint32_t tmp; + + if (*flags & USB_EP_DEV_IN) { + *flags = USB_EP_DEV_IN; + *p_max = (uint32_t)USB0->CSR[ep_idx - 1].TXxMAXP; + tmp = (uint32_t)USB0->CSR[ep_idx - 1].TXxCSRH; + + if (tmp & USB_TXCSRH1_AUTOSET) + *flags |= USB_EP_AUTO_SET; + if (tmp & USB_TXCSRH1_ISO) + *flags |= USB_EP_MODE_ISOC; + else + *flags |= USB_EP_MODE_BULK; + } + else { + *flags = USB_EP_DEV_OUT; + *p_max = (uint32_t)USB0->CSR[ep_idx - 1].RXxMAXP; + tmp = (uint32_t)USB0->CSR[ep_idx - 1].RXxCSRH; + + if (tmp & USB_RXCSRH1_AUTOCL) + *flags |= USB_EP_AUTO_CLEAR; + if (tmp & USB_RXCSRH1_ISO) + *flags |= USB_EP_MODE_ISOC; + else + *flags |= USB_EP_MODE_BULK; + } +} + +/** + * @brief Acknowledge the data from the host. + * @param ep_idx: Index of the endpoint + * @param last: true/false + * @retval None + */ +void ald_usb_dev_ep_data_ack(uint32_t ep_idx, bool last) +{ + if (ep_idx == USB_EP_0) + USB0->CSR0L = USB_CSRL0_RXRDYC | (last ? USB_CSRL0_DATAEND : 0); + else + USB0->CSR[ep_idx - 1].RXxCSRL &= ~(USB_RXCSRL1_RXRDY); +} + +/** + * @brief Stall the endpoint. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_dev_ep_stall(uint32_t ep_idx, uint32_t flags) +{ + if (ep_idx == USB_EP_0) + USB0->CSR0L |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC); + else if (flags == USB_EP_DEV_IN) + USB0->CSR[ep_idx - 1].TXxCSRL |= USB_TXCSRL1_STALL; + else + USB0->CSR[ep_idx - 1].RXxCSRL |= USB_RXCSRL1_STALL; +} + +/** + * @brief Cancel the stall status. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_dev_ep_stall_clear(uint32_t ep_idx, uint32_t flags) +{ + if (ep_idx == USB_EP_0) + USB0->CSR0L &= ~USB_CSRL0_STALLED; + else if (flags == USB_EP_DEV_IN) { + USB0->CSR[ep_idx - 1].TXxCSRL &= ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); + USB0->CSR[ep_idx - 1].TXxCSRL |= USB_TXCSRL1_CLRDT; + } + else { + USB0->CSR[ep_idx - 1].RXxCSRL &= ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + USB0->CSR[ep_idx - 1].RXxCSRL |= USB_RXCSRL1_CLRDT; + } +} + +/** + * @brief Clear the status of the endpoint. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_dev_ep_status_clear(uint32_t ep_idx, uint32_t flags) +{ + if (ep_idx == USB_EP_0) { + if (flags & USB_DEV_EP0_OUT_PKTRDY) + USB0->CSR0L |= USB_CSRL0_RXRDYC; + if (flags & USB_DEV_EP0_SETUP_END) + USB0->CSR0L |= USB_CSRL0_SETENDC; + if (flags & USB_DEV_EP0_SENT_STALL) + USB0->CSR0L &= ~(USB_DEV_EP0_SENT_STALL); + } + else { + USB0->CSR[ep_idx - 1].TXxCSRL &= ~(flags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN)); + USB0->CSR[ep_idx - 1].RXxCSRL &= ~((flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR + | USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT); + } +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group3 Host functions + * @brief Host functions + * @{ + */ +/** + * @brief Gets the device's address. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval Address + */ +uint32_t ald_usb_host_addr_get(uint32_t ep_idx, uint32_t flags) +{ + if (flags & USB_EP_HOST_OUT) + return USB0->ADDR[ep_idx].TXxFUNCADDR; + else + return USB0->ADDR[ep_idx].RXxFUNCADDR; +} + +/** + * @brief Sets the device's address. + * @param ep_idx: Index of the endpoint. + * @param addr: The device's address. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags) +{ + if (flags & USB_EP_HOST_OUT) + USB0->ADDR[ep_idx].TXxFUNCADDR = addr; + else + USB0->ADDR[ep_idx].RXxFUNCADDR = addr; +} + +/** + * @brief Configure the endpoint in host mode. + * @param ep_idx: Index of the endpoint. + * @param p_max: Size of the maximum package. + * @param nak_val: Value of the nack. + * @param t_ep: Target endpoint. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags) +{ + uint32_t tmp; + + if (ep_idx == USB_EP_0) { + USB0->NACK = nak_val; + + if (flags & USB_EP_SPEED_HIGH) + USB0->TYPE0 = USB_TYPE0_SPEED_HIGH; + else if (flags & USB_EP_SPEED_FULL) + USB0->TYPE0 = USB_TYPE0_SPEED_FULL; + else + USB0->TYPE0 = USB_TYPE0_SPEED_LOW; + } + else { + tmp = t_ep; + + if (flags & USB_EP_SPEED_HIGH) + tmp |= USB_TXTYPE1_SPEED_HIGH; + else if (flags & USB_EP_SPEED_FULL) + tmp |= USB_TXTYPE1_SPEED_FULL; + else + tmp |= USB_TXTYPE1_SPEED_LOW; + + switch (flags & USB_EP_MODE_MASK) { + case USB_EP_MODE_BULK: + tmp |= USB_TXTYPE1_PROTO_BULK; + break; + + case USB_EP_MODE_ISOC: + tmp |= USB_TXTYPE1_PROTO_ISOC; + break; + + case USB_EP_MODE_INT: + tmp |= USB_TXTYPE1_PROTO_INT; + break; + + case USB_EP_MODE_CTRL: + tmp |= USB_TXTYPE1_PROTO_CTRL; + break; + } + + if (flags & USB_EP_HOST_OUT) { + USB0->CSR[ep_idx - 1].TXxTYPE = tmp; + USB0->CSR[ep_idx - 1].TXxINTERVAL = nak_val; + USB0->CSR[ep_idx - 1].TXxMAXP = p_max; + + tmp = 0; + if (flags & USB_EP_AUTO_SET) + tmp |= USB_TXCSRH1_AUTOSET; + USB0->CSR[ep_idx - 1].TXxCSRH = (uint8_t)tmp; + } + else { + USB0->CSR[ep_idx - 1].RXxTYPE = tmp; + USB0->CSR[ep_idx - 1].RXxINTERVAL = nak_val; + USB0->CSR[ep_idx - 1].RXxMAXP = p_max; + + tmp = 0; + if (flags & USB_EP_AUTO_CLEAR) + tmp |= USB_RXCSRH1_AUTOCL; + if (flags & USB_EP_AUTO_REQUEST) + tmp |= USB_RXCSRH1_AUTORQ; + + USB0->CSR[ep_idx - 1].RXxCSRH = (uint8_t)tmp; + } + } +} + +/** + * @brief Acknowledge the data in host mode. + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_ep_data_ack(uint32_t ep_idx) +{ + if (ep_idx == USB_EP_0) + USB0->CSR0L &= ~(USB_CSRL0_RXRDY); + else + USB0->CSR[ep_idx - 1].RXxCSRL &= ~(USB_RXCSRL1_RXRDY); +} + +/** + * @brief Toggle the data in host mode. + * @param ep_idx: Index of the endpoint. + * @param toggle: true/false. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_ep_data_toggle(uint32_t ep_idx, bool toggle, uint32_t flags) +{ + uint32_t tmp = 0; + + if (toggle) { + if (ep_idx == USB_EP_0) + tmp = USB_CSRH0_DT; + else if (flags == USB_EP_HOST_IN) + tmp = USB_RXCSRH1_DT; + else + tmp = USB_TXCSRH1_DT; + } + + if (ep_idx == USB_EP_0) { + USB0->CSR0H = (uint8_t)((USB0->CSR0H & ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) | + (tmp | USB_CSRH0_DTWE)); + } + else if (flags == USB_EP_HOST_IN) { + USB0->CSR[ep_idx - 1].RXxCSRH = (uint8_t)((USB0->CSR[ep_idx - 1].RXxCSRH & + ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) | + (tmp | USB_RXCSRH1_DTWE)); + } + else { + USB0->CSR[ep_idx - 1].TXxCSRH = (uint8_t)((USB0->CSR[ep_idx - 1].TXxCSRH & + ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) | + (tmp | USB_TXCSRH1_DTWE)); + } +} + +/** + * @brief Clear the status of endpoint in host mode. + * @param ep_idx: Index of the endpoint. + * @param flags: Flags. + * @retval None + */ +void ald_usb_host_ep_status_clear(uint32_t ep_idx, uint32_t flags) +{ + if (ep_idx == USB_EP_0) { + USB0->CSR0L &= ~flags; + } + else { + USB0->CSR[ep_idx - 1].TXxCSRL &= ~flags; + USB0->CSR[ep_idx - 1].RXxCSRL &= ~flags; + } +} + +/** + * @brief Gets the HUB's address. + * @param ep_idx: Index of the endpoint. + * @param flags: Flags. + * @retval Address + */ +uint32_t ald_usb_host_hub_addr_get(uint32_t ep_idx, uint32_t flags) +{ + if (flags & USB_EP_HOST_OUT) + return USB0->ADDR[ep_idx].TXxHUBADDR; + else + return USB0->ADDR[ep_idx].RXxHUBADDR; +} + +/** + * @brief Sets the HUB's address. + * @param ep_idx: Index of the endpoint. + * @param addr: HUB's address which will be set. + * @param flags: Flags. + * @retval Address + */ +void ald_usb_host_hub_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags) +{ + if (flags & USB_EP_HOST_OUT) + USB0->ADDR[ep_idx].TXxHUBADDR = addr; + else + USB0->ADDR[ep_idx].RXxHUBADDR = addr; + + if (ep_idx == USB_EP_0) { + if (flags & USB_EP_SPEED_FULL) + USB0->TYPE0 |= USB_TYPE0_SPEED_FULL; + else if (flags & USB_EP_SPEED_HIGH) + USB0->TYPE0 |= USB_TYPE0_SPEED_HIGH; + else + USB0->TYPE0 |= USB_TYPE0_SPEED_LOW; + } +} + +/** + * @brief Disable power. + * @retval None + */ +void ald_usb_host_pwr_disable(void) +{ + return; +} + +/** + * @brief Enable power. + * @retval None + */ +void ald_usb_host_pwr_enable(void) +{ + return; +} + +/** + * @brief Configure power in host mode. + * @param flags: Flags + * @retval None + */ +void ald_usb_host_pwr_config(uint32_t flags) +{ + return; +} + +/** + * @brief Disable the fault parameters of the power. + * @retval None + */ +void ald_usb_host_pwr_fault_disable(void) +{ + return; +} + +/** + * @brief Enable the fault parameters of the power. + * @retval None + */ +void ald_usb_host_pwr_fault_enable(void) +{ + return; +} + +/** + * @brief Request data IN(from device to host) + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_request_in(uint32_t ep_idx) +{ + if (ep_idx == USB_EP_0) + USB0->CSR0L = USB_RXCSRL1_REQPKT; + else + USB0->CSR[ep_idx - 1].RXxCSRL = USB_RXCSRL1_REQPKT; +} + +/** + * @brief Clear the status of request IN. + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_request_in_clear(uint32_t ep_idx) +{ + if (ep_idx == USB_EP_0) + USB0->CSR0L &= ~(USB_RXCSRL1_REQPKT); + else + USB0->CSR[ep_idx - 1].RXxCSRL &= ~(USB_RXCSRL1_REQPKT); +} + +/** + * @brief Request data IN at endpoint 0. + * @retval None + */ +void ald_usb_host_request_status(void) +{ + USB0->CSR0L = USB_CSRL0_REQPKT | USB_CSRL0_STATUS; +} + +/** + * @brief Reset the USB's bus. + * @param start: true/false. + * @retval None + */ +void ald_usb_host_reset(bool start) +{ + if (start) + USB0->POWER |= USB_POWER_RESET; + else + USB0->POWER &= ~(USB_POWER_RESET); +} + +/** + * @brief Resume the devices. + * @param start: true/false. + * @retval None + */ +void ald_usb_host_resume(bool start) +{ + if (start) + USB0->POWER |= USB_POWER_RESUME; + else + USB0->POWER &= ~(USB_POWER_RESUME); +} + +/** + * @brief Suspend the devices. + * @retval None + */ +void ald_usb_host_suspend(void) +{ + USB0->POWER |= USB_POWER_SUSPEND; +} + +/** + * @brief Gets the device's speed. + * @retval Type of the speed. + */ +uint32_t ald_usb_host_speed_get(void) +{ + if (USB0->POWER & USB_POWER_HS_M) + return USB_HIGH_SPEED; + + if (USB0->DEVCTL & USB_DEVCTL_FSDEV) + return USB_FULL_SPEED; + + if (USB0->DEVCTL & USB_DEVCTL_LSDEV) + return USB_LOW_SPEED; + + return USB_UNDEF_SPEED; +} + +/** + * @brief Sets the endpoint speed. + * @param ep_idx: Index of the endpoint. + * @param flags: Type of the speed. + * @retval None + */ +void ald_usb_host_ep_speed_set(uint32_t ep_idx, uint32_t flags) +{ + uint32_t tmp; + + if (flags & USB_EP_SPEED_HIGH) + tmp = USB_TYPE0_SPEED_HIGH; + else if (flags & USB_EP_SPEED_FULL) + tmp = USB_TYPE0_SPEED_FULL; + else + tmp = USB_TYPE0_SPEED_LOW; + + if (ep_idx == USB_EP_0) + USB0->TYPE0 |= tmp; + else if (flags & USB_EP_HOST_OUT) + USB0->CSR[ep_idx - 1].TXxTYPE |= tmp; + else + USB0->CSR[ep_idx - 1].RXxTYPE |= tmp; +} + +/** + * @brief Ping the endpoint. + * @param ep_idx: Index of the endpoint. + * @param enable: ENABLE/DISABLE. + * @retval None + */ +void ald_usb_host_ep_ping(uint32_t ep_idx, bool enable) +{ + if (enable) + USB0->CSR0H &= ~(USB_CSRH0_DISPING); + else + USB0->CSR0H |= USB_CSRH0_DISPING; +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group4 Endpoint functions + * @brief Endpoint functions + * @{ + */ +/** + * @brief Gets the size of the available data. + * @param ep_idx: Index of the endpoint + * @retval Size in bytes. + */ +uint32_t ald_usb_ep_data_avail(uint32_t ep_idx) +{ + if (ep_idx == USB_EP_0) { + if ((USB0->CSR0L & USB_CSRL0_RXRDY) == 0) + return 0; + + return USB0->COUNT0; + } + else { + if ((USB0->CSR[ep_idx - 1].RXxCSRL & USB_CSRL0_RXRDY) == 0) + return 0; + + return USB0->CSR[ep_idx - 1].RXxCOUNT; + } +} + +/** + * @brief Gets the data from FIFO. + * @param ep_idx: Index of the endpoint + * @param data: Pointer to the buffer. + * @param size: Size of the data. + * @retval Status. + */ +int32_t ald_usb_ep_data_get(uint32_t ep_idx, uint8_t *data, uint32_t *size) +{ + uint32_t i; + + if (ep_idx == USB_EP_0) { + if ((USB0->CSR0L & USB_CSRL0_RXRDY) == 0) { + *size = 0; + return -1; + } + i = USB0->COUNT0; + } + else { + if ((USB0->CSR[ep_idx - 1].RXxCSRL & USB_CSRL0_RXRDY) == 0) { + *size = 0; + return -1; + } + i = USB0->CSR[ep_idx - 1].RXxCOUNT; + } + + i = (i < *size) ? i : *size; + *size = i; + + for (; i > 0; i--) + *data++ = USB0->FIFO[ep_idx].Byte[0]; + + return 0; +} + +/** + * @brief Puts data to the FIFO. + * @param ep_idx: Index of the endpoint + * @param data: Pointer to the data. + * @param size: Size of the data. + * @retval Status. + */ +int32_t ald_usb_ep_data_put(uint32_t ep_idx, uint8_t *data, uint32_t size) +{ + if (ep_idx == USB_EP_0) { + if (USB0->CSR0L & USB_CSRL0_TXRDY) + return -1; + } + else { + if (USB0->CSR[ep_idx - 1].TXxCSRL & USB_TXCSRL1_TXRDY) + return -1; + } + + for (; size > 0; size--) + USB0->FIFO[ep_idx].Byte[0] = *data++; + + return 0; +} + +/** + * @brief Send data. + * @param ep_idx: Index of the endpoint + * @param tx_type: Type. + * @retval Status. + */ +int32_t ald_usb_ep_data_send(uint32_t ep_idx, uint32_t tx_type) +{ + uint32_t tmp; + + if (ep_idx == USB_EP_0) { + if (USB0->CSR0L & USB_CSRL0_TXRDY) + return -1; + + tmp = tx_type & 0xff; + USB0->CSR0L = tmp; + } + else { + if (USB0->CSR[ep_idx - 1].TXxCSRL & USB_TXCSRL1_TXRDY) + return -1; + + tmp = (tx_type >> 8) & 0xff; + USB0->CSR[ep_idx - 1].TXxCSRL = tmp; + } + + return 0; +} + +/** + * @brief Clear the status of the toggle. + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_ep_data_toggle_clear(uint32_t ep_idx, uint32_t flags) +{ + if (flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + USB0->CSR[ep_idx - 1].TXxCSRL |= USB_TXCSRL1_CLRDT; + else + USB0->CSR[ep_idx - 1].RXxCSRL |= USB_RXCSRL1_CLRDT; +} + +/** + * @brief Sets the size of request data IN + * @param ep_idx: Index of the endpoint + * @param count: Size of request data IN. + * @retval None + */ +void ald_usb_ep_req_packet_count(uint32_t ep_idx, uint32_t count) +{ + USB0->EP_RQPKTCOUNT[ep_idx - 1] = count; +} + +/** + * @brief Gets the status of the endpoint. + * @param ep_idx: Index of the endpoint + * @retval Status. + */ +uint32_t ald_usb_ep_status(uint32_t ep_idx) +{ + uint32_t status; + + if (ep_idx == USB_EP_0) { + status = USB0->CSR0L; + status |= (USB0->CSR0H) << USB_RX_EPSTATUS_SHIFT; + } + else { + status = USB0->CSR[ep_idx - 1].TXxCSRL; + status |= USB0->CSR[ep_idx - 1].TXxCSRH << 8; + status |= USB0->CSR[ep_idx - 1].RXxCSRL << 16; + status |= USB0->CSR[ep_idx - 1].RXxCSRH << 24; + } + + return status; +} + +/** + * @brief Configure the endpoint in DMA mode. + * @param ep_idx: Index of the endpoint + * @param flag: Flags. + * @param en: ENABLE/DISABLE. + * @retval None + */ +void ald_usb_ep_dma_config(uint32_t ep_idx, uint32_t flag, type_func_t en) +{ + if (ep_idx == USB_EP_0) + return; + + if (en) { + switch (flag) { + case USB_DMA_EP_CFG_TX: + USB0->CSR[ep_idx - 1].TXxCSRH |= USB_DMA_EP_TX_MSK; + break; + case USB_DMA_EP_CFG_RX_DEV: + USB0->CSR[ep_idx - 1].RXxCSRH |= USB_DMA_EP_RX_DEV_MSK; + break; + case USB_DMA_EP_CFG_RX_HOST: + USB0->CSR[ep_idx - 1].RXxCSRH |= USB_DMA_EP_RX_HOST_MSK; + break; + default: + break; + } + } + else { + switch (flag) { + case USB_DMA_EP_CFG_TX: + USB0->CSR[ep_idx - 1].TXxCSRH &= ~(USB_DMA_EP_TX_MSK); + break; + case USB_DMA_EP_CFG_RX_DEV: + USB0->CSR[ep_idx - 1].RXxCSRH &= ~(USB_DMA_EP_RX_DEV_MSK); + break; + case USB_DMA_EP_CFG_RX_HOST: + USB0->CSR[ep_idx - 1].RXxCSRH &= ~(USB_DMA_EP_RX_HOST_MSK); + break; + default: + break; + } + } + + return; +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group5 FIFO functions + * @brief FIFO functions + * @{ + */ +/** + * @brief Gets the address of the FIFO. + * @param ep_idx: Index of the endpoint + * @retval Address + */ +uint32_t ald_usb_fifo_addr_get(uint32_t ep_idx) +{ + return (uint32_t)&USB0->FIFO[ep_idx].Word; +} + +/** + * @brief Gets the parameters of the FIFO. + * @param ep_idx: Index of the endpoint + * @param addr: Address. + * @param size: Size of FIFO. + * @param flags: Flags. + * @retval None + */ +void ald_usb_fifo_config_get(uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags) +{ + uint32_t tmp = USB0->INDEX; + + USB0->INDEX = ep_idx; + + if (flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) { + *addr = (USB0->TXFIFOADD << 3); + *size = (USB0->TXFIFOSIZE & 0xF); + } + else { + *addr = (USB0->RXFIFOADD << 3); + *size = (USB0->RXFIFOSIZE & 0xF); + } + + USB0->INDEX = tmp; + return; +} + +/** + * @brief Sets the parameters of the FIFO. + * @param ep_idx: Index of the endpoint + * @param addr: Address. + * @param size: Size of FIFO. + * @param flags: Flags. + * @retval None + */ +void ald_usb_fifo_config_set(uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags) +{ + uint32_t tmp = USB0->INDEX; + + USB0->INDEX = ep_idx; + + if (flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) { + USB0->TXFIFOADD = (addr >> 3); + USB0->TXFIFOSIZE = (size & 0xF); + } + else { + USB0->RXFIFOADD = (addr >> 3); + USB0->RXFIFOSIZE = (size & 0xF); + } + + USB0->INDEX = tmp; + return; +} + +/** + * @brief Flush the FIFO + * @param ep_idx: Index of the endpoint + * @param flags: Flags. + * @retval None + */ +void ald_usb_fifo_flush(uint32_t ep_idx, uint32_t flags) +{ + if (ep_idx == USB_EP_0) { + if ((USB0->CSR0L & (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0) + USB0->CSR0H |= USB_CSRH0_FLUSH; + } + else { + if (flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) { + if (USB0->CSR[ep_idx - 1].TXxCSRL & USB_TXCSRL1_TXRDY) + USB0->CSR[ep_idx - 1].TXxCSRL |= USB_TXCSRL1_FLUSH; + } + else { + if (USB0->CSR[ep_idx - 1].RXxCSRL & USB_RXCSRL1_RXRDY) + USB0->CSR[ep_idx - 1].RXxCSRL |= USB_RXCSRL1_FLUSH; + } + } +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group6 Interrupt functions + * @brief Interrupt functions + * @{ + */ +/** + * @brief Disable interrupt. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_disable(uint32_t flags) +{ + if (flags & USB_INTCTRL_STATUS) + USB0->USBIE &= ~(flags & USB_INTCTRL_STATUS); +} + +/** + * @brief Enable interrupt. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_enable(uint32_t flags) +{ + if (flags & USB_INTCTRL_STATUS) + USB0->USBIE |= flags ; +} + +/** + * @brief Gets the status of the interrupt. + * @retval Status. + */ +uint32_t ald_usb_int_status_get(void) +{ + return USB0->USBIS; +} + +/** + * @brief Disable interrupt of the endpoint. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_disable_ep(uint32_t flags) +{ + USB0->TXIE &= ~(flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); + USB0->RXIE &= ~((flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> USB_INTEP_RX_SHIFT); +} + +/** + * @brief Enable interrupt of the endpoint. + * @param flags: Type of the interrupt. + * @retval None + */ +void ald_usb_int_enable_ep(uint32_t flags) +{ + + USB0->TXIE |= flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0); + USB0->RXIE |= ((flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> USB_INTEP_RX_SHIFT); +} + +/** + * @brief Gets the ststus of the endpoint interrupt. + * @retval Status. + */ +uint32_t ald_usb_int_status_ep_get(void) +{ + uint32_t status; + + status = USB0->TXIS; + status |= (USB0->RXIS << USB_INTEP_RX_SHIFT); + + return status; +} + +/** + * @brief Register USB's interrupt. + * @retval None + */ +void ald_usb_int_register(void) +{ + ald_mcu_irq_config(USB_INT_IRQn, 2, 2, ENABLE); + +} + +/** + * @brief Unregister USB's interrupt. + * @retval None + */ +void ald_usb_int_unregister(void) +{ + ald_mcu_irq_config(USB_INT_IRQn, 2, 2, DISABLE); +} + +/** + * @brief Get USB's interrupt number. + * @retval None + */ +uint32_t ald_usb_int_num_get(void) +{ + return USB_INT_IRQn; +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group7 DMA functions + * @brief DMA functions + * @{ + */ +/** + * @brief Configure DMA's channel. + * @param ch: Channel. + * @param addr: Address. + * @param count: Size of the data to be moved. + * @param ctrl: Parameters of the DMA's controler + * @retval None + */ +void ald_usb_dma_channel_config(uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl) +{ + USB0->DMA_CH[ch].DMA_ADDR = addr; + USB0->DMA_CH[ch].DMA_COUNT = count; + USB0->DMA_CH[ch].DMA_CNTL = ctrl; + return; +} + +/** + * @brief Start multiple receive. + * @param ep_idx: Index of the endpoint + * @retval None + */ +void ald_usb_dma_mult_recv_start(uint32_t ep_idx) +{ + USB0->CSR[ep_idx - 1].RXxCSRH &= ~(USB_RXCSRH1_DMAMOD); + return; +} + + +/** + * @brief Start DMA's machine. + * @param ch: Channel. + * @retval None + */ +void ald_usb_dma_channel_start(uint8_t ch) +{ + USB0->DMA_CH[ch].DMA_CNTL |= 0x1; + return; +} + +/** + * @brief Stop DMA's machine. + * @param ch: Channel. + * @retval None + */ +void ald_usb_dma_channel_stop(uint8_t ch) +{ + USB0->DMA_CH[ch].DMA_CNTL &= (uint32_t)(~0x1); + return; +} + +/** + * @brief Gets flags of the interrupt. + * @retval Flags of the interrupt. + */ +uint32_t ald_usb_dma_get_interrupt_flag(void) +{ + return USB0->DMA_INTR; +} + +/** + * @brief Gets the status of the error. + * @param ch: Channel. + * @retval Status. + */ +uint32_t ald_usb_dma_get_channel_error(uint8_t ch) +{ + if (USB0->DMA_CH[ch].DMA_CNTL & USB_DMA_CH_ERR_MSK) + return 1; + + return 0; +} + +/** + * @brief Clear the status of the error. + * @param ch: Channel. + * @retval None + */ +void ald_usb_dma_clear_channel_error(uint8_t ch) +{ + USB0->DMA_CH[ch].DMA_CNTL &= ~(USB_DMA_CH_ERR_MSK); +} +/** + * @} + */ + +/** @defgroup USB_Public_Functions_Group8 LPM functions + * @brief LPM functions + * @{ + */ +/** + * @brief Transmit a LPM transaction in host mode. + * @param addr: Address. + * @param ep_idx: Index of the endpoint. + * @retval None + */ +void ald_usb_host_lpm_send(uint32_t addr, uint32_t ep_idx) +{ + uint32_t tmp; + + USB0->LPM_FADDR = addr; + + tmp = USB0->LPM_ATTR & ~(USB_LPMATTR_ENDPT_M); + tmp |= ep_idx << USB_LPMATTR_ENDPT_S; + + USB0->LPM_ATTR = tmp; + USB0->LPM_CNTRL |= USB_LPMCNTRL_LPMXMT; +} + +/** + * @brief Configure the LPM parameters in host mode. + * @param resume_time: Resume time. + * @param config: Parameters + * @retval None + */ +void ald_usb_host_lpm_config(uint32_t resume_time, uint32_t config) +{ + uint32_t tmp; + + tmp = USB0->LPM_ATTR; + tmp &= ~(USB_LPMATTR_HIRD_M); + tmp |= ((((resume_time - 50) / 75) & 0xF) << USB_LPMATTR_HIRD_S); + tmp |= config; + USB0->LPM_ATTR = tmp; +} + +/** + * @brief Gets status of remote wakeup. + * @retval Status. + */ +uint32_t ald_usb_lpm_remote_wake_is_enable(void) +{ + if (USB0->LPM_ATTR & USB_LPMATTR_RMTWAK) + return 1; + + return 0; +} + +/** + * @brief Initiate a RESUME from the L1 state in host mode. + * @retval None + */ +void ald_usb_host_lpm_resume(void) +{ + USB0->LPM_CNTRL |= USB_LPMCNTRL_LPMRES; +} + +/** + * @brief Enable remote wakeup in device mode. + * @retval None + */ +void ald_usb_dev_lpm_remote_wake(void) +{ + USB0->LPM_CNTRL |= USB_LPMCNTRL_LPMRES; +} + +/** + * @brief Enable remote wakeup in device mode. + * @retval None + */ +void ald_usb_dev_lpm_config(uint32_t config) +{ + USB0->LPM_CNTRL = config; +} + +/** + * @brief Enable LPM in device mode. + * @retval None + */ +void ald_usb_dev_lpm_enable(void) +{ + USB0->LPM_CNTRL |= (USB_LPMCNTRL_LPMXMT | USB_LPMCNTRL_ENABLE); +} + +/** + * @brief Disable LPM in device mode. + * @retval None + */ +void ald_usb_dev_lpm_disable(void) +{ + USB0->LPM_CNTRL &= ~(USB_LPMCNTRL_LPMXMT); +} + +/** + * @brief Gets the link status + * @retval Status + */ +uint32_t ald_usb_lpm_link_status_get(void) +{ + return (USB0->LPM_ATTR & USB_LPMATTR_LS_M); +} + +/** + * @brief Gets the index of the endpoint. + * @retval Index of the endpoint. + */ +uint32_t ald_usb_lpm_ep_get(void) +{ + uint32_t tmp; + + tmp = USB0->LPM_ATTR; + tmp &= USB_LPMATTR_ENDPT_M; + tmp = tmp >> USB_LPMATTR_ENDPT_S; + + return tmp; +} + +/** + * @brief Gets the status of the interrupt. + * @retval Status. + */ +uint32_t ald_usb_lpm_int_status_get(void) +{ + return USB0->LPM_INTR; +} + +/** + * @brief Disable the LPM interrupt. + * @retval None + */ +void ald_usb_lpm_int_disable(uint32_t ints) +{ + USB0->LPM_INTREN &= ~ints; +} + +/** + * @brief Enable the LPM interrupt. + * @retval None + */ +void ald_usb_lpm_int_enable(uint32_t ints) +{ + USB0->LPM_INTREN |= ints; +} +/** + * @} + */ + +/** + * @} + */ +#endif +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_wdt.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_wdt.c new file mode 100644 index 00000000..8bf1bc2c --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/ald_wdt.c @@ -0,0 +1,238 @@ +/** + ********************************************************************************* + * + * @file ald_wdt.c + * @brief WDT module driver. + * + * @version V1.0 + * @date 18 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 18 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ +#include "ald_conf.h" + +/** @addtogroup ES32FXXX_ALD + * @{ + */ + +/** @defgroup WDT WDT + * @brief WDT module driver + * @{ + */ +#ifdef ALD_WDT + + +/** @defgroup WWDT_Public_Functions WWDT Public Functions + * @brief Init and configure WWDT function + * @{ + */ +/** + * @brief Initializes the WWDT according to the specified parameters. + * @param load: Specifies the free-running downcounter value. + * @param win: specifics the no dog windows, + * the parameter can be one of the following values: + * @arg @ref WWDT_WIN_25 No dog window size: 25% + * @arg @ref WWDT_WIN_50 No dog window size: 50% + * @arg @ref WWDT_WIN_75 No dog window size: 75% + * @arg @ref WWDT_WIN_00 No dog window size: 0% + * @param interrupt: Enable or disable interrupt. + * @retval None + */ +void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt) +{ + assert_param(IS_WWDT_WIN_TYPE(win)); + assert_param(IS_FUNC_STATE(interrupt)); + + WWDT_UNLOCK(); + WRITE_REG(WWDT->LOAD, load); + MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, win << WWDT_CON_WWDTWIN_POSS); + SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK); + SET_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK); + MODIFY_REG(WWDT->CON, WWDT_CON_IE_MSK, interrupt << WWDT_CON_IE_POS); + WWDT_LOCK(); + + return; +} + +/** + * @brief Start the WWDT + * @retval None + */ +void ald_wwdt_start(void) +{ + WWDT_UNLOCK(); + SET_BIT(WWDT->CON, WWDT_CON_EN_MSK); + WWDT_LOCK(); + + return; +} + +/** + * @brief Get the free-running downcounter value + * @retval Value + */ +uint32_t ald_wwdt_get_value(void) +{ + return WWDT->VALUE; +} + +/** + * @brief Get interrupt state + * @retval Value + */ +it_status_t ald_wwdt_get_flag_status(void) +{ + if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK)) + return SET; + + return RESET; +} + +/** + * @brief Clear interrupt state + * @retval None + */ +void ald_wwdt_clear_flag_status(void) +{ + WRITE_REG(WWDT->INTCLR, 1); + return; +} + +/** + * @brief Refreshes the WWDT + * @retval None + */ +void ald_wwdt_feed_dog(void) +{ + uint16_t i = 0; + + WWDT_UNLOCK(); + WRITE_REG(WWDT->INTCLR, 0x1); + WWDT_LOCK(); + for (i = 0; i < 0x2ff; ++i) + __NOP(); + + return; +} +/** + * @} + */ + +/** @defgroup IWDT_Public_Functions IWDT Public Functions + * @brief Init and configure IWDT function + * @{ + */ +/** + * @brief Initializes the IWDG according to the specified parameters. + * @param load: Specifies the free-running downcounter value. + * @param interrupt: Enable or disable interrupt. + * @retval None + */ +void ald_iwdt_init(uint32_t load, type_func_t interrupt) +{ + assert_param(IS_FUNC_STATE(interrupt)); + + IWDT_UNLOCK(); + WRITE_REG(IWDT->LOAD, load); + SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK); + SET_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK); + MODIFY_REG(IWDT->CON, IWDT_CON_IE_MSK, interrupt << IWDT_CON_IE_POS); + IWDT_LOCK(); + + return; +} + +/** + * @brief Start the IWDT + * @retval None + */ +void ald_iwdt_start(void) +{ + IWDT_UNLOCK(); + SET_BIT(IWDT->CON, IWDT_CON_EN_MSK); + IWDT_LOCK(); + + return; +} + +/** + * @brief Get the free-running downcounter value + * @retval Value + */ +uint32_t ald_iwdt_get_value(void) +{ + return IWDT->VALUE; +} + +/** + * @brief Get interrupt state + * @retval Value + */ +it_status_t ald_iwdt_get_flag_status(void) +{ + if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK)) + return SET; + + return RESET; +} + +/** + * @brief Clear interrupt state + * @retval None + */ +void ald_iwdt_clear_flag_status(void) +{ + IWDT_UNLOCK(); + WRITE_REG(IWDT->INTCLR, 1); + IWDT_LOCK(); + return; +} + +/** + * @brief Refreshes the WWDT + * @retval None + */ +void ald_iwdt_feed_dog(void) +{ + uint16_t i = 0; + + IWDT_UNLOCK(); + WRITE_REG(IWDT->INTCLR, 1); + IWDT_LOCK(); + for (i = 0; i < 0x2ff; ++i) + __NOP(); + + return; +} +/** + * @} + */ + +#endif /* ALD_WDT */ +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/ALD/ES32F36xx/Source/utils.c b/demo/es32/Drivers/ALD/ES32F36xx/Source/utils.c new file mode 100644 index 00000000..474dc1c4 --- /dev/null +++ b/demo/es32/Drivers/ALD/ES32F36xx/Source/utils.c @@ -0,0 +1,715 @@ +/** + ********************************************************************************* + * + * @file utils.c + * @brief This file contains the Utilities functions/types for the driver. + * + * @version V1.1 + * @date 13 Apr 2021 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 07 Nov 2019 AE Team The first version + * 13 Apr 2021 AE Team Add API: sys_config() + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include +#include "ald_conf.h" + +/** @defgroup ES32FXXX_ALD EASTSOFT ES32F3xx ALD + * @brief Shanghai Eastsoft Microelectronics Cortex-M Chip Abstraction Layer Driver(ALD) + * @{ + */ + +/** @defgroup UTILS Utils + * @brief Utils module driver + * @{ + */ + +/** @defgroup ALD_Private_Constants Private Constants + * @brief ALD Private Constants + * @{ + */ + +/** + * @brief ALD version number + */ +#define __ALD_VERSION_MAIN (0x01) /**< [31:24] main version */ +#define __ALD_VERSION_SUB1 (0x00) /**< [23:16] sub1 version */ +#define __ALD_VERSION_SUB2 (0x00) /**< [15:8] sub2 version */ +#define __ALD_VERSION_RC (0x00) /**< [7:0] release candidate */ +#define __ALD_VERSION ((__ALD_VERSION_MAIN << 24) | \ + (__ALD_VERSION_SUB1 << 16) | \ + (__ALD_VERSION_SUB2 << 8 ) | \ + (__ALD_VERSION_RC)) +/** + * @} + */ + +/** @defgroup ALD_Private_Variables Private Variables + * @{ + */ +/** @brief lib_tick: Increase by one millisecond + */ +static __IO uint32_t lib_tick; +uint32_t __systick_interval = SYSTICK_INTERVAL_1MS; +/** + * @} + */ + + +/** @defgroup ALD_Public_Functions Public Functions + * @{ + */ + +/** @defgroup ALD_Public_Functions_Group1 Initialization Function + * @brief Initialization functions + * + * @verbatim + =============================================================================== + ##### Initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes interface, the NVIC allocation and initial clock + configuration. It initializes the source of time base also when timeout + is needed and the backup domain when enabled. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) Systick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms. + (++) Time base configuration function (ald_tick_init()) is called automatically + at the beginning of the program after reset by ald_cmu_init() or at + any time when clock is configured. + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if ald_delay_ms() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. + (+) Configure the interval of Systick interrupt. + + @endverbatim + * @{ + */ + +/** + * @brief This function Configures time base source, NVIC and DMA. + * @note This function is called at the beginning of program after reset and before + * the clock configuration. + * @note The time base configuration is based on MSI clock when exiting from Reset. + * Once done, time base tick start incrementing. + * In the default implementation, Systick is used as source of time base. + * The tick variable is incremented each 1ms in its ISR. + * @retval None + */ +void ald_cmu_init(void) +{ + NVIC_SetPriorityGrouping(NVIC_PRIORITY_GROUP_2); + ald_cmu_clock_config_default(); + ald_tick_init(TICK_INT_PRIORITY); +#ifdef ALD_DMA + ald_cmu_perh_clock_config(CMU_PERH_DMA, ENABLE); + ald_dma_init(DMA0); +#endif + return; +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if ald_delay_ms() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param prio: Tick interrupt priority. + * @retval None + */ +__weak void ald_tick_init(uint32_t prio) +{ + /* Configure the SysTick IRQ */ + SysTick_Config(ald_cmu_get_sys_clock() / SYSTICK_INTERVAL_1MS); + NVIC_SetPriority(SysTick_IRQn, prio); + + return; +} + +/** + * @brief Selects the interval of systick interrupt. + * @param value: The value of interval: + * @arg @ref SYSTICK_INTERVAL_1MS 1 millisecond + * @arg @ref SYSTICK_INTERVAL_10MS 10 milliseconds + * @arg @ref SYSTICK_INTERVAL_100MS 100 milliseconds + * @arg @ref SYSTICK_INTERVAL_1000MS 1 second + * @retval None + */ +void ald_systick_interval_select(systick_interval_t value) +{ + assert_param(IS_SYSTICK_INTERVAL(value)); + + if (value == 0) return; + + SysTick_Config(ald_cmu_get_sys_clock() / value); + __systick_interval = value; + + if (TICK_INT_PRIORITY != 15) + NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY); + + return; +} +/** + * @} + */ + +/** @defgroup ALD_Public_Functions_Group2 Control functions + * @brief Control functions + * + * @verbatim + =============================================================================== + ##### Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the ALD version + (+) Waiting for flag + (+) Configure the interrupt + (+) Provide system tick value + (+) Initialize core timestamp + (+) Get core timestamp + (+) Get CPU ID + (+) Get UID + (+) Get CHIPID + + @endverbatim + * @{ + */ + +/** + * @brief This function invoked by Systick ISR. + * @note This function is declared as __weak to be overwritten in case of + * other implementations in user file. + * @retval None + */ +__weak void ald_systick_irq_cbk(void) +{ + /* do nothing */ + return; +} + +/** + * @brief This function is called to increment a global variable "lib_tick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in Systick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void ald_inc_tick(void) +{ + ++lib_tick; + ald_systick_irq_cbk(); +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t ald_get_tick(void) +{ + return lib_tick; +} + +/** + * @brief This function provides accurate delay (in microseconds) based + * on variable incremented. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where lib_tick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param delay: specifies the delay time length, in microseconds(us). + * @retval None + */ +__weak void ald_delay_us(__IO uint32_t delay) +{ + uint32_t start, now, delta, reload, us_tick; + start = SysTick->VAL; + reload = SysTick->LOAD; + us_tick = ald_cmu_get_sys_clock() / 1000000UL; + do + { + now = SysTick->VAL; + delta = (start > now) ? (start - now) : (reload + start - now); + } + while (delta < (us_tick * delay)); +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where lib_tick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param delay: specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void ald_delay_ms(__IO uint32_t delay) +{ + uint32_t tick, __delay; + + switch (__systick_interval) { + case SYSTICK_INTERVAL_1MS: + __delay = delay; + break; + + case SYSTICK_INTERVAL_10MS: + __delay = delay / 10; + break; + + case SYSTICK_INTERVAL_100MS: + __delay = delay / 100; + break; + + case SYSTICK_INTERVAL_1000MS: + __delay = delay / 1000; + break; + + default: + __delay = delay; + break; + } + + tick = ald_get_tick(); + __delay = __delay == 0 ? 1 : __delay; + + while ((ald_get_tick() - tick) < __delay) + ; +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Once ald_suspend_tick() is called, the the SysTick interrupt + * will be disabled and so Tick increment is suspended. + * @note This function is declared as __weak to be overwritten + * in case of other implementations in user file. + * @retval None + */ +__weak void ald_suspend_tick(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation, SysTick timer is the source of + * time base. It is used to generate interrupts at regular time + * intervals. Once ald_resume_tick() is called, the the SysTick + * interrupt will be enabled and so Tick increment is resumed. + * @note This function is declared as __weak to be overwritten + * in case of other implementations in user file. + * @retval None + */ +__weak void ald_resume_tick(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief This method returns the ALD revision + * @retval version: 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t ald_get_ald_version(void) +{ + return __ALD_VERSION; +} + +/** + * @brief Configure the flash wait period. + * @param cycle: The period. + * @retval None + */ +void ald_flash_wait_config(uint8_t cycle) +{ + uint32_t tmp; + + tmp = MSC->MEMWAIT; + MODIFY_REG(tmp, MSC_MEMWAIT_FLASH_W_MSK, (0x30U | cycle) << MSC_MEMWAIT_FLASH_W_POSS); + MSC->MEMWAIT = tmp; + + return; +} + +/** + * @brief Waiting the specified bit in the register change to SET/RESET. + * @param reg: The register address. + * @param bit: The specified bit. + * @param status: The status for waiting. + * @param timeout: Timeout duration. + * @retval Status, see @ref ald_status_t. + */ +ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout) +{ + uint32_t tick = ald_get_tick(); + + assert_param(timeout > 0); + + if (status == SET) { + while (!(IS_BIT_SET(*reg, bit))) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + } + else { + while ((IS_BIT_SET(*reg, bit))) { + if (((ald_get_tick()) - tick) > timeout) + return TIMEOUT; + } + } + + return OK; +} + +/** + * @brief Configure interrupt. + * @param irq: Interrunpt type. + * @param preempt_prio: preempt priority(0-3). + * @param sub_prio: sub-priority(0-3). + * @param status: Status. + * @arg ENABLE + * @arg DISABLE + * @retval None + */ +void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status) +{ + uint32_t pri; + uint8_t sub_bw, pre_bw; + uint8_t sub_mask = 0xF; + + assert_param(IS_FUNC_STATE(status)); + assert_param(IS_PREEMPT_PRIO(preempt_prio)); + assert_param(IS_SUB_PRIO(sub_prio)); + + if (status == ENABLE) { + pre_bw = 7 - (((SCB->AIRCR) >> 8) & 7); + sub_bw = 4 - pre_bw; + sub_mask >>= pre_bw; + + pri = preempt_prio << sub_bw; + pri |= sub_prio & sub_mask; + + NVIC_SetPriority(irq, pri); + NVIC_EnableIRQ(irq); + } + else { + NVIC_DisableIRQ(irq); + } + + return; +} + +/** + * @brief Initialize core timestamp. + * @retval None + */ +void ald_mcu_timestamp_init(void) +{ + DEM_CR |= (uint32_t)DEM_CR_TRCENA; + DWT_CYCCNT = 0x0; + DWT_CR |= (uint32_t)DWT_CR_CYCCNTEA; + + return; +} + +/** + * @brief Get core timestamp. + * @retval None + */ +uint32_t ald_mcu_get_timestamp(void) +{ + return (uint32_t)DWT_CYCCNT; +} + +/** + * @brief Get the CPU ID. + * @retval CPU ID. + */ +uint32_t ald_mcu_get_cpu_id(void) +{ + return SCB->CPUID; +} + +/** + * @brief Get the UID. + * @param buf: Pointer to UID, len: 12Bytes(96-bits) + * @retval None + */ +void ald_mcu_get_uid(uint8_t *buf) +{ + memcpy(&buf[0], (void *)MCU_UID0_ADDR, 4); + memcpy(&buf[4], (void *)MCU_UID1_ADDR, 4); + memcpy(&buf[8], (void *)MCU_UID2_ADDR, 4); + + return; +} + +/** + * @brief Get the CHIPID + * @retval CHPID + */ +uint32_t ald_mcu_get_chipid(void) +{ + return (uint32_t)*(uint32_t *)MCU_CHIPID_ADDR; +} + +/** + * @brief Bypass bootroom and set VR1_Ref 0xA + * @retval None + */ +void sys_config(void) +{ + uint32_t i = 0, tmp = 0; + uint8_t err = 0, flag = 0; + uint32_t inf014 = 0, inf0154 = 0, inf0244 = 0; + uint8_t cnt = 4; + + uint32_t *inf0_addr = (uint32_t *)0x20003C00; + /* read bootroom cfg register */ + inf014 = *((uint32_t *)(0x80000 + 56)); + /* read VR1_VREF register */ + inf0154 = *((uint32_t *)(0x80000 + 616)); + /* read Chip_v */ + inf0244 = *((uint32_t *)(0x80000 + 0x03D0)); + + /* if D version ,do nothing */ + if (inf0244 == 0xFFFFFF44) return; + + if (inf0154 == 0xFFFFFFFF) + while(1); + + /* if bypass bootroom */ + if ((0xFFFFFFFF != inf014)) { + /* change cfg_boot value = 0xffff */ + inf014 = 0xFFFFFFFF; + flag = 0x1; + } + + /* change CFG_VR1_VREF value, FLASH ref 0xA */ + tmp = (inf0154 >> 8) & 0xF; + if (0xA != tmp) { + inf0154 &= (uint32_t)~(0xF << 8); + inf0154 |= (0xA << 8); + inf0154 = (inf0154 & (0x0000FFFF)) | ((~(inf0154 & 0xFFFF)) << 16); + flag = 0x1; + } + + /* if flag reset, return */ + if (0x0 == flag) + return; + + /* 0x80000, 256words,INFO0 value */ + for (i = 0; i < 256; i++) + inf0_addr[i] = *((uint32_t *)(0x80000 + i * 4)); + + /* refresh value */ + inf0_addr[14] = inf014; + inf0_addr[154] = inf0154; + + while(--cnt) { + err = 0; + /* unlock */ + *((volatile uint32_t *)(0x40080000)) = 0x55AA6996; + *((volatile uint32_t *)(0x40080100)) = 0x5A962814; + *((volatile uint32_t *)(0x40080100)) = 0xE7CB69A5; + + /* erase */ + if (ald_iap_erase_page(0x80000) == OK) { + /* program 256*4bytes, info0 */ + if (ald_iap_program_words(0x80000, (uint8_t *)inf0_addr, 1024, 0) == OK) { + /* check */ + for (i = 0; i < 256; i++) { + if (inf0_addr[i] != *((uint32_t *)(0x80000 + i * 4))) { + err = 1; + break;; + } + } + if (err == 0) { + /* lock */ + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080000)) = 0x123456; + return; + } + } + else { + err = 1; + } + } + else { + err = 1; + } + } + + if (err) { + ald_iap_erase_page(0x80000); + /* lock */ + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080000)) = 0x123456; + while(1); + } +} + +/** + * @brief ADC adjust parameter config + * @retval None + */ +void adc_config(void) +{ + uint32_t inf0176 = 0, inf0178 = 0; + uint32_t inf0250 = 0, inf0251 = 0; + uint32_t inf0242 = 0, i = 0; + uint8_t flag = 0, err = 0; + uint8_t cnt = 4; + /* ram store inf0 1k buffer, 15k ~ 16k */ + uint32_t *inf0_addr = (uint32_t *)0x20003C00; + + /* Read ADC_GE */ + inf0242 = *((uint32_t *)(0x80000 + 968)); + + if (0xF5230ADC == inf0242) return; + + /* read Lot ID */ + inf0250 = *((uint32_t *)(0x80000 + 1000)); + inf0251 = *((uint32_t *)(0x80000 + 1004)); + inf0251 = (inf0251 & 0xFFFF0000) >> 16; + + /* read CFG_ADC0DA/CFG_ADC1DA */ + inf0176 = *((uint32_t *)(0x80000 + 704)); + inf0178 = *((uint32_t *)(0x80000 + 712)); + + switch(inf0250) { + case 0x45465537: + if ((inf0251 == 0x3034) || (inf0251 == 0x3035)) + flag = 1; + break; + case 0x45503931: + if ((inf0251 == 0x3732) || (inf0251 == 0x3734)) + flag = 1; + break; + case 0x45503935: + if ((inf0251 == 0x3837) || (inf0251 == 0x3839)) + flag = 1; + break; + default: + break; + } + + if (!flag) return; + + inf0176 ^= (0x1 << 15); + inf0176 = (inf0176 & 0x0000FFFF) | ((~(inf0176 & 0xFFFF)) << 16); + + inf0178 ^= (0x1 << 15); + inf0178 = (inf0178 & 0x0000FFFF) | ((~(inf0178 & 0xFFFF)) << 16); + + /* 0x80000, 256words,INFO0 value */ + for (i = 0; i < 256; i++) + inf0_addr[i] = *((uint32_t *)(0x80000 + i * 4)); + + inf0_addr[176] = inf0176; + inf0_addr[178] = inf0178; + inf0_addr[242] = 0xF5230ADC; + + while(--cnt) { + err = 0; + /* unlock */ + *((volatile uint32_t *)(0x40080000)) = 0x55AA6996; + *((volatile uint32_t *)(0x40080100)) = 0x5A962814; + *((volatile uint32_t *)(0x40080100)) = 0xE7CB69A5; + + /* erase */ + if (ald_iap_erase_page(0x80000) == OK) { + /* program 256*4bytes, info0 */ + if (ald_iap_program_words(0x80000, (uint8_t *)inf0_addr, 1024, 0) == OK) { + /* check */ + for (i = 0; i < 256; i++) { + if (inf0_addr[i] != *((uint32_t *)(0x80000 + i * 4))) { + err = 1; + break;; + } + } + if (err == 0) { + /* lock */ + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080000)) = 0x123456; + return; + } + } + else { + err = 1; + } + } + else { + err = 1; + } + } + + if (err) { + ald_iap_erase_page(0x80000); + /* lock */ + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080100)) = 0x123456; + *((volatile uint32_t *)(0x40080000)) = 0x123456; + while(1); + } +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h b/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h new file mode 100644 index 00000000..9359018f --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/Include/es32f36xx.h @@ -0,0 +1,9167 @@ +/** + ********************************************************************************* + * + * @file es32f36xx.h + * @brief ES32F36xx Device Head File + * + * @version V1.0 + * @date 18 Dec 2018 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 18 Dec 2018 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#ifndef __ES32F36XX_H__ +#define __ES32F36XX_H__ + +#define __I volatile const /* defines 'read only' permissions */ +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +#define __CHECK_DEVICE_DEFINES +#define __NVIC_PRIO_BITS 4U +#define __CM3_REV 0x0200U +#define __MPU_PRESENT 0x1 +#define __Vendor_SysTickConfig 0U + +typedef enum IRQn { + /* Cortex-M3 processor cxceptions index */ + Reset_IRQn = -15, + NMI_IRQn = -14, + HardFault_IRQn = -13, + MemManage_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + /* es32f36xx specific interrupt index */ + WWDG_IRQn = 0, + IWDG_IRQn = 1, + LVD_IRQn = 2, + RTC_IRQn = 3, + CMU_IRQn = 6, + ADC0_IRQn = 7, + CAN0_TX_IRQn = 8, + CAN0_RX0_IRQn = 9, + CAN0_RX1_IRQn = 10, + CAN0_EXCEPTION_IRQn = 11, + AD16C4T0_BRK_IRQn = 12, + AD16C4T0_UP_IRQn = 13, + AD16C4T0_TRIG_COM_IRQn = 14, + AD16C4T0_CC_IRQn = 15, + AD16C4T1_BRK_IRQn = 16, + AD16C4T1_UP_IRQn = 17, + AD16C4T1_TRIG_COM_IRQn = 18, + AD16C4T1_CC_IRQn = 19, + GP32C4T0_IRQn = 20, + GP32C4T1_IRQn = 21, + BS16T0_IRQn = 22, + BS16T1_IRQn = 23, + GP16C4T0_IRQn = 24, + GP16C4T1_IRQn = 25, + DAC0_CH0_IRQn = 27, + I2C0_EV_IRQn = 28, + I2C0_ERR_IRQn = 29, + I2C1_EV_IRQn = 30, + I2C1_ERR_IRQn = 31, + SPI0_I2S0_IRQn = 32, + SPI1_I2S1_IRQn = 33, + UART0_IRQn = 34, + UART1_IRQn = 35, + UART2_IRQn = 36, + UART3_IRQn = 37, + UART4_IRQn = 38, + UART5_IRQn = 39, + CRYPT_IRQn = 42, + ACMP0_IRQn = 43, + ACMP1_IRQn = 44, + SPI2_I2S2_IRQn = 45, + EBI_IRQn = 47, + TRNG_IRQn = 48, + TSENSE_IRQn = 49, + EXTI0_IRQn = 50, + EXTI1_IRQn = 51, + EXTI2_IRQn = 52, + EXTI3_IRQn = 53, + EXTI4_IRQn = 54, + EXTI5_IRQn = 55, + EXTI6_IRQn = 56, + EXTI7_IRQn = 57, + EXTI8_IRQn = 58, + EXTI9_IRQn = 59, + EXTI10_IRQn = 60, + EXTI11_IRQn = 61, + EXTI12_IRQn = 62, + EXTI13_IRQn = 63, + EXTI14_IRQn = 64, + EXTI15_IRQn = 65, + DMA_IRQn = 66, + ADC1_IRQn = 67, + DAC0_CH1_IRQn = 68, + QSPI_IRQn = 69, + USB_INT_IRQn = 70, + USB_DMA_IRQn = 71, + ACMP2_IRQn = 72, +} IRQn_Type; + + +#include +#include "core_cm3.h" + +#if defined (__CC_ARM) +#pragma anon_unions +#endif + +/* Peripheral register define */ + +/****************** Bit definition for SYSCFG_PROT register ************************/ + +#define SYSCFG_PROT_KEY_POSS 0U +#define SYSCFG_PROT_KEY_POSE 31U +#define SYSCFG_PROT_KEY_MSK BITS(SYSCFG_PROT_KEY_POSS,SYSCFG_PROT_KEY_POSE) + +#define SYSCFG_PROT_PROT_POS 0U +#define SYSCFG_PROT_PROT_MSK BIT(SYSCFG_PROT_PROT_POS) + +/****************** Bit definition for SYSCFG_MEMRMP register ************************/ + +#define SYSCFG_MEMRMP_BFRMPEN_POS 8U +#define SYSCFG_MEMRMP_BFRMPEN_MSK BIT(SYSCFG_MEMRMP_BFRMPEN_POS) + +#define SYSCFG_MEMRMP_BRRMPEN_POS 0U +#define SYSCFG_MEMRMP_BRRMPEN_MSK BIT(SYSCFG_MEMRMP_BRRMPEN_POS) + +/****************** Bit definition for SYSCFG_USBCFG register ************************/ + +#define SYSCFG_USBCFG_CLKRDY_POS 26U +#define SYSCFG_USBCFG_CLKRDY_MSK BIT(SYSCFG_USBCFG_CLKRDY_POS) + +#define SYSCFG_USBCFG_CLKRDYBP_POS 25U +#define SYSCFG_USBCFG_CLKRDYBP_MSK BIT(SYSCFG_USBCFG_CLKRDYBP_POS) + +#define SYSCFG_USBCFG_CKSEL_POS 24U +#define SYSCFG_USBCFG_CKSEL_MSK BIT(SYSCFG_USBCFG_CKSEL_POS) + +#define SYSCFG_USBCFG_ITRM_POSS 22U +#define SYSCFG_USBCFG_ITRM_POSE 23U +#define SYSCFG_USBCFG_ITRM_MSK BITS(SYSCFG_USBCFG_ITRM_POSS,SYSCFG_USBCFG_ITRM_POSE) + +#define SYSCFG_USBCFG_CKDIVN_POSS 16U +#define SYSCFG_USBCFG_CKDIVN_POSE 21U +#define SYSCFG_USBCFG_CKDIVN_MSK BITS(SYSCFG_USBCFG_CKDIVN_POSS,SYSCFG_USBCFG_CKDIVN_POSE) + +#define SYSCFG_USBCFG_CKDIVM_POSS 8U +#define SYSCFG_USBCFG_CKDIVM_POSE 11U +#define SYSCFG_USBCFG_CKDIVM_MSK BITS(SYSCFG_USBCFG_CKDIVM_POSS,SYSCFG_USBCFG_CKDIVM_POSE) + +#define SYSCFG_USBCFG_HSDRV_POSS 2U +#define SYSCFG_USBCFG_HSDRV_POSE 3U +#define SYSCFG_USBCFG_HSDRV_MSK BITS(SYSCFG_USBCFG_HSDRV_POSS,SYSCFG_USBCFG_HSDRV_POSE) + +#define SYSCFG_USBCFG_TXHBSE_POS 1U +#define SYSCFG_USBCFG_TXHBSE_MSK BIT(SYSCFG_USBCFG_TXHBSE_POS) + +#define SYSCFG_USBCFG_TXLBSE_POS 0U +#define SYSCFG_USBCFG_TXLBSE_MSK BIT(SYSCFG_USBCFG_TXLBSE_POS) + +/****************** Bit definition for SYSCFG_TBKCFG register ************************/ + +#define SYSCFG_TBKCFG_CLUBKE_POS 2U +#define SYSCFG_TBKCFG_CLUBKE_MSK BIT(SYSCFG_TBKCFG_CLUBKE_POS) + +#define SYSCFG_TBKCFG_LVDBKE_POS 1U +#define SYSCFG_TBKCFG_LVDBKE_MSK BIT(SYSCFG_TBKCFG_LVDBKE_POS) + +#define SYSCFG_TBKCFG_CSSBKE_POS 0U +#define SYSCFG_TBKCFG_CSSBKE_MSK BIT(SYSCFG_TBKCFG_CSSBKE_POS) + +typedef struct +{ + __IO uint32_t PROT; + __IO uint32_t MEMRMP; + uint32_t rsv0; + __IO uint32_t USBCFG; + __IO uint32_t TBKCFG; + uint32_t rsv1[59]; + __IO uint32_t TESTKEY; + uint32_t rsv2[7]; + __IO uint32_t USBTEST; +} SYSCFG_TypeDef; + +/****************** Bit definition for MSC_FLASHKEY register ************************/ + +#define MSC_FLASHKEY_STATUS_POSS 0U +#define MSC_FLASHKEY_STATUS_POSE 1U +#define MSC_FLASHKEY_STATUS_MSK BITS(MSC_FLASHKEY_STATUS_POSS,MSC_FLASHKEY_STATUS_POSE) + +/****************** Bit definition for MSC_INFOKEY register ************************/ + +#define MSC_INFOKEY_STATUS_POSS 0U +#define MSC_INFOKEY_STATUS_POSE 1U +#define MSC_INFOKEY_STATUS_MSK BITS(MSC_INFOKEY_STATUS_POSS,MSC_INFOKEY_STATUS_POSE) + +/****************** Bit definition for MSC_FLASHADDR register ************************/ + +#define MSC_FLASHADDR_IFREN_POS 19U +#define MSC_FLASHADDR_IFREN_MSK BIT(MSC_FLASHADDR_IFREN_POS) + +#define MSC_FLASHADDR_ADDR_POSS 0U +#define MSC_FLASHADDR_ADDR_POSE 18U +#define MSC_FLASHADDR_ADDR_MSK BITS(MSC_FLASHADDR_ADDR_POSS,MSC_FLASHADDR_ADDR_POSE) + +/****************** Bit definition for MSC_FLASHFIFO register ************************/ + +#define MSC_FLASHFIFO_FIFO_POSS 0U +#define MSC_FLASHFIFO_FIFO_POSE 31U +#define MSC_FLASHFIFO_FIFO_MSK BITS(MSC_FLASHFIFO_FIFO_POSS,MSC_FLASHFIFO_FIFO_POSE) + +/****************** Bit definition for MSC_FLASHDL register ************************/ + +#define MSC_FLASHDL_DATAL_POSS 0U +#define MSC_FLASHDL_DATAL_POSE 31U +#define MSC_FLASHDL_DATAL_MSK BITS(MSC_FLASHDL_DATAL_POSS,MSC_FLASHDL_DATAL_POSE) + +/****************** Bit definition for MSC_FLASHDH register ************************/ + +#define MSC_FLASHDH_DATAH_POSS 0U +#define MSC_FLASHDH_DATAH_POSE 31U +#define MSC_FLASHDH_DATAH_MSK BITS(MSC_FLASHDH_DATAH_POSS,MSC_FLASHDH_DATAH_POSE) + +/****************** Bit definition for MSC_FLASHCMD register ************************/ + +#define MSC_FLASHCMD_CMD_POSS 0U +#define MSC_FLASHCMD_CMD_POSE 31U +#define MSC_FLASHCMD_CMD_MSK BITS(MSC_FLASHCMD_CMD_POSS,MSC_FLASHCMD_CMD_POSE) + +/****************** Bit definition for MSC_FLASHCR register ************************/ + +#define MSC_FLASHCR_FIFOEN_POS 5U +#define MSC_FLASHCR_FIFOEN_MSK BIT(MSC_FLASHCR_FIFOEN_POS) + +#define MSC_FLASHCR_FLASHREQ_POS 4U +#define MSC_FLASHCR_FLASHREQ_MSK BIT(MSC_FLASHCR_FLASHREQ_POS) + +#define MSC_FLASHCR_IAPRST_POS 1U +#define MSC_FLASHCR_IAPRST_MSK BIT(MSC_FLASHCR_IAPRST_POS) + +#define MSC_FLASHCR_IAPEN_POS 0U +#define MSC_FLASHCR_IAPEN_MSK BIT(MSC_FLASHCR_IAPEN_POS) + +/****************** Bit definition for MSC_FLASHSR register ************************/ + +#define MSC_FLASHSR_TIMEOUT_POS 7U +#define MSC_FLASHSR_TIMEOUT_MSK BIT(MSC_FLASHSR_TIMEOUT_POS) + +#define MSC_FLASHSR_PROG_POS 6U +#define MSC_FLASHSR_PROG_MSK BIT(MSC_FLASHSR_PROG_POS) + +#define MSC_FLASHSR_SERA_POS 5U +#define MSC_FLASHSR_SERA_MSK BIT(MSC_FLASHSR_SERA_POS) + +#define MSC_FLASHSR_MASE_POS 4U +#define MSC_FLASHSR_MASE_MSK BIT(MSC_FLASHSR_MASE_POS) + +#define MSC_FLASHSR_ADDR_OV_POS 3U +#define MSC_FLASHSR_ADDR_OV_MSK BIT(MSC_FLASHSR_ADDR_OV_POS) + +#define MSC_FLASHSR_WRP_FLAG_POS 2U +#define MSC_FLASHSR_WRP_FLAG_MSK BIT(MSC_FLASHSR_WRP_FLAG_POS) + +#define MSC_FLASHSR_BUSY_POS 1U +#define MSC_FLASHSR_BUSY_MSK BIT(MSC_FLASHSR_BUSY_POS) + +#define MSC_FLASHSR_FLASHACK_POS 0U +#define MSC_FLASHSR_FLASHACK_MSK BIT(MSC_FLASHSR_FLASHACK_POS) + +/****************** Bit definition for MSC_FLASHPL register ************************/ + +#define MSC_FLASHPL_PROG_LEN_POSS 0U +#define MSC_FLASHPL_PROG_LEN_POSE 15U +#define MSC_FLASHPL_PROG_LEN_MSK BITS(MSC_FLASHPL_PROG_LEN_POSS,MSC_FLASHPL_PROG_LEN_POSE) + +/****************** Bit definition for MSC_MEMWAIT register ************************/ + +#define MSC_MEMWAIT_SRAM_W_POSS 8U +#define MSC_MEMWAIT_SRAM_W_POSE 9U +#define MSC_MEMWAIT_SRAM_W_MSK BITS(MSC_MEMWAIT_SRAM_W_POSS,MSC_MEMWAIT_SRAM_W_POSE) + +#define MSC_MEMWAIT_FLASH_W_POSS 0U +#define MSC_MEMWAIT_FLASH_W_POSE 3U +#define MSC_MEMWAIT_FLASH_W_MSK BITS(MSC_MEMWAIT_FLASH_W_POSS,MSC_MEMWAIT_FLASH_W_POSE) + +typedef struct +{ + __IO uint32_t FLASHKEY; + __IO uint32_t INFOKEY; + __IO uint32_t FLASHADDR; + __O uint32_t FLASHFIFO; + __IO uint32_t FLASHDL; + __IO uint32_t FLASHDH; + __O uint32_t FLASHCMD; + __IO uint32_t FLASHCR; + __I uint32_t FLASHSR; + __IO uint32_t FLASHPL; + __IO uint32_t MEMWAIT; +} MSC_TypeDef; + +/****************** Bit definition for BKPC_PROT register ************************/ + +#define BKPC_PROT_KEY_POSS 1U +#define BKPC_PROT_KEY_POSE 31U +#define BKPC_PROT_KEY_MSK BITS(BKPC_PROT_KEY_POSS,BKPC_PROT_KEY_POSE) + +#define BKPC_PROT_PROT_POS 0U +#define BKPC_PROT_PROT_MSK BIT(BKPC_PROT_PROT_POS) + +/****************** Bit definition for BKPC_CR register ************************/ + +#define BKPC_CR_WKPOL_POS 12U +#define BKPC_CR_WKPOL_MSK BIT(BKPC_CR_WKPOL_POS) + +#define BKPC_CR_WKPS_POSS 9U +#define BKPC_CR_WKPS_POSE 11U +#define BKPC_CR_WKPS_MSK BITS(BKPC_CR_WKPS_POSS,BKPC_CR_WKPS_POSE) + +#define BKPC_CR_WKPEN_POS 8U +#define BKPC_CR_WKPEN_MSK BIT(BKPC_CR_WKPEN_POS) + +#define BKPC_CR_MRST_WKPEN_POS 7U +#define BKPC_CR_MRST_WKPEN_MSK BIT(BKPC_CR_MRST_WKPEN_POS) + +#define BKPC_CR_LRCEN_POS 2U +#define BKPC_CR_LRCEN_MSK BIT(BKPC_CR_LRCEN_POS) + +#define BKPC_CR_LOSMEN_POS 1U +#define BKPC_CR_LOSMEN_MSK BIT(BKPC_CR_LOSMEN_POS) + +#define BKPC_CR_LOSCEN_POS 0U +#define BKPC_CR_LOSCEN_MSK BIT(BKPC_CR_LOSCEN_POS) + +/****************** Bit definition for BKPC_PCCR register ************************/ + +#define BKPC_PCCR_CLKEN_POS 16U +#define BKPC_PCCR_CLKEN_MSK BIT(BKPC_PCCR_CLKEN_POS) + +#define BKPC_PCCR_TSENSECS_POSS 4U +#define BKPC_PCCR_TSENSECS_POSE 5U +#define BKPC_PCCR_TSENSECS_MSK BITS(BKPC_PCCR_TSENSECS_POSS,BKPC_PCCR_TSENSECS_POSE) + +#define BKPC_PCCR_RTCCS_POSS 0U +#define BKPC_PCCR_RTCCS_POSE 1U +#define BKPC_PCCR_RTCCS_MSK BITS(BKPC_PCCR_RTCCS_POSS,BKPC_PCCR_RTCCS_POSE) + +/****************** Bit definition for BKPC_PDCR register ************************/ + +#define BKPC_PDCR_ISOLATE_POS 0U +#define BKPC_PDCR_ISOLATE_MSK BIT(BKPC_PDCR_ISOLATE_POS) + +#define BKPC_PDCR_PWRDOWN_POS 0U +#define BKPC_PDCR_PWRDOWN_MSK BIT(BKPC_PDCR_PWRDOWN_POS) + +typedef struct +{ + __IO uint32_t PROT; + __IO uint32_t CR; + __IO uint32_t PCCR; + __IO uint32_t PCR; +} BKPC_TypeDef; + +/****************** Bit definition for PMU_CR0 register ************************/ + +#define PMU_CR0_MTSTOP_POS 21U +#define PMU_CR0_MTSTOP_MSK BIT(PMU_CR0_MTSTOP_POS) + +#define PMU_CR0_LPSTOP_POS 20U +#define PMU_CR0_LPSTOP_MSK BIT(PMU_CR0_LPSTOP_POS) + +#define PMU_CR0_LPRUN_POS 19U +#define PMU_CR0_LPRUN_MSK BIT(PMU_CR0_LPRUN_POS) + +#define PMU_CR0_LPVS_POSS 16U +#define PMU_CR0_LPVS_POSE 17U +#define PMU_CR0_LPVS_MSK BITS(PMU_CR0_LPVS_POSS,PMU_CR0_LPVS_POSE) + +#define PMU_CR0_SFPD_POS 15U +#define PMU_CR0_SFPD_MSK BIT(PMU_CR0_SFPD_POS) + +#define PMU_CR0_CSTANDBYF_POS 3U +#define PMU_CR0_CSTANDBYF_MSK BIT(PMU_CR0_CSTANDBYF_POS) + +#define PMU_CR0_CWUF_POS 2U +#define PMU_CR0_CWUF_MSK BIT(PMU_CR0_CWUF_POS) + +#define PMU_CR0_LPM_POSS 0U +#define PMU_CR0_LPM_POSE 1U +#define PMU_CR0_LPM_MSK BITS(PMU_CR0_LPM_POSS,PMU_CR0_LPM_POSE) + +/****************** Bit definition for PMU_CR1 register ************************/ + +#define PMU_CR1_LDO18RDY_POS 15U +#define PMU_CR1_LDO18RDY_MSK BIT(PMU_CR1_LDO18RDY_POS) + +#define PMU_CR1_LDO18PRM_POS 2U +#define PMU_CR1_LDO18PRM_MSK BIT(PMU_CR1_LDO18PRM_POS) + +#define PMU_CR1_LDO18MOD_POSS 0U +#define PMU_CR1_LDO18MOD_POSE 1U +#define PMU_CR1_LDO18MOD_MSK BITS(PMU_CR1_LDO18MOD_POSS,PMU_CR1_LDO18MOD_POSE) + +/****************** Bit definition for PMU_SR register ************************/ + +#define PMU_SR_RSTAT_POS 3U +#define PMU_SR_RSTAT_MSK BIT(PMU_SR_RSTAT_POS) + +#define PMU_SR_USBRDY_POS 2U +#define PMU_SR_USBRDY_MSK BIT(PMU_SR_USBRDY_POS) + +#define PMU_SR_STANDBYF_POS 1U +#define PMU_SR_STANDBYF_MSK BIT(PMU_SR_STANDBYF_POS) + +#define PMU_SR_WUF_POS 0U +#define PMU_SR_WUF_MSK BIT(PMU_SR_WUF_POS) + +/****************** Bit definition for PMU_LVDCR register ************************/ + +#define PMU_LVDCR_LVDO_POS 15U +#define PMU_LVDCR_LVDO_MSK BIT(PMU_LVDCR_LVDO_POS) + +#define PMU_LVDCR_LVDFLT_POS 11U +#define PMU_LVDCR_LVDFLT_MSK BIT(PMU_LVDCR_LVDFLT_POS) + +#define PMU_LVDCR_LVIFS_POSS 8U +#define PMU_LVDCR_LVIFS_POSE 10U +#define PMU_LVDCR_LVIFS_MSK BITS(PMU_LVDCR_LVIFS_POSS,PMU_LVDCR_LVIFS_POSE) + +#define PMU_LVDCR_LVDS_POSS 4U +#define PMU_LVDCR_LVDS_POSE 7U +#define PMU_LVDCR_LVDS_MSK BITS(PMU_LVDCR_LVDS_POSS,PMU_LVDCR_LVDS_POSE) + +#define PMU_LVDCR_LVDCIF_POS 3U +#define PMU_LVDCR_LVDCIF_MSK BIT(PMU_LVDCR_LVDCIF_POS) + +#define PMU_LVDCR_LVDIF_POS 2U +#define PMU_LVDCR_LVDIF_MSK BIT(PMU_LVDCR_LVDIF_POS) + +#define PMU_LVDCR_LVDIE_POS 1U +#define PMU_LVDCR_LVDIE_MSK BIT(PMU_LVDCR_LVDIE_POS) + +#define PMU_LVDCR_LVDEN_POS 0U +#define PMU_LVDCR_LVDEN_MSK BIT(PMU_LVDCR_LVDEN_POS) + +/****************** Bit definition for PMU_PWRCR register ************************/ + +#define PMU_PWRCR_ROM_POS 12U +#define PMU_PWRCR_ROM_MSK BIT(PMU_PWRCR_ROM_POS) + +#define PMU_PWRCR_USB_POS 11U +#define PMU_PWRCR_USB_MSK BIT(PMU_PWRCR_USB_POS) + +#define PMU_PWRCR_QSPI_POS 10U +#define PMU_PWRCR_QSPI_MSK BIT(PMU_PWRCR_QSPI_POS) + +#define PMU_PWRCR_BXCAN_POS 8U +#define PMU_PWRCR_BXCAN_MSK BIT(PMU_PWRCR_BXCAN_POS) + +#define PMU_PWRCR_SRAM_POSS 0U +#define PMU_PWRCR_SRAM_POSE 5U +#define PMU_PWRCR_SRAM_MSK BITS(PMU_PWRCR_SRAM_POSS,PMU_PWRCR_SRAM_POSE) + +/****************** Bit definition for PMU_VREFCR register ************************/ + +#define PMU_VREFCR_VREFEN_POS 0U +#define PMU_VREFCR_VREFEN_MSK BIT(PMU_VREFCR_VREFEN_POS) + +typedef struct +{ + __IO uint32_t CR0; + __IO uint32_t CR1; + __I uint32_t SR; + __IO uint32_t LVDCR; + __IO uint32_t PWRCR; + uint32_t RESERVED0[3] ; + __IO uint32_t VREFCR; +} PMU_TypeDef; + +/****************** Bit definition for RMU_CR register ************************/ + +#define RMU_CR_BORVS_POSS 4U +#define RMU_CR_BORVS_POSE 7U +#define RMU_CR_BORVS_MSK BITS(RMU_CR_BORVS_POSS,RMU_CR_BORVS_POSE) + +#define RMU_CR_BORFLT_POSS 1U +#define RMU_CR_BORFLT_POSE 3U +#define RMU_CR_BORFLT_MSK BITS(RMU_CR_BORFLT_POSS,RMU_CR_BORFLT_POSE) + +#define RMU_CR_BOREN_POS 0U +#define RMU_CR_BOREN_MSK BIT(RMU_CR_BOREN_POS) + +/****************** Bit definition for RMU_RSTSR register ************************/ + +#define RMU_RSTSR_CFGERR_POS 16U +#define RMU_RSTSR_CFGERR_MSK BIT(RMU_RSTSR_CFGERR_POS) + +#define RMU_RSTSR_CFG_POS 10U +#define RMU_RSTSR_CFG_MSK BIT(RMU_RSTSR_CFG_POS) + +#define RMU_RSTSR_CPU_POS 9U +#define RMU_RSTSR_CPU_MSK BIT(RMU_RSTSR_CPU_POS) + +#define RMU_RSTSR_MCU_POS 8U +#define RMU_RSTSR_MCU_MSK BIT(RMU_RSTSR_MCU_POS) + +#define RMU_RSTSR_CHIP_POS 7U +#define RMU_RSTSR_CHIP_MSK BIT(RMU_RSTSR_CHIP_POS) + +#define RMU_RSTSR_LOCKUP_POS 6U +#define RMU_RSTSR_LOCKUP_MSK BIT(RMU_RSTSR_LOCKUP_POS) + +#define RMU_RSTSR_WWDT_POS 5U +#define RMU_RSTSR_WWDT_MSK BIT(RMU_RSTSR_WWDT_POS) + +#define RMU_RSTSR_IWDT_POS 4U +#define RMU_RSTSR_IWDT_MSK BIT(RMU_RSTSR_IWDT_POS) + +#define RMU_RSTSR_NMRST_POS 3U +#define RMU_RSTSR_NMRST_MSK BIT(RMU_RSTSR_NMRST_POS) + +#define RMU_RSTSR_BOR_POS 2U +#define RMU_RSTSR_BOR_MSK BIT(RMU_RSTSR_BOR_POS) + +#define RMU_RSTSR_WAKEUP_POS 1U +#define RMU_RSTSR_WAKEUP_MSK BIT(RMU_RSTSR_WAKEUP_POS) + +#define RMU_RSTSR_POR_POS 0U +#define RMU_RSTSR_POR_MSK BIT(RMU_RSTSR_POR_POS) + +/****************** Bit definition for RMU_CRSTSR register ************************/ + +#define RMU_CRSTSR_CFG_POS 10U +#define RMU_CRSTSR_CFG_MSK BIT(RMU_CRSTSR_CFG_POS) + +#define RMU_CRSTSR_CPU_POS 9U +#define RMU_CRSTSR_CPU_MSK BIT(RMU_CRSTSR_CPU_POS) + +#define RMU_CRSTSR_MCU_POS 8U +#define RMU_CRSTSR_MCU_MSK BIT(RMU_CRSTSR_MCU_POS) + +#define RMU_CRSTSR_CHIP_POS 7U +#define RMU_CRSTSR_CHIP_MSK BIT(RMU_CRSTSR_CHIP_POS) + +#define RMU_CRSTSR_LOCKUP_POS 6U +#define RMU_CRSTSR_LOCKUP_MSK BIT(RMU_CRSTSR_LOCKUP_POS) + +#define RMU_CRSTSR_WWDT_POS 5U +#define RMU_CRSTSR_WWDT_MSK BIT(RMU_CRSTSR_WWDT_POS) + +#define RMU_CRSTSR_IWDT_POS 4U +#define RMU_CRSTSR_IWDT_MSK BIT(RMU_CRSTSR_IWDT_POS) + +#define RMU_CRSTSR_NMRST_POS 3U +#define RMU_CRSTSR_NMRST_MSK BIT(RMU_CRSTSR_NMRST_POS) + +#define RMU_CRSTSR_BOR_POS 2U +#define RMU_CRSTSR_BOR_MSK BIT(RMU_CRSTSR_BOR_POS) + +#define RMU_CRSTSR_WAKEUP_POS 1U +#define RMU_CRSTSR_WAKEUP_MSK BIT(RMU_CRSTSR_WAKEUP_POS) + +#define RMU_CRSTSR_POR_POS 0U +#define RMU_CRSTSR_POR_MSK BIT(RMU_CRSTSR_POR_POS) + +/****************** Bit definition for RMU_AHB1RSTR register ************************/ + +#define RMU_AHB1RSTR_ECCRST_POS 11U +#define RMU_AHB1RSTR_ECCRST_MSK BIT(RMU_AHB1RSTR_ECCRST_POS) + +#define RMU_AHB1RSTR_USBRST_POS 10U +#define RMU_AHB1RSTR_USBRST_MSK BIT(RMU_AHB1RSTR_USBRST_POS) + +#define RMU_AHB1RSTR_TRNGRST_POS 4U +#define RMU_AHB1RSTR_TRNGRST_MSK BIT(RMU_AHB1RSTR_TRNGRST_POS) + +#define RMU_AHB1RSTR_PISRST_POS 5U +#define RMU_AHB1RSTR_PISRST_MSK BIT(RMU_AHB1RSTR_PISRST_POS) + +#define RMU_AHB1RSTR_TRNGRST_POS 4U +#define RMU_AHB1RSTR_TRNGRST_MSK BIT(RMU_AHB1RSTR_TRNGRST_POS) + +#define RMU_AHB1RSTR_CRYPTRST_POS 3U +#define RMU_AHB1RSTR_CRYPTRST_MSK BIT(RMU_AHB1RSTR_CRYPTRST_POS) + +#define RMU_AHB1RSTR_CALCRST_POS 2U +#define RMU_AHB1RSTR_CALCRST_MSK BIT(RMU_AHB1RSTR_CALCRST_POS) + +#define RMU_AHB1RSTR_CRCRST_POS 1U +#define RMU_AHB1RSTR_CRCRST_MSK BIT(RMU_AHB1RSTR_CRCRST_POS) + +#define RMU_AHB1RSTR_GPIORST_POS 0U +#define RMU_AHB1RSTR_GPIORST_MSK BIT(RMU_AHB1RSTR_GPIORST_POS) + +/****************** Bit definition for RMU_AHB2RSTR register ************************/ + +#define RMU_AHB2RSTR_EBIRST_POS 8U +#define RMU_AHB2RSTR_EBIRST_MSK BIT(RMU_AHB2RSTR_EBIRST_POS) + +#define RMU_AHB2RSTR_CPURST_POS 1U +#define RMU_AHB2RSTR_CPURST_MSK BIT(RMU_AHB2RSTR_CPURST_POS) + +#define RMU_AHB2RSTR_CHIPRST_POS 0U +#define RMU_AHB2RSTR_CHIPRST_MSK BIT(RMU_AHB2RSTR_CHIPRST_POS) + +/****************** Bit definition for RMU_APB1RSTR register ************************/ + +#define RMU_APB1RSTR_QSPIRST_POS 25U +#define RMU_APB1RSTR_QSPIRST_MSK BIT(RMU_APB1RSTR_QSPIRST_POS) + +#define RMU_APB1RSTR_CAN0RST_POS 24U +#define RMU_APB1RSTR_CAN0RST_MSK BIT(RMU_APB1RSTR_CAN0RST_POS) + +#define RMU_APB1RSTR_I2C1RST_POS 21U +#define RMU_APB1RSTR_I2C1RST_MSK BIT(RMU_APB1RSTR_I2C1RST_POS) + +#define RMU_APB1RSTR_I2C0RST_POS 20U +#define RMU_APB1RSTR_I2C0RST_MSK BIT(RMU_APB1RSTR_I2C0RST_POS) + +#define RMU_APB1RSTR_SPI2RST_POS 18U +#define RMU_APB1RSTR_SPI2RST_MSK BIT(RMU_APB1RSTR_SPI2RST_POS) + +#define RMU_APB1RSTR_SPI1RST_POS 17U +#define RMU_APB1RSTR_SPI1RST_MSK BIT(RMU_APB1RSTR_SPI1RST_POS) + +#define RMU_APB1RSTR_SPI0RST_POS 16U +#define RMU_APB1RSTR_SPI0RST_MSK BIT(RMU_APB1RSTR_SPI0RST_POS) + +#define RMU_APB1RSTR_UART5RST_POS 13U +#define RMU_APB1RSTR_UART5RST_MSK BIT(RMU_APB1RSTR_UART5RST_POS) + +#define RMU_APB1RSTR_UART4RST_POS 12U +#define RMU_APB1RSTR_UART4RST_MSK BIT(RMU_APB1RSTR_UART4RST_POS) + +#define RMU_APB1RSTR_UART3RST_POS 11U +#define RMU_APB1RSTR_UART3RST_MSK BIT(RMU_APB1RSTR_UART3RST_POS) + +#define RMU_APB1RSTR_UART2RST_POS 10U +#define RMU_APB1RSTR_UART2RST_MSK BIT(RMU_APB1RSTR_UART2RST_POS) + +#define RMU_APB1RSTR_UART1RST_POS 9U +#define RMU_APB1RSTR_UART1RST_MSK BIT(RMU_APB1RSTR_UART1RST_POS) + +#define RMU_APB1RSTR_UART0RST_POS 8U +#define RMU_APB1RSTR_UART0RST_MSK BIT(RMU_APB1RSTR_UART0RST_POS) + +#define RMU_APB1RSTR_TIM7RST_POS 7U +#define RMU_APB1RSTR_TIM7RST_MSK BIT(RMU_APB1RSTR_TIM7RST_POS) + +#define RMU_APB1RSTR_TIM6RST_POS 6U +#define RMU_APB1RSTR_TIM6RST_MSK BIT(RMU_APB1RSTR_TIM6RST_POS) + +#define RMU_APB1RSTR_TIM5RST_POS 5U +#define RMU_APB1RSTR_TIM5RST_MSK BIT(RMU_APB1RSTR_TIM5RST_POS) + +#define RMU_APB1RSTR_TIM4RST_POS 4U +#define RMU_APB1RSTR_TIM4RST_MSK BIT(RMU_APB1RSTR_TIM4RST_POS) + +#define RMU_APB1RSTR_TIM3RST_POS 3U +#define RMU_APB1RSTR_TIM3RST_MSK BIT(RMU_APB1RSTR_TIM3RST_POS) + +#define RMU_APB1RSTR_TIM2RST_POS 2U +#define RMU_APB1RSTR_TIM2RST_MSK BIT(RMU_APB1RSTR_TIM2RST_POS) + +#define RMU_APB1RSTR_TIM1RST_POS 1U +#define RMU_APB1RSTR_TIM1RST_MSK BIT(RMU_APB1RSTR_TIM1RST_POS) + +#define RMU_APB1RSTR_TIM0RST_POS 0U +#define RMU_APB1RSTR_TIM0RST_MSK BIT(RMU_APB1RSTR_TIM0RST_POS) + +/****************** Bit definition for RMU_APB2RSTR register ************************/ + +#define RMU_APB2RSTR_BKPRAMRST_POS 18U +#define RMU_APB2RSTR_BKPRAMRST_MSK BIT(RMU_APB2RSTR_BKPRAMRST_POS) + +#define RMU_APB2RSTR_BKPCRST_POS 17U +#define RMU_APB2RSTR_BKPCRST_MSK BIT(RMU_APB2RSTR_BKPCRST_POS) + +#define RMU_APB2RSTR_TSENSERST_POS 16U +#define RMU_APB2RSTR_TSENSERST_MSK BIT(RMU_APB2RSTR_TSENSERST_POS) + +#define RMU_APB2RSTR_RTCRST_POS 15U +#define RMU_APB2RSTR_RTCRST_MSK BIT(RMU_APB2RSTR_RTCRST_POS) + +#define RMU_APB2RSTR_IWDTRST_POS 14U +#define RMU_APB2RSTR_IWDTRST_MSK BIT(RMU_APB2RSTR_IWDTRST_POS) + +#define RMU_APB2RSTR_LCDRST_POS 13U +#define RMU_APB2RSTR_LCDRST_MSK BIT(RMU_APB2RSTR_LCDRST_POS) + +#define RMU_APB2RSTR_WWDTRST_POS 12U +#define RMU_APB2RSTR_WWDTRST_MSK BIT(RMU_APB2RSTR_WWDTRST_POS) + +#define RMU_APB2RSTR_ACMP2RST_POS 11U +#define RMU_APB2RSTR_ACMP2RST_MSK BIT(RMU_APB2RSTR_DACRST_POS) + +#define RMU_APB2RSTR_DACRST_POS 9U +#define RMU_APB2RSTR_DACRST_MSK BIT(RMU_APB2RSTR_DACRST_POS) + +#define RMU_APB2RSTR_OPAMPRST_POS 8U +#define RMU_APB2RSTR_OPAMPRST_MSK BIT(RMU_APB2RSTR_OPAMPRST_POS) + +#define RMU_APB2RSTR_ACMP1RST_POS 7U +#define RMU_APB2RSTR_ACMP1RST_MSK BIT(RMU_APB2RSTR_ACMP1RST_POS) + +#define RMU_APB2RSTR_ACMP0RST_POS 6U +#define RMU_APB2RSTR_ACMP0RST_MSK BIT(RMU_APB2RSTR_ACMP0RST_POS) + +#define RMU_APB2RSTR_ADC1RST_POS 5U +#define RMU_APB2RSTR_ADC1RST_MSK BIT(RMU_APB2RSTR_ADC1RST_POS) + +#define RMU_APB2RSTR_ADC0RST_POS 4U +#define RMU_APB2RSTR_ADC0RST_MSK BIT(RMU_APB2RSTR_ADC0RST_POS) + +#define RMU_APB2RSTR_LPUART0RST_POS 2U +#define RMU_APB2RSTR_LPUART0RST_MSK BIT(RMU_APB2RSTR_LPUART0RST_POS) + +#define RMU_APB2RSTR_LPTIM0RST_POS 0U +#define RMU_APB2RSTR_LPTIM0RST_MSK BIT(RMU_APB2RSTR_LPTIM0RST_POS) + +typedef struct +{ + __IO uint32_t CR; + uint32_t RESERVED0[3] ; + __I uint32_t RSTSR; + __O uint32_t CRSTSR; + uint32_t RESERVED1[2] ; + __O uint32_t AHB1RSTR; + __O uint32_t AHB2RSTR; + uint32_t RESERVED2[2] ; + __O uint32_t APB1RSTR; + __O uint32_t APB2RSTR; +} RMU_TypeDef; + +/****************** Bit definition for CMU_CSR register ************************/ + +#define CMU_CSR_CFT_RDYN_POS 25U +#define CMU_CSR_CFT_RDYN_MSK BIT(CMU_CSR_CFT_RDYN_POS) + +#define CMU_CSR_CFT_STU_POS 24U +#define CMU_CSR_CFT_STU_MSK BIT(CMU_CSR_CFT_STU_POS) + +#define CMU_CSR_CFT_CMD_POSS 16U +#define CMU_CSR_CFT_CMD_POSE 23U +#define CMU_CSR_CFT_CMD_MSK BITS(CMU_CSR_CFT_CMD_POSS,CMU_CSR_CFT_CMD_POSE) + +#define CMU_CSR_SYS_RDYN_POS 12U +#define CMU_CSR_SYS_RDYN_MSK BIT(CMU_CSR_SYS_RDYN_POS) + +#define CMU_CSR_SYS_STU_POSS 8U +#define CMU_CSR_SYS_STU_POSE 10U +#define CMU_CSR_SYS_STU_MSK BITS(CMU_CSR_SYS_STU_POSS,CMU_CSR_SYS_STU_POSE) + +#define CMU_CSR_SYS_CMD_POSS 0U +#define CMU_CSR_SYS_CMD_POSE 2U +#define CMU_CSR_SYS_CMD_MSK BITS(CMU_CSR_SYS_CMD_POSS,CMU_CSR_SYS_CMD_POSE) + +/****************** Bit definition for CMU_CFGR register ************************/ + +#define CMU_CFGR_HRCFCS_POS 26U +#define CMU_CFGR_HRCFCS_MSK BIT(CMU_CFGR_HRCFCS_POS) + +#define CMU_CFGR_HRCFST_POS 25U +#define CMU_CFGR_HRCFST_MSK BIT(CMU_CFGR_HRCFST_POS) + +#define CMU_CFGR_HRCFSW_POS 24U +#define CMU_CFGR_HRCFSW_MSK BIT(CMU_CFGR_HRCFSW_POS) + +#define CMU_CFGR_PCLK2DIV_POSS 20U +#define CMU_CFGR_PCLK2DIV_POSE 23U +#define CMU_CFGR_PCLK2DIV_MSK BITS(CMU_CFGR_PCLK2DIV_POSS,CMU_CFGR_PCLK2DIV_POSE) + +#define CMU_CFGR_PCLK1DIV_POSS 16U +#define CMU_CFGR_PCLK1DIV_POSE 19U +#define CMU_CFGR_PCLK1DIV_MSK BITS(CMU_CFGR_PCLK1DIV_POSS,CMU_CFGR_PCLK1DIV_POSE) + +#define CMU_CFGR_SYSDIV_POSS 12U +#define CMU_CFGR_SYSDIV_POSE 15U +#define CMU_CFGR_SYSDIV_MSK BITS(CMU_CFGR_SYSDIV_POSS,CMU_CFGR_SYSDIV_POSE) + +#define CMU_CFGR_HCLK2DIV_POSS 4U +#define CMU_CFGR_HCLK2DIV_POSE 7U +#define CMU_CFGR_HCLK2DIV_MSK BITS(CMU_CFGR_HCLK2DIV_POSS,CMU_CFGR_HCLK2DIV_POSE) + +#define CMU_CFGR_HCLK1DIV_POSS 0U +#define CMU_CFGR_HCLK1DIV_POSE 3U +#define CMU_CFGR_HCLK1DIV_MSK BITS(CMU_CFGR_HCLK1DIV_POSS,CMU_CFGR_HCLK1DIV_POSE) + +/****************** Bit definition for CMU_CLKENR register ************************/ + +#define CMU_CLKENR_HOSC1MEN_POS 17U +#define CMU_CLKENR_HOSC1MEN_MSK BIT(CMU_CLKENR_HOSC1MEN_POS) + +#define CMU_CLKENR_HRC1MEN_POS 16U +#define CMU_CLKENR_HRC1MEN_MSK BIT(CMU_CLKENR_HRC1MEN_POS) + +#define CMU_CLKENR_PLL2EN_POS 9U +#define CMU_CLKENR_PLL2EN_MSK BIT(CMU_CLKENR_PLL2EN_POS) + +#define CMU_CLKENR_PLL1EN_POS 8U +#define CMU_CLKENR_PLL1EN_MSK BIT(CMU_CLKENR_PLL1EN_POS) + +#define CMU_CLKENR_ULRCEN_POS 4U +#define CMU_CLKENR_ULRCEN_MSK BIT(CMU_CLKENR_ULRCEN_POS) + +#define CMU_CLKENR_LRCEN_POS 3U +#define CMU_CLKENR_LRCEN_MSK BIT(CMU_CLKENR_LRCEN_POS) + +#define CMU_CLKENR_HRCEN_POS 2U +#define CMU_CLKENR_HRCEN_MSK BIT(CMU_CLKENR_HRCEN_POS) + +#define CMU_CLKENR_LOSCEN_POS 1U +#define CMU_CLKENR_LOSCEN_MSK BIT(CMU_CLKENR_LOSCEN_POS) + +#define CMU_CLKENR_HOSCEN_POS 0U +#define CMU_CLKENR_HOSCEN_MSK BIT(CMU_CLKENR_HOSCEN_POS) + +/****************** Bit definition for CMU_CLKSR register ************************/ + +#define CMU_CLKSR_PLL2RDY_POS 25U +#define CMU_CLKSR_PLL2RDY_MSK BIT(CMU_CLKSR_PLL2RDY_POS) + +#define CMU_CLKSR_PLL1RDY_POS 24U +#define CMU_CLKSR_PLL1RDY_MSK BIT(CMU_CLKSR_PLL1RDY_POS) + +#define CMU_CLKSR_LRCRDY_POS 19U +#define CMU_CLKSR_LRCRDY_MSK BIT(CMU_CLKSR_LRCRDY_POS) + +#define CMU_CLKSR_HRCRDY_POS 18U +#define CMU_CLKSR_HRCRDY_MSK BIT(CMU_CLKSR_HRCRDY_POS) + +#define CMU_CLKSR_LOSCRDY_POS 17U +#define CMU_CLKSR_LOSCRDY_MSK BIT(CMU_CLKSR_LOSCRDY_POS) + +#define CMU_CLKSR_HOSCRDY_POS 16U +#define CMU_CLKSR_HOSCRDY_MSK BIT(CMU_CLKSR_HOSCRDY_POS) + +#define CMU_CLKSR_PLL2ACT_POS 9U +#define CMU_CLKSR_PLL2ACT_MSK BIT(CMU_CLKSR_PLL2ACT_POS) + +#define CMU_CLKSR_PLL1ACT_POS 8U +#define CMU_CLKSR_PLL1ACT_MSK BIT(CMU_CLKSR_PLL1ACT_POS) + +#define CMU_CLKSR_ULRCACT_POS 4U +#define CMU_CLKSR_ULRCACT_MSK BIT(CMU_CLKSR_ULRCACT_POS) + +#define CMU_CLKSR_LRCACT_POS 3U +#define CMU_CLKSR_LRCACT_MSK BIT(CMU_CLKSR_LRCACT_POS) + +#define CMU_CLKSR_HRCACT_POS 2U +#define CMU_CLKSR_HRCACT_MSK BIT(CMU_CLKSR_HRCACT_POS) + +#define CMU_CLKSR_LOSCACT_POS 1U +#define CMU_CLKSR_LOSCACT_MSK BIT(CMU_CLKSR_LOSCACT_POS) + +#define CMU_CLKSR_HOSCACT_POS 0U +#define CMU_CLKSR_HOSCACT_MSK BIT(CMU_CLKSR_HOSCACT_POS) + +/****************** Bit definition for CMU_PLLCFG register ************************/ + +#define CMU_PLLCFG_PLL2LCKN_POS 17U +#define CMU_PLLCFG_PLL2LCKN_MSK BIT(CMU_PLLCFG_PLL2LCKN_POS) + +#define CMU_PLLCFG_PLL1LCKN_POS 16U +#define CMU_PLLCFG_PLL1LCKN_MSK BIT(CMU_PLLCFG_PLL1LCKN_POS) + +#define CMU_PLLCFG_PLL2RFS_POSS 8U +#define CMU_PLLCFG_PLL2RFS_POSE 9U +#define CMU_PLLCFG_PLL2RFS_MSK BITS(CMU_PLLCFG_PLL2RFS_POSS,CMU_PLLCFG_PLL2RFS_POSE) + +#define CMU_PLLCFG_PLL1OS_POSS 4U +#define CMU_PLLCFG_PLL1OS_POSE 5U +#define CMU_PLLCFG_PLL1OS_MSK BITS(CMU_PLLCFG_PLL1OS_POSS,CMU_PLLCFG_PLL1OS_POSE) + +#define CMU_PLLCFG_PLL1RFS_POSS 0U +#define CMU_PLLCFG_PLL1RFS_POSE 2U +#define CMU_PLLCFG_PLL1RFS_MSK BITS(CMU_PLLCFG_PLL1RFS_POSS,CMU_PLLCFG_PLL1RFS_POSE) + +/****************** Bit definition for CMU_HOSCCFG register ************************/ + +#define CMU_HOSCCFG_FREQ_POSS 0U +#define CMU_HOSCCFG_FREQ_POSE 4U +#define CMU_HOSCCFG_FREQ_MSK BITS(CMU_HOSCCFG_FREQ_POSS,CMU_HOSCCFG_FREQ_POSE) + +/****************** Bit definition for CMU_HOSMCR register ************************/ + +#define CMU_HOSMCR_NMIE_POS 20U +#define CMU_HOSMCR_NMIE_MSK BIT(CMU_HOSMCR_NMIE_POS) + +#define CMU_HOSMCR_STPIF_POS 19U +#define CMU_HOSMCR_STPIF_MSK BIT(CMU_HOSMCR_STPIF_POS) + +#define CMU_HOSMCR_STRIF_POS 18U +#define CMU_HOSMCR_STRIF_MSK BIT(CMU_HOSMCR_STRIF_POS) + +#define CMU_HOSMCR_STPIE_POS 17U +#define CMU_HOSMCR_STPIE_MSK BIT(CMU_HOSMCR_STPIE_POS) + +#define CMU_HOSMCR_STRIE_POS 16U +#define CMU_HOSMCR_STRIE_MSK BIT(CMU_HOSMCR_STRIE_POS) + +#define CMU_HOSMCR_FRQS_POSS 8U +#define CMU_HOSMCR_FRQS_POSE 10U +#define CMU_HOSMCR_FRQS_MSK BITS(CMU_HOSMCR_FRQS_POSS,CMU_HOSMCR_FRQS_POSE) + +#define CMU_HOSMCR_CLKS_POS 1U +#define CMU_HOSMCR_CLKS_MSK BIT(CMU_HOSMCR_CLKS_POS) + +#define CMU_HOSMCR_EN_POS 0U +#define CMU_HOSMCR_EN_MSK BIT(CMU_HOSMCR_EN_POS) + +/****************** Bit definition for CMU_LOSMCR register ************************/ + +#define CMU_LOSMCR_NMIE_POS 20U +#define CMU_LOSMCR_NMIE_MSK BIT(CMU_LOSMCR_NMIE_POS) + +#define CMU_LOSMCR_STPIF_POS 19U +#define CMU_LOSMCR_STPIF_MSK BIT(CMU_LOSMCR_STPIF_POS) + +#define CMU_LOSMCR_STRIF_POS 18U +#define CMU_LOSMCR_STRIF_MSK BIT(CMU_LOSMCR_STRIF_POS) + +#define CMU_LOSMCR_STPIE_POS 17U +#define CMU_LOSMCR_STPIE_MSK BIT(CMU_LOSMCR_STPIE_POS) + +#define CMU_LOSMCR_STRIE_POS 16U +#define CMU_LOSMCR_STRIE_MSK BIT(CMU_LOSMCR_STRIE_POS) + +#define CMU_LOSMCR_CLKS_POS 1U +#define CMU_LOSMCR_CLKS_MSK BIT(CMU_LOSMCR_CLKS_POS) + +#define CMU_LOSMCR_EN_POS 0U +#define CMU_LOSMCR_EN_MSK BIT(CMU_LOSMCR_EN_POS) + +/****************** Bit definition for CMU_PULMCR register ************************/ + +#define CMU_PULMCR_NMIE_POS 20U +#define CMU_PULMCR_NMIE_MSK BIT(CMU_PULMCR_NMIE_POS) + +#define CMU_PULMCR_ULKIF_POS 19U +#define CMU_PULMCR_ULKIF_MSK BIT(CMU_PULMCR_ULKIF_POS) + +#define CMU_PULMCR_LCKIF_POS 18U +#define CMU_PULMCR_LCKIF_MSK BIT(CMU_PULMCR_LCKIF_POS) + +#define CMU_PULMCR_ULKIE_POS 17U +#define CMU_PULMCR_ULKIE_MSK BIT(CMU_PULMCR_ULKIE_POS) + +#define CMU_PULMCR_LCKIE_POS 16U +#define CMU_PULMCR_LCKIE_MSK BIT(CMU_PULMCR_LCKIE_POS) + +#define CMU_PULMCR_MODE_POSS 8U +#define CMU_PULMCR_MODE_POSE 9U +#define CMU_PULMCR_MODE_MSK BITS(CMU_PULMCR_MODE_POSS,CMU_PULMCR_MODE_POSE) + +#define CMU_PULMCR_CLKS_POS 1U +#define CMU_PULMCR_CLKS_MSK BIT(CMU_PULMCR_CLKS_POS) + +#define CMU_PULMCR_EN_POS 0U +#define CMU_PULMCR_EN_MSK BIT(CMU_PULMCR_EN_POS) + +/****************** Bit definition for CMU_CLKOCR register ************************/ + +#define CMU_CLKOCR_LSCOS_POSS 24U +#define CMU_CLKOCR_LSCOS_POSE 26U +#define CMU_CLKOCR_LSCOS_MSK BITS(CMU_CLKOCR_LSCOS_POSS,CMU_CLKOCR_LSCOS_POSE) + +#define CMU_CLKOCR_LSCOEN_POS 16U +#define CMU_CLKOCR_LSCOEN_MSK BIT(CMU_CLKOCR_LSCOEN_POS) + +#define CMU_CLKOCR_HSCODIV_POSS 12U +#define CMU_CLKOCR_HSCODIV_POSE 14U +#define CMU_CLKOCR_HSCODIV_MSK BITS(CMU_CLKOCR_HSCODIV_POSS,CMU_CLKOCR_HSCODIV_POSE) + +#define CMU_CLKOCR_HSCOS_POSS 8U +#define CMU_CLKOCR_HSCOS_POSE 10U +#define CMU_CLKOCR_HSCOS_MSK BITS(CMU_CLKOCR_HSCOS_POSS,CMU_CLKOCR_HSCOS_POSE) + +#define CMU_CLKOCR_HSCOEN_POS 0U +#define CMU_CLKOCR_HSCOEN_MSK BIT(CMU_CLKOCR_HSCOEN_POS) + +/****************** Bit definition for CMU_BUZZCR register ************************/ + +#define CMU_BUZZCR_DAT_POSS 16U +#define CMU_BUZZCR_DAT_POSE 31U +#define CMU_BUZZCR_DAT_MSK BITS(CMU_BUZZCR_DAT_POSS,CMU_BUZZCR_DAT_POSE) + +#define CMU_BUZZCR_DIV_POSS 8U +#define CMU_BUZZCR_DIV_POSE 10U +#define CMU_BUZZCR_DIV_MSK BITS(CMU_BUZZCR_DIV_POSS,CMU_BUZZCR_DIV_POSE) + +#define CMU_BUZZCR_EN_POS 0U +#define CMU_BUZZCR_EN_MSK BIT(CMU_BUZZCR_EN_POS) + +/****************** Bit definition for CMU_AHB1ENR register ************************/ + +#define CMU_AHB1ENR_ECCEN_POS 11U +#define CMU_AHB1ENR_ECCEN_MSK BIT(CMU_AHB1ENR_ECCEN_POS) + +#define CMU_AHB1ENR_USBEN_POS 10U +#define CMU_AHB1ENR_USBEN_MSK BIT(CMU_AHB1ENR_USBEN_POS) + +#define CMU_AHB1ENR_DMAEN_POS 8U +#define CMU_AHB1ENR_DMAEN_MSK BIT(CMU_AHB1ENR_DMAEN_POS) + +#define CMU_AHB1ENR_QSPIEN_POS 7U +#define CMU_AHB1ENR_QSPIEN_MSK BIT(CMU_AHB1ENR_QSPIEN_POS) + +#define CMU_AHB1ENR_EBIEN_POS 6U +#define CMU_AHB1ENR_EBIEN_MSK BIT(CMU_AHB1ENR_EBIEN_POS) + +#define CMU_AHB1ENR_PISEN_POS 5U +#define CMU_AHB1ENR_PISEN_MSK BIT(CMU_AHB1ENR_PISEN_POS) + +#define CMU_AHB1ENR_TRNGEN_POS 4U +#define CMU_AHB1ENR_TRNGEN_MSK BIT(CMU_AHB1ENR_TRNGEN_POS) + +#define CMU_AHB1ENR_CRYPTEN_POS 3U +#define CMU_AHB1ENR_CRYPTEN_MSK BIT(CMU_AHB1ENR_CRYPTEN_POS) + +#define CMU_AHB1ENR_CALCEN_POS 2U +#define CMU_AHB1ENR_CALCEN_MSK BIT(CMU_AHB1ENR_CALCEN_POS) + +#define CMU_AHB1ENR_CRCEN_POS 1U +#define CMU_AHB1ENR_CRCEN_MSK BIT(CMU_AHB1ENR_CRCEN_POS) + +#define CMU_AHB1ENR_GPIOEN_POS 0U +#define CMU_AHB1ENR_GPIOEN_MSK BIT(CMU_AHB1ENR_GPIOEN_POS) + +/****************** Bit definition for CMU_APB1ENR register ************************/ + +#define CMU_APB1ENR_QSPIEN_POS 25U +#define CMU_APB1ENR_QSPIEN_MSK BIT(CMU_APB1ENR_QSPIEN_POS) + +#define CMU_APB1ENR_CAN0EN_POS 24U +#define CMU_APB1ENR_CAN0EN_MSK BIT(CMU_APB1ENR_CAN0EN_POS) + +#define CMU_APB1ENR_I2C1EN_POS 21U +#define CMU_APB1ENR_I2C1EN_MSK BIT(CMU_APB1ENR_I2C1EN_POS) + +#define CMU_APB1ENR_I2C0EN_POS 20U +#define CMU_APB1ENR_I2C0EN_MSK BIT(CMU_APB1ENR_I2C0EN_POS) + +#define CMU_APB1ENR_SPI2EN_POS 18U +#define CMU_APB1ENR_SPI2EN_MSK BIT(CMU_APB1ENR_SPI2EN_POS) + +#define CMU_APB1ENR_SPI1EN_POS 17U +#define CMU_APB1ENR_SPI1EN_MSK BIT(CMU_APB1ENR_SPI1EN_POS) + +#define CMU_APB1ENR_SPI0EN_POS 16U +#define CMU_APB1ENR_SPI0EN_MSK BIT(CMU_APB1ENR_SPI0EN_POS) + +#define CMU_APB1ENR_UART5EN_POS 13U +#define CMU_APB1ENR_UART5EN_MSK BIT(CMU_APB1ENR_UART5EN_POS) + +#define CMU_APB1ENR_UART4EN_POS 12U +#define CMU_APB1ENR_UART4EN_MSK BIT(CMU_APB1ENR_UART4EN_POS) + +#define CMU_APB1ENR_UART3EN_POS 11U +#define CMU_APB1ENR_UART3EN_MSK BIT(CMU_APB1ENR_UART3EN_POS) + +#define CMU_APB1ENR_UART2EN_POS 10U +#define CMU_APB1ENR_UART2EN_MSK BIT(CMU_APB1ENR_UART2EN_POS) + +#define CMU_APB1ENR_UART1EN_POS 9U +#define CMU_APB1ENR_UART1EN_MSK BIT(CMU_APB1ENR_UART1EN_POS) + +#define CMU_APB1ENR_UART0EN_POS 8U +#define CMU_APB1ENR_UART0EN_MSK BIT(CMU_APB1ENR_UART0EN_POS) + +#define CMU_APB1ENR_TIM7EN_POS 7U +#define CMU_APB1ENR_TIM7EN_MSK BIT(CMU_APB1ENR_TIM7EN_POS) + +#define CMU_APB1ENR_TIM6EN_POS 6U +#define CMU_APB1ENR_TIM6EN_MSK BIT(CMU_APB1ENR_TIM6EN_POS) + +#define CMU_APB1ENR_TIM5EN_POS 5U +#define CMU_APB1ENR_TIM5EN_MSK BIT(CMU_APB1ENR_TIM5EN_POS) + +#define CMU_APB1ENR_TIM4EN_POS 4U +#define CMU_APB1ENR_TIM4EN_MSK BIT(CMU_APB1ENR_TIM4EN_POS) + +#define CMU_APB1ENR_TIM3EN_POS 3U +#define CMU_APB1ENR_TIM3EN_MSK BIT(CMU_APB1ENR_TIM3EN_POS) + +#define CMU_APB1ENR_TIM2EN_POS 2U +#define CMU_APB1ENR_TIM2EN_MSK BIT(CMU_APB1ENR_TIM2EN_POS) + +#define CMU_APB1ENR_TIM1EN_POS 1U +#define CMU_APB1ENR_TIM1EN_MSK BIT(CMU_APB1ENR_TIM1EN_POS) + +#define CMU_APB1ENR_TIM0EN_POS 0U +#define CMU_APB1ENR_TIM0EN_MSK BIT(CMU_APB1ENR_TIM0EN_POS) + +/****************** Bit definition for CMU_APB2ENR register ************************/ + +#define CMU_APB2ENR_DBGCEN_POS 19U +#define CMU_APB2ENR_DBGCEN_MSK BIT(CMU_APB2ENR_DBGCEN_POS) + +#define CMU_APB2ENR_BKPCEN_POS 17U +#define CMU_APB2ENR_BKPCEN_MSK BIT(CMU_APB2ENR_BKPCEN_POS) + +#define CMU_APB2ENR_TSENSEEN_POS 16U +#define CMU_APB2ENR_TSENSEEN_MSK BIT(CMU_APB2ENR_TSENSEEN_POS) + +#define CMU_APB2ENR_RTCEN_POS 15U +#define CMU_APB2ENR_RTCEN_MSK BIT(CMU_APB2ENR_RTCEN_POS) + +#define CMU_APB2ENR_IWDTEN_POS 14U +#define CMU_APB2ENR_IWDTEN_MSK BIT(CMU_APB2ENR_IWDTEN_POS) + +#define CMU_APB2ENR_LCDEN_POS 13U +#define CMU_APB2ENR_LCDEN_MSK BIT(CMU_APB2ENR_LCDEN_POS) + +#define CMU_APB2ENR_WWDTEN_POS 12U +#define CMU_APB2ENR_WWDTEN_MSK BIT(CMU_APB2ENR_WWDTEN_POS) + +#define CMU_APB2ENR_ACMP2EN_POS 11U +#define CMU_APB2ENR_ACMP2EN_MSK BIT(CMU_APB2ENR_ACMP2EN_POS) + +#define CMU_APB2ENR_DAC0EN_POS 9U +#define CMU_APB2ENR_DAC0EN_MSK BIT(CMU_APB2ENR_DAC0EN_POS) + +#define CMU_APB2ENR_OPAMPEN_POS 8U +#define CMU_APB2ENR_OPAMPEN_MSK BIT(CMU_APB2ENR_OPAMPEN_POS) + +#define CMU_APB2ENR_ACMP1EN_POS 7U +#define CMU_APB2ENR_ACMP1EN_MSK BIT(CMU_APB2ENR_ACMP1EN_POS) + +#define CMU_APB2ENR_ACMP0EN_POS 6U +#define CMU_APB2ENR_ACMP0EN_MSK BIT(CMU_APB2ENR_ACMP0EN_POS) + +#define CMU_APB2ENR_ADC1EN_POS 5U +#define CMU_APB2ENR_ADC1EN_MSK BIT(CMU_APB2ENR_ADC1EN_POS) + +#define CMU_APB2ENR_ADC0EN_POS 4U +#define CMU_APB2ENR_ADC0EN_MSK BIT(CMU_APB2ENR_ADC0EN_POS) + +#define CMU_APB2ENR_LPUART0EN_POS 2U +#define CMU_APB2ENR_LPUART0EN_MSK BIT(CMU_APB2ENR_LPUART0EN_POS) + +#define CMU_APB2ENR_LPTIM0EN_POS 0U +#define CMU_APB2ENR_LPTIM0EN_MSK BIT(CMU_APB2ENR_LPTIM0EN_POS) + +/****************** Bit definition for CMU_LPENR register ************************/ + +#define CMU_LPENR_STOP1CS_POSS 16U +#define CMU_LPENR_STOP1CS_POSE 18U +#define CMU_LPENR_STOP1CS_MSK BITS(CMU_LPENR_STOP1CS_POSS,CMU_LPENR_STOP1CS_POSE) + +#define CMU_LPENR_HOSCEN_POS 3U +#define CMU_LPENR_HOSCEN_MSK BIT(CMU_LPENR_HOSCEN_POS) + +#define CMU_LPENR_HRCEN_POS 2U +#define CMU_LPENR_HRCEN_MSK BIT(CMU_LPENR_HRCEN_POS) + +#define CMU_LPENR_LOSCEN_POS 1U +#define CMU_LPENR_LOSCEN_MSK BIT(CMU_LPENR_LOSCEN_POS) + +#define CMU_LPENR_LRCEN_POS 0U +#define CMU_LPENR_LRCEN_MSK BIT(CMU_LPENR_LRCEN_POS) + +/****************** Bit definition for CMU_PERICR register ************************/ + +#define CMU_PERICR_USBPHYCS_POSS 28U +#define CMU_PERICR_USBPHYCS_POSE 30U +#define CMU_PERICR_USBPHYCS_MSK BITS(CMU_PERICR_USBPHYCS_POSS,CMU_PERICR_USBPHYCS_POSE) + +#define CMU_PERICR_QSPICS_POSS 24U +#define CMU_PERICR_QSPICS_POSE 26U +#define CMU_PERICR_QSPICS_MSK BITS(CMU_PERICR_QSPICS_POSS,CMU_PERICR_QSPICS_POSE) + +#define CMU_PERICR_LCD_POSS 16U +#define CMU_PERICR_LCD_POSE 18U +#define CMU_PERICR_LCD_MSK BITS(CMU_PERICR_LCD_POSS,CMU_PERICR_LCD_POSE) + +#define CMU_PERICR_LPUART0_POSS 8U +#define CMU_PERICR_LPUART0_POSE 11U +#define CMU_PERICR_LPUART0_MSK BITS(CMU_PERICR_LPUART0_POSS,CMU_PERICR_LPUART0_POSE) + +#define CMU_PERICR_LPTIM0_POSS 0U +#define CMU_PERICR_LPTIM0_POSE 3U +#define CMU_PERICR_LPTIM0_MSK BITS(CMU_PERICR_LPTIM0_POSS,CMU_PERICR_LPTIM0_POSE) + +/****************** Bit definition for CMU_PERIDIVR register ************************/ + +#define CMU_PERIDIVR_USBPHYDIV_POSS 28U +#define CMU_PERIDIVR_USBPHYDIV_POSE 31U +#define CMU_PERIDIVR_USBPHYDIV_MSK BITS(CMU_PERIDIVR_USBPHYDIV_POSS,CMU_PERIDIVR_USBPHYDIV_POSE) + +typedef struct +{ + __O uint32_t CSR; + __IO uint32_t CFGR; + uint32_t RESERVED0[2] ; + __IO uint32_t CLKENR; + __I uint32_t CLKSR; + __IO uint32_t PLLCFG; + __IO uint32_t HOSCCFG; + __IO uint32_t HOSMCR; + __IO uint32_t LOSMCR; + __IO uint32_t PULMCR; + uint32_t RESERVED1 ; + __IO uint32_t CLKOCR; + __IO uint32_t BUZZCR; + uint32_t RESERVED2[2] ; + __IO uint32_t AHB1ENR; + uint32_t RESERVED3[3] ; + __IO uint32_t APB1ENR; + __IO uint32_t APB2ENR; + uint32_t RESERVED4[2] ; + __IO uint32_t LPENR; + uint32_t RESERVED5[7] ; + __IO uint32_t PERICR; + uint32_t RESERVED6 ; + __IO uint32_t PERIDIVR; +} CMU_TypeDef; + +/****************** Bit definition for DMA_STATUS register ************************/ + +#define DMA_STATUS_STATUS_POSS 4U +#define DMA_STATUS_STATUS_POSE 7U +#define DMA_STATUS_STATUS_MSK BITS(DMA_STATUS_STATUS_POSS,DMA_STATUS_STATUS_POSE) + +#define DMA_STATUS_MASTER_ENABLE_POS 0U +#define DMA_STATUS_MASTER_ENABLE_MSK BIT(DMA_STATUS_MASTER_ENABLE_POS) + +/****************** Bit definition for DMA_CFG register ************************/ + +#define DMA_CFG_CHNL_PROT_CTRL_POSS 5U +#define DMA_CFG_CHNL_PROT_CTRL_POSE 7U +#define DMA_CFG_CHNL_PROT_CTRL_MSK BITS(DMA_CFG_CHNL_PROT_CTRL_POSS,DMA_CFG_CHNL_PROT_CTRL_POSE) + +#define DMA_CFG_MASTER_ENABLE_POS 0U +#define DMA_CFG_MASTER_ENABLE_MSK BIT(DMA_CFG_MASTER_ENABLE_POS) + +/****************** Bit definition for DMA_CTRLBASE register ************************/ + +#define DMA_CTRLBASE_CTRL_BASE_PTR_POSS 9U +#define DMA_CTRLBASE_CTRL_BASE_PTR_POSE 31U +#define DMA_CTRLBASE_CTRL_BASE_PTR_MSK BITS(DMA_CTRLBASE_CTRL_BASE_PTR_POSS,DMA_CTRLBASE_CTRL_BASE_PTR_POSE) + +/****************** Bit definition for DMA_ALTCTRLBASE register ************************/ + +#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSS 0U +#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSE 31U +#define DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_MSK BITS(DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSS,DMA_ALTCTRLBASE_ALT_CTRL_BASE_PTR_POSE) + +/****************** Bit definition for DMA_CHWAITSTATUS register ************************/ + +#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS 0U +#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE 31U +#define DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_MSK BITS(DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSS,DMA_CHWAITSTATUS_DMA_WAITONREQ_STATUS_POSE) + +/****************** Bit definition for DMA_CHSWREQ register ************************/ + +#define DMA_CHSWREQ_CHSWREQ_POSS 0U +#define DMA_CHSWREQ_CHSWREQ_POSE 31U +#define DMA_CHSWREQ_CHSWREQ_MSK BITS(DMA_CHSWREQ_CHSWREQ_POSS,DMA_CHSWREQ_CHSWREQ_POSE) + +/****************** Bit definition for DMA_CHUSEBURSTSET register ************************/ + +#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS 0U +#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE 31U +#define DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_MSK BITS(DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSS,DMA_CHUSEBURSTSET_CHNL_USEBURST_SET_POSE) + +/****************** Bit definition for DMA_CHUSEBURSTCLR register ************************/ + +#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS 0U +#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE 31U +#define DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_MSK BITS(DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSS,DMA_CHUSEBURSTCLR_CHNL_USEBURST_CLR_POSE) + +/****************** Bit definition for DMA_CHREQMASKSET register ************************/ + +#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS 0U +#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE 31U +#define DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_MSK BITS(DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSS,DMA_CHREQMASKSET_CHNL_REQ_MASK_SET_POSE) + +/****************** Bit definition for DMA_CHREQMASKCLR register ************************/ + +#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS 0U +#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE 31U +#define DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_MSK BITS(DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSS,DMA_CHREQMASKCLR_CHNL_REQ_MASK_CLR_POSE) + +/****************** Bit definition for DMA_CHENSET register ************************/ + +#define DMA_CHENSET_CHNL_ENABLE_SET_POSS 0U +#define DMA_CHENSET_CHNL_ENABLE_SET_POSE 31U +#define DMA_CHENSET_CHNL_ENABLE_SET_MSK BITS(DMA_CHENSET_CHNL_ENABLE_SET_POSS,DMA_CHENSET_CHNL_ENABLE_SET_POSE) + +/****************** Bit definition for DMA_CHENCLR register ************************/ + +#define DMA_CHENCLR_CHNL_ENABLE_CLR_POSS 0U +#define DMA_CHENCLR_CHNL_ENABLE_CLR_POSE 31U +#define DMA_CHENCLR_CHNL_ENABLE_CLR_MSK BITS(DMA_CHENCLR_CHNL_ENABLE_CLR_POSS,DMA_CHENCLR_CHNL_ENABLE_CLR_POSE) + +/****************** Bit definition for DMA_CHPRIALTSET register ************************/ + +#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS 0U +#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE 31U +#define DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_MSK BITS(DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSS,DMA_CHPRIALTSET_CHNL_PRI_ALT_SET_POSE) + +/****************** Bit definition for DMA_CHPRIALTCLR register ************************/ + +#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS 0U +#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE 31U +#define DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_MSK BITS(DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSS,DMA_CHPRIALTCLR_CHNL_PRI_ALT_CLR_POSE) + +/****************** Bit definition for DMA_CHPRSET register ************************/ + +#define DMA_CHPRSET_CHNL_PRIORITY_SET_POSS 0U +#define DMA_CHPRSET_CHNL_PRIORITY_SET_POSE 31U +#define DMA_CHPRSET_CHNL_PRIORITY_SET_MSK BITS(DMA_CHPRSET_CHNL_PRIORITY_SET_POSS,DMA_CHPRSET_CHNL_PRIORITY_SET_POSE) + +/****************** Bit definition for DMA_CHPRCLR register ************************/ + +#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS 0U +#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE 31U +#define DMA_CHPRCLR_CHNL_PRIORITY_CLR_MSK BITS(DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSS,DMA_CHPRCLR_CHNL_PRIORITY_CLR_POSE) + +/****************** Bit definition for DMA_ERRCLR register ************************/ + +#define DMA_ERRCLR_ERR_CLR_POS 0U +#define DMA_ERRCLR_ERR_CLR_MSK BIT(DMA_ERRCLR_ERR_CLR_POS) + +/****************** Bit definition for DMA_IFLAG register ************************/ + +#define DMA_IFLAG_DMAERRIF_POS 31U +#define DMA_IFLAG_DMAERRIF_MSK BIT(DMA_IFLAG_DMAERRIF_POS) + +#define DMA_IFLAG_CH11DONEIF_POS 11U +#define DMA_IFLAG_CH11DONEIF_MSK BIT(DMA_IFLAG_CH11DONEIF_POS) + +#define DMA_IFLAG_CH10DONEIF_POS 10U +#define DMA_IFLAG_CH10DONEIF_MSK BIT(DMA_IFLAG_CH10DONEIF_POS) + +#define DMA_IFLAG_CH9DONEIF_POS 9U +#define DMA_IFLAG_CH9DONEIF_MSK BIT(DMA_IFLAG_CH9DONEIF_POS) + +#define DMA_IFLAG_CH8DONEIF_POS 8U +#define DMA_IFLAG_CH8DONEIF_MSK BIT(DMA_IFLAG_CH8DONEIF_POS) + +#define DMA_IFLAG_CH7DONEIF_POS 7U +#define DMA_IFLAG_CH7DONEIF_MSK BIT(DMA_IFLAG_CH7DONEIF_POS) + +#define DMA_IFLAG_CH6DONEIF_POS 6U +#define DMA_IFLAG_CH6DONEIF_MSK BIT(DMA_IFLAG_CH6DONEIF_POS) + +#define DMA_IFLAG_CH5DONEIF_POS 5U +#define DMA_IFLAG_CH5DONEIF_MSK BIT(DMA_IFLAG_CH5DONEIF_POS) + +#define DMA_IFLAG_CH4DONEIF_POS 4U +#define DMA_IFLAG_CH4DONEIF_MSK BIT(DMA_IFLAG_CH4DONEIF_POS) + +#define DMA_IFLAG_CH3DONEIF_POS 3U +#define DMA_IFLAG_CH3DONEIF_MSK BIT(DMA_IFLAG_CH3DONEIF_POS) + +#define DMA_IFLAG_CH2DONEIF_POS 2U +#define DMA_IFLAG_CH2DONEIF_MSK BIT(DMA_IFLAG_CH2DONEIF_POS) + +#define DMA_IFLAG_CH1DONEIF_POS 1U +#define DMA_IFLAG_CH1DONEIF_MSK BIT(DMA_IFLAG_CH1DONEIF_POS) + +#define DMA_IFLAG_CH0DONEIF_POS 0U +#define DMA_IFLAG_CH0DONEIF_MSK BIT(DMA_IFLAG_CH0DONEIF_POS) + +/****************** Bit definition for DMA_ICFR register ************************/ + +#define DMA_ICFR_DMAERRC_POS 31U +#define DMA_ICFR_DMAERRC_MSK BIT(DMA_ICFR_DMAERRC_POS) + +#define DMA_ICFR_CH11DONEC_POS 11U +#define DMA_ICFR_CH11DONEC_MSK BIT(DMA_ICFR_CH11DONEC_POS) + +#define DMA_ICFR_CH10DONEC_POS 10U +#define DMA_ICFR_CH10DONEC_MSK BIT(DMA_ICFR_CH10DONEC_POS) + +#define DMA_ICFR_CH9DONEC_POS 9U +#define DMA_ICFR_CH9DONEC_MSK BIT(DMA_ICFR_CH9DONEC_POS) + +#define DMA_ICFR_CH8DONEC_POS 8U +#define DMA_ICFR_CH8DONEC_MSK BIT(DMA_ICFR_CH8DONEC_POS) + +#define DMA_ICFR_CH7DONEC_POS 7U +#define DMA_ICFR_CH7DONEC_MSK BIT(DMA_ICFR_CH7DONEC_POS) + +#define DMA_ICFR_CH6DONEC_POS 6U +#define DMA_ICFR_CH6DONEC_MSK BIT(DMA_ICFR_CH6DONEC_POS) + +#define DMA_ICFR_CH5DONEC_POS 5U +#define DMA_ICFR_CH5DONEC_MSK BIT(DMA_ICFR_CH5DONEC_POS) + +#define DMA_ICFR_CH4DONEC_POS 4U +#define DMA_ICFR_CH4DONEC_MSK BIT(DMA_ICFR_CH4DONEC_POS) + +#define DMA_ICFR_CH3DONEC_POS 3U +#define DMA_ICFR_CH3DONEC_MSK BIT(DMA_ICFR_CH3DONEC_POS) + +#define DMA_ICFR_CH2DONEC_POS 2U +#define DMA_ICFR_CH2DONEC_MSK BIT(DMA_ICFR_CH2DONEC_POS) + +#define DMA_ICFR_CH1DONEC_POS 1U +#define DMA_ICFR_CH1DONEC_MSK BIT(DMA_ICFR_CH1DONEC_POS) + +#define DMA_ICFR_CH0DONEC_POS 0U +#define DMA_ICFR_CH0DONEC_MSK BIT(DMA_ICFR_CH0DONEC_POS) + +/****************** Bit definition for DMA_IER register ************************/ + +#define DMA_IER_DMAERRIE_POS 31U +#define DMA_IER_DMAERRIE_MSK BIT(DMA_IER_DMAERRIE_POS) + +#define DMA_IER_CH11DONEIE_POS 11U +#define DMA_IER_CH11DONEIE_MSK BIT(DMA_IER_CH11DONEIE_POS) + +#define DMA_IER_CH10DONEIE_POS 10U +#define DMA_IER_CH10DONEIE_MSK BIT(DMA_IER_CH10DONEIE_POS) + +#define DMA_IER_CH9DONEIE_POS 9U +#define DMA_IER_CH9DONEIE_MSK BIT(DMA_IER_CH9DONEIE_POS) + +#define DMA_IER_CH8DONEIE_POS 8U +#define DMA_IER_CH8DONEIE_MSK BIT(DMA_IER_CH8DONEIE_POS) + +#define DMA_IER_CH7DONEIE_POS 7U +#define DMA_IER_CH7DONEIE_MSK BIT(DMA_IER_CH7DONEIE_POS) + +#define DMA_IER_CH6DONEIE_POS 6U +#define DMA_IER_CH6DONEIE_MSK BIT(DMA_IER_CH6DONEIE_POS) + +#define DMA_IER_CH5DONEIE_POS 5U +#define DMA_IER_CH5DONEIE_MSK BIT(DMA_IER_CH5DONEIE_POS) + +#define DMA_IER_CH4DONEIE_POS 4U +#define DMA_IER_CH4DONEIE_MSK BIT(DMA_IER_CH4DONEIE_POS) + +#define DMA_IER_CH3DONEIE_POS 3U +#define DMA_IER_CH3DONEIE_MSK BIT(DMA_IER_CH3DONEIE_POS) + +#define DMA_IER_CH2DONEIE_POS 2U +#define DMA_IER_CH2DONEIE_MSK BIT(DMA_IER_CH2DONEIE_POS) + +#define DMA_IER_CH1DONEIE_POS 1U +#define DMA_IER_CH1DONEIE_MSK BIT(DMA_IER_CH1DONEIE_POS) + +#define DMA_IER_CH0DONEIE_POS 0U +#define DMA_IER_CH0DONEIE_MSK BIT(DMA_IER_CH0DONEIE_POS) + +/****************** Bit definition for DMA_CH0_SELCON register ************************/ + +#define DMA_CH0_SELCON_MSEL_POSS 8U +#define DMA_CH0_SELCON_MSEL_POSE 13U +#define DMA_CH0_SELCON_MSEL_MSK BITS(DMA_CH0_SELCON_MSEL_POSS,DMA_CH0_SELCON_MSEL_POSE) + +#define DMA_CH0_SELCON_MSIGSEL_POSS 0U +#define DMA_CH0_SELCON_MSIGSEL_POSE 3U +#define DMA_CH0_SELCON_MSIGSEL_MSK BITS(DMA_CH0_SELCON_MSIGSEL_POSS,DMA_CH0_SELCON_MSIGSEL_POSE) + +typedef struct +{ + __I uint32_t STATUS; + __IO uint32_t CFG; + __IO uint32_t CTRLBASE; + __I uint32_t ALTCTRLBASE; + __I uint32_t CHWAITSTATUS; + __IO uint32_t CHSWREQ; + __IO uint32_t CHUSEBURSTSET; + __O uint32_t CHUSEBURSTCLR; + __IO uint32_t CHREQMASKSET; + __O uint32_t CHREQMASKCLR; + __IO uint32_t CHENSET; + __O uint32_t CHENCLR; + __IO uint32_t CHPRIALTSET; + __O uint32_t CHPRIALTCLR; + __IO uint32_t CHPRSET; + __O uint32_t CHPRCLR; + uint32_t RESERVED0[3] ; + __IO uint32_t ERRCLR; + uint32_t RESERVED1[1004] ; + __I uint32_t IFLAG; + uint32_t RESERVED2 ; + __O uint32_t ICFR; + __IO uint32_t IER; + uint32_t RESERVED3[60] ; + __IO uint32_t CH_SELCON[12]; +} DMA_TypeDef; + +/****************** Bit definition for ECC_AREG(x = 1 .. 64) register ************************/ +#define ECC_AREGx_VAL_POSS 0U +#define ECC_AREGx_VAL_POSE 31U +#define ECC_AREGx_VAL_MSK BITS(ECC_AREG1_VAL_POSS,ECC_AREG1_VAL_POSE) + +/****************** Bit definition for ECC_NREG register ************************/ +#define ECC_NREGx_VAL_POSS 0U +#define ECC_NREGx_VAL_POSE 31U +#define ECC_NREGx_VAL_MSK BITS(ECC_AREG1_VAL_POSS,ECC_AREG1_VAL_POSE) + +/****************** Bit definition for ECC_CON register ************************/ + +#define ECC_CON_SINGST_POS 31U +#define ECC_CON_SINGST_MSK BIT(ECC_CON_SINGST_POS) + +#define ECC_CON_COMBST_POS 30U +#define ECC_CON_COMBST_MSK BIT(ECC_CON_COMBST_POS) + +#define ECC_CON_REMAP_POS 29U +#define ECC_CON_REMAP_MSK BIT(ECC_CON_REMAP_POS) + +#define ECC_CON_COMBMD_POSS 27U +#define ECC_CON_COMBMD_POSE 28U +#define ECC_CON_COMBMD_MSK BITS(ECC_CON_COMBMD_POSS,ECC_CON_COMBMD_POSE) + +#define ECC_CON_OPL_POSS 10U +#define ECC_CON_OPL_POSE 12U +#define ECC_CON_OPL_MSK BITS(ECC_CON_OPL_POSS,ECC_CON_OPL_POSE) + +#define ECC_CON_OPR_POSS 7U +#define ECC_CON_OPR_POSE 9U +#define ECC_CON_OPR_MSK BITS(ECC_CON_OPR_POSS,ECC_CON_OPR_POSE) + +#define ECC_CON_RES_POSS 4U +#define ECC_CON_RES_POSE 6U +#define ECC_CON_RES_MSK BITS(ECC_CON_RES_POSS,ECC_CON_RES_POSE) + +#define ECC_CON_MODE_POSS 1U +#define ECC_CON_MODE_POSE 3U +#define ECC_CON_MODE_MSK BITS(ECC_CON_MODE_POSS,ECC_CON_MODE_POSE) + +#define ECC_CON_IE_POS 0U +#define ECC_CON_IE_MSK BIT(ECC_CON_IE_POS) + +/****************** Bit definition for ECC_STAT register ************************/ + +#define ECC_STAT_ERR_POS 2U +#define ECC_STAT_ERR_MSK BIT(ECC_STAT_ERR_POS) + +#define ECC_STAT_DONE_POS 1U +#define ECC_STAT_DONE_MSK BIT(ECC_STAT_DONE_POS) + +#define ECC_STAT_BUSY_POS 0U +#define ECC_STAT_BUSY_MSK BIT(ECC_STAT_BUSY_POS) + +/****************** Bit definition for ECC_PARA register ************************/ + +#define ECC_PARA_VAL_POSS 0U +#define ECC_PARA_VAL_POSE 31U +#define ECC_PARA_VAL_MSK BITS(ECC_PARA_VAL_POSS,ECC_PARA_VAL_POSE) + +typedef struct +{ + __IO uint32_t AREG[64]; + __IO uint32_t NREG[8]; + uint32_t RESERVED0[120]; + __IO uint32_t CON; + __IO uint32_t STAT; + __IO uint32_t PARA; +} ECC_TypeDef; + +/****************** Bit definition for PIS_CH0_CON register ************************/ + +#define PIS_CH0_CON_SYNCSEL_POSS 24U +#define PIS_CH0_CON_SYNCSEL_POSE 26U +#define PIS_CH0_CON_SYNCSEL_MSK BITS(PIS_CH0_CON_SYNCSEL_POSS,PIS_CH0_CON_SYNCSEL_POSE) + +#define PIS_CH0_CON_PULCK_POSS 18U +#define PIS_CH0_CON_PULCK_POSE 19U +#define PIS_CH0_CON_PULCK_MSK BITS(PIS_CH0_CON_PULCK_POSS,PIS_CH0_CON_PULCK_POSE) + +#define PIS_CH0_CON_EDGS_POSS 16U +#define PIS_CH0_CON_EDGS_POSE 17U +#define PIS_CH0_CON_EDGS_MSK BITS(PIS_CH0_CON_EDGS_POSS,PIS_CH0_CON_EDGS_POSE) + +#define PIS_CH0_CON_SRCS_POSS 8U +#define PIS_CH0_CON_SRCS_POSE 13U +#define PIS_CH0_CON_SRCS_MSK BITS(PIS_CH0_CON_SRCS_POSS,PIS_CH0_CON_SRCS_POSE) + +#define PIS_CH0_CON_MSIGS_POSS 0U +#define PIS_CH0_CON_MSIGS_POSE 3U +#define PIS_CH0_CON_MSIGS_MSK BITS(PIS_CH0_CON_MSIGS_POSS,PIS_CH0_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH1_CON register ************************/ + +#define PIS_CH1_CON_SYNCSEL_POSS 24U +#define PIS_CH1_CON_SYNCSEL_POSE 26U +#define PIS_CH1_CON_SYNCSEL_MSK BITS(PIS_CH1_CON_SYNCSEL_POSS,PIS_CH1_CON_SYNCSEL_POSE) + +#define PIS_CH1_CON_PULCK_POSS 18U +#define PIS_CH1_CON_PULCK_POSE 19U +#define PIS_CH1_CON_PULCK_MSK BITS(PIS_CH1_CON_PULCK_POSS,PIS_CH1_CON_PULCK_POSE) + +#define PIS_CH1_CON_EDGS_POSS 16U +#define PIS_CH1_CON_EDGS_POSE 17U +#define PIS_CH1_CON_EDGS_MSK BITS(PIS_CH1_CON_EDGS_POSS,PIS_CH1_CON_EDGS_POSE) + +#define PIS_CH1_CON_SRCS_POSS 8U +#define PIS_CH1_CON_SRCS_POSE 13U +#define PIS_CH1_CON_SRCS_MSK BITS(PIS_CH1_CON_SRCS_POSS,PIS_CH1_CON_SRCS_POSE) + +#define PIS_CH1_CON_MSIGS_POSS 0U +#define PIS_CH1_CON_MSIGS_POSE 3U +#define PIS_CH1_CON_MSIGS_MSK BITS(PIS_CH1_CON_MSIGS_POSS,PIS_CH1_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH2_CON register ************************/ + +#define PIS_CH2_CON_SYNCSEL_POSS 24U +#define PIS_CH2_CON_SYNCSEL_POSE 26U +#define PIS_CH2_CON_SYNCSEL_MSK BITS(PIS_CH2_CON_SYNCSEL_POSS,PIS_CH2_CON_SYNCSEL_POSE) + +#define PIS_CH2_CON_PULCK_POSS 18U +#define PIS_CH2_CON_PULCK_POSE 19U +#define PIS_CH2_CON_PULCK_MSK BITS(PIS_CH2_CON_PULCK_POSS,PIS_CH2_CON_PULCK_POSE) + +#define PIS_CH2_CON_EDGS_POSS 16U +#define PIS_CH2_CON_EDGS_POSE 17U +#define PIS_CH2_CON_EDGS_MSK BITS(PIS_CH2_CON_EDGS_POSS,PIS_CH2_CON_EDGS_POSE) + +#define PIS_CH2_CON_SRCS_POSS 8U +#define PIS_CH2_CON_SRCS_POSE 13U +#define PIS_CH2_CON_SRCS_MSK BITS(PIS_CH2_CON_SRCS_POSS,PIS_CH2_CON_SRCS_POSE) + +#define PIS_CH2_CON_MSIGS_POSS 0U +#define PIS_CH2_CON_MSIGS_POSE 3U +#define PIS_CH2_CON_MSIGS_MSK BITS(PIS_CH2_CON_MSIGS_POSS,PIS_CH2_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH3_CON register ************************/ + +#define PIS_CH3_CON_SYNCSEL_POSS 24U +#define PIS_CH3_CON_SYNCSEL_POSE 26U +#define PIS_CH3_CON_SYNCSEL_MSK BITS(PIS_CH3_CON_SYNCSEL_POSS,PIS_CH3_CON_SYNCSEL_POSE) + +#define PIS_CH3_CON_PULCK_POSS 18U +#define PIS_CH3_CON_PULCK_POSE 19U +#define PIS_CH3_CON_PULCK_MSK BITS(PIS_CH3_CON_PULCK_POSS,PIS_CH3_CON_PULCK_POSE) + +#define PIS_CH3_CON_EDGS_POSS 16U +#define PIS_CH3_CON_EDGS_POSE 17U +#define PIS_CH3_CON_EDGS_MSK BITS(PIS_CH3_CON_EDGS_POSS,PIS_CH3_CON_EDGS_POSE) + +#define PIS_CH3_CON_SRCS_POSS 8U +#define PIS_CH3_CON_SRCS_POSE 13U +#define PIS_CH3_CON_SRCS_MSK BITS(PIS_CH3_CON_SRCS_POSS,PIS_CH3_CON_SRCS_POSE) + +#define PIS_CH3_CON_MSIGS_POSS 0U +#define PIS_CH3_CON_MSIGS_POSE 3U +#define PIS_CH3_CON_MSIGS_MSK BITS(PIS_CH3_CON_MSIGS_POSS,PIS_CH3_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH4_CON register ************************/ + +#define PIS_CH4_CON_SYNCSEL_POSS 24U +#define PIS_CH4_CON_SYNCSEL_POSE 26U +#define PIS_CH4_CON_SYNCSEL_MSK BITS(PIS_CH4_CON_SYNCSEL_POSS,PIS_CH4_CON_SYNCSEL_POSE) + +#define PIS_CH4_CON_PULCK_POSS 18U +#define PIS_CH4_CON_PULCK_POSE 19U +#define PIS_CH4_CON_PULCK_MSK BITS(PIS_CH4_CON_PULCK_POSS,PIS_CH4_CON_PULCK_POSE) + +#define PIS_CH4_CON_EDGS_POSS 16U +#define PIS_CH4_CON_EDGS_POSE 17U +#define PIS_CH4_CON_EDGS_MSK BITS(PIS_CH4_CON_EDGS_POSS,PIS_CH4_CON_EDGS_POSE) + +#define PIS_CH4_CON_SRCS_POSS 8U +#define PIS_CH4_CON_SRCS_POSE 13U +#define PIS_CH4_CON_SRCS_MSK BITS(PIS_CH4_CON_SRCS_POSS,PIS_CH4_CON_SRCS_POSE) + +#define PIS_CH4_CON_MSIGS_POSS 0U +#define PIS_CH4_CON_MSIGS_POSE 3U +#define PIS_CH4_CON_MSIGS_MSK BITS(PIS_CH4_CON_MSIGS_POSS,PIS_CH4_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH5_CON register ************************/ + +#define PIS_CH5_CON_SYNCSEL_POSS 24U +#define PIS_CH5_CON_SYNCSEL_POSE 26U +#define PIS_CH5_CON_SYNCSEL_MSK BITS(PIS_CH5_CON_SYNCSEL_POSS,PIS_CH5_CON_SYNCSEL_POSE) + +#define PIS_CH5_CON_PULCK_POSS 18U +#define PIS_CH5_CON_PULCK_POSE 19U +#define PIS_CH5_CON_PULCK_MSK BITS(PIS_CH5_CON_PULCK_POSS,PIS_CH5_CON_PULCK_POSE) + +#define PIS_CH5_CON_EDGS_POSS 16U +#define PIS_CH5_CON_EDGS_POSE 17U +#define PIS_CH5_CON_EDGS_MSK BITS(PIS_CH5_CON_EDGS_POSS,PIS_CH5_CON_EDGS_POSE) + +#define PIS_CH5_CON_SRCS_POSS 8U +#define PIS_CH5_CON_SRCS_POSE 13U +#define PIS_CH5_CON_SRCS_MSK BITS(PIS_CH5_CON_SRCS_POSS,PIS_CH5_CON_SRCS_POSE) + +#define PIS_CH5_CON_MSIGS_POSS 0U +#define PIS_CH5_CON_MSIGS_POSE 3U +#define PIS_CH5_CON_MSIGS_MSK BITS(PIS_CH5_CON_MSIGS_POSS,PIS_CH5_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH6_CON register ************************/ + +#define PIS_CH6_CON_SYNCSEL_POSS 24U +#define PIS_CH6_CON_SYNCSEL_POSE 26U +#define PIS_CH6_CON_SYNCSEL_MSK BITS(PIS_CH6_CON_SYNCSEL_POSS,PIS_CH6_CON_SYNCSEL_POSE) + +#define PIS_CH6_CON_PULCK_POSS 18U +#define PIS_CH6_CON_PULCK_POSE 19U +#define PIS_CH6_CON_PULCK_MSK BITS(PIS_CH6_CON_PULCK_POSS,PIS_CH6_CON_PULCK_POSE) + +#define PIS_CH6_CON_EDGS_POSS 16U +#define PIS_CH6_CON_EDGS_POSE 17U +#define PIS_CH6_CON_EDGS_MSK BITS(PIS_CH6_CON_EDGS_POSS,PIS_CH6_CON_EDGS_POSE) + +#define PIS_CH6_CON_SRCS_POSS 8U +#define PIS_CH6_CON_SRCS_POSE 13U +#define PIS_CH6_CON_SRCS_MSK BITS(PIS_CH6_CON_SRCS_POSS,PIS_CH6_CON_SRCS_POSE) + +#define PIS_CH6_CON_MSIGS_POSS 0U +#define PIS_CH6_CON_MSIGS_POSE 3U +#define PIS_CH6_CON_MSIGS_MSK BITS(PIS_CH6_CON_MSIGS_POSS,PIS_CH6_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH7_CON register ************************/ + +#define PIS_CH7_CON_SYNCSEL_POSS 24U +#define PIS_CH7_CON_SYNCSEL_POSE 26U +#define PIS_CH7_CON_SYNCSEL_MSK BITS(PIS_CH7_CON_SYNCSEL_POSS,PIS_CH7_CON_SYNCSEL_POSE) + +#define PIS_CH7_CON_PULCK_POSS 18U +#define PIS_CH7_CON_PULCK_POSE 19U +#define PIS_CH7_CON_PULCK_MSK BITS(PIS_CH7_CON_PULCK_POSS,PIS_CH7_CON_PULCK_POSE) + +#define PIS_CH7_CON_EDGS_POSS 16U +#define PIS_CH7_CON_EDGS_POSE 17U +#define PIS_CH7_CON_EDGS_MSK BITS(PIS_CH7_CON_EDGS_POSS,PIS_CH7_CON_EDGS_POSE) + +#define PIS_CH7_CON_SRCS_POSS 8U +#define PIS_CH7_CON_SRCS_POSE 13U +#define PIS_CH7_CON_SRCS_MSK BITS(PIS_CH7_CON_SRCS_POSS,PIS_CH7_CON_SRCS_POSE) + +#define PIS_CH7_CON_MSIGS_POSS 0U +#define PIS_CH7_CON_MSIGS_POSE 3U +#define PIS_CH7_CON_MSIGS_MSK BITS(PIS_CH7_CON_MSIGS_POSS,PIS_CH7_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH8_CON register ************************/ + +#define PIS_CH8_CON_SYNCSEL_POSS 24U +#define PIS_CH8_CON_SYNCSEL_POSE 26U +#define PIS_CH8_CON_SYNCSEL_MSK BITS(PIS_CH8_CON_SYNCSEL_POSS,PIS_CH8_CON_SYNCSEL_POSE) + +#define PIS_CH8_CON_PULCK_POSS 18U +#define PIS_CH8_CON_PULCK_POSE 19U +#define PIS_CH8_CON_PULCK_MSK BITS(PIS_CH8_CON_PULCK_POSS,PIS_CH8_CON_PULCK_POSE) + +#define PIS_CH8_CON_EDGS_POSS 16U +#define PIS_CH8_CON_EDGS_POSE 17U +#define PIS_CH8_CON_EDGS_MSK BITS(PIS_CH8_CON_EDGS_POSS,PIS_CH8_CON_EDGS_POSE) + +#define PIS_CH8_CON_SRCS_POSS 8U +#define PIS_CH8_CON_SRCS_POSE 13U +#define PIS_CH8_CON_SRCS_MSK BITS(PIS_CH8_CON_SRCS_POSS,PIS_CH8_CON_SRCS_POSE) + +#define PIS_CH8_CON_MSIGS_POSS 0U +#define PIS_CH8_CON_MSIGS_POSE 3U +#define PIS_CH8_CON_MSIGS_MSK BITS(PIS_CH8_CON_MSIGS_POSS,PIS_CH8_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH9_CON register ************************/ + +#define PIS_CH9_CON_SYNCSEL_POSS 24U +#define PIS_CH9_CON_SYNCSEL_POSE 26U +#define PIS_CH9_CON_SYNCSEL_MSK BITS(PIS_CH9_CON_SYNCSEL_POSS,PIS_CH9_CON_SYNCSEL_POSE) + +#define PIS_CH9_CON_PULCK_POSS 18U +#define PIS_CH9_CON_PULCK_POSE 19U +#define PIS_CH9_CON_PULCK_MSK BITS(PIS_CH9_CON_PULCK_POSS,PIS_CH9_CON_PULCK_POSE) + +#define PIS_CH9_CON_EDGS_POSS 16U +#define PIS_CH9_CON_EDGS_POSE 17U +#define PIS_CH9_CON_EDGS_MSK BITS(PIS_CH9_CON_EDGS_POSS,PIS_CH9_CON_EDGS_POSE) + +#define PIS_CH9_CON_SRCS_POSS 8U +#define PIS_CH9_CON_SRCS_POSE 13U +#define PIS_CH9_CON_SRCS_MSK BITS(PIS_CH9_CON_SRCS_POSS,PIS_CH9_CON_SRCS_POSE) + +#define PIS_CH9_CON_MSIGS_POSS 0U +#define PIS_CH9_CON_MSIGS_POSE 3U +#define PIS_CH9_CON_MSIGS_MSK BITS(PIS_CH9_CON_MSIGS_POSS,PIS_CH9_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH10_CON register ************************/ + +#define PIS_CH10_CON_SYNCSEL_POSS 24U +#define PIS_CH10_CON_SYNCSEL_POSE 26U +#define PIS_CH10_CON_SYNCSEL_MSK BITS(PIS_CH10_CON_SYNCSEL_POSS,PIS_CH10_CON_SYNCSEL_POSE) + +#define PIS_CH10_CON_PULCK_POSS 18U +#define PIS_CH10_CON_PULCK_POSE 19U +#define PIS_CH10_CON_PULCK_MSK BITS(PIS_CH10_CON_PULCK_POSS,PIS_CH10_CON_PULCK_POSE) + +#define PIS_CH10_CON_EDGS_POSS 16U +#define PIS_CH10_CON_EDGS_POSE 17U +#define PIS_CH10_CON_EDGS_MSK BITS(PIS_CH10_CON_EDGS_POSS,PIS_CH10_CON_EDGS_POSE) + +#define PIS_CH10_CON_SRCS_POSS 8U +#define PIS_CH10_CON_SRCS_POSE 13U +#define PIS_CH10_CON_SRCS_MSK BITS(PIS_CH10_CON_SRCS_POSS,PIS_CH10_CON_SRCS_POSE) + +#define PIS_CH10_CON_MSIGS_POSS 0U +#define PIS_CH10_CON_MSIGS_POSE 3U +#define PIS_CH10_CON_MSIGS_MSK BITS(PIS_CH10_CON_MSIGS_POSS,PIS_CH10_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH11_CON register ************************/ + +#define PIS_CH11_CON_SYNCSEL_POSS 24U +#define PIS_CH11_CON_SYNCSEL_POSE 26U +#define PIS_CH11_CON_SYNCSEL_MSK BITS(PIS_CH11_CON_SYNCSEL_POSS,PIS_CH11_CON_SYNCSEL_POSE) + +#define PIS_CH11_CON_PULCK_POSS 18U +#define PIS_CH11_CON_PULCK_POSE 19U +#define PIS_CH11_CON_PULCK_MSK BITS(PIS_CH11_CON_PULCK_POSS,PIS_CH11_CON_PULCK_POSE) + +#define PIS_CH11_CON_EDGS_POSS 16U +#define PIS_CH11_CON_EDGS_POSE 17U +#define PIS_CH11_CON_EDGS_MSK BITS(PIS_CH11_CON_EDGS_POSS,PIS_CH11_CON_EDGS_POSE) + +#define PIS_CH11_CON_SRCS_POSS 8U +#define PIS_CH11_CON_SRCS_POSE 13U +#define PIS_CH11_CON_SRCS_MSK BITS(PIS_CH11_CON_SRCS_POSS,PIS_CH11_CON_SRCS_POSE) + +#define PIS_CH11_CON_MSIGS_POSS 0U +#define PIS_CH11_CON_MSIGS_POSE 3U +#define PIS_CH11_CON_MSIGS_MSK BITS(PIS_CH11_CON_MSIGS_POSS,PIS_CH11_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH12_CON register ************************/ + +#define PIS_CH12_CON_SYNCSEL_POSS 24U +#define PIS_CH12_CON_SYNCSEL_POSE 26U +#define PIS_CH12_CON_SYNCSEL_MSK BITS(PIS_CH12_CON_SYNCSEL_POSS,PIS_CH12_CON_SYNCSEL_POSE) + +#define PIS_CH12_CON_PULCK_POSS 18U +#define PIS_CH12_CON_PULCK_POSE 19U +#define PIS_CH12_CON_PULCK_MSK BITS(PIS_CH12_CON_PULCK_POSS,PIS_CH12_CON_PULCK_POSE) + +#define PIS_CH12_CON_EDGS_POSS 16U +#define PIS_CH12_CON_EDGS_POSE 17U +#define PIS_CH12_CON_EDGS_MSK BITS(PIS_CH12_CON_EDGS_POSS,PIS_CH12_CON_EDGS_POSE) + +#define PIS_CH12_CON_SRCS_POSS 8U +#define PIS_CH12_CON_SRCS_POSE 13U +#define PIS_CH12_CON_SRCS_MSK BITS(PIS_CH12_CON_SRCS_POSS,PIS_CH12_CON_SRCS_POSE) + +#define PIS_CH12_CON_MSIGS_POSS 0U +#define PIS_CH12_CON_MSIGS_POSE 3U +#define PIS_CH12_CON_MSIGS_MSK BITS(PIS_CH12_CON_MSIGS_POSS,PIS_CH12_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH13_CON register ************************/ + +#define PIS_CH13_CON_SYNCSEL_POSS 24U +#define PIS_CH13_CON_SYNCSEL_POSE 26U +#define PIS_CH13_CON_SYNCSEL_MSK BITS(PIS_CH13_CON_SYNCSEL_POSS,PIS_CH13_CON_SYNCSEL_POSE) + +#define PIS_CH13_CON_PULCK_POSS 18U +#define PIS_CH13_CON_PULCK_POSE 19U +#define PIS_CH13_CON_PULCK_MSK BITS(PIS_CH13_CON_PULCK_POSS,PIS_CH13_CON_PULCK_POSE) + +#define PIS_CH13_CON_EDGS_POSS 16U +#define PIS_CH13_CON_EDGS_POSE 17U +#define PIS_CH13_CON_EDGS_MSK BITS(PIS_CH13_CON_EDGS_POSS,PIS_CH13_CON_EDGS_POSE) + +#define PIS_CH13_CON_SRCS_POSS 8U +#define PIS_CH13_CON_SRCS_POSE 13U +#define PIS_CH13_CON_SRCS_MSK BITS(PIS_CH13_CON_SRCS_POSS,PIS_CH13_CON_SRCS_POSE) + +#define PIS_CH13_CON_MSIGS_POSS 0U +#define PIS_CH13_CON_MSIGS_POSE 3U +#define PIS_CH13_CON_MSIGS_MSK BITS(PIS_CH13_CON_MSIGS_POSS,PIS_CH13_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH14_CON register ************************/ + +#define PIS_CH14_CON_SYNCSEL_POSS 24U +#define PIS_CH14_CON_SYNCSEL_POSE 26U +#define PIS_CH14_CON_SYNCSEL_MSK BITS(PIS_CH14_CON_SYNCSEL_POSS,PIS_CH14_CON_SYNCSEL_POSE) + +#define PIS_CH14_CON_PULCK_POSS 18U +#define PIS_CH14_CON_PULCK_POSE 19U +#define PIS_CH14_CON_PULCK_MSK BITS(PIS_CH14_CON_PULCK_POSS,PIS_CH14_CON_PULCK_POSE) + +#define PIS_CH14_CON_EDGS_POSS 16U +#define PIS_CH14_CON_EDGS_POSE 17U +#define PIS_CH14_CON_EDGS_MSK BITS(PIS_CH14_CON_EDGS_POSS,PIS_CH14_CON_EDGS_POSE) + +#define PIS_CH14_CON_SRCS_POSS 8U +#define PIS_CH14_CON_SRCS_POSE 13U +#define PIS_CH14_CON_SRCS_MSK BITS(PIS_CH14_CON_SRCS_POSS,PIS_CH14_CON_SRCS_POSE) + +#define PIS_CH14_CON_MSIGS_POSS 0U +#define PIS_CH14_CON_MSIGS_POSE 3U +#define PIS_CH14_CON_MSIGS_MSK BITS(PIS_CH14_CON_MSIGS_POSS,PIS_CH14_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH15_CON register ************************/ + +#define PIS_CH15_CON_SYNCSEL_POSS 24U +#define PIS_CH15_CON_SYNCSEL_POSE 26U +#define PIS_CH15_CON_SYNCSEL_MSK BITS(PIS_CH15_CON_SYNCSEL_POSS,PIS_CH15_CON_SYNCSEL_POSE) + +#define PIS_CH15_CON_PULCK_POSS 18U +#define PIS_CH15_CON_PULCK_POSE 19U +#define PIS_CH15_CON_PULCK_MSK BITS(PIS_CH15_CON_PULCK_POSS,PIS_CH15_CON_PULCK_POSE) + +#define PIS_CH15_CON_EDGS_POSS 16U +#define PIS_CH15_CON_EDGS_POSE 17U +#define PIS_CH15_CON_EDGS_MSK BITS(PIS_CH15_CON_EDGS_POSS,PIS_CH15_CON_EDGS_POSE) + +#define PIS_CH15_CON_SRCS_POSS 8U +#define PIS_CH15_CON_SRCS_POSE 13U +#define PIS_CH15_CON_SRCS_MSK BITS(PIS_CH15_CON_SRCS_POSS,PIS_CH15_CON_SRCS_POSE) + +#define PIS_CH15_CON_MSIGS_POSS 0U +#define PIS_CH15_CON_MSIGS_POSE 3U +#define PIS_CH15_CON_MSIGS_MSK BITS(PIS_CH15_CON_MSIGS_POSS,PIS_CH15_CON_MSIGS_POSE) + +/****************** Bit definition for PIS_CH_OER register ************************/ + +#define PIS_CH_OER_CH3OE_POS 3U +#define PIS_CH_OER_CH3OE_MSK BIT(PIS_CH_OER_CH3OE_POS) + +#define PIS_CH_OER_CH2OE_POS 2U +#define PIS_CH_OER_CH2OE_MSK BIT(PIS_CH_OER_CH2OE_POS) + +#define PIS_CH_OER_CH1OE_POS 1U +#define PIS_CH_OER_CH1OE_MSK BIT(PIS_CH_OER_CH1OE_POS) + +#define PIS_CH_OER_CH0OE_POS 0U +#define PIS_CH_OER_CH0OE_MSK BIT(PIS_CH_OER_CH0OE_POS) + +/****************** Bit definition for PIS_TAR_CON0 register ************************/ + +#define PIS_TAR_CON0_TIM3_CH4IN_SEL_POS 27U +#define PIS_TAR_CON0_TIM3_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH3IN_SEL_POS 26U +#define PIS_TAR_CON0_TIM3_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH2IN_SEL_POS 25U +#define PIS_TAR_CON0_TIM3_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM3_CH1IN_SEL_POS 24U +#define PIS_TAR_CON0_TIM3_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM3_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH4IN_SEL_POS 19U +#define PIS_TAR_CON0_TIM2_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH3IN_SEL_POS 18U +#define PIS_TAR_CON0_TIM2_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH2IN_SEL_POS 17U +#define PIS_TAR_CON0_TIM2_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM2_CH1IN_SEL_POS 16U +#define PIS_TAR_CON0_TIM2_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM2_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_BRKIN_SEL_POS 12U +#define PIS_TAR_CON0_TIM1_BRKIN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_BRKIN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_CH4IN_SEL_POS 11U +#define PIS_TAR_CON0_TIM1_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_CH3IN_SEL_POS 10U +#define PIS_TAR_CON0_TIM1_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_CH2IN_SEL_POS 9U +#define PIS_TAR_CON0_TIM1_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM1_CH1IN_SEL_POS 8U +#define PIS_TAR_CON0_TIM1_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM1_CH1IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_BRKIN_SEL_POS 4U +#define PIS_TAR_CON0_TIM0_BRKIN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_BRKIN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH4IN_SEL_POS 3U +#define PIS_TAR_CON0_TIM0_CH4IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH4IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH3IN_SEL_POS 2U +#define PIS_TAR_CON0_TIM0_CH3IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH3IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH2IN_SEL_POS 1U +#define PIS_TAR_CON0_TIM0_CH2IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH2IN_SEL_POS) + +#define PIS_TAR_CON0_TIM0_CH1IN_SEL_POS 0U +#define PIS_TAR_CON0_TIM0_CH1IN_SEL_MSK BIT(PIS_TAR_CON0_TIM0_CH1IN_SEL_POS) + +/****************** Bit definition for PIS_TAR_CON1 register ************************/ + +#define PIS_TAR_CON1_SPI1_CLK_SEL_POS 15U +#define PIS_TAR_CON1_SPI1_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI1_CLK_SEL_POS) + +#define PIS_TAR_CON1_SPI1_RX_SEL_POS 14U +#define PIS_TAR_CON1_SPI1_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI1_RX_SEL_POS) + +#define PIS_TAR_CON1_SPI0_CLK_SEL_POS 13U +#define PIS_TAR_CON1_SPI0_CLK_SEL_MSK BIT(PIS_TAR_CON1_SPI0_CLK_SEL_POS) + +#define PIS_TAR_CON1_SPI0_RX_SEL_POS 12U +#define PIS_TAR_CON1_SPI0_RX_SEL_MSK BIT(PIS_TAR_CON1_SPI0_RX_SEL_POS) + +#define PIS_TAR_CON1_LPUART0_RXD_SEL_POS 8U +#define PIS_TAR_CON1_LPUART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_LPUART0_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART5_RXD_SEL_POS 7U +#define PIS_TAR_CON1_UART5_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART5_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART4_RXD_SEL_POS 6U +#define PIS_TAR_CON1_UART4_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART4_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART3_RXD_SEL_POS 3U +#define PIS_TAR_CON1_UART3_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART3_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART2_RXD_SEL_POS 2U +#define PIS_TAR_CON1_UART2_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART2_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART1_RXD_SEL_POS 1U +#define PIS_TAR_CON1_UART1_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART1_RXD_SEL_POS) + +#define PIS_TAR_CON1_UART0_RXD_SEL_POS 0U +#define PIS_TAR_CON1_UART0_RXD_SEL_MSK BIT(PIS_TAR_CON1_UART0_RXD_SEL_POS) + +/****************** Bit definition for PIS_UART0_TXMCR register ************************/ + +#define PIS_UART0_TXMCR_TXMLVLS_POS 8U +#define PIS_UART0_TXMCR_TXMLVLS_MSK BIT(PIS_UART0_TXMCR_TXMLVLS_POS) + +#define PIS_UART0_TXMCR_TXMSS_POSS 4U +#define PIS_UART0_TXMCR_TXMSS_POSE 7U +#define PIS_UART0_TXMCR_TXMSS_MSK BITS(PIS_UART0_TXMCR_TXMSS_POSS,PIS_UART0_TXMCR_TXMSS_POSE) + +#define PIS_UART0_TXMCR_TXSIGS_POSS 0U +#define PIS_UART0_TXMCR_TXSIGS_POSE 3U +#define PIS_UART0_TXMCR_TXSIGS_MSK BITS(PIS_UART0_TXMCR_TXSIGS_POSS,PIS_UART0_TXMCR_TXSIGS_POSE) + +/****************** Bit definition for PIS_UART1_TXMCR register ************************/ + +#define PIS_UART1_TXMCR_TXMLVLS_POS 8U +#define PIS_UART1_TXMCR_TXMLVLS_MSK BIT(PIS_UART1_TXMCR_TXMLVLS_POS) + +#define PIS_UART1_TXMCR_TXMSS_POSS 4U +#define PIS_UART1_TXMCR_TXMSS_POSE 7U +#define PIS_UART1_TXMCR_TXMSS_MSK BITS(PIS_UART1_TXMCR_TXMSS_POSS,PIS_UART1_TXMCR_TXMSS_POSE) + +#define PIS_UART1_TXMCR_TXSIGS_POSS 0U +#define PIS_UART1_TXMCR_TXSIGS_POSE 3U +#define PIS_UART1_TXMCR_TXSIGS_MSK BITS(PIS_UART1_TXMCR_TXSIGS_POSS,PIS_UART1_TXMCR_TXSIGS_POSE) + +/****************** Bit definition for PIS_UART2_TXMCR register ************************/ + +#define PIS_UART2_TXMCR_TXMLVLS_POS 8U +#define PIS_UART2_TXMCR_TXMLVLS_MSK BIT(PIS_UART2_TXMCR_TXMLVLS_POS) + +#define PIS_UART2_TXMCR_TXMSS_POSS 4U +#define PIS_UART2_TXMCR_TXMSS_POSE 7U +#define PIS_UART2_TXMCR_TXMSS_MSK BITS(PIS_UART2_TXMCR_TXMSS_POSS,PIS_UART2_TXMCR_TXMSS_POSE) + +#define PIS_UART2_TXMCR_TXSIGS_POSS 0U +#define PIS_UART2_TXMCR_TXSIGS_POSE 3U +#define PIS_UART2_TXMCR_TXSIGS_MSK BITS(PIS_UART2_TXMCR_TXSIGS_POSS,PIS_UART2_TXMCR_TXSIGS_POSE) + +/****************** Bit definition for PIS_UART3_TXMCR register ************************/ + +#define PIS_UART3_TXMCR_TXMLVLS_POS 8U +#define PIS_UART3_TXMCR_TXMLVLS_MSK BIT(PIS_UART3_TXMCR_TXMLVLS_POS) + +#define PIS_UART3_TXMCR_TXMSS_POSS 4U +#define PIS_UART3_TXMCR_TXMSS_POSE 7U +#define PIS_UART3_TXMCR_TXMSS_MSK BITS(PIS_UART3_TXMCR_TXMSS_POSS,PIS_UART3_TXMCR_TXMSS_POSE) + +#define PIS_UART3_TXMCR_TXSIGS_POSS 0U +#define PIS_UART3_TXMCR_TXSIGS_POSE 3U +#define PIS_UART3_TXMCR_TXSIGS_MSK BITS(PIS_UART3_TXMCR_TXSIGS_POSS,PIS_UART3_TXMCR_TXSIGS_POSE) + +/****************** Bit definition for PIS_LPUART0_TXMCR register ************************/ + +#define PIS_LPUART0_TXMCR_TXMLVLS_POS 8U +#define PIS_LPUART0_TXMCR_TXMLVLS_MSK BIT(PIS_LPUART0_TXMCR_TXMLVLS_POS) + +#define PIS_LPUART0_TXMCR_TXMSS_POSS 4U +#define PIS_LPUART0_TXMCR_TXMSS_POSE 7U +#define PIS_LPUART0_TXMCR_TXMSS_MSK BITS(PIS_LPUART0_TXMCR_TXMSS_POSS,PIS_LPUART0_TXMCR_TXMSS_POSE) + +#define PIS_LPUART0_TXMCR_TXSIGS_POSS 0U +#define PIS_LPUART0_TXMCR_TXSIGS_POSE 3U +#define PIS_LPUART0_TXMCR_TXSIGS_MSK BITS(PIS_LPUART0_TXMCR_TXSIGS_POSS,PIS_LPUART0_TXMCR_TXSIGS_POSE) + +typedef struct +{ + __IO uint32_t CH_CON[16]; + __IO uint32_t CH_OER; + __IO uint32_t TAR_CON0; + __IO uint32_t TAR_CON1; + uint32_t RESERVED0[5] ; + __IO uint32_t UART0_TXMCR; + __IO uint32_t UART1_TXMCR; + __IO uint32_t UART2_TXMCR; + __IO uint32_t UART3_TXMCR; + __IO uint32_t LPUART0_TXMCR; +} PIS_TypeDef; + + +/****************** Bit definition for GPIO_DIN register ************************/ + +#define GPIO_DIN_DIN_POSS 0U +#define GPIO_DIN_DIN_POSE 15U +#define GPIO_DIN_DIN_MSK BITS(GPIO_DIN_DIN_POSS,GPIO_DIN_DIN_POSE) + +/****************** Bit definition for GPIO_DOUT register ************************/ + +#define GPIO_DOUT_DOUT_POSS 0U +#define GPIO_DOUT_DOUT_POSE 15U +#define GPIO_DOUT_DOUT_MSK BITS(GPIO_DOUT_DOUT_POSS,GPIO_DOUT_DOUT_POSE) + +/****************** Bit definition for GPIO_BSRR register ************************/ + +#define GPIO_BSRR_BRR_POSS 16U +#define GPIO_BSRR_BRR_POSE 31U +#define GPIO_BSRR_BRR_MSK BITS(GPIO_BSRR_BRR_POSS,GPIO_BSRR_BRR_POSE) + +#define GPIO_BSRR_BSR_POSS 0U +#define GPIO_BSRR_BSR_POSE 15U +#define GPIO_BSRR_BSR_MSK BITS(GPIO_BSRR_BSR_POSS,GPIO_BSRR_BSR_POSE) + +/****************** Bit definition for GPIO_BIR register ************************/ + +#define GPIO_BIR_BIR_POSS 0U +#define GPIO_BIR_BIR_POSE 15U +#define GPIO_BIR_BIR_MSK BITS(GPIO_BIR_BIR_POSS,GPIO_BIR_BIR_POSE) + +/****************** Bit definition for GPIO_MODE register ************************/ + +#define GPIO_MODE_MODE_POSS 0U +#define GPIO_MODE_MODE_POSE 31U +#define GPIO_MODE_MODE_MSK BITS(GPIO_MODE_MODE_POSS,GPIO_MODE_MODE_POSE) + +/****************** Bit definition for GPIO_ODOS register ************************/ + +#define GPIO_ODOS_ODOS_POSS 0U +#define GPIO_ODOS_ODOS_POSE 31U +#define GPIO_ODOS_ODOS_MSK BITS(GPIO_ODOS_ODOS_POSS,GPIO_ODOS_ODOS_POSE) + +/****************** Bit definition for GPIO_PUPD register ************************/ + +#define GPIO_PUPD_PUPD_POSS 0U +#define GPIO_PUPD_PUPD_POSE 31U +#define GPIO_PUPD_PUPD_MSK BITS(GPIO_PUPD_PUPD_POSS,GPIO_PUPD_PUPD_POSE) + +/****************** Bit definition for GPIO_PODRV register ************************/ + +#define GPIO_PODRV_PODRV_POSS 0U +#define GPIO_PODRV_PODRV_POSE 31U +#define GPIO_PODRV_PODRV_MSK BITS(GPIO_PODRV_PODRV_POSS,GPIO_PODRV_PODRV_POSE) + +/****************** Bit definition for GPIO_NODRV register ************************/ + +#define GPIO_NODRV_NODRV_POSS 0U +#define GPIO_NODRV_NODRV_POSE 31U +#define GPIO_NODRV_NODRV_MSK BITS(GPIO_NODRV_NODRV_POSS,GPIO_NODRV_NODRV_POSE) + +/****************** Bit definition for GPIO_FLT register ************************/ + +#define GPIO_FLT_FLT_POSS 0U +#define GPIO_FLT_FLT_POSE 15U +#define GPIO_FLT_FLT_MSK BITS(GPIO_FLT_FLT_POSS,GPIO_FLT_FLT_POSE) + +/****************** Bit definition for GPIO_TYPE register ************************/ + +#define GPIO_TYPE_TYPE_POSS 0U +#define GPIO_TYPE_TYPE_POSE 15U +#define GPIO_TYPE_TYPE_MSK BITS(GPIO_TYPE_TYPE_POSS,GPIO_TYPE_TYPE_POSE) + +/****************** Bit definition for GPIO_FUNC0 register ************************/ + +#define GPIO_FUNC0_FSEL_IO7_POSS 28U +#define GPIO_FUNC0_FSEL_IO7_POSE 31U +#define GPIO_FUNC0_FSEL_IO7_MSK BITS(GPIO_FUNC0_FSEL_IO7_POSS,GPIO_FUNC0_FSEL_IO7_POSE) + +#define GPIO_FUNC0_FSEL_IO6_POSS 24U +#define GPIO_FUNC0_FSEL_IO6_POSE 27U +#define GPIO_FUNC0_FSEL_IO6_MSK BITS(GPIO_FUNC0_FSEL_IO6_POSS,GPIO_FUNC0_FSEL_IO6_POSE) + +#define GPIO_FUNC0_FSEL_IO5_POSS 20U +#define GPIO_FUNC0_FSEL_IO5_POSE 23U +#define GPIO_FUNC0_FSEL_IO5_MSK BITS(GPIO_FUNC0_FSEL_IO5_POSS,GPIO_FUNC0_FSEL_IO5_POSE) + +#define GPIO_FUNC0_FSEL_IO4_POSS 16U +#define GPIO_FUNC0_FSEL_IO4_POSE 19U +#define GPIO_FUNC0_FSEL_IO4_MSK BITS(GPIO_FUNC0_FSEL_IO4_POSS,GPIO_FUNC0_FSEL_IO4_POSE) + +#define GPIO_FUNC0_FSEL_IO3_POSS 12U +#define GPIO_FUNC0_FSEL_IO3_POSE 15U +#define GPIO_FUNC0_FSEL_IO3_MSK BITS(GPIO_FUNC0_FSEL_IO3_POSS,GPIO_FUNC0_FSEL_IO3_POSE) + +#define GPIO_FUNC0_FSEL_IO2_POSS 8U +#define GPIO_FUNC0_FSEL_IO2_POSE 11U +#define GPIO_FUNC0_FSEL_IO2_MSK BITS(GPIO_FUNC0_FSEL_IO2_POSS,GPIO_FUNC0_FSEL_IO2_POSE) + +#define GPIO_FUNC0_FSEL_IO1_POSS 4U +#define GPIO_FUNC0_FSEL_IO1_POSE 7U +#define GPIO_FUNC0_FSEL_IO1_MSK BITS(GPIO_FUNC0_FSEL_IO1_POSS,GPIO_FUNC0_FSEL_IO1_POSE) + +#define GPIO_FUNC0_FSEL_IO0_POSS 0U +#define GPIO_FUNC0_FSEL_IO0_POSE 3U +#define GPIO_FUNC0_FSEL_IO0_MSK BITS(GPIO_FUNC0_FSEL_IO0_POSS,GPIO_FUNC0_FSEL_IO0_POSE) + +/****************** Bit definition for GPIO_FUNC1 register ************************/ + +#define GPIO_FUNC1_FSEL_IO15_POSS 28U +#define GPIO_FUNC1_FSEL_IO15_POSE 31U +#define GPIO_FUNC1_FSEL_IO15_MSK BITS(GPIO_FUNC1_FSEL_IO15_POSS,GPIO_FUNC1_FSEL_IO15_POSE) + +#define GPIO_FUNC1_FSEL_IO14_POSS 24U +#define GPIO_FUNC1_FSEL_IO14_POSE 27U +#define GPIO_FUNC1_FSEL_IO14_MSK BITS(GPIO_FUNC1_FSEL_IO14_POSS,GPIO_FUNC1_FSEL_IO14_POSE) + +#define GPIO_FUNC1_FSEL_IO13_POSS 20U +#define GPIO_FUNC1_FSEL_IO13_POSE 23U +#define GPIO_FUNC1_FSEL_IO13_MSK BITS(GPIO_FUNC1_FSEL_IO13_POSS,GPIO_FUNC1_FSEL_IO13_POSE) + +#define GPIO_FUNC1_FSEL_IO12_POSS 16U +#define GPIO_FUNC1_FSEL_IO12_POSE 19U +#define GPIO_FUNC1_FSEL_IO12_MSK BITS(GPIO_FUNC1_FSEL_IO12_POSS,GPIO_FUNC1_FSEL_IO12_POSE) + +#define GPIO_FUNC1_FSEL_IO11_POSS 12U +#define GPIO_FUNC1_FSEL_IO11_POSE 15U +#define GPIO_FUNC1_FSEL_IO11_MSK BITS(GPIO_FUNC1_FSEL_IO11_POSS,GPIO_FUNC1_FSEL_IO11_POSE) + +#define GPIO_FUNC1_FSEL_IO10_POSS 8U +#define GPIO_FUNC1_FSEL_IO10_POSE 11U +#define GPIO_FUNC1_FSEL_IO10_MSK BITS(GPIO_FUNC1_FSEL_IO10_POSS,GPIO_FUNC1_FSEL_IO10_POSE) + +#define GPIO_FUNC1_FSEL_IO9_POSS 4U +#define GPIO_FUNC1_FSEL_IO9_POSE 7U +#define GPIO_FUNC1_FSEL_IO9_MSK BITS(GPIO_FUNC1_FSEL_IO9_POSS,GPIO_FUNC1_FSEL_IO9_POSE) + +#define GPIO_FUNC1_FSEL_IO8_POSS 0U +#define GPIO_FUNC1_FSEL_IO8_POSE 3U +#define GPIO_FUNC1_FSEL_IO8_MSK BITS(GPIO_FUNC1_FSEL_IO8_POSS,GPIO_FUNC1_FSEL_IO8_POSE) + +/****************** Bit definition for GPIO_LOCK register ************************/ + +#define GPIO_LOCK_KEY_POSS 16U +#define GPIO_LOCK_KEY_POSE 31U +#define GPIO_LOCK_KEY_MSK BITS(GPIO_LOCK_KEY_POSS,GPIO_LOCK_KEY_POSE) + +#define GPIO_LOCK_LOCK_POSS 0U +#define GPIO_LOCK_LOCK_POSE 15U +#define GPIO_LOCK_LOCK_MSK BITS(GPIO_LOCK_LOCK_POSS,GPIO_LOCK_LOCK_POSE) + +typedef struct +{ + __I uint32_t DIN; + __IO uint32_t DOUT; + __O uint32_t BSRR; + __O uint32_t BIR; + __IO uint32_t MODE; + __IO uint32_t ODOS; + __IO uint32_t PUPD; + __IO uint32_t PODRV; + __IO uint32_t NODRV; + __IO uint32_t FLT; + __IO uint32_t TYPE; + __IO uint32_t FUNC0; + __IO uint32_t FUNC1; + __IO uint32_t LOCK; +} GPIO_TypeDef; + +/****************** Bit definition for GPIO_EXTIRER register ************************/ + +#define GPIO_EXTIRER_EXTIRER_POSS 0U +#define GPIO_EXTIRER_EXTIRER_POSE 15U +#define GPIO_EXTIRER_EXTIRER_MSK BITS(GPIO_EXTIRER_EXTIRER_POSS,GPIO_EXTIRER_EXTIRER_POSE) + +/****************** Bit definition for GPIO_EXTIFER register ************************/ + +#define GPIO_EXTIFER_EXTIFER_POSS 0U +#define GPIO_EXTIFER_EXTIFER_POSE 15U +#define GPIO_EXTIFER_EXTIFER_MSK BITS(GPIO_EXTIFER_EXTIFER_POSS,GPIO_EXTIFER_EXTIFER_POSE) + +/****************** Bit definition for GPIO_EXTIEN register ************************/ + +#define GPIO_EXTIEN_EXTIEN_POSS 0U +#define GPIO_EXTIEN_EXTIEN_POSE 15U +#define GPIO_EXTIEN_EXTIEN_MSK BITS(GPIO_EXTIEN_EXTIEN_POSS,GPIO_EXTIEN_EXTIEN_POSE) + +/****************** Bit definition for GPIO_EXTIFLAG register ************************/ + +#define GPIO_EXTIFLAG_EXTIFLAG_POSS 0U +#define GPIO_EXTIFLAG_EXTIFLAG_POSE 15U +#define GPIO_EXTIFLAG_EXTIFLAG_MSK BITS(GPIO_EXTIFLAG_EXTIFLAG_POSS,GPIO_EXTIFLAG_EXTIFLAG_POSE) + +/****************** Bit definition for GPIO_EXTISFR register ************************/ + +#define GPIO_EXTISFR_EXTISFR_POSS 0U +#define GPIO_EXTISFR_EXTISFR_POSE 15U +#define GPIO_EXTISFR_EXTISFR_MSK BITS(GPIO_EXTISFR_EXTISFR_POSS,GPIO_EXTISFR_EXTISFR_POSE) + +/****************** Bit definition for GPIO_EXTICFR register ************************/ + +#define GPIO_EXTICFR_EXTICFR_POSS 0U +#define GPIO_EXTICFR_EXTICFR_POSE 15U +#define GPIO_EXTICFR_EXTICFR_MSK BITS(GPIO_EXTICFR_EXTICFR_POSS,GPIO_EXTICFR_EXTICFR_POSE) + +/****************** Bit definition for GPIO_EXTIPSR0 register ************************/ + +#define GPIO_EXTIPSR0_EXTIS7_POSS 28U +#define GPIO_EXTIPSR0_EXTIS7_POSE 30U +#define GPIO_EXTIPSR0_EXTIS7_MSK BITS(GPIO_EXTIPSR0_EXTIS7_POSS,GPIO_EXTIPSR0_EXTIS7_POSE) + +#define GPIO_EXTIPSR0_EXTIS6_POSS 24U +#define GPIO_EXTIPSR0_EXTIS6_POSE 26U +#define GPIO_EXTIPSR0_EXTIS6_MSK BITS(GPIO_EXTIPSR0_EXTIS6_POSS,GPIO_EXTIPSR0_EXTIS6_POSE) + +#define GPIO_EXTIPSR0_EXTIS5_POSS 20U +#define GPIO_EXTIPSR0_EXTIS5_POSE 22U +#define GPIO_EXTIPSR0_EXTIS5_MSK BITS(GPIO_EXTIPSR0_EXTIS5_POSS,GPIO_EXTIPSR0_EXTIS5_POSE) + +#define GPIO_EXTIPSR0_EXTIS4_POSS 16U +#define GPIO_EXTIPSR0_EXTIS4_POSE 18U +#define GPIO_EXTIPSR0_EXTIS4_MSK BITS(GPIO_EXTIPSR0_EXTIS4_POSS,GPIO_EXTIPSR0_EXTIS4_POSE) + +#define GPIO_EXTIPSR0_EXTIS3_POSS 12U +#define GPIO_EXTIPSR0_EXTIS3_POSE 14U +#define GPIO_EXTIPSR0_EXTIS3_MSK BITS(GPIO_EXTIPSR0_EXTIS3_POSS,GPIO_EXTIPSR0_EXTIS3_POSE) + +#define GPIO_EXTIPSR0_EXTIS2_POSS 8U +#define GPIO_EXTIPSR0_EXTIS2_POSE 10U +#define GPIO_EXTIPSR0_EXTIS2_MSK BITS(GPIO_EXTIPSR0_EXTIS2_POSS,GPIO_EXTIPSR0_EXTIS2_POSE) + +#define GPIO_EXTIPSR0_EXTIS1_POSS 4U +#define GPIO_EXTIPSR0_EXTIS1_POSE 6U +#define GPIO_EXTIPSR0_EXTIS1_MSK BITS(GPIO_EXTIPSR0_EXTIS1_POSS,GPIO_EXTIPSR0_EXTIS1_POSE) + +#define GPIO_EXTIPSR0_EXTIS0_POSS 0U +#define GPIO_EXTIPSR0_EXTIS0_POSE 2U +#define GPIO_EXTIPSR0_EXTIS0_MSK BITS(GPIO_EXTIPSR0_EXTIS0_POSS,GPIO_EXTIPSR0_EXTIS0_POSE) + +/****************** Bit definition for GPIO_EXTIPSR1 register ************************/ + +#define GPIO_EXTIPSR1_EXTIS15_POSS 28U +#define GPIO_EXTIPSR1_EXTIS15_POSE 30U +#define GPIO_EXTIPSR1_EXTIS15_MSK BITS(GPIO_EXTIPSR1_EXTIS15_POSS,GPIO_EXTIPSR1_EXTIS15_POSE) + +#define GPIO_EXTIPSR1_EXTIS14_POSS 24U +#define GPIO_EXTIPSR1_EXTIS14_POSE 26U +#define GPIO_EXTIPSR1_EXTIS14_MSK BITS(GPIO_EXTIPSR1_EXTIS14_POSS,GPIO_EXTIPSR1_EXTIS14_POSE) + +#define GPIO_EXTIPSR1_EXTIS13_POSS 20U +#define GPIO_EXTIPSR1_EXTIS13_POSE 22U +#define GPIO_EXTIPSR1_EXTIS13_MSK BITS(GPIO_EXTIPSR1_EXTIS13_POSS,GPIO_EXTIPSR1_EXTIS13_POSE) + +#define GPIO_EXTIPSR1_EXTIS12_POSS 16U +#define GPIO_EXTIPSR1_EXTIS12_POSE 18U +#define GPIO_EXTIPSR1_EXTIS12_MSK BITS(GPIO_EXTIPSR1_EXTIS12_POSS,GPIO_EXTIPSR1_EXTIS12_POSE) + +#define GPIO_EXTIPSR1_EXTIS11_POSS 12U +#define GPIO_EXTIPSR1_EXTIS11_POSE 14U +#define GPIO_EXTIPSR1_EXTIS11_MSK BITS(GPIO_EXTIPSR1_EXTIS11_POSS,GPIO_EXTIPSR1_EXTIS11_POSE) + +#define GPIO_EXTIPSR1_EXTIS10_POSS 8U +#define GPIO_EXTIPSR1_EXTIS10_POSE 10U +#define GPIO_EXTIPSR1_EXTIS10_MSK BITS(GPIO_EXTIPSR1_EXTIS10_POSS,GPIO_EXTIPSR1_EXTIS10_POSE) + +#define GPIO_EXTIPSR1_EXTIS9_POSS 4U +#define GPIO_EXTIPSR1_EXTIS9_POSE 6U +#define GPIO_EXTIPSR1_EXTIS9_MSK BITS(GPIO_EXTIPSR1_EXTIS9_POSS,GPIO_EXTIPSR1_EXTIS9_POSE) + +#define GPIO_EXTIPSR1_EXTIS8_POSS 0U +#define GPIO_EXTIPSR1_EXTIS8_POSE 2U +#define GPIO_EXTIPSR1_EXTIS8_MSK BITS(GPIO_EXTIPSR1_EXTIS8_POSS,GPIO_EXTIPSR1_EXTIS8_POSE) + +/****************** Bit definition for GPIO_EXTIFLTCR register ************************/ + +#define GPIO_EXTIFLTCR_FLTCKS_POSS 24U +#define GPIO_EXTIFLTCR_FLTCKS_POSE 25U +#define GPIO_EXTIFLTCR_FLTCKS_MSK BITS(GPIO_EXTIFLTCR_FLTCKS_POSS,GPIO_EXTIFLTCR_FLTCKS_POSE) + +#define GPIO_EXTIFLTCR_FLTSEL_POSS 16U +#define GPIO_EXTIFLTCR_FLTSEL_POSE 23U +#define GPIO_EXTIFLTCR_FLTSEL_MSK BITS(GPIO_EXTIFLTCR_FLTSEL_POSS,GPIO_EXTIFLTCR_FLTSEL_POSE) + +#define GPIO_EXTIFLTCR_FLTEN_POSS 0U +#define GPIO_EXTIFLTCR_FLTEN_POSE 15U +#define GPIO_EXTIFLTCR_FLTEN_MSK BITS(GPIO_EXTIFLTCR_FLTEN_POSS,GPIO_EXTIFLTCR_FLTEN_POSE) + +typedef struct +{ + __IO uint32_t EXTIRER; + uint32_t RESERVED0 ; + __IO uint32_t EXTIFER; + uint32_t RESERVED1 ; + __IO uint32_t EXTIEN; + uint32_t RESERVED2 ; + __I uint32_t EXTIFLAG; + uint32_t RESERVED3 ; + __O uint32_t EXTISFR; + uint32_t RESERVED4 ; + __O uint32_t EXTICFR; + uint32_t RESERVED5 ; + __IO uint32_t EXTIPSR0; + __IO uint32_t EXTIPSR1; + uint32_t RESERVED6[2] ; + __IO uint32_t EXTIFLTCR; +} EXTI_TypeDef; + +/****************** Bit definition for RTC_WPR register ************************/ + +#define RTC_WPR_WP_POS 0U +#define RTC_WPR_WP_MSK BIT(RTC_WPR_WP_POS) + +/****************** Bit definition for RTC_CON register ************************/ + +#define RTC_CON_SSEC_POS 25U +#define RTC_CON_SSEC_MSK BIT(RTC_CON_SSEC_POS) + +#define RTC_CON_BUSY_POS 24U +#define RTC_CON_BUSY_MSK BIT(RTC_CON_BUSY_POS) + +#define RTC_CON_POL_POS 22U +#define RTC_CON_POL_MSK BIT(RTC_CON_POL_POS) + +#define RTC_CON_EOS_POSS 20U +#define RTC_CON_EOS_POSE 21U +#define RTC_CON_EOS_MSK BITS(RTC_CON_EOS_POSS,RTC_CON_EOS_POSE) + +#define RTC_CON_CKOS_POSS 17U +#define RTC_CON_CKOS_POSE 19U +#define RTC_CON_CKOS_MSK BITS(RTC_CON_CKOS_POSS,RTC_CON_CKOS_POSE) + +#define RTC_CON_CKOE_POS 16U +#define RTC_CON_CKOE_MSK BIT(RTC_CON_CKOE_POS) + +#define RTC_CON_WUCKS_POSS 13U +#define RTC_CON_WUCKS_POSE 15U +#define RTC_CON_WUCKS_MSK BITS(RTC_CON_WUCKS_POSS,RTC_CON_WUCKS_POSE) + +#define RTC_CON_WUTE_POS 12U +#define RTC_CON_WUTE_MSK BIT(RTC_CON_WUTE_POS) + +#define RTC_CON_DSTS_POS 10U +#define RTC_CON_DSTS_MSK BIT(RTC_CON_DSTS_POS) + +#define RTC_CON_SUB1H_POS 9U +#define RTC_CON_SUB1H_MSK BIT(RTC_CON_SUB1H_POS) + +#define RTC_CON_ADD1H_POS 8U +#define RTC_CON_ADD1H_MSK BIT(RTC_CON_ADD1H_POS) + +#define RTC_CON_TSPIN_POS 7U +#define RTC_CON_TSPIN_MSK BIT(RTC_CON_TSPIN_POS) + +#define RTC_CON_TSSEL_POS 6U +#define RTC_CON_TSSEL_MSK BIT(RTC_CON_TSSEL_POS) + +#define RTC_CON_TSEN_POS 5U +#define RTC_CON_TSEN_MSK BIT(RTC_CON_TSEN_POS) + +#define RTC_CON_SHDBP_POS 4U +#define RTC_CON_SHDBP_MSK BIT(RTC_CON_SHDBP_POS) + +#define RTC_CON_HFM_POS 3U +#define RTC_CON_HFM_MSK BIT(RTC_CON_HFM_POS) + +#define RTC_CON_ALMBEN_POS 2U +#define RTC_CON_ALMBEN_MSK BIT(RTC_CON_ALMBEN_POS) + +#define RTC_CON_ALMAEN_POS 1U +#define RTC_CON_ALMAEN_MSK BIT(RTC_CON_ALMAEN_POS) + +#define RTC_CON_GO_POS 0U +#define RTC_CON_GO_MSK BIT(RTC_CON_GO_POS) + +/****************** Bit definition for RTC_PSR register ************************/ + +#define RTC_PSR_APRS_POSS 16U +#define RTC_PSR_APRS_POSE 22U +#define RTC_PSR_APRS_MSK BITS(RTC_PSR_APRS_POSS,RTC_PSR_APRS_POSE) + +#define RTC_PSR_SPRS_POSS 0U +#define RTC_PSR_SPRS_POSE 14U +#define RTC_PSR_SPRS_MSK BITS(RTC_PSR_SPRS_POSS,RTC_PSR_SPRS_POSE) + +/****************** Bit definition for RTC_TAMPCON register ************************/ + +#define RTC_TAMPCON_TAMPFLT_POSS 20U +#define RTC_TAMPCON_TAMPFLT_POSE 21U +#define RTC_TAMPCON_TAMPFLT_MSK BITS(RTC_TAMPCON_TAMPFLT_POSS,RTC_TAMPCON_TAMPFLT_POSE) + +#define RTC_TAMPCON_TAMPCKS_POSS 17U +#define RTC_TAMPCON_TAMPCKS_POSE 19U +#define RTC_TAMPCON_TAMPCKS_MSK BITS(RTC_TAMPCON_TAMPCKS_POSS,RTC_TAMPCON_TAMPCKS_POSE) + +#define RTC_TAMPCON_TAMPTS_POS 16U +#define RTC_TAMPCON_TAMPTS_MSK BIT(RTC_TAMPCON_TAMPTS_POS) + +#define RTC_TAMPCON_TAMP1LV_POS 9U +#define RTC_TAMPCON_TAMP1LV_MSK BIT(RTC_TAMPCON_TAMP1LV_POS) + +#define RTC_TAMPCON_TAMP1EN_POS 8U +#define RTC_TAMPCON_TAMP1EN_MSK BIT(RTC_TAMPCON_TAMP1EN_POS) + +#define RTC_TAMPCON_TAMP0LV_POS 1U +#define RTC_TAMPCON_TAMP0LV_MSK BIT(RTC_TAMPCON_TAMP0LV_POS) + +#define RTC_TAMPCON_TAMP0EN_POS 0U +#define RTC_TAMPCON_TAMP0EN_MSK BIT(RTC_TAMPCON_TAMP0EN_POS) + +/****************** Bit definition for RTC_TIME register ************************/ + +#define RTC_TIME_PM_POS 22U +#define RTC_TIME_PM_MSK BIT(RTC_TIME_PM_POS) + +#define RTC_TIME_HRT_POSS 20U +#define RTC_TIME_HRT_POSE 21U +#define RTC_TIME_HRT_MSK BITS(RTC_TIME_HRT_POSS,RTC_TIME_HRT_POSE) + +#define RTC_TIME_HRU_POSS 16U +#define RTC_TIME_HRU_POSE 19U +#define RTC_TIME_HRU_MSK BITS(RTC_TIME_HRU_POSS,RTC_TIME_HRU_POSE) + +#define RTC_TIME_MINT_POSS 12U +#define RTC_TIME_MINT_POSE 14U +#define RTC_TIME_MINT_MSK BITS(RTC_TIME_MINT_POSS,RTC_TIME_MINT_POSE) + +#define RTC_TIME_MINU_POSS 8U +#define RTC_TIME_MINU_POSE 11U +#define RTC_TIME_MINU_MSK BITS(RTC_TIME_MINU_POSS,RTC_TIME_MINU_POSE) + +#define RTC_TIME_SECT_POSS 4U +#define RTC_TIME_SECT_POSE 6U +#define RTC_TIME_SECT_MSK BITS(RTC_TIME_SECT_POSS,RTC_TIME_SECT_POSE) + +#define RTC_TIME_SECU_POSS 0U +#define RTC_TIME_SECU_POSE 3U +#define RTC_TIME_SECU_MSK BITS(RTC_TIME_SECU_POSS,RTC_TIME_SECU_POSE) + +/****************** Bit definition for RTC_DATE register ************************/ + +#define RTC_DATE_WD_POSS 24U +#define RTC_DATE_WD_POSE 26U +#define RTC_DATE_WD_MSK BITS(RTC_DATE_WD_POSS,RTC_DATE_WD_POSE) + +#define RTC_DATE_YRT_POSS 20U +#define RTC_DATE_YRT_POSE 23U +#define RTC_DATE_YRT_MSK BITS(RTC_DATE_YRT_POSS,RTC_DATE_YRT_POSE) + +#define RTC_DATE_YRU_POSS 16U +#define RTC_DATE_YRU_POSE 19U +#define RTC_DATE_YRU_MSK BITS(RTC_DATE_YRU_POSS,RTC_DATE_YRU_POSE) + +#define RTC_DATE_MONT_POS 12U +#define RTC_DATE_MONT_MSK BIT(RTC_DATE_MONT_POS) + +#define RTC_DATE_MONU_POSS 8U +#define RTC_DATE_MONU_POSE 11U +#define RTC_DATE_MONU_MSK BITS(RTC_DATE_MONU_POSS,RTC_DATE_MONU_POSE) + +#define RTC_DATE_DAYT_POSS 4U +#define RTC_DATE_DAYT_POSE 5U +#define RTC_DATE_DAYT_MSK BITS(RTC_DATE_DAYT_POSS,RTC_DATE_DAYT_POSE) + +#define RTC_DATE_DAYU_POSS 0U +#define RTC_DATE_DAYU_POSE 3U +#define RTC_DATE_DAYU_MSK BITS(RTC_DATE_DAYU_POSS,RTC_DATE_DAYU_POSE) + +/****************** Bit definition for RTC_SSEC register ************************/ + +#define RTC_SSEC_VAL_POSS 0U +#define RTC_SSEC_VAL_POSE 15U +#define RTC_SSEC_VAL_MSK BITS(RTC_SSEC_VAL_POSS,RTC_SSEC_VAL_POSE) + +/****************** Bit definition for RTC_WUMAT register ************************/ + +#define RTC_WUMAT_VAL_POSS 0U +#define RTC_WUMAT_VAL_POSE 15U +#define RTC_WUMAT_VAL_MSK BITS(RTC_WUMAT_VAL_POSS,RTC_WUMAT_VAL_POSE) + +/****************** Bit definition for RTC_ALMA register ************************/ + +#define RTC_ALMA_WDS_POS 31U +#define RTC_ALMA_WDS_MSK BIT(RTC_ALMA_WDS_POS) + +#define RTC_ALMA_DAWD_POSS 24U +#define RTC_ALMA_DAWD_POSE 30U +#define RTC_ALMA_DAWD_MSK BITS(RTC_ALMA_DAWD_POSS,RTC_ALMA_DAWD_POSE) + +#define RTC_ALMA_DAYMSK_POS 30U +#define RTC_ALMA_DAYMSK_MSK BIT(RTC_ALMA_DAYMSK_POS) + +#define RTC_ALMA_DAWD_DAYT_POSS 28U +#define RTC_ALMA_DAWD_DAYT_POSE 29U +#define RTC_ALMA_DAWD_DAYT_MSK BITS(RTC_ALMA_DAWD_DAYT_POSS, RTC_ALMA_DAWD_DAYT_POSE) + +#define RTC_ALMA_DAWD_DAYU_POSS 24U +#define RTC_ALMA_DAWD_DAYU_POSE 27U +#define RTC_ALMA_DAWD_DAYU_MSK BITS(RTC_ALMA_DAWD_DAYU_POSS, RTC_ALMA_DAWD_DAYU_POSE) + +#define RTC_ALMA_HRMSK_POS 23U +#define RTC_ALMA_HRMSK_MSK BIT(RTC_ALMA_HRMSK_POS) + +#define RTC_ALMA_PM_POS 22U +#define RTC_ALMA_PM_MSK BIT(RTC_ALMA_PM_POS) + +#define RTC_ALMA_HRT_POSS 20U +#define RTC_ALMA_HRT_POSE 21U +#define RTC_ALMA_HRT_MSK BITS(RTC_ALMA_HRT_POSS,RTC_ALMA_HRT_POSE) + +#define RTC_ALMA_HRU_POSS 16U +#define RTC_ALMA_HRU_POSE 19U +#define RTC_ALMA_HRU_MSK BITS(RTC_ALMA_HRU_POSS,RTC_ALMA_HRU_POSE) + +#define RTC_ALMA_MINMSK_POS 15U +#define RTC_ALMA_MINMSK_MSK BIT(RTC_ALMA_MINMSK_POS) + +#define RTC_ALMA_MINT_POSS 12U +#define RTC_ALMA_MINT_POSE 14U +#define RTC_ALMA_MINT_MSK BITS(RTC_ALMA_MINT_POSS,RTC_ALMA_MINT_POSE) + +#define RTC_ALMA_MINU_POSS 8U +#define RTC_ALMA_MINU_POSE 11U +#define RTC_ALMA_MINU_MSK BITS(RTC_ALMA_MINU_POSS,RTC_ALMA_MINU_POSE) + +#define RTC_ALMA_SECMSK_POS 7U +#define RTC_ALMA_SECMSK_MSK BIT(RTC_ALMA_SECMSK_POS) + +#define RTC_ALMA_SECT_POSS 4U +#define RTC_ALMA_SECT_POSE 6U +#define RTC_ALMA_SECT_MSK BITS(RTC_ALMA_SECT_POSS,RTC_ALMA_SECT_POSE) + +#define RTC_ALMA_SECU_POSS 0U +#define RTC_ALMA_SECU_POSE 3U +#define RTC_ALMA_SECU_MSK BITS(RTC_ALMA_SECU_POSS,RTC_ALMA_SECU_POSE) + +/****************** Bit definition for RTC_ALMB register ************************/ + +#define RTC_ALMB_WDS_POS 31U +#define RTC_ALMB_WDS_MSK BIT(RTC_ALMB_WDS_POS) + +#define RTC_ALMB_DAWD_POSS 24U +#define RTC_ALMB_DAWD_POSE 30U +#define RTC_ALMB_DAWD_MSK BITS(RTC_ALMB_DAWD_POSS,RTC_ALMB_DAWD_POSE) + +#define RTC_ALMB_DAYMSK_POS 30U +#define RTC_ALMB_DAYMSK_MSK BIT(RTC_ALMB_DAYMSK_POS) + +#define RTC_ALMB_DAWD_DAYT_POSS 28U +#define RTC_ALMB_DAWD_DAYT_POSE 29U +#define RTC_ALMB_DAWD_DAYT_MSK BITS(RTC_ALMB_DAWD_DAYT_POSS, RTC_ALMB_DAWD_DAYT_POSE) + +#define RTC_ALMB_DAWD_DAYU_POSS 24U +#define RTC_ALMB_DAWD_DAYU_POSE 27U +#define RTC_ALMB_DAWD_DAYU_MSK BITS(RTC_ALMB_DAWD_DAYU_POSS, RTC_ALMB_DAWD_DAYU_POSE) + +#define RTC_ALMB_HRMSK_POS 23U +#define RTC_ALMB_HRMSK_MSK BIT(RTC_ALMB_HRMSK_POS) + +#define RTC_ALMB_PM_POS 22U +#define RTC_ALMB_PM_MSK BIT(RTC_ALMB_PM_POS) + +#define RTC_ALMB_HRT_POSS 20U +#define RTC_ALMB_HRT_POSE 21U +#define RTC_ALMB_HRT_MSK BITS(RTC_ALMB_HRT_POSS,RTC_ALMB_HRT_POSE) + +#define RTC_ALMB_HRU_POSS 16U +#define RTC_ALMB_HRU_POSE 19U +#define RTC_ALMB_HRU_MSK BITS(RTC_ALMB_HRU_POSS,RTC_ALMB_HRU_POSE) + +#define RTC_ALMB_MINMSK_POS 15U +#define RTC_ALMB_MINMSK_MSK BIT(RTC_ALMB_MINMSK_POS) + +#define RTC_ALMB_MINT_POSS 12U +#define RTC_ALMB_MINT_POSE 14U +#define RTC_ALMB_MINT_MSK BITS(RTC_ALMB_MINT_POSS,RTC_ALMB_MINT_POSE) + +#define RTC_ALMB_MINU_POSS 8U +#define RTC_ALMB_MINU_POSE 11U +#define RTC_ALMB_MINU_MSK BITS(RTC_ALMB_MINU_POSS,RTC_ALMB_MINU_POSE) + +#define RTC_ALMB_SECMSK_POS 7U +#define RTC_ALMB_SECMSK_MSK BIT(RTC_ALMB_SECMSK_POS) + +#define RTC_ALMB_SECT_POSS 4U +#define RTC_ALMB_SECT_POSE 6U +#define RTC_ALMB_SECT_MSK BITS(RTC_ALMB_SECT_POSS,RTC_ALMB_SECT_POSE) + +#define RTC_ALMB_SECU_POSS 0U +#define RTC_ALMB_SECU_POSE 3U +#define RTC_ALMB_SECU_MSK BITS(RTC_ALMB_SECU_POSS,RTC_ALMB_SECU_POSE) + +/****************** Bit definition for RTC_ALMASSEC register ************************/ + +#define RTC_ALMASSEC_SSECM_POSS 24U +#define RTC_ALMASSEC_SSECM_POSE 27U +#define RTC_ALMASSEC_SSECM_MSK BITS(RTC_ALMASSEC_SSECM_POSS,RTC_ALMASSEC_SSECM_POSE) + +#define RTC_ALMASSEC_SSEC_POSS 0U +#define RTC_ALMASSEC_SSEC_POSE 14U +#define RTC_ALMASSEC_SSEC_MSK BITS(RTC_ALMASSEC_SSEC_POSS,RTC_ALMASSEC_SSEC_POSE) + +/****************** Bit definition for RTC_ALMBSSEC register ************************/ + +#define RTC_ALMBSSEC_SSECM_POSS 24U +#define RTC_ALMBSSEC_SSECM_POSE 27U +#define RTC_ALMBSSEC_SSECM_MSK BITS(RTC_ALMBSSEC_SSECM_POSS,RTC_ALMBSSEC_SSECM_POSE) + +#define RTC_ALMBSSEC_SSEC_POSS 0U +#define RTC_ALMBSSEC_SSEC_POSE 14U +#define RTC_ALMBSSEC_SSEC_MSK BITS(RTC_ALMBSSEC_SSEC_POSS,RTC_ALMBSSEC_SSEC_POSE) + +/****************** Bit definition for RTC_TSTIME register ************************/ + +#define RTC_TSTIME_PM_POS 22U +#define RTC_TSTIME_PM_MSK BIT(RTC_TSTIME_PM_POS) + +#define RTC_TSTIME_HRT_POSS 20U +#define RTC_TSTIME_HRT_POSE 21U +#define RTC_TSTIME_HRT_MSK BITS(RTC_TSTIME_HRT_POSS,RTC_TSTIME_HRT_POSE) + +#define RTC_TSTIME_HRU_POSS 16U +#define RTC_TSTIME_HRU_POSE 19U +#define RTC_TSTIME_HRU_MSK BITS(RTC_TSTIME_HRU_POSS,RTC_TSTIME_HRU_POSE) + +#define RTC_TSTIME_MINT_POSS 12U +#define RTC_TSTIME_MINT_POSE 14U +#define RTC_TSTIME_MINT_MSK BITS(RTC_TSTIME_MINT_POSS,RTC_TSTIME_MINT_POSE) + +#define RTC_TSTIME_MINU_POSS 8U +#define RTC_TSTIME_MINU_POSE 11U +#define RTC_TSTIME_MINU_MSK BITS(RTC_TSTIME_MINU_POSS,RTC_TSTIME_MINU_POSE) + +#define RTC_TSTIME_SECT_POSS 4U +#define RTC_TSTIME_SECT_POSE 6U +#define RTC_TSTIME_SECT_MSK BITS(RTC_TSTIME_SECT_POSS,RTC_TSTIME_SECT_POSE) + +#define RTC_TSTIME_SECU_POSS 0U +#define RTC_TSTIME_SECU_POSE 3U +#define RTC_TSTIME_SECU_MSK BITS(RTC_TSTIME_SECU_POSS,RTC_TSTIME_SECU_POSE) + +/****************** Bit definition for RTC_TSDATE register ************************/ + +#define RTC_TSDATE_WD_POSS 24U +#define RTC_TSDATE_WD_POSE 26U +#define RTC_TSDATE_WD_MSK BITS(RTC_TSDATE_WD_POSS,RTC_TSDATE_WD_POSE) + +#define RTC_TSDATE_YRT_POSS 20U +#define RTC_TSDATE_YRT_POSE 23U +#define RTC_TSDATE_YRT_MSK BITS(RTC_TSDATE_YRT_POSS,RTC_TSDATE_YRT_POSE) + +#define RTC_TSDATE_YRU_POSS 16U +#define RTC_TSDATE_YRU_POSE 19U +#define RTC_TSDATE_YRU_MSK BITS(RTC_TSDATE_YRU_POSS,RTC_TSDATE_YRU_POSE) + +#define RTC_TSDATE_MONT_POS 12U +#define RTC_TSDATE_MONT_MSK BIT(RTC_TSDATE_MONT_POS) + +#define RTC_TSDATE_MONU_POSS 8U +#define RTC_TSDATE_MONU_POSE 11U +#define RTC_TSDATE_MONU_MSK BITS(RTC_TSDATE_MONU_POSS,RTC_TSDATE_MONU_POSE) + +#define RTC_TSDATE_DAYT_POSS 4U +#define RTC_TSDATE_DAYT_POSE 5U +#define RTC_TSDATE_DAYT_MSK BITS(RTC_TSDATE_DAYT_POSS,RTC_TSDATE_DAYT_POSE) + +#define RTC_TSDATE_DAYU_POSS 0U +#define RTC_TSDATE_DAYU_POSE 3U +#define RTC_TSDATE_DAYU_MSK BITS(RTC_TSDATE_DAYU_POSS,RTC_TSDATE_DAYU_POSE) + +/****************** Bit definition for RTC_TSSSEC register ************************/ + +#define RTC_TSSSEC_SSEC_POSS 0U +#define RTC_TSSSEC_SSEC_POSE 15U +#define RTC_TSSSEC_SSEC_MSK BITS(RTC_TSSSEC_SSEC_POSS,RTC_TSSSEC_SSEC_POSE) + +/****************** Bit definition for RTC_SSECTR register ************************/ + +#define RTC_SSECTR_INC_POS 31U +#define RTC_SSECTR_INC_MSK BIT(RTC_SSECTR_INC_POS) + +#define RTC_SSECTR_TRIM_POSS 0U +#define RTC_SSECTR_TRIM_POSE 14U +#define RTC_SSECTR_TRIM_MSK BITS(RTC_SSECTR_TRIM_POSS,RTC_SSECTR_TRIM_POSE) + +/****************** Bit definition for RTC_IER register ************************/ + +#define RTC_IER_TCE_POS 25U +#define RTC_IER_TCE_MSK BIT(RTC_IER_TCE_POS) + +#define RTC_IER_TCC_POS 24U +#define RTC_IER_TCC_MSK BIT(RTC_IER_TCC_POS) + +#define RTC_IER_WU_POS 18U +#define RTC_IER_WU_MSK BIT(RTC_IER_WU_POS) + +#define RTC_IER_SSTC_POS 17U +#define RTC_IER_SSTC_MSK BIT(RTC_IER_SSTC_POS) + +#define RTC_IER_RSC_POS 16U +#define RTC_IER_RSC_MSK BIT(RTC_IER_RSC_POS) + +#define RTC_IER_TAMP1_POS 13U +#define RTC_IER_TAMP1_MSK BIT(RTC_IER_TAMP1_POS) + +#define RTC_IER_TAMP0_POS 12U +#define RTC_IER_TAMP0_MSK BIT(RTC_IER_TAMP0_POS) + +#define RTC_IER_TSOV_POS 11U +#define RTC_IER_TSOV_MSK BIT(RTC_IER_TSOV_POS) + +#define RTC_IER_TS_POS 10U +#define RTC_IER_TS_MSK BIT(RTC_IER_TS_POS) + +#define RTC_IER_ALMB_POS 9U +#define RTC_IER_ALMB_MSK BIT(RTC_IER_ALMB_POS) + +#define RTC_IER_ALMA_POS 8U +#define RTC_IER_ALMA_MSK BIT(RTC_IER_ALMA_POS) + +#define RTC_IER_YR_POS 5U +#define RTC_IER_YR_MSK BIT(RTC_IER_YR_POS) + +#define RTC_IER_MON_POS 4U +#define RTC_IER_MON_MSK BIT(RTC_IER_MON_POS) + +#define RTC_IER_DAY_POS 3U +#define RTC_IER_DAY_MSK BIT(RTC_IER_DAY_POS) + +#define RTC_IER_HR_POS 2U +#define RTC_IER_HR_MSK BIT(RTC_IER_HR_POS) + +#define RTC_IER_MIN_POS 1U +#define RTC_IER_MIN_MSK BIT(RTC_IER_MIN_POS) + +#define RTC_IER_SEC_POS 0U +#define RTC_IER_SEC_MSK BIT(RTC_IER_SEC_POS) + +/****************** Bit definition for RTC_IFR register ************************/ + +#define RTC_IFR_TCEF_POS 25U +#define RTC_IFR_TCEF_MSK BIT(RTC_IFR_TCEF_POS) + +#define RTC_IFR_TCCF_POS 24U +#define RTC_IFR_TCCF_MSK BIT(RTC_IFR_TCCF_POS) + +#define RTC_IFR_WUF_POS 18U +#define RTC_IFR_WUF_MSK BIT(RTC_IFR_WUF_POS) + +#define RTC_IFR_SSTCF_POS 17U +#define RTC_IFR_SSTCF_MSK BIT(RTC_IFR_SSTCF_POS) + +#define RTC_IFR_RSCF_POS 16U +#define RTC_IFR_RSCF_MSK BIT(RTC_IFR_RSCF_POS) + +#define RTC_IFR_TAMP1F_POS 13U +#define RTC_IFR_TAMP1F_MSK BIT(RTC_IFR_TAMP1F_POS) + +#define RTC_IFR_TAMP0F_POS 12U +#define RTC_IFR_TAMP0F_MSK BIT(RTC_IFR_TAMP0F_POS) + +#define RTC_IFR_TSOVF_POS 11U +#define RTC_IFR_TSOVF_MSK BIT(RTC_IFR_TSOVF_POS) + +#define RTC_IFR_TSF_POS 10U +#define RTC_IFR_TSF_MSK BIT(RTC_IFR_TSF_POS) + +#define RTC_IFR_ALMBF_POS 9U +#define RTC_IFR_ALMBF_MSK BIT(RTC_IFR_ALMBF_POS) + +#define RTC_IFR_ALMAF_POS 8U +#define RTC_IFR_ALMAF_MSK BIT(RTC_IFR_ALMAF_POS) + +#define RTC_IFR_YRF_POS 5U +#define RTC_IFR_YRF_MSK BIT(RTC_IFR_YRF_POS) + +#define RTC_IFR_MONF_POS 4U +#define RTC_IFR_MONF_MSK BIT(RTC_IFR_MONF_POS) + +#define RTC_IFR_DAYF_POS 3U +#define RTC_IFR_DAYF_MSK BIT(RTC_IFR_DAYF_POS) + +#define RTC_IFR_HRF_POS 2U +#define RTC_IFR_HRF_MSK BIT(RTC_IFR_HRF_POS) + +#define RTC_IFR_MINF_POS 1U +#define RTC_IFR_MINF_MSK BIT(RTC_IFR_MINF_POS) + +#define RTC_IFR_SECF_POS 0U +#define RTC_IFR_SECF_MSK BIT(RTC_IFR_SECF_POS) + +/****************** Bit definition for RTC_IFCR register ************************/ + +#define RTC_IFCR_TCEFC_POS 25U +#define RTC_IFCR_TCEFC_MSK BIT(RTC_IFCR_TCEFC_POS) + +#define RTC_IFCR_TCCFC_POS 24U +#define RTC_IFCR_TCCFC_MSK BIT(RTC_IFCR_TCCFC_POS) + +#define RTC_IFCR_WUFC_POS 18U +#define RTC_IFCR_WUFC_MSK BIT(RTC_IFCR_WUFC_POS) + +#define RTC_IFCR_SSTCFC_POS 17U +#define RTC_IFCR_SSTCFC_MSK BIT(RTC_IFCR_SSTCFC_POS) + +#define RTC_IFCR_RSCFC_POS 16U +#define RTC_IFCR_RSCFC_MSK BIT(RTC_IFCR_RSCFC_POS) + +#define RTC_IFCR_TAMP1FC_POS 13U +#define RTC_IFCR_TAMP1FC_MSK BIT(RTC_IFCR_TAMP1FC_POS) + +#define RTC_IFCR_TAMP0FC_POS 12U +#define RTC_IFCR_TAMP0FC_MSK BIT(RTC_IFCR_TAMP0FC_POS) + +#define RTC_IFCR_TSOVFC_POS 11U +#define RTC_IFCR_TSOVFC_MSK BIT(RTC_IFCR_TSOVFC_POS) + +#define RTC_IFCR_TSFC_POS 10U +#define RTC_IFCR_TSFC_MSK BIT(RTC_IFCR_TSFC_POS) + +#define RTC_IFCR_ALMBFC_POS 9U +#define RTC_IFCR_ALMBFC_MSK BIT(RTC_IFCR_ALMBFC_POS) + +#define RTC_IFCR_ALMAFC_POS 8U +#define RTC_IFCR_ALMAFC_MSK BIT(RTC_IFCR_ALMAFC_POS) + +#define RTC_IFCR_YRFC_POS 5U +#define RTC_IFCR_YRFC_MSK BIT(RTC_IFCR_YRFC_POS) + +#define RTC_IFCR_MONFC_POS 4U +#define RTC_IFCR_MONFC_MSK BIT(RTC_IFCR_MONFC_POS) + +#define RTC_IFCR_DAYFC_POS 3U +#define RTC_IFCR_DAYFC_MSK BIT(RTC_IFCR_DAYFC_POS) + +#define RTC_IFCR_HRFC_POS 2U +#define RTC_IFCR_HRFC_MSK BIT(RTC_IFCR_HRFC_POS) + +#define RTC_IFCR_MINFC_POS 1U +#define RTC_IFCR_MINFC_MSK BIT(RTC_IFCR_MINFC_POS) + +#define RTC_IFCR_SECFC_POS 0U +#define RTC_IFCR_SECFC_MSK BIT(RTC_IFCR_SECFC_POS) + +/****************** Bit definition for RTC_ISR register ************************/ + +#define RTC_ISR_TCEF_POS 25U +#define RTC_ISR_TCEF_MSK BIT(RTC_ISR_TCEF_POS) + +#define RTC_ISR_TCCF_POS 24U +#define RTC_ISR_TCCF_MSK BIT(RTC_ISR_TCCF_POS) + +#define RTC_ISR_WUF_POS 18U +#define RTC_ISR_WUF_MSK BIT(RTC_ISR_WUF_POS) + +#define RTC_ISR_SSTCF_POS 17U +#define RTC_ISR_SSTCF_MSK BIT(RTC_ISR_SSTCF_POS) + +#define RTC_ISR_RSCF_POS 16U +#define RTC_ISR_RSCF_MSK BIT(RTC_ISR_RSCF_POS) + +#define RTC_ISR_TAMP1F_POS 13U +#define RTC_ISR_TAMP1F_MSK BIT(RTC_ISR_TAMP1F_POS) + +#define RTC_ISR_TAMP0F_POS 12U +#define RTC_ISR_TAMP0F_MSK BIT(RTC_ISR_TAMP0F_POS) + +#define RTC_ISR_TSOVF_POS 11U +#define RTC_ISR_TSOVF_MSK BIT(RTC_ISR_TSOVF_POS) + +#define RTC_ISR_TSF_POS 10U +#define RTC_ISR_TSF_MSK BIT(RTC_ISR_TSF_POS) + +#define RTC_ISR_ALMBF_POS 9U +#define RTC_ISR_ALMBF_MSK BIT(RTC_ISR_ALMBF_POS) + +#define RTC_ISR_ALMAF_POS 8U +#define RTC_ISR_ALMAF_MSK BIT(RTC_ISR_ALMAF_POS) + +#define RTC_ISR_YRF_POS 5U +#define RTC_ISR_YRF_MSK BIT(RTC_ISR_YRF_POS) + +#define RTC_ISR_MONF_POS 4U +#define RTC_ISR_MONF_MSK BIT(RTC_ISR_MONF_POS) + +#define RTC_ISR_DAYF_POS 3U +#define RTC_ISR_DAYF_MSK BIT(RTC_ISR_DAYF_POS) + +#define RTC_ISR_HRF_POS 2U +#define RTC_ISR_HRF_MSK BIT(RTC_ISR_HRF_POS) + +#define RTC_ISR_MINF_POS 1U +#define RTC_ISR_MINF_MSK BIT(RTC_ISR_MINF_POS) + +#define RTC_ISR_SECF_POS 0U +#define RTC_ISR_SECF_MSK BIT(RTC_ISR_SECF_POS) + +/****************** Bit definition for RTC_CALWPR register ************************/ + +#define RTC_CALWPR_WP_POS 0U +#define RTC_CALWPR_WP_MSK BIT(RTC_CALWPR_WP_POS) + +/****************** Bit definition for RTC_CALCON register ************************/ + +#define RTC_CALCON_DCMACC_POS 24U +#define RTC_CALCON_DCMACC_MSK BIT(RTC_CALCON_DCMACC_POS) + +#define RTC_CALCON_ALG_POS 23U +#define RTC_CALCON_ALG_MSK BIT(RTC_CALCON_ALG_POS) + +#define RTC_CALCON_TCP_POSS 20U +#define RTC_CALCON_TCP_POSE 22U +#define RTC_CALCON_TCP_MSK BITS(RTC_CALCON_TCP_POSS,RTC_CALCON_TCP_POSE) + +#define RTC_CALCON_ERR_POS 19U +#define RTC_CALCON_ERR_MSK BIT(RTC_CALCON_ERR_POS) + +#define RTC_CALCON_BUSY_POS 18U +#define RTC_CALCON_BUSY_MSK BIT(RTC_CALCON_BUSY_POS) + +#define RTC_CALCON_TCM_POSS 16U +#define RTC_CALCON_TCM_POSE 17U +#define RTC_CALCON_TCM_MSK BITS(RTC_CALCON_TCM_POSS,RTC_CALCON_TCM_POSE) + +#define RTC_CALCON_CALP_POSS 1U +#define RTC_CALCON_CALP_POSE 3U +#define RTC_CALCON_CALP_MSK BITS(RTC_CALCON_CALP_POSS,RTC_CALCON_CALP_POSE) + +#define RTC_CALCON_CALEN_POS 0U +#define RTC_CALCON_CALEN_MSK BIT(RTC_CALCON_CALEN_POS) + +/****************** Bit definition for RTC_CALDR register ************************/ + +#define RTC_CALDR_DATA_POSS 16U +#define RTC_CALDR_DATA_POSE 31U +#define RTC_CALDR_DATA_MSK BITS(RTC_CALDR_DATA_POSS,RTC_CALDR_DATA_POSE) + +#define RTC_CALDR_VAL_POSS 0U +#define RTC_CALDR_VAL_POSE 15U +#define RTC_CALDR_VAL_MSK BITS(RTC_CALDR_VAL_POSS,RTC_CALDR_VAL_POSE) + +/****************** Bit definition for RTC_TEMPR register ************************/ + +#define RTC_TEMPR_DATA_POSS 16U +#define RTC_TEMPR_DATA_POSE 31U +#define RTC_TEMPR_DATA_MSK BITS(RTC_TEMPR_DATA_POSS,RTC_TEMPR_DATA_POSE) + +#define RTC_TEMPR_VAL_POSS 0U +#define RTC_TEMPR_VAL_POSE 15U +#define RTC_TEMPR_VAL_MSK BITS(RTC_TEMPR_VAL_POSS,RTC_TEMPR_VAL_POSE) + +/****************** Bit definition for RTC_TEMPBDR register ************************/ + +#define RTC_TEMPBDR_VAL_POSS 0U +#define RTC_TEMPBDR_VAL_POSE 15U +#define RTC_TEMPBDR_VAL_MSK BITS(RTC_TEMPBDR_VAL_POSS,RTC_TEMPBDR_VAL_POSE) + +/****************** Bit definition for RTC_BKP register ************************/ + +#define RTC_BKP_BKP_POSS 0U +#define RTC_BKP_BKP_POSE 31U +#define RTC_BKP_BKP_MSK BITS(RTC_BKP_BKP_POSS,RTC_BKP_BKP_POSE) + +typedef struct +{ + __IO uint32_t WPR; + __IO uint32_t CON; + __IO uint32_t PSR; + __IO uint32_t TAMPCON; + __IO uint32_t TIME; + __IO uint32_t DATE; + __IO uint32_t SSEC; + __IO uint32_t WUMAT; + __IO uint32_t ALMA; + __IO uint32_t ALMB; + __IO uint32_t ALMASSEC; + __IO uint32_t ALMBSSEC; + __I uint32_t TSTIME; + __I uint32_t TSDATE; + __I uint32_t TSSSEC; + __O uint32_t SSECTR; + __IO uint32_t IER; + __I uint32_t IFR; + __O uint32_t IFCR; + __I uint32_t ISR; + __IO uint32_t CALWPR; + __IO uint32_t CALCON; + __IO uint32_t CALDR; + __IO uint32_t TEMPR; + __IO uint32_t LTCAR; + __IO uint32_t LTCBR; + __IO uint32_t LTCCR; + __IO uint32_t LTCDR; + __IO uint32_t LTCER; + __IO uint32_t HTCAR; + __IO uint32_t HTCBR; + __IO uint32_t HTCCR; + __IO uint32_t HTCDR; + __IO uint32_t HTCER; + __IO uint32_t TEMPBDR; + __IO uint32_t LTAXR; + __IO uint32_t HTAXR; + uint32_t RESERVED0[27] ; + __IO uint32_t BKPR[32]; +} RTC_TypeDef; + +/****************** Bit definition for TIMER_CON1 register ************************/ + +#define TIMER_CON1_DBGSEL_POSS 15U +#define TIMER_CON1_DBGSEL_MSK BIT(TIMER_CON1_DBGSEL_POSS) + +#define TIMER_CON1_OCCISS_POSS 11U +#define TIMER_CON1_OCCISS_POSE 13U +#define TIMER_CON1_OCCISS_MSK BITS(TIMER_CON1_OCCISS_POSS,TIMER_CON1_OCCISS_POSE) + +#define TIMER_CON1_OCCISP_POSS 10U +#define TIMER_CON1_OCCISP_MSK BIT(TIMER_CON1_OCCISP_POSS) + +#define TIMER_CON1_DFCKSEL_POSS 8U +#define TIMER_CON1_DFCKSEL_POSE 9U +#define TIMER_CON1_DFCKSEL_MSK BITS(TIMER_CON1_DFCKSEL_POSS,TIMER_CON1_DFCKSEL_POSE) + +#define TIMER_CON1_ARPEN_POS 7U +#define TIMER_CON1_ARPEN_MSK BIT(TIMER_CON1_ARPEN_POS) + +#define TIMER_CON1_CMSEL_POSS 5U +#define TIMER_CON1_CMSEL_POSE 6U +#define TIMER_CON1_CMSEL_MSK BITS(TIMER_CON1_CMSEL_POSS,TIMER_CON1_CMSEL_POSE) + +#define TIMER_CON1_DIRSEL_POS 4U +#define TIMER_CON1_DIRSEL_MSK BIT(TIMER_CON1_DIRSEL_POS) + +#define TIMER_CON1_SPMEN_POS 3U +#define TIMER_CON1_SPMEN_MSK BIT(TIMER_CON1_SPMEN_POS) + +#define TIMER_CON1_UERSEL_POS 2U +#define TIMER_CON1_UERSEL_MSK BIT(TIMER_CON1_UERSEL_POS) + +#define TIMER_CON1_DISUE_POS 1U +#define TIMER_CON1_DISUE_MSK BIT(TIMER_CON1_DISUE_POS) + +#define TIMER_CON1_CNTEN_POS 0U +#define TIMER_CON1_CNTEN_MSK BIT(TIMER_CON1_CNTEN_POS) + +/****************** Bit definition for TIMER_CON2 register ************************/ + +#define TIMER_CON2_OISS4_POS 14U +#define TIMER_CON2_OISS4_MSK BIT(TIMER_CON2_OISS4_POS) + +#define TIMER_CON2_OISS3N_POS 13U +#define TIMER_CON2_OISS3N_MSK BIT(TIMER_CON2_OISS3N_POS) + +#define TIMER_CON2_OISS3_POS 12U +#define TIMER_CON2_OISS3_MSK BIT(TIMER_CON2_OISS3_POS) + +#define TIMER_CON2_OISS2N_POS 11U +#define TIMER_CON2_OISS2N_MSK BIT(TIMER_CON2_OISS2N_POS) + +#define TIMER_CON2_OISS2_POS 10U +#define TIMER_CON2_OISS2_MSK BIT(TIMER_CON2_OISS2_POS) + +#define TIMER_CON2_OISS1N_POS 9U +#define TIMER_CON2_OISS1N_MSK BIT(TIMER_CON2_OISS1N_POS) + +#define TIMER_CON2_OISS1_POS 8U +#define TIMER_CON2_OISS1_MSK BIT(TIMER_CON2_OISS1_POS) + +#define TIMER_CON2_I1FSEL_POS 7U +#define TIMER_CON2_I1FSEL_MSK BIT(TIMER_CON2_I1FSEL_POS) + +#define TIMER_CON2_TRGOSEL_POSS 4U +#define TIMER_CON2_TRGOSEL_POSE 6U +#define TIMER_CON2_TRGOSEL_MSK BITS(TIMER_CON2_TRGOSEL_POSS,TIMER_CON2_TRGOSEL_POSE) + +#define TIMER_CON2_CCDMASEL_POS 3U +#define TIMER_CON2_CCDMASEL_MSK BIT(TIMER_CON2_CCDMASEL_POS) + +#define TIMER_CON2_CCUSEL_POS 2U +#define TIMER_CON2_CCUSEL_MSK BIT(TIMER_CON2_CCUSEL_POS) + +#define TIMER_CON2_CCPCEN_POS 0U +#define TIMER_CON2_CCPCEN_MSK BIT(TIMER_CON2_CCPCEN_POS) + +/****************** Bit definition for TIMER_SMCON register ************************/ + +#define TIMER_SMCON_ETPOL_POS 15U +#define TIMER_SMCON_ETPOL_MSK BIT(TIMER_SMCON_ETPOL_POS) + +#define TIMER_SMCON_ECM2EN_POS 14U +#define TIMER_SMCON_ECM2EN_MSK BIT(TIMER_SMCON_ECM2EN_POS) + +#define TIMER_SMCON_ETPSEL_POSS 12U +#define TIMER_SMCON_ETPSEL_POSE 13U +#define TIMER_SMCON_ETPSEL_MSK BITS(TIMER_SMCON_ETPSEL_POSS,TIMER_SMCON_ETPSEL_POSE) + +#define TIMER_SMCON_ETFLT_POSS 8U +#define TIMER_SMCON_ETFLT_POSE 11U +#define TIMER_SMCON_ETFLT_MSK BITS(TIMER_SMCON_ETFLT_POSS,TIMER_SMCON_ETFLT_POSE) + +#define TIMER_SMCON_MSCFG_POS 7U +#define TIMER_SMCON_MSCFG_MSK BIT(TIMER_SMCON_MSCFG_POS) + +#define TIMER_SMCON_TSSEL_POSS 4U +#define TIMER_SMCON_TSSEL_POSE 6U +#define TIMER_SMCON_TSSEL_MSK BITS(TIMER_SMCON_TSSEL_POSS,TIMER_SMCON_TSSEL_POSE) + +#define TIMER_SMCON_CHCSEL_POS 3U +#define TIMER_SMCON_CHCSEL_MASK BIT(TIMER_SMCON_CHCSEL_POS) + +#define TIMER_SMCON_SMODS_POSS 0U +#define TIMER_SMCON_SMODS_POSE 2U +#define TIMER_SMCON_SMODS_MSK BITS(TIMER_SMCON_SMODS_POSS,TIMER_SMCON_SMODS_POSE) + +/****************** Bit definition for TIMER_IER register ************************/ + +#define TIMER_IER_BRKIT_POS 7U +#define TIMER_IER_BRKIT_MSK BIT(TIMER_IER_BRKIT_POS) + +#define TIMER_IER_TRGIT_POS 6U +#define TIMER_IER_TRGIT_MSK BIT(TIMER_IER_TRGIT_POS) + +#define TIMER_IER_COMIT_POS 5U +#define TIMER_IER_COMIT_MSK BIT(TIMER_IER_COMIT_POS) + +#define TIMER_IER_CC4IT_POS 4U +#define TIMER_IER_CC4IT_MSK BIT(TIMER_IER_CC4IT_POS) + +#define TIMER_IER_CC3IT_POS 3U +#define TIMER_IER_CC3IT_MSK BIT(TIMER_IER_CC3IT_POS) + +#define TIMER_IER_CC2IT_POS 2U +#define TIMER_IER_CC2IT_MSK BIT(TIMER_IER_CC2IT_POS) + +#define TIMER_IER_CC1IT_POS 1U +#define TIMER_IER_CC1IT_MSK BIT(TIMER_IER_CC1IT_POS) + +#define TIMER_IER_UIT_POS 0U +#define TIMER_IER_UIT_MSK BIT(TIMER_IER_UIT_POS) + +/****************** Bit definition for TIMER_IDR register ************************/ +#define TIMER_IDR_BRKI_POS 7U +#define TIMER_IDR_BRKI_MSK BIT(TIMER_IDR_BRKI_POS) + +#define TIMER_IDR_TRGI_POS 6U +#define TIMER_IDR_TRGI_MSK BIT(TIMER_IDR_TRGI_POS) + +#define TIMER_IDR_COMI_POS 5U +#define TIMER_IDR_COMI_MSK BIT(TIMER_IDR_COMI_POS) + +#define TIMER_IDR_CC4I_POS 4U +#define TIMER_IDR_CC4I_MSK BIT(TIMER_IDR_CC4I_POS) + +#define TIMER_IDR_CC3I_POS 3U +#define TIMER_IDR_CC3I_MSK BIT(TIMER_IDR_CC3I_POS) + +#define TIMER_IDR_CC2I_POS 2U +#define TIMER_IDR_CC2I_MSK BIT(TIMER_IDR_CC2I_POS) + +#define TIMER_IDR_CC1I_POS 1U +#define TIMER_IDR_CC1I_MSK BIT(TIMER_IDR_CC1I_POS) + +#define TIMER_IDR_UI_POS 0U +#define TIMER_IDR_UI_MSK BIT(TIMER_IDR_UI_POS) + +/****************** Bit definition for TIMER_IVS register ************************/ + +#define TIMER_IVS_BKI_POS 7U +#define TIMER_IVS_BKI_MSK BIT(TIMER_IVS_BKI_POS) + +#define TIMER_IVS_TRGI_POS 6U +#define TIMER_IVS_TRGI_MSK BIT(TIMER_IVS_TRGI_POS) + +#define TIMER_IVS_COMI_POS 5U +#define TIMER_IVS_COMI_MSK BIT(TIMER_IVS_COMI_POS) + +#define TIMER_IVS_CC4I_POS 4U +#define TIMER_IVS_CC4I_MSK BIT(TIMER_IVS_CC4I_POS) + +#define TIMER_IVS_CC3I_POS 3U +#define TIMER_IVS_CC3I_MSK BIT(TIMER_IVS_CC3I_POS) + +#define TIMER_IVS_CC2I_POS 2U +#define TIMER_IVS_CC2I_MSK BIT(TIMER_IVS_CC2I_POS) + +#define TIMER_IVS_CC1I_POS 1U +#define TIMER_IVS_CC1I_MSK BIT(TIMER_IVS_CC1I_POS) + +#define TIMER_IVS_UEI_POS 0U +#define TIMER_IVS_UEI_MSK BIT(TIMER_IVS_UEI_POS) + +/****************** Bit definition for TIMER_RIF register ************************/ + +#define TIMER_RIF_CH4OVIF_POS 12U +#define TIMER_RIF_CH4OVIF_MSK BIT(TIMER_RIF_CH4OVIF_POS) + +#define TIMER_RIF_CH3OVIF_POS 11U +#define TIMER_RIF_CH3OVIF_MSK BIT(TIMER_RIF_CH3OVIF_POS) + +#define TIMER_RIF_CH2OVIF_POS 10U +#define TIMER_RIF_CH2OVIF_MSK BIT(TIMER_RIF_CH2OVIF_POS) + +#define TIMER_RIF_CH1OVIF_POS 9U +#define TIMER_RIF_CH1OVIF_MSK BIT(TIMER_RIF_CH1OVIF_POS) + +#define TIMER_RIF_BRKIF_POS 7U +#define TIMER_RIF_BRKIF_MSK BIT(TIMER_RIF_BRKIF_POS) + +#define TIMER_RIF_TRGIF_POS 6U +#define TIMER_RIF_TRGIF_MSK BIT(TIMER_RIF_TRGIF_POS) + +#define TIMER_RIF_COMIF_POS 5U +#define TIMER_RIF_COMIF_MSK BIT(TIMER_RIF_COMIF_POS) + +#define TIMER_RIF_CH4IF_POS 4U +#define TIMER_RIF_CH4IF_MSK BIT(TIMER_RIF_CH4IF_POS) + +#define TIMER_RIF_CH3IF_POS 3U +#define TIMER_RIF_CH3IF_MSK BIT(TIMER_RIF_CH3IF_POS) + +#define TIMER_RIF_CH2IF_POS 2U +#define TIMER_RIF_CH2IF_MSK BIT(TIMER_RIF_CH2IF_POS) + +#define TIMER_RIF_CH1IF_POS 1U +#define TIMER_RIF_CH1IF_MSK BIT(TIMER_RIF_CH1IF_POS) + +#define TIMER_RIF_UEVTIF_POS 0U +#define TIMER_RIF_UEVTIF_MSK BIT(TIMER_RIF_UEVTIF_POS) + +/****************** Bit definition for TIMER_IFM register ************************/ + +#define TIMER_IFM_BRKIM_POS 7U +#define TIMER_IFM_BRKIM_MSK BIT(TIMER_IFM_BRKIM_POS) + +#define TIMER_IFM_TRGI_POS 6U +#define TIMER_IFM_TRGI_MSK BIT(TIMER_IFM_TRGI_POS) + +#define TIMER_IFM_COMI_POS 5U +#define TIMER_IFM_COMI_MSK BIT(TIMER_IFM_COMI_POS) + +#define TIMER_IFM_CH4CCI_POS 4U +#define TIMER_IFM_CH4CCI_MSK BIT(TIMER_IFM_CH4CCI_POS) + +#define TIMER_IFM_CH3CCI_POS 3U +#define TIMER_IFM_CH3CCI_MSK BIT(TIMER_IFM_CH3CCI_POS) + +#define TIMER_IFM_CH2CCI_POS 2U +#define TIMER_IFM_CH2CCI_MSK BIT(TIMER_IFM_CH2CCI_POS) + +#define TIMER_IFM_CH1CCI_POS 1U +#define TIMER_IFM_CH1CCI_MSK BIT(TIMER_IFM_CH1CCI_POS) + +#define TIMER_IFM_UEI_POS 0U +#define TIMER_IFM_UEI_MSK BIT(TIMER_IFM_UEI_POS) + +/****************** Bit definition for TIMER_ICR register ************************/ + +#define TIMER_ICR_BRKIC_POS 7U +#define TIMER_ICR_BRKIC_MSK BIT(TIMER_ICR_BRKIC_POS) + +#define TIMER_ICR_TRGIC_POS 6U +#define TIMER_ICR_TRGIC_MSK BIT(TIMER_ICR_TRGIC_POS) + +#define TIMER_ICR_COMIC_POS 5U +#define TIMER_ICR_COMIC_MSK BIT(TIMER_ICR_COMIC_POS) + +#define TIMER_ICR_CH4CCIC_POS 4U +#define TIMER_ICR_CH4CCIC_MSK BIT(TIMER_ICR_CH4CCIC_POS) + +#define TIMER_ICR_CH3CCIC_POS 3U +#define TIMER_ICR_CH3CCIC_MSK BIT(TIMER_ICR_CH3CCIC_POS) + +#define TIMER_ICR_CH2CCIC_POS 2U +#define TIMER_ICR_CH2CCIC_MSK BIT(TIMER_ICR_CH2CCIC_POS) + +#define TIMER_ICR_CH1CCIC_POS 1U +#define TIMER_ICR_CH1CCIC_MSK BIT(TIMER_ICR_CH1CCIC_POS) + +#define TIMER_ICR_UEIC_POS 0U +#define TIMER_ICR_UEIC_MSK BIT(TIMER_ICR_UEIC_POS) + +/****************** Bit definition for TIMER_SGE register ************************/ + +#define TIMER_SGE_SGBRK_POS 7U +#define TIMER_SGE_SGBRK_MSK BIT(TIMER_SGE_SGBRK_POS) + +#define TIMER_SGE_SGTRG_POS 6U +#define TIMER_SGE_SGTRG_MSK BIT(TIMER_SGE_SGTRG_POS) + +#define TIMER_SGE_SGCOM_POS 5U +#define TIMER_SGE_SGCOM_MSK BIT(TIMER_SGE_SGCOM_POS) + +#define TIMER_SGE_SGCC4E_POS 4U +#define TIMER_SGE_SGCC4E_MSK BIT(TIMER_SGE_SGCC4E_POS) + +#define TIMER_SGE_SGCC3E_POS 3U +#define TIMER_SGE_SGCC3E_MSK BIT(TIMER_SGE_SGCC3E_POS) + +#define TIMER_SGE_SGCC2E_POS 2U +#define TIMER_SGE_SGCC2E_MSK BIT(TIMER_SGE_SGCC2E_POS) + +#define TIMER_SGE_SGCC1E_POS 1U +#define TIMER_SGE_SGCC1E_MSK BIT(TIMER_SGE_SGCC1E_POS) + +#define TIMER_SGE_SGU_POS 0U +#define TIMER_SGE_SGU_MSK BIT(TIMER_SGE_SGU_POS) + +/****************** Bit definition for TIMER_CHMR1 register ************************/ +/* Output */ +#define TIMER_CHMR1_CH2OCLREN_POS 15U +#define TIMER_CHMR1_CH2OCLREN_MSK BIT(TIMER_CHMR1_CH2OCLREN_POS) + +#define TIMER_CHMR1_CH2OMOD_POSS 12U +#define TIMER_CHMR1_CH2OMOD_POSE 14U +#define TIMER_CHMR1_CH2OMOD_MSK BITS(TIMER_CHMR1_CH2OMOD_POSS,TIMER_CHMR1_CH2OMOD_POSE) + +#define TIMER_CHMR1_CH2OPEN_POS 11U +#define TIMER_CHMR1_CH2OPEN_MSK BIT(TIMER_CHMR1_CH2OPEN_POS) + +#define TIMER_CHMR1_CH2OFEN_POS 10U +#define TIMER_CHMR1_CH2OFEN_MSK BIT(TIMER_CHMR1_CH2OFEN_POS) + +#define TIMER_CHMR1_CC2SSEL_POSS 8U +#define TIMER_CHMR1_CC2SSEL_POSE 9U +#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) + +#define TIMER_CHMR1_CH1OCLREN_POS 7U +#define TIMER_CHMR1_CH1OCLREN_MSK BIT(TIMER_CHMR1_CH1OCLREN_POS) + +#define TIMER_CHMR1_CH1OMOD_POSS 4U +#define TIMER_CHMR1_CH1OMOD_POSE 6U +#define TIMER_CHMR1_CH1OMOD_MSK BITS(TIMER_CHMR1_CH1OMOD_POSS,TIMER_CHMR1_CH1OMOD_POSE) + +#define TIMER_CHMR1_CH1OPREN_POS 3U +#define TIMER_CHMR1_CH1OPREN_MSK BIT(TIMER_CHMR1_CH1OPREN_POS) + +#define TIMER_CHMR1_CH1OHSEN_POS 2U +#define TIMER_CHMR1_CH1OHSEN_MSK BIT(TIMER_CHMR1_CH1OHSEN_POS) + +#define TIMER_CHMR1_CC1SSEL_POSS 0U +#define TIMER_CHMR1_CC1SSEL_POSE 1U +#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) + +/* Input */ +#define TIMER_CHMR1_I2FLT_POSS 12U +#define TIMER_CHMR1_I2FLT_POSE 15U +#define TIMER_CHMR1_I2FLT_MSK BITS(TIMER_CHMR1_I2FLT_POSS,TIMER_CHMR1_I2FLT_POSE) + +#define TIMER_CHMR1_IC2PRES_POSS 10U +#define TIMER_CHMR1_IC2PRES_POSE 11U +#define TIMER_CHMR1_IC2PRES_MSK BITS(TIMER_CHMR1_IC2PRES_POSS,TIMER_CHMR1_IC2PRES_POSE) + +#define TIMER_CHMR1_CC2SSEL_POSS 8U +#define TIMER_CHMR1_CC2SSEL_POSE 9U +#define TIMER_CHMR1_CC2SSEL_MSK BITS(TIMER_CHMR1_CC2SSEL_POSS,TIMER_CHMR1_CC2SSEL_POSE) + +#define TIMER_CHMR1_I1FLT_POSS 4U +#define TIMER_CHMR1_I1FLT_POSE 7U +#define TIMER_CHMR1_I1FLT_MSK BITS(TIMER_CHMR1_I1FLT_POSS,TIMER_CHMR1_I1FLT_POSE) + +#define TIMER_CHMR1_IC1PRES_POSS 2U +#define TIMER_CHMR1_IC1PRES_POSE 3U +#define TIMER_CHMR1_IC1PRES_MSK BITS(TIMER_CHMR1_IC1PRES_POSS,TIMER_CHMR1_IC1PRES_POSE) + +#define TIMER_CHMR1_CC1SSEL_POSS 0U +#define TIMER_CHMR1_CC1SSEL_POSE 1U +#define TIMER_CHMR1_CC1SSEL_MSK BITS(TIMER_CHMR1_CC1SSEL_POSS,TIMER_CHMR1_CC1SSEL_POSE) + +/****************** Bit definition for TIMER_CHMR2 register ************************/ +/* Output */ +#define TIMER_CHMR2_CH4OCLREN_POS 15U +#define TIMER_CHMR2_CH4OCLREN_MSK BIT(TIMER_CHMR2_CH4OCLREN_POS) + +#define TIMER_CHMR2_CH4OMOD_POSS 12U +#define TIMER_CHMR2_CH4OMOD_POSE 14U +#define TIMER_CHMR2_CH4OMOD_MSK BITS(TIMER_CHMR2_CH4OMOD_POSS,TIMER_CHMR2_CH4OMOD_POSE) + +#define TIMER_CHMR2_CH4OPEN_POS 11U +#define TIMER_CHMR2_CH4OPEN_MSK BIT(TIMER_CHMR2_CH4OPEN_POS) + +#define TIMER_CHMR2_CH4OHSEN_POS 10U +#define TIMER_CHMR2_CH4OHSEN_MSK BIT(TIMER_CHMR2_CH4OHSEN_POS) + +#define TIMER_CHMR2_CC4SSEL_POSS 8U +#define TIMER_CHMR2_CC4SSEL_POSE 9U +#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) + +#define TIMER_CHMR2_CH3OCLREN_POS 7U +#define TIMER_CHMR2_CH3OCLREN_MSK BIT(TIMER_CHMR2_CH3OCLREN_POS) + +#define TIMER_CHMR2_CH3OMOD_POSS 4U +#define TIMER_CHMR2_CH3OMOD_POSE 6U +#define TIMER_CHMR2_CH3OMOD_MSK BITS(TIMER_CHMR2_CH3OMOD_POSS,TIMER_CHMR2_CH3OMOD_POSE) + +#define TIMER_CHMR2_CH3OPEN_POS 3U +#define TIMER_CHMR2_CH3OPEN_MSK BIT(TIMER_CHMR2_CH3OPEN_POS) + +#define TIMER_CHMR2_CH3OFEN_POS 2U +#define TIMER_CHMR2_CH3OFEN_MSK BIT(TIMER_CHMR2_CH3OFEN_POS) + +#define TIMER_CHMR2_CC3SSEL_POSS 0U +#define TIMER_CHMR2_CC3SSEL_POSE 1U +#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) + +/* Input */ +#define TIMER_CHMR2_I4FLT_POSS 12U +#define TIMER_CHMR2_I4FLT_POSE 15U +#define TIMER_CHMR2_I4FLT_MSK BITS(TIMER_CHMR2_I4FLT_POSS,TIMER_CHMR2_I4FLT_POSE) + +#define TIMER_CHMR2_IC4PRES_POSS 10U +#define TIMER_CHMR2_IC4PRES_POSE 11U +#define TIMER_CHMR2_IC4PRES_MSK BITS(TIMER_CHMR2_IC4PRES_POSS,TIMER_CHMR2_IC4PRES_POSE) + +#define TIMER_CHMR2_CC4SSEL_POSS 8U +#define TIMER_CHMR2_CC4SSEL_POSE 9U +#define TIMER_CHMR2_CC4SSEL_MSK BITS(TIMER_CHMR2_CC4SSEL_POSS,TIMER_CHMR2_CC4SSEL_POSE) + +#define TIMER_CHMR2_I3FLT_POSS 4U +#define TIMER_CHMR2_I3FLT_POSE 7U +#define TIMER_CHMR2_I3FLT_MSK BITS(TIMER_CHMR2_I3FLT_POSS,TIMER_CHMR2_I3FLT_POSE) + +#define TIMER_CHMR2_IC3PRES_POSS 2U +#define TIMER_CHMR2_IC3PRES_POSE 3U +#define TIMER_CHMR2_IC3PRES_MSK BITS(TIMER_CHMR2_IC3PRES_POSS,TIMER_CHMR2_IC3PRES_POSE) + +#define TIMER_CHMR2_CC3SSEL_POSS 0U +#define TIMER_CHMR2_CC3SSEL_POSE 1U +#define TIMER_CHMR2_CC3SSEL_MSK BITS(TIMER_CHMR2_CC3SSEL_POSS,TIMER_CHMR2_CC3SSEL_POSE) + +/****************** Bit definition for TIMER_CCEP register ************************/ + +#define TIMER_CCEP_CC4POL_POS 13U +#define TIMER_CCEP_CC4POL_MSK BIT(TIMER_CCEP_CC4POL_POS) + +#define TIMER_CCEP_CC4EN_POS 12U +#define TIMER_CCEP_CC4EN_MSK BIT(TIMER_CCEP_CC4EN_POS) + +#define TIMER_CCEP_CC3NPOL_POS 11U +#define TIMER_CCEP_CC3NPOL_MSK BIT(TIMER_CCEP_CC3NPOL_POS) + +#define TIMER_CCEP_CC3NEN_POS 10U +#define TIMER_CCEP_CC3NEN_MSK BIT(TIMER_CCEP_CC3NEN_POS) + +#define TIMER_CCEP_CC3POL_POS 9U +#define TIMER_CCEP_CC3POL_MSK BIT(TIMER_CCEP_CC3POL_POS) + +#define TIMER_CCEP_CC3EN_POS 8U +#define TIMER_CCEP_CC3EN_MSK BIT(TIMER_CCEP_CC3EN_POS) + +#define TIMER_CCEP_CC2NPOL_POS 7U +#define TIMER_CCEP_CC2NPOL_MSK BIT(TIMER_CCEP_CC2NPOL_POS) + +#define TIMER_CCEP_CC2NEN_POS 6U +#define TIMER_CCEP_CC2NEN_MSK BIT(TIMER_CCEP_CC2NEN_POS) + +#define TIMER_CCEP_CC2POL_POS 5U +#define TIMER_CCEP_CC2POL_MSK BIT(TIMER_CCEP_CC2POL_POS) + +#define TIMER_CCEP_CC2EN_POS 4U +#define TIMER_CCEP_CC2EN_MSK BIT(TIMER_CCEP_CC2EN_POS) + +#define TIMER_CCEP_CC1NPOL_POS 3U +#define TIMER_CCEP_CC1NPOL_MSK BIT(TIMER_CCEP_CC1NPOL_POS) + +#define TIMER_CCEP_CC1NEN_POS 2U +#define TIMER_CCEP_CC1NEN_MSK BIT(TIMER_CCEP_CC1NEN_POS) + +#define TIMER_CCEP_CC1POL_POS 1U +#define TIMER_CCEP_CC1POL_MSK BIT(TIMER_CCEP_CC1POL_POS) + +#define TIMER_CCEP_CC1EN_POS 0U +#define TIMER_CCEP_CC1EN_MSK BIT(TIMER_CCEP_CC1EN_POS) + +/****************** Bit definition for TIMER_COUNT register ************************/ + +#define TIMER_COUNT_CNTV_POSS 0U +#define TIMER_COUNT_CNTV_POSE 15U +#define TIMER_COUNT_CNTV_MSK BITS(TIMER_COUNT_CNTV_POSS,TIMER_COUNT_CNTV_POSE) + +/****************** Bit definition for TIMER_PRES register ************************/ + +#define TIMER_PRES_PSCV_POSS 0U +#define TIMER_PRES_PSCV_POSE 15U +#define TIMER_PRES_PSCV_MSK BITS(TIMER_PRES_PSCV_POSS,TIMER_PRES_PSCV_POSE) + +/****************** Bit definition for TIMER_AR register ************************/ + +#define TIMER_AR_ARRV_POSS 0U +#define TIMER_AR_ARRV_POSE 15U +#define TIMER_AR_ARRV_MSK BITS(TIMER_AR_ARRV_POSS,TIMER_AR_ARRV_POSE) + +/****************** Bit definition for TIMER_REPAR register ************************/ + +#define TIMER_REPAR_REPV_POSS 0U +#define TIMER_REPAR_REPV_POSE 7U +#define TIMER_REPAR_REPV_MSK BITS(TIMER_REPAR_REPV_POSS,TIMER_REPAR_REPV_POSE) + +/****************** Bit definition for TIMER_CCVAL1 register ************************/ + +#define TIMER_CCVAL1_CCRV1_POSS 0U +#define TIMER_CCVAL1_CCRV1_POSE 15U +#define TIMER_CCVAL1_CCRV1_MSK BITS(TIMER_CCVAL1_CCRV1_POSS,TIMER_CCVAL1_CCRV1_POSE) + +/****************** Bit definition for TIMER_CCVAL2 register ************************/ + +#define TIMER_CCVAL2_CCRV2_POSS 0U +#define TIMER_CCVAL2_CCRV2_POSE 15U +#define TIMER_CCVAL2_CCRV2_MSK BITS(TIMER_CCVAL2_CCRV2_POSS,TIMER_CCVAL2_CCRV2_POSE) + +/****************** Bit definition for TIMER_CCVAL3 register ************************/ + +#define TIMER_CCVAL3_CCRV3_POSS 0U +#define TIMER_CCVAL3_CCRV3_POSE 15U +#define TIMER_CCVAL3_CCRV3_MSK BITS(TIMER_CCVAL3_CCRV3_POSS,TIMER_CCVAL3_CCRV3_POSE) + +/****************** Bit definition for TIMER_CCVAL4 register ************************/ + +#define TIMER_CCVAL4_CCRV4_POSS 0U +#define TIMER_CCVAL4_CCRV4_POSE 15U +#define TIMER_CCVAL4_CCRV4_MSK BITS(TIMER_CCVAL4_CCRV4_POSS,TIMER_CCVAL4_CCRV4_POSE) + +/****************** Bit definition for TIMER_BDCFG register ************************/ + +#define TIMER_BDCFG_GOEN_POS 15U +#define TIMER_BDCFG_GOEN_MSK BIT(TIMER_BDCFG_GOEN_POS) + +#define TIMER_BDCFG_AOEN_POS 14U +#define TIMER_BDCFG_AOEN_MSK BIT(TIMER_BDCFG_AOEN_POS) + +#define TIMER_BDCFG_BRKP_POS 13U +#define TIMER_BDCFG_BRKP_MSK BIT(TIMER_BDCFG_BRKP_POS) + +#define TIMER_BDCFG_BRKEN_POS 12U +#define TIMER_BDCFG_BRKEN_MSK BIT(TIMER_BDCFG_BRKEN_POS) + +#define TIMER_BDCFG_OFFSSR_POS 11U +#define TIMER_BDCFG_OFFSSR_MSK BIT(TIMER_BDCFG_OFFSSR_POS) + +#define TIMER_BDCFG_OFFSSI_POS 10U +#define TIMER_BDCFG_OFFSSI_MSK BIT(TIMER_BDCFG_OFFSSI_POS) + +#define TIMER_BDCFG_LOCKLVL_POSS 8U +#define TIMER_BDCFG_LOCKLVL_POSE 9U +#define TIMER_BDCFG_LOCKLVL_MSK BITS(TIMER_BDCFG_LOCKLVL_POSS,TIMER_BDCFG_LOCKLVL_POSE) + +#define TIMER_BDCFG_DT_POSS 0U +#define TIMER_BDCFG_DT_POSE 7U +#define TIMER_BDCFG_DT_MSK BITS(TIMER_BDCFG_DT_POSS,TIMER_BDCFG_DT_POSE) + +/****************** Bit definition for TIMER_DMAEN register ************************/ + +#define TIMER_DMAEN_TRGDMA_POS 6U +#define TIMER_DMAEN_TRGDMA_MSK BIT(TIMER_DMAEN_TRGDMA_POS) + +#define TIMER_DMAEN_COMD_POS 5U +#define TIMER_DMAEN_COMD_MSK BIT(TIMER_DMAEN_COMD_POS) + +#define TIMER_DMAEN_CC4D_POS 4U +#define TIMER_DMAEN_CC4D_MSK BIT(TIMER_DMAEN_CC4D_POS) + +#define TIMER_DMAEN_CC3D_POS 3U +#define TIMER_DMAEN_CC3D_MSK BIT(TIMER_DMAEN_CC3D_POS) + +#define TIMER_DMAEN_CC2D_POS 2U +#define TIMER_DMAEN_CC2D_MSK BIT(TIMER_DMAEN_CC2D_POS) + +#define TIMER_DMAEN_CC1D_POS 1U +#define TIMER_DMAEN_CC1D_MSK BIT(TIMER_DMAEN_CC1D_POS) + +#define TIMER_DMAEN_UD_POS 0U +#define TIMER_DMAEN_UD_MSK BIT(TIMER_DMAEN_UD_POS) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t SMCON; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; + __O uint32_t SGE; + __IO uint32_t CHMR1; + __IO uint32_t CHMR2; + __IO uint32_t CCEP; + __IO uint32_t COUNT; + __IO uint32_t PRES; + __IO uint32_t AR; + __IO uint32_t REPAR; + __IO uint32_t CCVAL1; + __IO uint32_t CCVAL2; + __IO uint32_t CCVAL3; + __IO uint32_t CCVAL4; + __IO uint32_t BDCFG; + __IO uint32_t DMAEN; +} TIMER_TypeDef; + +#ifdef ES32F36xx +#define TIMER0 AD16C4T0 +#define TIMER1 AD16C4T1 +#define TIMER2 GP32C4T0 +#define TIMER3 GP32C4T1 +#define TIMER4 BS16T0 +#define TIMER5 BS16T1 +#define TIMER6 GP16C4T0 +#define TIMER7 GP16C4T1 +#else +#define TIMER0 GP16C4T0 +#define TIMER1 GP16C4T1 +#define TIMER2 GP32C4T0 +#define TIMER3 GP32C4T1 +#define TIMER4 BS16T0 +#define TIMER5 BS16T1 +#define TIMER6 GP16C4T2 +#define TIMER7 GP16C4T3 +#endif + +/****************** Bit definition for USART_STAT register ************************/ + +#define USART_STAT_CTSIF_POS 9U +#define USART_STAT_CTSIF_MSK BIT(USART_STAT_CTSIF_POS) + +#define USART_STAT_TXEMPIF_POS 7U +#define USART_STAT_TXEMPIF_MSK BIT(USART_STAT_TXEMPIF_POS) + +#define USART_STAT_TXCIF_POS 6U +#define USART_STAT_TXCIF_MSK BIT(USART_STAT_TXCIF_POS) + +#define USART_STAT_RXNEIF_POS 5U +#define USART_STAT_RXNEIF_MSK BIT(USART_STAT_RXNEIF_POS) + +#define USART_STAT_IDLEIF_POS 4U +#define USART_STAT_IDLEIF_MSK BIT(USART_STAT_IDLEIF_POS) + +#define USART_STAT_OVRIF_POS 3U +#define USART_STAT_OVRIF_MSK BIT(USART_STAT_OVRIF_POS) + +#define USART_STAT_NDETIF_POS 2U +#define USART_STAT_NDETIF_MSK BIT(USART_STAT_NDETIF_POS) + +#define USART_STAT_FERRIF_POS 1U +#define USART_STAT_FERRIF_MSK BIT(USART_STAT_FERRIF_POS) + +#define USART_STAT_PERRIF_POS 0U +#define USART_STAT_PERRIF_MSK BIT(USART_STAT_PERRIF_POS) + +/****************** Bit definition for USART_DATA register ************************/ + +#define USART_DATA_VAL_POSS 0U +#define USART_DATA_VAL_POSE 8U +#define USART_DATA_VAL_MSK BITS(USART_DATA_VAL_POSS,USART_DATA_VAL_POSE) + +/****************** Bit definition for USART_BAUDCON register ************************/ + +#define USART_BAUDCON_DIV_M_POSS 4U +#define USART_BAUDCON_DIV_M_POSE 15U +#define USART_BAUDCON_DIV_M_MSK BITS(USART_BAUDCON_DIV_M_POSS,USART_BAUDCON_DIV_M_POSE) + +#define USART_BAUDCON_DIV_F_POSS 0U +#define USART_BAUDCON_DIV_F_POSE 3U +#define USART_BAUDCON_DIV_F_MSK BITS(USART_BAUDCON_DIV_F_POSS,USART_BAUDCON_DIV_F_POSE) + +/****************** Bit definition for USART_CON0 register ************************/ + +#define USART_CON0_EN_POS 13U +#define USART_CON0_EN_MSK BIT(USART_CON0_EN_POS) + +#define USART_CON0_DLEN_POS 12U +#define USART_CON0_DLEN_MSK BIT(USART_CON0_DLEN_POS) + +#define USART_CON0_WKMOD_POS 11U +#define USART_CON0_WKMOD_MSK BIT(USART_CON0_WKMOD_POS) + +#define USART_CON0_PEN_POS 10U +#define USART_CON0_PEN_MSK BIT(USART_CON0_PEN_POS) + +#define USART_CON0_PSEL_POS 9U +#define USART_CON0_PSEL_MSK BIT(USART_CON0_PSEL_POS) + +#define USART_CON0_PERRIE_POS 8U +#define USART_CON0_PERRIE_MSK BIT(USART_CON0_PERRIE_POS) + +#define USART_CON0_TXEMPIE_POS 7U +#define USART_CON0_TXEMPIE_MSK BIT(USART_CON0_TXEMPIE_POS) + +#define USART_CON0_TXCIE_POS 6U +#define USART_CON0_TXCIE_MSK BIT(USART_CON0_TXCIE_POS) + +#define USART_CON0_RXNEIE_POS 5U +#define USART_CON0_RXNEIE_MSK BIT(USART_CON0_RXNEIE_POS) + +#define USART_CON0_IDLEIE_POS 4U +#define USART_CON0_IDLEIE_MSK BIT(USART_CON0_IDLEIE_POS) + +#define USART_CON0_TXEN_POS 3U +#define USART_CON0_TXEN_MSK BIT(USART_CON0_TXEN_POS) + +#define USART_CON0_RXEN_POS 2U +#define USART_CON0_RXEN_MSK BIT(USART_CON0_RXEN_POS) + +#define USART_CON0_RXWK_POS 1U +#define USART_CON0_RXWK_MSK BIT(USART_CON0_RXWK_POS) + +/****************** Bit definition for USART_CON1 register ************************/ + +#define USART_CON1_STPLEN_POSS 12U +#define USART_CON1_STPLEN_POSE 13U +#define USART_CON1_STPLEN_MSK BITS(USART_CON1_STPLEN_POSS,USART_CON1_STPLEN_POSE) + +#define USART_CON1_SCKEN_POS 11U +#define USART_CON1_SCKEN_MSK BIT(USART_CON1_SCKEN_POS) + +#define USART_CON1_SCKPOL_POS 10U +#define USART_CON1_SCKPOL_MSK BIT(USART_CON1_SCKPOL_POS) + +#define USART_CON1_SCKPHA_POS 9U +#define USART_CON1_SCKPHA_MSK BIT(USART_CON1_SCKPHA_POS) + +#define USART_CON1_LBCP_POS 8U +#define USART_CON1_LBCP_MSK BIT(USART_CON1_LBCP_POS) + +#define USART_CON1_ADDR_POSS 0U +#define USART_CON1_ADDR_POSE 3U +#define USART_CON1_ADDR_MSK BITS(USART_CON1_ADDR_POSS,USART_CON1_ADDR_POSE) + +/****************** Bit definition for USART_CON2 register ************************/ + +#define USART_CON2_CTSIE_POS 10U +#define USART_CON2_CTSIE_MSK BIT(USART_CON2_CTSIE_POS) + +#define USART_CON2_CTSEN_POS 9U +#define USART_CON2_CTSEN_MSK BIT(USART_CON2_CTSEN_POS) + +#define USART_CON2_RTSEN_POS 8U +#define USART_CON2_RTSEN_MSK BIT(USART_CON2_RTSEN_POS) + +#define USART_CON2_TXDMAEN_POS 7U +#define USART_CON2_TXDMAEN_MSK BIT(USART_CON2_TXDMAEN_POS) + +#define USART_CON2_RXDMAEN_POS 6U +#define USART_CON2_RXDMAEN_MSK BIT(USART_CON2_RXDMAEN_POS) + +#define USART_CON2_SMARTEN_POS 5U +#define USART_CON2_SMARTEN_MSK BIT(USART_CON2_SMARTEN_POS) + +#define USART_CON2_NACK_POS 4U +#define USART_CON2_NACK_MSK BIT(USART_CON2_NACK_POS) + +#define USART_CON2_HDPSEL_POS 3U +#define USART_CON2_HDPSEL_MSK BIT(USART_CON2_HDPSEL_POS) + +#define USART_CON2_IREN_POS 1U +#define USART_CON2_IREN_MSK BIT(USART_CON2_IREN_POS) + +#define USART_CON2_ERRIE_POS 0U +#define USART_CON2_ERRIE_MSK BIT(USART_CON2_ERRIE_POS) + +/****************** Bit definition for USART_GP register ************************/ + +#define USART_GP_GTVAL_POSS 8U +#define USART_GP_GTVAL_POSE 15U +#define USART_GP_GTVAL_MSK BITS(USART_GP_GTVAL_POSS,USART_GP_GTVAL_POSE) + +#define USART_GP_PSC_POSS 0U +#define USART_GP_PSC_POSE 7U +#define USART_GP_PSC_MSK BITS(USART_GP_PSC_POSS,USART_GP_PSC_POSE) + +typedef struct +{ + __IO uint32_t STAT; + __IO uint32_t DATA; + __IO uint32_t BAUDCON; + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t GP; +} USART_TypeDef; + +/****************** Bit definition for UART_RXBUF register ************************/ + +#define UART_RXBUF_RXBUF_POSS 0U +#define UART_RXBUF_RXBUF_POSE 8U +#define UART_RXBUF_RXBUF_MSK BITS(UART_RXBUF_RXBUF_POSS,UART_RXBUF_RXBUF_POSE) + +/****************** Bit definition for UART_TXBUF register ************************/ + +#define UART_TXBUF_TXBUF_POSS 0U +#define UART_TXBUF_TXBUF_POSE 8U +#define UART_TXBUF_TXBUF_MSK BITS(UART_TXBUF_TXBUF_POSS,UART_TXBUF_TXBUF_POSE) + +/****************** Bit definition for UART_BRR register ************************/ + +#define UART_BRR_BRR_POSS 0U +#define UART_BRR_BRR_POSE 15U +#define UART_BRR_BRR_MSK BITS(UART_BRR_BRR_POSS,UART_BRR_BRR_POSE) + +/****************** Bit definition for UART_LCON register ************************/ + +#define UART_LCON_TXEN_POS 15U +#define UART_LCON_TXEN_MSK BIT(UART_LCON_TXEN_POS) + +#define UART_LCON_RXEN_POS 14U +#define UART_LCON_RXEN_MSK BIT(UART_LCON_RXEN_POS) + +#define UART_LCON_DBCEN_POS 13U +#define UART_LCON_DBCEN_MSK BIT(UART_LCON_DBCEN_POS) + +#define UART_LCON_BREAK_POS 10U +#define UART_LCON_BREAK_MSK BIT(UART_LCON_BREAK_POS) + +#define UART_LCON_SWAP_POS 9U +#define UART_LCON_SWAP_MSK BIT(UART_LCON_SWAP_POS) + +#define UART_LCON_TXINV_POS 8U +#define UART_LCON_TXINV_MSK BIT(UART_LCON_TXINV_POS) + +#define UART_LCON_RXINV_POS 7U +#define UART_LCON_RXINV_MSK BIT(UART_LCON_RXINV_POS) + +#define UART_LCON_DATAINV_POS 6U +#define UART_LCON_DATAINV_MSK BIT(UART_LCON_DATAINV_POS) + +#define UART_LCON_MSB_POS 5U +#define UART_LCON_MSB_MSK BIT(UART_LCON_MSB_POS) + +#define UART_LCON_PS_POS 4U +#define UART_LCON_PS_MSK BIT(UART_LCON_PS_POS) + +#define UART_LCON_PE_POS 3U +#define UART_LCON_PE_MSK BIT(UART_LCON_PE_POS) + +#define UART_LCON_STOP_POS 2U +#define UART_LCON_STOP_MSK BIT(UART_LCON_STOP_POS) + +#define UART_LCON_DLS_POSS 0U +#define UART_LCON_DLS_POSE 1U +#define UART_LCON_DLS_MSK BITS(UART_LCON_DLS_POSS,UART_LCON_DLS_POSE) + +/****************** Bit definition for UART_MCON register ************************/ + +#define UART_MCON_TXDMAEN_POS 15U +#define UART_MCON_TXDMAEN_MSK BIT(UART_MCON_TXDMAEN_POS) + +#define UART_MCON_RXDMAEN_POS 14U +#define UART_MCON_RXDMAEN_MSK BIT(UART_MCON_RXDMAEN_POS) + +#define UART_MCON_ABRREPT_POS 11U +#define UART_MCON_ABRREPT_MSK BIT(UART_MCON_ABRREPT_POS) + +#define UART_MCON_ABRMOD_POSS 9U +#define UART_MCON_ABRMOD_POSE 10U +#define UART_MCON_ABRMOD_MSK BITS(UART_MCON_ABRMOD_POSS,UART_MCON_ABRMOD_POSE) + +#define UART_MCON_ABREN_POS 8U +#define UART_MCON_ABREN_MSK BIT(UART_MCON_ABREN_POS) + +#define UART_MCON_BKREQ_POS 5U +#define UART_MCON_BKREQ_MSK BIT(UART_MCON_BKREQ_POS) + +#define UART_MCON_HDEN_POS 4U +#define UART_MCON_HDEN_MSK BIT(UART_MCON_HDEN_POS) + +#define UART_MCON_IREN_POS 3U +#define UART_MCON_IREN_MSK BIT(UART_MCON_IREN_POS) + +#define UART_MCON_AFCEN_POS 2U +#define UART_MCON_AFCEN_MSK BIT(UART_MCON_AFCEN_POS) + +#define UART_MCON_RTSSET_POS 1U +#define UART_MCON_RTSSET_MSK BIT(UART_MCON_RTSSET_POS) + +#define UART_MCON_LPBKEN_POS 0U +#define UART_MCON_LPBKEN_MSK BIT(UART_MCON_LPBKEN_POS) + +/****************** Bit definition for UART_RS485 register ************************/ + +#define UART_RS485_DLY_POSS 16U +#define UART_RS485_DLY_POSE 23U +#define UART_RS485_DLY_MSK BITS(UART_RS485_DLY_POSS,UART_RS485_DLY_POSE) + +#define UART_RS485_ADDR_POSS 8U +#define UART_RS485_ADDR_POSE 15U +#define UART_RS485_ADDR_MSK BITS(UART_RS485_ADDR_POSS,UART_RS485_ADDR_POSE) + +#define UART_RS485_AADINV_POS 3U +#define UART_RS485_AADINV_MSK BIT(UART_RS485_AADINV_POS) + +#define UART_RS485_AADACEN_POS 2U +#define UART_RS485_AADACEN_MSK BIT(UART_RS485_AADACEN_POS) + +#define UART_RS485_AADNEN_POS 1U +#define UART_RS485_AADNEN_MSK BIT(UART_RS485_AADNEN_POS) + +#define UART_RS485_AADEN_POS 0U +#define UART_RS485_AADEN_MSK BIT(UART_RS485_AADEN_POS) + +/****************** Bit definition for UART_SCARD register ************************/ + +#define UART_SCARD_BLEN_POSS 24U +#define UART_SCARD_BLEN_POSE 31U +#define UART_SCARD_BLEN_MSK BITS(UART_SCARD_BLEN_POSS,UART_SCARD_BLEN_POSE) + +#define UART_SCARD_GT_POSS 16U +#define UART_SCARD_GT_POSE 23U +#define UART_SCARD_GT_MSK BITS(UART_SCARD_GT_POSS,UART_SCARD_GT_POSE) + +#define UART_SCARD_PSC_POSS 8U +#define UART_SCARD_PSC_POSE 15U +#define UART_SCARD_PSC_MSK BITS(UART_SCARD_PSC_POSS,UART_SCARD_PSC_POSE) + +#define UART_SCARD_SCCNT_POSS 3U +#define UART_SCARD_SCCNT_POSE 5U +#define UART_SCARD_SCCNT_MSK BITS(UART_SCARD_SCCNT_POSS,UART_SCARD_SCCNT_POSE) + +#define UART_SCARD_SCLKEN_POS 2U +#define UART_SCARD_SCLKEN_MSK BIT(UART_SCARD_SCLKEN_POS) + +#define UART_SCARD_SCNACK_POS 1U +#define UART_SCARD_SCNACK_MSK BIT(UART_SCARD_SCNACK_POS) + +#define UART_SCARD_SCEN_POS 0U +#define UART_SCARD_SCEN_MSK BIT(UART_SCARD_SCEN_POS) + +/****************** Bit definition for UART_LIN register ************************/ + +#define UART_LIN_LINBKREQ_POS 2U +#define UART_LIN_LINBKREQ_MSK BIT(UART_LIN_LINBKREQ_POS) + +#define UART_LIN_LINBDL_POS 1U +#define UART_LIN_LINBDL_MSK BIT(UART_LIN_LINBDL_POS) + +#define UART_LIN_LINEN_POS 0U +#define UART_LIN_LINEN_MSK BIT(UART_LIN_LINEN_POS) + +/****************** Bit definition for UART_RTOR register ************************/ + +#define UART_RTOR_RTOEN_POS 24U +#define UART_RTOR_RTOEN_MSK BIT(UART_RTOR_RTOEN_POS) + +#define UART_RTOR_RTO_POSS 0U +#define UART_RTOR_RTO_POSE 23U +#define UART_RTOR_RTO_MSK BITS(UART_RTOR_RTO_POSS,UART_RTOR_RTO_POSE) + +/****************** Bit definition for UART_FCON register ************************/ + +#define UART_FCON_TXFL_POSS 11U +#define UART_FCON_TXFL_POSE 15U +#define UART_FCON_TXFL_MSK BITS(UART_FCON_TXFL_POSS,UART_FCON_TXFL_POSE) + +#define UART_FCON_TXTH_POSS 9U +#define UART_FCON_TXTH_POSE 10U +#define UART_FCON_TXTH_MSK BITS(UART_FCON_TXTH_POSS,UART_FCON_TXTH_POSE) + +#define UART_FCON_TFRST_POS 8U +#define UART_FCON_TFRST_MSK BIT(UART_FCON_TFRST_POS) + +#define UART_FCON_RXFL_POSS 3U +#define UART_FCON_RXFL_POSE 7U +#define UART_FCON_RXFL_MSK BITS(UART_FCON_RXFL_POSS,UART_FCON_RXFL_POSE) + +#define UART_FCON_RXTH_POSS 1U +#define UART_FCON_RXTH_POSE 2U +#define UART_FCON_RXTH_MSK BITS(UART_FCON_RXTH_POSS,UART_FCON_RXTH_POSE) + +#define UART_FCON_RFRST_POS 0U +#define UART_FCON_RFRST_MSK BIT(UART_FCON_RFRST_POS) + +/****************** Bit definition for UART_STAT register ************************/ + +#define UART_STAT_TFOERR_POS 18U +#define UART_STAT_TFOERR_MSK BIT(UART_STAT_TFOERR_POS) + +#define UART_STAT_TFFULL_POS 17U +#define UART_STAT_TFFULL_MSK BIT(UART_STAT_TFFULL_POS) + +#define UART_STAT_TFEMPTY_POS 16U +#define UART_STAT_TFEMPTY_MSK BIT(UART_STAT_TFEMPTY_POS) + +#define UART_STAT_TFTH_POS 15U +#define UART_STAT_TFTH_MSK BIT(UART_STAT_TFTH_POS) + +#define UART_STAT_TSBUSY_POS 14U +#define UART_STAT_TSBUSY_MSK BIT(UART_STAT_TSBUSY_POS) + +#define UART_STAT_RFUERR_POS 13U +#define UART_STAT_RFUERR_MSK BIT(UART_STAT_RFUERR_POS) + +#define UART_STAT_RFOERR_POS 12U +#define UART_STAT_RFOERR_MSK BIT(UART_STAT_RFOERR_POS) + +#define UART_STAT_RFFULL_POS 11U +#define UART_STAT_RFFULL_MSK BIT(UART_STAT_RFFULL_POS) + +#define UART_STAT_RFEMPTY_POS 10U +#define UART_STAT_RFEMPTY_MSK BIT(UART_STAT_RFEMPTY_POS) + +#define UART_STAT_RFTH_POS 9U +#define UART_STAT_RFTH_MSK BIT(UART_STAT_RFTH_POS) + +#define UART_STAT_RSBUSY_POS 8U +#define UART_STAT_RSBUSY_MSK BIT(UART_STAT_RSBUSY_POS) + +#define UART_STAT_CTSSTA_POS 3U +#define UART_STAT_CTSSTA_MSK BIT(UART_STAT_CTSSTA_POS) + +#define UART_STAT_BKERR_POS 2U +#define UART_STAT_BKERR_MSK BIT(UART_STAT_BKERR_POS) + +#define UART_STAT_FERR_POS 1U +#define UART_STAT_FERR_MSK BIT(UART_STAT_FERR_POS) + +#define UART_STAT_PERR_POS 0U +#define UART_STAT_PERR_MSK BIT(UART_STAT_PERR_POS) + +/****************** Bit definition for UART_IER register ************************/ + +#define UART_IER_TFOVER_POS 18U +#define UART_IER_TFOVER_MSK BIT(UART_IER_TFOVER_POS) + +#define UART_IER_TFEMPTY_POS 16U +#define UART_IER_TFEMPTY_MSK BIT(UART_IER_TFEMPTY_POS) + +#define UART_IER_TFTH_POS 15U +#define UART_IER_TFTH_MSK BIT(UART_IER_TFTH_POS) + +#define UART_IER_TBC_POS 14U +#define UART_IER_TBC_MSK BIT(UART_IER_TBC_POS) + +#define UART_IER_RFUERR_POS 13U +#define UART_IER_RFUERR_MSK BIT(UART_IER_RFUERR_POS) + +#define UART_IER_RFOERR_POS 12U +#define UART_IER_RFOERR_MSK BIT(UART_IER_RFOERR_POS) + +#define UART_IER_RFFULL_POS 11U +#define UART_IER_RFFULL_MSK BIT(UART_IER_RFFULL_POS) + +#define UART_IER_RFTH_POS 9U +#define UART_IER_RFTH_MSK BIT(UART_IER_RFTH_POS) + +#define UART_IER_NOISE_POS 8U +#define UART_IER_NOISE_MSK BIT(UART_IER_NOISE_POS) + +#define UART_IER_EOB_POS 7U +#define UART_IER_EOB_MSK BIT(UART_IER_EOB_POS) + +#define UART_IER_LINBK_POS 6U +#define UART_IER_LINBK_MSK BIT(UART_IER_LINBK_POS) + +#define UART_IER_ADDRM_POS 5U +#define UART_IER_ADDRM_MSK BIT(UART_IER_ADDRM_POS) + +#define UART_IER_RXTO_POS 4U +#define UART_IER_RXTO_MSK BIT(UART_IER_RXTO_POS) + +#define UART_IER_DCTS_POS 3U +#define UART_IER_DCTS_MSK BIT(UART_IER_DCTS_POS) + +#define UART_IER_ABTO_POS 2U +#define UART_IER_ABTO_MSK BIT(UART_IER_ABTO_POS) + +#define UART_IER_ABEND_POS 1U +#define UART_IER_ABEND_MSK BIT(UART_IER_ABEND_POS) + +#define UART_IER_RXBERR_POS 0U +#define UART_IER_RXBERR_MSK BIT(UART_IER_RXBERR_POS) + +/****************** Bit definition for UART_IDR register ************************/ + +#define UART_IDR_TFOVER_POS 18U +#define UART_IDR_TFOVER_MSK BIT(UART_IDR_TFOVER_POS) + +#define UART_IDR_TFEMPTY_POS 16U +#define UART_IDR_TFEMPTY_MSK BIT(UART_IDR_TFEMPTY_POS) + +#define UART_IDR_TFTH_POS 15U +#define UART_IDR_TFTH_MSK BIT(UART_IDR_TFTH_POS) + +#define UART_IDR_TBC_POS 14U +#define UART_IDR_TBC_MSK BIT(UART_IDR_TBC_POS) + +#define UART_IDR_RFUERR_POS 13U +#define UART_IDR_RFUERR_MSK BIT(UART_IDR_RFUERR_POS) + +#define UART_IDR_RFOERR_POS 12U +#define UART_IDR_RFOERR_MSK BIT(UART_IDR_RFOERR_POS) + +#define UART_IDR_RFFULL_POS 11U +#define UART_IDR_RFFULL_MSK BIT(UART_IDR_RFFULL_POS) + +#define UART_IDR_RFTH_POS 9U +#define UART_IDR_RFTH_MSK BIT(UART_IDR_RFTH_POS) + +#define UART_IDR_NOISE_POS 8U +#define UART_IDR_NOISE_MSK BIT(UART_IDR_NOISE_POS) + +#define UART_IDR_EOB_POS 7U +#define UART_IDR_EOB_MSK BIT(UART_IDR_EOB_POS) + +#define UART_IDR_LINBK_POS 6U +#define UART_IDR_LINBK_MSK BIT(UART_IDR_LINBK_POS) + +#define UART_IDR_ADDRM_POS 5U +#define UART_IDR_ADDRM_MSK BIT(UART_IDR_ADDRM_POS) + +#define UART_IDR_RXTO_POS 4U +#define UART_IDR_RXTO_MSK BIT(UART_IDR_RXTO_POS) + +#define UART_IDR_DCTS_POS 3U +#define UART_IDR_DCTS_MSK BIT(UART_IDR_DCTS_POS) + +#define UART_IDR_ABTO_POS 2U +#define UART_IDR_ABTO_MSK BIT(UART_IDR_ABTO_POS) + +#define UART_IDR_ABEND_POS 1U +#define UART_IDR_ABEND_MSK BIT(UART_IDR_ABEND_POS) + +#define UART_IDR_RXBERR_POS 0U +#define UART_IDR_RXBERR_MSK BIT(UART_IDR_RXBERR_POS) + +/****************** Bit definition for UART_IVS register ************************/ + +#define UART_IVS_TFOVER_POS 18U +#define UART_IVS_TFOVER_MSK BIT(UART_IVS_TFOVER_POS) + +#define UART_IVS_TFEMPTY_POS 16U +#define UART_IVS_TFEMPTY_MSK BIT(UART_IVS_TFEMPTY_POS) + +#define UART_IVS_TFTH_POS 15U +#define UART_IVS_TFTH_MSK BIT(UART_IVS_TFTH_POS) + +#define UART_IVS_TBC_POS 14U +#define UART_IVS_TBC_MSK BIT(UART_IVS_TBC_POS) + +#define UART_IVS_RFUERR_POS 13U +#define UART_IVS_RFUERR_MSK BIT(UART_IVS_RFUERR_POS) + +#define UART_IVS_RFOERR_POS 12U +#define UART_IVS_RFOERR_MSK BIT(UART_IVS_RFOERR_POS) + +#define UART_IVS_RFFULL_POS 11U +#define UART_IVS_RFFULL_MSK BIT(UART_IVS_RFFULL_POS) + +#define UART_IVS_RFTH_POS 9U +#define UART_IVS_RFTH_MSK BIT(UART_IVS_RFTH_POS) + +#define UART_IVS_NOISE_POS 8U +#define UART_IVS_NOISE_MSK BIT(UART_IVS_NOISE_POS) + +#define UART_IVS_EOB_POS 7U +#define UART_IVS_EOB_MSK BIT(UART_IVS_EOB_POS) + +#define UART_IVS_LINBK_POS 6U +#define UART_IVS_LINBK_MSK BIT(UART_IVS_LINBK_POS) + +#define UART_IVS_ADDRM_POS 5U +#define UART_IVS_ADDRM_MSK BIT(UART_IVS_ADDRM_POS) + +#define UART_IVS_RXTO_POS 4U +#define UART_IVS_RXTO_MSK BIT(UART_IVS_RXTO_POS) + +#define UART_IVS_DCTS_POS 3U +#define UART_IVS_DCTS_MSK BIT(UART_IVS_DCTS_POS) + +#define UART_IVS_ABTO_POS 2U +#define UART_IVS_ABTO_MSK BIT(UART_IVS_ABTO_POS) + +#define UART_IVS_ABEND_POS 1U +#define UART_IVS_ABEND_MSK BIT(UART_IVS_ABEND_POS) + +#define UART_IVS_RXBERR_POS 0U +#define UART_IVS_RXBERR_MSK BIT(UART_IVS_RXBERR_POS) + +/****************** Bit definition for UART_RIF register ************************/ + +#define UART_RIF_TFOVER_POS 18U +#define UART_RIF_TFOVER_MSK BIT(UART_RIF_TFOVER_POS) + +#define UART_RIF_TFEMPTY_POS 16U +#define UART_RIF_TFEMPTY_MSK BIT(UART_RIF_TFEMPTY_POS) + +#define UART_RIF_TFTH_POS 15U +#define UART_RIF_TFTH_MSK BIT(UART_RIF_TFTH_POS) + +#define UART_RIF_TBC_POS 14U +#define UART_RIF_TBC_MSK BIT(UART_RIF_TBC_POS) + +#define UART_RIF_RFUERR_POS 13U +#define UART_RIF_RFUERR_MSK BIT(UART_RIF_RFUERR_POS) + +#define UART_RIF_RFOERR_POS 12U +#define UART_RIF_RFOERR_MSK BIT(UART_RIF_RFOERR_POS) + +#define UART_RIF_RFFULL_POS 11U +#define UART_RIF_RFFULL_MSK BIT(UART_RIF_RFFULL_POS) + +#define UART_RIF_RFTH_POS 9U +#define UART_RIF_RFTH_MSK BIT(UART_RIF_RFTH_POS) + +#define UART_RIF_NOISE_POS 8U +#define UART_RIF_NOISE_MSK BIT(UART_RIF_NOISE_POS) + +#define UART_RIF_EOB_POS 7U +#define UART_RIF_EOB_MSK BIT(UART_RIF_EOB_POS) + +#define UART_RIF_LINBK_POS 6U +#define UART_RIF_LINBK_MSK BIT(UART_RIF_LINBK_POS) + +#define UART_RIF_ADDRM_POS 5U +#define UART_RIF_ADDRM_MSK BIT(UART_RIF_ADDRM_POS) + +#define UART_RIF_RXTO_POS 4U +#define UART_RIF_RXTO_MSK BIT(UART_RIF_RXTO_POS) + +#define UART_RIF_DCTS_POS 3U +#define UART_RIF_DCTS_MSK BIT(UART_RIF_DCTS_POS) + +#define UART_RIF_ABTO_POS 2U +#define UART_RIF_ABTO_MSK BIT(UART_RIF_ABTO_POS) + +#define UART_RIF_ABEND_POS 1U +#define UART_RIF_ABEND_MSK BIT(UART_RIF_ABEND_POS) + +#define UART_RIF_RXBERR_POS 0U +#define UART_RIF_RXBERR_MSK BIT(UART_RIF_RXBERR_POS) + +/****************** Bit definition for UART_IFM register ************************/ + +#define UART_IFM_TFOVER_POS 18U +#define UART_IFM_TFOVER_MSK BIT(UART_IFM_TFOVER_POS) + +#define UART_IFM_TFEMPTY_POS 16U +#define UART_IFM_TFEMPTY_MSK BIT(UART_IFM_TFEMPTY_POS) + +#define UART_IFM_TFTH_POS 15U +#define UART_IFM_TFTH_MSK BIT(UART_IFM_TFTH_POS) + +#define UART_IFM_TBC_POS 14U +#define UART_IFM_TBC_MSK BIT(UART_IFM_TBC_POS) + +#define UART_IFM_RFUERR_POS 13U +#define UART_IFM_RFUERR_MSK BIT(UART_IFM_RFUERR_POS) + +#define UART_IFM_RFOERR_POS 12U +#define UART_IFM_RFOERR_MSK BIT(UART_IFM_RFOERR_POS) + +#define UART_IFM_RFFULL_POS 11U +#define UART_IFM_RFFULL_MSK BIT(UART_IFM_RFFULL_POS) + +#define UART_IFM_RFTH_POS 9U +#define UART_IFM_RFTH_MSK BIT(UART_IFM_RFTH_POS) + +#define UART_IFM_NOISE_POS 8U +#define UART_IFM_NOISE_MSK BIT(UART_IFM_NOISE_POS) + +#define UART_IFM_EOB_POS 7U +#define UART_IFM_EOB_MSK BIT(UART_IFM_EOB_POS) + +#define UART_IFM_LINBK_POS 6U +#define UART_IFM_LINBK_MSK BIT(UART_IFM_LINBK_POS) + +#define UART_IFM_ADDRM_POS 5U +#define UART_IFM_ADDRM_MSK BIT(UART_IFM_ADDRM_POS) + +#define UART_IFM_RXTO_POS 4U +#define UART_IFM_RXTO_MSK BIT(UART_IFM_RXTO_POS) + +#define UART_IFM_DCTS_POS 3U +#define UART_IFM_DCTS_MSK BIT(UART_IFM_DCTS_POS) + +#define UART_IFM_ABTO_POS 2U +#define UART_IFM_ABTO_MSK BIT(UART_IFM_ABTO_POS) + +#define UART_IFM_ABEND_POS 1U +#define UART_IFM_ABEND_MSK BIT(UART_IFM_ABEND_POS) + +#define UART_IFM_RXBERR_POS 0U +#define UART_IFM_RXBERR_MSK BIT(UART_IFM_RXBERR_POS) + +/****************** Bit definition for UART_ICR register ************************/ + +#define UART_ICR_TFOVER_POS 18U +#define UART_ICR_TFOVER_MSK BIT(UART_ICR_TFOVER_POS) + +#define UART_ICR_TFEMPTY_POS 16U +#define UART_ICR_TFEMPTY_MSK BIT(UART_ICR_TFEMPTY_POS) + +#define UART_ICR_TFTH_POS 15U +#define UART_ICR_TFTH_MSK BIT(UART_ICR_TFTH_POS) + +#define UART_ICR_TBC_POS 14U +#define UART_ICR_TBC_MSK BIT(UART_ICR_TBC_POS) + +#define UART_ICR_RFUERR_POS 13U +#define UART_ICR_RFUERR_MSK BIT(UART_ICR_RFUERR_POS) + +#define UART_ICR_RFOERR_POS 12U +#define UART_ICR_RFOERR_MSK BIT(UART_ICR_RFOERR_POS) + +#define UART_ICR_RFFULL_POS 11U +#define UART_ICR_RFFULL_MSK BIT(UART_ICR_RFFULL_POS) + +#define UART_ICR_RFTH_POS 9U +#define UART_ICR_RFTH_MSK BIT(UART_ICR_RFTH_POS) + +#define UART_ICR_NOISE_POS 8U +#define UART_ICR_NOISE_MSK BIT(UART_ICR_NOISE_POS) + +#define UART_ICR_EOB_POS 7U +#define UART_ICR_EOB_MSK BIT(UART_ICR_EOB_POS) + +#define UART_ICR_LINBK_POS 6U +#define UART_ICR_LINBK_MSK BIT(UART_ICR_LINBK_POS) + +#define UART_ICR_ADDRM_POS 5U +#define UART_ICR_ADDRM_MSK BIT(UART_ICR_ADDRM_POS) + +#define UART_ICR_RXTO_POS 4U +#define UART_ICR_RXTO_MSK BIT(UART_ICR_RXTO_POS) + +#define UART_ICR_DCTS_POS 3U +#define UART_ICR_DCTS_MSK BIT(UART_ICR_DCTS_POS) + +#define UART_ICR_ABTO_POS 2U +#define UART_ICR_ABTO_MSK BIT(UART_ICR_ABTO_POS) + +#define UART_ICR_ABEND_POS 1U +#define UART_ICR_ABEND_MSK BIT(UART_ICR_ABEND_POS) + +#define UART_ICR_RXBERR_POS 0U +#define UART_ICR_RXBERR_MSK BIT(UART_ICR_RXBERR_POS) + +typedef struct +{ + __I uint32_t RXBUF; + __IO uint32_t TXBUF; + __IO uint32_t BRR; + __IO uint32_t LCON; + __IO uint32_t MCON; + __IO uint32_t RS485; + __IO uint32_t SCARD; + __IO uint32_t LIN; + __IO uint32_t RTOR; + __O uint32_t FCON; + __I uint32_t STAT; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} UART_TypeDef; + +/****************** Bit definition for SPI_CON1 register ************************/ + +#define SPI_CON1_BIDEN_POS 15U +#define SPI_CON1_BIDEN_MSK BIT(SPI_CON1_BIDEN_POS) + +#define SPI_CON1_BIDOEN_POS 14U +#define SPI_CON1_BIDOEN_MSK BIT(SPI_CON1_BIDOEN_POS) + +#define SPI_CON1_CRCEN_POS 13U +#define SPI_CON1_CRCEN_MSK BIT(SPI_CON1_CRCEN_POS) + +#define SPI_CON1_NXTCRC_POS 12U +#define SPI_CON1_NXTCRC_MSK BIT(SPI_CON1_NXTCRC_POS) + +#define SPI_CON1_FLEN_POS 11U +#define SPI_CON1_FLEN_MSK BIT(SPI_CON1_FLEN_POS) + +#define SPI_CON1_RXO_POS 10U +#define SPI_CON1_RXO_MSK BIT(SPI_CON1_RXO_POS) + +#define SPI_CON1_SSEN_POS 9U +#define SPI_CON1_SSEN_MSK BIT(SPI_CON1_SSEN_POS) + +#define SPI_CON1_SSOUT_POS 8U +#define SPI_CON1_SSOUT_MSK BIT(SPI_CON1_SSOUT_POS) + +#define SPI_CON1_LSBFST_POS 7U +#define SPI_CON1_LSBFST_MSK BIT(SPI_CON1_LSBFST_POS) + +#define SPI_CON1_SPIEN_POS 6U +#define SPI_CON1_SPIEN_MSK BIT(SPI_CON1_SPIEN_POS) + +#define SPI_CON1_BAUD_POSS 3U +#define SPI_CON1_BAUD_POSE 5U +#define SPI_CON1_BAUD_MSK BITS(SPI_CON1_BAUD_POSS,SPI_CON1_BAUD_POSE) + +#define SPI_CON1_MSTREN_POS 2U +#define SPI_CON1_MSTREN_MSK BIT(SPI_CON1_MSTREN_POS) + +#define SPI_CON1_CPOL_POS 1U +#define SPI_CON1_CPOL_MSK BIT(SPI_CON1_CPOL_POS) + +#define SPI_CON1_CPHA_POS 0U +#define SPI_CON1_CPHA_MSK BIT(SPI_CON1_CPHA_POS) + +/****************** Bit definition for SPI_CON2 register ************************/ + +#define SPI_CON2_RXFTH_POSS 14U +#define SPI_CON2_RXFTH_POSE 15U +#define SPI_CON2_RXFTH_MSK BITS(SPI_CON2_RXFTH_POSS,SPI_CON2_RXFTH_POSE) + +#define SPI_CON2_TXFTH_POSS 12U +#define SPI_CON2_TXFTH_POSE 13U +#define SPI_CON2_TXFTH_MSK BITS(SPI_CON2_TXFTH_POSS,SPI_CON2_TXFTH_POSE) + +#define SPI_CON2_FRF_POS 4U +#define SPI_CON2_FRF_MSK BIT(SPI_CON2_FRF_POS) + +#define SPI_CON2_NSSP_POS 3U +#define SPI_CON2_NSSP_MSK BIT(SPI_CON2_NSSP_POS) + +#define SPI_CON2_NSSOE_POS 2U +#define SPI_CON2_NSSOE_MSK BIT(SPI_CON2_NSSOE_POS) + +#define SPI_CON2_TXDMA_POS 1U +#define SPI_CON2_TXDMA_MSK BIT(SPI_CON2_TXDMA_POS) + +#define SPI_CON2_RXDMA_POS 0U +#define SPI_CON2_RXDMA_MSK BIT(SPI_CON2_RXDMA_POS) + +/****************** Bit definition for SPI_STAT register ************************/ + +#define SPI_STAT_RXFLV_POSS 24U +#define SPI_STAT_RXFLV_POSE 28U +#define SPI_STAT_RXFLV_MSK BITS(SPI_STAT_RXFLV_POSS,SPI_STAT_RXFLV_POSE) + +#define SPI_STAT_TXFLV_POSS 16U +#define SPI_STAT_TXFLV_POSE 20U +#define SPI_STAT_TXFLV_MSK BITS(SPI_STAT_TXFLV_POSS,SPI_STAT_TXFLV_POSE) + +#define SPI_STAT_BUSY_POS 15U +#define SPI_STAT_BUSY_MSK BIT(SPI_STAT_BUSY_POS) + +#define SPI_STAT_CHSIDE_POS 14U +#define SPI_STAT_CHSIDE_MSK BIT(SPI_STAT_CHSIDE_POS) + +#define SPI_STAT_RXTH_POS 12U +#define SPI_STAT_RXTH_MSK BIT(SPI_STAT_RXTH_POS) + +#define SPI_STAT_RXUD_POS 11U +#define SPI_STAT_RXUD_MSK BIT(SPI_STAT_RXUD_POS) + +#define SPI_STAT_RXOV_POS 10U +#define SPI_STAT_RXOV_MSK BIT(SPI_STAT_RXOV_POS) + +#define SPI_STAT_RXF_POS 9U +#define SPI_STAT_RXF_MSK BIT(SPI_STAT_RXF_POS) + +#define SPI_STAT_RXE_POS 8U +#define SPI_STAT_RXE_MSK BIT(SPI_STAT_RXE_POS) + +#define SPI_STAT_TXTH_POS 4U +#define SPI_STAT_TXTH_MSK BIT(SPI_STAT_TXTH_POS) + +#define SPI_STAT_TXUD_POS 3U +#define SPI_STAT_TXUD_MSK BIT(SPI_STAT_TXUD_POS) + +#define SPI_STAT_TXOV_POS 2U +#define SPI_STAT_TXOV_MSK BIT(SPI_STAT_TXOV_POS) + +#define SPI_STAT_TXF_POS 1U +#define SPI_STAT_TXF_MSK BIT(SPI_STAT_TXF_POS) + +#define SPI_STAT_TXE_POS 0U +#define SPI_STAT_TXE_MSK BIT(SPI_STAT_TXE_POS) + +/****************** Bit definition for SPI_DATA register ************************/ + +#define SPI_DATA_DATA_POSS 0U +#define SPI_DATA_DATA_POSE 15U +#define SPI_DATA_DATA_MSK BITS(SPI_DATA_DATA_POSS,SPI_DATA_DATA_POSE) + +/****************** Bit definition for SPI_CRCPOLY register ************************/ + +#define SPI_CRCPOLY_CRCPOLY_POSS 0U +#define SPI_CRCPOLY_CRCPOLY_POSE 15U +#define SPI_CRCPOLY_CRCPOLY_MSK BITS(SPI_CRCPOLY_CRCPOLY_POSS,SPI_CRCPOLY_CRCPOLY_POSE) + +/****************** Bit definition for SPI_RXCRC register ************************/ + +#define SPI_RXCRC_RXCRC_POSS 0U +#define SPI_RXCRC_RXCRC_POSE 15U +#define SPI_RXCRC_RXCRC_MSK BITS(SPI_RXCRC_RXCRC_POSS,SPI_RXCRC_RXCRC_POSE) + +/****************** Bit definition for SPI_TXCRC register ************************/ + +#define SPI_TXCRC_TXCRC_POSS 0U +#define SPI_TXCRC_TXCRC_POSE 15U +#define SPI_TXCRC_TXCRC_MSK BITS(SPI_TXCRC_TXCRC_POSS,SPI_TXCRC_TXCRC_POSE) + +/****************** Bit definition for SPI_I2SCFG register ************************/ + +#define SPI_I2SCFG_I2SMOD_POS 11U +#define SPI_I2SCFG_I2SMOD_MSK BIT(SPI_I2SCFG_I2SMOD_POS) + +#define SPI_I2SCFG_I2SE_POS 10U +#define SPI_I2SCFG_I2SE_MSK BIT(SPI_I2SCFG_I2SE_POS) + +#define SPI_I2SCFG_I2SCFG_POSS 8U +#define SPI_I2SCFG_I2SCFG_POSE 9U +#define SPI_I2SCFG_I2SCFG_MSK BITS(SPI_I2SCFG_I2SCFG_POSS,SPI_I2SCFG_I2SCFG_POSE) + +#define SPI_I2SCFG_PCMSYNC_POS 7U +#define SPI_I2SCFG_PCMSYNC_MSK BIT(SPI_I2SCFG_PCMSYNC_POS) + +#define SPI_I2SCFG_I2SSTD_POSS 4U +#define SPI_I2SCFG_I2SSTD_POSE 5U +#define SPI_I2SCFG_I2SSTD_MSK BITS(SPI_I2SCFG_I2SSTD_POSS,SPI_I2SCFG_I2SSTD_POSE) + +#define SPI_I2SCFG_CKPOL_POS 3U +#define SPI_I2SCFG_CKPOL_MSK BIT(SPI_I2SCFG_CKPOL_POS) + +#define SPI_I2SCFG_DATLEN_POSS 1U +#define SPI_I2SCFG_DATLEN_POSE 2U +#define SPI_I2SCFG_DATLEN_MSK BITS(SPI_I2SCFG_DATLEN_POSS,SPI_I2SCFG_DATLEN_POSE) + +#define SPI_I2SCFG_CHLEN_POS 0U +#define SPI_I2SCFG_CHLEN_MSK BIT(SPI_I2SCFG_CHLEN_POS) + +/****************** Bit definition for SPI_I2SPR register ************************/ + +#define SPI_I2SPR_EXTCKEN_POS 10U +#define SPI_I2SPR_EXTCKEN_MSK BIT(SPI_I2SPR_EXTCKEN_POS) + +#define SPI_I2SPR_MCKOE_POS 9U +#define SPI_I2SPR_MCKOE_MSK BIT(SPI_I2SPR_MCKOE_POS) + +#define SPI_I2SPR_ODD_POS 8U +#define SPI_I2SPR_ODD_MSK BIT(SPI_I2SPR_ODD_POS) + +#define SPI_I2SPR_I2SDIV_POSS 0U +#define SPI_I2SPR_I2SDIV_POSE 7U +#define SPI_I2SPR_I2SDIV_MSK BITS(SPI_I2SPR_I2SDIV_POSS,SPI_I2SPR_I2SDIV_POSE) + +/****************** Bit definition for SPI_IER register ************************/ + +#define SPI_IER_FREIE_POS 18U +#define SPI_IER_FREIE_MSK BIT(SPI_IER_FREIE_POS) + +#define SPI_IER_MODFIE_POS 17U +#define SPI_IER_MODFIE_MSK BIT(SPI_IER_MODFIE_POS) + +#define SPI_IER_CRCERRIE_POS 16U +#define SPI_IER_CRCERRIE_MSK BIT(SPI_IER_CRCERRIE_POS) + +#define SPI_IER_RXTHIE_POS 12U +#define SPI_IER_RXTHIE_MSK BIT(SPI_IER_RXTHIE_POS) + +#define SPI_IER_RXUDIE_POS 11U +#define SPI_IER_RXUDIE_MSK BIT(SPI_IER_RXUDIE_POS) + +#define SPI_IER_RXOVIE_POS 10U +#define SPI_IER_RXOVIE_MSK BIT(SPI_IER_RXOVIE_POS) + +#define SPI_IER_RXFIE_POS 9U +#define SPI_IER_RXFIE_MSK BIT(SPI_IER_RXFIE_POS) + +#define SPI_IER_TXTHIE_POS 4U +#define SPI_IER_TXTHIE_MSK BIT(SPI_IER_TXTHIE_POS) + +#define SPI_IER_TXUDIE_POS 3U +#define SPI_IER_TXUDIE_MSK BIT(SPI_IER_TXUDIE_POS) + +#define SPI_IER_TXOVIE_POS 2U +#define SPI_IER_TXOVIE_MSK BIT(SPI_IER_TXOVIE_POS) + +#define SPI_IER_TXEIE_POS 0U +#define SPI_IER_TXEIE_MSK BIT(SPI_IER_TXEIE_POS) + +/****************** Bit definition for SPI_IDR register ************************/ + +#define SPI_IDR_FREID_POS 18U +#define SPI_IDR_FREID_MSK BIT(SPI_IDR_FREID_POS) + +#define SPI_IDR_MODFID_POS 17U +#define SPI_IDR_MODFID_MSK BIT(SPI_IDR_MODFID_POS) + +#define SPI_IDR_CRCERRID_POS 16U +#define SPI_IDR_CRCERRID_MSK BIT(SPI_IDR_CRCERRID_POS) + +#define SPI_IDR_RXTHID_POS 12U +#define SPI_IDR_RXTHID_MSK BIT(SPI_IDR_RXTHID_POS) + +#define SPI_IDR_RXUDID_POS 11U +#define SPI_IDR_RXUDID_MSK BIT(SPI_IDR_RXUDID_POS) + +#define SPI_IDR_RXOVID_POS 10U +#define SPI_IDR_RXOVID_MSK BIT(SPI_IDR_RXOVID_POS) + +#define SPI_IDR_RXFID_POS 9U +#define SPI_IDR_RXFID_MSK BIT(SPI_IDR_RXFID_POS) + +#define SPI_IDR_TXTHID_POS 4U +#define SPI_IDR_TXTHID_MSK BIT(SPI_IDR_TXTHID_POS) + +#define SPI_IDR_TXUDID_POS 3U +#define SPI_IDR_TXUDID_MSK BIT(SPI_IDR_TXUDID_POS) + +#define SPI_IDR_TXOVID_POS 2U +#define SPI_IDR_TXOVID_MSK BIT(SPI_IDR_TXOVID_POS) + +#define SPI_IDR_TXEID_POS 0U +#define SPI_IDR_TXEID_MSK BIT(SPI_IDR_TXEID_POS) + +/****************** Bit definition for SPI_IVS register ************************/ + +#define SPI_IVS_FREIV_POS 18U +#define SPI_IVS_FREIV_MSK BIT(SPI_IVS_FREIV_POS) + +#define SPI_IVS_MODFIV_POS 17U +#define SPI_IVS_MODFIV_MSK BIT(SPI_IVS_MODFIV_POS) + +#define SPI_IVS_CRCERRIV_POS 16U +#define SPI_IVS_CRCERRIV_MSK BIT(SPI_IVS_CRCERRIV_POS) + +#define SPI_IVS_RXTHIV_POS 12U +#define SPI_IVS_RXTHIV_MSK BIT(SPI_IVS_RXTHIV_POS) + +#define SPI_IVS_RXUDIV_POS 11U +#define SPI_IVS_RXUDIV_MSK BIT(SPI_IVS_RXUDIV_POS) + +#define SPI_IVS_RXOVIV_POS 10U +#define SPI_IVS_RXOVIV_MSK BIT(SPI_IVS_RXOVIV_POS) + +#define SPI_IVS_RXFIV_POS 9U +#define SPI_IVS_RXFIV_MSK BIT(SPI_IVS_RXFIV_POS) + +#define SPI_IVS_TXTHIV_POS 4U +#define SPI_IVS_TXTHIV_MSK BIT(SPI_IVS_TXTHIV_POS) + +#define SPI_IVS_TXUDIV_POS 3U +#define SPI_IVS_TXUDIV_MSK BIT(SPI_IVS_TXUDIV_POS) + +#define SPI_IVS_TXOVIV_POS 2U +#define SPI_IVS_TXOVIV_MSK BIT(SPI_IVS_TXOVIV_POS) + +#define SPI_IVS_TXEIV_POS 0U +#define SPI_IVS_TXEIV_MSK BIT(SPI_IVS_TXEIV_POS) + +/****************** Bit definition for SPI_RIF register ************************/ + +#define SPI_RIF_FRERI_POS 18U +#define SPI_RIF_FRERI_MSK BIT(SPI_RIF_FRERI_POS) + +#define SPI_RIF_MODFRI_POS 17U +#define SPI_RIF_MODFRI_MSK BIT(SPI_RIF_MODFRI_POS) + +#define SPI_RIF_CRCERRRI_POS 16U +#define SPI_RIF_CRCERRRI_MSK BIT(SPI_RIF_CRCERRRI_POS) + +#define SPI_RIF_RXTHRI_POS 12U +#define SPI_RIF_RXTHRI_MSK BIT(SPI_RIF_RXTHRI_POS) + +#define SPI_RIF_RXUDRI_POS 11U +#define SPI_RIF_RXUDRI_MSK BIT(SPI_RIF_RXUDRI_POS) + +#define SPI_RIF_RXOVRI_POS 10U +#define SPI_RIF_RXOVRI_MSK BIT(SPI_RIF_RXOVRI_POS) + +#define SPI_RIF_RXFRI_POS 9U +#define SPI_RIF_RXFRI_MSK BIT(SPI_RIF_RXFRI_POS) + +#define SPI_RIF_TXTHRI_POS 4U +#define SPI_RIF_TXTHRI_MSK BIT(SPI_RIF_TXTHRI_POS) + +#define SPI_RIF_TXUDRI_POS 3U +#define SPI_RIF_TXUDRI_MSK BIT(SPI_RIF_TXUDRI_POS) + +#define SPI_RIF_TXOVRI_POS 2U +#define SPI_RIF_TXOVRI_MSK BIT(SPI_RIF_TXOVRI_POS) + +#define SPI_RIF_TXERI_POS 0U +#define SPI_RIF_TXERI_MSK BIT(SPI_RIF_TXERI_POS) + +/****************** Bit definition for SPI_IFM register ************************/ + +#define SPI_IFM_FREFM_POS 18U +#define SPI_IFM_FREFM_MSK BIT(SPI_IFM_FREFM_POS) + +#define SPI_IFM_MODFFM_POS 17U +#define SPI_IFM_MODFFM_MSK BIT(SPI_IFM_MODFFM_POS) + +#define SPI_IFM_CRCERRFM_POS 16U +#define SPI_IFM_CRCERRFM_MSK BIT(SPI_IFM_CRCERRFM_POS) + +#define SPI_IFM_RXTHFM_POS 12U +#define SPI_IFM_RXTHFM_MSK BIT(SPI_IFM_RXTHFM_POS) + +#define SPI_IFM_RXUDFM_POS 11U +#define SPI_IFM_RXUDFM_MSK BIT(SPI_IFM_RXUDFM_POS) + +#define SPI_IFM_RXOVFM_POS 10U +#define SPI_IFM_RXOVFM_MSK BIT(SPI_IFM_RXOVFM_POS) + +#define SPI_IFM_RXFFM_POS 9U +#define SPI_IFM_RXFFM_MSK BIT(SPI_IFM_RXFFM_POS) + +#define SPI_IFM_TXTHFM_POS 4U +#define SPI_IFM_TXTHFM_MSK BIT(SPI_IFM_TXTHFM_POS) + +#define SPI_IFM_TXUDFM_POS 3U +#define SPI_IFM_TXUDFM_MSK BIT(SPI_IFM_TXUDFM_POS) + +#define SPI_IFM_TXOVFM_POS 2U +#define SPI_IFM_TXOVFM_MSK BIT(SPI_IFM_TXOVFM_POS) + +#define SPI_IFM_TXEFM_POS 0U +#define SPI_IFM_TXEFM_MSK BIT(SPI_IFM_TXEFM_POS) + +/****************** Bit definition for SPI_ICR register ************************/ + +#define SPI_ICR_FREIC_POS 18U +#define SPI_ICR_FREIC_MSK BIT(SPI_ICR_FREIC_POS) + +#define SPI_ICR_MODFIC_POS 17U +#define SPI_ICR_MODFIC_MSK BIT(SPI_ICR_MODFIC_POS) + +#define SPI_ICR_CRCERRIC_POS 16U +#define SPI_ICR_CRCERRIC_MSK BIT(SPI_ICR_CRCERRIC_POS) + +#define SPI_ICR_RXTHIC_POS 12U +#define SPI_ICR_RXTHIC_MSK BIT(SPI_ICR_RXTHIC_POS) + +#define SPI_ICR_RXUDIC_POS 11U +#define SPI_ICR_RXUDIC_MSK BIT(SPI_ICR_RXUDIC_POS) + +#define SPI_ICR_RXOVIC_POS 10U +#define SPI_ICR_RXOVIC_MSK BIT(SPI_ICR_RXOVIC_POS) + +#define SPI_ICR_RXFIC_POS 9U +#define SPI_ICR_RXFIC_MSK BIT(SPI_ICR_RXFIC_POS) + +#define SPI_ICR_TXTHIC_POS 4U +#define SPI_ICR_TXTHIC_MSK BIT(SPI_ICR_TXTHIC_POS) + +#define SPI_ICR_TXUDIC_POS 3U +#define SPI_ICR_TXUDIC_MSK BIT(SPI_ICR_TXUDIC_POS) + +#define SPI_ICR_TXOVIC_POS 2U +#define SPI_ICR_TXOVIC_MSK BIT(SPI_ICR_TXOVIC_POS) + +#define SPI_ICR_TXEIC_POS 0U +#define SPI_ICR_TXEIC_MSK BIT(SPI_ICR_TXEIC_POS) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __I uint32_t STAT; + __IO uint32_t DATA; + __IO uint32_t CRCPOLY; + __I uint32_t RXCRC; + __I uint32_t TXCRC; + __IO uint32_t I2SCFG; + __IO uint32_t I2SPR; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} SPI_I2S_TypeDef; + +/****************** Bit definition for I2C_CON1 register ************************/ + +#define I2C_CON1_PECEN_POS 23U +#define I2C_CON1_PECEN_MSK BIT(I2C_CON1_PECEN_POS) + +#define I2C_CON1_ALERTEN_POS 22U +#define I2C_CON1_ALERTEN_MSK BIT(I2C_CON1_ALERTEN_POS) + +#define I2C_CON1_SMBDEN_POS 21U +#define I2C_CON1_SMBDEN_MSK BIT(I2C_CON1_SMBDEN_POS) + +#define I2C_CON1_SMBHEN_POS 20U +#define I2C_CON1_SMBHEN_MSK BIT(I2C_CON1_SMBHEN_POS) + +#define I2C_CON1_GCEN_POS 19U +#define I2C_CON1_GCEN_MSK BIT(I2C_CON1_GCEN_POS) + +#define I2C_CON1_NOSTRETCH_POS 17U +#define I2C_CON1_NOSTRETCH_MSK BIT(I2C_CON1_NOSTRETCH_POS) + +#define I2C_CON1_SBC_POS 16U +#define I2C_CON1_SBC_MSK BIT(I2C_CON1_SBC_POS) + +#define I2C_CON1_RXDMAEN_POS 15U +#define I2C_CON1_RXDMAEN_MSK BIT(I2C_CON1_RXDMAEN_POS) + +#define I2C_CON1_TXDMAEN_POS 14U +#define I2C_CON1_TXDMAEN_MSK BIT(I2C_CON1_TXDMAEN_POS) + +#define I2C_CON1_DNF_POSS 8U +#define I2C_CON1_DNF_POSE 11U +#define I2C_CON1_DNF_MSK BITS(I2C_CON1_DNF_POSS,I2C_CON1_DNF_POSE) + +#define I2C_CON1_PE_POS 0U +#define I2C_CON1_PE_MSK BIT(I2C_CON1_PE_POS) + +/****************** Bit definition for I2C_CON2 register ************************/ + +#define I2C_CON2_ACK_UPD_POS 29U +#define I2C_CON2_ACK_UPD_MSK BIT(I2C_CON2_ACK_UPD_POS) + +#define I2C_CON2_HOLDACK_POS 28U +#define I2C_CON2_HOLDACK_MSK BIT(I2C_CON2_HOLDACK_POS) + +#define I2C_CON2_PECBYTE_POS 26U +#define I2C_CON2_PECBYTE_MSK BIT(I2C_CON2_PECBYTE_POS) + +#define I2C_CON2_AUTOEND_POS 25U +#define I2C_CON2_AUTOEND_MSK BIT(I2C_CON2_AUTOEND_POS) + +#define I2C_CON2_RELOAD_POS 24U +#define I2C_CON2_RELOAD_MSK BIT(I2C_CON2_RELOAD_POS) + +#define I2C_CON2_NBYTES_POSS 16U +#define I2C_CON2_NBYTES_POSE 23U +#define I2C_CON2_NBYTES_MSK BITS(I2C_CON2_NBYTES_POSS,I2C_CON2_NBYTES_POSE) + +#define I2C_CON2_NACK_POS 15U +#define I2C_CON2_NACK_MSK BIT(I2C_CON2_NACK_POS) + +#define I2C_CON2_STOP_POS 14U +#define I2C_CON2_STOP_MSK BIT(I2C_CON2_STOP_POS) + +#define I2C_CON2_START_POS 13U +#define I2C_CON2_START_MSK BIT(I2C_CON2_START_POS) + +#define I2C_CON2_HEAD10R_POS 12U +#define I2C_CON2_HEAD10R_MSK BIT(I2C_CON2_HEAD10R_POS) + +#define I2C_CON2_ADD10_POS 11U +#define I2C_CON2_ADD10_MSK BIT(I2C_CON2_ADD10_POS) + +#define I2C_CON2_RD_WRN_POS 10U +#define I2C_CON2_RD_WRN_MSK BIT(I2C_CON2_RD_WRN_POS) + +#define I2C_CON2_SADD_POSS 0U +#define I2C_CON2_SADD_POSE 9U +#define I2C_CON2_SADD_MSK BITS(I2C_CON2_SADD_POSS,I2C_CON2_SADD_POSE) + +/****************** Bit definition for I2C_ADDR1 register ************************/ + +#define I2C_ADDR1_OA1EN_POS 15U +#define I2C_ADDR1_OA1EN_MSK BIT(I2C_ADDR1_OA1EN_POS) + +#define I2C_ADDR1_OA1MODE_POS 10U +#define I2C_ADDR1_OA1MODE_MSK BIT(I2C_ADDR1_OA1MODE_POS) + +#define I2C_ADDR1_OA1_POSS 0U +#define I2C_ADDR1_OA1_POSE 9U +#define I2C_ADDR1_OA1_MSK BITS(I2C_ADDR1_OA1_POSS,I2C_ADDR1_OA1_POSE) + +/****************** Bit definition for I2C_ADDR2 register ************************/ + +#define I2C_ADDR2_OA2EN_POS 15U +#define I2C_ADDR2_OA2EN_MSK BIT(I2C_ADDR2_OA2EN_POS) + +#define I2C_ADDR2_OA2MSK_POSS 8U +#define I2C_ADDR2_OA2MSK_POSE 10U +#define I2C_ADDR2_OA2MSK_MSK BITS(I2C_ADDR2_OA2MSK_POSS,I2C_ADDR2_OA2MSK_POSE) + +#define I2C_ADDR2_OA2_POSS 1U +#define I2C_ADDR2_OA2_POSE 7U +#define I2C_ADDR2_OA2_MSK BITS(I2C_ADDR2_OA2_POSS,I2C_ADDR2_OA2_POSE) + +/****************** Bit definition for I2C_TIMINGR register ************************/ + +#define I2C_TIMINGR_PRESC_POSS 28U +#define I2C_TIMINGR_PRESC_POSE 31U +#define I2C_TIMINGR_PRESC_MSK BITS(I2C_TIMINGR_PRESC_POSS,I2C_TIMINGR_PRESC_POSE) + +#define I2C_TIMINGR_SCLDEL_POSS 20U +#define I2C_TIMINGR_SCLDEL_POSE 23U +#define I2C_TIMINGR_SCLDEL_MSK BITS(I2C_TIMINGR_SCLDEL_POSS,I2C_TIMINGR_SCLDEL_POSE) + +#define I2C_TIMINGR_SDADEL_POSS 16U +#define I2C_TIMINGR_SDADEL_POSE 19U +#define I2C_TIMINGR_SDADEL_MSK BITS(I2C_TIMINGR_SDADEL_POSS,I2C_TIMINGR_SDADEL_POSE) + +#define I2C_TIMINGR_SCLH_POSS 8U +#define I2C_TIMINGR_SCLH_POSE 15U +#define I2C_TIMINGR_SCLH_MSK BITS(I2C_TIMINGR_SCLH_POSS,I2C_TIMINGR_SCLH_POSE) + +#define I2C_TIMINGR_SCLL_POSS 0U +#define I2C_TIMINGR_SCLL_POSE 7U +#define I2C_TIMINGR_SCLL_MSK BITS(I2C_TIMINGR_SCLL_POSS,I2C_TIMINGR_SCLL_POSE) + +/****************** Bit definition for I2C_TIMEOUTR register ************************/ + +#define I2C_TIMEOUTR_TEXTEN_POS 31U +#define I2C_TIMEOUTR_TEXTEN_MSK BIT(I2C_TIMEOUTR_TEXTEN_POS) + +#define I2C_TIMEOUTR_TIMEOUTB_POSS 16U +#define I2C_TIMEOUTR_TIMEOUTB_POSE 27U +#define I2C_TIMEOUTR_TIMEOUTB_MSK BITS(I2C_TIMEOUTR_TIMEOUTB_POSS,I2C_TIMEOUTR_TIMEOUTB_POSE) + +#define I2C_TIMEOUTR_TIMEOUTEN_POS 15U +#define I2C_TIMEOUTR_TIMEOUTEN_MSK BIT(I2C_TIMEOUTR_TIMEOUTEN_POS) + +#define I2C_TIMEOUTR_TIDLE_POS 12U +#define I2C_TIMEOUTR_TIDLE_MSK BIT(I2C_TIMEOUTR_TIDLE_POS) + +#define I2C_TIMEOUTR_TIMEOUTA_POSS 0U +#define I2C_TIMEOUTR_TIMEOUTA_POSE 11U +#define I2C_TIMEOUTR_TIMEOUTA_MSK BITS(I2C_TIMEOUTR_TIMEOUTA_POSS,I2C_TIMEOUTR_TIMEOUTA_POSE) + +/****************** Bit definition for I2C_STAT register ************************/ + +#define I2C_STAT_ADDCODE_POSS 17U +#define I2C_STAT_ADDCODE_POSE 23U +#define I2C_STAT_ADDCODE_MSK BITS(I2C_STAT_ADDCODE_POSS,I2C_STAT_ADDCODE_POSE) + +#define I2C_STAT_DIR_POS 16U +#define I2C_STAT_DIR_MSK BIT(I2C_STAT_DIR_POS) + +#define I2C_STAT_BUSY_POS 15U +#define I2C_STAT_BUSY_MSK BIT(I2C_STAT_BUSY_POS) + +#define I2C_STAT_TCR_POS 11U +#define I2C_STAT_TCR_MSK BIT(I2C_STAT_TCR_POS) + +#define I2C_STAT_TC_POS 10U +#define I2C_STAT_TC_MSK BIT(I2C_STAT_TC_POS) + +#define I2C_STAT_RXTH_POS 9U +#define I2C_STAT_RXTH_MSK BIT(I2C_STAT_RXTH_POS) + +#define I2C_STAT_RXUD_POS 8U +#define I2C_STAT_RXUD_MSK BIT(I2C_STAT_RXUD_POS) + +#define I2C_STAT_RXOV_POS 7U +#define I2C_STAT_RXOV_MSK BIT(I2C_STAT_RXOV_POS) + +#define I2C_STAT_RXF_POS 6U +#define I2C_STAT_RXF_MSK BIT(I2C_STAT_RXF_POS) + +#define I2C_STAT_RXE_POS 5U +#define I2C_STAT_RXE_MSK BIT(I2C_STAT_RXE_POS) + +#define I2C_STAT_TXTH_POS 4U +#define I2C_STAT_TXTH_MSK BIT(I2C_STAT_TXTH_POS) + +#define I2C_STAT_TXUD_POS 3U +#define I2C_STAT_TXUD_MSK BIT(I2C_STAT_TXUD_POS) + +#define I2C_STAT_TXOV_POS 2U +#define I2C_STAT_TXOV_MSK BIT(I2C_STAT_TXOV_POS) + +#define I2C_STAT_TXF_POS 1U +#define I2C_STAT_TXF_MSK BIT(I2C_STAT_TXF_POS) + +#define I2C_STAT_TXE_POS 0U +#define I2C_STAT_TXE_MSK BIT(I2C_STAT_TXE_POS) + +/****************** Bit definition for I2C_FCON register ************************/ + +#define I2C_FCON_RXFTH_POSS 14U +#define I2C_FCON_RXFTH_POSE 15U +#define I2C_FCON_RXFTH_MSK BITS(I2C_FCON_RXFTH_POSS,I2C_FCON_RXFTH_POSE) + +#define I2C_FCON_RXFRST_POS 13U +#define I2C_FCON_RXFRST_MSK BIT(I2C_FCON_RXFRST_POS) + +#define I2C_FCON_RXFLV_POSS 8U +#define I2C_FCON_RXFLV_POSE 12U +#define I2C_FCON_RXFLV_MSK BITS(I2C_FCON_RXFLV_POSS,I2C_FCON_RXFLV_POSE) + +#define I2C_FCON_TXFTH_POSS 6U +#define I2C_FCON_TXFTH_POSE 7U +#define I2C_FCON_TXFTH_MSK BITS(I2C_FCON_TXFTH_POSS,I2C_FCON_TXFTH_POSE) + +#define I2C_FCON_TXFRST_POS 5U +#define I2C_FCON_TXFRST_MSK BIT(I2C_FCON_TXFRST_POS) + +#define I2C_FCON_TXFLV_POSS 0U +#define I2C_FCON_TXFLV_POSE 4U +#define I2C_FCON_TXFLV_MSK BITS(I2C_FCON_TXFLV_POSS,I2C_FCON_TXFLV_POSE) + +/****************** Bit definition for I2C_PECR register ************************/ + +#define I2C_PECR_PEC_POSS 0U +#define I2C_PECR_PEC_POSE 7U +#define I2C_PECR_PEC_MSK BITS(I2C_PECR_PEC_POSS,I2C_PECR_PEC_POSE) + +/****************** Bit definition for I2C_RXDATA register ************************/ + +#define I2C_RXDATA_RXDATA_POSS 0U +#define I2C_RXDATA_RXDATA_POSE 7U +#define I2C_RXDATA_RXDATA_MSK BITS(I2C_RXDATA_RXDATA_POSS,I2C_RXDATA_RXDATA_POSE) + +/****************** Bit definition for I2C_TXDATA register ************************/ + +#define I2C_TXDATA_TXDATA_POSS 0U +#define I2C_TXDATA_TXDATA_POSE 7U +#define I2C_TXDATA_TXDATA_MSK BITS(I2C_TXDATA_TXDATA_POSS,I2C_TXDATA_TXDATA_POSE) + +/****************** Bit definition for I2C_IER register ************************/ + +#define I2C_IER_ALERTIE_POS 20U +#define I2C_IER_ALERTIE_MSK BIT(I2C_IER_ALERTIE_POS) + +#define I2C_IER_TOUTIE_POS 19U +#define I2C_IER_TOUTIE_MSK BIT(I2C_IER_TOUTIE_POS) + +#define I2C_IER_PECEIE_POS 18U +#define I2C_IER_PECEIE_MSK BIT(I2C_IER_PECEIE_POS) + +#define I2C_IER_ARLOIE_POS 17U +#define I2C_IER_ARLOIE_MSK BIT(I2C_IER_ARLOIE_POS) + +#define I2C_IER_BERRIE_POS 16U +#define I2C_IER_BERRIE_MSK BIT(I2C_IER_BERRIE_POS) + +#define I2C_IER_STOPIE_POS 14U +#define I2C_IER_STOPIE_MSK BIT(I2C_IER_STOPIE_POS) + +#define I2C_IER_NACKIE_POS 13U +#define I2C_IER_NACKIE_MSK BIT(I2C_IER_NACKIE_POS) + +#define I2C_IER_ADDRIE_POS 12U +#define I2C_IER_ADDRIE_MSK BIT(I2C_IER_ADDRIE_POS) + +#define I2C_IER_TCRIE_POS 11U +#define I2C_IER_TCRIE_MSK BIT(I2C_IER_TCRIE_POS) + +#define I2C_IER_TCIE_POS 10U +#define I2C_IER_TCIE_MSK BIT(I2C_IER_TCIE_POS) + +#define I2C_IER_RXTHIE_POS 9U +#define I2C_IER_RXTHIE_MSK BIT(I2C_IER_RXTHIE_POS) + +#define I2C_IER_RXUDIE_POS 8U +#define I2C_IER_RXUDIE_MSK BIT(I2C_IER_RXUDIE_POS) + +#define I2C_IER_RXOVIE_POS 7U +#define I2C_IER_RXOVIE_MSK BIT(I2C_IER_RXOVIE_POS) + +#define I2C_IER_RXFIE_POS 6U +#define I2C_IER_RXFIE_MSK BIT(I2C_IER_RXFIE_POS) + +#define I2C_IER_TXTHIE_POS 4U +#define I2C_IER_TXTHIE_MSK BIT(I2C_IER_TXTHIE_POS) + +#define I2C_IER_TXUDIE_POS 3U +#define I2C_IER_TXUDIE_MSK BIT(I2C_IER_TXUDIE_POS) + +#define I2C_IER_TXOVIE_POS 2U +#define I2C_IER_TXOVIE_MSK BIT(I2C_IER_TXOVIE_POS) + +#define I2C_IER_TXEIE_POS 0U +#define I2C_IER_TXEIE_MSK BIT(I2C_IER_TXEIE_POS) + +/****************** Bit definition for I2C_IDR register ************************/ + +#define I2C_IDR_ALERTID_POS 20U +#define I2C_IDR_ALERTID_MSK BIT(I2C_IDR_ALERTID_POS) + +#define I2C_IDR_TOUTID_POS 19U +#define I2C_IDR_TOUTID_MSK BIT(I2C_IDR_TOUTID_POS) + +#define I2C_IDR_PECEID_POS 18U +#define I2C_IDR_PECEID_MSK BIT(I2C_IDR_PECEID_POS) + +#define I2C_IDR_ARLOID_POS 17U +#define I2C_IDR_ARLOID_MSK BIT(I2C_IDR_ARLOID_POS) + +#define I2C_IDR_BERRID_POS 16U +#define I2C_IDR_BERRID_MSK BIT(I2C_IDR_BERRID_POS) + +#define I2C_IDR_STOPID_POS 14U +#define I2C_IDR_STOPID_MSK BIT(I2C_IDR_STOPID_POS) + +#define I2C_IDR_NACKID_POS 13U +#define I2C_IDR_NACKID_MSK BIT(I2C_IDR_NACKID_POS) + +#define I2C_IDR_ADDRID_POS 12U +#define I2C_IDR_ADDRID_MSK BIT(I2C_IDR_ADDRID_POS) + +#define I2C_IDR_TCRID_POS 11U +#define I2C_IDR_TCRID_MSK BIT(I2C_IDR_TCRID_POS) + +#define I2C_IDR_TCID_POS 10U +#define I2C_IDR_TCID_MSK BIT(I2C_IDR_TCID_POS) + +#define I2C_IDR_RXTHID_POS 9U +#define I2C_IDR_RXTHID_MSK BIT(I2C_IDR_RXTHID_POS) + +#define I2C_IDR_RXUDID_POS 8U +#define I2C_IDR_RXUDID_MSK BIT(I2C_IDR_RXUDID_POS) + +#define I2C_IDR_RXOVID_POS 7U +#define I2C_IDR_RXOVID_MSK BIT(I2C_IDR_RXOVID_POS) + +#define I2C_IDR_RXFID_POS 6U +#define I2C_IDR_RXFID_MSK BIT(I2C_IDR_RXFID_POS) + +#define I2C_IDR_TXTHID_POS 4U +#define I2C_IDR_TXTHID_MSK BIT(I2C_IDR_TXTHID_POS) + +#define I2C_IDR_TXUDID_POS 3U +#define I2C_IDR_TXUDID_MSK BIT(I2C_IDR_TXUDID_POS) + +#define I2C_IDR_TXOVID_POS 2U +#define I2C_IDR_TXOVID_MSK BIT(I2C_IDR_TXOVID_POS) + +#define I2C_IDR_TXEID_POS 0U +#define I2C_IDR_TXEID_MSK BIT(I2C_IDR_TXEID_POS) + +/****************** Bit definition for I2C_IVS register ************************/ + +#define I2C_IVS_ALERTIV_POS 20U +#define I2C_IVS_ALERTIV_MSK BIT(I2C_IVS_ALERTIV_POS) + +#define I2C_IVS_TOUTIV_POS 19U +#define I2C_IVS_TOUTIV_MSK BIT(I2C_IVS_TOUTIV_POS) + +#define I2C_IVS_PECEIV_POS 18U +#define I2C_IVS_PECEIV_MSK BIT(I2C_IVS_PECEIV_POS) + +#define I2C_IVS_ARLOIV_POS 17U +#define I2C_IVS_ARLOIV_MSK BIT(I2C_IVS_ARLOIV_POS) + +#define I2C_IVS_BERRIV_POS 16U +#define I2C_IVS_BERRIV_MSK BIT(I2C_IVS_BERRIV_POS) + +#define I2C_IVS_STOPIV_POS 14U +#define I2C_IVS_STOPIV_MSK BIT(I2C_IVS_STOPIV_POS) + +#define I2C_IVS_NACKIV_POS 13U +#define I2C_IVS_NACKIV_MSK BIT(I2C_IVS_NACKIV_POS) + +#define I2C_IVS_ADDRIV_POS 12U +#define I2C_IVS_ADDRIV_MSK BIT(I2C_IVS_ADDRIV_POS) + +#define I2C_IVS_TCRIV_POS 11U +#define I2C_IVS_TCRIV_MSK BIT(I2C_IVS_TCRIV_POS) + +#define I2C_IVS_TCIV_POS 10U +#define I2C_IVS_TCIV_MSK BIT(I2C_IVS_TCIV_POS) + +#define I2C_IVS_RXTHIV_POS 9U +#define I2C_IVS_RXTHIV_MSK BIT(I2C_IVS_RXTHIV_POS) + +#define I2C_IVS_RXUDIV_POS 8U +#define I2C_IVS_RXUDIV_MSK BIT(I2C_IVS_RXUDIV_POS) + +#define I2C_IVS_RXOVIV_POS 7U +#define I2C_IVS_RXOVIV_MSK BIT(I2C_IVS_RXOVIV_POS) + +#define I2C_IVS_RXFIV_POS 6U +#define I2C_IVS_RXFIV_MSK BIT(I2C_IVS_RXFIV_POS) + +#define I2C_IVS_TXTHIV_POS 4U +#define I2C_IVS_TXTHIV_MSK BIT(I2C_IVS_TXTHIV_POS) + +#define I2C_IVS_TXUDIV_POS 3U +#define I2C_IVS_TXUDIV_MSK BIT(I2C_IVS_TXUDIV_POS) + +#define I2C_IVS_TXOVIV_POS 2U +#define I2C_IVS_TXOVIV_MSK BIT(I2C_IVS_TXOVIV_POS) + +#define I2C_IVS_TXEIV_POS 0U +#define I2C_IVS_TXEIV_MSK BIT(I2C_IVS_TXEIV_POS) + +/****************** Bit definition for I2C_RIF register ************************/ + +#define I2C_RIF_ALERTRI_POS 20U +#define I2C_RIF_ALERTRI_MSK BIT(I2C_RIF_ALERTRI_POS) + +#define I2C_RIF_TOUTRI_POS 19U +#define I2C_RIF_TOUTRI_MSK BIT(I2C_RIF_TOUTRI_POS) + +#define I2C_RIF_PECERI_POS 18U +#define I2C_RIF_PECERI_MSK BIT(I2C_RIF_PECERI_POS) + +#define I2C_RIF_ARLORI_POS 17U +#define I2C_RIF_ARLORI_MSK BIT(I2C_RIF_ARLORI_POS) + +#define I2C_RIF_BERRRI_POS 16U +#define I2C_RIF_BERRRI_MSK BIT(I2C_RIF_BERRRI_POS) + +#define I2C_RIF_STOPRI_POS 14U +#define I2C_RIF_STOPRI_MSK BIT(I2C_RIF_STOPRI_POS) + +#define I2C_RIF_NACKRI_POS 13U +#define I2C_RIF_NACKRI_MSK BIT(I2C_RIF_NACKRI_POS) + +#define I2C_RIF_ADDRRI_POS 12U +#define I2C_RIF_ADDRRI_MSK BIT(I2C_RIF_ADDRRI_POS) + +#define I2C_RIF_TCRRI_POS 11U +#define I2C_RIF_TCRRI_MSK BIT(I2C_RIF_TCRRI_POS) + +#define I2C_RIF_TCRI_POS 10U +#define I2C_RIF_TCRI_MSK BIT(I2C_RIF_TCRI_POS) + +#define I2C_RIF_RXTHRI_POS 9U +#define I2C_RIF_RXTHRI_MSK BIT(I2C_RIF_RXTHRI_POS) + +#define I2C_RIF_RXUDRI_POS 8U +#define I2C_RIF_RXUDRI_MSK BIT(I2C_RIF_RXUDRI_POS) + +#define I2C_RIF_RXOVRI_POS 7U +#define I2C_RIF_RXOVRI_MSK BIT(I2C_RIF_RXOVRI_POS) + +#define I2C_RIF_RXFRI_POS 6U +#define I2C_RIF_RXFRI_MSK BIT(I2C_RIF_RXFRI_POS) + +#define I2C_RIF_TXTHRI_POS 4U +#define I2C_RIF_TXTHRI_MSK BIT(I2C_RIF_TXTHRI_POS) + +#define I2C_RIF_TXUDRI_POS 3U +#define I2C_RIF_TXUDRI_MSK BIT(I2C_RIF_TXUDRI_POS) + +#define I2C_RIF_TXOVRI_POS 2U +#define I2C_RIF_TXOVRI_MSK BIT(I2C_RIF_TXOVRI_POS) + +#define I2C_RIF_TXERI_POS 0U +#define I2C_RIF_TXERI_MSK BIT(I2C_RIF_TXERI_POS) + +/****************** Bit definition for I2C_IFM register ************************/ + +#define I2C_IFM_ALERTFM_POS 20U +#define I2C_IFM_ALERTFM_MSK BIT(I2C_IFM_ALERTFM_POS) + +#define I2C_IFM_TOUTFM_POS 19U +#define I2C_IFM_TOUTFM_MSK BIT(I2C_IFM_TOUTFM_POS) + +#define I2C_IFM_PECEFM_POS 18U +#define I2C_IFM_PECEFM_MSK BIT(I2C_IFM_PECEFM_POS) + +#define I2C_IFM_ARLOFM_POS 17U +#define I2C_IFM_ARLOFM_MSK BIT(I2C_IFM_ARLOFM_POS) + +#define I2C_IFM_BERRFM_POS 16U +#define I2C_IFM_BERRFM_MSK BIT(I2C_IFM_BERRFM_POS) + +#define I2C_IFM_STOPFM_POS 14U +#define I2C_IFM_STOPFM_MSK BIT(I2C_IFM_STOPFM_POS) + +#define I2C_IFM_NACKFM_POS 13U +#define I2C_IFM_NACKFM_MSK BIT(I2C_IFM_NACKFM_POS) + +#define I2C_IFM_ADDRFM_POS 12U +#define I2C_IFM_ADDRFM_MSK BIT(I2C_IFM_ADDRFM_POS) + +#define I2C_IFM_TCRFM_POS 11U +#define I2C_IFM_TCRFM_MSK BIT(I2C_IFM_TCRFM_POS) + +#define I2C_IFM_TCFM_POS 10U +#define I2C_IFM_TCFM_MSK BIT(I2C_IFM_TCFM_POS) + +#define I2C_IFM_RXTHFM_POS 9U +#define I2C_IFM_RXTHFM_MSK BIT(I2C_IFM_RXTHFM_POS) + +#define I2C_IFM_RXUDFM_POS 8U +#define I2C_IFM_RXUDFM_MSK BIT(I2C_IFM_RXUDFM_POS) + +#define I2C_IFM_RXOVFM_POS 7U +#define I2C_IFM_RXOVFM_MSK BIT(I2C_IFM_RXOVFM_POS) + +#define I2C_IFM_RXFFM_POS 6U +#define I2C_IFM_RXFFM_MSK BIT(I2C_IFM_RXFFM_POS) + +#define I2C_IFM_TXTHFM_POS 4U +#define I2C_IFM_TXTHFM_MSK BIT(I2C_IFM_TXTHFM_POS) + +#define I2C_IFM_TXUDFM_POS 3U +#define I2C_IFM_TXUDFM_MSK BIT(I2C_IFM_TXUDFM_POS) + +#define I2C_IFM_TXOVFM_POS 2U +#define I2C_IFM_TXOVFM_MSK BIT(I2C_IFM_TXOVFM_POS) + +#define I2C_IFM_TXEFM_POS 0U +#define I2C_IFM_TXEFM_MSK BIT(I2C_IFM_TXEFM_POS) + +/****************** Bit definition for I2C_ICR register ************************/ + +#define I2C_ICR_ALERTIC_POS 20U +#define I2C_ICR_ALERTIC_MSK BIT(I2C_ICR_ALERTIC_POS) + +#define I2C_ICR_TOUTIC_POS 19U +#define I2C_ICR_TOUTIC_MSK BIT(I2C_ICR_TOUTIC_POS) + +#define I2C_ICR_PECEIC_POS 18U +#define I2C_ICR_PECEIC_MSK BIT(I2C_ICR_PECEIC_POS) + +#define I2C_ICR_ARLOIC_POS 17U +#define I2C_ICR_ARLOIC_MSK BIT(I2C_ICR_ARLOIC_POS) + +#define I2C_ICR_BERRIC_POS 16U +#define I2C_ICR_BERRIC_MSK BIT(I2C_ICR_BERRIC_POS) + +#define I2C_ICR_STOPIC_POS 14U +#define I2C_ICR_STOPIC_MSK BIT(I2C_ICR_STOPIC_POS) + +#define I2C_ICR_NACKIC_POS 13U +#define I2C_ICR_NACKIC_MSK BIT(I2C_ICR_NACKIC_POS) + +#define I2C_ICR_ADDRIC_POS 12U +#define I2C_ICR_ADDRIC_MSK BIT(I2C_ICR_ADDRIC_POS) + +#define I2C_ICR_TCRIC_POS 11U +#define I2C_ICR_TCRIC_MSK BIT(I2C_ICR_TCRIC_POS) + +#define I2C_ICR_TCIC_POS 10U +#define I2C_ICR_TCIC_MSK BIT(I2C_ICR_TCIC_POS) + +#define I2C_ICR_RXTHIC_POS 9U +#define I2C_ICR_RXTHIC_MSK BIT(I2C_ICR_RXTHIC_POS) + +#define I2C_ICR_RXUDIC_POS 8U +#define I2C_ICR_RXUDIC_MSK BIT(I2C_ICR_RXUDIC_POS) + +#define I2C_ICR_RXOVIC_POS 7U +#define I2C_ICR_RXOVIC_MSK BIT(I2C_ICR_RXOVIC_POS) + +#define I2C_ICR_RXFIC_POS 6U +#define I2C_ICR_RXFIC_MSK BIT(I2C_ICR_RXFIC_POS) + +#define I2C_ICR_TXTHIC_POS 4U +#define I2C_ICR_TXTHIC_MSK BIT(I2C_ICR_TXTHIC_POS) + +#define I2C_ICR_TXUDIC_POS 3U +#define I2C_ICR_TXUDIC_MSK BIT(I2C_ICR_TXUDIC_POS) + +#define I2C_ICR_TXOVIC_POS 2U +#define I2C_ICR_TXOVIC_MSK BIT(I2C_ICR_TXOVIC_POS) + +#define I2C_ICR_TXEIC_POS 0U +#define I2C_ICR_TXEIC_MSK BIT(I2C_ICR_TXEIC_POS) + +typedef struct +{ + __IO uint32_t CON1; + __IO uint32_t CON2; + __IO uint32_t ADDR1; + __IO uint32_t ADDR2; + __IO uint32_t TIMINGR; + __IO uint32_t TIMEOUTR; + __I uint32_t STAT; + __IO uint32_t FCON; + __I uint32_t PECR; + __I uint32_t RXDATA; + __O uint32_t TXDATA; + __O uint32_t IER; + __O uint32_t IDR; + __I uint32_t IVS; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t ICR; +} I2C_TypeDef; + +/****************** Bit definition for CAN_CON register ************************/ + +#define CAN_CON_DBGSTP_POS 16U +#define CAN_CON_DBGSTP_MSK BIT(CAN_CON_DBGSTP_POS) + +#define CAN_CON_RST_POS 15U +#define CAN_CON_RST_MSK BIT(CAN_CON_RST_POS) + +#define CAN_CON_TTCEN_POS 7U +#define CAN_CON_TTCEN_MSK BIT(CAN_CON_TTCEN_POS) + +#define CAN_CON_ABOFFEN_POS 6U +#define CAN_CON_ABOFFEN_MSK BIT(CAN_CON_ABOFFEN_POS) + +#define CAN_CON_AWKEN_POS 5U +#define CAN_CON_AWKEN_MSK BIT(CAN_CON_AWKEN_POS) + +#define CAN_CON_ARTXDIS_POS 4U +#define CAN_CON_ARTXDIS_MSK BIT(CAN_CON_ARTXDIS_POS) + +#define CAN_CON_RXFOPM_POS 3U +#define CAN_CON_RXFOPM_MSK BIT(CAN_CON_RXFOPM_POS) + +#define CAN_CON_TXMP_POS 2U +#define CAN_CON_TXMP_MSK BIT(CAN_CON_TXMP_POS) + +#define CAN_CON_SLPREQ_POS 1U +#define CAN_CON_SLPREQ_MSK BIT(CAN_CON_SLPREQ_POS) + +#define CAN_CON_INIREQ_POS 0U +#define CAN_CON_INIREQ_MSK BIT(CAN_CON_INIREQ_POS) + +/****************** Bit definition for CAN_STAT register ************************/ + +#define CAN_STAT_RX_POS 11U +#define CAN_STAT_RX_MSK BIT(CAN_STAT_RX_POS) + +#define CAN_STAT_PRESMP_POS 10U +#define CAN_STAT_PRESMP_MSK BIT(CAN_STAT_PRESMP_POS) + +#define CAN_STAT_RXSTAT_POS 9U +#define CAN_STAT_RXSTAT_MSK BIT(CAN_STAT_RXSTAT_POS) + +#define CAN_STAT_TXSTAT_POS 8U +#define CAN_STAT_TXSTAT_MSK BIT(CAN_STAT_TXSTAT_POS) + +#define CAN_STAT_SLPIF_POS 4U +#define CAN_STAT_SLPIF_MSK BIT(CAN_STAT_SLPIF_POS) + +#define CAN_STAT_WKIF_POS 3U +#define CAN_STAT_WKIF_MSK BIT(CAN_STAT_WKIF_POS) + +#define CAN_STAT_ERRIF_POS 2U +#define CAN_STAT_ERRIF_MSK BIT(CAN_STAT_ERRIF_POS) + +#define CAN_STAT_SLPSTAT_POS 1U +#define CAN_STAT_SLPSTAT_MSK BIT(CAN_STAT_SLPSTAT_POS) + +#define CAN_STAT_INISTAT_POS 0U +#define CAN_STAT_INISTAT_MSK BIT(CAN_STAT_INISTAT_POS) + +/****************** Bit definition for CAN_IFC register ************************/ + +#define CAN_IFC_SLPIFC_POS 4U +#define CAN_IFC_SLPIFC_MSK BIT(CAN_IFC_SLPIFC_POS) + +#define CAN_IFC_WKIFC_POS 3U +#define CAN_IFC_WKIFC_MSK BIT(CAN_IFC_WKIFC_POS) + +#define CAN_IFC_ERRIFC_POS 2U +#define CAN_IFC_ERRIFC_MSK BIT(CAN_IFC_ERRIFC_POS) + +/****************** Bit definition for CAN_TXSTAT register ************************/ + +#define CAN_TXSTAT_TXM2LPF_POS 31U +#define CAN_TXSTAT_TXM2LPF_MSK BIT(CAN_TXSTAT_TXM2LPF_POS) + +#define CAN_TXSTAT_TXM1LPF_POS 30U +#define CAN_TXSTAT_TXM1LPF_MSK BIT(CAN_TXSTAT_TXM1LPF_POS) + +#define CAN_TXSTAT_TXM0LPF_POS 29U +#define CAN_TXSTAT_TXM0LPF_MSK BIT(CAN_TXSTAT_TXM0LPF_POS) + +#define CAN_TXSTAT_TXM2EF_POS 28U +#define CAN_TXSTAT_TXM2EF_MSK BIT(CAN_TXSTAT_TXM2EF_POS) + +#define CAN_TXSTAT_TXM1EF_POS 27U +#define CAN_TXSTAT_TXM1EF_MSK BIT(CAN_TXSTAT_TXM1EF_POS) + +#define CAN_TXSTAT_TXM0EF_POS 26U +#define CAN_TXSTAT_TXM0EF_MSK BIT(CAN_TXSTAT_TXM0EF_POS) + +#define CAN_TXSTAT_CODE_POSS 24U +#define CAN_TXSTAT_CODE_POSE 25U +#define CAN_TXSTAT_CODE_MSK BITS(CAN_TXSTAT_CODE_POSS,CAN_TXSTAT_CODE_POSE) + +#define CAN_TXSTAT_M2STPREQ_POS 23U +#define CAN_TXSTAT_M2STPREQ_MSK BIT(CAN_TXSTAT_M2STPREQ_POS) + +#define CAN_TXSTAT_M2TXERR_POS 19U +#define CAN_TXSTAT_M2TXERR_MSK BIT(CAN_TXSTAT_M2TXERR_POS) + +#define CAN_TXSTAT_M2ARBLST_POS 18U +#define CAN_TXSTAT_M2ARBLST_MSK BIT(CAN_TXSTAT_M2ARBLST_POS) + +#define CAN_TXSTAT_M2TXC_POS 17U +#define CAN_TXSTAT_M2TXC_MSK BIT(CAN_TXSTAT_M2TXC_POS) + +#define CAN_TXSTAT_M2REQC_POS 16U +#define CAN_TXSTAT_M2REQC_MSK BIT(CAN_TXSTAT_M2REQC_POS) + +#define CAN_TXSTAT_M1STPREQ_POS 15U +#define CAN_TXSTAT_M1STPREQ_MSK BIT(CAN_TXSTAT_M1STPREQ_POS) + +#define CAN_TXSTAT_M1TXERR_POS 11U +#define CAN_TXSTAT_M1TXERR_MSK BIT(CAN_TXSTAT_M1TXERR_POS) + +#define CAN_TXSTAT_M1ARBLST_POS 10U +#define CAN_TXSTAT_M1ARBLST_MSK BIT(CAN_TXSTAT_M1ARBLST_POS) + +#define CAN_TXSTAT_M1TXC_POS 9U +#define CAN_TXSTAT_M1TXC_MSK BIT(CAN_TXSTAT_M1TXC_POS) + +#define CAN_TXSTAT_M1REQC_POS 8U +#define CAN_TXSTAT_M1REQC_MSK BIT(CAN_TXSTAT_M1REQC_POS) + +#define CAN_TXSTAT_M0STPREQ_POS 7U +#define CAN_TXSTAT_M0STPREQ_MSK BIT(CAN_TXSTAT_M0STPREQ_POS) + +#define CAN_TXSTAT_M0TXERR_POS 3U +#define CAN_TXSTAT_M0TXERR_MSK BIT(CAN_TXSTAT_M0TXERR_POS) + +#define CAN_TXSTAT_M0ARBLST_POS 2U +#define CAN_TXSTAT_M0ARBLST_MSK BIT(CAN_TXSTAT_M0ARBLST_POS) + +#define CAN_TXSTAT_M0TXC_POS 1U +#define CAN_TXSTAT_M0TXC_MSK BIT(CAN_TXSTAT_M0TXC_POS) + +#define CAN_TXSTAT_M0REQC_POS 0U +#define CAN_TXSTAT_M0REQC_MSK BIT(CAN_TXSTAT_M0REQC_POS) + +/****************** Bit definition for CAN_TXSTATC register ************************/ + +#define CAN_TXSTATC_M2TXERR_POS 19U +#define CAN_TXSTATC_M2TXERR_MSK BIT(CAN_TXSTATC_M2TXERR_POS) + +#define CAN_TXSTATC_M2ARBLST_POS 18U +#define CAN_TXSTATC_M2ARBLST_MSK BIT(CAN_TXSTATC_M2ARBLST_POS) + +#define CAN_TXSTATC_M2TXC_POS 17U +#define CAN_TXSTATC_M2TXC_MSK BIT(CAN_TXSTATC_M2TXC_POS) + +#define CAN_TXSTATC_M2REQC_POS 16U +#define CAN_TXSTATC_M2REQC_MSK BIT(CAN_TXSTATC_M2REQC_POS) + +#define CAN_TXSTATC_M1TXERR_POS 11U +#define CAN_TXSTATC_M1TXERR_MSK BIT(CAN_TXSTATC_M1TXERR_POS) + +#define CAN_TXSTATC_M1ARBLST_POS 10U +#define CAN_TXSTATC_M1ARBLST_MSK BIT(CAN_TXSTATC_M1ARBLST_POS) + +#define CAN_TXSTATC_M1TXC_POS 9U +#define CAN_TXSTATC_M1TXC_MSK BIT(CAN_TXSTATC_M1TXC_POS) + +#define CAN_TXSTATC_M1REQC_POS 8U +#define CAN_TXSTATC_M1REQC_MSK BIT(CAN_TXSTATC_M1REQC_POS) + +#define CAN_TXSTATC_M0TXERR_POS 3U +#define CAN_TXSTATC_M0TXERR_MSK BIT(CAN_TXSTATC_M0TXERR_POS) + +#define CAN_TXSTATC_M0ARBLST_POS 2U +#define CAN_TXSTATC_M0ARBLST_MSK BIT(CAN_TXSTATC_M0ARBLST_POS) + +#define CAN_TXSTATC_M0TXC_POS 1U +#define CAN_TXSTATC_M0TXC_MSK BIT(CAN_TXSTATC_M0TXC_POS) + +#define CAN_TXSTATC_M0REQC_POS 0U +#define CAN_TXSTATC_M0REQC_MSK BIT(CAN_TXSTATC_M0REQC_POS) + +/****************** Bit definition for CAN_RXF0 register ************************/ + +#define CAN_RXF0_FREE_POS 5U +#define CAN_RXF0_FREE_MSK BIT(CAN_RXF0_FREE_POS) + +#define CAN_RXF0_OVR_POS 4U +#define CAN_RXF0_OVR_MSK BIT(CAN_RXF0_OVR_POS) + +#define CAN_RXF0_FULL_POS 3U +#define CAN_RXF0_FULL_MSK BIT(CAN_RXF0_FULL_POS) + +#define CAN_RXF0_PEND_POSS 0U +#define CAN_RXF0_PEND_POSE 1U +#define CAN_RXF0_PEND_MSK BITS(CAN_RXF0_PEND_POSS,CAN_RXF0_PEND_POSE) + +/****************** Bit definition for CAN_RXF0C register ************************/ + +#define CAN_RXF0C_OVRC_POS 4U +#define CAN_RXF0C_OVRC_MSK BIT(CAN_RXF0C_OVRC_POS) + +#define CAN_RXF0C_FULLC_POS 3U +#define CAN_RXF0C_FULLC_MSK BIT(CAN_RXF0C_FULLC_POS) + +/****************** Bit definition for CAN_RXF1 register ************************/ + +#define CAN_RXF1_FREE_POS 5U +#define CAN_RXF1_FREE_MSK BIT(CAN_RXF1_FREE_POS) + +#define CAN_RXF1_OVR_POS 4U +#define CAN_RXF1_OVR_MSK BIT(CAN_RXF1_OVR_POS) + +#define CAN_RXF1_FULL_POS 3U +#define CAN_RXF1_FULL_MSK BIT(CAN_RXF1_FULL_POS) + +#define CAN_RXF1_PEND_POSS 0U +#define CAN_RXF1_PEND_POSE 1U +#define CAN_RXF1_PEND_MSK BITS(CAN_RXF1_PEND_POSS,CAN_RXF1_PEND_POSE) + +/****************** Bit definition for CAN_RXF1C register ************************/ + +#define CAN_RXF1C_OVRC_POS 4U +#define CAN_RXF1C_OVRC_MSK BIT(CAN_RXF1C_OVRC_POS) + +#define CAN_RXF1C_FULLC_POS 3U +#define CAN_RXF1C_FULLC_MSK BIT(CAN_RXF1C_FULLC_POS) + +/****************** Bit definition for CAN_IE register ************************/ + +#define CAN_IE_SLPIE_POS 17U +#define CAN_IE_SLPIE_MSK BIT(CAN_IE_SLPIE_POS) + +#define CAN_IE_WKIE_POS 16U +#define CAN_IE_WKIE_MSK BIT(CAN_IE_WKIE_POS) + +#define CAN_IE_ERRIE_POS 15U +#define CAN_IE_ERRIE_MSK BIT(CAN_IE_ERRIE_POS) + +#define CAN_IE_PRERRIE_POS 11U +#define CAN_IE_PRERRIE_MSK BIT(CAN_IE_PRERRIE_POS) + +#define CAN_IE_BOFFIE_POS 10U +#define CAN_IE_BOFFIE_MSK BIT(CAN_IE_BOFFIE_POS) + +#define CAN_IE_PERRIE_POS 9U +#define CAN_IE_PERRIE_MSK BIT(CAN_IE_PERRIE_POS) + +#define CAN_IE_WARNIE_POS 8U +#define CAN_IE_WARNIE_MSK BIT(CAN_IE_WARNIE_POS) + +#define CAN_IE_F1OVRIE_POS 6U +#define CAN_IE_F1OVRIE_MSK BIT(CAN_IE_F1OVRIE_POS) + +#define CAN_IE_F1FULIE_POS 5U +#define CAN_IE_F1FULIE_MSK BIT(CAN_IE_F1FULIE_POS) + +#define CAN_IE_F1PIE_POS 4U +#define CAN_IE_F1PIE_MSK BIT(CAN_IE_F1PIE_POS) + +#define CAN_IE_F0OVRIE_POS 3U +#define CAN_IE_F0OVRIE_MSK BIT(CAN_IE_F0OVRIE_POS) + +#define CAN_IE_F0FULIE_POS 2U +#define CAN_IE_F0FULIE_MSK BIT(CAN_IE_F0FULIE_POS) + +#define CAN_IE_F0PIE_POS 1U +#define CAN_IE_F0PIE_MSK BIT(CAN_IE_F0PIE_POS) + +#define CAN_IE_TXMEIE_POS 0U +#define CAN_IE_TXMEIE_MSK BIT(CAN_IE_TXMEIE_POS) + +/****************** Bit definition for CAN_ERRSTAT register ************************/ + +#define CAN_ERRSTAT_RXERRC_POSS 24U +#define CAN_ERRSTAT_RXERRC_POSE 31U +#define CAN_ERRSTAT_RXERRC_MSK BITS(CAN_ERRSTAT_RXERRC_POSS,CAN_ERRSTAT_RXERRC_POSE) + +#define CAN_ERRSTAT_TXERRC_POSS 16U +#define CAN_ERRSTAT_TXERRC_POSE 23U +#define CAN_ERRSTAT_TXERRC_MSK BITS(CAN_ERRSTAT_TXERRC_POSS,CAN_ERRSTAT_TXERRC_POSE) + +#define CAN_ERRSTAT_PRERRF_POSS 4U +#define CAN_ERRSTAT_PRERRF_POSE 6U +#define CAN_ERRSTAT_PRERRF_MSK BITS(CAN_ERRSTAT_PRERRF_POSS,CAN_ERRSTAT_PRERRF_POSE) + +#define CAN_ERRSTAT_BOFF_POS 2U +#define CAN_ERRSTAT_BOFF_MSK BIT(CAN_ERRSTAT_BOFF_POS) + +#define CAN_ERRSTAT_PERRF_POS 1U +#define CAN_ERRSTAT_PERRF_MSK BIT(CAN_ERRSTAT_PERRF_POS) + +#define CAN_ERRSTAT_WARNF_POS 0U +#define CAN_ERRSTAT_WARNF_MSK BIT(CAN_ERRSTAT_WARNF_POS) + +/****************** Bit definition for CAN_BTIME register ************************/ + +#define CAN_BTIME_SILENT_POS 31U +#define CAN_BTIME_SILENT_MSK BIT(CAN_BTIME_SILENT_POS) + +#define CAN_BTIME_LOOP_POS 30U +#define CAN_BTIME_LOOP_MSK BIT(CAN_BTIME_LOOP_POS) + +#define CAN_BTIME_RESJW_POSS 24U +#define CAN_BTIME_RESJW_POSE 25U +#define CAN_BTIME_RESJW_MSK BITS(CAN_BTIME_RESJW_POSS,CAN_BTIME_RESJW_POSE) + +#define CAN_BTIME_SEG2_POSS 20U +#define CAN_BTIME_SEG2_POSE 22U +#define CAN_BTIME_SEG2_MSK BITS(CAN_BTIME_SEG2_POSS,CAN_BTIME_SEG2_POSE) + +#define CAN_BTIME_SEG1_POSS 16U +#define CAN_BTIME_SEG1_POSE 19U +#define CAN_BTIME_SEG1_MSK BITS(CAN_BTIME_SEG1_POSS,CAN_BTIME_SEG1_POSE) + +#define CAN_BTIME_BPSC_POSS 0U +#define CAN_BTIME_BPSC_POSE 9U +#define CAN_BTIME_BPSC_MSK BITS(CAN_BTIME_BPSC_POSS,CAN_BTIME_BPSC_POSE) + +/****************** Bit definition for CAN_TXID0 register ************************/ + +#define CAN_TXID0_STDID_POSS 21U +#define CAN_TXID0_STDID_POSE 31U +#define CAN_TXID0_STDID_MSK BITS(CAN_TXID0_STDID_POSS,CAN_TXID0_STDID_POSE) + +#define CAN_TXID0_EXID_POSS 3U +#define CAN_TXID0_EXID_POSE 20U +#define CAN_TXID0_EXID_MSK BITS(CAN_TXID0_EXID_POSS,CAN_TXID0_EXID_POSE) + +#define CAN_TXID0_IDE_POS 2U +#define CAN_TXID0_IDE_MSK BIT(CAN_TXID0_IDE_POS) + +#define CAN_TXID0_RTR_POS 1U +#define CAN_TXID0_RTR_MSK BIT(CAN_TXID0_RTR_POS) + +#define CAN_TXID0_TXMREQ_POS 0U +#define CAN_TXID0_TXMREQ_MSK BIT(CAN_TXID0_TXMREQ_POS) + +/****************** Bit definition for CAN_TXFCON0 register ************************/ + +#define CAN_TXFCON0_STAMP_POSS 16U +#define CAN_TXFCON0_STAMP_POSE 31U +#define CAN_TXFCON0_STAMP_MSK BITS(CAN_TXFCON0_STAMP_POSS,CAN_TXFCON0_STAMP_POSE) + +#define CAN_TXFCON0_TXGT_POS 8U +#define CAN_TXFCON0_TXGT_MSK BIT(CAN_TXFCON0_TXGT_POS) + +#define CAN_TXFCON0_DLEN_POSS 0U +#define CAN_TXFCON0_DLEN_POSE 3U +#define CAN_TXFCON0_DLEN_MSK BITS(CAN_TXFCON0_DLEN_POSS,CAN_TXFCON0_DLEN_POSE) + +/****************** Bit definition for CAN_TXDL0 register ************************/ + +#define CAN_TXDL0_BYTE3_POSS 24U +#define CAN_TXDL0_BYTE3_POSE 31U +#define CAN_TXDL0_BYTE3_MSK BITS(CAN_TXDL0_BYTE3_POSS,CAN_TXDL0_BYTE3_POSE) + +#define CAN_TXDL0_BYTE2_POSS 16U +#define CAN_TXDL0_BYTE2_POSE 23U +#define CAN_TXDL0_BYTE2_MSK BITS(CAN_TXDL0_BYTE2_POSS,CAN_TXDL0_BYTE2_POSE) + +#define CAN_TXDL0_BYTE1_POSS 8U +#define CAN_TXDL0_BYTE1_POSE 15U +#define CAN_TXDL0_BYTE1_MSK BITS(CAN_TXDL0_BYTE1_POSS,CAN_TXDL0_BYTE1_POSE) + +#define CAN_TXDL0_BYTE0_POSS 0U +#define CAN_TXDL0_BYTE0_POSE 7U +#define CAN_TXDL0_BYTE0_MSK BITS(CAN_TXDL0_BYTE0_POSS,CAN_TXDL0_BYTE0_POSE) + +/****************** Bit definition for CAN_TXDH0 register ************************/ + +#define CAN_TXDH0_BYTE7_POSS 24U +#define CAN_TXDH0_BYTE7_POSE 31U +#define CAN_TXDH0_BYTE7_MSK BITS(CAN_TXDH0_BYTE7_POSS,CAN_TXDH0_BYTE7_POSE) + +#define CAN_TXDH0_BYTE6_POSS 16U +#define CAN_TXDH0_BYTE6_POSE 23U +#define CAN_TXDH0_BYTE6_MSK BITS(CAN_TXDH0_BYTE6_POSS,CAN_TXDH0_BYTE6_POSE) + +#define CAN_TXDH0_BYTE5_POSS 8U +#define CAN_TXDH0_BYTE5_POSE 15U +#define CAN_TXDH0_BYTE5_MSK BITS(CAN_TXDH0_BYTE5_POSS,CAN_TXDH0_BYTE5_POSE) + +#define CAN_TXDH0_BYTE4_POSS 0U +#define CAN_TXDH0_BYTE4_POSE 7U +#define CAN_TXDH0_BYTE4_MSK BITS(CAN_TXDH0_BYTE4_POSS,CAN_TXDH0_BYTE4_POSE) + +/****************** Bit definition for CAN_TXID1 register ************************/ + +#define CAN_TXID1_STDID_POSS 21U +#define CAN_TXID1_STDID_POSE 31U +#define CAN_TXID1_STDID_MSK BITS(CAN_TXID1_STDID_POSS,CAN_TXID1_STDID_POSE) + +#define CAN_TXID1_EXID_POSS 3U +#define CAN_TXID1_EXID_POSE 20U +#define CAN_TXID1_EXID_MSK BITS(CAN_TXID1_EXID_POSS,CAN_TXID1_EXID_POSE) + +#define CAN_TXID1_IDE_POS 2U +#define CAN_TXID1_IDE_MSK BIT(CAN_TXID1_IDE_POS) + +#define CAN_TXID1_RTR_POS 1U +#define CAN_TXID1_RTR_MSK BIT(CAN_TXID1_RTR_POS) + +#define CAN_TXID1_TXMREQ_POS 0U +#define CAN_TXID1_TXMREQ_MSK BIT(CAN_TXID1_TXMREQ_POS) + +/****************** Bit definition for CAN_TXFCON1 register ************************/ + +#define CAN_TXFCON1_STAMP_POSS 16U +#define CAN_TXFCON1_STAMP_POSE 31U +#define CAN_TXFCON1_STAMP_MSK BITS(CAN_TXFCON1_STAMP_POSS,CAN_TXFCON1_STAMP_POSE) + +#define CAN_TXFCON1_TXGT_POS 8U +#define CAN_TXFCON1_TXGT_MSK BIT(CAN_TXFCON1_TXGT_POS) + +#define CAN_TXFCON1_DLEN_POSS 0U +#define CAN_TXFCON1_DLEN_POSE 3U +#define CAN_TXFCON1_DLEN_MSK BITS(CAN_TXFCON1_DLEN_POSS,CAN_TXFCON1_DLEN_POSE) + +/****************** Bit definition for CAN_TXDL1 register ************************/ + +#define CAN_TXDL1_BYTE3_POSS 24U +#define CAN_TXDL1_BYTE3_POSE 31U +#define CAN_TXDL1_BYTE3_MSK BITS(CAN_TXDL1_BYTE3_POSS,CAN_TXDL1_BYTE3_POSE) + +#define CAN_TXDL1_BYTE2_POSS 16U +#define CAN_TXDL1_BYTE2_POSE 23U +#define CAN_TXDL1_BYTE2_MSK BITS(CAN_TXDL1_BYTE2_POSS,CAN_TXDL1_BYTE2_POSE) + +#define CAN_TXDL1_BYTE1_POSS 8U +#define CAN_TXDL1_BYTE1_POSE 15U +#define CAN_TXDL1_BYTE1_MSK BITS(CAN_TXDL1_BYTE1_POSS,CAN_TXDL1_BYTE1_POSE) + +#define CAN_TXDL1_BYTE0_POSS 0U +#define CAN_TXDL1_BYTE0_POSE 7U +#define CAN_TXDL1_BYTE0_MSK BITS(CAN_TXDL1_BYTE0_POSS,CAN_TXDL1_BYTE0_POSE) + +/****************** Bit definition for CAN_TXDH1 register ************************/ + +#define CAN_TXDH1_BYTE7_POSS 24U +#define CAN_TXDH1_BYTE7_POSE 31U +#define CAN_TXDH1_BYTE7_MSK BITS(CAN_TXDH1_BYTE7_POSS,CAN_TXDH1_BYTE7_POSE) + +#define CAN_TXDH1_BYTE6_POSS 16U +#define CAN_TXDH1_BYTE6_POSE 23U +#define CAN_TXDH1_BYTE6_MSK BITS(CAN_TXDH1_BYTE6_POSS,CAN_TXDH1_BYTE6_POSE) + +#define CAN_TXDH1_BYTE5_POSS 8U +#define CAN_TXDH1_BYTE5_POSE 15U +#define CAN_TXDH1_BYTE5_MSK BITS(CAN_TXDH1_BYTE5_POSS,CAN_TXDH1_BYTE5_POSE) + +#define CAN_TXDH1_BYTE4_POSS 0U +#define CAN_TXDH1_BYTE4_POSE 7U +#define CAN_TXDH1_BYTE4_MSK BITS(CAN_TXDH1_BYTE4_POSS,CAN_TXDH1_BYTE4_POSE) + +/****************** Bit definition for CAN_TXID2 register ************************/ + +#define CAN_TXID2_STDID_POSS 21U +#define CAN_TXID2_STDID_POSE 31U +#define CAN_TXID2_STDID_MSK BITS(CAN_TXID2_STDID_POSS,CAN_TXID2_STDID_POSE) + +#define CAN_TXID2_EXID_POSS 3U +#define CAN_TXID2_EXID_POSE 20U +#define CAN_TXID2_EXID_MSK BITS(CAN_TXID2_EXID_POSS,CAN_TXID2_EXID_POSE) + +#define CAN_TXID2_IDE_POS 2U +#define CAN_TXID2_IDE_MSK BIT(CAN_TXID2_IDE_POS) + +#define CAN_TXID2_RTR_POS 1U +#define CAN_TXID2_RTR_MSK BIT(CAN_TXID2_RTR_POS) + +#define CAN_TXID2_TXMREQ_POS 0U +#define CAN_TXID2_TXMREQ_MSK BIT(CAN_TXID2_TXMREQ_POS) + +/****************** Bit definition for CAN_TXFCON2 register ************************/ + +#define CAN_TXFCON2_STAMP_POSS 16U +#define CAN_TXFCON2_STAMP_POSE 31U +#define CAN_TXFCON2_STAMP_MSK BITS(CAN_TXFCON2_STAMP_POSS,CAN_TXFCON2_STAMP_POSE) + +#define CAN_TXFCON2_TXGT_POS 8U +#define CAN_TXFCON2_TXGT_MSK BIT(CAN_TXFCON2_TXGT_POS) + +#define CAN_TXFCON2_DLEN_POSS 0U +#define CAN_TXFCON2_DLEN_POSE 3U +#define CAN_TXFCON2_DLEN_MSK BITS(CAN_TXFCON2_DLEN_POSS,CAN_TXFCON2_DLEN_POSE) + +/****************** Bit definition for CAN_TXDL2 register ************************/ + +#define CAN_TXDL2_BYTE3_POSS 24U +#define CAN_TXDL2_BYTE3_POSE 31U +#define CAN_TXDL2_BYTE3_MSK BITS(CAN_TXDL2_BYTE3_POSS,CAN_TXDL2_BYTE3_POSE) + +#define CAN_TXDL2_BYTE2_POSS 16U +#define CAN_TXDL2_BYTE2_POSE 23U +#define CAN_TXDL2_BYTE2_MSK BITS(CAN_TXDL2_BYTE2_POSS,CAN_TXDL2_BYTE2_POSE) + +#define CAN_TXDL2_BYTE1_POSS 8U +#define CAN_TXDL2_BYTE1_POSE 15U +#define CAN_TXDL2_BYTE1_MSK BITS(CAN_TXDL2_BYTE1_POSS,CAN_TXDL2_BYTE1_POSE) + +#define CAN_TXDL2_BYTE0_POSS 0U +#define CAN_TXDL2_BYTE0_POSE 7U +#define CAN_TXDL2_BYTE0_MSK BITS(CAN_TXDL2_BYTE0_POSS,CAN_TXDL2_BYTE0_POSE) + +/****************** Bit definition for CAN_TXDH2 register ************************/ + +#define CAN_TXDH2_BYTE7_POSS 24U +#define CAN_TXDH2_BYTE7_POSE 31U +#define CAN_TXDH2_BYTE7_MSK BITS(CAN_TXDH2_BYTE7_POSS,CAN_TXDH2_BYTE7_POSE) + +#define CAN_TXDH2_BYTE6_POSS 16U +#define CAN_TXDH2_BYTE6_POSE 23U +#define CAN_TXDH2_BYTE6_MSK BITS(CAN_TXDH2_BYTE6_POSS,CAN_TXDH2_BYTE6_POSE) + +#define CAN_TXDH2_BYTE5_POSS 8U +#define CAN_TXDH2_BYTE5_POSE 15U +#define CAN_TXDH2_BYTE5_MSK BITS(CAN_TXDH2_BYTE5_POSS,CAN_TXDH2_BYTE5_POSE) + +#define CAN_TXDH2_BYTE4_POSS 0U +#define CAN_TXDH2_BYTE4_POSE 7U +#define CAN_TXDH2_BYTE4_MSK BITS(CAN_TXDH2_BYTE4_POSS,CAN_TXDH2_BYTE4_POSE) + +/****************** Bit definition for CAN_RXF0ID register ************************/ + +#define CAN_RXF0ID_STDID_POSS 21U +#define CAN_RXF0ID_STDID_POSE 31U +#define CAN_RXF0ID_STDID_MSK BITS(CAN_RXF0ID_STDID_POSS,CAN_RXF0ID_STDID_POSE) + +#define CAN_RXF0ID_EXID_POSS 3U +#define CAN_RXF0ID_EXID_POSE 20U +#define CAN_RXF0ID_EXID_MSK BITS(CAN_RXF0ID_EXID_POSS,CAN_RXF0ID_EXID_POSE) + +#define CAN_RXF0ID_IDE_POS 2U +#define CAN_RXF0ID_IDE_MSK BIT(CAN_RXF0ID_IDE_POS) + +#define CAN_RXF0ID_RTR_POS 1U +#define CAN_RXF0ID_RTR_MSK BIT(CAN_RXF0ID_RTR_POS) + +/****************** Bit definition for CAN_RXF0INF register ************************/ + +#define CAN_RXF0INF_STAMP_POSS 16U +#define CAN_RXF0INF_STAMP_POSE 31U +#define CAN_RXF0INF_STAMP_MSK BITS(CAN_RXF0INF_STAMP_POSS,CAN_RXF0INF_STAMP_POSE) + +#define CAN_RXF0INF_FLTIDX_POSS 8U +#define CAN_RXF0INF_FLTIDX_POSE 15U +#define CAN_RXF0INF_FLTIDX_MSK BITS(CAN_RXF0INF_FLTIDX_POSS,CAN_RXF0INF_FLTIDX_POSE) + +#define CAN_RXF0INF_DLEN_POSS 0U +#define CAN_RXF0INF_DLEN_POSE 3U +#define CAN_RXF0INF_DLEN_MSK BITS(CAN_RXF0INF_DLEN_POSS,CAN_RXF0INF_DLEN_POSE) + +/****************** Bit definition for CAN_RXF0DL register ************************/ + +#define CAN_RXF0DL_BYTE3_POSS 24U +#define CAN_RXF0DL_BYTE3_POSE 31U +#define CAN_RXF0DL_BYTE3_MSK BITS(CAN_RXF0DL_BYTE3_POSS,CAN_RXF0DL_BYTE3_POSE) + +#define CAN_RXF0DL_BYTE2_POSS 16U +#define CAN_RXF0DL_BYTE2_POSE 23U +#define CAN_RXF0DL_BYTE2_MSK BITS(CAN_RXF0DL_BYTE2_POSS,CAN_RXF0DL_BYTE2_POSE) + +#define CAN_RXF0DL_BYTE1_POSS 8U +#define CAN_RXF0DL_BYTE1_POSE 15U +#define CAN_RXF0DL_BYTE1_MSK BITS(CAN_RXF0DL_BYTE1_POSS,CAN_RXF0DL_BYTE1_POSE) + +#define CAN_RXF0DL_BYTE0_POSS 0U +#define CAN_RXF0DL_BYTE0_POSE 7U +#define CAN_RXF0DL_BYTE0_MSK BITS(CAN_RXF0DL_BYTE0_POSS,CAN_RXF0DL_BYTE0_POSE) + +/****************** Bit definition for CAN_RXF0DH register ************************/ + +#define CAN_RXF0DH_BYTE7_POSS 24U +#define CAN_RXF0DH_BYTE7_POSE 31U +#define CAN_RXF0DH_BYTE7_MSK BITS(CAN_RXF0DH_BYTE7_POSS,CAN_RXF0DH_BYTE7_POSE) + +#define CAN_RXF0DH_BYTE6_POSS 16U +#define CAN_RXF0DH_BYTE6_POSE 23U +#define CAN_RXF0DH_BYTE6_MSK BITS(CAN_RXF0DH_BYTE6_POSS,CAN_RXF0DH_BYTE6_POSE) + +#define CAN_RXF0DH_BYTE5_POSS 8U +#define CAN_RXF0DH_BYTE5_POSE 15U +#define CAN_RXF0DH_BYTE5_MSK BITS(CAN_RXF0DH_BYTE5_POSS,CAN_RXF0DH_BYTE5_POSE) + +#define CAN_RXF0DH_BYTE4_POSS 0U +#define CAN_RXF0DH_BYTE4_POSE 7U +#define CAN_RXF0DH_BYTE4_MSK BITS(CAN_RXF0DH_BYTE4_POSS,CAN_RXF0DH_BYTE4_POSE) + +/****************** Bit definition for CAN_RXF1ID register ************************/ + +#define CAN_RXF1ID_STDID_POSS 21U +#define CAN_RXF1ID_STDID_POSE 31U +#define CAN_RXF1ID_STDID_MSK BITS(CAN_RXF1ID_STDID_POSS,CAN_RXF1ID_STDID_POSE) + +#define CAN_RXF1ID_EXID_POSS 3U +#define CAN_RXF1ID_EXID_POSE 20U +#define CAN_RXF1ID_EXID_MSK BITS(CAN_RXF1ID_EXID_POSS,CAN_RXF1ID_EXID_POSE) + +#define CAN_RXF1ID_IDE_POS 2U +#define CAN_RXF1ID_IDE_MSK BIT(CAN_RXF1ID_IDE_POS) + +#define CAN_RXF1ID_RTR_POS 1U +#define CAN_RXF1ID_RTR_MSK BIT(CAN_RXF1ID_RTR_POS) + +/****************** Bit definition for CAN_RXF1INF register ************************/ + +#define CAN_RXF1INF_STAMP_POSS 16U +#define CAN_RXF1INF_STAMP_POSE 31U +#define CAN_RXF1INF_STAMP_MSK BITS(CAN_RXF1INF_STAMP_POSS,CAN_RXF1INF_STAMP_POSE) + +#define CAN_RXF1INF_FLTIDX_POSS 8U +#define CAN_RXF1INF_FLTIDX_POSE 15U +#define CAN_RXF1INF_FLTIDX_MSK BITS(CAN_RXF1INF_FLTIDX_POSS,CAN_RXF1INF_FLTIDX_POSE) + +#define CAN_RXF1INF_DLEN_POSS 0U +#define CAN_RXF1INF_DLEN_POSE 3U +#define CAN_RXF1INF_DLEN_MSK BITS(CAN_RXF1INF_DLEN_POSS,CAN_RXF1INF_DLEN_POSE) + +/****************** Bit definition for CAN_RXF1DL register ************************/ + +#define CAN_RXF1DL_BYTE3_POSS 24U +#define CAN_RXF1DL_BYTE3_POSE 31U +#define CAN_RXF1DL_BYTE3_MSK BITS(CAN_RXF1DL_BYTE3_POSS,CAN_RXF1DL_BYTE3_POSE) + +#define CAN_RXF1DL_BYTE2_POSS 16U +#define CAN_RXF1DL_BYTE2_POSE 23U +#define CAN_RXF1DL_BYTE2_MSK BITS(CAN_RXF1DL_BYTE2_POSS,CAN_RXF1DL_BYTE2_POSE) + +#define CAN_RXF1DL_BYTE1_POSS 8U +#define CAN_RXF1DL_BYTE1_POSE 15U +#define CAN_RXF1DL_BYTE1_MSK BITS(CAN_RXF1DL_BYTE1_POSS,CAN_RXF1DL_BYTE1_POSE) + +#define CAN_RXF1DL_BYTE0_POSS 0U +#define CAN_RXF1DL_BYTE0_POSE 7U +#define CAN_RXF1DL_BYTE0_MSK BITS(CAN_RXF1DL_BYTE0_POSS,CAN_RXF1DL_BYTE0_POSE) + +/****************** Bit definition for CAN_RXF1DH register ************************/ + +#define CAN_RXF1DH_BYTE7_POSS 24U +#define CAN_RXF1DH_BYTE7_POSE 31U +#define CAN_RXF1DH_BYTE7_MSK BITS(CAN_RXF1DH_BYTE7_POSS,CAN_RXF1DH_BYTE7_POSE) + +#define CAN_RXF1DH_BYTE6_POSS 16U +#define CAN_RXF1DH_BYTE6_POSE 23U +#define CAN_RXF1DH_BYTE6_MSK BITS(CAN_RXF1DH_BYTE6_POSS,CAN_RXF1DH_BYTE6_POSE) + +#define CAN_RXF1DH_BYTE5_POSS 8U +#define CAN_RXF1DH_BYTE5_POSE 15U +#define CAN_RXF1DH_BYTE5_MSK BITS(CAN_RXF1DH_BYTE5_POSS,CAN_RXF1DH_BYTE5_POSE) + +#define CAN_RXF1DH_BYTE4_POSS 0U +#define CAN_RXF1DH_BYTE4_POSE 7U +#define CAN_RXF1DH_BYTE4_MSK BITS(CAN_RXF1DH_BYTE4_POSS,CAN_RXF1DH_BYTE4_POSE) + +/****************** Bit definition for CAN_FLTCON register ************************/ + +#define CAN_FLTCON_FLTINI_POS 0U +#define CAN_FLTCON_FLTINI_MSK BIT(CAN_FLTCON_FLTINI_POS) + +/****************** Bit definition for CAN_FLTM register ************************/ + +#define CAN_FLTM_MOD_POSS 0U +#define CAN_FLTM_MOD_POSE 13U +#define CAN_FLTM_MOD_MSK BITS(CAN_FLTM_MOD_POSS,CAN_FLTM_MOD_POSE) + +/****************** Bit definition for CAN_FLTWS register ************************/ + +#define CAN_FLTWS_SEL_POSS 0U +#define CAN_FLTWS_SEL_POSE 13U +#define CAN_FLTWS_SEL_MSK BITS(CAN_FLTWS_SEL_POSS,CAN_FLTWS_SEL_POSE) + +/****************** Bit definition for CAN_FLTAS register ************************/ + +#define CAN_FLTAS_ASSIGN_POSS 0U +#define CAN_FLTAS_ASSIGN_POSE 13U +#define CAN_FLTAS_ASSIGN_MSK BITS(CAN_FLTAS_ASSIGN_POSS,CAN_FLTAS_ASSIGN_POSE) + +/****************** Bit definition for CAN_FLTGO register ************************/ + +#define CAN_FLTGO_GO_POSS 0U +#define CAN_FLTGO_GO_POSE 13U +#define CAN_FLTGO_GO_MSK BITS(CAN_FLTGO_GO_POSS,CAN_FLTGO_GO_POSE) + +typedef struct { + __IO uint32_t TXID; + __IO uint32_t TXFCON; + __IO uint32_t TXDL; + __IO uint32_t TXDH; +} CAN_TxMailBox_Typedef; + +typedef struct { + __IO uint32_t RXFID; + __IO uint32_t RXFINF; + __IO uint32_t RXFDL; + __IO uint32_t RXFDH; +} CAN_RxFIFO_Typedef; + +typedef struct { + __IO uint32_t FLT1; + __IO uint32_t FLT2; +} CAN_Filter_Typedef; + +typedef struct +{ + __IO uint32_t CON; + __I uint32_t STAT; + __O uint32_t IFC; + __IO uint32_t TXSTAT; + __O uint32_t TXSTATC; + __IO uint32_t RXF0; + __O uint32_t RXF0C; + __IO uint32_t RXF1; + __O uint32_t RXF1C; + __IO uint32_t IE; + __IO uint32_t ERRSTAT; + __IO uint32_t BTIME; + uint32_t RESERVED0[84] ; + CAN_TxMailBox_Typedef TxMailBox[3]; + CAN_RxFIFO_Typedef RxFIFO[2]; + uint32_t RESERVED1[12] ; + __IO uint32_t FLTCON; + __IO uint32_t FLTM; + uint32_t RESERVED2 ; + __IO uint32_t FLTWS; + uint32_t RESERVED3 ; + __IO uint32_t FLTAS; + uint32_t RESERVED4 ; + __IO uint32_t FLTGO; + uint32_t RESERVED5[8] ; + CAN_Filter_Typedef Filter[14]; +} CAN_TypeDef; + +/****************** Bit definition for CRC_CR register ************************/ +#define CRC_CR_BYTORD_POS 24U +#define CRC_CR_BYTORD_MSK BIT(CRC_CR_BYTORD_POS) + +#define CRC_CR_DATLEN_POSS 22U +#define CRC_CR_DATLEN_POSE 23U +#define CRC_CR_DATLEN_MSK BITS(CRC_CR_DATLEN_POSS,CRC_CR_DATLEN_POSE) + +#define CRC_CR_MODE_POSS 20U +#define CRC_CR_MODE_POSE 21U +#define CRC_CR_MODE_MSK BITS(CRC_CR_MODE_POSS,CRC_CR_MODE_POSE) + +#define CRC_CR_CHSINV_POS 19U +#define CRC_CR_CHSINV_MSK BIT(CRC_CR_CHSINV_POS) + +#define CRC_CR_DATINV_POS 18U +#define CRC_CR_DATINV_MSK BIT(CRC_CR_DATINV_POS) + +#define CRC_CR_CHSREV_POS 17U +#define CRC_CR_CHSREV_MSK BIT(CRC_CR_CHSREV_POS) + +#define CRC_CR_DATREV_POS 16U +#define CRC_CR_DATREV_MSK BIT(CRC_CR_DATREV_POS) + +#define CRC_CR_DMAEN_POS 4U +#define CRC_CR_DMAEN_MSK BIT(CRC_CR_DMAEN_POS) + +#define CRC_CR_CWERR_POS 3U +#define CRC_CR_CWERR_MSK BIT(CRC_CR_CWERR_POS) + +#define CRC_CR_WERR_POS 2U +#define CRC_CR_WERR_MSK BIT(CRC_CR_WERR_POS) + +#define CRC_CR_RST_POS 1U +#define CRC_CR_RST_MSK BIT(CRC_CR_RST_POS) + +#define CRC_CR_EN_POS 0U +#define CRC_CR_EN_MSK BIT(CRC_CR_EN_POS) + +/****************** Bit definition for CRC_DATA register ************************/ + +#define CRC_DATA_DATA_POSS 0U +#define CRC_DATA_DATA_POSE 31U +#define CRC_DATA_DATA_MSK BITS(CRC_DATA_DATA_POSS,CRC_DATA_DATA_POSE) + +/****************** Bit definition for CRC_SEED register ************************/ + +#define CRC_SEED_SEED_POSS 0U +#define CRC_SEED_SEED_POSE 31U +#define CRC_SEED_SEED_MSK BITS(CRC_SEED_SEED_POSS,CRC_SEED_SEED_POSE) + +/****************** Bit definition for CRC_CHECKSUM register ************************/ + +#define CRC_CHECKSUM_CHECKSUM_POSS 0U +#define CRC_CHECKSUM_CHECKSUM_POSE 31U +#define CRC_CHECKSUM_CHECKSUM_MSK BITS(CRC_CHECKSUM_CHECKSUM_POSS,CRC_CHECKSUM_CHECKSUM_POSE) + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t DATA; + __IO uint32_t SEED; + __I uint32_t CHECKSUM; +} CRC_TypeDef; + +/****************** Bit definition for CRYPT_CON register ************************/ + +#define CRYPT_CON_CRYSEL_POS 31U +#define CRYPT_CON_CRYSEL_MSK BIT(CRYPT_CON_CRYSEL_POS) + +#define CRYPT_CON_RESCLR_POS 15U +#define CRYPT_CON_RESCLR_MSK BIT(CRYPT_CON_RESCLR_POS) + +#define CRYPT_CON_DMAEN_POS 14U +#define CRYPT_CON_DMAEN_MSK BIT(CRYPT_CON_DMAEN_POS) + +#define CRYPT_CON_FIFOODR_POS 13U +#define CRYPT_CON_FIFOODR_MSK BIT(CRYPT_CON_FIFOODR_POS) + +#define CRYPT_CON_FIFOEN_POS 12U +#define CRYPT_CON_FIFOEN_MSK BIT(CRYPT_CON_FIFOEN_POS) + +#define CRYPT_CON_DESKS_POS 11U +#define CRYPT_CON_DESKS_MSK BIT(CRYPT_CON_DESKS_POS) + +#define CRYPT_CON_TDES_POS 10U +#define CRYPT_CON_TDES_MSK BIT(CRYPT_CON_TDES_POS) + +#define CRYPT_CON_TYPE_POSS 8U +#define CRYPT_CON_TYPE_POSE 9U +#define CRYPT_CON_TYPE_MSK BITS(CRYPT_CON_TYPE_POSS,CRYPT_CON_TYPE_POSE) + +#define CRYPT_CON_IE_POS 7U +#define CRYPT_CON_IE_MSK BIT(CRYPT_CON_IE_POS) + +#define CRYPT_CON_IVEN_POS 6U +#define CRYPT_CON_IVEN_MSK BIT(CRYPT_CON_IVEN_POS) + +#define CRYPT_CON_MODE_POSS 4U +#define CRYPT_CON_MODE_POSE 5U +#define CRYPT_CON_MODE_MSK BITS(CRYPT_CON_MODE_POSS,CRYPT_CON_MODE_POSE) + +#define CRYPT_CON_AESKS_POSS 2U +#define CRYPT_CON_AESKS_POSE 3U +#define CRYPT_CON_AESKS_MSK BITS(CRYPT_CON_AESKS_POSS,CRYPT_CON_AESKS_POSE) + +#define CRYPT_CON_ENCS_POS 1U +#define CRYPT_CON_ENCS_MSK BIT(CRYPT_CON_ENCS_POS) + +#define CRYPT_CON_GO_POS 0U +#define CRYPT_CON_GO_MSK BIT(CRYPT_CON_GO_POS) + +/****************** Bit definition for CRYPT_IF register ************************/ + +#define CRYPT_IF_DONE_POS 8U +#define CRYPT_IF_DONE_MSK BIT(CRYPT_IF_DONE_POS) + +#define CRYPT_IF_MULTHIF_POS 2U +#define CRYPT_IF_MULTHIF_MSK BIT(CRYPT_IF_MULTHIF_POS) + +#define CRYPT_IF_DESIF_POS 1U +#define CRYPT_IF_DESIF_MSK BIT(CRYPT_IF_DESIF_POS) + +#define CRYPT_IF_AESIF_POS 0U +#define CRYPT_IF_AESIF_MSK BIT(CRYPT_IF_AESIF_POS) + +/****************** Bit definition for CRYPT_IFC register ************************/ + +#define CRYPT_IFC_MULTHIFC_POS 2U +#define CRYPT_IFC_MULTHIFC_MSK BIT(CRYPT_IFC_MULTHIFC_POS) + +#define CRYPT_IFC_DESIFC_POS 1U +#define CRYPT_IFC_DESIFC_MSK BIT(CRYPT_IFC_DESIFC_POS) + +#define CRYPT_IFC_AESIFC_POS 0U +#define CRYPT_IFC_AESIFC_MSK BIT(CRYPT_IFC_AESIFC_POS) + +/****************** Bit definition for CRYPT_FIFO register ************************/ + +#define CRYPT_FIFO_FIFO_POSS 0U +#define CRYPT_FIFO_FIFO_POSE 31U +#define CRYPT_FIFO_FIFO_MSK BITS(CRYPT_FIFO_FIFO_POSS,CRYPT_FIFO_FIFO_POSE) + +typedef struct +{ + __IO uint32_t DATA[4]; + __IO uint32_t KEY[8]; + __IO uint32_t IV[4]; + __I uint32_t RES[4]; + __IO uint32_t CON; + __I uint32_t IF; + __O uint32_t IFC; + __IO uint32_t FIFO; +} CRYPT_TypeDef; + +/****************** Bit definition for ADC_STAT register ************************/ + +#define ADC_STAT_ICHS_POS 9U +#define ADC_STAT_ICHS_MSK BIT(ADC_STAT_ICHS_POS) + +#define ADC_STAT_NCHS_POS 8U +#define ADC_STAT_NCHS_MSK BIT(ADC_STAT_NCHS_POS) + +#define ADC_STAT_OVR_POS 3U +#define ADC_STAT_OVR_MSK BIT(ADC_STAT_OVR_POS) + +#define ADC_STAT_ICHE_POS 2U +#define ADC_STAT_ICHE_MSK BIT(ADC_STAT_ICHE_POS) + +#define ADC_STAT_NCHE_POS 1U +#define ADC_STAT_NCHE_MSK BIT(ADC_STAT_NCHE_POS) + +#define ADC_STAT_AWDF_POS 0U +#define ADC_STAT_AWDF_MSK BIT(ADC_STAT_AWDF_POS) + +/****************** Bit definition for ADC_CLR register ************************/ + +#define ADC_CLR_ICHS_POS 9U +#define ADC_CLR_ICHS_MSK BIT(ADC_CLR_ICHS_POS) + +#define ADC_CLR_NCHS_POS 8U +#define ADC_CLR_NCHS_MSK BIT(ADC_CLR_NCHS_POS) + +#define ADC_CLR_OVR_POS 3U +#define ADC_CLR_OVR_MSK BIT(ADC_CLR_OVR_POS) + +#define ADC_CLR_ICHE_POS 2U +#define ADC_CLR_ICHE_MSK BIT(ADC_CLR_ICHE_POS) + +#define ADC_CLR_NCHE_POS 1U +#define ADC_CLR_NCHE_MSK BIT(ADC_CLR_NCHE_POS) + +#define ADC_CLR_AWDF_POS 0U +#define ADC_CLR_AWDF_MSK BIT(ADC_CLR_AWDF_POS) + +/****************** Bit definition for ADC_CON0 register ************************/ + +#define ADC_CON0_OVRIE_POS 26U +#define ADC_CON0_OVRIE_MSK BIT(ADC_CON0_OVRIE_POS) + +#define ADC_CON0_RSEL_POSS 24U +#define ADC_CON0_RSEL_POSE 25U +#define ADC_CON0_RSEL_MSK BITS(ADC_CON0_RSEL_POSS,ADC_CON0_RSEL_POSE) + +#define ADC_CON0_NCHWDEN_POS 23U +#define ADC_CON0_NCHWDEN_MSK BIT(ADC_CON0_NCHWDEN_POS) + +#define ADC_CON0_ICHWDTEN_POS 22U +#define ADC_CON0_ICHWDTEN_MSK BIT(ADC_CON0_ICHWDTEN_POS) + +#define ADC_CON0_ETRGN_POSS 13U +#define ADC_CON0_ETRGN_POSE 15U +#define ADC_CON0_ETRGN_MSK BITS(ADC_CON0_ETRGN_POSS,ADC_CON0_ETRGN_POSE) + +#define ADC_CON0_ICHDCEN_POS 12U +#define ADC_CON0_ICHDCEN_MSK BIT(ADC_CON0_ICHDCEN_POS) + +#define ADC_CON0_NCHDCEN_POS 11U +#define ADC_CON0_NCHDCEN_MSK BIT(ADC_CON0_NCHDCEN_POS) + +#define ADC_CON0_IAUTO_POS 10U +#define ADC_CON0_IAUTO_MSK BIT(ADC_CON0_IAUTO_POS) + +#define ADC_CON0_AWDSGL_POS 9U +#define ADC_CON0_AWDSGL_MSK BIT(ADC_CON0_AWDSGL_POS) + +#define ADC_CON0_SCANEN_POS 8U +#define ADC_CON0_SCANEN_MSK BIT(ADC_CON0_SCANEN_POS) + +#define ADC_CON0_ICHEIE_POS 7U +#define ADC_CON0_ICHEIE_MSK BIT(ADC_CON0_ICHEIE_POS) + +#define ADC_CON0_AWDIE_POS 6U +#define ADC_CON0_AWDIE_MSK BIT(ADC_CON0_AWDIE_POS) + +#define ADC_CON0_NCHEIE_POS 5U +#define ADC_CON0_NCHEIE_MSK BIT(ADC_CON0_NCHEIE_POS) + +#define ADC_CON0_AWDCH_POSS 0U +#define ADC_CON0_AWDCH_POSE 4U +#define ADC_CON0_AWDCH_MSK BITS(ADC_CON0_AWDCH_POSS,ADC_CON0_AWDCH_POSE) + +/****************** Bit definition for ADC_CON1 register ************************/ + +#define ADC_CON1_NCHTRG_POS 30U +#define ADC_CON1_NCHTRG_MSK BIT(ADC_CON1_NCHTRG_POS) + +#define ADC_CON1_NETS_POSS 28U +#define ADC_CON1_NETS_POSE 29U +#define ADC_CON1_NETS_MSK BITS(ADC_CON1_NETS_POSS,ADC_CON1_NETS_POSE) + +#define ADC_CON1_ICHTRG_POS 22U +#define ADC_CON1_ICHTRG_MSK BIT(ADC_CON1_ICHTRG_POS) + +#define ADC_CON1_IETS_POSS 20U +#define ADC_CON1_IETS_POSE 21U +#define ADC_CON1_IETS_MSK BITS(ADC_CON1_IETS_POSS,ADC_CON1_IETS_POSE) + +#define ADC_CON1_ALIGN_POS 11U +#define ADC_CON1_ALIGN_MSK BIT(ADC_CON1_ALIGN_POS) + +#define ADC_CON1_NCHESEL_POS 10U +#define ADC_CON1_NCHESEL_MSK BIT(ADC_CON1_NCHESEL_POS) + +#define ADC_CON1_DMA_POS 8U +#define ADC_CON1_DMA_MSK BIT(ADC_CON1_DMA_POS) + +#define ADC_CON1_CM_POS 1U +#define ADC_CON1_CM_MSK BIT(ADC_CON1_CM_POS) + +#define ADC_CON1_ADCEN_POS 0U +#define ADC_CON1_ADCEN_MSK BIT(ADC_CON1_ADCEN_POS) + +/****************** Bit definition for ADC_SMPT1 register ************************/ + +#define ADC_SMPT1_CHT_POSS 0U +#define ADC_SMPT1_CHT_POSE 31U +#define ADC_SMPT1_CHT_MSK BITS(ADC_SMPT1_CHT_POSS,ADC_SMPT1_CHT_POSE) + +/****************** Bit definition for ADC_SMPT2 register ************************/ + +#define ADC_SMPT2_CHT_POSS 0U +#define ADC_SMPT2_CHT_POSE 31U +#define ADC_SMPT2_CHT_MSK BITS(ADC_SMPT2_CHT_POSS,ADC_SMPT2_CHT_POSE) + +/****************** Bit definition for ADC_SMPT3 register ************************/ + +#define ADC_SMPT3_SMP_POSS 0U +#define ADC_SMPT3_SMP_POSE 31U +#define ADC_SMPT3_SMP_MSK BITS(ADC_SMPT3_SMP_POSS,ADC_SMPT3_SMP_POSE) + +/****************** Bit definition for ADC_ICHOFF1 register ************************/ + +#define ADC_ICHOFF1_IOFF_POSS 0U +#define ADC_ICHOFF1_IOFF_POSE 11U +#define ADC_ICHOFF1_IOFF_MSK BITS(ADC_ICHOFF1_IOFF_POSS,ADC_ICHOFF1_IOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF2 register ************************/ + +#define ADC_ICHOFF2_IOFF_POSS 0U +#define ADC_ICHOFF2_IOFF_POSE 11U +#define ADC_ICHOFF2_IOFF_MSK BITS(ADC_ICHOFF2_IOFF_POSS,ADC_ICHOFF2_IOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF3 register ************************/ + +#define ADC_ICHOFF3_IOFF_POSS 0U +#define ADC_ICHOFF3_IOFF_POSE 11U +#define ADC_ICHOFF3_IOFF_MSK BITS(ADC_ICHOFF3_IOFF_POSS,ADC_ICHOFF3_IOFF_POSE) + +/****************** Bit definition for ADC_ICHOFF4 register ************************/ + +#define ADC_ICHOFF4_IOFF_POSS 0U +#define ADC_ICHOFF4_IOFF_POSE 11U +#define ADC_ICHOFF4_IOFF_MSK BITS(ADC_ICHOFF4_IOFF_POSS,ADC_ICHOFF4_IOFF_POSE) + +/****************** Bit definition for ADC_NCHS1 register ************************/ + +#define ADC_NCHS1_NS4_POSS 24U +#define ADC_NCHS1_NS4_POSE 28U +#define ADC_NCHS1_NS4_MSK BITS(ADC_NCHS1_NS4_POSS,ADC_NCHS1_NS4_POSE) + +#define ADC_NCHS1_NS3_POSS 16U +#define ADC_NCHS1_NS3_POSE 20U +#define ADC_NCHS1_NS3_MSK BITS(ADC_NCHS1_NS3_POSS,ADC_NCHS1_NS3_POSE) + +#define ADC_NCHS1_NS2_POSS 8U +#define ADC_NCHS1_NS2_POSE 12U +#define ADC_NCHS1_NS2_MSK BITS(ADC_NCHS1_NS2_POSS,ADC_NCHS1_NS2_POSE) + +#define ADC_NCHS1_NS1_POSS 0U +#define ADC_NCHS1_NS1_POSE 4U +#define ADC_NCHS1_NS1_MSK BITS(ADC_NCHS1_NS1_POSS,ADC_NCHS1_NS1_POSE) + +/****************** Bit definition for ADC_NCHS2 register ************************/ + +#define ADC_NCHS2_NS8_POSS 24U +#define ADC_NCHS2_NS8_POSE 28U +#define ADC_NCHS2_NS8_MSK BITS(ADC_NCHS2_NS8_POSS,ADC_NCHS2_NS8_POSE) + +#define ADC_NCHS2_NS7_POSS 16U +#define ADC_NCHS2_NS7_POSE 20U +#define ADC_NCHS2_NS7_MSK BITS(ADC_NCHS2_NS7_POSS,ADC_NCHS2_NS7_POSE) + +#define ADC_NCHS2_NS6_POSS 8U +#define ADC_NCHS2_NS6_POSE 12U +#define ADC_NCHS2_NS6_MSK BITS(ADC_NCHS2_NS6_POSS,ADC_NCHS2_NS6_POSE) + +#define ADC_NCHS2_NS5_POSS 0U +#define ADC_NCHS2_NS5_POSE 4U +#define ADC_NCHS2_NS5_MSK BITS(ADC_NCHS2_NS5_POSS,ADC_NCHS2_NS5_POSE) + +/****************** Bit definition for ADC_NCHS3 register ************************/ + +#define ADC_NCHS3_NS12_POSS 24U +#define ADC_NCHS3_NS12_POSE 28U +#define ADC_NCHS3_NS12_MSK BITS(ADC_NCHS3_NS12_POSS,ADC_NCHS3_NS12_POSE) + +#define ADC_NCHS3_NS11_POSS 16U +#define ADC_NCHS3_NS11_POSE 20U +#define ADC_NCHS3_NS11_MSK BITS(ADC_NCHS3_NS11_POSS,ADC_NCHS3_NS11_POSE) + +#define ADC_NCHS3_NS10_POSS 8U +#define ADC_NCHS3_NS10_POSE 12U +#define ADC_NCHS3_NS10_MSK BITS(ADC_NCHS3_NS10_POSS,ADC_NCHS3_NS10_POSE) + +#define ADC_NCHS3_NS9_POSS 0U +#define ADC_NCHS3_NS9_POSE 4U +#define ADC_NCHS3_NS9_MSK BITS(ADC_NCHS3_NS9_POSS,ADC_NCHS3_NS9_POSE) + +/****************** Bit definition for ADC_NCHS4 register ************************/ + +#define ADC_NCHS4_NS16_POSS 24U +#define ADC_NCHS4_NS16_POSE 28U +#define ADC_NCHS4_NS16_MSK BITS(ADC_NCHS4_NS16_POSS,ADC_NCHS4_NS16_POSE) + +#define ADC_NCHS4_NS15_POSS 16U +#define ADC_NCHS4_NS15_POSE 20U +#define ADC_NCHS4_NS15_MSK BITS(ADC_NCHS4_NS15_POSS,ADC_NCHS4_NS15_POSE) + +#define ADC_NCHS4_NS14_POSS 8U +#define ADC_NCHS4_NS14_POSE 12U +#define ADC_NCHS4_NS14_MSK BITS(ADC_NCHS4_NS14_POSS,ADC_NCHS4_NS14_POSE) + +#define ADC_NCHS4_NS13_POSS 0U +#define ADC_NCHS4_NS13_POSE 4U +#define ADC_NCHS4_NS13_MSK BITS(ADC_NCHS4_NS13_POSS,ADC_NCHS4_NS13_POSE) + +/****************** Bit definition for ADC_ICHS register ************************/ + +#define ADC_ICHS_IS4_POSS 24U +#define ADC_ICHS_IS4_POSE 28U +#define ADC_ICHS_IS4_MSK BITS(ADC_ICHS_IS4_POSS,ADC_ICHS_IS4_POSE) + +#define ADC_ICHS_IS3_POSS 16U +#define ADC_ICHS_IS3_POSE 20U +#define ADC_ICHS_IS3_MSK BITS(ADC_ICHS_IS3_POSS,ADC_ICHS_IS3_POSE) + +#define ADC_ICHS_IS2_POSS 8U +#define ADC_ICHS_IS2_POSE 12U +#define ADC_ICHS_IS2_MSK BITS(ADC_ICHS_IS2_POSS,ADC_ICHS_IS2_POSE) + +#define ADC_ICHS_IS1_POSS 0U +#define ADC_ICHS_IS1_POSE 4U +#define ADC_ICHS_IS1_MSK BITS(ADC_ICHS_IS1_POSS,ADC_ICHS_IS1_POSE) + +/****************** Bit definition for ADC_CHSL register ************************/ + +#define ADC_CHSL_ISL_POSS 8U +#define ADC_CHSL_ISL_POSE 9U +#define ADC_CHSL_ISL_MSK BITS(ADC_CHSL_ISL_POSS,ADC_CHSL_ISL_POSE) + +#define ADC_CHSL_NSL_POSS 0U +#define ADC_CHSL_NSL_POSE 3U +#define ADC_CHSL_NSL_MSK BITS(ADC_CHSL_NSL_POSS,ADC_CHSL_NSL_POSE) + +/****************** Bit definition for ADC_WDTH register ************************/ + +#define ADC_WDTH_HT_POSS 0U +#define ADC_WDTH_HT_POSE 11U +#define ADC_WDTH_HT_MSK BITS(ADC_WDTH_HT_POSS,ADC_WDTH_HT_POSE) + +/****************** Bit definition for ADC_WDTL register ************************/ + +#define ADC_WDTL_LT_POSS 0U +#define ADC_WDTL_LT_POSE 11U +#define ADC_WDTL_LT_MSK BITS(ADC_WDTL_LT_POSS,ADC_WDTL_LT_POSE) + +/****************** Bit definition for ADC_ICHDR1 register ************************/ + +#define ADC_ICHDR1_VAL_POSS 0U +#define ADC_ICHDR1_VAL_POSE 15U +#define ADC_ICHDR1_VAL_MSK BITS(ADC_ICHDR1_VAL_POSS,ADC_ICHDR1_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR2 register ************************/ + +#define ADC_ICHDR2_VAL_POSS 0U +#define ADC_ICHDR2_VAL_POSE 15U +#define ADC_ICHDR2_VAL_MSK BITS(ADC_ICHDR2_VAL_POSS,ADC_ICHDR2_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR3 register ************************/ + +#define ADC_ICHDR3_VAL_POSS 0U +#define ADC_ICHDR3_VAL_POSE 15U +#define ADC_ICHDR3_VAL_MSK BITS(ADC_ICHDR3_VAL_POSS,ADC_ICHDR3_VAL_POSE) + +/****************** Bit definition for ADC_ICHDR4 register ************************/ + +#define ADC_ICHDR4_VAL_POSS 0U +#define ADC_ICHDR4_VAL_POSE 15U +#define ADC_ICHDR4_VAL_MSK BITS(ADC_ICHDR4_VAL_POSS,ADC_ICHDR4_VAL_POSE) + +/****************** Bit definition for ADC_NCHDR register ************************/ + +#define ADC_NCHDR_VAL_POSS 0U +#define ADC_NCHDR_VAL_POSE 15U +#define ADC_NCHDR_VAL_MSK BITS(ADC_NCHDR_VAL_POSS,ADC_NCHDR_VAL_POSE) + +/****************** Bit definition for ADC_CCR register ************************/ + +#define ADC_CCR_ADCH_PBUF_EN_POS 31U +#define ADC_CCR_ADCH_PBUF_EN_MSK BIT(ADC_CCR_ADCH_PBUF_EN_POS) + +#define ADC_CCR_ADCH_NBUF_EN_POS 30U +#define ADC_CCR_ADCH_NBUF_EN_MSK BIT(ADC_CCR_ADCH_NBUF_EN_POS) + +#define ADC_CCR_ADCH_INBUF_CALEN_POS 29U +#define ADC_CCR_ADCH_INBUF_CALEN_MSK BIT(ADC_CCR_ADCH_INBUF_CALEN_POS) + +#define ADC_CCR_TRMEN_POS 28U +#define ADC_CCR_TRMEN_MSK BIT(ADC_CCR_TRMEN_POS) + +#define ADC_CCR_GAINCALEN_POS 25U +#define ADC_CCR_GAINCALEN_MSK BIT(ADC_CCR_GAINCALEN_POS) + +#define ADC_CCR_OFFCALEN_POS 24U +#define ADC_CCR_OFFCALEN_MSK BIT(ADC_CCR_OFFCALEN_POS) + +#define ADC_CCR_VREFOEN_POS 19U +#define ADC_CCR_VREFOEN_MSK BIT(ADC_CCR_VREFOEN_POS) + +#define ADC_CCR_VRNSEL_POS 18U +#define ADC_CCR_VRNSEL_MSK BIT(ADC_CCR_VRNSEL_POS) + +#define ADC_CCR_VRPSEL_POSS 16U +#define ADC_CCR_VRPSEL_POSE 17U +#define ADC_CCR_VRPSEL_MSK BITS(ADC_CCR_VRPSEL_POSS,ADC_CCR_VRPSEL_POSE) + +#define ADC_CCR_PWRMODSEL_POS 15U +#define ADC_CCR_PWRMODSEL_MSK BIT(ADC_CCR_PWRMODSEL_POS) + +#define ADC_CCR_DIFFEN_POS 12U +#define ADC_CCR_DIFFEN_MSK BIT(ADC_CCR_DIFFEN_POS) + +#define ADC_CCR_IREFEN_POS 11U +#define ADC_CCR_IREFEN_MSK BIT(ADC_CCR_IREFEN_POS) + +#define ADC_CCR_VRBUFEN_POS 10U +#define ADC_CCR_VRBUFEN_MSK BIT(ADC_CCR_VRBUFEN_POS) + +#define ADC_CCR_VCMBUFEN_POS 9U +#define ADC_CCR_VCMBUFEN_MSK BIT(ADC_CCR_VCMBUFEN_POS) + +#define ADC_CCR_VREFEN_POS 8U +#define ADC_CCR_VREFEN_MSK BIT(ADC_CCR_VREFEN_POS) + +#define ADC_CCR_CKDIV_POSS 0U +#define ADC_CCR_CKDIV_POSE 2U +#define ADC_CCR_CKDIV_MSK BITS(ADC_CCR_CKDIV_POSS,ADC_CCR_CKDIV_POSE) + +typedef struct +{ + __I uint32_t STAT; + __O uint32_t CLR; + __IO uint32_t CON0; + __IO uint32_t CON1; + __IO uint32_t SMPT1; + __IO uint32_t SMPT2; + __IO uint32_t SMPT3; + __IO uint32_t RESERVED; + __IO uint32_t ICHOFF1; + __IO uint32_t ICHOFF2; + __IO uint32_t ICHOFF3; + __IO uint32_t ICHOFF4; + __IO uint32_t NCHS1; + __IO uint32_t NCHS2; + __IO uint32_t NCHS3; + __IO uint32_t NCHS4; + __IO uint32_t ICHS; + __IO uint32_t CHSL; + __IO uint32_t WDTH; + __IO uint32_t WDTL; + __I uint32_t ICHDR1; + __I uint32_t ICHDR2; + __I uint32_t ICHDR3; + __I uint32_t ICHDR4; + __I uint32_t NCHDR; + __IO uint32_t CCR; +} ADC_TypeDef; + +/****************** Bit definition for ACMP_CON register ************************/ + +#define ACMP_CON_FALLEN_POS 17U +#define ACMP_CON_FALLEN_MSK BIT(ACMP_CON_FALLEN_POS) + +#define ACMP_CON_RISEEN_POS 16U +#define ACMP_CON_RISEEN_MSK BIT(ACMP_CON_RISEEN_POS) + +#define ACMP_CON_MODSEL_POSS 14U +#define ACMP_CON_MODSEL_POSE 15U +#define ACMP_CON_MODSEL_MSK BITS(ACMP_CON_MODSEL_POSS,ACMP_CON_MODSEL_POSE) + +#define ACMP_CON_WARMUPT_POSS 8U +#define ACMP_CON_WARMUPT_POSE 10U +#define ACMP_CON_WARMUPT_MSK BITS(ACMP_CON_WARMUPT_POSS,ACMP_CON_WARMUPT_POSE) + +#define ACMP_CON_HYSTSEL_POSS 4U +#define ACMP_CON_HYSTSEL_POSE 6U +#define ACMP_CON_HYSTSEL_MSK BITS(ACMP_CON_HYSTSEL_POSS,ACMP_CON_HYSTSEL_POSE) + +#define ACMP_CON_OUTINV_POS 3U +#define ACMP_CON_OUTINV_MSK BIT(ACMP_CON_OUTINV_POS) + +#define ACMP_CON_INACTV_POS 2U +#define ACMP_CON_INACTV_MSK BIT(ACMP_CON_INACTV_POS) + +#define ACMP_CON_EN_POS 0U +#define ACMP_CON_EN_MSK BIT(ACMP_CON_EN_POS) + +/****************** Bit definition for ACMP_INPUTSEL register ************************/ + +#define ACMP_INPUTSEL_VDDLVL_POSS 8U +#define ACMP_INPUTSEL_VDDLVL_POSE 13U +#define ACMP_INPUTSEL_VDDLVL_MSK BITS(ACMP_INPUTSEL_VDDLVL_POSS,ACMP_INPUTSEL_VDDLVL_POSE) + +#define ACMP_INPUTSEL_NSEL_POSS 4U +#define ACMP_INPUTSEL_NSEL_POSE 7U +#define ACMP_INPUTSEL_NSEL_MSK BITS(ACMP_INPUTSEL_NSEL_POSS,ACMP_INPUTSEL_NSEL_POSE) + +#define ACMP_INPUTSEL_PSEL_POSS 0U +#define ACMP_INPUTSEL_PSEL_POSE 2U +#define ACMP_INPUTSEL_PSEL_MSK BITS(ACMP_INPUTSEL_PSEL_POSS,ACMP_INPUTSEL_PSEL_POSE) + +/****************** Bit definition for ACMP_STAT register ************************/ + +#define ACMP_STAT_OUT_POS 1U +#define ACMP_STAT_OUT_MSK BIT(ACMP_STAT_OUT_POS) + +#define ACMP_STAT_ACT_POS 0U +#define ACMP_STAT_ACT_MSK BIT(ACMP_STAT_ACT_POS) + +/****************** Bit definition for ACMP_IES register ************************/ + +#define ACMP_IES_WARMUP_POS 1U +#define ACMP_IES_WARMUP_MSK BIT(ACMP_IES_WARMUP_POS) + +#define ACMP_IES_EDGE_POS 0U +#define ACMP_IES_EDGE_MSK BIT(ACMP_IES_EDGE_POS) + +/****************** Bit definition for ACMP_IEV register ************************/ + +#define ACMP_IEV_WARMUP_POS 1U +#define ACMP_IEV_WARMUP_MSK BIT(ACMP_IEV_WARMUP_POS) + +#define ACMP_IEV_EDGE_POS 0U +#define ACMP_IEV_EDGE_MSK BIT(ACMP_IEV_EDGE_POS) + +/****************** Bit definition for ACMP_IEC register ************************/ + +#define ACMP_IEC_WARMUP_POS 1U +#define ACMP_IEC_WARMUP_MSK BIT(ACMP_IEC_WARMUP_POS) + +#define ACMP_IEC_EDGE_POS 0U +#define ACMP_IEC_EDGE_MSK BIT(ACMP_IEC_EDGE_POS) + +/****************** Bit definition for ACMP_RIF register ************************/ + +#define ACMP_RIF_WARMUP_POS 1U +#define ACMP_RIF_WARMUP_MSK BIT(ACMP_RIF_WARMUP_POS) + +#define ACMP_RIF_EDGE_POS 0U +#define ACMP_RIF_EDGE_MSK BIT(ACMP_RIF_EDGE_POS) + +/****************** Bit definition for ACMP_IFM register ************************/ + +#define ACMP_IFM_WARMUP_POS 1U +#define ACMP_IFM_WARMUP_MSK BIT(ACMP_IFM_WARMUP_POS) + +#define ACMP_IFM_EDGE_POS 0U +#define ACMP_IFM_EDGE_MSK BIT(ACMP_IFM_EDGE_POS) + +/****************** Bit definition for ACMP_IFC register ************************/ + +#define ACMP_IFC_WARMUP_POS 1U +#define ACMP_IFC_WARMUP_MSK BIT(ACMP_IFC_WARMUP_POS) + +#define ACMP_IFC_EDGE_POS 0U +#define ACMP_IFC_EDGE_MSK BIT(ACMP_IFC_EDGE_POS) + +/****************** Bit definition for ACMP_PORT register ************************/ + +#define ACMP_PORT_PEN_POS 0U +#define ACMP_PORT_PEN_MSK BIT(ACMP_PORT_PEN_POS) + +typedef struct +{ + __IO uint32_t CON; + __IO uint32_t INPUTSEL; + __I uint32_t STAT; + __O uint32_t IES; + __O uint32_t IEC; + __I uint32_t IEV; + __I uint32_t RIF; + __O uint32_t IFM; + __O uint32_t IFC; + __IO uint32_t PORT; +} ACMP_TypeDef; + +/****************** Bit definition for CALC_SQRTSR register ************************/ + +#define CALC_SQRTSR_BUSY_POS 0U +#define CALC_SQRTSR_BUSY_MSK BIT(CALC_SQRTSR_BUSY_POS) + +/****************** Bit definition for CALC_RDCND register ************************/ + +#define CALC_RDCND_RADICAND_POSS 0U +#define CALC_RDCND_RADICAND_POSE 31U +#define CALC_RDCND_RADICAND_MSK BITS(CALC_RDCND_RADICAND_POSS,CALC_RDCND_RADICAND_POSE) + +/****************** Bit definition for CALC_SQRTRES register ************************/ + +#define CALC_SQRTRES_RESULT_POSS 0U +#define CALC_SQRTRES_RESULT_POSE 15U +#define CALC_SQRTRES_RESULT_MSK BITS(CALC_SQRTRES_RESULT_POSS,CALC_SQRTRES_RESULT_POSE) + +/****************** Bit definition for CALC_DIVDR register ************************/ + +#define CALC_DIVDR_DIVD_POSS 0U +#define CALC_DIVDR_DIVD_POSE 31U +#define CALC_DIVDR_DIVD_MSK BITS(CALC_DIVDR_DIVD_POSS,CALC_DIVDR_DIVD_POSE) + +/****************** Bit definition for CALC_DIVSR register ************************/ + +#define CALC_DIVSR_DIVS_POSS 0U +#define CALC_DIVSR_DIVS_POSE 31U +#define CALC_DIVSR_DIVS_MSK BITS(CALC_DIVSR_DIVS_POSS,CALC_DIVSR_DIVS_POSE) + +/****************** Bit definition for CALC_DIVQR register ************************/ + +#define CALC_DIVQR_DIVQ_POSS 0U +#define CALC_DIVQR_DIVQ_POSE 31U +#define CALC_DIVQR_DIVQ_MSK BITS(CALC_DIVQR_DIVQ_POSS,CALC_DIVQR_DIVQ_POSE) + +/****************** Bit definition for CALC_DIVRR register ************************/ + +#define CALC_DIVRR_DIVS_POSS 0U +#define CALC_DIVRR_DIVS_POSE 31U +#define CALC_DIVRR_DIVS_MSK BITS(CALC_DIVRR_DIVS_POSS,CALC_DIVRR_DIVS_POSE) + +/****************** Bit definition for CALC_DIVCSR register ************************/ + +#define CALC_DIVCSR_TRM_POS 9U +#define CALC_DIVCSR_TRM_MSK BIT(CALC_DIVCSR_TRM_POS) + +#define CALC_DIVCSR_SIGN_POS 8U +#define CALC_DIVCSR_SIGN_MSK BIT(CALC_DIVCSR_SIGN_POS) + +#define CALC_DIVCSR_DZ_POS 1U +#define CALC_DIVCSR_DZ_MSK BIT(CALC_DIVCSR_DZ_POS) + +#define CALC_DIVCSR_BUSY_POS 0U +#define CALC_DIVCSR_BUSY_MSK BIT(CALC_DIVCSR_BUSY_POS) + +typedef struct +{ + __I uint32_t SQRTSR; + __IO uint32_t RDCND; + __I uint32_t SQRTRES; + uint32_t RESERVED0[5] ; + __IO uint32_t DIVDR; + __IO uint32_t DIVSR; + __I uint32_t DIVQR; + __I uint32_t DIVRR; + __IO uint32_t DIVCSR; +} CALC_TypeDef; + +/****************** Bit definition for TRNG_CR register ************************/ + +#define TRNG_CR_ADJC_POSS 16U +#define TRNG_CR_ADJC_POSE 17U +#define TRNG_CR_ADJC_MSK BITS(TRNG_CR_ADJC_POSS,TRNG_CR_ADJC_POSE) + +#define TRNG_CR_SDSEL_POSS 10U +#define TRNG_CR_SDSEL_POSE 11U +#define TRNG_CR_SDSEL_MSK BITS(TRNG_CR_SDSEL_POSS,TRNG_CR_SDSEL_POSE) + +#define TRNG_CR_DSEL_POSS 8U +#define TRNG_CR_DSEL_POSE 9U +#define TRNG_CR_DSEL_MSK BITS(TRNG_CR_DSEL_POSS,TRNG_CR_DSEL_POSE) + +#define TRNG_CR_POSTEN_POS 3U +#define TRNG_CR_POSTEN_MSK BIT(TRNG_CR_POSTEN_POS) + +#define TRNG_CR_TRNGSEL_POS 2U +#define TRNG_CR_TRNGSEL_MSK BIT(TRNG_CR_TRNGSEL_POS) + +#define TRNG_CR_ADJM_POS 1U +#define TRNG_CR_ADJM_MSK BIT(TRNG_CR_ADJM_POS) + +#define TRNG_CR_TRNGEN_POS 0U +#define TRNG_CR_TRNGEN_MSK BIT(TRNG_CR_TRNGEN_POS) + +/****************** Bit definition for TRNG_SR register ************************/ + +#define TRNG_SR_OVER_POS 3U +#define TRNG_SR_OVER_MSK BIT(TRNG_SR_OVER_POS) + +#define TRNG_SR_SERR_POS 2U +#define TRNG_SR_SERR_MSK BIT(TRNG_SR_SERR_POS) + +#define TRNG_SR_DAVLD_POS 1U +#define TRNG_SR_DAVLD_MSK BIT(TRNG_SR_DAVLD_POS) + +#define TRNG_SR_START_POS 0U +#define TRNG_SR_START_MSK BIT(TRNG_SR_START_POS) + +/****************** Bit definition for TRNG_DR register ************************/ + +#define TRNG_DR_DATA_POSS 0U +#define TRNG_DR_DATA_POSE 31U +#define TRNG_DR_DATA_MSK BITS(TRNG_DR_DATA_POSS,TRNG_DR_DATA_POSE) + +/****************** Bit definition for TRNG_SEED register ************************/ + +#define TRNG_SEED_SEED_POSS 0U +#define TRNG_SEED_SEED_POSE 31U +#define TRNG_SEED_SEED_MSK BITS(TRNG_SEED_SEED_POSS,TRNG_SEED_SEED_POSE) + +/****************** Bit definition for TRNG_CFGR register ************************/ + +#define TRNG_CFGR_TOPLMT_POSS 16U +#define TRNG_CFGR_TOPLMT_POSE 24U +#define TRNG_CFGR_TOPLMT_MSK BITS(TRNG_CFGR_TOPLMT_POSS,TRNG_CFGR_TOPLMT_POSE) + +#define TRNG_CFGR_CKDIV_POSS 8U +#define TRNG_CFGR_CKDIV_POSE 11U +#define TRNG_CFGR_CKDIV_MSK BITS(TRNG_CFGR_CKDIV_POSS,TRNG_CFGR_CKDIV_POSE) + +#define TRNG_CFGR_TSTART_POSS 0U +#define TRNG_CFGR_TSTART_POSE 2U +#define TRNG_CFGR_TSTART_MSK BITS(TRNG_CFGR_TSTART_POSS,TRNG_CFGR_TSTART_POSE) + +/****************** Bit definition for TRNG_IER register ************************/ + +#define TRNG_IER_SERR_POS 2U +#define TRNG_IER_SERR_MSK BIT(TRNG_IER_SERR_POS) + +#define TRNG_IER_DAVLD_POS 1U +#define TRNG_IER_DAVLD_MSK BIT(TRNG_IER_DAVLD_POS) + +#define TRNG_IER_START_POS 0U +#define TRNG_IER_START_MSK BIT(TRNG_IER_START_POS) + +/****************** Bit definition for TRNG_IFR register ************************/ + +#define TRNG_IFR_SERR_POS 2U +#define TRNG_IFR_SERR_MSK BIT(TRNG_IFR_SERR_POS) + +#define TRNG_IFR_DAVLD_POS 1U +#define TRNG_IFR_DAVLD_MSK BIT(TRNG_IFR_DAVLD_POS) + +#define TRNG_IFR_START_POS 0U +#define TRNG_IFR_START_MSK BIT(TRNG_IFR_START_POS) + +/****************** Bit definition for TRNG_IFCR register ************************/ + +#define TRNG_IFCR_SERRC_POS 2U +#define TRNG_IFCR_SERRC_MSK BIT(TRNG_IFCR_SERRC_POS) + +#define TRNG_IFCR_DAVLDC_POS 1U +#define TRNG_IFCR_DAVLDC_MSK BIT(TRNG_IFCR_DAVLDC_POS) + +#define TRNG_IFCR_STARTC_POS 0U +#define TRNG_IFCR_STARTC_MSK BIT(TRNG_IFCR_STARTC_POS) + +/****************** Bit definition for TRNG_ISR register ************************/ + +#define TRNG_ISR_SERR_POS 2U +#define TRNG_ISR_SERR_MSK BIT(TRNG_ISR_SERR_POS) + +#define TRNG_ISR_DAVLD_POS 1U +#define TRNG_ISR_DAVLD_MSK BIT(TRNG_ISR_DAVLD_POS) + +#define TRNG_ISR_START_POS 0U +#define TRNG_ISR_START_MSK BIT(TRNG_ISR_START_POS) + +typedef struct +{ + __IO uint32_t CR; + __I uint32_t SR; + __I uint32_t DR; + __IO uint32_t SEED; + __IO uint32_t CFGR; + __IO uint32_t IER; + __I uint32_t IFR; + __O uint32_t IFCR; + __I uint32_t ISR; +} TRNG_TypeDef; + +/****************** Bit definition for TSENSE_WPR register ************************/ + +#define TSENSE_WPR_WP_POS 0U +#define TSENSE_WPR_WP_MSK BIT(TSENSE_WPR_WP_POS) + +/****************** Bit definition for TSENSE_CR register ************************/ + +#define TSENSE_CR_TSU_POSS 12U +#define TSENSE_CR_TSU_POSE 14U +#define TSENSE_CR_TSU_MSK BITS(TSENSE_CR_TSU_POSS,TSENSE_CR_TSU_POSE) + +#define TSENSE_CR_TOM_POSS 8U +#define TSENSE_CR_TOM_POSE 10U +#define TSENSE_CR_TOM_MSK BITS(TSENSE_CR_TOM_POSS,TSENSE_CR_TOM_POSE) + +#define TSENSE_CR_CTN_POS 4U +#define TSENSE_CR_CTN_MSK BIT(TSENSE_CR_CTN_POS) + +#define TSENSE_CR_RST_POS 3U +#define TSENSE_CR_RST_MSK BIT(TSENSE_CR_RST_POS) + +#define TSENSE_CR_ENS_POS 2U +#define TSENSE_CR_ENS_MSK BIT(TSENSE_CR_ENS_POS) + +#define TSENSE_CR_REQEN_POS 1U +#define TSENSE_CR_REQEN_MSK BIT(TSENSE_CR_REQEN_POS) + +#define TSENSE_CR_EN_POS 0U +#define TSENSE_CR_EN_MSK BIT(TSENSE_CR_EN_POS) + +/****************** Bit definition for TSENSE_DR register ************************/ + +#define TSENSE_DR_ERR_POS 31U +#define TSENSE_DR_ERR_MSK BIT(TSENSE_DR_ERR_POS) + +#define TSENSE_DR_DATA_POSS 0U +#define TSENSE_DR_DATA_POSE 15U +#define TSENSE_DR_DATA_MSK BITS(TSENSE_DR_DATA_POSS,TSENSE_DR_DATA_POSE) + +/****************** Bit definition for TSENSE_PSR register ************************/ + +#define TSENSE_PSR_PRS_POSS 0U +#define TSENSE_PSR_PRS_POSE 7U +#define TSENSE_PSR_PRS_MSK BITS(TSENSE_PSR_PRS_POSS,TSENSE_PSR_PRS_POSE) + +/****************** Bit definition for TSENSE_IE register ************************/ + +#define TSENSE_IE_TSENSE_POS 0U +#define TSENSE_IE_TSENSE_MSK BIT(TSENSE_IE_TSENSE_POS) + +/****************** Bit definition for TSENSE_IF register ************************/ + +#define TSENSE_IF_TSENSE_POS 0U +#define TSENSE_IF_TSENSE_MSK BIT(TSENSE_IF_TSENSE_POS) + +/****************** Bit definition for TSENSE_IFCR register ************************/ + +#define TSENSE_IFCR_TSENSE_POS 0U +#define TSENSE_IFCR_TSENSE_MSK BIT(TSENSE_IFCR_TSENSE_POS) + +/****************** Bit definition for TSENSE_LTGR register ************************/ + +#define TSENSE_LTGR_LTG_POSS 0U +#define TSENSE_LTGR_LTG_POSE 20U +#define TSENSE_LTGR_LTG_MSK BITS(TSENSE_LTGR_LTG_POSS,TSENSE_LTGR_LTG_POSE) + +/****************** Bit definition for TSENSE_HTGR register ************************/ + +#define TSENSE_HTGR_HTG_POSS 0U +#define TSENSE_HTGR_HTG_POSE 20U +#define TSENSE_HTGR_HTG_MSK BITS(TSENSE_HTGR_HTG_POSS,TSENSE_HTGR_HTG_POSE) + +/****************** Bit definition for TSENSE_TBDR register ************************/ + +#define TSENSE_TBDR_TBD_POSS 0U +#define TSENSE_TBDR_TBD_POSE 15U +#define TSENSE_TBDR_TBD_MSK BITS(TSENSE_TBDR_TBD_POSS,TSENSE_TBDR_TBD_POSE) + +/****************** Bit definition for TSENSE_TCALBDR register ************************/ + +#define TSENSE_TCALBDR_TCAL_POSS 0U +#define TSENSE_TCALBDR_TCAL_POSE 16U +#define TSENSE_TCALBDR_TCAL_MSK BITS(TSENSE_TCALBDR_TCAL_POSS,TSENSE_TCALBDR_TCAL_POSE) + +/****************** Bit definition for TSENSE_SR register ************************/ + +#define TSENSE_SR_TSOUT_POS 31U +#define TSENSE_SR_TSOUT_MSK BIT(TSENSE_SR_TSOUT_POS) + +#define TSENSE_SR_NVLD_POS 25U +#define TSENSE_SR_NVLD_MSK BIT(TSENSE_SR_NVLD_POS) + +#define TSENSE_SR_TCAL_POSS 0U +#define TSENSE_SR_TCAL_POSE 24U +#define TSENSE_SR_TCAL_MSK BITS(TSENSE_SR_TCAL_POSS,TSENSE_SR_TCAL_POSE) + +typedef struct +{ + __IO uint32_t WPR; + __IO uint32_t CR; + __I uint32_t DR; + __IO uint32_t PSR; + __IO uint32_t IE; + __I uint32_t IF; + __IO uint32_t IFCR; + __IO uint32_t LTGR; + __IO uint32_t HTGR; + __IO uint32_t TBDR; + __IO uint32_t TCALBDR; + __I uint32_t SR; +} TSENSE_TypeDef; + +/****************** Bit definition for IWDT_LOAD register ************************/ + +#define IWDT_LOAD_LOAD_POSS 0U +#define IWDT_LOAD_LOAD_POSE 31U +#define IWDT_LOAD_LOAD_MSK BITS(IWDT_LOAD_LOAD_POSS,IWDT_LOAD_LOAD_POSE) + +/****************** Bit definition for IWDT_VALUE register ************************/ + +#define IWDT_VALUE_VALUE_POSS 0U +#define IWDT_VALUE_VALUE_POSE 31U +#define IWDT_VALUE_VALUE_MSK BITS(IWDT_VALUE_VALUE_POSS,IWDT_VALUE_VALUE_POSE) + +/****************** Bit definition for IWDT_CON register ************************/ + +#define IWDT_CON_CLKS_POS 3U +#define IWDT_CON_CLKS_MSK BIT(IWDT_CON_CLKS_POS) + +#define IWDT_CON_RSTEN_POS 2U +#define IWDT_CON_RSTEN_MSK BIT(IWDT_CON_RSTEN_POS) + +#define IWDT_CON_IE_POS 1U +#define IWDT_CON_IE_MSK BIT(IWDT_CON_IE_POS) + +#define IWDT_CON_EN_POS 0U +#define IWDT_CON_EN_MSK BIT(IWDT_CON_EN_POS) + +/****************** Bit definition for IWDT_INTCLR register ************************/ + +#define IWDT_INTCLR_INTCLR_POSS 0U +#define IWDT_INTCLR_INTCLR_POSE 31U +#define IWDT_INTCLR_INTCLR_MSK BITS(IWDT_INTCLR_INTCLR_POSS,IWDT_INTCLR_INTCLR_POSE) + +/****************** Bit definition for IWDT_RIS register ************************/ + +#define IWDT_RIS_WDTIF_POS 0U +#define IWDT_RIS_WDTIF_MSK BIT(IWDT_RIS_WDTIF_POS) + +/****************** Bit definition for IWDT_LOCK register ************************/ + +#define IWDT_LOCK_LOCK_POS 0U +#define IWDT_LOCK_LOCK_MSK BIT(IWDT_LOCK_LOCK_POS) + +typedef struct +{ + __O uint32_t LOAD; + __I uint32_t VALUE; + __IO uint32_t CON; + __O uint32_t INTCLR; + __I uint32_t RIS; + uint32_t RESERVED0[59] ; + __IO uint32_t LOCK; +} IWDT_TypeDef; + +/****************** Bit definition for WWDT_LOAD register ************************/ + +#define WWDT_LOAD_LOAD_POSS 0U +#define WWDT_LOAD_LOAD_POSE 31U +#define WWDT_LOAD_LOAD_MSK BITS(WWDT_LOAD_LOAD_POSS,WWDT_LOAD_LOAD_POSE) + +/****************** Bit definition for WWDT_VALUE register ************************/ + +#define WWDT_VALUE_VALUE_POSS 0U +#define WWDT_VALUE_VALUE_POSE 31U +#define WWDT_VALUE_VALUE_MSK BITS(WWDT_VALUE_VALUE_POSS,WWDT_VALUE_VALUE_POSE) + +/****************** Bit definition for WWDT_CON register ************************/ + +#define WWDT_CON_WWDTWIN_POSS 4U +#define WWDT_CON_WWDTWIN_POSE 5U +#define WWDT_CON_WWDTWIN_MSK BITS(WWDT_CON_WWDTWIN_POSS,WWDT_CON_WWDTWIN_POSE) + +#define WWDT_CON_CLKS_POS 3U +#define WWDT_CON_CLKS_MSK BIT(WWDT_CON_CLKS_POS) + +#define WWDT_CON_RSTEN_POS 2U +#define WWDT_CON_RSTEN_MSK BIT(WWDT_CON_RSTEN_POS) + +#define WWDT_CON_IE_POS 1U +#define WWDT_CON_IE_MSK BIT(WWDT_CON_IE_POS) + +#define WWDT_CON_EN_POS 0U +#define WWDT_CON_EN_MSK BIT(WWDT_CON_EN_POS) + +/****************** Bit definition for WWDT_INTCLR register ************************/ + +#define WWDT_INTCLR_INTCLR_POSS 0U +#define WWDT_INTCLR_INTCLR_POSE 31U +#define WWDT_INTCLR_INTCLR_MSK BITS(WWDT_INTCLR_INTCLR_POSS,WWDT_INTCLR_INTCLR_POSE) + +/****************** Bit definition for WWDT_RIS register ************************/ + +#define WWDT_RIS_WWDTIF_POS 0U +#define WWDT_RIS_WWDTIF_MSK BIT(WWDT_RIS_WWDTIF_POS) + +/****************** Bit definition for WWDT_LOCK register ************************/ + +#define WWDT_LOCK_LOCK_POS 0U +#define WWDT_LOCK_LOCK_MSK BIT(WWDT_LOCK_LOCK_POS) + +typedef struct +{ + __O uint32_t LOAD; + __I uint32_t VALUE; + __IO uint32_t CON; + __O uint32_t INTCLR; + __I uint32_t RIS; + uint32_t RESERVED0[59]; + __IO uint32_t LOCK; +} WWDT_TypeDef; + +/****************** Bit definition for QSPI_CR register ************************/ + +#define QSPI_CR_IDLES_POS 31U +#define QSPI_CR_IDLES_MSK BIT(QSPI_CR_IDLES_POS) +#define QSPI_CR_IDLES QSPI_CR_IDLES_MSK + + +#define QSPI_CR_DTRM_POS 24U +#define QSPI_CR_DTRM_MSK BIT(QSPI_CR_DTRM_POS) + +#define QSPI_CR_ADEN_POS 23U +#define QSPI_CR_ADEN_MSK BIT(QSPI_CR_ADEN_POS) + +#define QSPI_CR_BAUD_POSS 19U +#define QSPI_CR_BAUD_POSE 22U +#define QSPI_CR_BAUD_MSK BITS(QSPI_CR_BAUD_POSS,QSPI_CR_BAUD_POSE) + +#define QSPI_CR_XIPIM_POS 18U +#define QSPI_CR_XIPIM_MSK BIT(QSPI_CR_XIPIM_POS) + +#define QSPI_CR_XIPNX_POS 17U +#define QSPI_CR_XIPNX_MSK BIT(QSPI_CR_XIPNX_POS) + +#define QSPI_CR_AREN_POS 16U +#define QSPI_CR_AREN_MSK BIT(QSPI_CR_AREN_POS) + +#define QSPI_CR_DMAEN_POS 15U +#define QSPI_CR_DMAEN_MSK BIT(QSPI_CR_DMAEN_POS) + +#define QSPI_CR_SWPP_POS 14U +#define QSPI_CR_SWPP_MSK BIT(QSPI_CR_SWPP_POS) + +#define QSPI_CR_PSL_POSS 10U +#define QSPI_CR_PSL_POSE 13U +#define QSPI_CR_PSL_MSK BITS(QSPI_CR_PSL_POSS,QSPI_CR_PSL_POSE) + +#define QSPI_CR_PSD_POS 9U +#define QSPI_CR_PSD_MSK BIT(QSPI_CR_PSD_POS) + +#define QSPI_CR_LIMEN_POS 8U +#define QSPI_CR_LIMEN_MSK BIT(QSPI_CR_LIMEN_POS) + +#define QSPI_CR_DACEN_POS 7U +#define QSPI_CR_DACEN_MSK BIT(QSPI_CR_DACEN_POS) + +#define QSPI_CR_CPHA_POS 2U +#define QSPI_CR_CPHA_MSK BIT(QSPI_CR_CPHA_POS) +#define QSPI_CR_CPHA QSPI_CR_CPHA_MSK + +#define QSPI_CR_CPOL_POS 1U +#define QSPI_CR_CPOL_MSK BIT(QSPI_CR_CPOL_POS) +#define QSPI_CR_CPOL QSPI_CR_CPOL_MSK + +#define QSPI_CR_EN_POS 0U +#define QSPI_CR_EN_MSK BIT(QSPI_CR_EN_POS) + +/****************** Bit definition for QSPI_DRIR register ************************/ + +#define QSPI_DRIR_DCYC_POSS 24U +#define QSPI_DRIR_DCYC_POSE 28U +#define QSPI_DRIR_DCYC_MSK BITS(QSPI_DRIR_DCYC_POSS,QSPI_DRIR_DCYC_POSE) + +#define QSPI_DRIR_MBEN_POS 20U +#define QSPI_DRIR_MBEN_MSK BIT(QSPI_DRIR_MBEN_POS) + +#define QSPI_DRIR_DMODE_POSS 16U +#define QSPI_DRIR_DMODE_POSE 17U +#define QSPI_DRIR_DMODE_MSK BITS(QSPI_DRIR_DMODE_POSS,QSPI_DRIR_DMODE_POSE) + +#define QSPI_DRIR_ADMODE_POSS 12U +#define QSPI_DRIR_ADMODE_POSE 13U +#define QSPI_DRIR_ADMODE_MSK BITS(QSPI_DRIR_ADMODE_POSS,QSPI_DRIR_ADMODE_POSE) + +#define QSPI_DRIR_DDRM_POS 10U +#define QSPI_DRIR_DDRM_MSK BIT(QSPI_DRIR_DDRM_POS) + +#define QSPI_DRIR_IMODE_POSS 8U +#define QSPI_DRIR_IMODE_POSE 9U +#define QSPI_DRIR_IMODE_MSK BITS(QSPI_DRIR_IMODE_POSS,QSPI_DRIR_IMODE_POSE) + +#define QSPI_DRIR_RINST_POSS 0U +#define QSPI_DRIR_RINST_POSE 7U +#define QSPI_DRIR_RINST_MSK BITS(QSPI_DRIR_RINST_POSS,QSPI_DRIR_RINST_POSE) + +/****************** Bit definition for QSPI_DWIR register ************************/ + +#define QSPI_DWIR_DCYC_POSS 24U +#define QSPI_DWIR_DCYC_POSE 28U +#define QSPI_DWIR_DCYC_MSK BITS(QSPI_DWIR_DCYC_POSS,QSPI_DWIR_DCYC_POSE) + +#define QSPI_DWIR_DMODE_POSS 16U +#define QSPI_DWIR_DMODE_POSE 17U +#define QSPI_DWIR_DMODE_MSK BITS(QSPI_DWIR_DMODE_POSS,QSPI_DWIR_DMODE_POSE) + +#define QSPI_DWIR_ADMODE_POSS 12U +#define QSPI_DWIR_ADMODE_POSE 13U +#define QSPI_DWIR_ADMODE_MSK BITS(QSPI_DWIR_ADMODE_POSS,QSPI_DWIR_ADMODE_POSE) + +#define QSPI_DWIR_WELD_POS 8U +#define QSPI_DWIR_WELD_MSK BIT(QSPI_DWIR_WELD_POS) + +#define QSPI_DWIR_WINST_POSS 0U +#define QSPI_DWIR_WINST_POSE 7U +#define QSPI_DWIR_WINST_MSK BITS(QSPI_DWIR_WINST_POSS,QSPI_DWIR_WINST_POSE) + +/****************** Bit definition for QSPI_DDLR register ************************/ + +#define QSPI_DDLR_CSDA_POSS 24U +#define QSPI_DDLR_CSDA_POSE 31U +#define QSPI_DDLR_CSDA_MSK BITS(QSPI_DDLR_CSDA_POSS,QSPI_DDLR_CSDA_POSE) + +#define QSPI_DDLR_CSDADS_POSS 16U +#define QSPI_DDLR_CSDADS_POSE 23U +#define QSPI_DDLR_CSDADS_MSK BITS(QSPI_DDLR_CSDADS_POSS,QSPI_DDLR_CSDADS_POSE) + +#define QSPI_DDLR_CSEOT_POSS 8U +#define QSPI_DDLR_CSEOT_POSE 15U +#define QSPI_DDLR_CSEOT_MSK BITS(QSPI_DDLR_CSEOT_POSS,QSPI_DDLR_CSEOT_POSE) + +#define QSPI_DDLR_CSSOT_POSS 0U +#define QSPI_DDLR_CSSOT_POSE 7U +#define QSPI_DDLR_CSSOT_MSK BITS(QSPI_DDLR_CSSOT_POSS,QSPI_DDLR_CSSOT_POSE) + +/****************** Bit definition for QSPI_RDCR register ************************/ + +#define QSPI_RDCR_DLYT_POSS 16U +#define QSPI_RDCR_DLYT_POSE 19U +#define QSPI_RDCR_DLYT_MSK BITS(QSPI_RDCR_DLYT_POSS,QSPI_RDCR_DLYT_POSE) + +#define QSPI_RDCR_SMES_POS 5U +#define QSPI_RDCR_SMES_MSK BIT(QSPI_RDCR_SMES_POS) + +#define QSPI_RDCR_DLYR_POSS 1U +#define QSPI_RDCR_DLYR_POSE 4U +#define QSPI_RDCR_DLYR_MSK BITS(QSPI_RDCR_DLYR_POSS,QSPI_RDCR_DLYR_POSE) + +#define QSPI_RDCR_BYLPC_POS 0U +#define QSPI_RDCR_BYLPC_MSK BIT(QSPI_RDCR_BYLPC_POS) + +/****************** Bit definition for QSPI_DSCR register ************************/ + +#define QSPI_DSCR_CS3SIZE_POSS 27U +#define QSPI_DSCR_CS3SIZE_POSE 28U +#define QSPI_DSCR_CS3SIZE_MSK BITS(QSPI_DSCR_CS3SIZE_POSS,QSPI_DSCR_CS3SIZE_POSE) + +#define QSPI_DSCR_CS2SIZE_POSS 25U +#define QSPI_DSCR_CS2SIZE_POSE 26U +#define QSPI_DSCR_CS2SIZE_MSK BITS(QSPI_DSCR_CS2SIZE_POSS,QSPI_DSCR_CS2SIZE_POSE) + +#define QSPI_DSCR_CS1SIZE_POSS 23U +#define QSPI_DSCR_CS1SIZE_POSE 24U +#define QSPI_DSCR_CS1SIZE_MSK BITS(QSPI_DSCR_CS1SIZE_POSS,QSPI_DSCR_CS1SIZE_POSE) + +#define QSPI_DSCR_CS0SIZE_POSS 21U +#define QSPI_DSCR_CS0SIZE_POSE 22U +#define QSPI_DSCR_CS0SIZE_MSK BITS(QSPI_DSCR_CS0SIZE_POSS,QSPI_DSCR_CS0SIZE_POSE) + +#define QSPI_DSCR_BKSIZE_POSS 16U +#define QSPI_DSCR_BKSIZE_POSE 20U +#define QSPI_DSCR_BKSIZE_MSK BITS(QSPI_DSCR_BKSIZE_POSS,QSPI_DSCR_BKSIZE_POSE) + +#define QSPI_DSCR_PASIZE_POSS 4U +#define QSPI_DSCR_PASIZE_POSE 15U +#define QSPI_DSCR_PASIZE_MSK BITS(QSPI_DSCR_PASIZE_POSS,QSPI_DSCR_PASIZE_POSE) + +#define QSPI_DSCR_ADSIZE_POSS 0U +#define QSPI_DSCR_ADSIZE_POSE 3U +#define QSPI_DSCR_ADSIZE_MSK BITS(QSPI_DSCR_ADSIZE_POSS,QSPI_DSCR_ADSIZE_POSE) + +/****************** Bit definition for QSPI_SPR register ************************/ + +#define QSPI_SPR_SRAMPS_POSS 0U +#define QSPI_SPR_SRAMPS_POSE 7U +#define QSPI_SPR_SRAMPS_MSK BITS(QSPI_SPR_SRAMPS_POSS,QSPI_SPR_SRAMPS_POSE) + +/****************** Bit definition for QSPI_IATR register ************************/ + +#define QSPI_IATR_INDTAD_POSS 0U +#define QSPI_IATR_INDTAD_POSE 31U +#define QSPI_IATR_INDTAD_MSK BITS(QSPI_IATR_INDTAD_POSS,QSPI_IATR_INDTAD_POSE) + +/****************** Bit definition for QSPI_DMACR register ************************/ + +#define QSPI_DMACR_BNUMB_POSS 8U +#define QSPI_DMACR_BNUMB_POSE 11U +#define QSPI_DMACR_BNUMB_MSK BITS(QSPI_DMACR_BNUMB_POSS,QSPI_DMACR_BNUMB_POSE) + +#define QSPI_DMACR_SNUMB_POSS 0U +#define QSPI_DMACR_SNUMB_POSE 3U +#define QSPI_DMACR_SNUMB_MSK BITS(QSPI_DMACR_SNUMB_POSS,QSPI_DMACR_SNUMB_POSE) + +/****************** Bit definition for QSPI_RAR register ************************/ + +#define QSPI_RAR_READDR_POSS 0U +#define QSPI_RAR_READDR_POSE 31U +#define QSPI_RAR_READDR_MSK BITS(QSPI_RAR_READDR_POSS,QSPI_RAR_READDR_POSE) + +/****************** Bit definition for QSPI_MBR register ************************/ + +#define QSPI_MBR_MODEB_POSS 0U +#define QSPI_MBR_MODEB_POSE 7U +#define QSPI_MBR_MODEB_MSK BITS(QSPI_MBR_MODEB_POSS,QSPI_MBR_MODEB_POSE) + +/****************** Bit definition for QSPI_SFLR register ************************/ + +#define QSPI_SFLR_INDWSFL_POSS 16U +#define QSPI_SFLR_INDWSFL_POSE 21U +#define QSPI_SFLR_INDWSFL_MSK BITS(QSPI_SFLR_INDWSFL_POSS,QSPI_SFLR_INDWSFL_POSE) + +#define QSPI_SFLR_INDRSFL_POSS 0U +#define QSPI_SFLR_INDRSFL_POSE 5U +#define QSPI_SFLR_INDRSFL_MSK BITS(QSPI_SFLR_INDRSFL_POSS,QSPI_SFLR_INDRSFL_POSE) + +/****************** Bit definition for QSPI_TXHR register ************************/ + +#define QSPI_TXHR_TXTH_POSS 0U +#define QSPI_TXHR_TXTH_POSE 4U +#define QSPI_TXHR_TXTH_MSK BITS(QSPI_TXHR_TXTH_POSS,QSPI_TXHR_TXTH_POSE) + +/****************** Bit definition for QSPI_RXHR register ************************/ + +#define QSPI_RXHR_RXTH_POSS 0U +#define QSPI_RXHR_RXTH_POSE 4U +#define QSPI_RXHR_RXTH_MSK BITS(QSPI_RXHR_RXTH_POSS,QSPI_RXHR_RXTH_POSE) + +/****************** Bit definition for QSPI_WCR register ************************/ + +#define QSPI_WCR_PREPD_POSS 24U +#define QSPI_WCR_PREPD_POSE 31U +#define QSPI_WCR_PREPD_MSK BITS(QSPI_WCR_PREPD_POSS,QSPI_WCR_PREPD_POSE) + +#define QSPI_WCR_PCNT_POSS 16U +#define QSPI_WCR_PCNT_POSE 23U +#define QSPI_WCR_PCNT_MSK BITS(QSPI_WCR_PCNT_POSS,QSPI_WCR_PCNT_POSE) + +#define QSPI_WCR_PDIS_POS 14U +#define QSPI_WCR_PDIS_MSK BIT(QSPI_WCR_PDIS_POS) + +#define QSPI_WCR_PPLT_POS 13U +#define QSPI_WCR_PPLT_MSK BIT(QSPI_WCR_PPLT_POS) + +#define QSPI_WCR_PBIND_POSS 8U +#define QSPI_WCR_PBIND_POSE 10U +#define QSPI_WCR_PBIND_MSK BITS(QSPI_WCR_PBIND_POSS,QSPI_WCR_PBIND_POSE) + +#define QSPI_WCR_OPCODE_POSS 0U +#define QSPI_WCR_OPCODE_POSE 7U +#define QSPI_WCR_OPCODE_MSK BITS(QSPI_WCR_OPCODE_POSS,QSPI_WCR_OPCODE_POSE) + +/****************** Bit definition for QSPI_PER register ************************/ + +#define QSPI_PER_PCYCN_POSS 0U +#define QSPI_PER_PCYCN_POSE 31U +#define QSPI_PER_PCYCN_MSK BITS(QSPI_PER_PCYCN_POSS,QSPI_PER_PCYCN_POSE) + +/****************** Bit definition for QSPI_IFR register ************************/ + +#define QSPI_IFR_POLLF_POS 13U +#define QSPI_IFR_POLLF_MSK BIT(QSPI_IFR_POLLF_POS) +#define QSPI_IFR_POLLF QSPI_IFR_POLLF_MSK + +#define QSPI_IFR_INDRSFF_POS 12U +#define QSPI_IFR_INDRSFF_MSK BIT(QSPI_IFR_INDRSFF_POS) +#define QSPI_IFR_INDRSFF QSPI_IFR_INDRSFF_MSK + +#define QSPI_IFR_SRFFF_POS 11U +#define QSPI_IFR_SRFFF_MSK BIT(QSPI_IFR_SRFFF_POS) +#define QSPI_IFR_SRFFF QSPI_IFR_SRFFF_MSK + +#define QSPI_IFR_SRFNEF_POS 10U +#define QSPI_IFR_SRFNEF_MSK BIT(QSPI_IFR_SRFNEF_POS) +#define QSPI_IFR_SRFNEF QSPI_IFR_SRFNEF_MSK + +#define QSPI_IFR_STFFF_POS 9U +#define QSPI_IFR_STFFF_MSK BIT(QSPI_IFR_STFFF_POS) +#define QSPI_IFR_STFFF QSPI_IFR_STFFF_MSK + +#define QSPI_IFR_STFNFF_POS 8U +#define QSPI_IFR_STFNFF_MSK BIT(QSPI_IFR_STFNFF_POS) +#define QSPI_IFR_STFNFF QSPI_IFR_STFNFF_MSK + +#define QSPI_IFR_ROVF_POS 7U +#define QSPI_IFR_ROVF_MSK BIT(QSPI_IFR_ROVF_POS) +#define QSPI_IFR_ROVF QSPI_IFR_ROVF_MSK + +#define QSPI_IFR_INDTWF_POS 6U +#define QSPI_IFR_INDTWF_MSK BIT(QSPI_IFR_INDTWF_POS) +#define QSIP_IFR_INDTWF QSPI_IFR_INDTWF_MSK + +#define QSPI_IFR_AHBAEF_POS 5U +#define QSPI_IFR_AHBAEF_MSK BIT(QSPI_IFR_AHBAEF_POS) +#define QSPI_IFR_AHBAEF QSPI_IFR_AHBAEF_MSK + +#define QSPI_IFR_WPAF_POS 4U +#define QSPI_IFR_WPAF_MSK BIT(QSPI_IFR_WPAF_POS) +#define QSPI_IFR_WPAF QSPI_IFR_WPAF_MSK + +#define QSPI_IFR_INDRRF_POS 3U +#define QSPI_IFR_INDRRF_MSK BIT(QSPI_IFR_INDRRF_POS) +#define QSIP_IFR_INDRRF QSPI_IFR_INDRRF_MSK + +#define QSPI_IFR_INDCF_POS 2U +#define QSPI_IFR_INDCF_MSK BIT(QSPI_IFR_INDCF_POS) +#define QSPI_IFR_INDCF QSPI_IFR_INDCF_MSK + +#define QSPI_IFR_UDFF_POS 1U +#define QSPI_IFR_UDFF_MSK BIT(QSPI_IFR_UDFF_POS) +#define QSPI_IFR_UDFF QSPI_IFR_UDFF_MSK + +#define QSPI_IFR_MODFF_POS 0U +#define QSPI_IFR_MODFF_MSK BIT(QSPI_IFR_MODFF_POS) +#define QSPI_IFR_MODFF QSPI_IFR_MODFF_MSK + +/****************** Bit definition for QSPI_IMR register ************************/ + +#define QSPI_IMR_INTEN_POSS 0U +#define QSPI_IMR_INTEN_POSE 13U +#define QSPI_IMR_INTEN_MSK BITS(QSPI_IMR_INTEN_POSS,QSPI_IMR_INTEN_POSE) + +/****************** Bit definition for QSPI_WPLR register ************************/ + +#define QSPI_WPLR_LBLKNUM_POSS 0U +#define QSPI_WPLR_LBLKNUM_POSE 31U +#define QSPI_WPLR_LBLKNUM_MSK BITS(QSPI_WPLR_LBLKNUM_POSS,QSPI_WPLR_LBLKNUM_POSE) + +/****************** Bit definition for QSPI_WPHR register ************************/ + +#define QSPI_WPHR_HBLKNUM_POSS 0U +#define QSPI_WPHR_HBLKNUM_POSE 31U +#define QSPI_WPHR_HBLKNUM_MSK BITS(QSPI_WPHR_HBLKNUM_POSS,QSPI_WPHR_HBLKNUM_POSE) + +/****************** Bit definition for QSPI_WPCR register ************************/ + +#define QSPI_WPCR_WPEN_POS 1U +#define QSPI_WPCR_WPEN_MSK BIT(QSPI_WPCR_WPEN_POS) + +#define QSPI_WPCR_WPINV_POS 0U +#define QSPI_WPCR_WPINV_MSK BIT(QSPI_WPCR_WPINV_POS) + +/****************** Bit definition for QSPI_IRTR register ************************/ + +#define QSPI_IRTR_INDRNUM_POSS 6U +#define QSPI_IRTR_INDRNUM_POSE 7U +#define QSPI_IRTR_INDRNUM_MSK BITS(QSPI_IRTR_INDRNUM_POSS,QSPI_IRTR_INDRNUM_POSE) + +#define QSPI_IRTR_RDCS_POS 5U +#define QSPI_IRTR_RDCS_MSK BIT(QSPI_IRTR_RDCS_POS) + +#define QSPI_IRTR_RDQS_POS 4U +#define QSPI_IRTR_RDQS_MSK BIT(QSPI_IRTR_RDQS_POS) + +#define QSPI_IRTR_SRAMFS_POS 3U +#define QSPI_IRTR_SRAMFS_MSK BIT(QSPI_IRTR_SRAMFS_POS) + +#define QSPI_IRTR_RDPS_POS 2U +#define QSPI_IRTR_RDPS_MSK BIT(QSPI_IRTR_RDPS_POS) + +#define QSPI_IRTR_RDDIS_POS 1U +#define QSPI_IRTR_RDDIS_MSK BIT(QSPI_IRTR_RDDIS_POS) + +#define QSPI_IRTR_RDST_POS 0U +#define QSPI_IRTR_RDST_MSK BIT(QSPI_IRTR_RDST_POS) + +/****************** Bit definition for QSPI_IRTWR register ************************/ + +#define QSPI_IRTWR_VAULE_POSS 0U +#define QSPI_IRTWR_VAULE_POSE 31U +#define QSPI_IRTWR_VAULE_MSK BITS(QSPI_IRTWR_VAULE_POSS,QSPI_IRTWR_VAULE_POSE) + +/****************** Bit definition for QSPI_IRTSAR register ************************/ + +#define QSPI_IRTSAR_ADDR_POSS 0U +#define QSPI_IRTSAR_ADDR_POSE 31U +#define QSPI_IRTSAR_ADDR_MSK BITS(QSPI_IRTSAR_ADDR_POSS,QSPI_IRTSAR_ADDR_POSE) + +/****************** Bit definition for QSPI_IRTNR register ************************/ + +#define QSPI_IRTNR_NUM_POSS 0U +#define QSPI_IRTNR_NUM_POSE 31U +#define QSPI_IRTNR_NUM_MSK BITS(QSPI_IRTNR_NUM_POSS,QSPI_IRTNR_NUM_POSE) + +/****************** Bit definition for QSPI_IWTR register ************************/ + +#define QSPI_IWTR_INDWNUM_POSS 6U +#define QSPI_IWTR_INDWNUM_POSE 7U +#define QSPI_IWTR_INDWNUM_MSK BITS(QSPI_IWTR_INDWNUM_POSS,QSPI_IWTR_INDWNUM_POSE) + +#define QSPI_IWTR_WRCS_POS 5U +#define QSPI_IWTR_WRCS_MSK BIT(QSPI_IWTR_WRCS_POS) + +#define QSPI_IWTR_WRQS_POS 4U +#define QSPI_IWTR_WRQS_MSK BIT(QSPI_IWTR_WRQS_POS) + +#define QSPI_IWTR_WRPS_POS 2U +#define QSPI_IWTR_WRPS_MSK BIT(QSPI_IWTR_WRPS_POS) + +#define QSPI_IWTR_WRDIS_POS 1U +#define QSPI_IWTR_WRDIS_MSK BIT(QSPI_IWTR_WRDIS_POS) + +#define QSPI_IWTR_WRST_POS 0U +#define QSPI_IWTR_WRST_MSK BIT(QSPI_IWTR_WRST_POS) + +/****************** Bit definition for QSPI_IWTWR register ************************/ + +#define QSPI_IWTWR_VAULE_POSS 0U +#define QSPI_IWTWR_VAULE_POSE 31U +#define QSPI_IWTWR_VAULE_MSK BITS(QSPI_IWTWR_VAULE_POSS,QSPI_IWTWR_VAULE_POSE) + +/****************** Bit definition for QSPI_IWTSAR register ************************/ + +#define QSPI_IWTSAR_ADDR_POSS 0U +#define QSPI_IWTSAR_ADDR_POSE 31U +#define QSPI_IWTSAR_ADDR_MSK BITS(QSPI_IWTSAR_ADDR_POSS,QSPI_IWTSAR_ADDR_POSE) + +/****************** Bit definition for QSPI_IWTNR register ************************/ + +#define QSPI_IWTNR_NUM_POSS 0U +#define QSPI_IWTNR_NUM_POSE 31U +#define QSPI_IWTNR_NUM_MSK BITS(QSPI_IWTNR_NUM_POSS,QSPI_IWTNR_NUM_POSE) + +/****************** Bit definition for QSPI_ITARR register ************************/ + +#define QSPI_ITARR_RNGW_POSS 0U +#define QSPI_ITARR_RNGW_POSE 3U +#define QSPI_ITARR_RNGW_MSK BITS(QSPI_ITARR_RNGW_POSS,QSPI_ITARR_RNGW_POSE) + +/****************** Bit definition for QSPI_FCR register ************************/ + +#define QSPI_FCR_OPCODE_POSS 24U +#define QSPI_FCR_OPCODE_POSE 31U +#define QSPI_FCR_OPCODE_MSK BITS(QSPI_FCR_OPCODE_POSS,QSPI_FCR_OPCODE_POSE) + +#define QSPI_FCR_RDEN_POS 23U +#define QSPI_FCR_RDEN_MSK BIT(QSPI_FCR_RDEN_POS) + +#define QSPI_FCR_RDNUM_POSS 20U +#define QSPI_FCR_RDNUM_POSE 22U +#define QSPI_FCR_RDNUM_MSK BITS(QSPI_FCR_RDNUM_POSS,QSPI_FCR_RDNUM_POSE) + +#define QSPI_FCR_ADDREN_POS 19U +#define QSPI_FCR_ADDREN_MSK BIT(QSPI_FCR_ADDREN_POS) + +#define QSPI_FCR_MODBEN_POS 18U +#define QSPI_FCR_MODBEN_MSK BIT(QSPI_FCR_MODBEN_POS) + +#define QSPI_FCR_ADNUM_POSS 16U +#define QSPI_FCR_ADNUM_POSE 17U +#define QSPI_FCR_ADNUM_MSK BITS(QSPI_FCR_ADNUM_POSS,QSPI_FCR_ADNUM_POSE) + +#define QSPI_FCR_WREN_POS 15U +#define QSPI_FCR_WREN_MSK BIT(QSPI_FCR_WREN_POS) + +#define QSPI_FCR_WDNUM_POSS 12U +#define QSPI_FCR_WDNUM_POSE 14U +#define QSPI_FCR_WDNUM_MSK BITS(QSPI_FCR_WDNUM_POSS,QSPI_FCR_WDNUM_POSE) + +#define QSPI_FCR_DUMNUM_POSS 7U +#define QSPI_FCR_DUMNUM_POSE 11U +#define QSPI_FCR_DUMNUM_MSK BITS(QSPI_FCR_DUMNUM_POSS,QSPI_FCR_DUMNUM_POSE) + +#define QSPI_FCR_CMDS_POS 1U +#define QSPI_FCR_CMDS_MSK BIT(QSPI_FCR_CMDS_POS) + +#define QSPI_FCR_CMDT_POS 0U +#define QSPI_FCR_CMDT_MSK BIT(QSPI_FCR_CMDT_POS) + +/****************** Bit definition for QSPI_FCAR register ************************/ + +#define QSPI_FCAR_CMDADR_POSS 0U +#define QSPI_FCAR_CMDADR_POSE 31U +#define QSPI_FCAR_CMDADR_MSK BITS(QSPI_FCAR_CMDADR_POSS,QSPI_FCAR_CMDADR_POSE) + +/****************** Bit definition for QSPI_FCRLR register ************************/ + +#define QSPI_FCRLR_CMDDL_POSS 0U +#define QSPI_FCRLR_CMDDL_POSE 31U +#define QSPI_FCRLR_CMDDL_MSK BITS(QSPI_FCRLR_CMDDL_POSS,QSPI_FCRLR_CMDDL_POSE) + +/****************** Bit definition for QSPI_FCRHR register ************************/ + +#define QSPI_FCRHR_CMDDH_POSS 0U +#define QSPI_FCRHR_CMDDH_POSE 31U +#define QSPI_FCRHR_CMDDH_MSK BITS(QSPI_FCRHR_CMDDH_POSS,QSPI_FCRHR_CMDDH_POSE) + +/****************** Bit definition for QSPI_FCWLR register ************************/ + +#define QSPI_FCWLR_CMDDL_POSS 0U +#define QSPI_FCWLR_CMDDL_POSE 31U +#define QSPI_FCWLR_CMDDL_MSK BITS(QSPI_FCWLR_CMDDL_POSS,QSPI_FCWLR_CMDDL_POSE) + +/****************** Bit definition for QSPI_FCWHR register ************************/ + +#define QSPI_FCWHR_CMDDH_POSS 0U +#define QSPI_FCWHR_CMDDH_POSE 31U +#define QSPI_FCWHR_CMDDH_MSK BITS(QSPI_FCWHR_CMDDH_POSS,QSPI_FCWHR_CMDDH_POSE) + +/****************** Bit definition for QSPI_PFSR register ************************/ + +#define QSPI_PFSR_PSV_POS 8U +#define QSPI_PFSR_PSV_MSK BIT(QSPI_PFSR_PSV_POS) + +#define QSPI_PFSR_FLSS_POSS 0U +#define QSPI_PFSR_FLSS_POSE 7U +#define QSPI_PFSR_FLSS_MSK BITS(QSPI_PFSR_FLSS_POSS,QSPI_PFSR_FLSS_POSE) + +/****************** Bit definition for QSPI_MIDR register ************************/ + +#define QSPI_MIDR_ID1_POSS 24U +#define QSPI_MIDR_ID1_POSE 31U +#define QSPI_MIDR_ID1_MSK BITS(QSPI_MIDR_ID1_POSS,QSPI_MIDR_ID1_POSE) + +#define QSPI_MIDR_ID0_POSS 0U +#define QSPI_MIDR_ID0_POSE 23U +#define QSPI_MIDR_ID0_MSK BITS(QSPI_MIDR_ID0_POSS,QSPI_MIDR_ID0_POSE) + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t DRIR; + __IO uint32_t DWIR; + __IO uint32_t DDLR; + __IO uint32_t RDCR; + __IO uint32_t DSCR; + __IO uint32_t SPR; + __IO uint32_t IATR; + __IO uint32_t DMACR; + __IO uint32_t RAR; + __IO uint32_t MBR; + __I uint32_t SFLR; + __IO uint32_t TXHR; + __IO uint32_t RXHR; + __IO uint32_t WCR; + __IO uint32_t PER; + __IO uint32_t IFR; + __IO uint32_t IMR; + uint32_t RESERVED0[2] ; + __IO uint32_t WPLR; + __IO uint32_t WPHR; + __IO uint32_t WPCR; + uint32_t RESERVED1 ; + __O uint32_t IRTR; + __IO uint32_t IRTWR; + __IO uint32_t IRTSAR; + __IO uint32_t IRTNR; + __O uint32_t IWTR; + __IO uint32_t IWTWR; + __IO uint32_t IWTSAR; + __IO uint32_t IWTNR; + __IO uint32_t ITARR; + uint32_t RESERVED2[3] ; + __O uint32_t FCR; + __IO uint32_t FCAR; + uint32_t RESERVED3[2] ; + __I uint32_t FCRLR; + __I uint32_t FCRHR; + __IO uint32_t FCWLR; + __IO uint32_t FCWHR; + __I uint32_t PFSR; + uint32_t RESERVED4[18] ; + __I uint32_t MIDR; +} QSPI_TypeDef; + +/****************** Bit definition for EBI_BCTRLRx(x= 1..3) register ************************/ + +#define EBI_BCTRLRx_RWCBURSTEN_POS 19U +#define EBI_BCTRLRx_RWCBURSTEN_MSK BIT(EBI_BCTRLRx_RWCBURSTEN_POS) + +#define EBI_BCTRLRx_CPAGESIZE_POSS 16U +#define EBI_BCTRLRx_CPAGESIZE_POSE 18U +#define EBI_BCTRLRx_CPAGESIZE_MSK BITS(EBI_BCTRLRx_CPAGESIZE_POSS,EBI_BCTRLRx_CPAGESIZE_POSE) + +#define EBI_BCTRLRx_ASYNCWAIT_POS 15U +#define EBI_BCTRLRx_ASYNCWAIT_MSK BIT(EBI_BCTRLRx_ASYNCWAIT_POS) + +#define EBI_BCTRLRx_EXTMODEN_POS 14U +#define EBI_BCTRLRx_EXTMODEN_MSK BIT(EBI_BCTRLRx_EXTMODEN_POS) + +#define EBI_BCTRLRx_WAITEN_POS 13U +#define EBI_BCTRLRx_WAITEN_MSK BIT(EBI_BCTRLRx_WAITEN_POS) + +#define EBI_BCTRLRx_WREN_POS 12U +#define EBI_BCTRLRx_WREN_MSK BIT(EBI_BCTRLRx_WREN_POS) + +#define EBI_BCTRLRx_WAITCFG_POS 11U +#define EBI_BCTRLRx_WAITCFG_MSK BIT(EBI_BCTRLRx_WAITCFG_POS) + +#define EBI_BCTRLRx_WRAPMODE_POS 10U +#define EBI_BCTRLRx_WRAPMODE_MSK BIT(EBI_BCTRLRx_WRAPMODE_POS) + +#define EBI_BCTRLRx_WAITPOL_POS 9U +#define EBI_BCTRLRx_WAITPOL_MSK BIT(EBI_BCTRLRx_WAITPOL_POS) + +#define EBI_BCTRLRx_BURSTEN_POS 8U +#define EBI_BCTRLRx_BURSTEN_MSK BIT(EBI_BCTRLRx_BURSTEN_POS) + +#define EBI_BCTRLRx_FLASHACCEN_POS 6U +#define EBI_BCTRLRx_FLASHACCEN_MSK BIT(EBI_BCTRLRx_FLASHACCEN_POS) + +#define EBI_BCTRLRx_MEMWID_POSS 4U +#define EBI_BCTRLRx_MEMWID_POSE 5U +#define EBI_BCTRLRx_MEMWID_MSK BITS(EBI_BCTRLRx_MEMWID_POSS,EBI_BCTRLRx_MEMWID_POSE) +#define EBI_BCTRLRx_MEMWID_0 (0x1U << EBI_BCTRLRx_MEMWID_POSS) +#define EBI_BCTRLRx_MEMWID_1 (0x2U << EBI_BCTRLRx_MEMWID_POSS) + +#define EBI_BCTRLRx_MEMTYP_POSS 2U +#define EBI_BCTRLRx_MEMTYP_POSE 3U +#define EBI_BCTRLRx_MEMTYP_MSK BITS(EBI_BCTRLRx_MEMTYP_POSS,EBI_BCTRLRx_MEMTYP_POSE) +#define EBI_BCTRLRx_MEMTYP_0 (0x1U << EBI_BCTRLRx_MEMTYP_POSS) +#define EBI_BCTRLRx_MEMTYP_1 (0x2U << EBI_BCTRLRx_MEMTYP_POSS) + +#define EBI_BCTRLRx_MUXEN_POS 1U +#define EBI_BCTRLRx_MUXEN_MSK BIT(EBI_BCTRLRx_MUXEN_POS) + +#define EBI_BCTRLRx_MEMBKEN_POS 0U +#define EBI_BCTRLRx_MEMBKEN_MSK BIT(EBI_BCTRLRx_MEMBKEN_POS) + +/****************** Bit definition for EBI_BTRx(x= 1..3) register ************************/ + +#define EBI_BTRx_ACCMODE_POSS 28U +#define EBI_BTRx_ACCMODE_POSE 29U +#define EBI_BTRx_ACCMODE_MSK BITS(EBI_BTRx_ACCMODE_POSS,EBI_BTRx_ACCMODE_POSE) +#define EBI_BTRx_ACCMODE_0 (0x1U << EBI_BTRx_ACCMODE_POSS) +#define EBI_BTRx_ACCMODE_1 (0x2U << EBI_BTRx_ACCMODE_POSS) + +#define EBI_BTRx_DATALAT_POSS 24U +#define EBI_BTRx_DATALAT_POSE 27U +#define EBI_BTRx_DATALAT_MSK BITS(EBI_BTRx_DATALAT_POSS,EBI_BTRx_DATALAT_POSE) + +#define EBI_BTRx_CLKDIV_POSS 20U +#define EBI_BTRx_CLKDIV_POSE 23U +#define EBI_BTRx_CLKDIV_MSK BITS(EBI_BTRx_CLKDIV_POSS,EBI_BTRx_CLKDIV_POSE) + +#define EBI_BTRx_BUSTURN_POSS 16U +#define EBI_BTRx_BUSTURN_POSE 19U +#define EBI_BTRx_BUSTURN_MSK BITS(EBI_BTRx_BUSTURN_POSS,EBI_BTRx_BUSTURN_POSE) + +#define EBI_BTRx_DATAHOLD_POSS 8U +#define EBI_BTRx_DATAHOLD_POSE 15U +#define EBI_BTRx_DATAHOLD_MSK BITS(EBI_BTRx_DATAHOLD_POSS,EBI_BTRx_DATAHOLD_POSE) + +#define EBI_BTRx_ADDHOLD_POSS 4U +#define EBI_BTRx_ADDHOLD_POSE 7U +#define EBI_BTRx_ADDHOLD_MSK BITS(EBI_BTRx_ADDHOLD_POSS,EBI_BTRx_ADDHOLD_POSE) + +#define EBI_BTRx_ADDATASETUP_POSS 0U +#define EBI_BTRx_ADDATASETUP_POSE 3U +#define EBI_BTRx_ADDATASETUP_MSK BITS(EBI_BTRx_ADDATASETUP_POSS,EBI_BTRx_ADDATASETUP_POSE) + +/****************** Bit definition for EBI_BWRTRx(x= 1..3) register ************************/ + +#define EBI_BWRTRx_ACCMODE_POSS 28U +#define EBI_BWRTRx_ACCMODE_POSE 29U +#define EBI_BWRTRx_ACCMODE_MSK BITS(EBI_BWRTRx_ACCMODE_POSS,EBI_BWRTRx_ACCMODE_POSE) + +#define EBI_BWRTRx_BUSTURN_POSS 16U +#define EBI_BWRTRx_BUSTURN_POSE 19U +#define EBI_BWRTRx_BUSTURN_MSK BITS(EBI_BWRTRx_BUSTURN_POSS,EBI_BWRTRx_BUSTURN_POSE) + +#define EBI_BWRTRx_DATAHOLD_POSS 8U +#define EBI_BWRTRx_DATAHOLD_POSE 15U +#define EBI_BWRTRx_DATAHOLD_MSK BITS(EBI_BWRTRx_DATAHOLD_POSS,EBI_BWRTRx_DATAHOLD_POSE) + +#define EBI_BWRTRx_ADDHOLD_POSS 4U +#define EBI_BWRTRx_ADDHOLD_POSE 7U +#define EBI_BWRTRx_ADDHOLD_MSK BITS(EBI_BWRTRx_ADDHOLD_POSS,EBI_BWRTRx_ADDHOLD_POSE) + +#define EBI_BWRTRx_ADDATASETUP_POSS 0U +#define EBI_BWRTRx_ADDATASETUP_POSE 3U +#define EBI_BWRTRx_ADDATASETUP_MSK BITS(EBI_BWRTRx_ADDATASETUP_POSS,EBI_BWRTRx_ADDATASETUP_POSE) + +/****************** Bit definition for EBI_LCDCTRLx(x= 1..3) register ************************/ + +#define EBI_LCDCTRLx_HSYNCPOL_POS 29U +#define EBI_LCDCTRLx_HSYNCPOL_MSK BIT(EBI_LCDCTRLx_HSYNCPOL_POS) + +#define EBI_LCDCTRLx_VSYNCPOL_POS 28U +#define EBI_LCDCTRLx_VSYNCPOL_MSK BIT(EBI_LCDCTRLx_VSYNCPOL_POS) + +#define EBI_LCDCTRLx_DENPOL_POS 27U +#define EBI_LCDCTRLx_DENPOL_MSK BIT(EBI_LCDCTRLx_DENPOL_POS) + +#define EBI_LCDCTRLx_LCDEN_POS 26U +#define EBI_LCDCTRLx_LCDEN_MSK BIT(EBI_LCDCTRLx_LCDEN_POS) + +#define EBI_LCDCTRLx_LCDINT_POS 25U +#define EBI_LCDCTRLx_LCDINT_MSK BIT(EBI_LCDCTRLx_LCDINT_POS) + +#define EBI_LCDCTRLx_DCLKPOL_POS 24U +#define EBI_LCDCTRLx_DCLKPOL_MSK BIT(EBI_LCDCTRLx_DCLKPOL_POS) + +#define EBI_LCDCTRLx_DATASETUP_POSS 16U +#define EBI_LCDCTRLx_DATASETUP_POSE 23U +#define EBI_LCDCTRLx_DATASETUP_MSK BITS(EBI_LCDCTRLx_DATASETUP_POSS,EBI_LCDCTRLx_DATASETUP_POSE) + +#define EBI_LCDCTRLx_VSYNCWID_POSS 8U +#define EBI_LCDCTRLx_VSYNCWID_POSE 15U +#define EBI_LCDCTRLx_VSYNCWID_MSK BITS(EBI_LCDCTRLx_VSYNCWID_POSS,EBI_LCDCTRLx_VSYNCWID_POSE) + +#define EBI_LCDCTRLx_HSYNCWID_POSS 0U +#define EBI_LCDCTRLx_HSYNCWID_POSE 7U +#define EBI_LCDCTRLx_HSYNCWID_MSK BITS(EBI_LCDCTRLx_HSYNCWID_POSS,EBI_LCDCTRLx_HSYNCWID_POSE) + +/****************** Bit definition for EBI_LCDCFGx(x= 1..4) register ************************/ + +#define EBI_LCDCFGx_LINENUM_POSS 16U +#define EBI_LCDCFGx_LINENUM_POSE 31U +#define EBI_LCDCFGx_LINENUM_MSK BITS(EBI_LCDCFGx_LINENUM_POSS,EBI_LCDCFGx_LINENUM_POSE) + +#define EBI_LCDCFGx_PXLNUM_POSS 0U +#define EBI_LCDCFGx_PXLNUM_POSE 15U +#define EBI_LCDCFGx_PXLNUM_MSK BITS(EBI_LCDCFGx_PXLNUM_POSS,EBI_LCDCFGx_PXLNUM_POSE) + +/****************** Bit definition for EBI_LCDSTx(x= 1..3) register ************************/ + +#define EBI_LCDSTx_LINECNT_POSS 16U +#define EBI_LCDSTx_LINECNT_POSE 31U +#define EBI_LCDSTx_LINECNT_MSK BITS(EBI_LCDSTx_LINECNT_POSS,EBI_LCDSTx_LINECNT_POSE) + +#define EBI_LCDSTx_PXLCNT_POSS 0U +#define EBI_LCDSTx_PXLCNT_POSE 15U +#define EBI_LCDSTx_PXLCNT_MSK BITS(EBI_LCDSTx_PXLCNT_POSS,EBI_LCDSTx_PXLCNT_POSE) + +/****************** Bit definition for EBI_PCTRLRx(x = 2..3) register ************************/ + +#define EBI_PCTRLRx_ECCPSIZE_POSS 17U +#define EBI_PCTRLRx_ECCPSIZE_POSE 19U +#define EBI_PCTRLRx_ECCPSIZE_MSK BITS(EBI_PCTRLRx_ECCPSIZE_POSS,EBI_PCTRLRx_ECCPSIZE_POSE) +#define EBI_PCTRLRx_ECCPS_0 (0x1U << EBI_PCTRLRx_ECCPSIZE_POSS) +#define EBI_PCTRLRx_ECCPS_1 (0x2U << EBI_PCTRLRx_ECCPSIZE_POSS) +#define EBI_PCTRLRx_ECCPS_2 (0x4U << EBI_PCTRLRx_ECCPSIZE_POSS) + +#define EBI_PCTRLRx_ARDLY_POSS 13U +#define EBI_PCTRLRx_ARDLY_POSE 16U +#define EBI_PCTRLRx_ARDLY_MSK BITS(EBI_PCTRLRx_ARDLY_POSS,EBI_PCTRLRx_ARDLY_POSE) + +#define EBI_PCTRLRx_CRDLY_POSS 9U +#define EBI_PCTRLRx_CRDLY_POSE 12U +#define EBI_PCTRLRx_CRDLY_MSK BITS(EBI_PCTRLRx_CRDLY_POSS,EBI_PCTRLRx_CRDLY_POSE) + +#define EBI_PCTRLRx_TFUNSEL_POS 8U +#define EBI_PCTRLRx_TFUNSEL_MSK BIT(EBI_PCTRLRx_TFUNSEL_POS) + +#define EBI_PCTRLRx_ECCEN_POS 6U +#define EBI_PCTRLRx_ECCEN_MSK BIT(EBI_PCTRLRx_ECCEN_POS) + +#define EBI_PCTRLRx_DATBUSWID_POSS 4U +#define EBI_PCTRLRx_DATBUSWID_POSE 5U +#define EBI_PCTRLRx_DATBUSWID_MSK BITS(EBI_PCTRLRx_DATBUSWID_POSS,EBI_PCTRLRx_DATBUSWID_POSE) + +#define EBI_PCTRLRx_MEMTYP_POS 3U +#define EBI_PCTRLRx_MEMTYP_MSK BIT(EBI_PCTRLRx_MEMTYP_POS) + +#define EBI_PCTRLRx_MEMBKEN_POS 2U +#define EBI_PCTRLRx_MEMBKEN_MSK BIT(EBI_PCTRLRx_MEMBKEN_POS) + +#define EBI_PCTRLRx_WAITEN_POS 1U +#define EBI_PCTRLRx_WAITEN_MSK BIT(EBI_PCTRLRx_WAITEN_POS) + +/****************** Bit definition for EBI_STARx(x = 2..3) register ************************/ + +#define EBI_STARx_FIFOEMPT_POS 6U +#define EBI_STARx_FIFOEMPT_MSK BIT(EBI_STARx_FIFOEMPT_POS) + +#define EBI_STARx_IFALLEN_POS 5U +#define EBI_STARx_IFALLEN_MSK BIT(EBI_STARx_IFALLEN_POS) + +#define EBI_STARx_IHILEN_POS 4U +#define EBI_STARx_IHILEN_MSK BIT(EBI_STARx_IHILEN_POS) + +#define EBI_STARx_IRISEEN_POS 3U +#define EBI_STARx_IRISEEN_MSK BIT(EBI_STARx_IRISEEN_POS) + +#define EBI_STARx_IFALLS_POS 2U +#define EBI_STARx_IFALLS_MSK BIT(EBI_STARx_IFALLS_POS) + +#define EBI_STARx_IHILS_POS 1U +#define EBI_STARx_IHILS_MSK BIT(EBI_STARx_IHILS_POS) + +#define EBI_STARx_IRISES_POS 0U +#define EBI_STARx_IRISES_MSK BIT(EBI_STARx_IRISES_POS) + +/****************** Bit definition for EBI_PMEMRx(x = 2..3) register ************************/ + +#define EBI_PMEMRx_MEMHIZT_POSS 24U +#define EBI_PMEMRx_MEMHIZT_POSE 31U +#define EBI_PMEMRx_MEMHIZT_MSK BITS(EBI_PMEMRx_MEMHIZT_POSS,EBI_PMEMRx_MEMHIZT_POSE) + +#define EBI_PMEMRx_MEMHOLD_POSS 16U +#define EBI_PMEMRx_MEMHOLD_POSE 23U +#define EBI_PMEMRx_MEMHOLD_MSK BITS(EBI_PMEMRx_MEMHOLD_POSS,EBI_PMEMRx_MEMHOLD_POSE) + +#define EBI_PMEMRx_MEMWAIT_POSS 8U +#define EBI_PMEMRx_MEMWAIT_POSE 15U +#define EBI_PMEMRx_MEMWAIT_MSK BITS(EBI_PMEMRx_MEMWAIT_POSS,EBI_PMEMRx_MEMWAIT_POSE) + +#define EBI_PMEMRx_MEMSETUP_POSS 0U +#define EBI_PMEMRx_MEMSETUP_POSE 7U +#define EBI_PMEMRx_MEMSETUP_MSK BITS(EBI_PMEMRx_MEMSETUP_POSS,EBI_PMEMRx_MEMSETUP_POSE) + +/****************** Bit definition for EBI_PATTRx(x = 2..3) register ************************/ + +#define EBI_PATTRx_ATTHIZT_POSS 24U +#define EBI_PATTRx_ATTHIZT_POSE 31U +#define EBI_PATTRx_ATTHIZT_MSK BITS(EBI_PATTRx_ATTHIZT_POSS,EBI_PATTRx_ATTHIZT_POSE) + +#define EBI_PATTRx_ATTHOLD_POSS 16U +#define EBI_PATTRx_ATTHOLD_POSE 23U +#define EBI_PATTRx_ATTHOLD_MSK BITS(EBI_PATTRx_ATTHOLD_POSS,EBI_PATTRx_ATTHOLD_POSE) + +#define EBI_PATTRx_ATTWAIT_POSS 8U +#define EBI_PATTRx_ATTWAIT_POSE 15U +#define EBI_PATTRx_ATTWAIT_MSK BITS(EBI_PATTRx_ATTWAIT_POSS,EBI_PATTRx_ATTWAIT_POSE) + +#define EBI_PATTRx_ATTSETUP_POSS 0U +#define EBI_PATTRx_ATTSETUP_POSE 7U +#define EBI_PATTRx_ATTSETUP_MSK BITS(EBI_PATTRx_ATTSETUP_POSS,EBI_PATTRx_ATTSETUP_POSE) + +/****************** Bit definition for EBI_ECCRESULTx(x = 2..3) register ************************/ + +#define EBI_ECCRESULTx_ECCRESULT_POSS 0U +#define EBI_ECCRESULTx_ECCRESULT_POSE 31U +#define EBI_ECCRESULTx_ECCRESULT_MSK BITS(EBI_ECCRESULTx_ECCRESULT_POSS,EBI_ECCRESULTx_ECCRESULT_POSE) + +typedef struct +{ + __IO uint32_t BTCR[8]; +} EBI_Bank1_TypeDef; + +typedef struct +{ + __IO uint32_t BWTR[7]; +} EBI_Bank1E_TypeDef; + +typedef struct +{ + __IO uint32_t PCTRLR2; + __IO uint32_t STAR2; + __IO uint32_t PMEMR2; + __IO uint32_t PATTR2; + uint32_t RESERVED0; + __IO uint32_t ECCRESULT2; + uint32_t RESERVED1; + uint32_t RESERVED2; + __IO uint32_t PCTRLR3; + __IO uint32_t STAR3; + __IO uint32_t PMEMR3; + __IO uint32_t PATTR3; + uint32_t RESERVED3; + __IO uint32_t ECCRESULT3; +} EBI_Bank2_3_TypeDef; + +typedef struct +{ + __IO uint32_t LCDCRCFGS[15]; + +} EBI_Bank1_LCD_TypeDef; + + +/****************** Bit definition for USB_FADDR register ************************/ + +#define USB_FADDR_FADDR_POSS 0U +#define USB_FADDR_FADDR_POSE 6U +#define USB_FADDR_FADDR_MSK BITS(USB_FADDR_FADDR_POSS,USB_FADDR_FADDR_POSE) + +/****************** Bit definition for USB_POWER register ************************/ + +#define USB_POWER_ISOUPDATA_POS 7U +#define USB_POWER_ISOUPDATA_MSK BIT(USB_POWER_ISOUPDATA_POS) + +#define USB_POWER_SOFTCONN_POS 6U +#define USB_POWER_SOFTCONN_MSK BIT(USB_POWER_SOFTCONN_POS) + +#define USB_POWER_HS_EN_POS 5U +#define USB_POWER_HS_EN_MSK BIT(USB_POWER_HS_EN_POS) + +#define USB_POWER_HS_M_POS 4U +#define USB_POWER_HS_M_MSK BIT(USB_POWER_HS_M_POS) + +#define USB_POWER_RESET_POS 3U +#define USB_POWER_RESET_MSK BIT(USB_POWER_RESET_POS) + +#define USB_POWER_RESUME_POS 2U +#define USB_POWER_RESUME_MSK BIT(USB_POWER_RESUME_POS) + +#define USB_POWER_SUSPEND_POS 1U +#define USB_POWER_SUSPEND_MSK BIT(USB_POWER_SUSPEND_POS) + +#define USB_POWER_EN_SPDM_POS 0U +#define USB_POWER_EN_SPDM_MSK BIT(USB_POWER_EN_SPDM_POS) + +/****************** Bit definition for USB_TXIS register ************************/ + +#define USB_TXIS_EP7TX_IF_POS 7U +#define USB_TXIS_EP7TX_IF_MSK BIT(USB_TXIS_EP7TX_IF_POS) + +#define USB_TXIS_EP6TX_IF_POS 6U +#define USB_TXIS_EP6TX_IF_MSK BIT(USB_TXIS_EP6TX_IF_POS) + +#define USB_TXIS_EP5TX_IF_POS 5U +#define USB_TXIS_EP5TX_IF_MSK BIT(USB_TXIS_EP5TX_IF_POS) + +#define USB_TXIS_EP4TX_IF_POS 4U +#define USB_TXIS_EP4TX_IF_MSK BIT(USB_TXIS_EP4TX_IF_POS) + +#define USB_TXIS_EP3TX_IF_POS 3U +#define USB_TXIS_EP3TX_IF_MSK BIT(USB_TXIS_EP3TX_IF_POS) + +#define USB_TXIS_EP2TX_IF_POS 2U +#define USB_TXIS_EP2TX_IF_MSK BIT(USB_TXIS_EP2TX_IF_POS) + +#define USB_TXIS_EP1TX_IF_POS 1U +#define USB_TXIS_EP1TX_IF_MSK BIT(USB_TXIS_EP1TX_IF_POS) + +#define USB_TXIS_EP0_IF_POS 0U +#define USB_TXIS_EP0_IF_MSK BIT(USB_TXIS_EP0_IF_POS) + +/****************** Bit definition for USB_RXIS register ************************/ + +#define USB_RXIS_EP7RX_IF_POS 7U +#define USB_RXIS_EP7RX_IF_MSK BIT(USB_RXIS_EP7RX_IF_POS) + +#define USB_RXIS_EP6RX_IF_POS 6U +#define USB_RXIS_EP6RX_IF_MSK BIT(USB_RXIS_EP6RX_IF_POS) + +#define USB_RXIS_EP5RX_IF_POS 5U +#define USB_RXIS_EP5RX_IF_MSK BIT(USB_RXIS_EP5RX_IF_POS) + +#define USB_RXIS_EP4RX_IF_POS 4U +#define USB_RXIS_EP4RX_IF_MSK BIT(USB_RXIS_EP4RX_IF_POS) + +#define USB_RXIS_EP3RX_IF_POS 3U +#define USB_RXIS_EP3RX_IF_MSK BIT(USB_RXIS_EP3RX_IF_POS) + +#define USB_RXIS_EP2RX_IF_POS 2U +#define USB_RXIS_EP2RX_IF_MSK BIT(USB_RXIS_EP2RX_IF_POS) + +#define USB_RXIS_EP1RX_IF_POS 1U +#define USB_RXIS_EP1RX_IF_MSK BIT(USB_RXIS_EP1RX_IF_POS) + +/****************** Bit definition for USB_TXIE register ************************/ + +#define USB_TXIE_EP7TX_IE_POS 7U +#define USB_TXIE_EP7TX_IE_MSK BIT(USB_TXIE_EP7TX_IE_POS) + +#define USB_TXIE_EP6TX_IE_POS 6U +#define USB_TXIE_EP6TX_IE_MSK BIT(USB_TXIE_EP6TX_IE_POS) + +#define USB_TXIE_EP5TX_IE_POS 5U +#define USB_TXIE_EP5TX_IE_MSK BIT(USB_TXIE_EP5TX_IE_POS) + +#define USB_TXIE_EP4TX_IE_POS 4U +#define USB_TXIE_EP4TX_IE_MSK BIT(USB_TXIE_EP4TX_IE_POS) + +#define USB_TXIE_EP3TX_IE_POS 3U +#define USB_TXIE_EP3TX_IE_MSK BIT(USB_TXIE_EP3TX_IE_POS) + +#define USB_TXIE_EP2TX_IE_POS 2U +#define USB_TXIE_EP2TX_IE_MSK BIT(USB_TXIE_EP2TX_IE_POS) + +#define USB_TXIE_EP1TX_IE_POS 1U +#define USB_TXIE_EP1TX_IE_MSK BIT(USB_TXIE_EP1TX_IE_POS) + +#define USB_TXIE_EP0_IE_POS 0U +#define USB_TXIE_EP0_IE_MSK BIT(USB_TXIE_EP0_IE_POS) + +/****************** Bit definition for USB_RXIE register ************************/ + +#define USB_RXIE_EP7RX_IE_POS 7U +#define USB_RXIE_EP7RX_IE_MSK BIT(USB_RXIE_EP7RX_IE_POS) + +#define USB_RXIE_EP6RX_IE_POS 6U +#define USB_RXIE_EP6RX_IE_MSK BIT(USB_RXIE_EP6RX_IE_POS) + +#define USB_RXIE_EP5RX_IE_POS 5U +#define USB_RXIE_EP5RX_IE_MSK BIT(USB_RXIE_EP5RX_IE_POS) + +#define USB_RXIE_EP4RX_IE_POS 4U +#define USB_RXIE_EP4RX_IE_MSK BIT(USB_RXIE_EP4RX_IE_POS) + +#define USB_RXIE_EP3RX_IE_POS 3U +#define USB_RXIE_EP3RX_IE_MSK BIT(USB_RXIE_EP3RX_IE_POS) + +#define USB_RXIE_EP2RX_IE_POS 2U +#define USB_RXIE_EP2RX_IE_MSK BIT(USB_RXIE_EP2RX_IE_POS) + +#define USB_RXIE_EP1RX_IE_POS 1U +#define USB_RXIE_EP1RX_IE_MSK BIT(USB_RXIE_EP1RX_IE_POS) + +/****************** Bit definition for USB_USBIS register ************************/ + +#define USB_USBIS_DISCON_IF_POS 5U +#define USB_USBIS_DISCON_IF_MSK BIT(USB_USBIS_DISCON_IF_POS) + +#define USB_USBIS_SOF_IF_POS 3U +#define USB_USBIS_SOF_IF_MSK BIT(USB_USBIS_SOF_IF_POS) + +#define USB_USBIS_RESET_IF_POS 2U +#define USB_USBIS_RESET_IF_MSK BIT(USB_USBIS_RESET_IF_POS) + +#define USB_USBIS_RESUME_IF_POS 1U +#define USB_USBIS_RESUME_IF_MSK BIT(USB_USBIS_RESUME_IF_POS) + +#define USB_USBIS_SUSPEND_IF_POS 0U +#define USB_USBIS_SUSPEND_IF_MSK BIT(USB_USBIS_SUSPEND_IF_POS) + +/****************** Bit definition for USB_USBIE register ************************/ + +#define USB_USBIE_DISCON_IE_POS 5U +#define USB_USBIE_DISCON_IE_MSK BIT(USB_USBIE_DISCON_IE_POS) + +#define USB_USBIE_SOF_IE_POS 3U +#define USB_USBIE_SOF_IE_MSK BIT(USB_USBIE_SOF_IE_POS) + +#define USB_USBIE_RESET_IE_POS 2U +#define USB_USBIE_RESET_IE_MSK BIT(USB_USBIE_RESET_IE_POS) + +#define USB_USBIE_RESUME_IE_POS 1U +#define USB_USBIE_RESUME_IE_MSK BIT(USB_USBIE_RESUME_IE_POS) + +#define USB_USBIE_SUSPEND_IE_POS 0U +#define USB_USBIE_SUSPEND_IE_MSK BIT(USB_USBIE_SUSPEND_IE_POS) + +/****************** Bit definition for USB_FRAME register ************************/ + +#define USB_FRAME_FRAME_POSS 0U +#define USB_FRAME_FRAME_POSE 10U +#define USB_FRAME_FRAME_MSK BITS(USB_FRAME_FRAME_POSS,USB_FRAME_FRAME_POSE) + +/****************** Bit definition for USB_INDEX register ************************/ + +#define USB_INDEX_EP_INDEX_POSS 0U +#define USB_INDEX_EP_INDEX_POSE 3U +#define USB_INDEX_EP_INDEX_MSK BITS(USB_INDEX_EP_INDEX_POSS,USB_INDEX_EP_INDEX_POSE) + +/****************** Bit definition for USB_TEST register ************************/ + +#define USB_TEST_FORCE_HST_POS 7U +#define USB_TEST_FORCE_HST_MSK BIT(USB_TEST_FORCE_HST_POS) + +#define USB_TEST_FIFO_ACS_POS 6U +#define USB_TEST_FIFO_ACS_MSK BIT(USB_TEST_FIFO_ACS_POS) + +#define USB_TEST_FORCE_FS_POS 5U +#define USB_TEST_FORCE_FS_MSK BIT(USB_TEST_FORCE_FS_POS) + +#define USB_TEST_FORCE_HS_POS 4U +#define USB_TEST_FORCE_HS_MSK BIT(USB_TEST_FORCE_HS_POS) + +#define USB_TEST_TEST_PKT_POS 3U +#define USB_TEST_TEST_PKT_MSK BIT(USB_TEST_TEST_PKT_POS) + +#define USB_TEST_TEST_K_POS 2U +#define USB_TEST_TEST_K_MSK BIT(USB_TEST_TEST_K_POS) + +#define USB_TEST_TEST_J_POS 1U +#define USB_TEST_TEST_J_MSK BIT(USB_TEST_TEST_J_POS) + +#define USB_TEST_TEST_SENA_POS 0U +#define USB_TEST_TEST_SENA_MSK BIT(USB_TEST_TEST_SENA_POS) + +typedef union { + uint8_t Byte[4]; + uint16_t HalfWord[2]; + uint32_t Word; +} USB_FIFO_Typedef; + +/****************** Bit definition for USB_DEVCTL register ************************/ + +#define USB_DEVCTL_BDEVICE_POS 7U +#define USB_DEVCTL_BDEVICE_MSK BIT(USB_DEVCTL_BDEVICE_POS) + +#define USB_DEVCTL_FSDEV_POS 6U +#define USB_DEVCTL_FSDEV_MSK BIT(USB_DEVCTL_FSDEV_POS) + +#define USB_DEVCTL_LSDEV_POS 5U +#define USB_DEVCTL_LSDEV_MSK BIT(USB_DEVCTL_LSDEV_POS) + +#define USB_DEVCTL_VBUS_POSS 3U +#define USB_DEVCTL_VBUS_POSE 4U +#define USB_DEVCTL_VBUS_MSK BITS(USB_DEVCTL_VBUS_POSS,USB_DEVCTL_VBUS_POSE) + +#define USB_DEVCTL_HOSTMODE_POS 2U +#define USB_DEVCTL_HOSTMODE_MSK BIT(USB_DEVCTL_HOSTMODE_POS) + +#define USB_DEVCTL_HOSTREQ_POS 1U +#define USB_DEVCTL_HOSTREQ_MSK BIT(USB_DEVCTL_HOSTREQ_POS) + +#define USB_DEVCTL_SESSION_POS 0U +#define USB_DEVCTL_SESSION_MSK BIT(USB_DEVCTL_SESSION_POS) + +/****************** Bit definition for USB_TXFIFOSIZE register ************************/ + +#define USB_TXFIFOSIZE_DPB_POS 4U +#define USB_TXFIFOSIZE_DPB_MSK BIT(USB_TXFIFOSIZE_DPB_POS) + +#define USB_TXFIFOSIZE_TXFIFOSIZE_POSS 0U +#define USB_TXFIFOSIZE_TXFIFOSIZE_POSE 3U +#define USB_TXFIFOSIZE_TXFIFOSIZE_MSK BITS(USB_TXFIFOSIZE_TXFIFOSIZE_POSS,USB_TXFIFOSIZE_TXFIFOSIZE_POSE) + +/****************** Bit definition for USB_RXFIFOSIZE register ************************/ + +#define USB_RXFIFOSIZE_DPB_POS 4U +#define USB_RXFIFOSIZE_DPB_MSK BIT(USB_RXFIFOSIZE_DPB_POS) + +#define USB_RXFIFOSIZE_RXFIFOSIZE_POSS 0U +#define USB_RXFIFOSIZE_RXFIFOSIZE_POSE 3U +#define USB_RXFIFOSIZE_RXFIFOSIZE_MSK BITS(USB_RXFIFOSIZE_RXFIFOSIZE_POSS,USB_RXFIFOSIZE_RXFIFOSIZE_POSE) + +/****************** Bit definition for USB_TXFIFOADD register ************************/ + +#define USB_TXFIFOADD_ADDR_POSS 0U +#define USB_TXFIFOADD_ADDR_POSE 8U +#define USB_TXFIFOADD_ADDR_MSK BITS(USB_TXFIFOADD_ADDR_POSS,USB_TXFIFOADD_ADDR_POSE) + +/****************** Bit definition for USB_RXFIFOADD register ************************/ + +#define USB_RXFIFOADD_ADDR_POSS 0U +#define USB_RXFIFOADD_ADDR_POSE 8U +#define USB_RXFIFOADD_ADDR_MSK BITS(USB_RXFIFOADD_ADDR_POSS,USB_RXFIFOADD_ADDR_POSE) + +/****************** Bit definition for USB_LINKINFO register ************************/ + +#define USB_LINKINFO_WTCON_POSS 4U +#define USB_LINKINFO_WTCON_POSE 7U +#define USB_LINKINFO_WTCON_MSK BITS(USB_LINKINFO_WTCON_POSS,USB_LINKINFO_WTCON_POSE) + +#define USB_LINKINFO_WTID_POSS 0U +#define USB_LINKINFO_WTID_POSE 3U +#define USB_LINKINFO_WTID_MSK BITS(USB_LINKINFO_WTID_POSS,USB_LINKINFO_WTID_POSE) + +/****************** Bit definition for USB_VPLEN register ************************/ + +#define USB_VPLEN_VPLEN_POSS 0U +#define USB_VPLEN_VPLEN_POSE 7U +#define USB_VPLEN_VPLEN_MSK BITS(USB_VPLEN_VPLEN_POSS,USB_VPLEN_VPLEN_POSE) + +/****************** Bit definition for USB_HS_EOF1 register ************************/ + +#define USB_HS_EOF1_HSEOF1_POSS 0U +#define USB_HS_EOF1_HSEOF1_POSE 7U +#define USB_HS_EOF1_HSEOF1_MSK BITS(USB_HS_EOF1_HSEOF1_POSS,USB_HS_EOF1_HSEOF1_POSE) + +/****************** Bit definition for USB_FS_EOF1 register ************************/ + +#define USB_FS_EOF1_FSEOF1_POSS 0U +#define USB_FS_EOF1_FSEOF1_POSE 7U +#define USB_FS_EOF1_FSEOF1_MSK BITS(USB_FS_EOF1_FSEOF1_POSS,USB_FS_EOF1_FSEOF1_POSE) + +/****************** Bit definition for USB_LS_EOF1 register ************************/ + +#define USB_LS_EOF1_LSEOF1_POSS 0U +#define USB_LS_EOF1_LSEOF1_POSE 7U +#define USB_LS_EOF1_LSEOF1_MSK BITS(USB_LS_EOF1_LSEOF1_POSS,USB_LS_EOF1_LSEOF1_POSE) + +/****************** Bit definition for TXxFUNCADDR register ************************/ + +#define USB_TXxFUNCADDR_ADDR_POSS 0U +#define USB_TXxFUNCADDR_ADDR_POSE 6U +#define USB_TXxFUNCADDR_ADDR_MSK BITS(USB_TXxFUNCADDR_ADDR_POSS,USB_TXxFUNCADDR_ADDR_POSE) + +/****************** Bit definition for TXxHUBADDR register ************************/ + +#define USB_TXxHUBADDR_ADDR_POSS 0U +#define USB_TXxHUBADDR_ADDR_POSE 6U +#define USB_TXxHUBADDR_ADDR_MSK BITS(USB_TXxHUBADDR_ADDR_POSS,USB_TXxHUBADDR_ADDR_POSE) + +#define USB_TXxHUBADDR_MULTTRAN_POS 7U +#define USB_TXxHUBADDR_MULTTRAN_MSK BIT(USB_TXxHUBADDR_MULTTRAN_POS) + +/****************** Bit definition for TXxHUBPORT register ************************/ + +#define USB_TXxHUBPORT_HUBPORT_POSS 0U +#define USB_TXxHUBPORT_HUBPORT_POSE 6U +#define USB_TXxHUBPORT_HUBPORT_MSK BITS(USB_TXxHUBPORT_HUBPORT_POSS,USB_TXxHUBPORT_HUBPORT_POSE) + +/****************** Bit definition for RXxFUNCADDR register ************************/ + +#define USB_RXxFUNCADDR_ADDR_POSS 0U +#define USB_RXxFUNCADDR_ADDR_POSE 6U +#define USB_RXxFUNCADDR_ADDR_MSK BITS(USB_RXxFUNCADDR_ADDR_POSS,USB_RXxFUNCADDR_ADDR_POSE) + +/****************** Bit definition for RXxHUBADDR register ************************/ + +#define USB_RXxHUBADDR_ADDR_POSS 0U +#define USB_RXxHUBADDR_ADDR_POSE 6U +#define USB_RXxHUBADDR_ADDR_MSK BITS(USB_RXxHUBADDR_ADDR_POSS,USB_RXxHUBADDR_ADDR_POSE) + +#define USB_RXxHUBADDR_MULTTRAN_POS 7U +#define USB_RXxHUBADDR_MULTTRAN_MSK BIT(USB_RXxHUBADDR_MULTTRAN_POS) + +/****************** Bit definition for RXxHUBPORT register ************************/ + +#define USB_RXxHUBPORT_HUBPORT_POSS 0U +#define USB_RXxHUBPORT_HUBPORT_POSE 6U +#define USB_RXxHUBPORT_HUBPORT_MSK BITS(USB_RXxHUBPORT_HUBPORT_POSS,USB_RXxHUBPORT_HUBPORT_POSE) + +typedef struct { + __IO uint8_t TXxFUNCADDR; + uint8_t rsv0; + __IO uint8_t TXxHUBADDR; + __IO uint8_t TXxHUBPORT; + __IO uint8_t RXxFUNCADDR; + uint8_t rsv1; + __IO uint8_t RXxHUBADDR; + __IO uint8_t RXxHUBPORT; +} USB_ADDR_Typedef; + +typedef struct{ + __IO uint16_t TXxMAXP; + __IO uint8_t TXxCSRL; + __IO uint8_t TXxCSRH; + __IO uint16_t RXxMAXP; + __IO uint8_t RXxCSRL; + __IO uint8_t RXxCSRH; + __I uint16_t RXxCOUNT; + __IO uint8_t TXxTYPE; + __IO uint8_t TXxINTERVAL; + __IO uint8_t RXxTYPE; + __IO uint8_t RXxINTERVAL; + uint8_t rsv0[2]; +} USB_CSRx_Typedef; + +/****************** Bit definition for DMA_INTR register ************************/ + +#define USB_DMA_INTR_CH0_POS 0U +#define USB_DMA_INTR_CH0_MSK BIT(USB_DMA_INTR_CH0_POS) + +#define USB_DMA_INTR_CH1_POS 1U +#define USB_DMA_INTR_CH1_MSK BIT(USB_DMA_INTR_CH1_POS) + +#define USB_DMA_INTR_CH2_POS 2U +#define USB_DMA_INTR_CH2_MSK BIT(USB_DMA_INTR_CH2_POS) + +#define USB_DMA_INTR_CH3_POS 3U +#define USB_DMA_INTR_CH3_MSK BIT(USB_DMA_INTR_CH3_POS) + +/****************** Bit definition for DMA_CNTL register ************************/ + +#define USB_DMA_CNTL_EN_POS 0U +#define USB_DMA_CNTL_EN_MSK BIT(USB_DMA_CNTL_EN_POS) + +#define USB_DMA_CNTL_DIR_POS 1U +#define USB_DMA_CNTL_DIR_MSK BIT(USB_DMA_CNTL_DIR_POS) + +#define USB_DMA_CNTL_MODE_POS 2U +#define USB_DMA_CNTL_MODE_MSK BIT(USB_DMA_CNTL_MODE_POS) + +#define USB_DMA_CNTL_IE_POS 3U +#define USB_DMA_CNTL_IE_MSK BIT(USB_DMA_CNTL_IE_POS) + +#define USB_DMA_CNTL_EP_POSS 4U +#define USB_DMA_CNTL_EP_POSE 7U +#define USB_DMA_CNTL_EP_MSK BITS(USB_DMA_CNTL_EP_POSS,USB_DMA_CNTL_EP_POSE) + +#define USB_DMA_CNTL_ERR_POS 8U +#define USB_DMA_CNTL_ERR_MSK BIT(USB_DMA_CNTL_ERR_POS) + +#define USB_DMA_CNTL_BRSTM_POSS 9U +#define USB_DMA_CNTL_BRSTM_POSE 10U +#define USB_DMA_CNTL_BRSTM_MSK BITS(USB_DMA_CNTL_BRSTM_POSS,USB_DMA_CNTL_BRSTM_POSE) + +typedef struct{ + __IO uint32_t DMA_CNTL; + __IO uint32_t DMA_ADDR; + __IO uint32_t DMA_COUNT; + uint32_t rsv; +} USB_DMA_CHx_Typedef; + +/****************** Bit definition for USB_RXDPKTBUFDIS register ************************/ + +#define USB_RXDPKTBUFDIS_EP7_POS 7U +#define USB_RXDPKTBUFDIS_EP7_MSK BIT(USB_RXDPKTBUFDIS_EP7_POS) + +#define USB_RXDPKTBUFDIS_EP6_POS 6U +#define USB_RXDPKTBUFDIS_EP6_MSK BIT(USB_RXDPKTBUFDIS_EP6_POS) + +#define USB_RXDPKTBUFDIS_EP5_POS 5U +#define USB_RXDPKTBUFDIS_EP5_MSK BIT(USB_RXDPKTBUFDIS_EP5_POS) + +#define USB_RXDPKTBUFDIS_EP4_POS 4U +#define USB_RXDPKTBUFDIS_EP4_MSK BIT(USB_RXDPKTBUFDIS_EP4_POS) + +#define USB_RXDPKTBUFDIS_EP3_POS 3U +#define USB_RXDPKTBUFDIS_EP3_MSK BIT(USB_RXDPKTBUFDIS_EP3_POS) + +#define USB_RXDPKTBUFDIS_EP2_POS 2U +#define USB_RXDPKTBUFDIS_EP2_MSK BIT(USB_RXDPKTBUFDIS_EP2_POS) + +#define USB_RXDPKTBUFDIS_EP1_POS 1U +#define USB_RXDPKTBUFDIS_EP1_MSK BIT(USB_RXDPKTBUFDIS_EP1_POS) + +/****************** Bit definition for USB_TXDPKTBUFDIS register ************************/ + +#define USB_TXDPKTBUFDIS_EP7_POS 7U +#define USB_TXDPKTBUFDIS_EP7_MSK BIT(USB_TXDPKTBUFDIS_EP7_POS) + +#define USB_TXDPKTBUFDIS_EP6_POS 6U +#define USB_TXDPKTBUFDIS_EP6_MSK BIT(USB_TXDPKTBUFDIS_EP6_POS) + +#define USB_TXDPKTBUFDIS_EP5_POS 5U +#define USB_TXDPKTBUFDIS_EP5_MSK BIT(USB_TXDPKTBUFDIS_EP5_POS) + +#define USB_TXDPKTBUFDIS_EP4_POS 4U +#define USB_TXDPKTBUFDIS_EP4_MSK BIT(USB_TXDPKTBUFDIS_EP4_POS) + +#define USB_TXDPKTBUFDIS_EP3_POS 3U +#define USB_TXDPKTBUFDIS_EP3_MSK BIT(USB_TXDPKTBUFDIS_EP3_POS) + +#define USB_TXDPKTBUFDIS_EP2_POS 2U +#define USB_TXDPKTBUFDIS_EP2_MSK BIT(USB_TXDPKTBUFDIS_EP2_POS) + +#define USB_TXDPKTBUFDIS_EP1_POS 1U +#define USB_TXDPKTBUFDIS_EP1_MSK BIT(USB_TXDPKTBUFDIS_EP1_POS) + +/****************** Bit definition for USB_LPM_ATTR register ************************/ + +#define USB_LPM_ATTR_ENDPNT_POSS 12U +#define USB_LPM_ATTR_ENDPNT_POSE 15U +#define USB_LPM_ATTR_ENDPNT_MSK BITS(USB_LPM_ATTR_ENDPNT_POSS,USB_LPM_ATTR_ENDPNT_POSE) + +#define USB_LPM_ATTR_RMTWAK_POS 8U +#define USB_LPM_ATTR_RMTWAK_MSK BIT(USB_LPM_ATTR_RMTWAK_POS) + +#define USB_LPM_ATTR_HIRD_POSS 4U +#define USB_LPM_ATTR_HIRD_POSE 7U +#define USB_LPM_ATTR_HIRD_MSK BITS(USB_LPM_ATTR_HIRD_POSS,USB_LPM_ATTR_HIRD_POSE) + +#define USB_LPM_ATTR_LINKSTATE_POSS 0U +#define USB_LPM_ATTR_LINKSTATE_POSE 3U +#define USB_LPM_ATTR_LINKSTATE_MSK BITS(USB_LPM_ATTR_LINKSTATE_POSS,USB_LPM_ATTR_LINKSTATE_POSE) + +/****************** Bit definition for USB_LPM_CNTRL register ************************/ + +#define USB_LPM_CNTRL_LPMNACK_POS 4U +#define USB_LPM_CNTRL_LPMNACK_MSK BIT(USB_LPM_CNTRL_LPMNACK_POS) + +#define USB_LPM_CNTRL_LPMEN_POSS 2U +#define USB_LPM_CNTRL_LPMEN_POSE 3U +#define USB_LPM_CNTRL_LPMEN_MSK BITS(USB_LPM_CNTRL_LPMEN_POSS,USB_LPM_CNTRL_LPMEN_POSE) + +#define USB_LPM_CNTRL_LPMRES_POS 1U +#define USB_LPM_CNTRL_LPMRES_MSK BIT(USB_LPM_CNTRL_LPMRES_POS) + +#define USB_LPM_CNTRL_LPMXMT_POS 0U +#define USB_LPM_CNTRL_LPMXMT_MSK BIT(USB_LPM_CNTRL_LPMXMT_POS) + +/****************** Bit definition for USB_LPM_INTREN register ************************/ + +#define USB_LPM_INTREN_LPMERREN_POS 5U +#define USB_LPM_INTREN_LPMERREN_MSK BIT(USB_LPM_INTREN_LPMERREN_POS) + +#define USB_LPM_INTREN_LPMRESEN_POS 4U +#define USB_LPM_INTREN_LPMRESEN_MSK BIT(USB_LPM_INTREN_LPMRESEN_POS) + +#define USB_LPM_INTREN_LPMNCEN_POS 3U +#define USB_LPM_INTREN_LPMNCEN_MSK BIT(USB_LPM_INTREN_LPMNCEN_POS) + +#define USB_LPM_INTREN_LPMACKEN_POS 2U +#define USB_LPM_INTREN_LPMACKEN_MSK BIT(USB_LPM_INTREN_LPMACKEN_POS) + +#define USB_LPM_INTREN_LPMNYEN_POS 1U +#define USB_LPM_INTREN_LPMNYEN_MSK BIT(USB_LPM_INTREN_LPMNYEN_POS) + +#define USB_LPM_INTREN_LPMSTEN_POS 0U +#define USB_LPM_INTREN_LPMSTEN_MSK BIT(USB_LPM_INTREN_LPMSTEN_POS) + +/****************** Bit definition for USB_LPM_INTR register ************************/ + +#define USB_LPM_INTR_LPMERR_POS 5U +#define USB_LPM_INTR_LPMERR_MSK BIT(USB_LPM_INTR_LPMERR_POS) + +#define USB_LPM_INTR_LPMRES_POS 4U +#define USB_LPM_INTR_LPMRES_MSK BIT(USB_LPM_INTR_LPMRES_POS) + +#define USB_LPM_INTR_LPMNC_POS 3U +#define USB_LPM_INTR_LPMNC_MSK BIT(USB_LPM_INTR_LPMNC_POS) + +#define USB_LPM_INTR_LPMACK_POS 2U +#define USB_LPM_INTR_LPMACK_MSK BIT(USB_LPM_INTR_LPMACK_POS) + +#define USB_LPM_INTR_LPMNY_POS 1U +#define USB_LPM_INTR_LPMNY_MSK BIT(USB_LPM_INTR_LPMNY_POS) + +#define USB_LPM_INTR_LPMST_POS 0U +#define USB_LPM_INTR_LPMST_MSK BIT(USB_LPM_INTR_LPMST_POS) + +/****************** Bit definition for USB_LPM_FADDR register ************************/ + +#define USB_LPM_FADDR_LPMFADDR_POSS 0U +#define USB_LPM_FADDR_LPMFADDR_POSE 6U +#define USB_LPM_FADDR_LPMFADDR_MSK BITS(USB_LPM_FADDR_LPMFADDR_POSS,USB_LPM_FADDR_LPMFADDR_POSE) + +typedef struct { + __IO uint8_t FADDR; + __IO uint8_t POWER; + __I uint8_t TXIS; + uint8_t rsv0; + __I uint8_t RXIS; + uint8_t rsv1; + __IO uint8_t TXIE; + uint8_t rsv2; + __IO uint8_t RXIE; + uint8_t rsv3; + __I uint8_t USBIS; + __IO uint8_t USBIE; + __I uint16_t FRAME; + __IO uint8_t INDEX; + __IO uint8_t TEST; + uint32_t rsv4[4]; + __IO USB_FIFO_Typedef FIFO[8]; + uint32_t rsv5[8]; + __IO uint8_t DEVCTL; + uint8_t rsv6; + __IO uint8_t TXFIFOSIZE; + __IO uint8_t RXFIFOSIZE; + __IO uint16_t TXFIFOADD; + __IO uint16_t RXFIFOADD; + uint8_t rsv7[18]; + __IO uint8_t LINKINFO; + __IO uint8_t VPLEN; + __IO uint8_t HS_EOF1; + __IO uint8_t FS_EOF1; + __IO uint8_t LS_EOF1; + uint8_t rsv8; + USB_ADDR_Typedef ADDR[8]; + uint32_t rsv9[16]; + uint8_t rsv10[2]; + __IO uint8_t CSR0L; + __IO uint8_t CSR0H; + uint8_t rsv11[4]; + __I uint8_t COUNT0; + uint8_t rsv12; + __IO uint8_t TYPE0; + __IO uint8_t NACK; + uint8_t rsv13[3]; + __I uint8_t CONFIG0; + USB_CSRx_Typedef CSR[7]; + uint32_t rsv14[32]; + __IO uint8_t DMA_INTR; + uint8_t rsv15[3]; + USB_DMA_CHx_Typedef DMA_CH[8]; + uint32_t rsv16[32]; + __IO uint32_t EP_RQPKTCOUNT[7]; + uint32_t rsv17[8]; + __IO uint16_t RXDPKTBUFDIS; + __IO uint16_t TXDPKTBUFDIS; + uint32_t rsv18[7]; + __IO uint16_t LPM_ATTR; + __IO uint8_t LPM_CNTRL; + __IO uint8_t LPM_INTREN; + __IO uint8_t LPM_INTR; + __IO uint8_t LPM_FADDR; +} USB_TypeDef; + +/****************** Bit definition for DBGC_IDCODE register ************************/ + +#define DBGC_IDCODE_REV_ID_POSS 16U +#define DBGC_IDCODE_REV_ID_POSE 31U +#define DBGC_IDCODE_REV_ID_MSK BITS(DBGC_IDCODE_REV_ID_POSS,DBGC_IDCODE_REV_ID_POSE) + +#define DBGC_IDCODE_CORE_ID_POSS 12U +#define DBGC_IDCODE_CORE_ID_POSE 15U +#define DBGC_IDCODE_CORE_ID_MSK BITS(DBGC_IDCODE_CORE_ID_POSS,DBGC_IDCODE_CORE_ID_POSE) + +#define DBGC_IDCODE_DEV_ID_POSS 0U +#define DBGC_IDCODE_DEV_ID_POSE 11U +#define DBGC_IDCODE_DEV_ID_MSK BITS(DBGC_IDCODE_DEV_ID_POSS,DBGC_IDCODE_DEV_ID_POSE) + +/****************** Bit definition for DBGC_CR register ************************/ + +#define DBGC_CR_DBG_STANDBY_POS 3U +#define DBGC_CR_DBG_STANDBY_MSK BIT(DBGC_CR_DBG_STANDBY_POS) + +#define DBGC_CR_DBG_STOP2_POS 2U +#define DBGC_CR_DBG_STOP2_MSK BIT(DBGC_CR_DBG_STOP2_POS) + +#define DBGC_CR_DBG_STOP1_POS 1U +#define DBGC_CR_DBG_STOP1_MSK BIT(DBGC_CR_DBG_STOP1_POS) + +#define DBGC_CR_DBG_SLEEP_POS 0U +#define DBGC_CR_DBG_SLEEP_MSK BIT(DBGC_CR_DBG_SLEEP_POS) + +/****************** Bit definition for DBGC_APB1FZ register ************************/ + +#define DBGC_APB1FZ_CAN_STOP_POS 12U +#define DBGC_APB1FZ_CAN_STOP_MSK BIT(DBGC_APB1FZ_CAN_STOP_POS) + +#define DBGC_APB1FZ_I2C1_SMBUS_TO_POS 9U +#define DBGC_APB1FZ_I2C1_SMBUS_TO_MSK BIT(DBGC_APB1FZ_I2C1_SMBUS_TO_POS) + +#define DBGC_APB1FZ_I2C0_SMBUS_TO_POS 8U +#define DBGC_APB1FZ_I2C0_SMBUS_TO_MSK BIT(DBGC_APB1FZ_I2C0_SMBUS_TO_POS) + +#define DBGC_APB1FZ_TIM7_STOP_POS 7U +#define DBGC_APB1FZ_TIM7_STOP_MSK BIT(DBGC_APB1FZ_TIM7_STOP_POS) + +#define DBGC_APB1FZ_TIM6_STOP_POS 6U +#define DBGC_APB1FZ_TIM6_STOP_MSK BIT(DBGC_APB1FZ_TIM6_STOP_POS) + +#define DBGC_APB1FZ_TIM5_STOP_POS 5U +#define DBGC_APB1FZ_TIM5_STOP_MSK BIT(DBGC_APB1FZ_TIM5_STOP_POS) + +#define DBGC_APB1FZ_TIM4_STOP_POS 4U +#define DBGC_APB1FZ_TIM4_STOP_MSK BIT(DBGC_APB1FZ_TIM4_STOP_POS) + +#define DBGC_APB1FZ_TIM3_STOP_POS 3U +#define DBGC_APB1FZ_TIM3_STOP_MSK BIT(DBGC_APB1FZ_TIM3_STOP_POS) + +#define DBGC_APB1FZ_TIM2_STOP_POS 2U +#define DBGC_APB1FZ_TIM2_STOP_MSK BIT(DBGC_APB1FZ_TIM2_STOP_POS) + +#define DBGC_APB1FZ_TIM1_STOP_POS 1U +#define DBGC_APB1FZ_TIM1_STOP_MSK BIT(DBGC_APB1FZ_TIM1_STOP_POS) + +#define DBGC_APB1FZ_TIM0_STOP_POS 0U +#define DBGC_APB1FZ_TIM0_STOP_MSK BIT(DBGC_APB1FZ_TIM0_STOP_POS) + +/****************** Bit definition for DBGC_APB2FZ register ************************/ + +#define DBGC_APB2FZ_RTC_STOP_POS 10U +#define DBGC_APB2FZ_RTC_STOP_MSK BIT(DBGC_APB2FZ_RTC_STOP_POS) + +#define DBGC_APB2FZ_WWDT_STOP_POS 9U +#define DBGC_APB2FZ_WWDT_STOP_MSK BIT(DBGC_APB2FZ_WWDT_STOP_POS) + +#define DBGC_APB2FZ_IWDT_STOP_POS 8U +#define DBGC_APB2FZ_IWDT_STOP_MSK BIT(DBGC_APB2FZ_IWDT_STOP_POS) + +#define DBGC_APB2FZ_LPTIM0_STOP_POS 0U +#define DBGC_APB2FZ_LPTIM0_STOP_MSK BIT(DBGC_APB2FZ_LPTIM0_STOP_POS) + +typedef struct +{ + __I uint32_t IDCODE; + __IO uint32_t CR; + __IO uint32_t APB1FZ; + __IO uint32_t APB2FZ; +} DBGC_TypeDef; + +/****************** Bit definition for DAC_CON register ************************/ + +#define DAC_CON_RCYCLSEL_POSS 20U +#define DAC_CON_RCYCLSEL_POSE 21U +#define DAC_CON_RCYCLSEL_MSK BITS(DAC_CON_RCYCLSEL_POSS,DAC_CON_RCYCLSEL_POSE) + +#define DAC_CON_PRES_POSS 16U +#define DAC_CON_PRES_POSE 18U +#define DAC_CON_PRES_MSK BITS(DAC_CON_PRES_POSS,DAC_CON_PRES_POSE) + +#define DAC_CON_CH0PRESRST_POS 7U +#define DAC_CON_CH0PRESRST_MSK BIT(DAC_CON_CH0PRESRST_POS) + +#define DAC_CON_OUTENPIS_POS 6U +#define DAC_CON_OUTENPIS_MSK BIT(DAC_CON_OUTENPIS_POS) + +#define DAC_CON_OUTMD_POSS 4U +#define DAC_CON_OUTMD_POSE 5U +#define DAC_CON_OUTMD_MSK BITS(DAC_CON_OUTMD_POSS,DAC_CON_OUTMD_POSE) + +#define DAC_CON_CONVMD_POSS 2U +#define DAC_CON_CONVMD_POSE 3U +#define DAC_CON_CONVMD_MSK BITS(DAC_CON_CONVMD_POSS,DAC_CON_CONVMD_POSE) + +#define DAC_CON_SINEMD_POS 1U +#define DAC_CON_SINEMD_MSK BIT(DAC_CON_SINEMD_POS) + +#define DAC_CON_DIFEN_POS 0U +#define DAC_CON_DIFEN_MSK BIT(DAC_CON_DIFEN_POS) + +/****************** Bit definition for DAC_STAT register ************************/ + +#define DAC_STAT_CH1BSY_POS 1U +#define DAC_STAT_CH1BSY_MSK BIT(DAC_STAT_CH1BSY_POS) + +#define DAC_STAT_CH0BSY_POS 0U +#define DAC_STAT_CH0BSY_MSK BIT(DAC_STAT_CH0BSY_POS) + +/****************** Bit definition for DAC_CH0CTRL register ************************/ + +#define DAC_CH0CTRL_PISSEL_POSS 4U +#define DAC_CH0CTRL_PISSEL_POSE 7U +#define DAC_CH0CTRL_PISSEL_MSK BITS(DAC_CH0CTRL_PISSEL_POSS,DAC_CH0CTRL_PISSEL_POSE) + +#define DAC_CH0CTRL_PISEN_POS 2U +#define DAC_CH0CTRL_PISEN_MSK BIT(DAC_CH0CTRL_PISEN_POS) + +#define DAC_CH0CTRL_RCYCLEN_POS 1U +#define DAC_CH0CTRL_RCYCLEN_MSK BIT(DAC_CH0CTRL_RCYCLEN_POS) + +#define DAC_CH0CTRL_EN_POS 0U +#define DAC_CH0CTRL_EN_MSK BIT(DAC_CH0CTRL_EN_POS) + +/****************** Bit definition for DAC_CH1CTRL register ************************/ + +#define DAC_CH1CTRL_PISSEL_POSS 4U +#define DAC_CH1CTRL_PISSEL_POSE 7U +#define DAC_CH1CTRL_PISSEL_MSK BITS(DAC_CH1CTRL_PISSEL_POSS,DAC_CH1CTRL_PISSEL_POSE) + +#define DAC_CH1CTRL_PISEN_POS 2U +#define DAC_CH1CTRL_PISEN_MSK BIT(DAC_CH1CTRL_PISEN_POS) + +#define DAC_CH1CTRL_RCYCLEN_POS 1U +#define DAC_CH1CTRL_RCYCLEN_MSK BIT(DAC_CH1CTRL_RCYCLEN_POS) + +#define DAC_CH1CTRL_EN_POS 0U +#define DAC_CH1CTRL_EN_MSK BIT(DAC_CH1CTRL_EN_POS) + +/****************** Bit definition for DAC_IES register ************************/ + +#define DAC_IES_CH1UDF_POS 5U +#define DAC_IES_CH1UDF_MSK BIT(DAC_IES_CH1UDF_POS) + +#define DAC_IES_CH0UDF_POS 4U +#define DAC_IES_CH0UDF_MSK BIT(DAC_IES_CH0UDF_POS) + +#define DAC_IES_CH1_POS 1U +#define DAC_IES_CH1_MSK BIT(DAC_IES_CH1_POS) + +#define DAC_IES_CH0_POS 0U +#define DAC_IES_CH0_MSK BIT(DAC_IES_CH0_POS) + +/****************** Bit definition for DAC_IEC register ************************/ + +#define DAC_IEC_CH1UDF_POS 5U +#define DAC_IEC_CH1UDF_MSK BIT(DAC_IEC_CH1UDF_POS) + +#define DAC_IEC_CH0UDF_POS 4U +#define DAC_IEC_CH0UDF_MSK BIT(DAC_IEC_CH0UDF_POS) + +#define DAC_IEC_CH1_POS 1U +#define DAC_IEC_CH1_MSK BIT(DAC_IEC_CH1_POS) + +#define DAC_IEC_CH0_POS 0U +#define DAC_IEC_CH0_MSK BIT(DAC_IEC_CH0_POS) + +/****************** Bit definition for DAC_IEV register ************************/ + +#define DAC_IEV_CH1UDF_POS 5U +#define DAC_IEV_CH1UDF_MSK BIT(DAC_IEV_CH1UDF_POS) + +#define DAC_IEV_CH0UDF_POS 4U +#define DAC_IEV_CH0UDF_MSK BIT(DAC_IEV_CH0UDF_POS) + +#define DAC_IEV_CH1_POS 1U +#define DAC_IEV_CH1_MSK BIT(DAC_IEV_CH1_POS) + +#define DAC_IEV_CH0_POS 0U +#define DAC_IEV_CH0_MSK BIT(DAC_IEV_CH0_POS) + +/****************** Bit definition for DAC_RIF register ************************/ + +#define DAC_RIF_CH1UDF_POS 5U +#define DAC_RIF_CH1UDF_MSK BIT(DAC_RIF_CH1UDF_POS) + +#define DAC_RIF_CH0UDF_POS 4U +#define DAC_RIF_CH0UDF_MSK BIT(DAC_RIF_CH0UDF_POS) + +#define DAC_RIF_CH1_POS 1U +#define DAC_RIF_CH1_MSK BIT(DAC_RIF_CH1_POS) + +#define DAC_RIF_CH0_POS 0U +#define DAC_RIF_CH0_MSK BIT(DAC_RIF_CH0_POS) + +/****************** Bit definition for DAC_IFM register ************************/ + +#define DAC_IFM_CH1UDF_POS 5U +#define DAC_IFM_CH1UDF_MSK BIT(DAC_IFM_CH1UDF_POS) + +#define DAC_IFM_CH0UDF_POS 4U +#define DAC_IFM_CH0UDF_MSK BIT(DAC_IFM_CH0UDF_POS) + +#define DAC_IFM_CH1_POS 1U +#define DAC_IFM_CH1_MSK BIT(DAC_IFM_CH1_POS) + +#define DAC_IFM_CH0_POS 0U +#define DAC_IFM_CH0_MSK BIT(DAC_IFM_CH0_POS) + +/****************** Bit definition for DAC_IFC register ************************/ + +#define DAC_IFC_CH1UDF_POS 5U +#define DAC_IFC_CH1UDF_MSK BIT(DAC_IFC_CH1UDF_POS) + +#define DAC_IFC_CH0UDF_POS 4U +#define DAC_IFC_CH0UDF_MSK BIT(DAC_IFC_CH0UDF_POS) + +#define DAC_IFC_CH1_POS 1U +#define DAC_IFC_CH1_MSK BIT(DAC_IFC_CH1_POS) + +#define DAC_IFC_CH0_POS 0U +#define DAC_IFC_CH0_MSK BIT(DAC_IFC_CH0_POS) + +/****************** Bit definition for DAC_CH0DATA register ************************/ + +#define DAC_CH0DATA_VAL_POSS 0U +#define DAC_CH0DATA_VAL_POSE 11U +#define DAC_CH0DATA_VAL_MSK BITS(DAC_CH0DATA_VAL_POSS,DAC_CH0DATA_VAL_POSE) + +/****************** Bit definition for DAC_CH1DATA register ************************/ + +#define DAC_CH1DATA_VAL_POSS 0U +#define DAC_CH1DATA_VAL_POSE 11U +#define DAC_CH1DATA_VAL_MSK BITS(DAC_CH1DATA_VAL_POSS,DAC_CH1DATA_VAL_POSE) + +/****************** Bit definition for DAC_COMBDATA register ************************/ + +#define DAC_COMBDATA_CH1VAL_POSS 16U +#define DAC_COMBDATA_CH1VAL_POSE 27U +#define DAC_COMBDATA_CH1VAL_MSK BITS(DAC_COMBDATA_CH1VAL_POSS,DAC_COMBDATA_CH1VAL_POSE) + +#define DAC_COMBDATA_CH0VAL_POSS 0U +#define DAC_COMBDATA_CH0VAL_POSE 11U +#define DAC_COMBDATA_CH0VAL_MSK BITS(DAC_COMBDATA_CH0VAL_POSS,DAC_COMBDATA_CH0VAL_POSE) + +/****************** Bit definition for DAC_CAL register ************************/ + +#define DAC_CAL_SELF_CALEN_POS 31U +#define DAC_CAL_SELF_CALEN_MSK BIT(DAC_CAL_SELF_CALEN_POS) + +typedef struct +{ + __IO uint32_t CON; + __I uint32_t STAT; + __IO uint32_t CH0CTRL; + __IO uint32_t CH1CTRL; + __O uint32_t IES; + __O uint32_t IEC; + __I uint32_t IEV; + __I uint32_t RIF; + __I uint32_t IFM; + __O uint32_t IFC; + __IO uint32_t CH0DATA; + __IO uint32_t CH1DATA; + __O uint32_t COMBDATA; + __IO uint32_t CAL; +} DAC_TypeDef; + + +/* Base addresses */ +#define SRAM_BASE (0x20000000UL) +#define APB1_BASE (0x40000000UL) +#define APB2_BASE (0x40040000UL) +#define AHB_BASE (0x40080000UL) +#define EBI_BASE (0x60000000UL) +#define EBI_R_BASE (0xA0000000UL) + + +/* APB1 peripherals Base Address */ +#define AD16C4T0_BASE (APB1_BASE + 0x0000) +#define AD16C4T1_BASE (APB1_BASE + 0x0400) +#define GP32C4T0_BASE (APB1_BASE + 0x0800) +#define GP32C4T1_BASE (APB1_BASE + 0x0C00) +#define BS16T0_BASE (APB1_BASE + 0x1000) +#define BS16T1_BASE (APB1_BASE + 0x1400) +#define GP16C4T0_BASE (APB1_BASE + 0x1800) +#define GP16C4T1_BASE (APB1_BASE + 0x1C00) +#define UART0_BASE (APB1_BASE + 0x4000) +#define UART1_BASE (APB1_BASE + 0x4400) +#define UART2_BASE (APB1_BASE + 0x4800) +#define UART3_BASE (APB1_BASE + 0x4C00) +#define UART4_BASE (APB1_BASE + 0x5000) +#define UART5_BASE (APB1_BASE + 0x5400) +#define SPI0_I2S0_BASE (APB1_BASE + 0x6000) +#define SPI1_I2S1_BASE (APB1_BASE + 0x6400) +#define SPI2_I2S2_BASE (APB1_BASE + 0x6800) +#define I2C0_BASE (APB1_BASE + 0x8000) +#define I2C1_BASE (APB1_BASE + 0x8400) +#define CAN0_BASE (APB1_BASE + 0xB000) +#define DMA0_BASE (APB1_BASE + 0xC000) +#define QSPI_BASE (APB1_BASE + 0xD400) + +/* APB2 peripherals Base Address */ +#define ADC0_BASE (APB2_BASE + 0x2000) +#define ADC1_BASE (APB2_BASE + 0x2400) +#define ACMP0_BASE (APB2_BASE + 0x3000) +#define ACMP1_BASE (APB2_BASE + 0x3400) +#define ACMP2_BASE (APB2_BASE + 0x3800) +#define DAC0_BASE (APB2_BASE + 0x5000) +#define WWDT_BASE (APB2_BASE + 0x6000) +#define IWDT_BASE (APB2_BASE + 0x6400) +#define LCD_BASE (APB2_BASE + 0x7000) +#define BKPC_BASE (APB2_BASE + 0x8000) +#define RTC_BASE (APB2_BASE + 0x8400) +#define TSENSE_BASE (APB2_BASE + 0x8800) +#define DBGC_BASE (APB2_BASE + 0xA000) + +/* AHB peripherals Base Address */ +#define SYSTEM_BASE (AHB_BASE + 0x0000) +#define CMU_BASE (AHB_BASE + 0x0400) +#define RMU_BASE (AHB_BASE + 0x0800) +#define PMU_BASE (AHB_BASE + 0x0C00) +#define MSC_BASE (AHB_BASE + 0x1000) +#define GPIOA_BASE (AHB_BASE + 0x4000) +#define GPIOB_BASE (AHB_BASE + 0x4040) +#define GPIOC_BASE (AHB_BASE + 0x4080) +#define GPIOD_BASE (AHB_BASE + 0x40C0) +#define GPIOE_BASE (AHB_BASE + 0x4100) +#define GPIOF_BASE (AHB_BASE + 0x4140) +#define GPIOG_BASE (AHB_BASE + 0x4180) +#define GPIOH_BASE (AHB_BASE + 0x41C0) +#define EXTI_BASE (AHB_BASE + 0x4300) +#define CRC_BASE (AHB_BASE + 0x5000) +#define CALC_BASE (AHB_BASE + 0x5400) +#define CRYPT_BASE (AHB_BASE + 0x5800) +#define TRNG_BASE (AHB_BASE + 0x5C00) +#define PIS_BASE (AHB_BASE + 0x6000) +#define USB0_BASE (AHB_BASE + 0x6400) + +/* EBI Base Address */ +#define EBI_BANK1 (EBI_BASE) +#define EBI_BANK1_1 (EBI_BANK1) +#define EBI_BANK1_2 (EBI_BANK1 + 0x04000000UL) +#define EBI_BANK1_3 (EBI_BANK1 + 0x08000000UL) +#define EBI_BANK1_4 (EBI_BANK1 + 0x0C000000UL) +#define EBI_BANK2 (EBI_BASE + 0x10000000UL) +#define EBI_BANK3 (EBI_BASE + 0x20000000UL) +#define EBI_BANK1_R_BASE (EBI_R_BASE + 0x0000) +#define EBI_BANK1E_R_BASE (EBI_R_BASE + 0x0104) +#define EBI_BANK2_3_R_BASE (EBI_R_BASE + 0x0060) +#define EBI_BANK1_LCD_R_BASE (EBI_R_BASE + 0X0200) + +/* APB1 peripherals */ +#define AD16C4T0 ((TIMER_TypeDef *)AD16C4T0_BASE) +#define AD16C4T1 ((TIMER_TypeDef *)AD16C4T1_BASE) +#define GP32C4T0 ((TIMER_TypeDef *)GP32C4T0_BASE) +#define GP32C4T1 ((TIMER_TypeDef *)GP32C4T1_BASE) +#define BS16T0 ((TIMER_TypeDef *)BS16T0_BASE) +#define BS16T1 ((TIMER_TypeDef *)BS16T1_BASE) +#define GP16C4T0 ((TIMER_TypeDef *)GP16C4T0_BASE) +#define GP16C4T1 ((TIMER_TypeDef *)GP16C4T1_BASE) +#define UART0 ((UART_TypeDef *)UART0_BASE) +#define UART1 ((UART_TypeDef *)UART1_BASE) +#define UART2 ((UART_TypeDef *)UART2_BASE) +#define UART3 ((UART_TypeDef *)UART3_BASE) +#define UART4 ((UART_TypeDef *)UART4_BASE) +#define UART5 ((UART_TypeDef *)UART5_BASE) +#define SPI0 ((SPI_I2S_TypeDef *)SPI0_I2S0_BASE) +#define SPI1 ((SPI_I2S_TypeDef *)SPI1_I2S1_BASE) +#define SPI2 ((SPI_I2S_TypeDef *)SPI2_I2S2_BASE) +#define I2S0 ((SPI_I2S_TypeDef *)SPI0_I2S0_BASE) +#define I2S1 ((SPI_I2S_TypeDef *)SPI1_I2S1_BASE) +#define I2S2 ((SPI_I2S_TypeDef *)SPI2_I2S2_BASE) +#define I2C0 ((I2C_TypeDef *)I2C0_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define CAN0 ((CAN_TypeDef *)CAN0_BASE) +#define DMA0 ((DMA_TypeDef *)DMA0_BASE) +#define QSPI ((QSPI_TypeDef *)QSPI_BASE) + +/* APB2 peripherals */ +#define ADC0 ((ADC_TypeDef *)ADC0_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ACMP0 ((ACMP_TypeDef *)ACMP0_BASE) +#define ACMP1 ((ACMP_TypeDef *)ACMP1_BASE) +#define ACMP2 ((ACMP_TypeDef *)ACMP2_BASE) +#define DAC0 ((DAC_TypeDef *)DAC0_BASE) +#define WWDT ((WWDT_TypeDef *)WWDT_BASE) +#define IWDT ((IWDT_TypeDef *)IWDT_BASE) +#define BKPC ((BKPC_TypeDef *)BKPC_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define TSENSE ((TSENSE_TypeDef *)TSENSE_BASE) +#define DBGC ((DBGC_TypeDef *)DBGC_BASE) + +/* AHB peripherals */ +#define SYSCFG ((SYSCFG_TypeDef *)SYSTEM_BASE) +#define CMU ((CMU_TypeDef *)CMU_BASE) +#define RMU ((RMU_TypeDef *)RMU_BASE) +#define PMU ((PMU_TypeDef *)PMU_BASE) +#define MSC ((MSC_TypeDef *)MSC_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *)GPIOH_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define CALC ((CALC_TypeDef *)CALC_BASE) +#define CRYPT ((CRYPT_TypeDef *)CRYPT_BASE) +#define TRNG ((TRNG_TypeDef *)TRNG_BASE) +#define PIS ((PIS_TypeDef *)PIS_BASE) +#define USB0 ((USB_TypeDef *)USB0_BASE) + +/* EBI peripherals */ +#define EBI_Bank1 ((EBI_Bank1_TypeDef *)EBI_BANK1_R_BASE) +#define EBI_Bank1E ((EBI_Bank1E_TypeDef *)EBI_BANK1E_R_BASE) +#define EBI_Bank2_3 ((EBI_Bank2_3_TypeDef *)EBI_BANK2_3_R_BASE) +#define EBI_Bank1_LCD ((EBI_Bank1_LCD_TypeDef *)EBI_BANK1_LCD_R_BASE) + +#endif diff --git a/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/ReleaseNote.html b/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/ReleaseNote.html new file mode 100644 index 00000000..8613dfeb --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/ReleaseNote.html @@ -0,0 +1,14 @@ + + + + +ReleaseNote +

ES32F36xx Device Release Note

+

V1.00 2019-12-16

+
    +
  1. First release
    2. + +
+

 

+ + \ No newline at end of file diff --git a/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/ReleaseNote.md b/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/ReleaseNote.md new file mode 100644 index 00000000..ce25a4bf --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/ReleaseNote.md @@ -0,0 +1,6 @@ +# ES32F36xx Device Release Note + +## V1.00 2019-12-16 + +1. First release + diff --git a/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/SConscript b/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/SConscript new file mode 100644 index 00000000..c1125e18 --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/SConscript @@ -0,0 +1,22 @@ +from building import * +import esconfig +#1.生成group_startup（对应project里面的startup） +cwd = GetCurrentDir() + +#add *.s file +if esconfig.CROSS_TOOL == 'gcc': + stup = Glob('Startup/gcc/*.s') +elif esconfig.CROSS_TOOL == 'keil': + stup = Glob('Startup/keil/*.s') +elif esconfig.CROSS_TOOL == 'iar': + stup = Glob('Startup/iar/*.s') + + +#add include path,其实startup没有对应的.h文件，但是这里的操作是把内核相关的.h文件以及芯片寄存器的.h文件以及芯片寄存器的.h文件 +#include在魔法棒c/c++里面的include paths里 +include_path = [cwd + '..\..\..\..\Include'] +include_path += [cwd + '/Include', cwd + '/Include/ES32W3120'] +group_startup = DefineGroup('startup', stup, depend = [''], CPPPATH = include_path) + +#返回group_startup +Return('group_startup') diff --git a/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.s b/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.s new file mode 100644 index 00000000..68d648f1 --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/Startup/gcc/startup_es32f36xx.s @@ -0,0 +1,502 @@ +/** + ****************************************************************************** + * @file startup_es32f36xx.s + * @author AE Team + * @brief ES32F36xx devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + * @note + * Change Logs: + * Date Author Notes + * 23 Jan 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + + .syntax unified + .arch armv7-m + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + + ldr r0, =0x55AA6996 + ldr r1, =0x40080000 + str r0, [r1] + + ldr r0, =0x5A962814 + ldr r1, =0x40080100 + str r0, [r1] + ldr r0, =0xE7CB69A5 + str r0, [r1] + + ldr r0, =0x40083C00 + ldr r1, [r0] + ldr r2, =0xffff + and r1, r2 + ldr r2, =0x55AA0000 + orr r1, r2 + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + + mov r0, r0 + mov r0, r0 + + ldr r0, =0x123456 + ldr r1, =0x40080100 + str r0, [r1] + + ldr r0, =0x40080404 + ldr r1, =0x4000000 + str r1, [r0] + + ldr r0, =0x123456 + ldr r1, =0x40080000 + str r0, [r1] + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + bl sys_config + bl adc_config + + bl __libc_init_array + + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack /* 0, load top of stack */ + .word Reset_Handler /* 1, reset handler */ + .word NMI_Handler /* 2, nmi handler */ + .word HardFault_Handler /* 3, hard fault handler */ + .word MemManage_Handler /* 4, MPU Fault Handler */ + .word BusFault_Handler /* 5, Bus Fault Handler */ + .word UsageFault_Handler /* 6, Usage Fault Handler */ + .word 0 /* 7, Reserved */ + .word 0 /* 8, Reserved */ + .word 0 /* 9, Reserved */ + .word 0 /* 10, Reserved */ + .word SVC_Handler /* 11, svcall handler */ + .word DebugMon_Handler /* 12, Debug Monitor Handler */ + .word 0 /* 13, Reserved */ + .word PendSV_Handler /* 14, pendsv handler */ + .word SysTick_Handler /* 15, systick handler */ + .word WWDG_Handler /* 16, irq0 WWDG handler */ + .word IWDG_Handler /* 17, irq1 IWDG handler */ + .word LVD_Handler /* 18, irq2 LVD handler */ + .word RTC_Handler /* 19, irq3 RTC handler */ + .word 0 /* 20, irq4 Reserved */ + .word 0 /* 21, irq5 Reserved */ + .word CMU_Handler /* 22, irq6 CMU handler */ + .word ADC0_Handler /* 23, irq7 ADC0 handler */ + .word CAN0_TX_Handler /* 24, irq8 CAN0_TX handler */ + .word CAN0_RX0_Handler /* 25, irq9 CAN0_RX0 handler */ + .word CAN0_RX1_Handler /* 26, irq10 CAN0_RX1 handler */ + .word CAN0_EXCEPTION_Handler /* 27, irq11 CAN0_EXCEPTION handler */ + .word AD16C4T0_BRK_Handler /* 28, irq12 AD16C4T0_BRK handler */ + .word AD16C4T0_UP_Handler /* 29, irq13 AD16C4T0_UP handler */ + .word AD16C4T0_TRIG_COM_Handler /* 30, irq14 AD16C4T0_TRIG_COM handler */ + .word AD16C4T0_CC_Handler /* 31, irq15 AD16C4T0_CC handler */ + .word AD16C4T1_BRK_Handler /* 32, irq16 AD16C4T1_BRK handler */ + .word AD16C4T1_UP_Handler /* 33, irq17 AD16C4T1_UP handler */ + .word AD16C4T1_TRIG_COM_Handler /* 34, irq18 AD16C4T1_TRIG_COM handler */ + .word AD16C4T1_CC_Handler /* 35, irq19 AD16C4T1_CC handler */ + .word GP32C4T0_Handler /* 36, irq20 GP32C4T0 handler */ + .word GP32C4T1_Handler /* 37, irq21 GP32C4T1 handler */ + .word BS16T0_Handler /* 38, irq22 BS16T0 handler */ + .word BS16T1_Handler /* 39, irq23 BS16T1 handler */ + .word GP16C4T0_Handler /* 40, irq24 GP16C4T0 handler */ + .word GP16C4T1_Handler /* 41, irq25 GP16C4T1 handler */ + .word 0 /* 42, irq26 Reserved */ + .word DAC0_CH0_Handler /* 43, irq27 DAC0_CH0 handler */ + .word I2C0_EV_Handler /* 44, irq28 I2C0_EV handler */ + .word I2C0_ERR_Handler /* 45, irq29 I2C0_ERR handler */ + .word I2C1_EV_Handler /* 46 irq30 I2C1_EV handler */ + .word I2C1_ERR_Handler /* 47, irq31 I2C1_ERR handler */ + .word SPI0_I2S0_Handler /* 48, irq32 SPI0_I2S0 handler */ + .word SPI1_I2S1_Handler /* 49, irq33 SPI1_I2S1 handler */ + .word UART0_Handler /* 50, irq34 UART0 handler */ + .word UART1_Handler /* 51, irq35 UART1 handler */ + .word UART2_Handler /* 52, irq36 UART2 handler */ + .word UART3_Handler /* 53, irq37 UART3 handler */ + .word UART4_Handler /* 54, irq38 UART4 handler */ + .word UART5_Handler /* 55, irq39 UART5 handler */ + .word 0 /* 56, irq40 Reserved */ + .word 0 /* 57, irq41 Reserved */ + .word CRYPT_Handler /* 58, irq42 CRYPT handler */ + .word ACMP0_Handler /* 59, irq43 ACMP0 handler */ + .word ACMP1_Handler /* 60, irq44 ACMP1 handler */ + .word SPI2_I2S2_Handler /* 61, irq45 SPI2_I2S2 handler */ + .word 0 /* 62, irq46 Reserved */ + .word EBI_Handler /* 63, irq47 EBI handler */ + .word TRNG_Handler /* 64, irq48 TRNG handler */ + .word TSENSE_Handler /* 65, irq49 TSENSE handler */ + .word EXTI0_Handler /* 66, irq50 EXTI0 handler */ + .word EXTI1_Handler /* 67, irq51 EXTI1 handler */ + .word EXTI2_Handler /* 68, irq52 EXTI2 handler */ + .word EXTI3_Handler /* 69, irq53 EXTI3 handler */ + .word EXTI4_Handler /* 70, irq54 EXTI4 handler */ + .word EXTI5_Handler /* 71, irq55 EXTI5 handler */ + .word EXTI6_Handler /* 72, irq56 EXTI6 handler */ + .word EXTI7_Handler /* 73, irq57 EXTI7 handler */ + .word EXTI8_Handler /* 74, irq58 EXTI8 handler */ + .word EXTI9_Handler /* 75, irq59 EXTI9 handler */ + .word EXTI10_Handler /* 76, irq60 EXTI10 handler */ + .word EXTI11_Handler /* 77, irq61 EXTI11 handler */ + .word EXTI12_Handler /* 78, irq62 EXTI12 handler */ + .word EXTI13_Handler /* 79, irq63 EXTI13 handler */ + .word EXTI14_Handler /* 80, irq64 EXTI14 handler */ + .word EXTI15_Handler /* 81, irq65 EXTI15 handler */ + .word DMA_Handler /* 82, irq66 DMA handler */ + .word ADC1_Handler /* 83, irq67 ADC1 handler */ + .word DAC0_CH1_Handler /* 84, irq68 DAC0_CH1 handler */ + .word QSPI_Handler /* 85, irq69 QSPI handler */ + .word USB_INT_Handler /* 86, irq70 USB_INT handler */ + .word USB_DMA_Handler /* 87, irq71 USB_DMA handler */ + .word ACMP2_Handler /* 88, irq72 ACMP2 handler */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_Handler + .thumb_set WWDG_Handler,Default_Handler + + .weak IWDG_Handler + .thumb_set IWDG_Handler,Default_Handler + + .weak LVD_Handler + .thumb_set LVD_Handler,Default_Handler + + .weak RTC_Handler + .thumb_set RTC_Handler,Default_Handler + + .weak CMU_Handler + .thumb_set CMU_Handler,Default_Handler + + .weak ADC0_Handler + .thumb_set ADC0_Handler,Default_Handler + + .weak CAN0_TX_Handler + .thumb_set CAN0_TX_Handler,Default_Handler + + .weak CAN0_RX0_Handler + .thumb_set CAN0_RX0_Handler,Default_Handler + + .weak CAN0_RX1_Handler + .thumb_set CAN0_RX1_Handler,Default_Handler + + .weak CAN0_EXCEPTION_Handler + .thumb_set CAN0_EXCEPTION_Handler,Default_Handler + + .weak AD16C4T0_BRK_Handler + .thumb_set AD16C4T0_BRK_Handler,Default_Handler + + .weak AD16C4T0_UP_Handler + .thumb_set AD16C4T0_UP_Handler,Default_Handler + + .weak AD16C4T0_TRIG_COM_Handler + .thumb_set AD16C4T0_TRIG_COM_Handler,Default_Handler + + .weak AD16C4T0_CC_Handler + .thumb_set AD16C4T0_CC_Handler,Default_Handler + + .weak AD16C4T1_BRK_Handler + .thumb_set AD16C4T1_BRK_Handler,Default_Handler + + .weak AD16C4T1_UP_Handler + .thumb_set AD16C4T1_UP_Handler,Default_Handler + + .weak AD16C4T1_TRIG_COM_Handler + .thumb_set AD16C4T1_TRIG_COM_Handler,Default_Handler + + .weak AD16C4T1_CC_Handler + .thumb_set AD16C4T1_CC_Handler,Default_Handler + + .weak GP32C4T0_Handler + .thumb_set GP32C4T0_Handler,Default_Handler + + .weak GP32C4T1_Handler + .thumb_set GP32C4T1_Handler,Default_Handler + + .weak BS16T0_Handler + .thumb_set BS16T0_Handler,Default_Handler + + .weak BS16T1_Handler + .thumb_set BS16T1_Handler,Default_Handler + + .weak GP16C4T0_Handler + .thumb_set GP16C4T0_Handler,Default_Handler + + .weak GP16C4T1_Handler + .thumb_set GP16C4T1_Handler,Default_Handler + + .weak DAC0_CH0_Handler + .thumb_set DAC0_CH0_Handler,Default_Handler + + .weak I2C0_EV_Handler + .thumb_set I2C0_EV_Handler,Default_Handler + + .weak I2C0_ERR_Handler + .thumb_set I2C0_ERR_Handler,Default_Handler + + .weak I2C1_EV_Handler + .thumb_set I2C1_EV_Handler,Default_Handler + + .weak I2C1_ERR_Handler + .thumb_set I2C1_ERR_Handler,Default_Handler + + .weak SPI0_I2S0_Handler + .thumb_set SPI0_I2S0_Handler,Default_Handler + + .weak SPI1_I2S1_Handler + .thumb_set SPI1_I2S1_Handler,Default_Handler + + .weak UART0_Handler + .thumb_set UART0_Handler,Default_Handler + + .weak UART1_Handler + .thumb_set UART1_Handler,Default_Handler + + .weak UART2_Handler + .thumb_set UART2_Handler,Default_Handler + + .weak UART3_Handler + .thumb_set UART3_Handler,Default_Handler + + .weak UART4_Handler + .thumb_set UART4_Handler,Default_Handler + + .weak UART5_Handler + .thumb_set UART5_Handler,Default_Handler + + .weak CRYPT_Handler + .thumb_set CRYPT_Handler,Default_Handler + + .weak ACMP0_Handler + .thumb_set ACMP0_Handler,Default_Handler + + .weak ACMP1_Handler + .thumb_set ACMP1_Handler,Default_Handler + + .weak SPI2_I2S2_Handler + .thumb_set SPI2_I2S2_Handler,Default_Handler + + .weak EBI_Handler + .thumb_set EBI_Handler,Default_Handler + + .weak TRNG_Handler + .thumb_set TRNG_Handler,Default_Handler + + .weak TSENSE_Handler + .thumb_set TSENSE_Handler,Default_Handler + + .weak EXTI0_Handler + .thumb_set EXTI0_Handler,Default_Handler + + .weak EXTI1_Handler + .thumb_set EXTI1_Handler,Default_Handler + + .weak EXTI2_Handler + .thumb_set EXTI2_Handler,Default_Handler + + .weak EXTI3_Handler + .thumb_set EXTI3_Handler,Default_Handler + + .weak EXTI4_Handler + .thumb_set EXTI4_Handler,Default_Handler + + .weak EXTI5_Handler + .thumb_set EXTI5_Handler,Default_Handler + + .weak EXTI6_Handler + .thumb_set EXTI6_Handler,Default_Handler + + .weak EXTI7_Handler + .thumb_set EXTI7_Handler,Default_Handler + + .weak EXTI8_Handler + .thumb_set EXTI8_Handler,Default_Handler + + .weak EXTI9_Handler + .thumb_set EXTI9_Handler,Default_Handler + + .weak EXTI10_Handler + .thumb_set EXTI10_Handler,Default_Handler + + .weak EXTI11_Handler + .thumb_set EXTI11_Handler,Default_Handler + + .weak EXTI12_Handler + .thumb_set EXTI12_Handler,Default_Handler + + .weak EXTI13_Handler + .thumb_set EXTI13_Handler,Default_Handler + + .weak EXTI14_Handler + .thumb_set EXTI14_Handler,Default_Handler + + .weak EXTI15_Handler + .thumb_set EXTI15_Handler,Default_Handler + + .weak DMA_Handler + .thumb_set DMA_Handler,Default_Handler + + .weak ADC1_Handler + .thumb_set ADC1_Handler,Default_Handler + + .weak DAC0_CH1_Handler + .thumb_set DAC0_CH1_Handler,Default_Handler + + .weak QSPI_Handler + .thumb_set QSPI_Handler,Default_Handler + + .weak USB_INT_Handler + .thumb_set USB_INT_Handler,Default_Handler + + .weak USB_DMA_Handler + .thumb_set USB_DMA_Handler,Default_Handler + + .weak ACMP2_Handler + .thumb_set ACMP2_Handler,Default_Handler + diff --git a/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/Startup/iar/startup_es32f36xx.s b/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/Startup/iar/startup_es32f36xx.s new file mode 100644 index 00000000..8cbaf6eb --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/Startup/iar/startup_es32f36xx.s @@ -0,0 +1,571 @@ +;******************************************************************************* +; file : startup_es32f36xx.s +; description: es32f36xx Device Startup File +; author : AE Team +; data : 04 Jul 2019 +; note +; Change Logs: +; Date Author Notes +; 04 Jul 2019 AE Team The first version +; +; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +;********************************************************************************* + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN sys_config + EXTERN adc_config + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ;0, load top of stack + DCD RESET_Handler ;1, reset handler + DCD NMI_Handler ;2, nmi handler + DCD HardFault_Handler ;3, hard fault handler + DCD MemManage_Handler ;4, MPU Fault Handler + DCD BusFault_Handler ;5, Bus Fault Handler + DCD UsageFault_Handler ;6, Usage Fault Handler + DCD 0 ;7, Reserved + DCD 0 ;8, Reserved + DCD 0 ;9, Reserved + DCD 0 ;10, Reserved + DCD SVC_Handler ;11, svcall handler + DCD DebugMon_Handler ;12, Debug Monitor Handler + DCD 0 ;13, Reserved + DCD PendSV_Handler ;14, pendsv handler + DCD SysTick_Handler ;15, systick handler + DCD WWDG_Handler ;16, irq0 WWDG handler + DCD IWDG_Handler ;17, irq1 IWDG handler + DCD LVD_Handler ;18, irq2 LVD handler + DCD RTC_Handler ;19, irq3 RTC handler + DCD 0 ;20, irq4 Reserved + DCD 0 ;21, irq5 Reserved + DCD CMU_Handler ;22, irq6 CMU handler + DCD ADC0_Handler ;23, irq7 ADC0 handler + DCD CAN0_TX_Handler ;24, irq8 CAN0_TX handler + DCD CAN0_RX0_Handler ;25, irq9 CAN0_RX0 handler + DCD CAN0_RX1_Handler ;26, irq10 CAN0_RX1 handler + DCD CAN0_EXCEPTION_Handler ;27, irq11 CAN0_EXCEPTION handler + DCD AD16C4T0_BRK_Handler ;28, irq12 AD16C4T0_BRK handler + DCD AD16C4T0_UP_Handler ;29, irq13 AD16C4T0_UP handler + DCD AD16C4T0_TRIG_COM_Handler ;30, irq14 AD16C4T0_TRIG_COM handler + DCD AD16C4T0_CC_Handler ;31, irq15 AD16C4T0_CC handler + DCD AD16C4T1_BRK_Handler ;32, irq16 AD16C4T1_BRK handler + DCD AD16C4T1_UP_Handler ;33, irq17 AD16C4T1_UP handler + DCD AD16C4T1_TRIG_COM_Handler ;34, irq18 AD16C4T1_TRIG_COM handler + DCD AD16C4T1_CC_Handler ;35, irq19 AD16C4T1_CC handler + DCD GP32C4T0_Handler ;36, irq20 GP32C4T0 handler + DCD GP32C4T1_Handler ;37, irq21 GP32C4T1 handler + DCD BS16T0_Handler ;38, irq22 BS16T0 handler + DCD BS16T1_Handler ;39, irq23 BS16T1 handler + DCD GP16C4T0_Handler ;40, irq24 GP16C4T0 handler + DCD GP16C4T1_Handler ;41, irq25 GP16C4T1 handler + DCD 0 ;42, irq26 Reserved + DCD DAC0_CH0_Handler ;43, irq27 DAC0_CH0 handler + DCD I2C0_EV_Handler ;44, irq28 I2C0_EV handler + DCD I2C0_ERR_Handler ;45, irq29 I2C0_ERR handler + DCD I2C1_EV_Handler ;46, irq30 I2C1_EV handler + DCD I2C1_ERR_Handler ;47, irq31 I2C1_ERR handler + DCD SPI0_I2S0_Handler ;48, irq32 SPI0_I2S0 handler + DCD SPI1_I2S1_Handler ;49, irq33 SPI1_I2S1 handler + DCD UART0_Handler ;50, irq34 UART0 handler + DCD UART1_Handler ;51, irq35 UART1 handler + DCD UART2_Handler ;52, irq36 UART2 handler + DCD UART3_Handler ;53, irq37 UART3 handler + DCD UART4_Handler ;54, irq38 UART4 handler + DCD UART5_Handler ;55, irq39 UART5 handler + DCD 0 ;56, irq40 Reserved + DCD 0 ;57, irq41 Reserved + DCD CRYPT_Handler ;58, irq42 CRYPT handler + DCD ACMP0_Handler ;59, irq43 ACMP0 handler + DCD ACMP1_Handler ;60, irq44 ACMP1 handler + DCD SPI2_I2S2_Handler ;61, irq45 SPI2_I2S2 handler + DCD 0 ;62, irq46 Reserved + DCD EBI_Handler ;63, irq47 EBI handler + DCD TRNG_Handler ;64, irq48 TRNG handler + DCD TSENSE_Handler ;65, irq49 TSENSE handler + DCD EXTI0_Handler ;66, irq50 EXTI0 handler + DCD EXTI1_Handler ;67, irq51 EXTI1 handler + DCD EXTI2_Handler ;68, irq52 EXTI2 handler + DCD EXTI3_Handler ;69, irq53 EXTI3 handler + DCD EXTI4_Handler ;70, irq54 EXTI4 handler + DCD EXTI5_Handler ;71, irq55 EXTI5 handler + DCD EXTI6_Handler ;72, irq56 EXTI6 handler + DCD EXTI7_Handler ;73, irq57 EXTI7 handler + DCD EXTI8_Handler ;74, irq58 EXTI8 handler + DCD EXTI9_Handler ;75, irq59 EXTI9 handler + DCD EXTI10_Handler ;76, irq60 EXTI10 handler + DCD EXTI11_Handler ;77, irq61 EXTI11 handler + DCD EXTI12_Handler ;78, irq62 EXTI12 handler + DCD EXTI13_Handler ;79, irq63 EXTI13 handler + DCD EXTI14_Handler ;80, irq64 EXTI14 handler + DCD EXTI15_Handler ;81, irq65 EXTI15 handler + DCD DMA_Handler ;82, irq66 DMA handler + DCD ADC1_Handler ;83, irq67 ADC1 handler + DCD DAC0_CH1_Handler ;84, irq68 DAC0_CH1 handler + DCD QSPI_Handler ;85, irq69 QSPI handler + DCD USB_INT_Handler ;86, irq70 USB_INT handler + DCD USB_DMA_Handler ;87, irq71 USB_DMA handler + DCD ACMP2_Handler ;88, irq72 ACMP2 handler + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK RESET_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +RESET_Handler + ldr r0, =0x55AA6996 + ldr r1, =0x40080000 + str r0, [r1] + + ldr r0, =0x5A962814 + ldr r1, =0x40080100 + str r0, [r1] + ldr r0, =0xE7CB69A5 + str r0, [r1] + + ldr r0, =0x40083C00 + ldr r1, [r0] + ldr r2, =0xffff + and r1, r2, r1 + ldr r2, =0x55AA0000 + orr r1, r2, r1 + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + + mov r0, r0 + mov r0, r0 + + ldr r0, =0x123456 + ldr r1, =0x40080100 + str r0, [r1] + + ldr r0, =0x40080404 + ldr r1, =0x4000000 + str r1, [r0] + + ldr r0, =0x123456 + ldr r1, =0x40080000 + str r0, [r1] + + LDR R0, =sys_config + BLX R0 + + LDR R0, =adc_config + BLX R0 + + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_Handler + B WWDG_Handler + + PUBWEAK IWDG_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IWDG_Handler + B IWDG_Handler + + PUBWEAK LVD_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_Handler + B LVD_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Handler + B RTC_Handler + + PUBWEAK CMU_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CMU_Handler + B CMU_Handler + + PUBWEAK ADC0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC0_Handler + B ADC0_Handler + + PUBWEAK CAN0_TX_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_TX_Handler + B CAN0_TX_Handler + + PUBWEAK CAN0_RX0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX0_Handler + B CAN0_RX0_Handler + + PUBWEAK CAN0_RX1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_RX1_Handler + B CAN0_RX1_Handler + + PUBWEAK CAN0_EXCEPTION_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN0_EXCEPTION_Handler + B CAN0_EXCEPTION_Handler + + PUBWEAK AD16C4T0_BRK_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T0_BRK_Handler + B AD16C4T0_BRK_Handler + + PUBWEAK AD16C4T0_UP_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T0_UP_Handler + B AD16C4T0_UP_Handler + + PUBWEAK AD16C4T0_TRIG_COM_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T0_TRIG_COM_Handler + B AD16C4T0_TRIG_COM_Handler + + PUBWEAK AD16C4T0_CC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T0_CC_Handler + B AD16C4T0_CC_Handler + + PUBWEAK AD16C4T1_BRK_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T1_BRK_Handler + B AD16C4T1_BRK_Handler + + PUBWEAK AD16C4T1_UP_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T1_UP_Handler + B AD16C4T1_UP_Handler + + PUBWEAK AD16C4T1_TRIG_COM_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T1_TRIG_COM_Handler + B AD16C4T1_TRIG_COM_Handler + + PUBWEAK AD16C4T1_CC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +AD16C4T1_CC_Handler + B AD16C4T1_CC_Handler + + PUBWEAK GP32C4T0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +GP32C4T0_Handler + B GP32C4T0_Handler + + PUBWEAK GP32C4T1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +GP32C4T1_Handler + B GP32C4T1_Handler + + PUBWEAK BS16T0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BS16T0_Handler + B BS16T0_Handler + + PUBWEAK BS16T1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BS16T1_Handler + B BS16T1_Handler + + PUBWEAK GP16C4T0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C4T0_Handler + B GP16C4T0_Handler + + PUBWEAK GP16C4T1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +GP16C4T1_Handler + B GP16C4T1_Handler + + PUBWEAK DAC0_CH0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DAC0_CH0_Handler + B DAC0_CH0_Handler + + PUBWEAK I2C0_EV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_Handler + B I2C0_EV_Handler + + PUBWEAK I2C0_ERR_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ERR_Handler + B I2C0_ERR_Handler + + PUBWEAK I2C1_EV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_Handler + B I2C1_EV_Handler + + PUBWEAK I2C1_ERR_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ERR_Handler + B I2C1_ERR_Handler + + PUBWEAK SPI0_I2S0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_I2S0_Handler + B SPI0_I2S0_Handler + + PUBWEAK SPI1_I2S1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_I2S1_Handler + B SPI1_I2S1_Handler + + PUBWEAK UART0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART0_Handler + B UART0_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART1_Handler + B UART1_Handler + + PUBWEAK UART2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART2_Handler + B UART2_Handler + + PUBWEAK UART3_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART3_Handler + B UART3_Handler + + PUBWEAK UART4_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_Handler + B UART4_Handler + + PUBWEAK UART5_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_Handler + B UART5_Handler + + PUBWEAK CRYPT_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYPT_Handler + B CRYPT_Handler + + PUBWEAK ACMP0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ACMP0_Handler + B ACMP0_Handler + + PUBWEAK ACMP1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ACMP1_Handler + B ACMP1_Handler + + PUBWEAK SPI2_I2S2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_I2S2_Handler + B SPI2_I2S2_Handler + + PUBWEAK EBI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EBI_Handler + B EBI_Handler + + PUBWEAK TRNG_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TRNG_Handler + B TRNG_Handler + + PUBWEAK TSENSE_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TSENSE_Handler + B TSENSE_Handler + + PUBWEAK EXTI0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_Handler + B EXTI0_Handler + + PUBWEAK EXTI1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_Handler + B EXTI1_Handler + + PUBWEAK EXTI2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_Handler + B EXTI2_Handler + + PUBWEAK EXTI3_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_Handler + B EXTI3_Handler + + PUBWEAK EXTI4_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_Handler + B EXTI4_Handler + + PUBWEAK EXTI5_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI5_Handler + B EXTI5_Handler + + PUBWEAK EXTI6_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI6_Handler + B EXTI6_Handler + + PUBWEAK EXTI7_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI7_Handler + B EXTI7_Handler + + PUBWEAK EXTI8_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI8_Handler + B EXTI8_Handler + + PUBWEAK EXTI9_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_Handler + B EXTI9_Handler + + PUBWEAK EXTI10_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI10_Handler + B EXTI10_Handler + + PUBWEAK EXTI11_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI11_Handler + B EXTI11_Handler + + PUBWEAK EXTI12_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI12_Handler + B EXTI12_Handler + + PUBWEAK EXTI13_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI13_Handler + B EXTI13_Handler + + PUBWEAK EXTI14_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI14_Handler + B EXTI14_Handler + + PUBWEAK EXTI15_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_Handler + B EXTI15_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_Handler + B DMA_Handler + + PUBWEAK ADC1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_Handler + B ADC1_Handler + + PUBWEAK DAC0_CH1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DAC0_CH1_Handler + B DAC0_CH1_Handler + + PUBWEAK QSPI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +QSPI_Handler + B QSPI_Handler + + PUBWEAK USB_INT_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_INT_Handler + B USB_INT_Handler + + PUBWEAK USB_DMA_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_DMA_Handler + B USB_DMA_Handler + + PUBWEAK ACMP2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ACMP2_Handler + B ACMP2_Handler + + END diff --git a/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s b/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s new file mode 100644 index 00000000..77346c38 --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s @@ -0,0 +1,689 @@ +;******************************************************************************* +; file : startup_es32f36xx.s +; description: es32f36xx Device Startup File +; author : AE Team +; data : 23 Jan 2019 +; note +; Change Logs: +; Date Author Notes +; 23 Jan 2019 AE Team The first version +; +; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +;********************************************************************************* + +;Stack Configuration------------------------------------------------------------ +Stack_Size EQU 0x00000800 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp +;------------------------------------------------------------------------------- + +;Heap Configuration------------------------------------------------------------- +Heap_Size EQU 0x00002000 + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit +;------------------------------------------------------------------------------- + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset------------------------------------- + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ;0, load top of stack + DCD RESET_Handler ;1, reset handler + DCD NMI_Handler ;2, nmi handler + DCD HardFault_Handler ;3, hard fault handler + DCD MemManage_Handler ;4, MPU Fault Handler + DCD BusFault_Handler ;5, Bus Fault Handler + DCD UsageFault_Handler ;6, Usage Fault Handler + DCD 0 ;7, Reserved + DCD 0 ;8, Reserved + DCD 0 ;9, Reserved + DCD 0 ;10, Reserved + DCD SVC_Handler ;11, svcall handler + DCD DebugMon_Handler ;12, Debug Monitor Handler + DCD 0 ;13, Reserved + DCD PendSV_Handler ;14, pendsv handler + DCD SysTick_Handler ;15, systick handler + DCD WWDG_Handler ;16, irq0 WWDG handler + DCD IWDG_Handler ;17, irq1 IWDG handler + DCD LVD_Handler ;18, irq2 LVD handler + DCD RTC_Handler ;19, irq3 RTC handler + DCD 0 ;20, irq4 Reserved + DCD 0 ;21, irq5 Reserved + DCD CMU_Handler ;22, irq6 CMU handler + DCD ADC0_Handler ;23, irq7 ADC0 handler + DCD CAN0_TX_Handler ;24, irq8 CAN0_TX handler + DCD CAN0_RX0_Handler ;25, irq9 CAN0_RX0 handler + DCD CAN0_RX1_Handler ;26, irq10 CAN0_RX1 handler + DCD CAN0_EXCEPTION_Handler ;27, irq11 CAN0_EXCEPTION handler + DCD AD16C4T0_BRK_Handler ;28, irq12 AD16C4T0_BRK handler + DCD AD16C4T0_UP_Handler ;29, irq13 AD16C4T0_UP handler + DCD AD16C4T0_TRIG_COM_Handler ;30, irq14 AD16C4T0_TRIG_COM handler + DCD AD16C4T0_CC_Handler ;31, irq15 AD16C4T0_CC handler + DCD AD16C4T1_BRK_Handler ;32, irq16 AD16C4T1_BRK handler + DCD AD16C4T1_UP_Handler ;33, irq17 AD16C4T1_UP handler + DCD AD16C4T1_TRIG_COM_Handler ;34, irq18 AD16C4T1_TRIG_COM handler + DCD AD16C4T1_CC_Handler ;35, irq19 AD16C4T1_CC handler + DCD GP32C4T0_Handler ;36, irq20 GP32C4T0 handler + DCD GP32C4T1_Handler ;37, irq21 GP32C4T1 handler + DCD BS16T0_Handler ;38, irq22 BS16T0 handler + DCD BS16T1_Handler ;39, irq23 BS16T1 handler + DCD GP16C4T0_Handler ;40, irq24 GP16C4T0 handler + DCD GP16C4T1_Handler ;41, irq25 GP16C4T1 handler + DCD 0 ;42, irq26 Reserved + DCD DAC0_CH0_Handler ;43, irq27 DAC0_CH0 handler + DCD I2C0_EV_Handler ;44, irq28 I2C0_EV handler + DCD I2C0_ERR_Handler ;45, irq29 I2C0_ERR handler + DCD I2C1_EV_Handler ;46, irq30 I2C1_EV handler + DCD I2C1_ERR_Handler ;47, irq31 I2C1_ERR handler + DCD SPI0_I2S0_Handler ;48, irq32 SPI0_I2S0 handler + DCD SPI1_I2S1_Handler ;49, irq33 SPI1_I2S1 handler + DCD UART0_Handler ;50, irq34 UART0 handler + DCD UART1_Handler ;51, irq35 UART1 handler + DCD UART2_Handler ;52, irq36 UART2 handler + DCD UART3_Handler ;53, irq37 UART3 handler + DCD UART4_Handler ;54, irq38 UART4 handler + DCD UART5_Handler ;55, irq39 UART5 handler + DCD 0 ;56, irq40 Reserved + DCD 0 ;57, irq41 Reserved + DCD CRYPT_Handler ;58, irq42 CRYPT handler + DCD ACMP0_Handler ;59, irq43 ACMP0 handler + DCD ACMP1_Handler ;60, irq44 ACMP1 handler + DCD SPI2_I2S2_Handler ;61, irq45 SPI2_I2S2 handler + DCD 0 ;62, irq46 Reserved + DCD EBI_Handler ;63, irq47 EBI handler + DCD TRNG_Handler ;64, irq48 TRNG handler + DCD TSENSE_Handler ;65, irq49 TSENSE handler + DCD EXTI0_Handler ;66, irq50 EXTI0 handler + DCD EXTI1_Handler ;67, irq51 EXTI1 handler + DCD EXTI2_Handler ;68, irq52 EXTI2 handler + DCD EXTI3_Handler ;69, irq53 EXTI3 handler + DCD EXTI4_Handler ;70, irq54 EXTI4 handler + DCD EXTI5_Handler ;71, irq55 EXTI5 handler + DCD EXTI6_Handler ;72, irq56 EXTI6 handler + DCD EXTI7_Handler ;73, irq57 EXTI7 handler + DCD EXTI8_Handler ;74, irq58 EXTI8 handler + DCD EXTI9_Handler ;75, irq59 EXTI9 handler + DCD EXTI10_Handler ;76, irq60 EXTI10 handler + DCD EXTI11_Handler ;77, irq61 EXTI11 handler + DCD EXTI12_Handler ;78, irq62 EXTI12 handler + DCD EXTI13_Handler ;79, irq63 EXTI13 handler + DCD EXTI14_Handler ;80, irq64 EXTI14 handler + DCD EXTI15_Handler ;81, irq65 EXTI15 handler + DCD DMA_Handler ;82, irq66 DMA handler + DCD ADC1_Handler ;83, irq67 ADC1 handler + DCD DAC0_CH1_Handler ;84, irq68 DAC0_CH1 handler + DCD QSPI_Handler ;85, irq69 QSPI handler + DCD USB_INT_Handler ;86, irq70 USB_INT handler + DCD USB_DMA_Handler ;87, irq71 USB_DMA handler + DCD ACMP2_Handler ;88, irq72 ACMP2 handler + +;------------------------------------------------------------------------------- + AREA INT, CODE, READONLY ;code begin + +;Reset Handler---------------------------------------------- +RESET_Handler PROC + EXPORT RESET_Handler [WEAK] + + ldr r0, =0x55AA6996 + ldr r1, =0x40080000 + str r0, [r1] + + ldr r0, =0x5A962814 + ldr r1, =0x40080100 + str r0, [r1] + ldr r0, =0xE7CB69A5 + str r0, [r1] + + ldr r0, =0x40083C00 + ldr r1, [r0] + ldr r2, =0xffff + and r1, r2 + ldr r2, =0x55AA0000 + orr r1, r2 + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + str r1, [r0] + + mov r0, r0 + mov r0, r0 + + ldr r0, =0x123456 + ldr r1, =0x40080100 + str r0, [r1] + + ldr r0, =0x40080404 + ldr r1, =0x4000000 + str r1, [r0] + + ldr r0, =0x123456 + ldr r1, =0x40080000 + str r0, [r1] + + IMPORT sys_config + LDR R0, =sys_config + BLX R0 + + IMPORT adc_config + LDR R0, =adc_config + BLX R0 + + IMPORT __main + LDR R0, =__main + BX R0 + NOP + ALIGN + ENDP + +;system int------------------------------------------------- +NMI_Handler PROC ;int 2 + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler \ + PROC ;int3 + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler \ + PROC ;int4 + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler \ + PROC ;int5 + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler \ + PROC ;int6 + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler \ + PROC ;int11 + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler \ + PROC ;int12 + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler \ + PROC ;int14 + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler \ + PROC ;int15 + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +;peripheral module int ----------------------------------------------- +WWDG_Handler \ + PROC ;int16 + EXPORT WWDG_Handler [WEAK] + B . + ENDP + +IWDG_Handler \ + PROC ;int17 + EXPORT IWDG_Handler [WEAK] + B . + ENDP + +LVD_Handler \ + PROC ;int18 + EXPORT LVD_Handler [WEAK] + B . + ENDP + +RTC_Handler \ + PROC ;int19 + EXPORT RTC_Handler [WEAK] + B . + ENDP + +FLASH_Handler \ + PROC ;int21 + EXPORT FLASH_Handler [WEAK] + B . + ENDP + +CMU_Handler \ + PROC ;int22 + EXPORT CMU_Handler [WEAK] + B . + ENDP + +ADC0_Handler \ + PROC ;int23 + EXPORT ADC0_Handler [WEAK] + B . + ENDP + +CAN0_TX_Handler \ + PROC ;int24 + EXPORT CAN0_TX_Handler [WEAK] + B . + ENDP + +CAN0_RX0_Handler \ + PROC ;int25 + EXPORT CAN0_RX0_Handler [WEAK] + B . + ENDP + +CAN0_RX1_Handler \ + PROC ;int26 + EXPORT CAN0_RX1_Handler [WEAK] + B . + ENDP + +CAN0_EXCEPTION_Handler \ + PROC ;int27 + EXPORT CAN0_EXCEPTION_Handler [WEAK] + B . + ENDP + +AD16C4T0_BRK_Handler \ + PROC ;int28 + EXPORT AD16C4T0_BRK_Handler [WEAK] + B . + ENDP + +AD16C4T0_UP_Handler \ + PROC ;int29 + EXPORT AD16C4T0_UP_Handler [WEAK] + B . + ENDP + +AD16C4T0_TRIG_COM_Handler \ + PROC ;int30 + EXPORT AD16C4T0_TRIG_COM_Handler [WEAK] + B . + ENDP + +AD16C4T0_CC_Handler \ + PROC ;int31 + EXPORT AD16C4T0_CC_Handler [WEAK] + B . + ENDP + +AD16C4T1_BRK_Handler \ + PROC ;int32 + EXPORT AD16C4T1_BRK_Handler [WEAK] + B . + ENDP + +AD16C4T1_UP_Handler \ + PROC ;int33 + EXPORT AD16C4T1_UP_Handler [WEAK] + B . + ENDP + +AD16C4T1_TRIG_COM_Handler \ + PROC ;int34 + EXPORT AD16C4T1_TRIG_COM_Handler [WEAK] + B . + ENDP + +AD16C4T1_CC_Handler \ + PROC ;int35 + EXPORT AD16C4T1_CC_Handler [WEAK] + B . + ENDP + +GP32C4T0_Handler \ + PROC ;int36 + EXPORT GP32C4T0_Handler [WEAK] + B . + ENDP + +GP32C4T1_Handler \ + PROC ;int37 + EXPORT GP32C4T1_Handler [WEAK] + B . + ENDP + +BS16T0_Handler \ + PROC ;int38 + EXPORT BS16T0_Handler [WEAK] + B . + ENDP + +BS16T1_Handler \ + PROC ;int39 + EXPORT BS16T1_Handler [WEAK] + B . + ENDP + +GP16C4T0_Handler \ + PROC ;int40 + EXPORT GP16C4T0_Handler [WEAK] + B . + ENDP + +GP16C4T1_Handler \ + PROC ;int41 + EXPORT GP16C4T1_Handler [WEAK] + B . + ENDP + +DAC0_CH0_Handler \ + PROC ;int43 + EXPORT DAC0_CH0_Handler [WEAK] + B . + ENDP + +I2C0_EV_Handler \ + PROC ;int44 + EXPORT I2C0_EV_Handler [WEAK] + B . + ENDP + +I2C0_ERR_Handler \ + PROC ;int45 + EXPORT I2C0_ERR_Handler [WEAK] + B . + ENDP + +I2C1_EV_Handler \ + PROC ;int46 + EXPORT I2C1_EV_Handler [WEAK] + B . + ENDP + +I2C1_ERR_Handler \ + PROC ;int47 + EXPORT I2C1_ERR_Handler [WEAK] + B . + ENDP + +SPI0_I2S0_Handler \ + PROC ;int48 + EXPORT SPI0_I2S0_Handler [WEAK] + B . + ENDP + +SPI1_I2S1_Handler \ + PROC ;int49 + EXPORT SPI1_I2S1_Handler [WEAK] + B . + ENDP + +UART0_Handler \ + PROC ;int50 + EXPORT UART0_Handler [WEAK] + B . + ENDP + +UART1_Handler \ + PROC ;int51 + EXPORT UART1_Handler [WEAK] + B . + ENDP + +UART2_Handler \ + PROC ;int52 + EXPORT UART2_Handler [WEAK] + B . + ENDP + +UART3_Handler \ + PROC ;int53 + EXPORT UART3_Handler [WEAK] + B . + ENDP + +UART4_Handler \ + PROC ;int54 + EXPORT UART4_Handler [WEAK] + B . + ENDP + +UART5_Handler \ + PROC ;int55 + EXPORT UART5_Handler [WEAK] + B . + ENDP + +CRYPT_Handler \ + PROC ;int58 + EXPORT CRYPT_Handler [WEAK] + B . + ENDP + +ACMP0_Handler \ + PROC ;int59 + EXPORT ACMP0_Handler [WEAK] + B . + ENDP + +ACMP1_Handler \ + PROC ;int60 + EXPORT ACMP1_Handler [WEAK] + B . + ENDP + +SPI2_I2S2_Handler \ + PROC ;int61 + EXPORT SPI2_I2S2_Handler [WEAK] + B . + ENDP + +EBI_Handler \ + PROC ;int63 + EXPORT EBI_Handler [WEAK] + B . + ENDP + +TRNG_Handler \ + PROC ;int64 + EXPORT TRNG_Handler [WEAK] + B . + ENDP + +TSENSE_Handler \ + PROC ;int65 + EXPORT TSENSE_Handler [WEAK] + B . + ENDP + +EXTI0_Handler \ + PROC ;int66 + EXPORT EXTI0_Handler [WEAK] + B . + ENDP + +EXTI1_Handler \ + PROC ;int67 + EXPORT EXTI1_Handler [WEAK] + B . + ENDP + +EXTI2_Handler \ + PROC ;int68 + EXPORT EXTI2_Handler [WEAK] + B . + ENDP + +EXTI3_Handler \ + PROC ;int69 + EXPORT EXTI3_Handler [WEAK] + B . + ENDP + +EXTI4_Handler \ + PROC ;int70 + EXPORT EXTI4_Handler [WEAK] + B . + ENDP + +EXTI5_Handler \ + PROC ;int71 + EXPORT EXTI5_Handler [WEAK] + B . + ENDP + +EXTI6_Handler \ + PROC ;int72 + EXPORT EXTI6_Handler [WEAK] + B . + ENDP + +EXTI7_Handler \ + PROC ;int73 + EXPORT EXTI7_Handler [WEAK] + B . + ENDP + +EXTI8_Handler \ + PROC ;int74 + EXPORT EXTI8_Handler [WEAK] + B . + ENDP + +EXTI9_Handler \ + PROC ;int75 + EXPORT EXTI9_Handler [WEAK] + B . + ENDP + +EXTI10_Handler \ + PROC ;int76 + EXPORT EXTI10_Handler [WEAK] + B . + ENDP + +EXTI11_Handler \ + PROC ;int77 + EXPORT EXTI11_Handler [WEAK] + B . + ENDP + +EXTI12_Handler \ + PROC ;int78 + EXPORT EXTI12_Handler [WEAK] + B . + ENDP + +EXTI13_Handler \ + PROC ;int79 + EXPORT EXTI13_Handler [WEAK] + B . + ENDP + +EXTI14_Handler \ + PROC ;int80 + EXPORT EXTI14_Handler [WEAK] + B . + ENDP + +EXTI15_Handler \ + PROC ;int81 + EXPORT EXTI15_Handler [WEAK] + B . + ENDP + +DMA_Handler \ + PROC ;int82 + EXPORT DMA_Handler [WEAK] + B . + ENDP + +ADC1_Handler \ + PROC ;int83 + EXPORT ADC1_Handler [WEAK] + B . + ENDP + +DAC0_CH1_Handler \ + PROC ;int84 + EXPORT DAC0_CH1_Handler [WEAK] + B . + ENDP + +QSPI_Handler \ + PROC ;int85 + EXPORT QSPI_Handler [WEAK] + B . + ENDP + +USB_INT_Handler \ + PROC ;int86 + EXPORT USB_INT_Handler [WEAK] + B . + ENDP + +USB_DMA_Handler \ + PROC ;int87 + EXPORT USB_DMA_Handler [WEAK] + B . + ENDP + +ACMP2_Handler \ + PROC ;int88 + EXPORT ACMP2_Handler [WEAK] + B . + ENDP + +; User Initial Stack & Heap----------------------------------------------------- + ALIGN + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/System/system_es32f36xx.c b/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/System/system_es32f36xx.c new file mode 100644 index 00000000..0f8495c4 --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Device/EastSoft/ES32F36xx/System/system_es32f36xx.c @@ -0,0 +1,44 @@ +/** + ********************************************************************************* + * + * @file system_es32f3xx.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer + * + * @version V1.0 + * @date 24 Dec 2019 + * @author AE Team + * @note + * Change Logs: + * Date Author Notes + * 24 Dec 2019 AE Team The first version + * + * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ********************************************************************************** + */ + +#include "utils.h" + + +/** + * @brief Configuring system clock before startup. + * @note This function must be used after reset. + * @retval None + */ +void system_init (void) +{ + /* do nothing */ +} \ No newline at end of file diff --git a/demo/es32/Drivers/CMSIS/Include/arm_common_tables.h b/demo/es32/Drivers/CMSIS/Include/arm_common_tables.h new file mode 100644 index 00000000..dfea7460 --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/demo/es32/Drivers/CMSIS/Include/arm_const_structs.h b/demo/es32/Drivers/CMSIS/Include/arm_const_structs.h new file mode 100644 index 00000000..80a3e8bb --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/demo/es32/Drivers/CMSIS/Include/arm_math.h b/demo/es32/Drivers/CMSIS/Include/arm_math.h new file mode 100644 index 00000000..ea9dd26a --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/arm_math.h @@ -0,0 +1,7157 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP LibraryU + * @version V1.5.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library + * on Armv8-M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 Arm Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/demo/es32/Drivers/CMSIS/Include/cmsis_armcc.h b/demo/es32/Drivers/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 00000000..093d35b9 --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,870 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/demo/es32/Drivers/CMSIS/Include/cmsis_armclang.h b/demo/es32/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 00000000..5c4c20e8 --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1877 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/demo/es32/Drivers/CMSIS/Include/cmsis_compiler.h b/demo/es32/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 00000000..94212eb8 --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/demo/es32/Drivers/CMSIS/Include/cmsis_gcc.h b/demo/es32/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 00000000..5d0f07e8 --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2088 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.3 + * @date 16. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/demo/es32/Drivers/CMSIS/Include/cmsis_iccarm.h b/demo/es32/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 00000000..edcaee3d --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,913 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.5 + * @date 10. January 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/demo/es32/Drivers/CMSIS/Include/cmsis_version.h b/demo/es32/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 00000000..660f612a --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/demo/es32/Drivers/CMSIS/Include/core_armv8mbl.h b/demo/es32/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 00000000..47a39893 --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1896 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/demo/es32/Drivers/CMSIS/Include/core_armv8mml.h b/demo/es32/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 00000000..0951a1f7 --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2960 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/demo/es32/Drivers/CMSIS/Include/core_cm0.h b/demo/es32/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 00000000..a3f1b9ac --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/demo/es32/Drivers/CMSIS/Include/core_cm0plus.h b/demo/es32/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 00000000..f8f30c34 --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1023 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/demo/es32/Drivers/CMSIS/Include/core_cm23.h b/demo/es32/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 00000000..7d1d478a --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,1899 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/demo/es32/Drivers/CMSIS/Include/core_cm3.h b/demo/es32/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 00000000..a2c0d080 --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1933 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/demo/es32/Drivers/CMSIS/Include/core_cm33.h b/demo/es32/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 00000000..b1efbcae --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,2963 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/demo/es32/Drivers/CMSIS/Include/core_cm4.h b/demo/es32/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 00000000..a11a3817 --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2118 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/demo/es32/Drivers/CMSIS/Include/core_cm7.h b/demo/es32/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 00000000..1fe53bf0 --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2660 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/demo/es32/Drivers/CMSIS/Include/core_sc000.h b/demo/es32/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 00000000..9aab5e5b --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1016 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/demo/es32/Drivers/CMSIS/Include/core_sc300.h b/demo/es32/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 00000000..a569ef2a --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1903 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/demo/es32/Drivers/CMSIS/Include/mpu_armv7.h b/demo/es32/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 00000000..aa180c9e --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,197 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) + +#define ARM_MPU_AP_NONE 0U +#define ARM_MPU_AP_PRIV 1U +#define ARM_MPU_AP_URO 2U +#define ARM_MPU_AP_FULL 3U +#define ARM_MPU_AP_PRO 5U +#define ARM_MPU_AP_RO 6U + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (MPU_RASR_ENABLE_Msk)) + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/demo/es32/Drivers/CMSIS/Include/mpu_armv8.h b/demo/es32/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 00000000..0ccfc74f --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Pos) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/demo/es32/Drivers/CMSIS/Include/tz_context.h b/demo/es32/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 00000000..0d09749f --- /dev/null +++ b/demo/es32/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/demo/es32/usb_device/ES32F369x/MDK-ARM/example.uvoptx b/demo/es32/usb_device/ES32F369x/MDK-ARM/example.uvoptx index efd32625..39376be1 100644 --- a/demo/es32/usb_device/ES32F369x/MDK-ARM/example.uvoptx +++ b/demo/es32/usb_device/ES32F369x/MDK-ARM/example.uvoptx @@ -103,7 +103,7 @@ 1 0 0 - 6 + 3 @@ -114,7 +114,7 @@ - STLink\ST-LINKIII-KEIL_SWO.dll + BIN\CMSIS_AGDI.dll @@ -276,7 +276,7 @@ startup - 0 + 1 0 0 0 @@ -287,7 +287,7 @@ 0 0 0 - ..\Drivers\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s + ..\..\..\Drivers\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s startup_es32f36xx.s 0 0 @@ -307,7 +307,7 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_bkpc.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_bkpc.c ald_bkpc.c 0 0 @@ -319,7 +319,7 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_cmu.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_cmu.c ald_cmu.c 0 0 @@ -331,7 +331,7 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_dma.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_dma.c ald_dma.c 0 0 @@ -343,7 +343,7 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_gpio.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_gpio.c ald_gpio.c 0 0 @@ -355,8 +355,8 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_pmu.c - ald_pmu.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_iap.c + ald_iap.c 0 0 @@ -367,8 +367,8 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_rmu.c - ald_rmu.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_pmu.c + ald_pmu.c 0 0 @@ -379,8 +379,8 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_uart.c - ald_uart.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_rmu.c + ald_rmu.c 0 0 @@ -391,8 +391,8 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_usb.c - ald_usb.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_uart.c + ald_uart.c 0 0 @@ -403,8 +403,8 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_iap.c - ald_iap.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_usb.c + ald_usb.c 0 0 @@ -415,7 +415,7 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\utils.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\utils.c utils.c 0 0 diff --git a/demo/es32/usb_device/ES32F369x/MDK-ARM/example.uvprojx b/demo/es32/usb_device/ES32F369x/MDK-ARM/example.uvprojx index 0f57c065..2697826d 100644 --- a/demo/es32/usb_device/ES32F369x/MDK-ARM/example.uvprojx +++ b/demo/es32/usb_device/ES32F369x/MDK-ARM/example.uvprojx @@ -340,7 +340,7 @@ USE_ASSERT,ES32F36xx,USBD_CDC_HS - ..\Drivers\CMSIS\Include;..\Drivers\CMSIS\Device\EastSoft\ES32F36xx\Include;..\Drivers\ALD\ES32F36xx\Include;..\Inc;..\..\..\..\..\common;..\..\..\..\..\core;..\..\..\..\..\class\cdc + ..\..\..\Drivers\CMSIS\Include;..\..\..\Drivers\CMSIS\Device\EastSoft\ES32F36xx\Include;..\..\..\Drivers\ALD\ES32F36xx\Include;..\Inc;..\..\..\..\..\common;..\..\..\..\..\core;..\..\..\..\..\class\cdc @@ -387,7 +387,7 @@ startup_es32f36xx.s 2 - ..\Drivers\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s + ..\..\..\Drivers\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s @@ -397,52 +397,52 @@ ald_bkpc.c 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_bkpc.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_bkpc.c ald_cmu.c 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_cmu.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_cmu.c ald_dma.c 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_dma.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_dma.c ald_gpio.c 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_gpio.c - - - ald_pmu.c - 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_pmu.c - - - ald_rmu.c - 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_rmu.c - - - ald_uart.c - 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_uart.c - - - ald_usb.c - 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_usb.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_gpio.c ald_iap.c 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_iap.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_iap.c + + + ald_pmu.c + 1 + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_pmu.c + + + ald_rmu.c + 1 + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_rmu.c + + + ald_uart.c + 1 + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_uart.c + + + ald_usb.c + 1 + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_usb.c utils.c 1 - ..\Drivers\ALD\ES32F36xx\Source\utils.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\utils.c diff --git a/demo/es32/usb_device/ES32F369x/copy Drivers from es32 sdk here.txt b/demo/es32/usb_device/ES32F369x/copy Drivers from es32 sdk here.txt deleted file mode 100644 index e69de29b..00000000 diff --git a/demo/es32/usb_host/ES32F369x/MDK-ARM/example.uvoptx b/demo/es32/usb_host/ES32F369x/MDK-ARM/example.uvoptx index 0a2e0509..ce16373c 100644 --- a/demo/es32/usb_host/ES32F369x/MDK-ARM/example.uvoptx +++ b/demo/es32/usb_host/ES32F369x/MDK-ARM/example.uvoptx @@ -103,7 +103,7 @@ 1 0 0 - 6 + 3 @@ -114,7 +114,7 @@ - STLink\ST-LINKIII-KEIL_SWO.dll + BIN\CMSIS_AGDI.dll @@ -130,7 +130,7 @@ 0 DLGUARM - (105=-1,-1,-1,-1,0) + 0 @@ -163,56 +163,7 @@ -T0 - - - 0 - 0 - 155 - 1 -
0
- 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\..\..\class\hid\usbh_hid.c - - - - - 1 - 0 - 175 - 1 -
0
- 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\..\..\class\hid\usbh_hid.c - - - - - 2 - 0 - 88 - 1 -
0
- 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\..\..\class\hid\usbh_hid.c - - - - + 0 @@ -320,7 +271,7 @@ 0 0 0 - ..\Drivers\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s + ..\..\..\Drivers\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s startup_es32f36xx.s 0 0 @@ -329,7 +280,7 @@ ald - 0 + 1 0 0 0 @@ -340,7 +291,7 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_bkpc.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_bkpc.c ald_bkpc.c 0 0 @@ -352,7 +303,7 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_cmu.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_cmu.c ald_cmu.c 0 0 @@ -364,7 +315,7 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_dma.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_dma.c ald_dma.c 0 0 @@ -376,7 +327,7 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_gpio.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_gpio.c ald_gpio.c 0 0 @@ -388,8 +339,8 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_pmu.c - ald_pmu.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_iap.c + ald_iap.c 0 0 @@ -400,8 +351,8 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_rmu.c - ald_rmu.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_pmu.c + ald_pmu.c 0 0 @@ -412,8 +363,8 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_uart.c - ald_uart.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_rmu.c + ald_rmu.c 0 0 @@ -424,8 +375,8 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_usb.c - ald_usb.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_uart.c + ald_uart.c 0 0 @@ -436,8 +387,8 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\ald_iap.c - ald_iap.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_usb.c + ald_usb.c 0 0 @@ -448,7 +399,7 @@ 0 0 0 - ..\Drivers\ALD\ES32F36xx\Source\utils.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\utils.c utils.c 0 0 @@ -457,7 +408,7 @@ app - 1 + 0 0 0 0 diff --git a/demo/es32/usb_host/ES32F369x/MDK-ARM/example.uvprojx b/demo/es32/usb_host/ES32F369x/MDK-ARM/example.uvprojx index 648c3d6e..66e15565 100644 --- a/demo/es32/usb_host/ES32F369x/MDK-ARM/example.uvprojx +++ b/demo/es32/usb_host/ES32F369x/MDK-ARM/example.uvprojx @@ -340,7 +340,7 @@ USE_ASSERT,ES32F36xx, - ..\Drivers\CMSIS\Include;..\Drivers\CMSIS\Device\EastSoft\ES32F36xx\Include;..\Drivers\ALD\ES32F36xx\Include;..\Inc;..\..\..\..\..\common;..\..\..\..\..\core;..\..\..\..\..\class\cdc;..\..\..\..\..\class\hid;..\..\..\..\..\class\msc;..\..\..\..\..\class\hub;..\..\..\..\..\class\wireless;..\..\..\..\..\osal;..\..\..\..\..\third_party\FreeRTOS-10.4\include;..\..\..\..\..\third_party\FreeRTOS-10.4\portable\GCC\ARM_CM3 + ..\..\..\Drivers\CMSIS\Include;..\..\..\Drivers\CMSIS\Device\EastSoft\ES32F36xx\Include;..\..\..\Drivers\ALD\ES32F36xx\Include;..\Inc;..\..\..\..\..\common;..\..\..\..\..\core;..\..\..\..\..\class\cdc;..\..\..\..\..\class\hid;..\..\..\..\..\class\msc;..\..\..\..\..\class\hub;..\..\..\..\..\class\wireless;..\..\..\..\..\osal;..\..\..\..\..\third_party\FreeRTOS-10.4\include;..\..\..\..\..\third_party\FreeRTOS-10.4\portable\GCC\ARM_CM3 @@ -387,7 +387,7 @@ startup_es32f36xx.s 2 - ..\Drivers\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s + ..\..\..\Drivers\CMSIS\Device\EastSoft\ES32F36xx\Startup\keil\startup_es32f36xx.s @@ -397,52 +397,52 @@ ald_bkpc.c 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_bkpc.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_bkpc.c ald_cmu.c 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_cmu.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_cmu.c ald_dma.c 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_dma.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_dma.c ald_gpio.c 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_gpio.c - - - ald_pmu.c - 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_pmu.c - - - ald_rmu.c - 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_rmu.c - - - ald_uart.c - 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_uart.c - - - ald_usb.c - 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_usb.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_gpio.c ald_iap.c 1 - ..\Drivers\ALD\ES32F36xx\Source\ald_iap.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_iap.c + + + ald_pmu.c + 1 + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_pmu.c + + + ald_rmu.c + 1 + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_rmu.c + + + ald_uart.c + 1 + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_uart.c + + + ald_usb.c + 1 + ..\..\..\Drivers\ALD\ES32F36xx\Source\ald_usb.c utils.c 1 - ..\Drivers\ALD\ES32F36xx\Source\utils.c + ..\..\..\Drivers\ALD\ES32F36xx\Source\utils.c @@ -596,4 +596,13 @@ + + + + example + 1 + + + + diff --git a/demo/es32/usb_host/ES32F369x/copy Drivers from es32 sdk here.txt b/demo/es32/usb_host/ES32F369x/copy Drivers from es32 sdk here.txt deleted file mode 100644 index e69de29b..00000000