Files
CherryUSB/port/fsdev/usb_dc_fsdev.c

524 lines
17 KiB
C
Raw Normal View History

2021-12-04 19:28:20 +08:00
#include "usbd_core.h"
2022-01-11 22:42:51 +08:00
#include "usb_fsdev_reg.h"
2021-12-04 19:28:20 +08:00
#ifndef USBD_IRQHandler
2021-12-04 19:28:20 +08:00
#define USBD_IRQHandler USB_LP_CAN1_RX0_IRQHandler //use actual usb irq name instead
#endif
2021-12-04 19:28:20 +08:00
2022-02-20 20:53:42 +08:00
#ifndef USB_BASE
2022-03-11 21:08:41 +08:00
#define USB_BASE (0x40005C00UL) /*!< USB_IP Peripheral Registers base address */
2022-02-20 20:53:42 +08:00
#endif
2021-12-04 19:28:20 +08:00
#ifndef USB_NUM_BIDIR_ENDPOINTS
#define USB_NUM_BIDIR_ENDPOINTS 8
#endif
#ifndef USB_RAM_SIZE
#define USB_RAM_SIZE 512
#endif
#define USB ((USB_TypeDef *)USB_BASE)
2021-12-04 19:28:20 +08:00
#define USB_BTABLE_SIZE (8 * USB_NUM_BIDIR_ENDPOINTS)
2022-06-15 20:50:59 +08:00
static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
2021-12-04 19:28:20 +08:00
/* Endpoint state */
2022-06-14 22:08:04 +08:00
struct fsdev_ep_state {
uint16_t ep_mps; /* Endpoint max packet size */
uint8_t ep_type; /* Endpoint type */
uint8_t ep_stalled; /* Endpoint stall flag */
2021-12-04 19:28:20 +08:00
uint16_t ep_pma_buf_len; /** Previously allocated buffer size */
uint16_t ep_pma_addr; /** ep pmd allocated addr */
uint8_t *xfer_buf;
uint32_t xfer_len;
uint32_t actual_xfer_len;
2021-12-04 19:28:20 +08:00
};
/* Driver state */
2022-06-14 22:08:04 +08:00
struct fsdev_udc {
struct usb_setup_packet setup;
2022-06-15 20:50:59 +08:00
volatile uint8_t dev_addr; /*!< USB Address */
volatile uint32_t pma_offset; /*!< pma offset */
2022-06-14 22:08:04 +08:00
struct fsdev_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/
struct fsdev_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
} g_fsdev_udc;
2021-12-04 19:28:20 +08:00
__WEAK void usb_dc_low_level_init(void)
{
}
__WEAK void usb_dc_low_level_deinit(void)
{
}
2021-12-04 19:28:20 +08:00
int usb_dc_init(void)
{
2022-06-14 22:08:04 +08:00
memset(&g_fsdev_udc, 0, sizeof(struct fsdev_udc));
2021-12-04 19:28:20 +08:00
2022-06-14 22:08:04 +08:00
g_fsdev_udc.pma_offset = USB_BTABLE_SIZE;
2021-12-04 19:28:20 +08:00
usb_dc_low_level_init();
2021-12-04 19:28:20 +08:00
/* Init Device */
/* CNTR_FRES = 1 */
2022-02-20 20:53:42 +08:00
USB->CNTR = (uint16_t)USB_CNTR_FRES;
2021-12-04 19:28:20 +08:00
/* CNTR_FRES = 0 */
2022-02-20 20:53:42 +08:00
USB->CNTR = 0U;
2021-12-04 19:28:20 +08:00
/* Clear pending interrupts */
2022-02-20 20:53:42 +08:00
USB->ISTR = 0U;
2021-12-04 19:28:20 +08:00
/*Set Btable Address*/
2022-02-20 20:53:42 +08:00
USB->BTABLE = BTABLE_ADDRESS;
2021-12-04 19:28:20 +08:00
uint32_t winterruptmask;
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
USB_CNTR_SUSPM | USB_CNTR_ERRM |
USB_CNTR_SOFM | USB_CNTR_ESOFM |
USB_CNTR_RESETM;
/* Set interrupt mask */
2022-02-20 20:53:42 +08:00
USB->CNTR = (uint16_t)winterruptmask;
2021-12-04 19:28:20 +08:00
return 0;
}
2022-03-11 21:08:41 +08:00
int usb_dc_deinit(void)
2021-12-04 19:28:20 +08:00
{
/* disable all interrupts and force USB reset */
2022-02-20 20:53:42 +08:00
USB->CNTR = (uint16_t)USB_CNTR_FRES;
2021-12-04 19:28:20 +08:00
/* clear interrupt status register */
2022-02-20 20:53:42 +08:00
USB->ISTR = 0U;
2021-12-04 19:28:20 +08:00
/* switch-off device */
2022-02-20 20:53:42 +08:00
USB->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
2021-12-04 19:28:20 +08:00
usb_dc_low_level_deinit();
2022-03-11 21:08:41 +08:00
return 0;
2021-12-04 19:28:20 +08:00
}
int usbd_set_address(const uint8_t addr)
{
if (addr == 0U) {
/* set device address and enable function */
2022-02-20 20:53:42 +08:00
USB->DADDR = (uint16_t)USB_DADDR_EF;
2021-12-04 19:28:20 +08:00
}
2022-06-14 22:08:04 +08:00
g_fsdev_udc.dev_addr = addr;
2021-12-04 19:28:20 +08:00
return 0;
}
int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
{
uint8_t ep_idx = USB_EP_GET_IDX(ep_cfg->ep_addr);
if (ep_idx > (USB_NUM_BIDIR_ENDPOINTS - 1)) {
USB_LOG_ERR("Ep addr %d overflow\r\n", ep_cfg->ep_addr);
2021-12-04 19:28:20 +08:00
return -1;
}
uint16_t wEpRegVal;
/* initialize Endpoint */
switch (ep_cfg->ep_type) {
case USB_ENDPOINT_TYPE_CONTROL:
2022-02-20 20:53:42 +08:00
wEpRegVal = USB_EP_CONTROL;
2021-12-04 19:28:20 +08:00
break;
case USB_ENDPOINT_TYPE_BULK:
2022-02-20 20:53:42 +08:00
wEpRegVal = USB_EP_BULK;
2021-12-04 19:28:20 +08:00
break;
case USB_ENDPOINT_TYPE_INTERRUPT:
2022-02-20 20:53:42 +08:00
wEpRegVal = USB_EP_INTERRUPT;
2021-12-04 19:28:20 +08:00
break;
case USB_ENDPOINT_TYPE_ISOCHRONOUS:
2022-02-20 20:53:42 +08:00
wEpRegVal = USB_EP_ISOCHRONOUS;
2021-12-04 19:28:20 +08:00
break;
default:
break;
}
2022-02-20 20:53:42 +08:00
PCD_SET_EPTYPE(USB, ep_idx, wEpRegVal);
PCD_SET_EP_ADDRESS(USB, ep_idx, ep_idx);
2021-12-04 19:28:20 +08:00
if (USB_EP_DIR_IS_OUT(ep_cfg->ep_addr)) {
2022-06-14 22:08:04 +08:00
g_fsdev_udc.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
g_fsdev_udc.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
if (g_fsdev_udc.out_ep[ep_idx].ep_mps > g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len) {
2022-06-20 20:22:35 +08:00
if (g_fsdev_udc.pma_offset + g_fsdev_udc.out_ep[ep_idx].ep_mps > USB_RAM_SIZE) {
USB_LOG_ERR("Ep pma %d overflow\r\n", ep_cfg->ep_addr);
2021-12-04 19:28:20 +08:00
return -1;
}
2022-06-14 22:08:04 +08:00
g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len = ep_cfg->ep_mps;
g_fsdev_udc.out_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset;
2021-12-04 19:28:20 +08:00
/*Set the endpoint Receive buffer address */
2022-06-14 22:08:04 +08:00
PCD_SET_EP_RX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset);
g_fsdev_udc.pma_offset += ep_cfg->ep_mps;
2021-12-04 19:28:20 +08:00
}
/*Set the endpoint Receive buffer counter*/
2022-02-20 20:53:42 +08:00
PCD_SET_EP_RX_CNT(USB, ep_idx, ep_cfg->ep_mps);
PCD_CLEAR_RX_DTOG(USB, ep_idx);
2021-12-04 19:28:20 +08:00
} else {
2022-06-14 22:08:04 +08:00
g_fsdev_udc.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
g_fsdev_udc.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
if (g_fsdev_udc.in_ep[ep_idx].ep_mps > g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len) {
2022-06-20 20:22:35 +08:00
if (g_fsdev_udc.pma_offset + g_fsdev_udc.in_ep[ep_idx].ep_mps > USB_RAM_SIZE) {
USB_LOG_ERR("Ep pma %d overflow\r\n", ep_cfg->ep_addr);
2021-12-04 19:28:20 +08:00
return -1;
}
2022-06-14 22:08:04 +08:00
g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len = ep_cfg->ep_mps;
g_fsdev_udc.in_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset;
2021-12-04 19:28:20 +08:00
/*Set the endpoint Transmit buffer address */
2022-06-14 22:08:04 +08:00
PCD_SET_EP_TX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset);
g_fsdev_udc.pma_offset += ep_cfg->ep_mps;
2021-12-04 19:28:20 +08:00
}
2022-02-20 20:53:42 +08:00
PCD_CLEAR_TX_DTOG(USB, ep_idx);
if (ep_cfg->ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
2021-12-04 19:28:20 +08:00
/* Configure NAK status for the Endpoint */
2022-02-20 20:53:42 +08:00
PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK);
2021-12-04 19:28:20 +08:00
} else {
/* Configure TX Endpoint to disabled state */
2022-02-20 20:53:42 +08:00
PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS);
2021-12-04 19:28:20 +08:00
}
}
return 0;
}
2022-02-20 20:53:42 +08:00
2021-12-04 19:28:20 +08:00
int usbd_ep_close(const uint8_t ep)
{
uint8_t ep_idx = USB_EP_GET_IDX(ep);
if (USB_EP_DIR_IS_OUT(ep)) {
2022-02-20 20:53:42 +08:00
PCD_CLEAR_RX_DTOG(USB, ep_idx);
2021-12-04 19:28:20 +08:00
/* Configure DISABLE status for the Endpoint*/
2022-02-20 20:53:42 +08:00
PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_DIS);
2021-12-04 19:28:20 +08:00
} else {
2022-02-20 20:53:42 +08:00
PCD_CLEAR_TX_DTOG(USB, ep_idx);
2021-12-04 19:28:20 +08:00
/* Configure DISABLE status for the Endpoint*/
2022-02-20 20:53:42 +08:00
PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS);
2021-12-04 19:28:20 +08:00
}
return 0;
}
2022-02-20 20:53:42 +08:00
2021-12-04 19:28:20 +08:00
int usbd_ep_set_stall(const uint8_t ep)
{
uint8_t ep_idx = USB_EP_GET_IDX(ep);
if (USB_EP_DIR_IS_OUT(ep)) {
2022-02-20 20:53:42 +08:00
PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_STALL);
2021-12-04 19:28:20 +08:00
} else {
2022-02-20 20:53:42 +08:00
PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_STALL);
2021-12-04 19:28:20 +08:00
}
return 0;
}
2022-02-20 20:53:42 +08:00
2021-12-04 19:28:20 +08:00
int usbd_ep_clear_stall(const uint8_t ep)
{
uint8_t ep_idx = USB_EP_GET_IDX(ep);
if (USB_EP_DIR_IS_OUT(ep)) {
PCD_CLEAR_RX_DTOG(USB, ep_idx);
/* Configure VALID status for the Endpoint */
PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
} else {
2022-02-20 20:53:42 +08:00
PCD_CLEAR_TX_DTOG(USB, ep_idx);
2021-12-04 19:28:20 +08:00
2022-06-14 22:08:04 +08:00
if (g_fsdev_udc.in_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
2021-12-04 19:28:20 +08:00
/* Configure NAK status for the Endpoint */
2022-02-20 20:53:42 +08:00
PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK);
2021-12-04 19:28:20 +08:00
}
}
return 0;
}
2022-02-20 20:53:42 +08:00
2021-12-04 19:28:20 +08:00
int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
{
if (USB_EP_DIR_IS_OUT(ep)) {
} else {
}
return 0;
}
int usbd_ep_start_write(const uint8_t ep, const uint8_t *data, uint32_t data_len)
2021-12-04 19:28:20 +08:00
{
uint8_t ep_idx = USB_EP_GET_IDX(ep);
if (!data && data_len) {
return -1;
}
g_fsdev_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data;
g_fsdev_udc.in_ep[ep_idx].xfer_len = data_len;
g_fsdev_udc.in_ep[ep_idx].actual_xfer_len = 0;
data_len = MIN(data_len, g_fsdev_udc.in_ep[ep_idx].ep_mps);
2021-12-04 19:28:20 +08:00
2022-06-15 20:50:59 +08:00
fsdev_write_pma(USB, (uint8_t *)data, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)data_len);
2022-02-20 20:53:42 +08:00
PCD_SET_EP_TX_CNT(USB, ep_idx, (uint16_t)data_len);
PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID);
2021-12-04 19:28:20 +08:00
return 0;
}
int usbd_ep_start_read(const uint8_t ep, uint8_t *data, uint32_t data_len)
2021-12-04 19:28:20 +08:00
{
uint8_t ep_idx = USB_EP_GET_IDX(ep);
if (!data && data_len) {
2021-12-04 19:28:20 +08:00
return -1;
}
g_fsdev_udc.out_ep[ep_idx].xfer_buf = data;
g_fsdev_udc.out_ep[ep_idx].xfer_len = data_len;
g_fsdev_udc.out_ep[ep_idx].actual_xfer_len = 0;
2021-12-04 19:28:20 +08:00
PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
2021-12-04 19:28:20 +08:00
return 0;
}
void USBD_IRQHandler(void)
{
uint16_t wIstr, wEPVal;
uint8_t ep_idx;
uint8_t read_count;
uint16_t write_count;
2021-12-04 19:28:20 +08:00
uint16_t store_ep[8];
wIstr = USB->ISTR;
2021-12-04 19:28:20 +08:00
if (wIstr & USB_ISTR_CTR) {
2022-02-20 20:53:42 +08:00
while ((USB->ISTR & USB_ISTR_CTR) != 0U) {
wIstr = USB->ISTR;
2021-12-04 19:28:20 +08:00
/* extract highest priority endpoint number */
ep_idx = (uint8_t)(wIstr & USB_ISTR_EP_ID);
2021-12-04 19:28:20 +08:00
if (ep_idx == 0U) {
2021-12-04 19:28:20 +08:00
if ((wIstr & USB_ISTR_DIR) == 0U) {
PCD_CLEAR_TX_EP_CTR(USB, ep_idx);
write_count = PCD_GET_EP_TX_CNT(USB, ep_idx);
g_fsdev_udc.in_ep[ep_idx].xfer_buf += write_count;
g_fsdev_udc.in_ep[ep_idx].xfer_len -= write_count;
g_fsdev_udc.in_ep[ep_idx].actual_xfer_len += write_count;
usbd_event_ep_in_complete_handler(ep_idx | 0x80, g_fsdev_udc.in_ep[ep_idx].actual_xfer_len);
2021-12-04 19:28:20 +08:00
if (g_fsdev_udc.setup.wLength == 0) {
/* In status, start reading setup */
usbd_ep_start_read(0x00, NULL, 0);
} else if (g_fsdev_udc.setup.wLength && ((g_fsdev_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) {
/* In status, start reading setup */
usbd_ep_start_read(0x00, NULL, 0);
}
if ((g_fsdev_udc.dev_addr > 0U) && (write_count == 0U)) {
2022-06-14 22:08:04 +08:00
USB->DADDR = ((uint16_t)g_fsdev_udc.dev_addr | USB_DADDR_EF);
g_fsdev_udc.dev_addr = 0U;
2021-12-04 19:28:20 +08:00
}
2022-01-26 21:59:15 +08:00
} else {
wEPVal = PCD_GET_ENDPOINT(USB, ep_idx);
2022-01-26 21:59:15 +08:00
if ((wEPVal & USB_EP_SETUP) != 0U) {
PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
2022-01-26 21:59:15 +08:00
read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
fsdev_read_pma(USB, (uint8_t *)&g_fsdev_udc.setup, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
2022-01-26 21:59:15 +08:00
usbd_event_ep0_setup_complete_handler((uint8_t *)&g_fsdev_udc.setup);
2022-01-26 21:59:15 +08:00
} else if ((wEPVal & USB_EP_CTR_RX) != 0U) {
PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
fsdev_read_pma(USB, g_fsdev_udc.out_ep[ep_idx].xfer_buf, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
g_fsdev_udc.out_ep[ep_idx].xfer_buf += read_count;
g_fsdev_udc.out_ep[ep_idx].xfer_len -= read_count;
g_fsdev_udc.out_ep[ep_idx].actual_xfer_len += read_count;
usbd_event_ep_out_complete_handler(ep_idx, g_fsdev_udc.out_ep[ep_idx].actual_xfer_len);
if (read_count == 0) {
/* Out status, start reading setup */
usbd_ep_start_read(0x00, NULL, 0);
}
2022-01-26 21:59:15 +08:00
}
2021-12-04 19:28:20 +08:00
}
} else {
wEPVal = PCD_GET_ENDPOINT(USB, ep_idx);
2021-12-04 19:28:20 +08:00
if ((wEPVal & USB_EP_CTR_RX) != 0U) {
PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
fsdev_read_pma(USB, g_fsdev_udc.out_ep[ep_idx].xfer_buf, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
g_fsdev_udc.out_ep[ep_idx].xfer_buf += read_count;
g_fsdev_udc.out_ep[ep_idx].xfer_len -= read_count;
g_fsdev_udc.out_ep[ep_idx].actual_xfer_len += read_count;
if ((read_count < g_fsdev_udc.out_ep[ep_idx].ep_mps) ||
(g_fsdev_udc.out_ep[ep_idx].xfer_len == 0)) {
usbd_event_ep_out_complete_handler(ep_idx, g_fsdev_udc.out_ep[ep_idx].actual_xfer_len);
} else {
PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
}
2021-12-04 19:28:20 +08:00
}
if ((wEPVal & USB_EP_CTR_TX) != 0U) {
PCD_CLEAR_TX_EP_CTR(USB, ep_idx);
write_count = PCD_GET_EP_TX_CNT(USB, ep_idx);
g_fsdev_udc.in_ep[ep_idx].xfer_buf += write_count;
g_fsdev_udc.in_ep[ep_idx].xfer_len -= write_count;
g_fsdev_udc.in_ep[ep_idx].actual_xfer_len += write_count;
if (g_fsdev_udc.in_ep[ep_idx].xfer_len == 0) {
usbd_event_ep_in_complete_handler(ep_idx | 0x80, g_fsdev_udc.in_ep[ep_idx].actual_xfer_len);
} else {
write_count = MIN(g_fsdev_udc.in_ep[ep_idx].xfer_len, g_fsdev_udc.in_ep[ep_idx].ep_mps);
fsdev_write_pma(USB, g_fsdev_udc.in_ep[ep_idx].xfer_buf, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)write_count);
PCD_SET_EP_TX_CNT(USB, ep_idx, write_count);
PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID);
}
2021-12-04 19:28:20 +08:00
}
}
}
}
if (wIstr & USB_ISTR_RESET) {
2022-06-14 22:08:04 +08:00
memset(&g_fsdev_udc, 0, sizeof(struct fsdev_udc));
g_fsdev_udc.pma_offset = USB_BTABLE_SIZE;
usbd_event_reset_handler();
/* start reading setup packet */
PCD_SET_EP_RX_STATUS(USB, 0, USB_EP_RX_VALID);
2022-02-20 20:53:42 +08:00
USB->ISTR &= (uint16_t)(~USB_ISTR_RESET);
2021-12-04 19:28:20 +08:00
}
if (wIstr & USB_ISTR_PMAOVR) {
2022-02-20 20:53:42 +08:00
USB->ISTR &= (uint16_t)(~USB_ISTR_PMAOVR);
2021-12-04 19:28:20 +08:00
}
if (wIstr & USB_ISTR_ERR) {
2022-02-20 20:53:42 +08:00
USB->ISTR &= (uint16_t)(~USB_ISTR_ERR);
2021-12-04 19:28:20 +08:00
}
if (wIstr & USB_ISTR_WKUP) {
2022-02-20 20:53:42 +08:00
USB->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE);
USB->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
2021-12-04 19:28:20 +08:00
2022-02-20 20:53:42 +08:00
USB->ISTR &= (uint16_t)(~USB_ISTR_WKUP);
2021-12-04 19:28:20 +08:00
}
if (wIstr & USB_ISTR_SUSP) {
/* WA: To Clear Wakeup flag if raised with suspend signal */
/* Store Endpoint register */
for (uint8_t i = 0U; i < 8U; i++) {
2022-02-20 20:53:42 +08:00
store_ep[i] = PCD_GET_ENDPOINT(USB, i);
2021-12-04 19:28:20 +08:00
}
/* FORCE RESET */
2022-02-20 20:53:42 +08:00
USB->CNTR |= (uint16_t)(USB_CNTR_FRES);
2021-12-04 19:28:20 +08:00
/* CLEAR RESET */
2022-02-20 20:53:42 +08:00
USB->CNTR &= (uint16_t)(~USB_CNTR_FRES);
2021-12-04 19:28:20 +08:00
/* wait for reset flag in ISTR */
2022-02-20 20:53:42 +08:00
while ((USB->ISTR & USB_ISTR_RESET) == 0U) {
2021-12-04 19:28:20 +08:00
}
/* Clear Reset Flag */
2022-02-20 20:53:42 +08:00
USB->ISTR &= (uint16_t)(~USB_ISTR_RESET);
2021-12-04 19:28:20 +08:00
/* Restore Registre */
for (uint8_t i = 0U; i < 8U; i++) {
2022-02-20 20:53:42 +08:00
PCD_SET_ENDPOINT(USB, i, store_ep[i]);
2021-12-04 19:28:20 +08:00
}
/* Force low-power mode in the macrocell */
2022-02-20 20:53:42 +08:00
USB->CNTR |= (uint16_t)USB_CNTR_FSUSP;
2021-12-04 19:28:20 +08:00
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
2022-02-20 20:53:42 +08:00
USB->ISTR &= (uint16_t)(~USB_ISTR_SUSP);
2021-12-04 19:28:20 +08:00
2022-02-20 20:53:42 +08:00
USB->CNTR |= (uint16_t)USB_CNTR_LP_MODE;
2021-12-04 19:28:20 +08:00
}
if (wIstr & USB_ISTR_SOF) {
2022-02-20 20:53:42 +08:00
USB->ISTR &= (uint16_t)(~USB_ISTR_SOF);
2021-12-04 19:28:20 +08:00
}
if (wIstr & USB_ISTR_ESOF) {
2022-02-20 20:53:42 +08:00
USB->ISTR &= (uint16_t)(~USB_ISTR_ESOF);
2021-12-04 19:28:20 +08:00
}
}
2022-06-15 20:50:59 +08:00
static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
2021-12-04 19:28:20 +08:00
{
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
uint32_t BaseAddr = (uint32_t)USBx;
uint32_t i, temp1, temp2;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
for (i = n; i != 0U; i--) {
temp1 = *pBuf;
pBuf++;
temp2 = temp1 | ((uint16_t)((uint16_t)*pBuf << 8));
*pdwVal = (uint16_t)temp2;
pdwVal++;
#if PMA_ACCESS > 1U
pdwVal++;
#endif
pBuf++;
}
}
/**
* @brief Copy data from packet memory area (PMA) to user memory buffer
* @param USBx USB peripheral instance register address.
* @param pbUsrBuf pointer to user memory area.
* @param wPMABufAddr address into PMA.
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
2022-06-15 20:50:59 +08:00
static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
2021-12-04 19:28:20 +08:00
{
uint32_t n = (uint32_t)wNBytes >> 1;
uint32_t BaseAddr = (uint32_t)USBx;
uint32_t i, temp;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
for (i = n; i != 0U; i--) {
temp = *(__IO uint16_t *)pdwVal;
pdwVal++;
*pBuf = (uint8_t)((temp >> 0) & 0xFFU);
pBuf++;
*pBuf = (uint8_t)((temp >> 8) & 0xFFU);
pBuf++;
#if PMA_ACCESS > 1U
pdwVal++;
#endif
}
if ((wNBytes % 2U) != 0U) {
temp = *pdwVal;
*pBuf = (uint8_t)((temp >> 0) & 0xFFU);
}
}