diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403acct7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403acct7.s
deleted file mode 100644
index 9161d9e..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403acct7.s
+++ /dev/null
@@ -1,379 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403acct7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for keil
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD 0 ; Reserved
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
- EXPORT TMR1_OV_TMR10_IRQHandler [WEAK]
- EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
- EXPORT TMR1_CC_IRQHandler [WEAK]
- EXPORT TMR2_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR3_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR4_GLOBAL_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_I2S2EXT_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTCAlarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
- EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
- EXPORT TMR8_OV_TMR13_IRQHandler [WEAK]
- EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
- EXPORT TMR8_CC_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT TMR5_GLOBAL_IRQHandler [WEAK]
- EXPORT SPI3_I2S3EXT_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TMR6_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR7_GLOBAL_IRQHandler [WEAK]
- EXPORT DMA2_Channel1_IRQHandler [WEAK]
- EXPORT DMA2_Channel2_IRQHandler [WEAK]
- EXPORT DMA2_Channel3_IRQHandler [WEAK]
- EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
- EXPORT SDIO2_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT ACC_IRQHandler [WEAK]
- EXPORT USB_HP_IRQHandler [WEAK]
- EXPORT USB_LP_IRQHandler [WEAK]
- EXPORT DMA2_Channel6_7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TMR1_BRK_TMR9_IRQHandler
-TMR1_OV_TMR10_IRQHandler
-TMR1_TRG_COM_TMR11_IRQHandler
-TMR1_CC_IRQHandler
-TMR2_GLOBAL_IRQHandler
-TMR3_GLOBAL_IRQHandler
-TMR4_GLOBAL_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_I2S2EXT_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-TMR8_BRK_TMR12_IRQHandler
-TMR8_OV_TMR13_IRQHandler
-TMR8_TRG_COM_TMR14_IRQHandler
-TMR8_CC_IRQHandler
-ADC3_IRQHandler
-TMR5_GLOBAL_IRQHandler
-SPI3_I2S3EXT_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TMR6_GLOBAL_IRQHandler
-TMR7_GLOBAL_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-SDIO2_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-SPI4_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-ACC_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DMA2_Channel6_7_IRQHandler
-USART6_IRQHandler
-UART7_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403accu7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403accu7.s
deleted file mode 100644
index 3e5750d..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403accu7.s
+++ /dev/null
@@ -1,379 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403accu7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for keil
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD 0 ; Reserved
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
- EXPORT TMR1_OV_TMR10_IRQHandler [WEAK]
- EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
- EXPORT TMR1_CC_IRQHandler [WEAK]
- EXPORT TMR2_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR3_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR4_GLOBAL_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_I2S2EXT_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTCAlarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
- EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
- EXPORT TMR8_OV_TMR13_IRQHandler [WEAK]
- EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
- EXPORT TMR8_CC_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT TMR5_GLOBAL_IRQHandler [WEAK]
- EXPORT SPI3_I2S3EXT_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TMR6_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR7_GLOBAL_IRQHandler [WEAK]
- EXPORT DMA2_Channel1_IRQHandler [WEAK]
- EXPORT DMA2_Channel2_IRQHandler [WEAK]
- EXPORT DMA2_Channel3_IRQHandler [WEAK]
- EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
- EXPORT SDIO2_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT ACC_IRQHandler [WEAK]
- EXPORT USB_HP_IRQHandler [WEAK]
- EXPORT USB_LP_IRQHandler [WEAK]
- EXPORT DMA2_Channel6_7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TMR1_BRK_TMR9_IRQHandler
-TMR1_OV_TMR10_IRQHandler
-TMR1_TRG_COM_TMR11_IRQHandler
-TMR1_CC_IRQHandler
-TMR2_GLOBAL_IRQHandler
-TMR3_GLOBAL_IRQHandler
-TMR4_GLOBAL_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_I2S2EXT_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-TMR8_BRK_TMR12_IRQHandler
-TMR8_OV_TMR13_IRQHandler
-TMR8_TRG_COM_TMR14_IRQHandler
-TMR8_CC_IRQHandler
-ADC3_IRQHandler
-TMR5_GLOBAL_IRQHandler
-SPI3_I2S3EXT_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TMR6_GLOBAL_IRQHandler
-TMR7_GLOBAL_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-SDIO2_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-SPI4_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-ACC_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DMA2_Channel6_7_IRQHandler
-USART6_IRQHandler
-UART7_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403acet7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403acet7.s
deleted file mode 100644
index 8d49dcb..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403acet7.s
+++ /dev/null
@@ -1,379 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403acet7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for keil
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD 0 ; Reserved
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
- EXPORT TMR1_OV_TMR10_IRQHandler [WEAK]
- EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
- EXPORT TMR1_CC_IRQHandler [WEAK]
- EXPORT TMR2_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR3_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR4_GLOBAL_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_I2S2EXT_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTCAlarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
- EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
- EXPORT TMR8_OV_TMR13_IRQHandler [WEAK]
- EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
- EXPORT TMR8_CC_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT TMR5_GLOBAL_IRQHandler [WEAK]
- EXPORT SPI3_I2S3EXT_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TMR6_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR7_GLOBAL_IRQHandler [WEAK]
- EXPORT DMA2_Channel1_IRQHandler [WEAK]
- EXPORT DMA2_Channel2_IRQHandler [WEAK]
- EXPORT DMA2_Channel3_IRQHandler [WEAK]
- EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
- EXPORT SDIO2_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT ACC_IRQHandler [WEAK]
- EXPORT USB_HP_IRQHandler [WEAK]
- EXPORT USB_LP_IRQHandler [WEAK]
- EXPORT DMA2_Channel6_7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TMR1_BRK_TMR9_IRQHandler
-TMR1_OV_TMR10_IRQHandler
-TMR1_TRG_COM_TMR11_IRQHandler
-TMR1_CC_IRQHandler
-TMR2_GLOBAL_IRQHandler
-TMR3_GLOBAL_IRQHandler
-TMR4_GLOBAL_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_I2S2EXT_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-TMR8_BRK_TMR12_IRQHandler
-TMR8_OV_TMR13_IRQHandler
-TMR8_TRG_COM_TMR14_IRQHandler
-TMR8_CC_IRQHandler
-ADC3_IRQHandler
-TMR5_GLOBAL_IRQHandler
-SPI3_I2S3EXT_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TMR6_GLOBAL_IRQHandler
-TMR7_GLOBAL_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-SDIO2_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-SPI4_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-ACC_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DMA2_Channel6_7_IRQHandler
-USART6_IRQHandler
-UART7_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403aceu7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403aceu7.s
deleted file mode 100644
index c9ac871..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403aceu7.s
+++ /dev/null
@@ -1,379 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403aceu7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for keil
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD 0 ; Reserved
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
- EXPORT TMR1_OV_TMR10_IRQHandler [WEAK]
- EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
- EXPORT TMR1_CC_IRQHandler [WEAK]
- EXPORT TMR2_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR3_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR4_GLOBAL_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_I2S2EXT_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTCAlarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
- EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
- EXPORT TMR8_OV_TMR13_IRQHandler [WEAK]
- EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
- EXPORT TMR8_CC_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT TMR5_GLOBAL_IRQHandler [WEAK]
- EXPORT SPI3_I2S3EXT_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TMR6_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR7_GLOBAL_IRQHandler [WEAK]
- EXPORT DMA2_Channel1_IRQHandler [WEAK]
- EXPORT DMA2_Channel2_IRQHandler [WEAK]
- EXPORT DMA2_Channel3_IRQHandler [WEAK]
- EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
- EXPORT SDIO2_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT ACC_IRQHandler [WEAK]
- EXPORT USB_HP_IRQHandler [WEAK]
- EXPORT USB_LP_IRQHandler [WEAK]
- EXPORT DMA2_Channel6_7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TMR1_BRK_TMR9_IRQHandler
-TMR1_OV_TMR10_IRQHandler
-TMR1_TRG_COM_TMR11_IRQHandler
-TMR1_CC_IRQHandler
-TMR2_GLOBAL_IRQHandler
-TMR3_GLOBAL_IRQHandler
-TMR4_GLOBAL_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_I2S2EXT_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-TMR8_BRK_TMR12_IRQHandler
-TMR8_OV_TMR13_IRQHandler
-TMR8_TRG_COM_TMR14_IRQHandler
-TMR8_CC_IRQHandler
-ADC3_IRQHandler
-TMR5_GLOBAL_IRQHandler
-SPI3_I2S3EXT_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TMR6_GLOBAL_IRQHandler
-TMR7_GLOBAL_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-SDIO2_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-SPI4_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-ACC_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DMA2_Channel6_7_IRQHandler
-USART6_IRQHandler
-UART7_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403acgt7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403acgt7.s
deleted file mode 100644
index 7bc887a..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403acgt7.s
+++ /dev/null
@@ -1,379 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403acgt7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for keil
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD 0 ; Reserved
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
- EXPORT TMR1_OV_TMR10_IRQHandler [WEAK]
- EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
- EXPORT TMR1_CC_IRQHandler [WEAK]
- EXPORT TMR2_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR3_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR4_GLOBAL_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_I2S2EXT_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTCAlarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
- EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
- EXPORT TMR8_OV_TMR13_IRQHandler [WEAK]
- EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
- EXPORT TMR8_CC_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT TMR5_GLOBAL_IRQHandler [WEAK]
- EXPORT SPI3_I2S3EXT_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TMR6_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR7_GLOBAL_IRQHandler [WEAK]
- EXPORT DMA2_Channel1_IRQHandler [WEAK]
- EXPORT DMA2_Channel2_IRQHandler [WEAK]
- EXPORT DMA2_Channel3_IRQHandler [WEAK]
- EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
- EXPORT SDIO2_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT ACC_IRQHandler [WEAK]
- EXPORT USB_HP_IRQHandler [WEAK]
- EXPORT USB_LP_IRQHandler [WEAK]
- EXPORT DMA2_Channel6_7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TMR1_BRK_TMR9_IRQHandler
-TMR1_OV_TMR10_IRQHandler
-TMR1_TRG_COM_TMR11_IRQHandler
-TMR1_CC_IRQHandler
-TMR2_GLOBAL_IRQHandler
-TMR3_GLOBAL_IRQHandler
-TMR4_GLOBAL_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_I2S2EXT_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-TMR8_BRK_TMR12_IRQHandler
-TMR8_OV_TMR13_IRQHandler
-TMR8_TRG_COM_TMR14_IRQHandler
-TMR8_CC_IRQHandler
-ADC3_IRQHandler
-TMR5_GLOBAL_IRQHandler
-SPI3_I2S3EXT_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TMR6_GLOBAL_IRQHandler
-TMR7_GLOBAL_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-SDIO2_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-SPI4_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-ACC_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DMA2_Channel6_7_IRQHandler
-USART6_IRQHandler
-UART7_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403acgu7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403acgu7.s
deleted file mode 100644
index 606ef0b..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403acgu7.s
+++ /dev/null
@@ -1,379 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403acgu7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for keil
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD 0 ; Reserved
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
- EXPORT TMR1_OV_TMR10_IRQHandler [WEAK]
- EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
- EXPORT TMR1_CC_IRQHandler [WEAK]
- EXPORT TMR2_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR3_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR4_GLOBAL_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_I2S2EXT_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTCAlarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
- EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
- EXPORT TMR8_OV_TMR13_IRQHandler [WEAK]
- EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
- EXPORT TMR8_CC_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT TMR5_GLOBAL_IRQHandler [WEAK]
- EXPORT SPI3_I2S3EXT_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TMR6_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR7_GLOBAL_IRQHandler [WEAK]
- EXPORT DMA2_Channel1_IRQHandler [WEAK]
- EXPORT DMA2_Channel2_IRQHandler [WEAK]
- EXPORT DMA2_Channel3_IRQHandler [WEAK]
- EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
- EXPORT SDIO2_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT ACC_IRQHandler [WEAK]
- EXPORT USB_HP_IRQHandler [WEAK]
- EXPORT USB_LP_IRQHandler [WEAK]
- EXPORT DMA2_Channel6_7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TMR1_BRK_TMR9_IRQHandler
-TMR1_OV_TMR10_IRQHandler
-TMR1_TRG_COM_TMR11_IRQHandler
-TMR1_CC_IRQHandler
-TMR2_GLOBAL_IRQHandler
-TMR3_GLOBAL_IRQHandler
-TMR4_GLOBAL_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_I2S2EXT_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-TMR8_BRK_TMR12_IRQHandler
-TMR8_OV_TMR13_IRQHandler
-TMR8_TRG_COM_TMR14_IRQHandler
-TMR8_CC_IRQHandler
-ADC3_IRQHandler
-TMR5_GLOBAL_IRQHandler
-SPI3_I2S3EXT_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TMR6_GLOBAL_IRQHandler
-TMR7_GLOBAL_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-SDIO2_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-SPI4_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-ACC_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DMA2_Channel6_7_IRQHandler
-USART6_IRQHandler
-UART7_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403arct7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403arct7.s
deleted file mode 100644
index 1878cf5..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403arct7.s
+++ /dev/null
@@ -1,385 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403arct7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for keil
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD XMC_IRQHandler ; XMC
- DCD SDIO1_IRQHandler ; SDIO1
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
- EXPORT TMR1_OV_TMR10_IRQHandler [WEAK]
- EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
- EXPORT TMR1_CC_IRQHandler [WEAK]
- EXPORT TMR2_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR3_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR4_GLOBAL_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_I2S2EXT_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTCAlarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
- EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
- EXPORT TMR8_OV_TMR13_IRQHandler [WEAK]
- EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
- EXPORT TMR8_CC_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT XMC_IRQHandler [WEAK]
- EXPORT SDIO1_IRQHandler [WEAK]
- EXPORT TMR5_GLOBAL_IRQHandler [WEAK]
- EXPORT SPI3_I2S3EXT_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TMR6_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR7_GLOBAL_IRQHandler [WEAK]
- EXPORT DMA2_Channel1_IRQHandler [WEAK]
- EXPORT DMA2_Channel2_IRQHandler [WEAK]
- EXPORT DMA2_Channel3_IRQHandler [WEAK]
- EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
- EXPORT SDIO2_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT ACC_IRQHandler [WEAK]
- EXPORT USB_HP_IRQHandler [WEAK]
- EXPORT USB_LP_IRQHandler [WEAK]
- EXPORT DMA2_Channel6_7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TMR1_BRK_TMR9_IRQHandler
-TMR1_OV_TMR10_IRQHandler
-TMR1_TRG_COM_TMR11_IRQHandler
-TMR1_CC_IRQHandler
-TMR2_GLOBAL_IRQHandler
-TMR3_GLOBAL_IRQHandler
-TMR4_GLOBAL_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_I2S2EXT_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-TMR8_BRK_TMR12_IRQHandler
-TMR8_OV_TMR13_IRQHandler
-TMR8_TRG_COM_TMR14_IRQHandler
-TMR8_CC_IRQHandler
-ADC3_IRQHandler
-XMC_IRQHandler
-SDIO1_IRQHandler
-TMR5_GLOBAL_IRQHandler
-SPI3_I2S3EXT_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TMR6_GLOBAL_IRQHandler
-TMR7_GLOBAL_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-SDIO2_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-SPI4_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-ACC_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DMA2_Channel6_7_IRQHandler
-USART6_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403aret7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403aret7.s
deleted file mode 100644
index a2a4a98..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403aret7.s
+++ /dev/null
@@ -1,385 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403aret7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for keil
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD XMC_IRQHandler ; XMC
- DCD SDIO1_IRQHandler ; SDIO1
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
- EXPORT TMR1_OV_TMR10_IRQHandler [WEAK]
- EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
- EXPORT TMR1_CC_IRQHandler [WEAK]
- EXPORT TMR2_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR3_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR4_GLOBAL_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_I2S2EXT_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTCAlarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
- EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
- EXPORT TMR8_OV_TMR13_IRQHandler [WEAK]
- EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
- EXPORT TMR8_CC_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT XMC_IRQHandler [WEAK]
- EXPORT SDIO1_IRQHandler [WEAK]
- EXPORT TMR5_GLOBAL_IRQHandler [WEAK]
- EXPORT SPI3_I2S3EXT_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TMR6_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR7_GLOBAL_IRQHandler [WEAK]
- EXPORT DMA2_Channel1_IRQHandler [WEAK]
- EXPORT DMA2_Channel2_IRQHandler [WEAK]
- EXPORT DMA2_Channel3_IRQHandler [WEAK]
- EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
- EXPORT SDIO2_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT ACC_IRQHandler [WEAK]
- EXPORT USB_HP_IRQHandler [WEAK]
- EXPORT USB_LP_IRQHandler [WEAK]
- EXPORT DMA2_Channel6_7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TMR1_BRK_TMR9_IRQHandler
-TMR1_OV_TMR10_IRQHandler
-TMR1_TRG_COM_TMR11_IRQHandler
-TMR1_CC_IRQHandler
-TMR2_GLOBAL_IRQHandler
-TMR3_GLOBAL_IRQHandler
-TMR4_GLOBAL_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_I2S2EXT_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-TMR8_BRK_TMR12_IRQHandler
-TMR8_OV_TMR13_IRQHandler
-TMR8_TRG_COM_TMR14_IRQHandler
-TMR8_CC_IRQHandler
-ADC3_IRQHandler
-XMC_IRQHandler
-SDIO1_IRQHandler
-TMR5_GLOBAL_IRQHandler
-SPI3_I2S3EXT_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TMR6_GLOBAL_IRQHandler
-TMR7_GLOBAL_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-SDIO2_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-SPI4_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-ACC_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DMA2_Channel6_7_IRQHandler
-USART6_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403argt7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403argt7.s
deleted file mode 100644
index 93f7f30..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403argt7.s
+++ /dev/null
@@ -1,385 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403argt7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for keil
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD XMC_IRQHandler ; XMC
- DCD SDIO1_IRQHandler ; SDIO1
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
- EXPORT TMR1_OV_TMR10_IRQHandler [WEAK]
- EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
- EXPORT TMR1_CC_IRQHandler [WEAK]
- EXPORT TMR2_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR3_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR4_GLOBAL_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_I2S2EXT_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTCAlarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
- EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
- EXPORT TMR8_OV_TMR13_IRQHandler [WEAK]
- EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
- EXPORT TMR8_CC_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT XMC_IRQHandler [WEAK]
- EXPORT SDIO1_IRQHandler [WEAK]
- EXPORT TMR5_GLOBAL_IRQHandler [WEAK]
- EXPORT SPI3_I2S3EXT_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TMR6_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR7_GLOBAL_IRQHandler [WEAK]
- EXPORT DMA2_Channel1_IRQHandler [WEAK]
- EXPORT DMA2_Channel2_IRQHandler [WEAK]
- EXPORT DMA2_Channel3_IRQHandler [WEAK]
- EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
- EXPORT SDIO2_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT ACC_IRQHandler [WEAK]
- EXPORT USB_HP_IRQHandler [WEAK]
- EXPORT USB_LP_IRQHandler [WEAK]
- EXPORT DMA2_Channel6_7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TMR1_BRK_TMR9_IRQHandler
-TMR1_OV_TMR10_IRQHandler
-TMR1_TRG_COM_TMR11_IRQHandler
-TMR1_CC_IRQHandler
-TMR2_GLOBAL_IRQHandler
-TMR3_GLOBAL_IRQHandler
-TMR4_GLOBAL_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_I2S2EXT_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-TMR8_BRK_TMR12_IRQHandler
-TMR8_OV_TMR13_IRQHandler
-TMR8_TRG_COM_TMR14_IRQHandler
-TMR8_CC_IRQHandler
-ADC3_IRQHandler
-XMC_IRQHandler
-SDIO1_IRQHandler
-TMR5_GLOBAL_IRQHandler
-SPI3_I2S3EXT_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TMR6_GLOBAL_IRQHandler
-TMR7_GLOBAL_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-SDIO2_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-SPI4_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-ACC_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DMA2_Channel6_7_IRQHandler
-USART6_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403avct7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403avct7.s
deleted file mode 100644
index 6bd3e84..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403avct7.s
+++ /dev/null
@@ -1,385 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403avct7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for keil
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD XMC_IRQHandler ; XMC
- DCD SDIO1_IRQHandler ; SDIO1
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
- EXPORT TMR1_OV_TMR10_IRQHandler [WEAK]
- EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
- EXPORT TMR1_CC_IRQHandler [WEAK]
- EXPORT TMR2_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR3_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR4_GLOBAL_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_I2S2EXT_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTCAlarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
- EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
- EXPORT TMR8_OV_TMR13_IRQHandler [WEAK]
- EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
- EXPORT TMR8_CC_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT XMC_IRQHandler [WEAK]
- EXPORT SDIO1_IRQHandler [WEAK]
- EXPORT TMR5_GLOBAL_IRQHandler [WEAK]
- EXPORT SPI3_I2S3EXT_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TMR6_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR7_GLOBAL_IRQHandler [WEAK]
- EXPORT DMA2_Channel1_IRQHandler [WEAK]
- EXPORT DMA2_Channel2_IRQHandler [WEAK]
- EXPORT DMA2_Channel3_IRQHandler [WEAK]
- EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
- EXPORT SDIO2_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT ACC_IRQHandler [WEAK]
- EXPORT USB_HP_IRQHandler [WEAK]
- EXPORT USB_LP_IRQHandler [WEAK]
- EXPORT DMA2_Channel6_7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TMR1_BRK_TMR9_IRQHandler
-TMR1_OV_TMR10_IRQHandler
-TMR1_TRG_COM_TMR11_IRQHandler
-TMR1_CC_IRQHandler
-TMR2_GLOBAL_IRQHandler
-TMR3_GLOBAL_IRQHandler
-TMR4_GLOBAL_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_I2S2EXT_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-TMR8_BRK_TMR12_IRQHandler
-TMR8_OV_TMR13_IRQHandler
-TMR8_TRG_COM_TMR14_IRQHandler
-TMR8_CC_IRQHandler
-ADC3_IRQHandler
-XMC_IRQHandler
-SDIO1_IRQHandler
-TMR5_GLOBAL_IRQHandler
-SPI3_I2S3EXT_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TMR6_GLOBAL_IRQHandler
-TMR7_GLOBAL_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-SDIO2_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-SPI4_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-ACC_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DMA2_Channel6_7_IRQHandler
-USART6_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403avet7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403avet7.s
deleted file mode 100644
index c14164b..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403avet7.s
+++ /dev/null
@@ -1,385 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403avet7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for keil
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD XMC_IRQHandler ; XMC
- DCD SDIO1_IRQHandler ; SDIO1
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
- EXPORT TMR1_OV_TMR10_IRQHandler [WEAK]
- EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
- EXPORT TMR1_CC_IRQHandler [WEAK]
- EXPORT TMR2_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR3_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR4_GLOBAL_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_I2S2EXT_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTCAlarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
- EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
- EXPORT TMR8_OV_TMR13_IRQHandler [WEAK]
- EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
- EXPORT TMR8_CC_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT XMC_IRQHandler [WEAK]
- EXPORT SDIO1_IRQHandler [WEAK]
- EXPORT TMR5_GLOBAL_IRQHandler [WEAK]
- EXPORT SPI3_I2S3EXT_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TMR6_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR7_GLOBAL_IRQHandler [WEAK]
- EXPORT DMA2_Channel1_IRQHandler [WEAK]
- EXPORT DMA2_Channel2_IRQHandler [WEAK]
- EXPORT DMA2_Channel3_IRQHandler [WEAK]
- EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
- EXPORT SDIO2_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT ACC_IRQHandler [WEAK]
- EXPORT USB_HP_IRQHandler [WEAK]
- EXPORT USB_LP_IRQHandler [WEAK]
- EXPORT DMA2_Channel6_7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TMR1_BRK_TMR9_IRQHandler
-TMR1_OV_TMR10_IRQHandler
-TMR1_TRG_COM_TMR11_IRQHandler
-TMR1_CC_IRQHandler
-TMR2_GLOBAL_IRQHandler
-TMR3_GLOBAL_IRQHandler
-TMR4_GLOBAL_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_I2S2EXT_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-TMR8_BRK_TMR12_IRQHandler
-TMR8_OV_TMR13_IRQHandler
-TMR8_TRG_COM_TMR14_IRQHandler
-TMR8_CC_IRQHandler
-ADC3_IRQHandler
-XMC_IRQHandler
-SDIO1_IRQHandler
-TMR5_GLOBAL_IRQHandler
-SPI3_I2S3EXT_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TMR6_GLOBAL_IRQHandler
-TMR7_GLOBAL_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-SDIO2_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-SPI4_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-ACC_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DMA2_Channel6_7_IRQHandler
-USART6_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403avgt7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403avgt7.s
deleted file mode 100644
index 50595a8..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/arm/startup_at32f403avgt7.s
+++ /dev/null
@@ -1,385 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403avgt7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for keil
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD XMC_IRQHandler ; XMC
- DCD SDIO1_IRQHandler ; SDIO1
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
- EXPORT TMR1_OV_TMR10_IRQHandler [WEAK]
- EXPORT TMR1_TRG_COM_TMR11_IRQHandler [WEAK]
- EXPORT TMR1_CC_IRQHandler [WEAK]
- EXPORT TMR2_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR3_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR4_GLOBAL_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_I2S2EXT_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTCAlarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
- EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
- EXPORT TMR8_OV_TMR13_IRQHandler [WEAK]
- EXPORT TMR8_TRG_COM_TMR14_IRQHandler [WEAK]
- EXPORT TMR8_CC_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT XMC_IRQHandler [WEAK]
- EXPORT SDIO1_IRQHandler [WEAK]
- EXPORT TMR5_GLOBAL_IRQHandler [WEAK]
- EXPORT SPI3_I2S3EXT_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TMR6_GLOBAL_IRQHandler [WEAK]
- EXPORT TMR7_GLOBAL_IRQHandler [WEAK]
- EXPORT DMA2_Channel1_IRQHandler [WEAK]
- EXPORT DMA2_Channel2_IRQHandler [WEAK]
- EXPORT DMA2_Channel3_IRQHandler [WEAK]
- EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
- EXPORT SDIO2_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT CAN2_TX_IRQHandler [WEAK]
- EXPORT CAN2_RX0_IRQHandler [WEAK]
- EXPORT CAN2_RX1_IRQHandler [WEAK]
- EXPORT CAN2_SCE_IRQHandler [WEAK]
- EXPORT ACC_IRQHandler [WEAK]
- EXPORT USB_HP_IRQHandler [WEAK]
- EXPORT USB_LP_IRQHandler [WEAK]
- EXPORT DMA2_Channel6_7_IRQHandler [WEAK]
- EXPORT USART6_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT UART8_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN1_TX_IRQHandler
-USB_LP_CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TMR1_BRK_TMR9_IRQHandler
-TMR1_OV_TMR10_IRQHandler
-TMR1_TRG_COM_TMR11_IRQHandler
-TMR1_CC_IRQHandler
-TMR2_GLOBAL_IRQHandler
-TMR3_GLOBAL_IRQHandler
-TMR4_GLOBAL_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_I2S2EXT_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTCAlarm_IRQHandler
-USBWakeUp_IRQHandler
-TMR8_BRK_TMR12_IRQHandler
-TMR8_OV_TMR13_IRQHandler
-TMR8_TRG_COM_TMR14_IRQHandler
-TMR8_CC_IRQHandler
-ADC3_IRQHandler
-XMC_IRQHandler
-SDIO1_IRQHandler
-TMR5_GLOBAL_IRQHandler
-SPI3_I2S3EXT_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TMR6_GLOBAL_IRQHandler
-TMR7_GLOBAL_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_5_IRQHandler
-SDIO2_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-SPI4_IRQHandler
-CAN2_TX_IRQHandler
-CAN2_RX0_IRQHandler
-CAN2_RX1_IRQHandler
-CAN2_SCE_IRQHandler
-ACC_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DMA2_Channel6_7_IRQHandler
-USART6_IRQHandler
-UART7_IRQHandler
-UART8_IRQHandler
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/linker/AT32F403AxC.icf b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/linker/AT32F403AxC.icf
deleted file mode 100644
index ddcaf1e..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/linker/AT32F403AxC.icf
+++ /dev/null
@@ -1,30 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20037FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x1000;
-define symbol __ICFEDIT_size_heap__ = 0x1000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/linker/AT32F403AxE.icf b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/linker/AT32F403AxE.icf
deleted file mode 100644
index d850b6e..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/linker/AT32F403AxE.icf
+++ /dev/null
@@ -1,30 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20037FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x1000;
-define symbol __ICFEDIT_size_heap__ = 0x1000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/linker/AT32F403AxG.icf b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/linker/AT32F403AxG.icf
deleted file mode 100644
index f7b2272..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/linker/AT32F403AxG.icf
+++ /dev/null
@@ -1,30 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__ = 0x20037FFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x1000;
-define symbol __ICFEDIT_size_heap__ = 0x1000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403acct7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403acct7.s
deleted file mode 100644
index a94f271..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403acct7.s
+++ /dev/null
@@ -1,550 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403acct7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for IAR Systems
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD 0 ; Reserved
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMPER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_IRQHandler
- B TAMPER_IRQHandler
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
- PUBWEAK DMA1_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
- B DMA1_Channel2_IRQHandler
-
- PUBWEAK DMA1_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
- B DMA1_Channel3_IRQHandler
-
- PUBWEAK DMA1_Channel4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
- B DMA1_Channel4_IRQHandler
-
- PUBWEAK DMA1_Channel5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
- B DMA1_Channel5_IRQHandler
-
- PUBWEAK DMA1_Channel6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
- B DMA1_Channel6_IRQHandler
-
- PUBWEAK DMA1_Channel7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
- B DMA1_Channel7_IRQHandler
-
- PUBWEAK ADC1_2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_2_IRQHandler
- B ADC1_2_IRQHandler
-
- PUBWEAK USB_HP_CAN1_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_CAN1_TX_IRQHandler
- B USB_HP_CAN1_TX_IRQHandler
-
- PUBWEAK USB_LP_CAN1_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_CAN1_RX0_IRQHandler
- B USB_LP_CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler
- B CAN1_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TMR1_BRK_TMR9_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_BRK_TMR9_IRQHandler
- B TMR1_BRK_TMR9_IRQHandler
-
- PUBWEAK TMR1_OV_TMR10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_OV_TMR10_IRQHandler
- B TMR1_OV_TMR10_IRQHandler
-
- PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_TRG_COM_TMR11_IRQHandler
- B TMR1_TRG_COM_TMR11_IRQHandler
-
- PUBWEAK TMR1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_CC_IRQHandler
- B TMR1_CC_IRQHandler
-
- PUBWEAK TMR2_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR2_GLOBAL_IRQHandler
- B TMR2_GLOBAL_IRQHandler
-
- PUBWEAK TMR3_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR3_GLOBAL_IRQHandler
- B TMR3_GLOBAL_IRQHandler
-
- PUBWEAK TMR4_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR4_GLOBAL_IRQHandler
- B TMR4_GLOBAL_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_I2S2EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_I2S2EXT_IRQHandler
- B SPI2_I2S2EXT_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTCAlarm_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTCAlarm_IRQHandler
- B RTCAlarm_IRQHandler
-
- PUBWEAK USBWakeUp_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBWakeUp_IRQHandler
- B USBWakeUp_IRQHandler
-
- PUBWEAK TMR8_BRK_TMR12_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_BRK_TMR12_IRQHandler
- B TMR8_BRK_TMR12_IRQHandler
-
- PUBWEAK TMR8_OV_TMR13_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_OV_TMR13_IRQHandler
- B TMR8_OV_TMR13_IRQHandler
-
- PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_TRG_COM_TMR14_IRQHandler
- B TMR8_TRG_COM_TMR14_IRQHandler
-
- PUBWEAK TMR8_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_CC_IRQHandler
- B TMR8_CC_IRQHandler
-
- PUBWEAK ADC3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC3_IRQHandler
- B ADC3_IRQHandler
-
- PUBWEAK TMR5_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR5_GLOBAL_IRQHandler
- B TMR5_GLOBAL_IRQHandler
-
- PUBWEAK SPI3_I2S3EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_I2S3EXT_IRQHandler
- B SPI3_I2S3EXT_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TMR6_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR6_GLOBAL_IRQHandler
- B TMR6_GLOBAL_IRQHandler
-
- PUBWEAK TMR7_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR7_GLOBAL_IRQHandler
- B TMR7_GLOBAL_IRQHandler
-
- PUBWEAK DMA2_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
- B DMA2_Channel1_IRQHandler
-
- PUBWEAK DMA2_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
- B DMA2_Channel2_IRQHandler
-
- PUBWEAK DMA2_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
- B DMA2_Channel3_IRQHandler
-
- PUBWEAK DMA2_Channel4_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_5_IRQHandler
- B DMA2_Channel4_5_IRQHandler
-
- PUBWEAK SDIO2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO2_IRQHandler
- B SDIO2_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- PUBWEAK CAN2_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
- B CAN2_TX_IRQHandler
-
- PUBWEAK CAN2_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
- B CAN2_RX0_IRQHandler
-
- PUBWEAK CAN2_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
- B CAN2_RX1_IRQHandler
-
- PUBWEAK CAN2_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler
- B CAN2_SCE_IRQHandler
-
- PUBWEAK ACC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ACC_IRQHandler
- B ACC_IRQHandler
-
- PUBWEAK USB_HP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
- B USB_HP_IRQHandler
-
- PUBWEAK USB_LP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
- B USB_LP_IRQHandler
-
- PUBWEAK DMA2_Channel6_7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel6_7_IRQHandler
- B DMA2_Channel6_7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART7_IRQHandler
- B UART7_IRQHandler
-
- PUBWEAK UART8_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART8_IRQHandler
- B UART8_IRQHandler
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403accu7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403accu7.s
deleted file mode 100644
index cd3a4c9..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403accu7.s
+++ /dev/null
@@ -1,550 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403accu7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for IAR Systems
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD 0 ; Reserved
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMPER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_IRQHandler
- B TAMPER_IRQHandler
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
- PUBWEAK DMA1_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
- B DMA1_Channel2_IRQHandler
-
- PUBWEAK DMA1_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
- B DMA1_Channel3_IRQHandler
-
- PUBWEAK DMA1_Channel4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
- B DMA1_Channel4_IRQHandler
-
- PUBWEAK DMA1_Channel5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
- B DMA1_Channel5_IRQHandler
-
- PUBWEAK DMA1_Channel6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
- B DMA1_Channel6_IRQHandler
-
- PUBWEAK DMA1_Channel7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
- B DMA1_Channel7_IRQHandler
-
- PUBWEAK ADC1_2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_2_IRQHandler
- B ADC1_2_IRQHandler
-
- PUBWEAK USB_HP_CAN1_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_CAN1_TX_IRQHandler
- B USB_HP_CAN1_TX_IRQHandler
-
- PUBWEAK USB_LP_CAN1_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_CAN1_RX0_IRQHandler
- B USB_LP_CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler
- B CAN1_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TMR1_BRK_TMR9_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_BRK_TMR9_IRQHandler
- B TMR1_BRK_TMR9_IRQHandler
-
- PUBWEAK TMR1_OV_TMR10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_OV_TMR10_IRQHandler
- B TMR1_OV_TMR10_IRQHandler
-
- PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_TRG_COM_TMR11_IRQHandler
- B TMR1_TRG_COM_TMR11_IRQHandler
-
- PUBWEAK TMR1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_CC_IRQHandler
- B TMR1_CC_IRQHandler
-
- PUBWEAK TMR2_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR2_GLOBAL_IRQHandler
- B TMR2_GLOBAL_IRQHandler
-
- PUBWEAK TMR3_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR3_GLOBAL_IRQHandler
- B TMR3_GLOBAL_IRQHandler
-
- PUBWEAK TMR4_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR4_GLOBAL_IRQHandler
- B TMR4_GLOBAL_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_I2S2EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_I2S2EXT_IRQHandler
- B SPI2_I2S2EXT_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTCAlarm_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTCAlarm_IRQHandler
- B RTCAlarm_IRQHandler
-
- PUBWEAK USBWakeUp_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBWakeUp_IRQHandler
- B USBWakeUp_IRQHandler
-
- PUBWEAK TMR8_BRK_TMR12_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_BRK_TMR12_IRQHandler
- B TMR8_BRK_TMR12_IRQHandler
-
- PUBWEAK TMR8_OV_TMR13_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_OV_TMR13_IRQHandler
- B TMR8_OV_TMR13_IRQHandler
-
- PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_TRG_COM_TMR14_IRQHandler
- B TMR8_TRG_COM_TMR14_IRQHandler
-
- PUBWEAK TMR8_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_CC_IRQHandler
- B TMR8_CC_IRQHandler
-
- PUBWEAK ADC3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC3_IRQHandler
- B ADC3_IRQHandler
-
- PUBWEAK TMR5_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR5_GLOBAL_IRQHandler
- B TMR5_GLOBAL_IRQHandler
-
- PUBWEAK SPI3_I2S3EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_I2S3EXT_IRQHandler
- B SPI3_I2S3EXT_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TMR6_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR6_GLOBAL_IRQHandler
- B TMR6_GLOBAL_IRQHandler
-
- PUBWEAK TMR7_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR7_GLOBAL_IRQHandler
- B TMR7_GLOBAL_IRQHandler
-
- PUBWEAK DMA2_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
- B DMA2_Channel1_IRQHandler
-
- PUBWEAK DMA2_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
- B DMA2_Channel2_IRQHandler
-
- PUBWEAK DMA2_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
- B DMA2_Channel3_IRQHandler
-
- PUBWEAK DMA2_Channel4_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_5_IRQHandler
- B DMA2_Channel4_5_IRQHandler
-
- PUBWEAK SDIO2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO2_IRQHandler
- B SDIO2_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- PUBWEAK CAN2_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
- B CAN2_TX_IRQHandler
-
- PUBWEAK CAN2_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
- B CAN2_RX0_IRQHandler
-
- PUBWEAK CAN2_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
- B CAN2_RX1_IRQHandler
-
- PUBWEAK CAN2_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler
- B CAN2_SCE_IRQHandler
-
- PUBWEAK ACC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ACC_IRQHandler
- B ACC_IRQHandler
-
- PUBWEAK USB_HP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
- B USB_HP_IRQHandler
-
- PUBWEAK USB_LP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
- B USB_LP_IRQHandler
-
- PUBWEAK DMA2_Channel6_7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel6_7_IRQHandler
- B DMA2_Channel6_7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART7_IRQHandler
- B UART7_IRQHandler
-
- PUBWEAK UART8_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART8_IRQHandler
- B UART8_IRQHandler
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403acet7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403acet7.s
deleted file mode 100644
index 57856c0..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403acet7.s
+++ /dev/null
@@ -1,550 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403acet7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for IAR Systems
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD 0 ; Reserved
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMPER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_IRQHandler
- B TAMPER_IRQHandler
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
- PUBWEAK DMA1_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
- B DMA1_Channel2_IRQHandler
-
- PUBWEAK DMA1_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
- B DMA1_Channel3_IRQHandler
-
- PUBWEAK DMA1_Channel4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
- B DMA1_Channel4_IRQHandler
-
- PUBWEAK DMA1_Channel5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
- B DMA1_Channel5_IRQHandler
-
- PUBWEAK DMA1_Channel6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
- B DMA1_Channel6_IRQHandler
-
- PUBWEAK DMA1_Channel7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
- B DMA1_Channel7_IRQHandler
-
- PUBWEAK ADC1_2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_2_IRQHandler
- B ADC1_2_IRQHandler
-
- PUBWEAK USB_HP_CAN1_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_CAN1_TX_IRQHandler
- B USB_HP_CAN1_TX_IRQHandler
-
- PUBWEAK USB_LP_CAN1_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_CAN1_RX0_IRQHandler
- B USB_LP_CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler
- B CAN1_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TMR1_BRK_TMR9_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_BRK_TMR9_IRQHandler
- B TMR1_BRK_TMR9_IRQHandler
-
- PUBWEAK TMR1_OV_TMR10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_OV_TMR10_IRQHandler
- B TMR1_OV_TMR10_IRQHandler
-
- PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_TRG_COM_TMR11_IRQHandler
- B TMR1_TRG_COM_TMR11_IRQHandler
-
- PUBWEAK TMR1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_CC_IRQHandler
- B TMR1_CC_IRQHandler
-
- PUBWEAK TMR2_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR2_GLOBAL_IRQHandler
- B TMR2_GLOBAL_IRQHandler
-
- PUBWEAK TMR3_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR3_GLOBAL_IRQHandler
- B TMR3_GLOBAL_IRQHandler
-
- PUBWEAK TMR4_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR4_GLOBAL_IRQHandler
- B TMR4_GLOBAL_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_I2S2EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_I2S2EXT_IRQHandler
- B SPI2_I2S2EXT_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTCAlarm_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTCAlarm_IRQHandler
- B RTCAlarm_IRQHandler
-
- PUBWEAK USBWakeUp_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBWakeUp_IRQHandler
- B USBWakeUp_IRQHandler
-
- PUBWEAK TMR8_BRK_TMR12_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_BRK_TMR12_IRQHandler
- B TMR8_BRK_TMR12_IRQHandler
-
- PUBWEAK TMR8_OV_TMR13_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_OV_TMR13_IRQHandler
- B TMR8_OV_TMR13_IRQHandler
-
- PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_TRG_COM_TMR14_IRQHandler
- B TMR8_TRG_COM_TMR14_IRQHandler
-
- PUBWEAK TMR8_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_CC_IRQHandler
- B TMR8_CC_IRQHandler
-
- PUBWEAK ADC3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC3_IRQHandler
- B ADC3_IRQHandler
-
- PUBWEAK TMR5_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR5_GLOBAL_IRQHandler
- B TMR5_GLOBAL_IRQHandler
-
- PUBWEAK SPI3_I2S3EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_I2S3EXT_IRQHandler
- B SPI3_I2S3EXT_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TMR6_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR6_GLOBAL_IRQHandler
- B TMR6_GLOBAL_IRQHandler
-
- PUBWEAK TMR7_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR7_GLOBAL_IRQHandler
- B TMR7_GLOBAL_IRQHandler
-
- PUBWEAK DMA2_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
- B DMA2_Channel1_IRQHandler
-
- PUBWEAK DMA2_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
- B DMA2_Channel2_IRQHandler
-
- PUBWEAK DMA2_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
- B DMA2_Channel3_IRQHandler
-
- PUBWEAK DMA2_Channel4_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_5_IRQHandler
- B DMA2_Channel4_5_IRQHandler
-
- PUBWEAK SDIO2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO2_IRQHandler
- B SDIO2_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- PUBWEAK CAN2_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
- B CAN2_TX_IRQHandler
-
- PUBWEAK CAN2_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
- B CAN2_RX0_IRQHandler
-
- PUBWEAK CAN2_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
- B CAN2_RX1_IRQHandler
-
- PUBWEAK CAN2_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler
- B CAN2_SCE_IRQHandler
-
- PUBWEAK ACC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ACC_IRQHandler
- B ACC_IRQHandler
-
- PUBWEAK USB_HP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
- B USB_HP_IRQHandler
-
- PUBWEAK USB_LP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
- B USB_LP_IRQHandler
-
- PUBWEAK DMA2_Channel6_7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel6_7_IRQHandler
- B DMA2_Channel6_7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART7_IRQHandler
- B UART7_IRQHandler
-
- PUBWEAK UART8_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART8_IRQHandler
- B UART8_IRQHandler
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403aceu7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403aceu7.s
deleted file mode 100644
index 2d0f7f4..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403aceu7.s
+++ /dev/null
@@ -1,550 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403aceu7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for IAR Systems
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD 0 ; Reserved
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMPER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_IRQHandler
- B TAMPER_IRQHandler
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
- PUBWEAK DMA1_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
- B DMA1_Channel2_IRQHandler
-
- PUBWEAK DMA1_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
- B DMA1_Channel3_IRQHandler
-
- PUBWEAK DMA1_Channel4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
- B DMA1_Channel4_IRQHandler
-
- PUBWEAK DMA1_Channel5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
- B DMA1_Channel5_IRQHandler
-
- PUBWEAK DMA1_Channel6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
- B DMA1_Channel6_IRQHandler
-
- PUBWEAK DMA1_Channel7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
- B DMA1_Channel7_IRQHandler
-
- PUBWEAK ADC1_2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_2_IRQHandler
- B ADC1_2_IRQHandler
-
- PUBWEAK USB_HP_CAN1_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_CAN1_TX_IRQHandler
- B USB_HP_CAN1_TX_IRQHandler
-
- PUBWEAK USB_LP_CAN1_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_CAN1_RX0_IRQHandler
- B USB_LP_CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler
- B CAN1_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TMR1_BRK_TMR9_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_BRK_TMR9_IRQHandler
- B TMR1_BRK_TMR9_IRQHandler
-
- PUBWEAK TMR1_OV_TMR10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_OV_TMR10_IRQHandler
- B TMR1_OV_TMR10_IRQHandler
-
- PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_TRG_COM_TMR11_IRQHandler
- B TMR1_TRG_COM_TMR11_IRQHandler
-
- PUBWEAK TMR1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_CC_IRQHandler
- B TMR1_CC_IRQHandler
-
- PUBWEAK TMR2_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR2_GLOBAL_IRQHandler
- B TMR2_GLOBAL_IRQHandler
-
- PUBWEAK TMR3_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR3_GLOBAL_IRQHandler
- B TMR3_GLOBAL_IRQHandler
-
- PUBWEAK TMR4_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR4_GLOBAL_IRQHandler
- B TMR4_GLOBAL_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_I2S2EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_I2S2EXT_IRQHandler
- B SPI2_I2S2EXT_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTCAlarm_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTCAlarm_IRQHandler
- B RTCAlarm_IRQHandler
-
- PUBWEAK USBWakeUp_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBWakeUp_IRQHandler
- B USBWakeUp_IRQHandler
-
- PUBWEAK TMR8_BRK_TMR12_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_BRK_TMR12_IRQHandler
- B TMR8_BRK_TMR12_IRQHandler
-
- PUBWEAK TMR8_OV_TMR13_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_OV_TMR13_IRQHandler
- B TMR8_OV_TMR13_IRQHandler
-
- PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_TRG_COM_TMR14_IRQHandler
- B TMR8_TRG_COM_TMR14_IRQHandler
-
- PUBWEAK TMR8_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_CC_IRQHandler
- B TMR8_CC_IRQHandler
-
- PUBWEAK ADC3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC3_IRQHandler
- B ADC3_IRQHandler
-
- PUBWEAK TMR5_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR5_GLOBAL_IRQHandler
- B TMR5_GLOBAL_IRQHandler
-
- PUBWEAK SPI3_I2S3EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_I2S3EXT_IRQHandler
- B SPI3_I2S3EXT_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TMR6_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR6_GLOBAL_IRQHandler
- B TMR6_GLOBAL_IRQHandler
-
- PUBWEAK TMR7_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR7_GLOBAL_IRQHandler
- B TMR7_GLOBAL_IRQHandler
-
- PUBWEAK DMA2_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
- B DMA2_Channel1_IRQHandler
-
- PUBWEAK DMA2_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
- B DMA2_Channel2_IRQHandler
-
- PUBWEAK DMA2_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
- B DMA2_Channel3_IRQHandler
-
- PUBWEAK DMA2_Channel4_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_5_IRQHandler
- B DMA2_Channel4_5_IRQHandler
-
- PUBWEAK SDIO2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO2_IRQHandler
- B SDIO2_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- PUBWEAK CAN2_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
- B CAN2_TX_IRQHandler
-
- PUBWEAK CAN2_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
- B CAN2_RX0_IRQHandler
-
- PUBWEAK CAN2_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
- B CAN2_RX1_IRQHandler
-
- PUBWEAK CAN2_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler
- B CAN2_SCE_IRQHandler
-
- PUBWEAK ACC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ACC_IRQHandler
- B ACC_IRQHandler
-
- PUBWEAK USB_HP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
- B USB_HP_IRQHandler
-
- PUBWEAK USB_LP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
- B USB_LP_IRQHandler
-
- PUBWEAK DMA2_Channel6_7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel6_7_IRQHandler
- B DMA2_Channel6_7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART7_IRQHandler
- B UART7_IRQHandler
-
- PUBWEAK UART8_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART8_IRQHandler
- B UART8_IRQHandler
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403acgt7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403acgt7.s
deleted file mode 100644
index a72c2ce..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403acgt7.s
+++ /dev/null
@@ -1,550 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403acgt7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for IAR Systems
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD 0 ; Reserved
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMPER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_IRQHandler
- B TAMPER_IRQHandler
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
- PUBWEAK DMA1_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
- B DMA1_Channel2_IRQHandler
-
- PUBWEAK DMA1_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
- B DMA1_Channel3_IRQHandler
-
- PUBWEAK DMA1_Channel4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
- B DMA1_Channel4_IRQHandler
-
- PUBWEAK DMA1_Channel5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
- B DMA1_Channel5_IRQHandler
-
- PUBWEAK DMA1_Channel6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
- B DMA1_Channel6_IRQHandler
-
- PUBWEAK DMA1_Channel7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
- B DMA1_Channel7_IRQHandler
-
- PUBWEAK ADC1_2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_2_IRQHandler
- B ADC1_2_IRQHandler
-
- PUBWEAK USB_HP_CAN1_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_CAN1_TX_IRQHandler
- B USB_HP_CAN1_TX_IRQHandler
-
- PUBWEAK USB_LP_CAN1_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_CAN1_RX0_IRQHandler
- B USB_LP_CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler
- B CAN1_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TMR1_BRK_TMR9_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_BRK_TMR9_IRQHandler
- B TMR1_BRK_TMR9_IRQHandler
-
- PUBWEAK TMR1_OV_TMR10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_OV_TMR10_IRQHandler
- B TMR1_OV_TMR10_IRQHandler
-
- PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_TRG_COM_TMR11_IRQHandler
- B TMR1_TRG_COM_TMR11_IRQHandler
-
- PUBWEAK TMR1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_CC_IRQHandler
- B TMR1_CC_IRQHandler
-
- PUBWEAK TMR2_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR2_GLOBAL_IRQHandler
- B TMR2_GLOBAL_IRQHandler
-
- PUBWEAK TMR3_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR3_GLOBAL_IRQHandler
- B TMR3_GLOBAL_IRQHandler
-
- PUBWEAK TMR4_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR4_GLOBAL_IRQHandler
- B TMR4_GLOBAL_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_I2S2EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_I2S2EXT_IRQHandler
- B SPI2_I2S2EXT_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTCAlarm_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTCAlarm_IRQHandler
- B RTCAlarm_IRQHandler
-
- PUBWEAK USBWakeUp_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBWakeUp_IRQHandler
- B USBWakeUp_IRQHandler
-
- PUBWEAK TMR8_BRK_TMR12_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_BRK_TMR12_IRQHandler
- B TMR8_BRK_TMR12_IRQHandler
-
- PUBWEAK TMR8_OV_TMR13_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_OV_TMR13_IRQHandler
- B TMR8_OV_TMR13_IRQHandler
-
- PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_TRG_COM_TMR14_IRQHandler
- B TMR8_TRG_COM_TMR14_IRQHandler
-
- PUBWEAK TMR8_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_CC_IRQHandler
- B TMR8_CC_IRQHandler
-
- PUBWEAK ADC3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC3_IRQHandler
- B ADC3_IRQHandler
-
- PUBWEAK TMR5_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR5_GLOBAL_IRQHandler
- B TMR5_GLOBAL_IRQHandler
-
- PUBWEAK SPI3_I2S3EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_I2S3EXT_IRQHandler
- B SPI3_I2S3EXT_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TMR6_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR6_GLOBAL_IRQHandler
- B TMR6_GLOBAL_IRQHandler
-
- PUBWEAK TMR7_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR7_GLOBAL_IRQHandler
- B TMR7_GLOBAL_IRQHandler
-
- PUBWEAK DMA2_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
- B DMA2_Channel1_IRQHandler
-
- PUBWEAK DMA2_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
- B DMA2_Channel2_IRQHandler
-
- PUBWEAK DMA2_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
- B DMA2_Channel3_IRQHandler
-
- PUBWEAK DMA2_Channel4_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_5_IRQHandler
- B DMA2_Channel4_5_IRQHandler
-
- PUBWEAK SDIO2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO2_IRQHandler
- B SDIO2_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- PUBWEAK CAN2_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
- B CAN2_TX_IRQHandler
-
- PUBWEAK CAN2_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
- B CAN2_RX0_IRQHandler
-
- PUBWEAK CAN2_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
- B CAN2_RX1_IRQHandler
-
- PUBWEAK CAN2_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler
- B CAN2_SCE_IRQHandler
-
- PUBWEAK ACC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ACC_IRQHandler
- B ACC_IRQHandler
-
- PUBWEAK USB_HP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
- B USB_HP_IRQHandler
-
- PUBWEAK USB_LP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
- B USB_LP_IRQHandler
-
- PUBWEAK DMA2_Channel6_7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel6_7_IRQHandler
- B DMA2_Channel6_7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART7_IRQHandler
- B UART7_IRQHandler
-
- PUBWEAK UART8_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART8_IRQHandler
- B UART8_IRQHandler
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403acgu7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403acgu7.s
deleted file mode 100644
index 1fd3100..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403acgu7.s
+++ /dev/null
@@ -1,550 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403acgu7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for IAR Systems
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD 0 ; Reserved
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMPER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_IRQHandler
- B TAMPER_IRQHandler
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
- PUBWEAK DMA1_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
- B DMA1_Channel2_IRQHandler
-
- PUBWEAK DMA1_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
- B DMA1_Channel3_IRQHandler
-
- PUBWEAK DMA1_Channel4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
- B DMA1_Channel4_IRQHandler
-
- PUBWEAK DMA1_Channel5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
- B DMA1_Channel5_IRQHandler
-
- PUBWEAK DMA1_Channel6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
- B DMA1_Channel6_IRQHandler
-
- PUBWEAK DMA1_Channel7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
- B DMA1_Channel7_IRQHandler
-
- PUBWEAK ADC1_2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_2_IRQHandler
- B ADC1_2_IRQHandler
-
- PUBWEAK USB_HP_CAN1_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_CAN1_TX_IRQHandler
- B USB_HP_CAN1_TX_IRQHandler
-
- PUBWEAK USB_LP_CAN1_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_CAN1_RX0_IRQHandler
- B USB_LP_CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler
- B CAN1_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TMR1_BRK_TMR9_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_BRK_TMR9_IRQHandler
- B TMR1_BRK_TMR9_IRQHandler
-
- PUBWEAK TMR1_OV_TMR10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_OV_TMR10_IRQHandler
- B TMR1_OV_TMR10_IRQHandler
-
- PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_TRG_COM_TMR11_IRQHandler
- B TMR1_TRG_COM_TMR11_IRQHandler
-
- PUBWEAK TMR1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_CC_IRQHandler
- B TMR1_CC_IRQHandler
-
- PUBWEAK TMR2_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR2_GLOBAL_IRQHandler
- B TMR2_GLOBAL_IRQHandler
-
- PUBWEAK TMR3_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR3_GLOBAL_IRQHandler
- B TMR3_GLOBAL_IRQHandler
-
- PUBWEAK TMR4_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR4_GLOBAL_IRQHandler
- B TMR4_GLOBAL_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_I2S2EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_I2S2EXT_IRQHandler
- B SPI2_I2S2EXT_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTCAlarm_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTCAlarm_IRQHandler
- B RTCAlarm_IRQHandler
-
- PUBWEAK USBWakeUp_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBWakeUp_IRQHandler
- B USBWakeUp_IRQHandler
-
- PUBWEAK TMR8_BRK_TMR12_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_BRK_TMR12_IRQHandler
- B TMR8_BRK_TMR12_IRQHandler
-
- PUBWEAK TMR8_OV_TMR13_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_OV_TMR13_IRQHandler
- B TMR8_OV_TMR13_IRQHandler
-
- PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_TRG_COM_TMR14_IRQHandler
- B TMR8_TRG_COM_TMR14_IRQHandler
-
- PUBWEAK TMR8_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_CC_IRQHandler
- B TMR8_CC_IRQHandler
-
- PUBWEAK ADC3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC3_IRQHandler
- B ADC3_IRQHandler
-
- PUBWEAK TMR5_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR5_GLOBAL_IRQHandler
- B TMR5_GLOBAL_IRQHandler
-
- PUBWEAK SPI3_I2S3EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_I2S3EXT_IRQHandler
- B SPI3_I2S3EXT_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TMR6_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR6_GLOBAL_IRQHandler
- B TMR6_GLOBAL_IRQHandler
-
- PUBWEAK TMR7_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR7_GLOBAL_IRQHandler
- B TMR7_GLOBAL_IRQHandler
-
- PUBWEAK DMA2_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
- B DMA2_Channel1_IRQHandler
-
- PUBWEAK DMA2_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
- B DMA2_Channel2_IRQHandler
-
- PUBWEAK DMA2_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
- B DMA2_Channel3_IRQHandler
-
- PUBWEAK DMA2_Channel4_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_5_IRQHandler
- B DMA2_Channel4_5_IRQHandler
-
- PUBWEAK SDIO2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO2_IRQHandler
- B SDIO2_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- PUBWEAK CAN2_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
- B CAN2_TX_IRQHandler
-
- PUBWEAK CAN2_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
- B CAN2_RX0_IRQHandler
-
- PUBWEAK CAN2_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
- B CAN2_RX1_IRQHandler
-
- PUBWEAK CAN2_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler
- B CAN2_SCE_IRQHandler
-
- PUBWEAK ACC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ACC_IRQHandler
- B ACC_IRQHandler
-
- PUBWEAK USB_HP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
- B USB_HP_IRQHandler
-
- PUBWEAK USB_LP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
- B USB_LP_IRQHandler
-
- PUBWEAK DMA2_Channel6_7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel6_7_IRQHandler
- B DMA2_Channel6_7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART7_IRQHandler
- B UART7_IRQHandler
-
- PUBWEAK UART8_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART8_IRQHandler
- B UART8_IRQHandler
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403arct7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403arct7.s
deleted file mode 100644
index 691ee8c..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403arct7.s
+++ /dev/null
@@ -1,560 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403arct7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for IAR Systems
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD XMC_IRQHandler ; XMC
- DCD SDIO1_IRQHandler ; SDIO1
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMPER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_IRQHandler
- B TAMPER_IRQHandler
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
- PUBWEAK DMA1_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
- B DMA1_Channel2_IRQHandler
-
- PUBWEAK DMA1_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
- B DMA1_Channel3_IRQHandler
-
- PUBWEAK DMA1_Channel4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
- B DMA1_Channel4_IRQHandler
-
- PUBWEAK DMA1_Channel5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
- B DMA1_Channel5_IRQHandler
-
- PUBWEAK DMA1_Channel6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
- B DMA1_Channel6_IRQHandler
-
- PUBWEAK DMA1_Channel7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
- B DMA1_Channel7_IRQHandler
-
- PUBWEAK ADC1_2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_2_IRQHandler
- B ADC1_2_IRQHandler
-
- PUBWEAK USB_HP_CAN1_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_CAN1_TX_IRQHandler
- B USB_HP_CAN1_TX_IRQHandler
-
- PUBWEAK USB_LP_CAN1_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_CAN1_RX0_IRQHandler
- B USB_LP_CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler
- B CAN1_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TMR1_BRK_TMR9_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_BRK_TMR9_IRQHandler
- B TMR1_BRK_TMR9_IRQHandler
-
- PUBWEAK TMR1_OV_TMR10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_OV_TMR10_IRQHandler
- B TMR1_OV_TMR10_IRQHandler
-
- PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_TRG_COM_TMR11_IRQHandler
- B TMR1_TRG_COM_TMR11_IRQHandler
-
- PUBWEAK TMR1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_CC_IRQHandler
- B TMR1_CC_IRQHandler
-
- PUBWEAK TMR2_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR2_GLOBAL_IRQHandler
- B TMR2_GLOBAL_IRQHandler
-
- PUBWEAK TMR3_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR3_GLOBAL_IRQHandler
- B TMR3_GLOBAL_IRQHandler
-
- PUBWEAK TMR4_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR4_GLOBAL_IRQHandler
- B TMR4_GLOBAL_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_I2S2EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_I2S2EXT_IRQHandler
- B SPI2_I2S2EXT_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTCAlarm_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTCAlarm_IRQHandler
- B RTCAlarm_IRQHandler
-
- PUBWEAK USBWakeUp_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBWakeUp_IRQHandler
- B USBWakeUp_IRQHandler
-
- PUBWEAK TMR8_BRK_TMR12_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_BRK_TMR12_IRQHandler
- B TMR8_BRK_TMR12_IRQHandler
-
- PUBWEAK TMR8_OV_TMR13_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_OV_TMR13_IRQHandler
- B TMR8_OV_TMR13_IRQHandler
-
- PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_TRG_COM_TMR14_IRQHandler
- B TMR8_TRG_COM_TMR14_IRQHandler
-
- PUBWEAK TMR8_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_CC_IRQHandler
- B TMR8_CC_IRQHandler
-
- PUBWEAK ADC3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC3_IRQHandler
- B ADC3_IRQHandler
-
- PUBWEAK XMC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-XMC_IRQHandler
- B XMC_IRQHandler
-
- PUBWEAK SDIO1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO1_IRQHandler
- B SDIO1_IRQHandler
-
- PUBWEAK TMR5_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR5_GLOBAL_IRQHandler
- B TMR5_GLOBAL_IRQHandler
-
- PUBWEAK SPI3_I2S3EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_I2S3EXT_IRQHandler
- B SPI3_I2S3EXT_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TMR6_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR6_GLOBAL_IRQHandler
- B TMR6_GLOBAL_IRQHandler
-
- PUBWEAK TMR7_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR7_GLOBAL_IRQHandler
- B TMR7_GLOBAL_IRQHandler
-
- PUBWEAK DMA2_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
- B DMA2_Channel1_IRQHandler
-
- PUBWEAK DMA2_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
- B DMA2_Channel2_IRQHandler
-
- PUBWEAK DMA2_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
- B DMA2_Channel3_IRQHandler
-
- PUBWEAK DMA2_Channel4_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_5_IRQHandler
- B DMA2_Channel4_5_IRQHandler
-
- PUBWEAK SDIO2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO2_IRQHandler
- B SDIO2_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- PUBWEAK CAN2_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
- B CAN2_TX_IRQHandler
-
- PUBWEAK CAN2_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
- B CAN2_RX0_IRQHandler
-
- PUBWEAK CAN2_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
- B CAN2_RX1_IRQHandler
-
- PUBWEAK CAN2_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler
- B CAN2_SCE_IRQHandler
-
- PUBWEAK ACC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ACC_IRQHandler
- B ACC_IRQHandler
-
- PUBWEAK USB_HP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
- B USB_HP_IRQHandler
-
- PUBWEAK USB_LP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
- B USB_LP_IRQHandler
-
- PUBWEAK DMA2_Channel6_7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel6_7_IRQHandler
- B DMA2_Channel6_7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART7_IRQHandler
- B UART7_IRQHandler
-
- PUBWEAK UART8_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART8_IRQHandler
- B UART8_IRQHandler
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403aret7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403aret7.s
deleted file mode 100644
index f96d3ad..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403aret7.s
+++ /dev/null
@@ -1,560 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403aret7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for IAR Systems
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD XMC_IRQHandler ; XMC
- DCD SDIO1_IRQHandler ; SDIO1
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMPER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_IRQHandler
- B TAMPER_IRQHandler
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
- PUBWEAK DMA1_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
- B DMA1_Channel2_IRQHandler
-
- PUBWEAK DMA1_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
- B DMA1_Channel3_IRQHandler
-
- PUBWEAK DMA1_Channel4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
- B DMA1_Channel4_IRQHandler
-
- PUBWEAK DMA1_Channel5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
- B DMA1_Channel5_IRQHandler
-
- PUBWEAK DMA1_Channel6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
- B DMA1_Channel6_IRQHandler
-
- PUBWEAK DMA1_Channel7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
- B DMA1_Channel7_IRQHandler
-
- PUBWEAK ADC1_2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_2_IRQHandler
- B ADC1_2_IRQHandler
-
- PUBWEAK USB_HP_CAN1_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_CAN1_TX_IRQHandler
- B USB_HP_CAN1_TX_IRQHandler
-
- PUBWEAK USB_LP_CAN1_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_CAN1_RX0_IRQHandler
- B USB_LP_CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler
- B CAN1_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TMR1_BRK_TMR9_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_BRK_TMR9_IRQHandler
- B TMR1_BRK_TMR9_IRQHandler
-
- PUBWEAK TMR1_OV_TMR10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_OV_TMR10_IRQHandler
- B TMR1_OV_TMR10_IRQHandler
-
- PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_TRG_COM_TMR11_IRQHandler
- B TMR1_TRG_COM_TMR11_IRQHandler
-
- PUBWEAK TMR1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_CC_IRQHandler
- B TMR1_CC_IRQHandler
-
- PUBWEAK TMR2_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR2_GLOBAL_IRQHandler
- B TMR2_GLOBAL_IRQHandler
-
- PUBWEAK TMR3_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR3_GLOBAL_IRQHandler
- B TMR3_GLOBAL_IRQHandler
-
- PUBWEAK TMR4_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR4_GLOBAL_IRQHandler
- B TMR4_GLOBAL_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_I2S2EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_I2S2EXT_IRQHandler
- B SPI2_I2S2EXT_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTCAlarm_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTCAlarm_IRQHandler
- B RTCAlarm_IRQHandler
-
- PUBWEAK USBWakeUp_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBWakeUp_IRQHandler
- B USBWakeUp_IRQHandler
-
- PUBWEAK TMR8_BRK_TMR12_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_BRK_TMR12_IRQHandler
- B TMR8_BRK_TMR12_IRQHandler
-
- PUBWEAK TMR8_OV_TMR13_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_OV_TMR13_IRQHandler
- B TMR8_OV_TMR13_IRQHandler
-
- PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_TRG_COM_TMR14_IRQHandler
- B TMR8_TRG_COM_TMR14_IRQHandler
-
- PUBWEAK TMR8_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_CC_IRQHandler
- B TMR8_CC_IRQHandler
-
- PUBWEAK ADC3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC3_IRQHandler
- B ADC3_IRQHandler
-
- PUBWEAK XMC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-XMC_IRQHandler
- B XMC_IRQHandler
-
- PUBWEAK SDIO1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO1_IRQHandler
- B SDIO1_IRQHandler
-
- PUBWEAK TMR5_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR5_GLOBAL_IRQHandler
- B TMR5_GLOBAL_IRQHandler
-
- PUBWEAK SPI3_I2S3EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_I2S3EXT_IRQHandler
- B SPI3_I2S3EXT_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TMR6_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR6_GLOBAL_IRQHandler
- B TMR6_GLOBAL_IRQHandler
-
- PUBWEAK TMR7_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR7_GLOBAL_IRQHandler
- B TMR7_GLOBAL_IRQHandler
-
- PUBWEAK DMA2_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
- B DMA2_Channel1_IRQHandler
-
- PUBWEAK DMA2_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
- B DMA2_Channel2_IRQHandler
-
- PUBWEAK DMA2_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
- B DMA2_Channel3_IRQHandler
-
- PUBWEAK DMA2_Channel4_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_5_IRQHandler
- B DMA2_Channel4_5_IRQHandler
-
- PUBWEAK SDIO2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO2_IRQHandler
- B SDIO2_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- PUBWEAK CAN2_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
- B CAN2_TX_IRQHandler
-
- PUBWEAK CAN2_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
- B CAN2_RX0_IRQHandler
-
- PUBWEAK CAN2_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
- B CAN2_RX1_IRQHandler
-
- PUBWEAK CAN2_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler
- B CAN2_SCE_IRQHandler
-
- PUBWEAK ACC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ACC_IRQHandler
- B ACC_IRQHandler
-
- PUBWEAK USB_HP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
- B USB_HP_IRQHandler
-
- PUBWEAK USB_LP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
- B USB_LP_IRQHandler
-
- PUBWEAK DMA2_Channel6_7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel6_7_IRQHandler
- B DMA2_Channel6_7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART7_IRQHandler
- B UART7_IRQHandler
-
- PUBWEAK UART8_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART8_IRQHandler
- B UART8_IRQHandler
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403argt7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403argt7.s
deleted file mode 100644
index 43a4650..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403argt7.s
+++ /dev/null
@@ -1,560 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403argt7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for IAR Systems
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD XMC_IRQHandler ; XMC
- DCD SDIO1_IRQHandler ; SDIO1
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMPER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_IRQHandler
- B TAMPER_IRQHandler
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
- PUBWEAK DMA1_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
- B DMA1_Channel2_IRQHandler
-
- PUBWEAK DMA1_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
- B DMA1_Channel3_IRQHandler
-
- PUBWEAK DMA1_Channel4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
- B DMA1_Channel4_IRQHandler
-
- PUBWEAK DMA1_Channel5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
- B DMA1_Channel5_IRQHandler
-
- PUBWEAK DMA1_Channel6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
- B DMA1_Channel6_IRQHandler
-
- PUBWEAK DMA1_Channel7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
- B DMA1_Channel7_IRQHandler
-
- PUBWEAK ADC1_2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_2_IRQHandler
- B ADC1_2_IRQHandler
-
- PUBWEAK USB_HP_CAN1_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_CAN1_TX_IRQHandler
- B USB_HP_CAN1_TX_IRQHandler
-
- PUBWEAK USB_LP_CAN1_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_CAN1_RX0_IRQHandler
- B USB_LP_CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler
- B CAN1_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TMR1_BRK_TMR9_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_BRK_TMR9_IRQHandler
- B TMR1_BRK_TMR9_IRQHandler
-
- PUBWEAK TMR1_OV_TMR10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_OV_TMR10_IRQHandler
- B TMR1_OV_TMR10_IRQHandler
-
- PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_TRG_COM_TMR11_IRQHandler
- B TMR1_TRG_COM_TMR11_IRQHandler
-
- PUBWEAK TMR1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_CC_IRQHandler
- B TMR1_CC_IRQHandler
-
- PUBWEAK TMR2_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR2_GLOBAL_IRQHandler
- B TMR2_GLOBAL_IRQHandler
-
- PUBWEAK TMR3_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR3_GLOBAL_IRQHandler
- B TMR3_GLOBAL_IRQHandler
-
- PUBWEAK TMR4_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR4_GLOBAL_IRQHandler
- B TMR4_GLOBAL_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_I2S2EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_I2S2EXT_IRQHandler
- B SPI2_I2S2EXT_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTCAlarm_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTCAlarm_IRQHandler
- B RTCAlarm_IRQHandler
-
- PUBWEAK USBWakeUp_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBWakeUp_IRQHandler
- B USBWakeUp_IRQHandler
-
- PUBWEAK TMR8_BRK_TMR12_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_BRK_TMR12_IRQHandler
- B TMR8_BRK_TMR12_IRQHandler
-
- PUBWEAK TMR8_OV_TMR13_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_OV_TMR13_IRQHandler
- B TMR8_OV_TMR13_IRQHandler
-
- PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_TRG_COM_TMR14_IRQHandler
- B TMR8_TRG_COM_TMR14_IRQHandler
-
- PUBWEAK TMR8_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_CC_IRQHandler
- B TMR8_CC_IRQHandler
-
- PUBWEAK ADC3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC3_IRQHandler
- B ADC3_IRQHandler
-
- PUBWEAK XMC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-XMC_IRQHandler
- B XMC_IRQHandler
-
- PUBWEAK SDIO1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO1_IRQHandler
- B SDIO1_IRQHandler
-
- PUBWEAK TMR5_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR5_GLOBAL_IRQHandler
- B TMR5_GLOBAL_IRQHandler
-
- PUBWEAK SPI3_I2S3EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_I2S3EXT_IRQHandler
- B SPI3_I2S3EXT_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TMR6_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR6_GLOBAL_IRQHandler
- B TMR6_GLOBAL_IRQHandler
-
- PUBWEAK TMR7_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR7_GLOBAL_IRQHandler
- B TMR7_GLOBAL_IRQHandler
-
- PUBWEAK DMA2_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
- B DMA2_Channel1_IRQHandler
-
- PUBWEAK DMA2_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
- B DMA2_Channel2_IRQHandler
-
- PUBWEAK DMA2_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
- B DMA2_Channel3_IRQHandler
-
- PUBWEAK DMA2_Channel4_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_5_IRQHandler
- B DMA2_Channel4_5_IRQHandler
-
- PUBWEAK SDIO2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO2_IRQHandler
- B SDIO2_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- PUBWEAK CAN2_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
- B CAN2_TX_IRQHandler
-
- PUBWEAK CAN2_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
- B CAN2_RX0_IRQHandler
-
- PUBWEAK CAN2_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
- B CAN2_RX1_IRQHandler
-
- PUBWEAK CAN2_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler
- B CAN2_SCE_IRQHandler
-
- PUBWEAK ACC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ACC_IRQHandler
- B ACC_IRQHandler
-
- PUBWEAK USB_HP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
- B USB_HP_IRQHandler
-
- PUBWEAK USB_LP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
- B USB_LP_IRQHandler
-
- PUBWEAK DMA2_Channel6_7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel6_7_IRQHandler
- B DMA2_Channel6_7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART7_IRQHandler
- B UART7_IRQHandler
-
- PUBWEAK UART8_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART8_IRQHandler
- B UART8_IRQHandler
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403avct7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403avct7.s
deleted file mode 100644
index 1f5f7eb..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403avct7.s
+++ /dev/null
@@ -1,560 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403avct7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for IAR Systems
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD XMC_IRQHandler ; XMC
- DCD SDIO1_IRQHandler ; SDIO1
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMPER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_IRQHandler
- B TAMPER_IRQHandler
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
- PUBWEAK DMA1_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
- B DMA1_Channel2_IRQHandler
-
- PUBWEAK DMA1_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
- B DMA1_Channel3_IRQHandler
-
- PUBWEAK DMA1_Channel4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
- B DMA1_Channel4_IRQHandler
-
- PUBWEAK DMA1_Channel5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
- B DMA1_Channel5_IRQHandler
-
- PUBWEAK DMA1_Channel6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
- B DMA1_Channel6_IRQHandler
-
- PUBWEAK DMA1_Channel7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
- B DMA1_Channel7_IRQHandler
-
- PUBWEAK ADC1_2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_2_IRQHandler
- B ADC1_2_IRQHandler
-
- PUBWEAK USB_HP_CAN1_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_CAN1_TX_IRQHandler
- B USB_HP_CAN1_TX_IRQHandler
-
- PUBWEAK USB_LP_CAN1_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_CAN1_RX0_IRQHandler
- B USB_LP_CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler
- B CAN1_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TMR1_BRK_TMR9_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_BRK_TMR9_IRQHandler
- B TMR1_BRK_TMR9_IRQHandler
-
- PUBWEAK TMR1_OV_TMR10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_OV_TMR10_IRQHandler
- B TMR1_OV_TMR10_IRQHandler
-
- PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_TRG_COM_TMR11_IRQHandler
- B TMR1_TRG_COM_TMR11_IRQHandler
-
- PUBWEAK TMR1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_CC_IRQHandler
- B TMR1_CC_IRQHandler
-
- PUBWEAK TMR2_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR2_GLOBAL_IRQHandler
- B TMR2_GLOBAL_IRQHandler
-
- PUBWEAK TMR3_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR3_GLOBAL_IRQHandler
- B TMR3_GLOBAL_IRQHandler
-
- PUBWEAK TMR4_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR4_GLOBAL_IRQHandler
- B TMR4_GLOBAL_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_I2S2EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_I2S2EXT_IRQHandler
- B SPI2_I2S2EXT_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTCAlarm_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTCAlarm_IRQHandler
- B RTCAlarm_IRQHandler
-
- PUBWEAK USBWakeUp_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBWakeUp_IRQHandler
- B USBWakeUp_IRQHandler
-
- PUBWEAK TMR8_BRK_TMR12_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_BRK_TMR12_IRQHandler
- B TMR8_BRK_TMR12_IRQHandler
-
- PUBWEAK TMR8_OV_TMR13_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_OV_TMR13_IRQHandler
- B TMR8_OV_TMR13_IRQHandler
-
- PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_TRG_COM_TMR14_IRQHandler
- B TMR8_TRG_COM_TMR14_IRQHandler
-
- PUBWEAK TMR8_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_CC_IRQHandler
- B TMR8_CC_IRQHandler
-
- PUBWEAK ADC3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC3_IRQHandler
- B ADC3_IRQHandler
-
- PUBWEAK XMC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-XMC_IRQHandler
- B XMC_IRQHandler
-
- PUBWEAK SDIO1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO1_IRQHandler
- B SDIO1_IRQHandler
-
- PUBWEAK TMR5_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR5_GLOBAL_IRQHandler
- B TMR5_GLOBAL_IRQHandler
-
- PUBWEAK SPI3_I2S3EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_I2S3EXT_IRQHandler
- B SPI3_I2S3EXT_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TMR6_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR6_GLOBAL_IRQHandler
- B TMR6_GLOBAL_IRQHandler
-
- PUBWEAK TMR7_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR7_GLOBAL_IRQHandler
- B TMR7_GLOBAL_IRQHandler
-
- PUBWEAK DMA2_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
- B DMA2_Channel1_IRQHandler
-
- PUBWEAK DMA2_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
- B DMA2_Channel2_IRQHandler
-
- PUBWEAK DMA2_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
- B DMA2_Channel3_IRQHandler
-
- PUBWEAK DMA2_Channel4_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_5_IRQHandler
- B DMA2_Channel4_5_IRQHandler
-
- PUBWEAK SDIO2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO2_IRQHandler
- B SDIO2_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- PUBWEAK CAN2_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
- B CAN2_TX_IRQHandler
-
- PUBWEAK CAN2_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
- B CAN2_RX0_IRQHandler
-
- PUBWEAK CAN2_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
- B CAN2_RX1_IRQHandler
-
- PUBWEAK CAN2_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler
- B CAN2_SCE_IRQHandler
-
- PUBWEAK ACC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ACC_IRQHandler
- B ACC_IRQHandler
-
- PUBWEAK USB_HP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
- B USB_HP_IRQHandler
-
- PUBWEAK USB_LP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
- B USB_LP_IRQHandler
-
- PUBWEAK DMA2_Channel6_7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel6_7_IRQHandler
- B DMA2_Channel6_7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART7_IRQHandler
- B UART7_IRQHandler
-
- PUBWEAK UART8_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART8_IRQHandler
- B UART8_IRQHandler
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403avet7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403avet7.s
deleted file mode 100644
index c82ea3e..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403avet7.s
+++ /dev/null
@@ -1,560 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403avet7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for IAR Systems
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD XMC_IRQHandler ; XMC
- DCD SDIO1_IRQHandler ; SDIO1
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMPER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_IRQHandler
- B TAMPER_IRQHandler
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
- PUBWEAK DMA1_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
- B DMA1_Channel2_IRQHandler
-
- PUBWEAK DMA1_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
- B DMA1_Channel3_IRQHandler
-
- PUBWEAK DMA1_Channel4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
- B DMA1_Channel4_IRQHandler
-
- PUBWEAK DMA1_Channel5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
- B DMA1_Channel5_IRQHandler
-
- PUBWEAK DMA1_Channel6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
- B DMA1_Channel6_IRQHandler
-
- PUBWEAK DMA1_Channel7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
- B DMA1_Channel7_IRQHandler
-
- PUBWEAK ADC1_2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_2_IRQHandler
- B ADC1_2_IRQHandler
-
- PUBWEAK USB_HP_CAN1_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_CAN1_TX_IRQHandler
- B USB_HP_CAN1_TX_IRQHandler
-
- PUBWEAK USB_LP_CAN1_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_CAN1_RX0_IRQHandler
- B USB_LP_CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler
- B CAN1_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TMR1_BRK_TMR9_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_BRK_TMR9_IRQHandler
- B TMR1_BRK_TMR9_IRQHandler
-
- PUBWEAK TMR1_OV_TMR10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_OV_TMR10_IRQHandler
- B TMR1_OV_TMR10_IRQHandler
-
- PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_TRG_COM_TMR11_IRQHandler
- B TMR1_TRG_COM_TMR11_IRQHandler
-
- PUBWEAK TMR1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_CC_IRQHandler
- B TMR1_CC_IRQHandler
-
- PUBWEAK TMR2_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR2_GLOBAL_IRQHandler
- B TMR2_GLOBAL_IRQHandler
-
- PUBWEAK TMR3_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR3_GLOBAL_IRQHandler
- B TMR3_GLOBAL_IRQHandler
-
- PUBWEAK TMR4_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR4_GLOBAL_IRQHandler
- B TMR4_GLOBAL_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_I2S2EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_I2S2EXT_IRQHandler
- B SPI2_I2S2EXT_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTCAlarm_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTCAlarm_IRQHandler
- B RTCAlarm_IRQHandler
-
- PUBWEAK USBWakeUp_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBWakeUp_IRQHandler
- B USBWakeUp_IRQHandler
-
- PUBWEAK TMR8_BRK_TMR12_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_BRK_TMR12_IRQHandler
- B TMR8_BRK_TMR12_IRQHandler
-
- PUBWEAK TMR8_OV_TMR13_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_OV_TMR13_IRQHandler
- B TMR8_OV_TMR13_IRQHandler
-
- PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_TRG_COM_TMR14_IRQHandler
- B TMR8_TRG_COM_TMR14_IRQHandler
-
- PUBWEAK TMR8_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_CC_IRQHandler
- B TMR8_CC_IRQHandler
-
- PUBWEAK ADC3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC3_IRQHandler
- B ADC3_IRQHandler
-
- PUBWEAK XMC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-XMC_IRQHandler
- B XMC_IRQHandler
-
- PUBWEAK SDIO1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO1_IRQHandler
- B SDIO1_IRQHandler
-
- PUBWEAK TMR5_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR5_GLOBAL_IRQHandler
- B TMR5_GLOBAL_IRQHandler
-
- PUBWEAK SPI3_I2S3EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_I2S3EXT_IRQHandler
- B SPI3_I2S3EXT_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TMR6_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR6_GLOBAL_IRQHandler
- B TMR6_GLOBAL_IRQHandler
-
- PUBWEAK TMR7_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR7_GLOBAL_IRQHandler
- B TMR7_GLOBAL_IRQHandler
-
- PUBWEAK DMA2_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
- B DMA2_Channel1_IRQHandler
-
- PUBWEAK DMA2_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
- B DMA2_Channel2_IRQHandler
-
- PUBWEAK DMA2_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
- B DMA2_Channel3_IRQHandler
-
- PUBWEAK DMA2_Channel4_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_5_IRQHandler
- B DMA2_Channel4_5_IRQHandler
-
- PUBWEAK SDIO2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO2_IRQHandler
- B SDIO2_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- PUBWEAK CAN2_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
- B CAN2_TX_IRQHandler
-
- PUBWEAK CAN2_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
- B CAN2_RX0_IRQHandler
-
- PUBWEAK CAN2_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
- B CAN2_RX1_IRQHandler
-
- PUBWEAK CAN2_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler
- B CAN2_SCE_IRQHandler
-
- PUBWEAK ACC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ACC_IRQHandler
- B ACC_IRQHandler
-
- PUBWEAK USB_HP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
- B USB_HP_IRQHandler
-
- PUBWEAK USB_LP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
- B USB_LP_IRQHandler
-
- PUBWEAK DMA2_Channel6_7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel6_7_IRQHandler
- B DMA2_Channel6_7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART7_IRQHandler
- B UART7_IRQHandler
-
- PUBWEAK UART8_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART8_IRQHandler
- B UART8_IRQHandler
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403avgt7.s b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403avgt7.s
deleted file mode 100644
index 65ce62e..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/iar/startup_at32f403avgt7.s
+++ /dev/null
@@ -1,560 +0,0 @@
-;**************************************************************************
-;* File : startup_at32f403avgt7.s
-;* Version: V1.2.2
-;* Date : 2020-07-01
-;* Brief : at32f4xx startup file for IAR Systems
-;**************************************************************************
-;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper
- DCD RTC_IRQHandler ; RTC
- DCD FLASH_IRQHandler ; Flash
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line 0
- DCD EXTI1_IRQHandler ; EXTI Line 1
- DCD EXTI2_IRQHandler ; EXTI Line 2
- DCD EXTI3_IRQHandler ; EXTI Line 3
- DCD EXTI4_IRQHandler ; EXTI Line 4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 & ADC2
- DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
- DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; CAN1 RX1
- DCD CAN1_SCE_IRQHandler ; CAN1 SCE
- DCD EXTI9_5_IRQHandler ; EXTI Line [9:5]
- DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Break and TMR9
- DCD TMR1_OV_TMR10_IRQHandler ; TMR1 Update and TMR10
- DCD TMR1_TRG_COM_TMR11_IRQHandler ; TMR1 Trigger and Commutation and TMR11
- DCD TMR1_CC_IRQHandler ; TMR1 Capture Compare
- DCD TMR2_GLOBAL_IRQHandler ; TMR2
- DCD TMR3_GLOBAL_IRQHandler ; TMR3
- DCD TMR4_GLOBAL_IRQHandler ; TMR4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; EXTI Line [15:10]
- DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
- DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Break and TMR12
- DCD TMR8_OV_TMR13_IRQHandler ; TMR8 Update and TMR13
- DCD TMR8_TRG_COM_TMR14_IRQHandler ; TMR8 Trigger and Commutation and TMR14
- DCD TMR8_CC_IRQHandler ; TMR8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD XMC_IRQHandler ; XMC
- DCD SDIO1_IRQHandler ; SDIO1
- DCD TMR5_GLOBAL_IRQHandler ; TMR5
- DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TMR6_GLOBAL_IRQHandler ; TMR6
- DCD TMR7_GLOBAL_IRQHandler ; TMR7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
- DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
- DCD SDIO2_IRQHandler ; SDIO2
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD SPI4_IRQHandler ; SPI4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD CAN2_TX_IRQHandler ; CAN2 TX
- DCD CAN2_RX0_IRQHandler ; CAN2 RX0
- DCD CAN2_RX1_IRQHandler ; CAN2 RX1
- DCD CAN2_SCE_IRQHandler ; CAN2 SCE
- DCD ACC_IRQHandler ; ACC
- DCD USB_HP_IRQHandler ; USB HP
- DCD USB_LP_IRQHandler ; USB LP
- DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
- DCD USART6_IRQHandler ; USART6
- DCD UART7_IRQHandler ; UART7
- DCD UART8_IRQHandler ; UART8
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMPER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_IRQHandler
- B TAMPER_IRQHandler
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
- PUBWEAK DMA1_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
- B DMA1_Channel2_IRQHandler
-
- PUBWEAK DMA1_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
- B DMA1_Channel3_IRQHandler
-
- PUBWEAK DMA1_Channel4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
- B DMA1_Channel4_IRQHandler
-
- PUBWEAK DMA1_Channel5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
- B DMA1_Channel5_IRQHandler
-
- PUBWEAK DMA1_Channel6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
- B DMA1_Channel6_IRQHandler
-
- PUBWEAK DMA1_Channel7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
- B DMA1_Channel7_IRQHandler
-
- PUBWEAK ADC1_2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_2_IRQHandler
- B ADC1_2_IRQHandler
-
- PUBWEAK USB_HP_CAN1_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_CAN1_TX_IRQHandler
- B USB_HP_CAN1_TX_IRQHandler
-
- PUBWEAK USB_LP_CAN1_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_CAN1_RX0_IRQHandler
- B USB_LP_CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler
- B CAN1_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TMR1_BRK_TMR9_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_BRK_TMR9_IRQHandler
- B TMR1_BRK_TMR9_IRQHandler
-
- PUBWEAK TMR1_OV_TMR10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_OV_TMR10_IRQHandler
- B TMR1_OV_TMR10_IRQHandler
-
- PUBWEAK TMR1_TRG_COM_TMR11_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_TRG_COM_TMR11_IRQHandler
- B TMR1_TRG_COM_TMR11_IRQHandler
-
- PUBWEAK TMR1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR1_CC_IRQHandler
- B TMR1_CC_IRQHandler
-
- PUBWEAK TMR2_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR2_GLOBAL_IRQHandler
- B TMR2_GLOBAL_IRQHandler
-
- PUBWEAK TMR3_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR3_GLOBAL_IRQHandler
- B TMR3_GLOBAL_IRQHandler
-
- PUBWEAK TMR4_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR4_GLOBAL_IRQHandler
- B TMR4_GLOBAL_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_I2S2EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_I2S2EXT_IRQHandler
- B SPI2_I2S2EXT_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTCAlarm_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-RTCAlarm_IRQHandler
- B RTCAlarm_IRQHandler
-
- PUBWEAK USBWakeUp_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USBWakeUp_IRQHandler
- B USBWakeUp_IRQHandler
-
- PUBWEAK TMR8_BRK_TMR12_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_BRK_TMR12_IRQHandler
- B TMR8_BRK_TMR12_IRQHandler
-
- PUBWEAK TMR8_OV_TMR13_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_OV_TMR13_IRQHandler
- B TMR8_OV_TMR13_IRQHandler
-
- PUBWEAK TMR8_TRG_COM_TMR14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_TRG_COM_TMR14_IRQHandler
- B TMR8_TRG_COM_TMR14_IRQHandler
-
- PUBWEAK TMR8_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR8_CC_IRQHandler
- B TMR8_CC_IRQHandler
-
- PUBWEAK ADC3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ADC3_IRQHandler
- B ADC3_IRQHandler
-
- PUBWEAK XMC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-XMC_IRQHandler
- B XMC_IRQHandler
-
- PUBWEAK SDIO1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO1_IRQHandler
- B SDIO1_IRQHandler
-
- PUBWEAK TMR5_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR5_GLOBAL_IRQHandler
- B TMR5_GLOBAL_IRQHandler
-
- PUBWEAK SPI3_I2S3EXT_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_I2S3EXT_IRQHandler
- B SPI3_I2S3EXT_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TMR6_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR6_GLOBAL_IRQHandler
- B TMR6_GLOBAL_IRQHandler
-
- PUBWEAK TMR7_GLOBAL_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-TMR7_GLOBAL_IRQHandler
- B TMR7_GLOBAL_IRQHandler
-
- PUBWEAK DMA2_Channel1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
- B DMA2_Channel1_IRQHandler
-
- PUBWEAK DMA2_Channel2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
- B DMA2_Channel2_IRQHandler
-
- PUBWEAK DMA2_Channel3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
- B DMA2_Channel3_IRQHandler
-
- PUBWEAK DMA2_Channel4_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_5_IRQHandler
- B DMA2_Channel4_5_IRQHandler
-
- PUBWEAK SDIO2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO2_IRQHandler
- B SDIO2_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- PUBWEAK CAN2_TX_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler
- B CAN2_TX_IRQHandler
-
- PUBWEAK CAN2_RX0_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler
- B CAN2_RX0_IRQHandler
-
- PUBWEAK CAN2_RX1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler
- B CAN2_RX1_IRQHandler
-
- PUBWEAK CAN2_SCE_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler
- B CAN2_SCE_IRQHandler
-
- PUBWEAK ACC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-ACC_IRQHandler
- B ACC_IRQHandler
-
- PUBWEAK USB_HP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
- B USB_HP_IRQHandler
-
- PUBWEAK USB_LP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
- B USB_LP_IRQHandler
-
- PUBWEAK DMA2_Channel6_7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel6_7_IRQHandler
- B DMA2_Channel6_7_IRQHandler
-
- PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler
- B USART6_IRQHandler
-
- PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART7_IRQHandler
- B UART7_IRQHandler
-
- PUBWEAK UART8_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-UART8_IRQHandler
- B UART8_IRQHandler
-
- END
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/system_at32f4xx.c b/.platformio/packages/framework-cmsis-at32f40/Source/Templates/system_at32f4xx.c
deleted file mode 100644
index b73ff8c..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/system_at32f4xx.c
+++ /dev/null
@@ -1,3473 +0,0 @@
-/**
- ******************************************************************************
- * File : system_at32f4xx.c
- * Version: V1.2.2
- * Date : 2020-07-01
- * Brief : CMSIS Cortex-M4 system source file
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup at32f4xx_system
- * @{
- */
-
-/** @addtogroup at32f4xx_System_Private_Includes
- * @{
- */
-
-#include "at32f4xx.h"
-
-/**
- * @}
- */
-
-/** @addtogroup at32f4xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup at32f4xx_System_Private_Defines
- * @{
- */
-
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
- frequency (after reset the HSI is used as SYSCLK source)
-
- IMPORTANT NOTE:
- ==============
- 1. After each device reset the HSI is used as System clock source.
-
- 2. Please make sure that the selected System clock doesn't exceed your device's
- maximum frequency.
-
- 3. If none of the define below is enabled, the HSI is used as System clock
- source.
-
- 4. The System clock configuration functions provided within this file assume that:
- - For at32f4xx devices, an external 8MHz crystal is used to drive the System clock.
- If you are using different crystal you have to adapt those functions accordingly.
-
- Clock (MHz)
- PLL from HSE or HSI
- SYSCLK HCLK PCLK2 PCLK1
- 24 24 24 24
- 36 36 36 36
- 48 48 48 24
- 56 56 56 28
- 72 72 72 36
- 96 96 48 48
- 108 108 54 54
- 120 120 60 60
- 144 144 72 72
- 150 150 75 75
- 168 168 84 84
- 176 176 88 88
- 192 192 96 96
- 200 200 100 100
- 224 224 112 112
- 240 240 120 120
- */
-
-#if defined (AT32F403xx) || defined (AT32F413xx) || \
- defined (AT32F415xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
-/* #define SYSCLK_FREQ_HSE HSE_VALUE */
-/* #define SYSCLK_FREQ_24MHz 24000000 */
-/* #define SYSCLK_FREQ_36MHz 36000000 */
-/* #define SYSCLK_FREQ_48MHz 48000000 */
-/* #define SYSCLK_FREQ_56MHz 56000000 */
-#define SYSCLK_FREQ_72MHz 72000000
-/* #define SYSCLK_FREQ_96MHz 96000000 */
-/* #define SYSCLK_FREQ_108MHz 108000000 */
-/* #define SYSCLK_FREQ_120MHz 120000000 */
-/* #define SYSCLK_FREQ_144MHz 144000000 */
-/* #define SYSCLK_FREQ_24MHz_HSI 24000000 */
-/* #define SYSCLK_FREQ_36MHz_HSI 36000000 */
-/* #define SYSCLK_FREQ_48MHz_HSI 48000000 */
-/* #define SYSCLK_FREQ_56MHz_HSI 56000000 */
-/* #define SYSCLK_FREQ_72MHz_HSI 72000000 */
-/* #define SYSCLK_FREQ_96MHz_HSI 96000000 */
-/* #define SYSCLK_FREQ_108MHz_HSI 108000000 */
-/* #define SYSCLK_FREQ_120MHz_HSI 120000000 */
-/* #define SYSCLK_FREQ_144MHz_HSI 144000000 */
-#endif
-
-#if defined (AT32F415xx)
-/* #define SYSCLK_FREQ_150MHz 150000000 */
-/* #define SYSCLK_FREQ_150MHz_HSI 150000000 */
-#endif
-
-#if defined (AT32F403xx) || defined (AT32F413xx) || \
- defined (AT32F403Axx)|| defined (AT32F407xx)
-/* #define SYSCLK_FREQ_168MHz 168000000 */
-/* #define SYSCLK_FREQ_176MHz 176000000 */
-/* #define SYSCLK_FREQ_192MHz 192000000 */
-/* #define SYSCLK_FREQ_200MHz 200000000 */
-/* #define SYSCLK_FREQ_168MHz_HSI 168000000 */
-/* #define SYSCLK_FREQ_176MHz_HSI 176000000 */
-/* #define SYSCLK_FREQ_192MHz_HSI 192000000 */
-/* #define SYSCLK_FREQ_200MHz_HSI 200000000 */
-#endif
-
-#if defined (AT32F403Axx)|| defined (AT32F407xx)
-/* #define SYSCLK_FREQ_224MHz 224000000 */
-/* #define SYSCLK_FREQ_240MHz 240000000 */
-/* #define SYSCLK_FREQ_224MHz_HSI 224000000 */
-/* #define SYSCLK_FREQ_240MHz_HSI 240000000 */
-#endif
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
- (AT32 High density and XL-density devices) as data memory */
-
-/* #define DATA_IN_ExtSRAM */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
-This value must be a multiple of 0x200. */
-
-
-/**
- * @}
- */
-
-/** @addtogroup at32f4xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup at32f4xx_System_Private_Variables
- * @{
- */
-
-/*******************************************************************************
-* Clock Definitions
-*******************************************************************************/
-#ifdef SYSCLK_FREQ_HSE
-uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz
-uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_96MHz
-uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_108MHz
-uint32_t SystemCoreClock = SYSCLK_FREQ_108MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_120MHz
-uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_144MHz
-uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_150MHz
-uint32_t SystemCoreClock = SYSCLK_FREQ_150MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_168MHz
-uint32_t SystemCoreClock = SYSCLK_FREQ_168MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_176MHz
-uint32_t SystemCoreClock = SYSCLK_FREQ_176MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_192MHz
-uint32_t SystemCoreClock = SYSCLK_FREQ_192MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_200MHz
-uint32_t SystemCoreClock = SYSCLK_FREQ_200MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_224MHz
-uint32_t SystemCoreClock = SYSCLK_FREQ_224MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_240MHz
-uint32_t SystemCoreClock = SYSCLK_FREQ_240MHz; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz_HSI
-uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSI; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_36MHz_HSI
-uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz_HSI; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz_HSI
-uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz_HSI
-uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz_HSI
-uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_96MHz_HSI
-uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_108MHz_HSI
-uint32_t SystemCoreClock = SYSCLK_FREQ_108MHz_HSI; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_120MHz_HSI
-uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_144MHz_HSI
-uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_150MHz_HSI
-uint32_t SystemCoreClock = SYSCLK_FREQ_150MHz_HSI; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_168MHz_HSI
-uint32_t SystemCoreClock = SYSCLK_FREQ_168MHz_HSI; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_176MHz_HSI
-uint32_t SystemCoreClock = SYSCLK_FREQ_176MHz_HSI; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_192MHz_HSI
-uint32_t SystemCoreClock = SYSCLK_FREQ_192MHz_HSI; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_200MHz_HSI
-uint32_t SystemCoreClock = SYSCLK_FREQ_200MHz_HSI; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_224MHz_HSI
-uint32_t SystemCoreClock = SYSCLK_FREQ_224MHz_HSI; /*!< System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_240MHz_HSI
-uint32_t SystemCoreClock = SYSCLK_FREQ_240MHz_HSI; /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-#define SYSCLK_FREQ_HSI HSI_VALUE
-uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPscTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-/**
- * @}
- */
-
-/** @addtogroup at32f4xx_System_Private_FunctionPrototypes
- * @{
- */
-
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-static void SetSysClockTo24M(void);
-#elif defined SYSCLK_FREQ_36MHz
-static void SetSysClockTo36M(void);
-#elif defined SYSCLK_FREQ_48MHz
-static void SetSysClockTo48M(void);
-#elif defined SYSCLK_FREQ_56MHz
-static void SetSysClockTo56M(void);
-#elif defined SYSCLK_FREQ_72MHz
-static void SetSysClockTo72M(void);
-#elif defined SYSCLK_FREQ_96MHz
-static void SetSysClockTo96M(void);
-#elif defined SYSCLK_FREQ_108MHz
-static void SetSysClockTo108M(void);
-#elif defined SYSCLK_FREQ_120MHz
-static void SetSysClockTo120M(void);
-#elif defined SYSCLK_FREQ_144MHz
-static void SetSysClockTo144M(void);
-#elif defined SYSCLK_FREQ_150MHz
-static void SetSysClockTo150M(void);
-#elif defined SYSCLK_FREQ_168MHz
-static void SetSysClockTo168M(void);
-#elif defined SYSCLK_FREQ_176MHz
-static void SetSysClockTo176M(void);
-#elif defined SYSCLK_FREQ_192MHz
-static void SetSysClockTo192M(void);
-#elif defined SYSCLK_FREQ_200MHz
-static void SetSysClockTo200M(void);
-#elif defined SYSCLK_FREQ_224MHz
-static void SetSysClockTo224M(void);
-#elif defined SYSCLK_FREQ_240MHz
-static void SetSysClockTo240M(void);
-#elif defined SYSCLK_FREQ_24MHz_HSI
-static void SetSysClockTo24MHSI(void);
-#elif defined SYSCLK_FREQ_36MHz_HSI
-static void SetSysClockTo36MHSI(void);
-#elif defined SYSCLK_FREQ_48MHz_HSI
-static void SetSysClockTo48MHSI(void);
-#elif defined SYSCLK_FREQ_56MHz_HSI
-static void SetSysClockTo56MHSI(void);
-#elif defined SYSCLK_FREQ_72MHz_HSI
-static void SetSysClockTo72MHSI(void);
-#elif defined SYSCLK_FREQ_96MHz_HSI
-static void SetSysClockTo96MHSI(void);
-#elif defined SYSCLK_FREQ_108MHz_HSI
-static void SetSysClockTo108MHSI(void);
-#elif defined SYSCLK_FREQ_120MHz_HSI
-static void SetSysClockTo120MHSI(void);
-#elif defined SYSCLK_FREQ_144MHz_HSI
-static void SetSysClockTo144MHSI(void);
-#elif defined SYSCLK_FREQ_150MHz_HSI
-static void SetSysClockTo150MHSI(void);
-#elif defined SYSCLK_FREQ_168MHz_HSI
-static void SetSysClockTo168MHSI(void);
-#elif defined SYSCLK_FREQ_176MHz_HSI
-static void SetSysClockTo176MHSI(void);
-#elif defined SYSCLK_FREQ_192MHz_HSI
-static void SetSysClockTo192MHSI(void);
-#elif defined SYSCLK_FREQ_200MHz_HSI
-static void SetSysClockTo200MHSI(void);
-#elif defined SYSCLK_FREQ_224MHz_HSI
-static void SetSysClockTo224MHSI(void);
-#elif defined SYSCLK_FREQ_240MHz_HSI
-static void SetSysClockTo240MHSI(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-static void SystemInit_ExtMemCtrl(void);
-#endif /* DATA_IN_ExtSRAM */
-
-/**
- * @}
- */
-
-/** @addtogroup at32f4xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the Embedded Flash Interface, the PLL and update the
- * SystemCoreClock variable.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-void SystemInit (void)
-{
-#if defined (AT32F415xx)
- /* Enable low power mode, 0x40007050[bit2] */
- RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_PWR, ENABLE);
- *(volatile uint8_t *)(0x40007050) |= (uint8_t)(0x1 << 2);
- RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_PWR, DISABLE);
-#endif
-
-#if defined (__FPU_USED) && (__FPU_USED == 1U)
- SCB->CPACR |= ((3U << 10U * 2U) | /* set CP10 Full Access */
- (3U << 11U * 2U) ); /* set CP11 Full Access */
-#endif
-
- /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
- /* Set HSIEN bit */
- BIT_SET(RCC->CTRL, RCC_CTRL_HSIEN);
-
- /* Reset SW, AHBPSC, APB1PSC, APB2PSC, ADCPSC and CLKOUT bits */
- BIT_CLEAR(RCC->CFG, RCC_CFG_SYSCLKSEL | RCC_CFG_AHBPSC | \
- RCC_CFG_APB1PSC | RCC_CFG_APB2PSC | \
- RCC_CFG_ADCPSC | RCC_CFG_CLKOUT);
-
- /* Reset HSEEN, HSECFDEN and PLLEN bits */
- BIT_CLEAR(RCC->CTRL, RCC_CTRL_HSEEN | RCC_CTRL_HSECFDEN | \
- RCC_CTRL_PLLEN);
-
- /* Reset HSEBYPS bit */
- BIT_CLEAR(RCC->CTRL, RCC_CTRL_HSEBYPS);
-
- /* Reset PLLRC, PLLHSEPSC, PLLMUL, USBPSC and PLLRANGE bits */
- BIT_CLEAR(RCC->CFG, RCC_CFG_PLLRC | RCC_CFG_PLLHSEPSC | \
- RCC_CFG_PLLMULT | RCC_CFG_USBPSC | RCC_CFG_PLLRANGE);
-
- /* Reset USB768B, CLKOUT[3], HSICAL_KEY[7:0] */
- BIT_CLEAR(RCC->MISC, 0x010100FF);
-
- /* Disable all interrupts and clear pending bits */
- RCC->CLKINT = RCC_CLKINT_LSISTBLFC | RCC_CLKINT_LSESTBLFC | \
- RCC_CLKINT_HSISTBLFC | RCC_CLKINT_HSESTBLFC | \
- RCC_CLKINT_PLLSTBLFC | RCC_CLKINT_HSECFDFC;
-
-#ifdef DATA_IN_ExtSRAM
- SystemInit_ExtMemCtrl();
-#endif /* DATA_IN_ExtSRAM */
-
- /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
- /* Configure the Flash Latency cycles and enable prefetch buffer */
- SetSysClock();
-
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in at32f4xx.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in at32f4xx.h file (default value
- * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
- * that HSE_VALUE is same as the real frequency of the crystal used.
- * Otherwise, this function may have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmult = 0, pllrefclk = 0, tempcfg = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFG & RCC_CFG_SYSCLKSTS;
-
- switch (tmp)
- {
- case RCC_CFG_SYSCLKSTS_HSI: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
-
- case RCC_CFG_SYSCLKSTS_HSE: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
-
- case RCC_CFG_SYSCLKSTS_PLL: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllrefclk = RCC->CFG & RCC_CFG_PLLRC;
- tempcfg = RCC->CFG;
- pllmult = RCC_GET_PLLMULT(tempcfg);
-
- if (pllrefclk == RCC_PLLRefClk_HSI_Div2)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmult;
- }
- else
- {
- /* HSE selected as PLL clock entry */
- if ((RCC->CFG & RCC_CFG_PLLHSEPSC) != (uint32_t)RESET)
- {
- /* HSE oscillator clock divided by 2 */
- SystemCoreClock = (HSE_VALUE >> 1) * pllmult;
- }
- else
- {
- SystemCoreClock = HSE_VALUE * pllmult;
- }
- }
-
- break;
-
- default:
- SystemCoreClock = HSI_VALUE;
- break;
- }
-
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPscTable[((RCC->CFG & RCC_CFG_AHBPSC) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
- * @param None
- * @retval None
- */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
- SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
- SetSysClockTo24M();
-#elif defined SYSCLK_FREQ_36MHz
- SetSysClockTo36M();
-#elif defined SYSCLK_FREQ_48MHz
- SetSysClockTo48M();
-#elif defined SYSCLK_FREQ_56MHz
- SetSysClockTo56M();
-#elif defined SYSCLK_FREQ_72MHz
- SetSysClockTo72M();
-#elif defined SYSCLK_FREQ_96MHz
- SetSysClockTo96M();
-#elif defined SYSCLK_FREQ_108MHz
- SetSysClockTo108M();
-#elif defined SYSCLK_FREQ_120MHz
- SetSysClockTo120M();
-#elif defined SYSCLK_FREQ_144MHz
- SetSysClockTo144M();
-#elif defined SYSCLK_FREQ_150MHz
- SetSysClockTo150M();
-#elif defined SYSCLK_FREQ_168MHz
- SetSysClockTo168M();
-#elif defined SYSCLK_FREQ_176MHz
- SetSysClockTo176M();
-#elif defined SYSCLK_FREQ_192MHz
- SetSysClockTo192M();
-#elif defined SYSCLK_FREQ_200MHz
- SetSysClockTo200M();
-#elif defined SYSCLK_FREQ_224MHz
- SetSysClockTo224M();
-#elif defined SYSCLK_FREQ_240MHz
- SetSysClockTo240M();
-#elif defined SYSCLK_FREQ_24MHz_HSI
- SetSysClockTo24MHSI();
-#elif defined SYSCLK_FREQ_36MHz_HSI
- SetSysClockTo36MHSI();
-#elif defined SYSCLK_FREQ_48MHz_HSI
- SetSysClockTo48MHSI();
-#elif defined SYSCLK_FREQ_56MHz_HSI
- SetSysClockTo56MHSI();
-#elif defined SYSCLK_FREQ_72MHz_HSI
- SetSysClockTo72MHSI();
-#elif defined SYSCLK_FREQ_96MHz_HSI
- SetSysClockTo96MHSI();
-#elif defined SYSCLK_FREQ_108MHz_HSI
- SetSysClockTo108MHSI();
-#elif defined SYSCLK_FREQ_120MHz_HSI
- SetSysClockTo120MHSI();
-#elif defined SYSCLK_FREQ_144MHz_HSI
- SetSysClockTo144MHSI();
-#elif defined SYSCLK_FREQ_150MHz_HSI
- SetSysClockTo150MHSI();
-#elif defined SYSCLK_FREQ_168MHz_HSI
- SetSysClockTo168MHSI();
-#elif defined SYSCLK_FREQ_176MHz_HSI
- SetSysClockTo176MHSI();
-#elif defined SYSCLK_FREQ_192MHz_HSI
- SetSysClockTo192MHSI();
-#elif defined SYSCLK_FREQ_200MHz_HSI
- SetSysClockTo200MHSI();
-#elif defined SYSCLK_FREQ_224MHz_HSI
- SetSysClockTo224MHSI();
-#elif defined SYSCLK_FREQ_240MHz_HSI
- SetSysClockTo240MHSI();
-#endif
-
- /* If none of the define above is enabled, the HSI is used as System clock
- source (default after reset) */
-}
-
-/**
- * @brief Setup the external memory controller. Called in startup_at32f4xx.s
- * before jump to __main
- * @param None
- * @retval None
- */
-#ifdef DATA_IN_ExtSRAM
-/**
- * @brief Setup the external memory controller.
- * Called in startup_at32f4xx_xx.s/.c before jump to main.
- * This function configures the external SRAM mounted
- * (AT32 High density devices). This SRAM will be used as program
- * data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtrl(void)
-{
- /* Enable XMC clock */
- RCC->AHBEN = RCC_AHBEN_SRAMEN | RCC_AHBEN_FLASHEN | RCC_AHBEN_XMCEN;
-
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
- RCC->APB2EN = RCC_APB2EN_GPIODEN | RCC_APB2EN_GPIOEEN | RCC_APB2EN_GPIOFEN | RCC_APB2EN_GPIOGEN;
-
- /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
- /*---------------- SRAM Address lines configuration -------------------------*/
- /*---------------- NOE and NWE configuration --------------------------------*/
- /*---------------- NE3 configuration ----------------------------------------*/
- /*---------------- NBL0, NBL1 configuration ---------------------------------*/
-
- GPIOD->CTRLL = 0x44BB44BB;
- GPIOD->CTRLH = 0xBBBBBBBB;
-
- GPIOE->CTRLL = 0xB44444BB;
- GPIOE->CTRLH = 0xBBBBBBBB;
-
- GPIOF->CTRLL = 0x44BBBBBB;
- GPIOF->CTRLH = 0xBBBB4444;
-
- GPIOG->CTRLL = 0x44BBBBBB;
- GPIOG->CTRLH = 0x44444B44;
-
- /*---------------- XMC Configuration ---------------------------------------*/
- /*---------------- Enable XMC Bank1_SRAM Bank ------------------------------*/
-
- XMC_Bank1->BK1CTRLR[4] = 0x00001011;
- XMC_Bank1->BK1CTRLR[5] = 0x00000200;
-}
-#endif /* DATA_IN_ExtSRAM */
-
-#ifndef SYSCLK_FREQ_HSI
-#ifdef AT32F403xx
-/**
- * @brief Delay to wait for HSE stable.
- * @note This function should be used before reading the HSESTBL flag.
- * @param None
- * @retval None
- */
-static void WaitHseStbl(uint32_t delay)
-{
- uint32_t i;
-
- for(i = 0; i < delay; i++)
- ;
-}
-#endif
-#endif /* SYSCLK_FREQ_HSI */
-
-#ifdef SYSCLK_FREQ_HSE
-/**
- * @brief Selects HSE as System clock source and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockToHSE(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1;
-
- /* Select HSE as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_HSE;
-
- /* Wait till HSE is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != (uint32_t)0x04)
- {
- }
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_24MHz
-/**
- * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo24M(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1;
-
- /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT6);
-#if defined (AT32F415xx)
- /* Config PLL clock resource Table */
- RCC_PLLFrefTableConfig(HSE_VALUE);
-#endif
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_36MHz
-/**
- * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo36M(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1;
-
- /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT9);
-#if defined (AT32F415xx)
- /* Config PLL clock resource Table */
- RCC_PLLFrefTableConfig(HSE_VALUE);
-#endif
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-#elif defined SYSCLK_FREQ_48MHz
-/**
- * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo48M(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT6);
-#if defined (AT32F415xx)
- /* Config PLL clock resource Table */
- RCC_PLLFrefTableConfig(HSE_VALUE);
-#endif
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-/**
- * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo56M(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT7);
-#if defined (AT32F415xx)
- /* Config PLL clock resource Table */
- RCC_PLLFrefTableConfig(HSE_VALUE);
-#endif
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-/**
- * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo72M(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT9);
-#if defined (AT32F415xx)
- /* Config PLL clock resource Table */
- RCC_PLLFrefTableConfig(HSE_VALUE);
-#endif
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_96MHz
-/**
- * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo96M(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
-#if defined (AT32F415xx)
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT12);
-#else
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT12 | RCC_CFG_PLLRANGE_GT72MHZ);
-#endif
-#if defined (AT32F415xx)
- /* Config PLL clock resource Table */
- RCC_PLLFrefTableConfig(HSE_VALUE);
-#endif
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_108MHz
-/**
- * @brief Sets System clock frequency to 108MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo108M(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = (HSE/2) * 27 = 108 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
-
-#if defined (AT32F415xx)
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT27);
-#else
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT27 \
- | RCC_CFG_PLLRANGE_GT72MHZ);
-#endif
-#if defined (AT32F415xx)
- /* Config PLL clock resource Table */
- RCC_PLLFrefTableConfig(HSE_VALUE);
-#endif
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_120MHz
-/**
- * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo120M(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
-
-#if defined (AT32F415xx)
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT15);
-#else
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT15 | RCC_CFG_PLLRANGE_GT72MHZ);
-#endif
-#if defined (AT32F415xx)
- /* Config PLL clock resource Table */
- RCC_PLLFrefTableConfig(HSE_VALUE);
-#endif
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx) || defined (AT32F415xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx) || defined (AT32F415xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_144MHz
-/**
- * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo144M(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
-
-#if defined (AT32F415xx)
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18);
-#else
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18 | RCC_CFG_PLLRANGE_GT72MHZ);
-#endif
-#if defined (AT32F415xx)
- /* Config PLL clock resource Table */
- RCC_PLLFrefTableConfig(HSE_VALUE);
-#endif
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx) || defined (AT32F415xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx) || defined (AT32F415xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_150MHz
-/**
- * @brief Sets System clock frequency to 150MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo150M(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = (HSE * 75) / (1 * 4) = 150 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE);
- RCC_PLLconfig2(PLL_FREF_8M, 75, 1, PLL_FR_4);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx) || defined (AT32F415xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx) || defined (AT32F415xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_168MHz
-/**
- * @brief Sets System clock frequency to 168MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo168M(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = HSE * 21 = 168 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT21 | RCC_CFG_PLLRANGE_GT72MHZ);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_176MHz
-/**
- * @brief Sets System clock frequency to 176MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo176M(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = HSE * 22 = 176 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT22 | RCC_CFG_PLLRANGE_GT72MHZ);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_192MHz
-/**
- * @brief Sets System clock frequency to 192MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo192M(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = HSE * 24 = 192 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT24 | RCC_CFG_PLLRANGE_GT72MHZ);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_200MHz
-/**
- * @brief Sets System clock frequency to 200MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo200M(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = HSE * 25 = 200 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT25 | RCC_CFG_PLLRANGE_GT72MHZ);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_224MHz
-/**
- * @brief Sets System clock frequency to 224MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo224M(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = HSE * 28 = 224 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT28 | RCC_CFG_PLLRANGE_GT72MHZ);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_240MHz
-/**
- * @brief Sets System clock frequency to 240MHz and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo240M(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSE */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL;
- StartUpCounter++;
- }
- while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-#ifdef AT32F403xx
- WaitHseStbl(HSE_STABLE_DELAY);
-#endif
- if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = HSE * 30 = 240 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT30 | RCC_CFG_PLLRANGE_GT72MHZ);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
- else
- {
- /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-#elif defined SYSCLK_FREQ_24MHz_HSI
-/**
- * @brief Sets System clock frequency to 24MHz from HSI and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo24MHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
- StartUpCounter++;
- }
- while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
-
- if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1;
-
- /* PLL configuration: PLLCLK = (HSI/2) * 6 = 24 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT6);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
- }
-}
-
-#elif defined SYSCLK_FREQ_36MHz_HSI
-/**
- * @brief Sets System clock frequency to 36MHz from HSI and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo36MHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
- StartUpCounter++;
- }
- while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
-
- if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
-
- /* PCLK1 = HCLK */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1;
-
- /* PLL configuration: PLLCLK = (HSI/2) * 9 = 36 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT9);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
- }
-}
-
-#elif defined SYSCLK_FREQ_48MHz_HSI
-/**
- * @brief Sets System clock frequency to 48MHz from HSI and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo48MHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
- StartUpCounter++;
- }
- while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
-
- if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = (HSI/2) * 12 = 48 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT12);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
- }
-}
-
-#elif defined SYSCLK_FREQ_56MHz_HSI
-/**
- * @brief Sets System clock frequency to 56MHz from HSI and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo56MHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
- StartUpCounter++;
- }
- while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
-
- if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = (HSI/2) * 14 = 56 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT14);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
- }
-}
-
-#elif defined SYSCLK_FREQ_72MHz_HSI
-/**
- * @brief Sets System clock frequency to 72MHz from HSI and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo72MHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
- StartUpCounter++;
- }
- while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
-
- if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = (HSI/2) * 18 = 72 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT18);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
- }
-}
-
-#elif defined SYSCLK_FREQ_96MHz_HSI
-/**
- * @brief Sets System clock frequency to 96MHz from HSI and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo96MHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
- StartUpCounter++;
- }
- while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
-
- if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = (HSI/2) * 24 = 96 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
-
-#if defined (AT32F415xx)
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT24);
-#else
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT24 | RCC_CFG_PLLRANGE_GT72MHZ);
-#endif
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
- }
-}
-
-#elif defined SYSCLK_FREQ_108MHz_HSI
-/**
- * @brief Sets System clock frequency to 108MHz from HSI and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo108MHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
- StartUpCounter++;
- }
- while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
-
- if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = (HSI/2) * 27 = 108 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
-
-#if defined (AT32F415xx)
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT27);
-#else
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT27 | RCC_CFG_PLLRANGE_GT72MHZ);
-#endif
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
- }
-}
-
-#elif defined SYSCLK_FREQ_120MHz_HSI
-/**
- * @brief Sets System clock frequency to 120MHz from HSI and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo120MHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
- StartUpCounter++;
- }
- while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
-
- if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = (HSI/2) * 30 = 120 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
-
-#if defined (AT32F415xx)
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT30);
-#else
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT30 | RCC_CFG_PLLRANGE_GT72MHZ);
-#endif
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx) || defined (AT32F415xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx) || defined (AT32F415xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
-}
-
-#elif defined SYSCLK_FREQ_144MHz_HSI
-/**
- * @brief Sets System clock frequency to 144MHz from HSI and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo144MHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
- StartUpCounter++;
- }
- while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
-
- if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = (HSI/2) * 36 = 144 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
-
-#if defined (AT32F415xx)
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT36);
-#else
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT36 | RCC_CFG_PLLRANGE_GT72MHZ);
-#endif
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx) || defined (AT32F415xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx) || defined (AT32F415xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
-}
-
-#elif defined SYSCLK_FREQ_150MHz_HSI
-/**
- * @brief Sets System clock frequency to 150MHz from HSI and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo150MHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
- StartUpCounter++;
- }
- while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
-
- if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
-#if defined (AT32F415xx)
- /* Enable Prefetch Buffer */
- FLASH->ACR |= FLASH_ACR_PRFTBE;
-
- /* Flash 1 wait state */
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4;
-#endif
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = ((HSI/2) * 150) / (1 * 4) = 150 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2);
- RCC_PLLconfig2(PLL_FREF_4M, 150, 1, PLL_FR_4);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx) || defined (AT32F415xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx) || defined (AT32F415xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
-}
-
-#elif defined SYSCLK_FREQ_168MHz_HSI
-/**
- * @brief Sets System clock frequency to 168MHz from HSI and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo168MHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
- StartUpCounter++;
- }
- while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
-
- if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = (HSI/2) * 42 = 168 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT42 | RCC_CFG_PLLRANGE_GT72MHZ);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
-}
-#elif defined SYSCLK_FREQ_176MHz_HSI
-/**
- * @brief Sets System clock frequency to 176MHz from HSI and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo176MHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
- StartUpCounter++;
- }
- while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
-
- if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = (HSI/2) * 44 = 176 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT44 | RCC_CFG_PLLRANGE_GT72MHZ);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
-}
-#elif defined SYSCLK_FREQ_192MHz_HSI
-/**
- * @brief Sets System clock frequency to 192MHz from HSI and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo192MHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
- StartUpCounter++;
- }
- while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
-
- if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = (HSI/2) * 48 = 192 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT48 | RCC_CFG_PLLRANGE_GT72MHZ);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
-}
-#elif defined SYSCLK_FREQ_200MHz_HSI
-/**
- * @brief Sets System clock frequency to 200MHz from HSI and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo200MHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
- StartUpCounter++;
- }
- while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
-
- if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = (HSI/2) * 50 = 200 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT50 | RCC_CFG_PLLRANGE_GT72MHZ);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
-}
-
-#elif defined SYSCLK_FREQ_224MHz_HSI
-/**
- * @brief Sets System clock frequency to 224MHz from HSI and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo224MHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
- StartUpCounter++;
- }
- while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
-
- if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = (HSI/2) * 56 = 224 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT56 | RCC_CFG_PLLRANGE_GT72MHZ);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
-}
-
-#elif defined SYSCLK_FREQ_240MHz_HSI
-/**
- * @brief Sets System clock frequency to 240MHz from HSI and configure HCLK, PCLK2
- * and PCLK1 prescalers.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-static void SetSysClockTo240MHSI(void)
-{
- __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
-
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
- /* Enable HSI */
- RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN);
-
- /* Wait till HSI is ready and if Time out is reached exit */
- do
- {
- HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL;
- StartUpCounter++;
- }
- while((HSIStatus == 0) && (StartUpCounter != 0xFFFF));
-
- if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET)
- {
- HSIStatus = (uint32_t)0x01;
- }
- else
- {
- HSIStatus = (uint32_t)0x00;
- }
-
- if (HSIStatus == (uint32_t)0x01)
- {
- /* HCLK = SYSCLK */
- RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1;
-
- /* PCLK2 = HCLK/2 */
- RCC->CFG &= 0xFFFFC7FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2;
-
- /* PCLK1 = HCLK/2 */
- RCC->CFG &= 0xFFFFF8FF;
- RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2;
-
- /* PLL configuration: PLLCLK = (HSI/2) * 60 = 240 MHz */
- RCC->CFG &= RCC_CFG_PLLCFG_MASK;
- RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT60 | RCC_CFG_PLLRANGE_GT72MHZ);
-
- /* Enable PLL */
- RCC->CTRL |= RCC_CTRL_PLLEN;
-
- /* Wait till PLL is ready */
- while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0)
- {
- }
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(ENABLE);
-#endif
- /* Select PLL as system clock source */
- RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL));
- RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL)
- {
- }
-#ifdef AT32F403xx
- WaitHseStbl(PLL_STABLE_DELAY);
-#endif
-#if defined (AT32F413xx) || defined (AT32F403Axx)|| \
- defined (AT32F407xx)
- RCC_StepModeCmd(DISABLE);
-#endif
- }
-}
-
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403acct7.s b/.platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403acct7.s
similarity index 100%
rename from .platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403acct7.s
rename to .platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403acct7.s
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403accu7.s b/.platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403accu7.s
similarity index 100%
rename from .platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403accu7.s
rename to .platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403accu7.s
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403acet7.s b/.platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403acet7.s
similarity index 100%
rename from .platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403acet7.s
rename to .platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403acet7.s
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403aceu7.s b/.platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403aceu7.s
similarity index 100%
rename from .platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403aceu7.s
rename to .platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403aceu7.s
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403acgt7.s b/.platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403acgt7.s
similarity index 100%
rename from .platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403acgt7.s
rename to .platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403acgt7.s
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403acgu7.s b/.platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403acgu7.s
similarity index 100%
rename from .platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403acgu7.s
rename to .platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403acgu7.s
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403arct7.s b/.platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403arct7.s
similarity index 100%
rename from .platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403arct7.s
rename to .platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403arct7.s
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403aret7.s b/.platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403aret7.s
similarity index 100%
rename from .platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403aret7.s
rename to .platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403aret7.s
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403argt7.s b/.platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403argt7.s
similarity index 100%
rename from .platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403argt7.s
rename to .platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403argt7.s
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403avct7.s b/.platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403avct7.s
similarity index 100%
rename from .platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403avct7.s
rename to .platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403avct7.s
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403avet7.s b/.platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403avet7.s
similarity index 100%
rename from .platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403avet7.s
rename to .platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403avet7.s
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403avgt7.s b/.platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403avgt7.s
similarity index 100%
rename from .platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/startup_at32f403avgt7.s
rename to .platformio/packages/framework-cmsis-at32f40/Startup/gcc/startup_at32f403avgt7.s
diff --git a/.platformio/packages/framework-cmsis-at32f40/libraries/AT32_USB-FS-Device_Driver/src/usb_core.c b/.platformio/packages/framework-cmsis-at32f40/libraries/AT32_USB-FS-Device_Driver/src/usb_core.c
index ecb9885..6d683ce 100644
--- a/.platformio/packages/framework-cmsis-at32f40/libraries/AT32_USB-FS-Device_Driver/src/usb_core.c
+++ b/.platformio/packages/framework-cmsis-at32f40/libraries/AT32_USB-FS-Device_Driver/src/usb_core.c
@@ -422,7 +422,6 @@ void DataStageOut(void)
pEPinfo->Usb_rLength -= Length;
pEPinfo->Usb_rOffset += Length;
PMAToUserBufferCopy(Buffer, GetEPRxAddr(ENDP0), Length);
-
}
if (pEPinfo->Usb_rLength != 0)
@@ -444,6 +443,7 @@ void DataStageOut(void)
}
else if (pEPinfo->Usb_rLength == 0)
{
+ (*pEPinfo->CopyData)(0); //added to notify write to array finished
pInformation->ControlState = WAIT_STATUS_IN;
USB_StatusIn();
}
@@ -478,9 +478,7 @@ void DataStageIn(void)
/* No more data to send so STALL the TX Status*/
ControlState = WAIT_STATUS_OUT;
vSetEPTxStatus(EP_TX_STALL);
-
}
-
goto Expect_Status_Out;
}
diff --git a/.platformio/packages/framework-cmsis-at32f40/libraries/AT32_USB-FS-Device_Driver/src/usb_init.c b/.platformio/packages/framework-cmsis-at32f40/libraries/AT32_USB-FS-Device_Driver/src/usb_init.c
index a17a70b..673abe3 100644
--- a/.platformio/packages/framework-cmsis-at32f40/libraries/AT32_USB-FS-Device_Driver/src/usb_init.c
+++ b/.platformio/packages/framework-cmsis-at32f40/libraries/AT32_USB-FS-Device_Driver/src/usb_init.c
@@ -88,8 +88,6 @@ void USB_BluePill_Reenumerate()
*/
void USB_Init(void)
{
- /*if use USB SRAM_Size = 768 Byte, default is 512 Byte*/
- Set_USB768ByteMode();
//reenumerate();
//USB_BluePill_Reenumerate();
pInformation = &Device_Info;
diff --git a/.platformio/packages/framework-cmsis-at32f40/libraries/AT32_USB-FS-Device_Driver/src/usb_int.c b/.platformio/packages/framework-cmsis-at32f40/libraries/AT32_USB-FS-Device_Driver/src/usb_int.c
index 8ba7afc..1358e90 100644
--- a/.platformio/packages/framework-cmsis-at32f40/libraries/AT32_USB-FS-Device_Driver/src/usb_int.c
+++ b/.platformio/packages/framework-cmsis-at32f40/libraries/AT32_USB-FS-Device_Driver/src/usb_int.c
@@ -38,7 +38,34 @@ void CTR_LP(void)
{
/* extract highest priority endpoint number */
EPindex = (uint8_t)(wIstr & INTSTS_EP_ID);
- if (EPindex == 0 )
+ if (EPindex != 0 )
+ {
+ /* Decode and service non control endpoints interrupt */
+
+ /* process related endpoint register */
+ wEPVal = _GetENDPOINT(EPindex);
+ if ((wEPVal & EP_CTFR_TX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTFR_TX(EPindex);
+
+ /* call IN service function */
+ (*pEpInt_IN[EPindex-1])();
+ continue;
+ } /* if((wEPVal & EP_CTFR_TX) != 0) */
+
+ if ((wEPVal & EP_CTFR_RX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTFR_RX(EPindex);
+
+ /* call OUT service function */
+ (*pEpInt_OUT[EPindex-1])();
+
+ } /* if((wEPVal & EP_CTFR_RX) */
+
+ }/* if(EPindex != 0) */
+ else
{
/* Decode and service control endpoint interrupt */
/* calling related service routine */
@@ -99,33 +126,7 @@ void CTR_LP(void)
return;
}
}
- }/* if(EPindex == 0) */
- else
- {
- /* Decode and service non control endpoints interrupt */
-
- /* process related endpoint register */
- wEPVal = _GetENDPOINT(EPindex);
- if ((wEPVal & EP_CTFR_RX) != 0)
- {
- /* clear int flag */
- _ClearEP_CTFR_RX(EPindex);
-
- /* call OUT service function */
- (*pEpInt_OUT[EPindex-1])();
-
- } /* if((wEPVal & EP_CTFR_RX) */
-
- if ((wEPVal & EP_CTFR_TX) != 0)
- {
- /* clear int flag */
- _ClearEP_CTFR_TX(EPindex);
-
- /* call IN service function */
- (*pEpInt_IN[EPindex-1])();
- } /* if((wEPVal & EP_CTFR_TX) != 0) */
-
- }/* if(EPindex == 0) else */
+ }/* if(EPindex != 0) else */
}/* while(...) */
}
diff --git a/.platformio/packages/framework-cmsis-at32f40/piopm b/.platformio/packages/framework-cmsis-at32f40/piopm
deleted file mode 100644
index 683df28..0000000
--- a/.platformio/packages/framework-cmsis-at32f40/piopm
+++ /dev/null
@@ -1 +0,0 @@
-{"type": "tool", "name": "framework-cmsis-at32f40", "version": "1.0.0", "spec": {"owner": "platformio", "id": 8089, "name": "framework-cmsis-at32f40", "requirements": null, "url": null}}
\ No newline at end of file
diff --git a/.platformio/packages/framework-cmsis-at32f43/.github/ISSUE_TEMPLATE/bug_report.md b/.platformio/packages/framework-cmsis-at32f43/.github/ISSUE_TEMPLATE/bug_report.md
new file mode 100644
index 0000000..a03bdb2
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/.github/ISSUE_TEMPLATE/bug_report.md
@@ -0,0 +1,34 @@
+---
+name: Bug report
+about: Create a report to help us improve
+title: ''
+labels: ''
+assignees: ''
+
+---
+
+**Caution**
+The Issues are strictly limited for the reporting of problem encountered with the software provided in this project.
+
+**Describe the set-up**
+ * The board
+ * IDE or at least the compiler and its version
+
+**Describe the bug**
+A clear and concise description of what the bug is.
+
+**How To Reproduce**
+1. Indicate the global behavior of your application project
+
+2. The modules that you suspect to be the cause of the problem (Driver, BSP, MW ...)
+
+3. The use case that generates the problem
+
+4. How we can reproduce the problem
+
+
+**Additional context**
+If you have a first analysis or patch correction, thank you to share your proposal.
+
+**Screenshots**
+If applicable, add screenshots to help explain your problem.
diff --git a/.platformio/packages/framework-cmsis-at32f43/.github/ISSUE_TEMPLATE/other-issue.md b/.platformio/packages/framework-cmsis-at32f43/.github/ISSUE_TEMPLATE/other-issue.md
new file mode 100644
index 0000000..d9dc00e
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/.github/ISSUE_TEMPLATE/other-issue.md
@@ -0,0 +1,21 @@
+---
+name: 'Other Issue '
+about: Generic issue description
+title: ''
+labels: ''
+assignees: ''
+
+---
+
+**Caution**
+The Issues are strictly limited for the reporting of problem encountered with the software provided in this project.
+
+**Describe the set-up**
+ * The board
+ * IDE or at least the compiler and its version
+
+**Additional context**
+If you have a first analysis or a patch proposal, thank you to share your proposal.
+
+**Screenshots**
+If applicable, add screenshots to help explain your problem.
diff --git a/.platformio/packages/framework-cmsis-at32f43/.github/PULL_REQUEST_TEMPLATE.md b/.platformio/packages/framework-cmsis-at32f43/.github/PULL_REQUEST_TEMPLATE.md
new file mode 100644
index 0000000..721da06
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/.github/PULL_REQUEST_TEMPLATE.md
@@ -0,0 +1,8 @@
+## IMPORTANT INFORMATION
+
+### Contributor License Agreement (CLA)
+* The Pull Request feature will be considered by STMicroelectronics only after a **Contributor License Agreement (CLA)** mechanism has been deployed.
+* We are currently working on the set-up of this procedure.
+
+
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/.piopm b/.platformio/packages/framework-cmsis-at32f43/.piopm
new file mode 100644
index 0000000..47726ef
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/.piopm
@@ -0,0 +1 @@
+{"type": "tool", "name": "framework-cmsis-at32f43", "version": "1.0.0", "spec": {"owner": "platformio", "id": 8089, "name": "framework-cmsis-at32f43", "requirements": null, "url": null}}
\ No newline at end of file
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437.h
new file mode 100644
index 0000000..6361691
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437.h
@@ -0,0 +1,779 @@
+/**
+ **************************************************************************
+ * @file at32f435_437.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#ifndef __AT32F435_437_H
+#define __AT32F435_437_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__CC_ARM)
+ #pragma anon_unions
+#endif
+
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup AT32F435_437
+ * @{
+ */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * tip: to avoid modifying this file each time you need to switch between these
+ * devices, you can define the device in your toolchain compiler preprocessor.
+ */
+
+#if !defined (AT32F435CCU7) && !defined (AT32F435CGU7) && !defined (AT32F435CMU7) && \
+ !defined (AT32F435CCT7) && !defined (AT32F435CGT7) && !defined (AT32F435CMT7) && \
+ !defined (AT32F435RCT7) && !defined (AT32F435RGT7) && !defined (AT32F435RMT7) && \
+ !defined (AT32F435VCT7) && !defined (AT32F435VGT7) && !defined (AT32F435VMT7) && \
+ !defined (AT32F435ZCT7) && !defined (AT32F435ZGT7) && !defined (AT32F435ZMT7) && \
+ !defined (AT32F437RCT7) && !defined (AT32F437RGT7) && !defined (AT32F437RMT7) && \
+ !defined (AT32F437VCT7) && !defined (AT32F437VGT7) && !defined (AT32F437VMT7) && \
+ !defined (AT32F437ZCT7) && !defined (AT32F437ZGT7) && !defined (AT32F437ZMT7)
+
+ #error "Please select first the target device used in your application (in at32f435_437.h file)"
+#endif
+
+#if defined (AT32F435CCU7) || defined (AT32F435CGU7) || defined (AT32F435CMU7) || \
+ defined (AT32F435CCT7) || defined (AT32F435CGT7) || defined (AT32F435CMT7) || \
+ defined (AT32F435RCT7) || defined (AT32F435RGT7) || defined (AT32F435RMT7) || \
+ defined (AT32F435VCT7) || defined (AT32F435VGT7) || defined (AT32F435VMT7) || \
+ defined (AT32F435ZCT7) || defined (AT32F435ZGT7) || defined (AT32F435ZMT7)
+
+ #define AT32F435xx
+#endif
+
+#if defined (AT32F437RCT7) || defined (AT32F437RGT7) || defined (AT32F437RMT7) || \
+ defined (AT32F437VCT7) || defined (AT32F437VGT7) || defined (AT32F437VMT7) || \
+ defined (AT32F437ZCT7) || defined (AT32F437ZGT7) || defined (AT32F437ZMT7)
+
+ #define AT32F437xx
+#endif
+
+#ifndef USE_STDPERIPH_DRIVER
+/**
+ * @brief comment the line below if you will not use the peripherals drivers.
+ * in this case, these drivers will not be included and the application code will
+ * be based on direct access to peripherals registers
+ */
+ #ifdef _RTE_
+ #include "RTE_Components.h"
+ #ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK
+ #define USE_STDPERIPH_DRIVER
+ #endif
+ #endif
+#endif
+
+/**
+ * @brief at32f435_437 standard peripheral library version number
+ */
+#define __AT32F435_437_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
+#define __AT32F435_437_LIBRARY_VERSION_MIDDLE (0x00) /*!< [23:16] middle version */
+#define __AT32F435_437_LIBRARY_VERSION_MINOR (0x04) /*!< [15:8] minor version */
+#define __AT32F435_437_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __AT32F435_437_LIBRARY_VERSION ((__AT32F435_437_LIBRARY_VERSION_MAJOR << 24) | \
+ (__AT32F435_437_LIBRARY_VERSION_MIDDLE << 16) | \
+ (__AT32F435_437_LIBRARY_VERSION_MINOR << 8) | \
+ (__AT32F435_437_LIBRARY_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup configuration_section_for_cmsis
+ * @{
+ */
+
+/**
+ * @brief configuration of the cortex-m4 processor and core peripherals
+ */
+#define __CM4_REV 0x0001U /*!< core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< mpu present */
+#define __NVIC_PRIO_BITS 4 /*!< at32 uses 4 bits for the priority levels */
+#define __Vendor_SysTickConfig 0 /*!< set to 1 if different systick config is used */
+#define __FPU_PRESENT 1U /*!< fpu present */
+
+/**
+ * @brief at32f435_437 interrupt number definition, according to the selected device
+ * in @ref library_configuration_section
+ */
+typedef enum IRQn
+{
+ /****** cortex-m4 processor exceptions numbers ***************************************************/
+ Reset_IRQn = -15, /*!< 1 reset vector, invoked on power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
+ HardFault_IRQn = -13, /*!< 3 hard fault, all classes of fault */
+ MemoryManagement_IRQn = -12, /*!< 4 cortex-m4 memory management interrupt */
+ BusFault_IRQn = -11, /*!< 5 cortex-m4 bus fault interrupt */
+ UsageFault_IRQn = -10, /*!< 6 cortex-m4 usage fault interrupt */
+ SVCall_IRQn = -5, /*!< 11 cortex-m4 sv call interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 cortex-m4 debug monitor interrupt */
+ PendSV_IRQn = -2, /*!< 14 cortex-m4 pend sv interrupt */
+ SysTick_IRQn = -1, /*!< 15 cortex-m4 system tick interrupt */
+
+ /****** at32 specific interrupt numbers *********************************************************/
+ WWDT_IRQn = 0, /*!< window watchdog timer interrupt */
+ PVM_IRQn = 1, /*!< pvm through exint line detection interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< tamper and timestamp interrupts through the exint line */
+ ERTC_WKUP_IRQn = 3, /*!< ertc wakeup through the exint line */
+ FLASH_IRQn = 4, /*!< flash global interrupt */
+ CRM_IRQn = 5, /*!< crm global interrupt */
+ EXINT0_IRQn = 6, /*!< exint line0 interrupt */
+ EXINT1_IRQn = 7, /*!< exint line1 interrupt */
+ EXINT2_IRQn = 8, /*!< exint line2 interrupt */
+ EXINT3_IRQn = 9, /*!< exint line3 interrupt */
+ EXINT4_IRQn = 10, /*!< exint line4 interrupt */
+ EDMA_Stream1_IRQn = 11, /*!< edma stream 1 global interrupt */
+ EDMA_Stream2_IRQn = 12, /*!< edma stream 2 global interrupt */
+ EDMA_Stream3_IRQn = 13, /*!< edma stream 3 global interrupt */
+ EDMA_Stream4_IRQn = 14, /*!< edma stream 4 global interrupt */
+ EDMA_Stream5_IRQn = 15, /*!< edma stream 5 global interrupt */
+ EDMA_Stream6_IRQn = 16, /*!< edma stream 6 global interrupt */
+ EDMA_Stream7_IRQn = 17, /*!< edma stream 7 global interrupt */
+
+#if defined (AT32F435xx)
+ ADC1_2_3_IRQn = 18, /*!< adc1 adc2 and adc3 global interrupt */
+ CAN1_TX_IRQn = 19, /*!< can1 tx interrupts */
+ CAN1_RX0_IRQn = 20, /*!< can1 rx0 interrupts */
+ CAN1_RX1_IRQn = 21, /*!< can1 rx1 interrupt */
+ CAN1_SE_IRQn = 22, /*!< can1 se interrupt */
+ EXINT9_5_IRQn = 23, /*!< external line[9:5] interrupts */
+ TMR1_BRK_TMR9_IRQn = 24, /*!< tmr1 brake interrupt */
+ TMR1_OVF_TMR10_IRQn = 25, /*!< tmr1 overflow interrupt */
+ TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< tmr1 trigger and hall interrupt */
+ TMR1_CH_IRQn = 27, /*!< tmr1 channel interrupt */
+ TMR2_GLOBAL_IRQn = 28, /*!< tmr2 global interrupt */
+ TMR3_GLOBAL_IRQn = 29, /*!< tmr3 global interrupt */
+ TMR4_GLOBAL_IRQn = 30, /*!< tmr4 global interrupt */
+ I2C1_EVT_IRQn = 31, /*!< i2c1 event interrupt */
+ I2C1_ERR_IRQn = 32, /*!< i2c1 error interrupt */
+ I2C2_EVT_IRQn = 33, /*!< i2c2 event interrupt */
+ I2C2_ERR_IRQn = 34, /*!< i2c2 error interrupt */
+ SPI1_IRQn = 35, /*!< spi1 global interrupt */
+ SPI2_I2S2EXT_IRQn = 36, /*!< spi2 global interrupt */
+ USART1_IRQn = 37, /*!< usart1 global interrupt */
+ USART2_IRQn = 38, /*!< usart2 global interrupt */
+ USART3_IRQn = 39, /*!< usart3 global interrupt */
+ EXINT15_10_IRQn = 40, /*!< external line[15:10] interrupts */
+ ERTCAlarm_IRQn = 41, /*!< ertc alarm through exint line interrupt */
+ OTGFS1_WKUP_IRQn = 42, /*!< otgfs1 wakeup from suspend through exint line interrupt */
+ TMR8_BRK_TMR12_IRQn = 43, /*!< tmr8 brake interrupt */
+ TMR8_OVF_TMR13_IRQn = 44, /*!< tmr8 overflow interrupt */
+ TMR8_TRG_HALL_TMR14_IRQn = 45, /*!< tmr8 trigger and hall interrupt */
+ TMR8_CH_IRQn = 46, /*!< tmr8 channel interrupt */
+ EDMA_Stream8_IRQn = 47, /*!< edma stream 8 global interrupt */
+ XMC_IRQn = 48, /*!< xmc global interrupt */
+ SDIO1_IRQn = 49, /*!< sdio global interrupt */
+ TMR5_GLOBAL_IRQn = 50, /*!< tmr5 global interrupt */
+ SPI3_I2S3EXT_IRQn = 51, /*!< spi3 global interrupt */
+ UART4_IRQn = 52, /*!< uart4 global interrupt */
+ UART5_IRQn = 53, /*!< uart5 global interrupt */
+ TMR6_DAC_GLOBAL_IRQn = 54, /*!< tmr6 and dac global interrupt */
+ TMR7_GLOBAL_IRQn = 55, /*!< tmr7 global interrupt */
+ DMA1_Channel1_IRQn = 56, /*!< dma1 channel 0 global interrupt */
+ DMA1_Channel2_IRQn = 57, /*!< dma1 channel 1 global interrupt */
+ DMA1_Channel3_IRQn = 58, /*!< dma1 channel 2 global interrupt */
+ DMA1_Channel4_IRQn = 59, /*!< dma1 channel 3 global interrupt */
+ DMA1_Channel5_IRQn = 60, /*!< dma1 channel 4 global interrupt */
+ CAN2_TX_IRQn = 63, /*!< can2 tx interrupt */
+ CAN2_RX0_IRQn = 64, /*!< can2 rx0 interrupt */
+ CAN2_RX1_IRQn = 65, /*!< can2 rx1 interrupt */
+ CAN2_SE_IRQn = 66, /*!< can2 se interrupt */
+ OTGFS1_IRQn = 67, /*!< otgfs1 interrupt */
+ DMA1_Channel6_IRQn = 68, /*!< dma1 channel 5 global interrupt */
+ DMA1_Channel7_IRQn = 69, /*!< dma1 channel 6 global interrupt */
+ USART6_IRQn = 71, /*!< usart6 interrupt */
+ I2C3_EVT_IRQn = 72, /*!< i2c3 event interrupt */
+ I2C3_ERR_IRQn = 73, /*!< i2c3 error interrupt */
+ OTGFS2_WKUP_IRQn = 76, /*!< otgfs2 wakeup from suspend through exint line interrupt */
+ OTGFS2_IRQn = 77, /*!< otgfs2 interrupt */
+ DVP_IRQn = 78, /*!< dvp interrupt */
+ FPU_IRQn = 81, /*!< fpu interrupt */
+ UART7_IRQn = 82, /*!< uart7 interrupt */
+ UART8_IRQn = 83, /*!< uart8 interrupt */
+ SPI4_IRQn = 84, /*!< spi4 global interrupt */
+ QSPI2_IRQn = 91, /*!< qspi2 global interrupt */
+ QSPI1_IRQn = 92, /*!< qspi1 global interrupt */
+ DMAMUX_IRQn = 94, /*!< dmamux global interrupt */
+ SDIO2_IRQn = 102, /*!< sdio2 global interrupt */
+ ACC_IRQn = 103, /*!< acc interrupt */
+ TMR20_BRK_IRQn = 104, /*!< tmr20 brake interrupt */
+ TMR20_OVF_IRQn = 105, /*!< tmr20 overflow interrupt */
+ TMR20_TRG_HALL_IRQn = 106, /*!< tmr20 trigger and hall interrupt */
+ TMR20_CH_IRQn = 107, /*!< tmr20 channel interrupt */
+ DMA2_Channel1_IRQn = 108, /*!< dma1 channel 1 global interrupt */
+ DMA2_Channel2_IRQn = 109, /*!< dma1 channel 2 global interrupt */
+ DMA2_Channel3_IRQn = 110, /*!< dma1 channel 3 global interrupt */
+ DMA2_Channel4_IRQn = 111, /*!< dma1 channel 4 global interrupt */
+ DMA2_Channel5_IRQn = 112, /*!< dma1 channel 5 global interrupt */
+ DMA2_Channel6_IRQn = 113, /*!< dma1 channel 6 global interrupt */
+ DMA2_Channel7_IRQn = 114, /*!< dma1 channel 7 global interrupt */
+#endif
+
+#if defined (AT32F437xx)
+ ADC1_2_3_IRQn = 18, /*!< adc1 adc2 and adc3 global interrupt */
+ CAN1_TX_IRQn = 19, /*!< can1 tx interrupts */
+ CAN1_RX0_IRQn = 20, /*!< can1 rx0 interrupts */
+ CAN1_RX1_IRQn = 21, /*!< can1 rx1 interrupt */
+ CAN1_SE_IRQn = 22, /*!< can1 se interrupt */
+ EXINT9_5_IRQn = 23, /*!< external line[9:5] interrupts */
+ TMR1_BRK_TMR9_IRQn = 24, /*!< tmr1 brake interrupt */
+ TMR1_OVF_TMR10_IRQn = 25, /*!< tmr1 overflow interrupt */
+ TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< tmr1 trigger and hall interrupt */
+ TMR1_CH_IRQn = 27, /*!< tmr1 channel interrupt */
+ TMR2_GLOBAL_IRQn = 28, /*!< tmr2 global interrupt */
+ TMR3_GLOBAL_IRQn = 29, /*!< tmr3 global interrupt */
+ TMR4_GLOBAL_IRQn = 30, /*!< tmr4 global interrupt */
+ I2C1_EVT_IRQn = 31, /*!< i2c1 event interrupt */
+ I2C1_ERR_IRQn = 32, /*!< i2c1 error interrupt */
+ I2C2_EVT_IRQn = 33, /*!< i2c2 event interrupt */
+ I2C2_ERR_IRQn = 34, /*!< i2c2 error interrupt */
+ SPI1_IRQn = 35, /*!< spi1 global interrupt */
+ SPI2_I2S2EXT_IRQn = 36, /*!< spi2 global interrupt */
+ USART1_IRQn = 37, /*!< usart1 global interrupt */
+ USART2_IRQn = 38, /*!< usart2 global interrupt */
+ USART3_IRQn = 39, /*!< usart3 global interrupt */
+ EXINT15_10_IRQn = 40, /*!< external line[15:10] interrupts */
+ ERTCAlarm_IRQn = 41, /*!< ertc alarm through exint line interrupt */
+ OTGFS1_WKUP_IRQn = 42, /*!< otgfs1 wakeup from suspend through exint line interrupt */
+ TMR8_BRK_TMR12_IRQn = 43, /*!< tmr8 brake interrupt */
+ TMR8_OVF_TMR13_IRQn = 44, /*!< tmr8 overflow interrupt */
+ TMR8_TRG_HALL_TMR14_IRQn = 45, /*!< tmr8 trigger and hall interrupt */
+ TMR8_CH_IRQn = 46, /*!< tmr8 channel interrupt */
+ EDMA_Stream8_IRQn = 47, /*!< dma1 stream 8 global interrupt */
+ XMC_IRQn = 48, /*!< xmc global interrupt */
+ SDIO1_IRQn = 49, /*!< sdio global interrupt */
+ TMR5_GLOBAL_IRQn = 50, /*!< tmr5 global interrupt */
+ SPI3_I2S3EXT_IRQn = 51, /*!< spi3 global interrupt */
+ UART4_IRQn = 52, /*!< uart4 global interrupt */
+ UART5_IRQn = 53, /*!< uart5 global interrupt */
+ TMR6_DAC_GLOBAL_IRQn = 54, /*!< tmr6 and dac global interrupt */
+ TMR7_GLOBAL_IRQn = 55, /*!< tmr7 global interrupt */
+ DMA1_Channel1_IRQn = 56, /*!< dma1 channel 0 global interrupt */
+ DMA1_Channel2_IRQn = 57, /*!< dma1 channel 1 global interrupt */
+ DMA1_Channel3_IRQn = 58, /*!< dma1 channel 2 global interrupt */
+ DMA1_Channel4_IRQn = 59, /*!< dma1 channel 3 global interrupt */
+ DMA1_Channel5_IRQn = 60, /*!< dma1 channel 4 global interrupt */
+ EMAC_IRQn = 61, /*!< emac interrupt */
+ EMAC_WKUP_IRQn = 62, /*!< emac wakeup interrupt */
+ CAN2_TX_IRQn = 63, /*!< can2 tx interrupt */
+ CAN2_RX0_IRQn = 64, /*!< can2 rx0 interrupt */
+ CAN2_RX1_IRQn = 65, /*!< can2 rx1 interrupt */
+ CAN2_SE_IRQn = 66, /*!< can2 se interrupt */
+ OTGFS1_IRQn = 67, /*!< otgfs1 interrupt */
+ DMA1_Channel6_IRQn = 68, /*!< dma1 channel 5 global interrupt */
+ DMA1_Channel7_IRQn = 69, /*!< dma1 channel 6 global interrupt */
+ USART6_IRQn = 71, /*!< usart6 interrupt */
+ I2C3_EVT_IRQn = 72, /*!< i2c3 event interrupt */
+ I2C3_ERR_IRQn = 73, /*!< i2c3 error interrupt */
+ OTGFS2_WKUP_IRQn = 76, /*!< otgfs2 wakeup from suspend through exint line interrupt */
+ OTGFS2_IRQn = 77, /*!< otgfs2 interrupt */
+ DVP_IRQn = 78, /*!< dvp interrupt */
+ FPU_IRQn = 81, /*!< fpu interrupt */
+ UART7_IRQn = 82, /*!< uart7 interrupt */
+ UART8_IRQn = 83, /*!< uart8 interrupt */
+ SPI4_IRQn = 84, /*!< spi4 global interrupt */
+ QSPI2_IRQn = 91, /*!< qspi2 global interrupt */
+ QSPI1_IRQn = 92, /*!< qspi1 global interrupt */
+ DMAMUX_IRQn = 94, /*!< dmamux global interrupt */
+ SDIO2_IRQn = 102, /*!< sdio2 global interrupt */
+ ACC_IRQn = 103, /*!< acc interrupt */
+ TMR20_BRK_IRQn = 104, /*!< tmr20 brake interrupt */
+ TMR20_OVF_IRQn = 105, /*!< tmr20 overflow interrupt */
+ TMR20_TRG_HALL_IRQn = 106, /*!< tmr20 trigger and hall interrupt */
+ TMR20_CH_IRQn = 107, /*!< tmr20 channel interrupt */
+ DMA2_Channel1_IRQn = 108, /*!< dma1 channel 1 global interrupt */
+ DMA2_Channel2_IRQn = 109, /*!< dma1 channel 2 global interrupt */
+ DMA2_Channel3_IRQn = 110, /*!< dma1 channel 3 global interrupt */
+ DMA2_Channel4_IRQn = 111, /*!< dma1 channel 4 global interrupt */
+ DMA2_Channel5_IRQn = 112, /*!< dma1 channel 5 global interrupt */
+ DMA2_Channel6_IRQn = 113, /*!< dma1 channel 6 global interrupt */
+ DMA2_Channel7_IRQn = 114, /*!< dma1 channel 7 global interrupt */
+#endif
+
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h"
+#include "system_at32f435_437.h"
+#include
+
+/** @addtogroup Exported_types
+ * @{
+ */
+
+typedef int32_t INT32;
+typedef int16_t INT16;
+typedef int8_t INT8;
+typedef uint32_t UINT32;
+typedef uint16_t UINT16;
+typedef uint8_t UINT8;
+
+typedef int32_t s32;
+typedef int16_t s16;
+typedef int8_t s8;
+
+typedef const int32_t sc32; /*!< read only */
+typedef const int16_t sc16; /*!< read only */
+typedef const int8_t sc8; /*!< read only */
+
+typedef __IO int32_t vs32;
+typedef __IO int16_t vs16;
+typedef __IO int8_t vs8;
+
+typedef __I int32_t vsc32; /*!< read only */
+typedef __I int16_t vsc16; /*!< read only */
+typedef __I int8_t vsc8; /*!< read only */
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+typedef const uint32_t uc32; /*!< read only */
+typedef const uint16_t uc16; /*!< read only */
+typedef const uint8_t uc8; /*!< read only */
+
+typedef __IO uint32_t vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t vu8;
+
+typedef __I uint32_t vuc32; /*!< read only */
+typedef __I uint16_t vuc16; /*!< read only */
+typedef __I uint8_t vuc8; /*!< read only */
+
+typedef enum {RESET = 0, SET = !RESET} flag_status;
+typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
+typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+#define REG8(addr) *(volatile uint8_t *)(addr)
+#define REG16(addr) *(volatile uint16_t *)(addr)
+#define REG32(addr) *(volatile uint32_t *)(addr)
+
+#define MAKE_VALUE(reg_offset, bit_num) (((reg_offset) << 16) | (bit_num & 0x1f))
+
+#define PERIPH_REG(periph_base, value) REG32((periph_base + (value >> 16)))
+#define PERIPH_REG_BIT(value) (0x1u << (value & 0x1f))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define XMC_SDRAM_MEM_BASE ((uint32_t)0xC0000000)
+#define QSPI2_MEM_BASE ((uint32_t)0xB0000000)
+#define XMC_CARD_MEM_BASE ((uint32_t)0xA8000000)
+#define QSPI2_REG_BASE ((uint32_t)0xA0002000)
+#define QSPI1_REG_BASE ((uint32_t)0xA0001000)
+#define XMC_REG_BASE ((uint32_t)0xA0000000)
+#define XMC_BANK1_REG_BASE (XMC_REG_BASE + 0x0000)
+#define XMC_BANK2_REG_BASE (XMC_REG_BASE + 0x0060)
+#define XMC_BANK3_REG_BASE (XMC_REG_BASE + 0x0080)
+#define XMC_BANK4_REG_BASE (XMC_REG_BASE + 0x00A0)
+#define XMC_SDRAM_REG_BASE (XMC_REG_BASE + 0x0140)
+#define QSPI1_MEM_BASE ((uint32_t)0x90000000)
+#define XMC_MEM_BASE ((uint32_t)0x60000000)
+#define PERIPH_BASE ((uint32_t)0x40000000)
+#define SRAM_BB_BASE ((uint32_t)0x22000000)
+#define PERIPH_BB_BASE ((uint32_t)0x42000000)
+#define SRAM_BASE ((uint32_t)0x20000000)
+#define USD_BASE ((uint32_t)0x1FFFC000)
+#define FLASH_BASE ((uint32_t)0x08000000)
+
+#define DEBUG_BASE ((uint32_t)0xE0042000)
+
+#define APB1PERIPH_BASE (PERIPH_BASE)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH1_BASE (PERIPH_BASE + 0x20000)
+#define AHBPERIPH2_BASE (PERIPH_BASE + 0x10000000)
+
+#if defined (AT32F435xx)
+/* apb1 bus base address */
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define PWC_BASE (APB1PERIPH_BASE + 0x7000)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define WDT_BASE (APB1PERIPH_BASE + 0x3000)
+#define WWDT_BASE (APB1PERIPH_BASE + 0x2C00)
+#define ERTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define TMR14_BASE (APB1PERIPH_BASE + 0x2000)
+#define TMR13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TMR12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TMR7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TMR6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TMR5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TMR4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TMR3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TMR2_BASE (APB1PERIPH_BASE + 0x0000)
+/* apb2 bus base address */
+#define I2S2EXT_BASE (APB2PERIPH_BASE + 0x7800)
+#define I2S3EXT_BASE (APB2PERIPH_BASE + 0x7C00)
+#define ACC_BASE (APB2PERIPH_BASE + 0x7400)
+#define TMR20_BASE (APB2PERIPH_BASE + 0x4C00)
+#define TMR11_BASE (APB2PERIPH_BASE + 0x4800)
+#define TMR10_BASE (APB2PERIPH_BASE + 0x4400)
+#define TMR9_BASE (APB2PERIPH_BASE + 0x4000)
+#define EXINT_BASE (APB2PERIPH_BASE + 0x3C00)
+#define SCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
+#define ADCCOM_BASE (APB2PERIPH_BASE + 0x2300)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define TMR8_BASE (APB2PERIPH_BASE + 0x0400)
+#define TMR1_BASE (APB2PERIPH_BASE + 0x0000)
+/* ahb bus base address */
+#define OTGFS2_BASE (AHBPERIPH1_BASE + 0x20000)
+#define SDIO1_BASE (AHBPERIPH1_BASE + 0xC400)
+#define GPIOH_BASE (AHBPERIPH1_BASE + 0x1C00)
+#define GPIOG_BASE (AHBPERIPH1_BASE + 0x1800)
+#define GPIOF_BASE (AHBPERIPH1_BASE + 0x1400)
+#define GPIOE_BASE (AHBPERIPH1_BASE + 0x1000)
+#define GPIOD_BASE (AHBPERIPH1_BASE + 0x0C00)
+#define GPIOC_BASE (AHBPERIPH1_BASE + 0x0800)
+#define GPIOB_BASE (AHBPERIPH1_BASE + 0x0400)
+#define GPIOA_BASE (AHBPERIPH1_BASE + 0x0000)
+
+#define DMA1_BASE (AHBPERIPH1_BASE + 0x6400)
+#define DMA1_CHANNEL1_BASE (DMA1_BASE + 0x0008)
+#define DMA1_CHANNEL2_BASE (DMA1_BASE + 0x001C)
+#define DMA1_CHANNEL3_BASE (DMA1_BASE + 0x0030)
+#define DMA1_CHANNEL4_BASE (DMA1_BASE + 0x0044)
+#define DMA1_CHANNEL5_BASE (DMA1_BASE + 0x0058)
+#define DMA1_CHANNEL6_BASE (DMA1_BASE + 0x006C)
+#define DMA1_CHANNEL7_BASE (DMA1_BASE + 0x0080)
+
+#define DMA1MUX_BASE (DMA1_BASE + 0x0104)
+#define DMA1MUX_CHANNEL1_BASE (DMA1MUX_BASE)
+#define DMA1MUX_CHANNEL2_BASE (DMA1MUX_BASE + 0x0004)
+#define DMA1MUX_CHANNEL3_BASE (DMA1MUX_BASE + 0x0008)
+#define DMA1MUX_CHANNEL4_BASE (DMA1MUX_BASE + 0x000C)
+#define DMA1MUX_CHANNEL5_BASE (DMA1MUX_BASE + 0x0010)
+#define DMA1MUX_CHANNEL6_BASE (DMA1MUX_BASE + 0x0014)
+#define DMA1MUX_CHANNEL7_BASE (DMA1MUX_BASE + 0x0018)
+
+#define DMA1MUX_GENERATOR1_BASE (DMA1_BASE + 0x0120)
+#define DMA1MUX_GENERATOR2_BASE (DMA1_BASE + 0x0124)
+#define DMA1MUX_GENERATOR3_BASE (DMA1_BASE + 0x0128)
+#define DMA1MUX_GENERATOR4_BASE (DMA1_BASE + 0x012C)
+
+#define DMA2_BASE (AHBPERIPH1_BASE + 0x6600)
+#define DMA2_CHANNEL1_BASE (DMA2_BASE + 0x0008)
+#define DMA2_CHANNEL2_BASE (DMA2_BASE + 0x001C)
+#define DMA2_CHANNEL3_BASE (DMA2_BASE + 0x0030)
+#define DMA2_CHANNEL4_BASE (DMA2_BASE + 0x0044)
+#define DMA2_CHANNEL5_BASE (DMA2_BASE + 0x0058)
+#define DMA2_CHANNEL6_BASE (DMA2_BASE + 0x006C)
+#define DMA2_CHANNEL7_BASE (DMA2_BASE + 0x0080)
+
+#define DMA2MUX_BASE (DMA2_BASE + 0x0104)
+#define DMA2MUX_CHANNEL1_BASE (DMA2MUX_BASE)
+#define DMA2MUX_CHANNEL2_BASE (DMA2MUX_BASE + 0x0004)
+#define DMA2MUX_CHANNEL3_BASE (DMA2MUX_BASE + 0x0008)
+#define DMA2MUX_CHANNEL4_BASE (DMA2MUX_BASE + 0x000C)
+#define DMA2MUX_CHANNEL5_BASE (DMA2MUX_BASE + 0x0010)
+#define DMA2MUX_CHANNEL6_BASE (DMA2MUX_BASE + 0x0014)
+#define DMA2MUX_CHANNEL7_BASE (DMA2MUX_BASE + 0x0018)
+
+#define DMA2MUX_GENERATOR1_BASE (DMA2_BASE + 0x0120)
+#define DMA2MUX_GENERATOR2_BASE (DMA2_BASE + 0x0124)
+#define DMA2MUX_GENERATOR3_BASE (DMA2_BASE + 0x0128)
+#define DMA2MUX_GENERATOR4_BASE (DMA2_BASE + 0x012C)
+
+#define EDMA_BASE (AHBPERIPH1_BASE + 0x6000)
+#define EDMA_STREAM1_BASE (EDMA_BASE + 0x0010)
+#define EDMA_STREAM2_BASE (EDMA_BASE + 0x0028)
+#define EDMA_STREAM3_BASE (EDMA_BASE + 0x0040)
+#define EDMA_STREAM4_BASE (EDMA_BASE + 0x0058)
+#define EDMA_STREAM5_BASE (EDMA_BASE + 0x0070)
+#define EDMA_STREAM6_BASE (EDMA_BASE + 0x0088)
+#define EDMA_STREAM7_BASE (EDMA_BASE + 0x00A0)
+#define EDMA_STREAM8_BASE (EDMA_BASE + 0x00B8)
+
+#define EDMA_2D_BASE (EDMA_BASE + 0x00F4)
+#define EDMA_STREAM1_2D_BASE (EDMA_2D_BASE + 0x0004)
+#define EDMA_STREAM2_2D_BASE (EDMA_2D_BASE + 0x000C)
+#define EDMA_STREAM3_2D_BASE (EDMA_2D_BASE + 0x0014)
+#define EDMA_STREAM4_2D_BASE (EDMA_2D_BASE + 0x001C)
+#define EDMA_STREAM5_2D_BASE (EDMA_2D_BASE + 0x0024)
+#define EDMA_STREAM6_2D_BASE (EDMA_2D_BASE + 0x002C)
+#define EDMA_STREAM7_2D_BASE (EDMA_2D_BASE + 0x0034)
+#define EDMA_STREAM8_2D_BASE (EDMA_2D_BASE + 0x003C)
+
+#define EDMA_LL_BASE (EDMA_BASE + 0x00D0)
+#define EDMA_STREAM1_LL_BASE (EDMA_LL_BASE + 0x0004)
+#define EDMA_STREAM2_LL_BASE (EDMA_LL_BASE + 0x0008)
+#define EDMA_STREAM3_LL_BASE (EDMA_LL_BASE + 0x000C)
+#define EDMA_STREAM4_LL_BASE (EDMA_LL_BASE + 0x0010)
+#define EDMA_STREAM5_LL_BASE (EDMA_LL_BASE + 0x0014)
+#define EDMA_STREAM6_LL_BASE (EDMA_LL_BASE + 0x0018)
+#define EDMA_STREAM7_LL_BASE (EDMA_LL_BASE + 0x001C)
+#define EDMA_STREAM8_LL_BASE (EDMA_LL_BASE + 0x0020)
+
+#define EDMAMUX_BASE (EDMA_BASE + 0x0140)
+#define EDMAMUX_CHANNEL1_BASE (EDMAMUX_BASE)
+#define EDMAMUX_CHANNEL2_BASE (EDMAMUX_BASE + 0x0004)
+#define EDMAMUX_CHANNEL3_BASE (EDMAMUX_BASE + 0x0008)
+#define EDMAMUX_CHANNEL4_BASE (EDMAMUX_BASE + 0x000C)
+#define EDMAMUX_CHANNEL5_BASE (EDMAMUX_BASE + 0x0010)
+#define EDMAMUX_CHANNEL6_BASE (EDMAMUX_BASE + 0x0014)
+#define EDMAMUX_CHANNEL7_BASE (EDMAMUX_BASE + 0x0018)
+#define EDMAMUX_CHANNEL8_BASE (EDMAMUX_BASE + 0x001C)
+
+#define EDMAMUX_GENERATOR1_BASE (EDMA_BASE + 0x0160)
+#define EDMAMUX_GENERATOR2_BASE (EDMA_BASE + 0x0164)
+#define EDMAMUX_GENERATOR3_BASE (EDMA_BASE + 0x0168)
+#define EDMAMUX_GENERATOR4_BASE (EDMA_BASE + 0x016C)
+
+#define FLASH_REG_BASE (AHBPERIPH1_BASE + 0x3C00)
+#define CRM_BASE (AHBPERIPH1_BASE + 0x3800)
+#define CRC_BASE (AHBPERIPH1_BASE + 0x3000)
+#define SDIO2_BASE (AHBPERIPH2_BASE + 0x61000)
+#define DVP_BASE (AHBPERIPH2_BASE + 0x50000)
+#define OTGFS1_BASE (AHBPERIPH2_BASE + 0x00000)
+#endif
+
+#if defined (AT32F437xx)
+/* apb1 bus base address */
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define PWC_BASE (APB1PERIPH_BASE + 0x7000)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define WDT_BASE (APB1PERIPH_BASE + 0x3000)
+#define WWDT_BASE (APB1PERIPH_BASE + 0x2C00)
+#define ERTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define TMR14_BASE (APB1PERIPH_BASE + 0x2000)
+#define TMR13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TMR12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TMR7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TMR6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TMR5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TMR4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TMR3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TMR2_BASE (APB1PERIPH_BASE + 0x0000)
+/* apb2 bus base address */
+#define I2S2EXT_BASE (APB2PERIPH_BASE + 0x7800)
+#define I2S3EXT_BASE (APB2PERIPH_BASE + 0x7C00)
+#define ACC_BASE (APB2PERIPH_BASE + 0x7400)
+#define TMR20_BASE (APB2PERIPH_BASE + 0x4C00)
+#define TMR11_BASE (APB2PERIPH_BASE + 0x4800)
+#define TMR10_BASE (APB2PERIPH_BASE + 0x4400)
+#define TMR9_BASE (APB2PERIPH_BASE + 0x4000)
+#define EXINT_BASE (APB2PERIPH_BASE + 0x3C00)
+#define SCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
+#define ADCCOM_BASE (APB2PERIPH_BASE + 0x2300)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define TMR8_BASE (APB2PERIPH_BASE + 0x0400)
+#define TMR1_BASE (APB2PERIPH_BASE + 0x0000)
+/* ahb bus base address */
+#define OTGFS2_BASE (AHBPERIPH1_BASE + 0x20000)
+#define SDIO1_BASE (AHBPERIPH1_BASE + 0xC400)
+#define EMAC_BASE (AHBPERIPH1_BASE + 0x8000)
+#define GPIOH_BASE (AHBPERIPH1_BASE + 0x1C00)
+#define GPIOG_BASE (AHBPERIPH1_BASE + 0x1800)
+#define GPIOF_BASE (AHBPERIPH1_BASE + 0x1400)
+#define GPIOE_BASE (AHBPERIPH1_BASE + 0x1000)
+#define GPIOD_BASE (AHBPERIPH1_BASE + 0x0C00)
+#define GPIOC_BASE (AHBPERIPH1_BASE + 0x0800)
+#define GPIOB_BASE (AHBPERIPH1_BASE + 0x0400)
+#define GPIOA_BASE (AHBPERIPH1_BASE + 0x0000)
+
+#define DMA1_BASE (AHBPERIPH1_BASE + 0x6400)
+#define DMA1_CHANNEL1_BASE (DMA1_BASE + 0x0008)
+#define DMA1_CHANNEL2_BASE (DMA1_BASE + 0x001C)
+#define DMA1_CHANNEL3_BASE (DMA1_BASE + 0x0030)
+#define DMA1_CHANNEL4_BASE (DMA1_BASE + 0x0044)
+#define DMA1_CHANNEL5_BASE (DMA1_BASE + 0x0058)
+#define DMA1_CHANNEL6_BASE (DMA1_BASE + 0x006C)
+#define DMA1_CHANNEL7_BASE (DMA1_BASE + 0x0080)
+
+#define DMA1MUX_BASE (DMA1_BASE + 0x0104)
+#define DMA1MUX_CHANNEL1_BASE (DMA1MUX_BASE)
+#define DMA1MUX_CHANNEL2_BASE (DMA1MUX_BASE + 0x0004)
+#define DMA1MUX_CHANNEL3_BASE (DMA1MUX_BASE + 0x0008)
+#define DMA1MUX_CHANNEL4_BASE (DMA1MUX_BASE + 0x000C)
+#define DMA1MUX_CHANNEL5_BASE (DMA1MUX_BASE + 0x0010)
+#define DMA1MUX_CHANNEL6_BASE (DMA1MUX_BASE + 0x0014)
+#define DMA1MUX_CHANNEL7_BASE (DMA1MUX_BASE + 0x0018)
+
+#define DMA1MUX_GENERATOR1_BASE (DMA1_BASE + 0x0120)
+#define DMA1MUX_GENERATOR2_BASE (DMA1_BASE + 0x0124)
+#define DMA1MUX_GENERATOR3_BASE (DMA1_BASE + 0x0128)
+#define DMA1MUX_GENERATOR4_BASE (DMA1_BASE + 0x012C)
+
+#define DMA2_BASE (AHBPERIPH1_BASE + 0x6600)
+#define DMA2_CHANNEL1_BASE (DMA2_BASE + 0x0008)
+#define DMA2_CHANNEL2_BASE (DMA2_BASE + 0x001C)
+#define DMA2_CHANNEL3_BASE (DMA2_BASE + 0x0030)
+#define DMA2_CHANNEL4_BASE (DMA2_BASE + 0x0044)
+#define DMA2_CHANNEL5_BASE (DMA2_BASE + 0x0058)
+#define DMA2_CHANNEL6_BASE (DMA2_BASE + 0x006C)
+#define DMA2_CHANNEL7_BASE (DMA2_BASE + 0x0080)
+
+#define DMA2MUX_BASE (DMA2_BASE + 0x0104)
+#define DMA2MUX_CHANNEL1_BASE (DMA2MUX_BASE)
+#define DMA2MUX_CHANNEL2_BASE (DMA2MUX_BASE + 0x0004)
+#define DMA2MUX_CHANNEL3_BASE (DMA2MUX_BASE + 0x0008)
+#define DMA2MUX_CHANNEL4_BASE (DMA2MUX_BASE + 0x000C)
+#define DMA2MUX_CHANNEL5_BASE (DMA2MUX_BASE + 0x0010)
+#define DMA2MUX_CHANNEL6_BASE (DMA2MUX_BASE + 0x0014)
+#define DMA2MUX_CHANNEL7_BASE (DMA2MUX_BASE + 0x0018)
+
+#define DMA2MUX_GENERATOR1_BASE (DMA2_BASE + 0x0120)
+#define DMA2MUX_GENERATOR2_BASE (DMA2_BASE + 0x0124)
+#define DMA2MUX_GENERATOR3_BASE (DMA2_BASE + 0x0128)
+#define DMA2MUX_GENERATOR4_BASE (DMA2_BASE + 0x012C)
+
+#define EDMA_BASE (AHBPERIPH1_BASE + 0x6000)
+#define EDMA_STREAM1_BASE (EDMA_BASE + 0x0010)
+#define EDMA_STREAM2_BASE (EDMA_BASE + 0x0028)
+#define EDMA_STREAM3_BASE (EDMA_BASE + 0x0040)
+#define EDMA_STREAM4_BASE (EDMA_BASE + 0x0058)
+#define EDMA_STREAM5_BASE (EDMA_BASE + 0x0070)
+#define EDMA_STREAM6_BASE (EDMA_BASE + 0x0088)
+#define EDMA_STREAM7_BASE (EDMA_BASE + 0x00A0)
+#define EDMA_STREAM8_BASE (EDMA_BASE + 0x00B8)
+
+#define EDMA_2D_BASE (EDMA_BASE + 0x00F4)
+#define EDMA_STREAM1_2D_BASE (EDMA_2D_BASE + 0x0004)
+#define EDMA_STREAM2_2D_BASE (EDMA_2D_BASE + 0x000C)
+#define EDMA_STREAM3_2D_BASE (EDMA_2D_BASE + 0x0014)
+#define EDMA_STREAM4_2D_BASE (EDMA_2D_BASE + 0x001C)
+#define EDMA_STREAM5_2D_BASE (EDMA_2D_BASE + 0x0024)
+#define EDMA_STREAM6_2D_BASE (EDMA_2D_BASE + 0x002C)
+#define EDMA_STREAM7_2D_BASE (EDMA_2D_BASE + 0x0034)
+#define EDMA_STREAM8_2D_BASE (EDMA_2D_BASE + 0x003C)
+
+#define EDMA_LL_BASE (EDMA_BASE + 0x00D0)
+#define EDMA_STREAM1_LL_BASE (EDMA_LL_BASE + 0x0004)
+#define EDMA_STREAM2_LL_BASE (EDMA_LL_BASE + 0x0008)
+#define EDMA_STREAM3_LL_BASE (EDMA_LL_BASE + 0x000C)
+#define EDMA_STREAM4_LL_BASE (EDMA_LL_BASE + 0x0010)
+#define EDMA_STREAM5_LL_BASE (EDMA_LL_BASE + 0x0014)
+#define EDMA_STREAM6_LL_BASE (EDMA_LL_BASE + 0x0018)
+#define EDMA_STREAM7_LL_BASE (EDMA_LL_BASE + 0x001C)
+#define EDMA_STREAM8_LL_BASE (EDMA_LL_BASE + 0x0020)
+
+#define EDMAMUX_BASE (EDMA_BASE + 0x0140)
+#define EDMAMUX_CHANNEL1_BASE (EDMAMUX_BASE)
+#define EDMAMUX_CHANNEL2_BASE (EDMAMUX_BASE + 0x0004)
+#define EDMAMUX_CHANNEL3_BASE (EDMAMUX_BASE + 0x0008)
+#define EDMAMUX_CHANNEL4_BASE (EDMAMUX_BASE + 0x000C)
+#define EDMAMUX_CHANNEL5_BASE (EDMAMUX_BASE + 0x0010)
+#define EDMAMUX_CHANNEL6_BASE (EDMAMUX_BASE + 0x0014)
+#define EDMAMUX_CHANNEL7_BASE (EDMAMUX_BASE + 0x0018)
+#define EDMAMUX_CHANNEL8_BASE (EDMAMUX_BASE + 0x001C)
+
+#define EDMAMUX_GENERATOR1_BASE (EDMA_BASE + 0x0160)
+#define EDMAMUX_GENERATOR2_BASE (EDMA_BASE + 0x0164)
+#define EDMAMUX_GENERATOR3_BASE (EDMA_BASE + 0x0168)
+#define EDMAMUX_GENERATOR4_BASE (EDMA_BASE + 0x016C)
+
+#define FLASH_REG_BASE (AHBPERIPH1_BASE + 0x3C00)
+#define CRM_BASE (AHBPERIPH1_BASE + 0x3800)
+#define CRC_BASE (AHBPERIPH1_BASE + 0x3000)
+#define SDIO2_BASE (AHBPERIPH2_BASE + 0x61000)
+#define DVP_BASE (AHBPERIPH2_BASE + 0x50000)
+#define OTGFS1_BASE (AHBPERIPH2_BASE + 0x00000)
+
+#define EMAC_MAC_BASE (EMAC_BASE)
+#define EMAC_MMC_BASE (EMAC_BASE + 0x0100)
+#define EMAC_PTP_BASE (EMAC_BASE + 0x0700)
+#define EMAC_DMA_BASE (EMAC_BASE + 0x1000)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#include "at32f435_437_def.h"
+#include "at32f435_437_conf.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_acc.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_acc.h
new file mode 100644
index 0000000..061da6e
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_acc.h
@@ -0,0 +1,205 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_acc.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 acc header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_ACC_H
+#define __AT32F435_437_ACC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup ACC
+ * @{
+ */
+
+/** @defgroup ACC_exported_constants
+ * @{
+ */
+
+#define ACC_CAL_HICKCAL ((uint16_t)0x0000) /*!< acc hick calibration */
+#define ACC_CAL_HICKTRIM ((uint16_t)0x0002) /*!< acc hick trim */
+
+#define ACC_RSLOST_FLAG ((uint16_t)0x0002) /*!< acc reference signal lost error flag */
+#define ACC_CALRDY_FLAG ((uint16_t)0x0001) /*!< acc internal high-speed clock calibration ready error flag */
+
+#define ACC_CALRDYIEN_INT ((uint16_t)0x0020) /*!< acc internal high-speed clock calibration ready interrupt enable */
+#define ACC_EIEN_INT ((uint16_t)0x0010) /*!< acc reference signal lost interrupt enable */
+
+#define ACC_SOF_OTG1 ((uint16_t)0x0000) /*!< acc sof signal select: otg1 */
+#define ACC_SOF_OTG2 ((uint16_t)0x0004) /*!< acc sof signal select: otg2 */
+
+/**
+ * @}
+ */
+
+/** @defgroup ACC_exported_types
+ * @{
+ */
+
+/**
+ * @brief type define acc register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief acc sts register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t calrdy : 1; /* [0] */
+ __IO uint32_t rslost : 1; /* [1] */
+ __IO uint32_t reserved1 : 30;/* [31:2] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief acc ctrl1 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t calon : 1; /* [0] */
+ __IO uint32_t entrim : 1; /* [1] */
+ __IO uint32_t reserved1 : 2; /* [3:2] */
+ __IO uint32_t eien : 1; /* [4] */
+ __IO uint32_t calrdyien : 1; /* [5] */
+ __IO uint32_t reserved2 : 2; /* [7:6] */
+ __IO uint32_t step : 4; /* [11:8] */
+ __IO uint32_t reserved3 : 20;/* [31:12] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief acc ctrl2 register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t hickcal : 8; /* [7:0] */
+ __IO uint32_t hicktrim : 6; /* [13:8] */
+ __IO uint32_t reserved1 : 18;/* [31:14] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief acc acc_c1 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t c1;
+ struct
+ {
+ __IO uint32_t c1 : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } c1_bit;
+ };
+
+ /**
+ * @brief acc acc_c2 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t c2;
+ struct
+ {
+ __IO uint32_t c2 : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } c2_bit;
+ };
+
+ /**
+ * @brief acc acc_c3 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t c3;
+ struct
+ {
+ __IO uint32_t c3 : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } c3_bit;
+ };
+} acc_type;
+
+/**
+ * @}
+ */
+
+#define ACC ((acc_type *) ACC_BASE)
+
+/** @defgroup ACC_exported_functions
+ * @{
+ */
+
+void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state);
+void acc_step_set(uint8_t step_value);
+void acc_sof_select(uint16_t sof_sel);
+void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state);
+uint8_t acc_hicktrim_get(void);
+uint8_t acc_hickcal_get(void);
+void acc_write_c1(uint16_t acc_c1_value);
+void acc_write_c2(uint16_t acc_c2_value);
+void acc_write_c3(uint16_t acc_c3_value);
+uint16_t acc_read_c1(void);
+uint16_t acc_read_c2(void);
+uint16_t acc_read_c3(void);
+flag_status acc_flag_get(uint16_t acc_flag);
+void acc_flag_clear(uint16_t acc_flag);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_adc.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_adc.h
new file mode 100644
index 0000000..53510b9
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_adc.h
@@ -0,0 +1,938 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_adc.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 adc header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_ADC_H
+#define __AT32F435_437_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/** @defgroup ADC_interrupts_definition
+ * @brief adc interrupt
+ * @{
+ */
+
+#define ADC_OCCE_INT ((uint32_t)0x00000020) /*!< ordinary channels conversion end interrupt */
+#define ADC_VMOR_INT ((uint32_t)0x00000040) /*!< voltage monitoring out of range interrupt */
+#define ADC_PCCE_INT ((uint32_t)0x00000080) /*!< preempt channels conversion end interrupt */
+#define ADC_OCCO_INT ((uint32_t)0x04000000) /*!< ordinary channel conversion overflow interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition
+ * @brief adc flag
+ * @{
+ */
+
+#define ADC_VMOR_FLAG ((uint8_t)0x01) /*!< voltage monitoring out of range flag */
+#define ADC_OCCE_FLAG ((uint8_t)0x02) /*!< ordinary channels conversion end flag */
+#define ADC_PCCE_FLAG ((uint8_t)0x04) /*!< preempt channels conversion end flag */
+#define ADC_PCCS_FLAG ((uint8_t)0x08) /*!< preempt channel conversion start flag */
+#define ADC_OCCS_FLAG ((uint8_t)0x10) /*!< ordinary channel conversion start flag */
+#define ADC_OCCO_FLAG ((uint8_t)0x20) /*!< ordinary channel conversion overflow flag */
+#define ADC_RDY_FLAG ((uint8_t)0x40) /*!< adc ready to conversion flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_exported_types
+ * @{
+ */
+
+/**
+ * @brief adc division type
+ */
+typedef enum
+{
+ ADC_HCLK_DIV_2 = 0x00, /*!< adcclk is hclk/2 */
+ ADC_HCLK_DIV_3 = 0x01, /*!< adcclk is hclk/3 */
+ ADC_HCLK_DIV_4 = 0x02, /*!< adcclk is hclk/4 */
+ ADC_HCLK_DIV_5 = 0x03, /*!< adcclk is hclk/5 */
+ ADC_HCLK_DIV_6 = 0x04, /*!< adcclk is hclk/6 */
+ ADC_HCLK_DIV_7 = 0x05, /*!< adcclk is hclk/7 */
+ ADC_HCLK_DIV_8 = 0x06, /*!< adcclk is hclk/8 */
+ ADC_HCLK_DIV_9 = 0x07, /*!< adcclk is hclk/9 */
+ ADC_HCLK_DIV_10 = 0x08, /*!< adcclk is hclk/10 */
+ ADC_HCLK_DIV_11 = 0x09, /*!< adcclk is hclk/11 */
+ ADC_HCLK_DIV_12 = 0x0A, /*!< adcclk is hclk/12 */
+ ADC_HCLK_DIV_13 = 0x0B, /*!< adcclk is hclk/13 */
+ ADC_HCLK_DIV_14 = 0x0C, /*!< adcclk is hclk/14 */
+ ADC_HCLK_DIV_15 = 0x0D, /*!< adcclk is hclk/15 */
+ ADC_HCLK_DIV_16 = 0x0E, /*!< adcclk is hclk/16 */
+ ADC_HCLK_DIV_17 = 0x0F /*!< adcclk is hclk/17 */
+} adc_div_type;
+
+/**
+ * @brief adc combine mode type
+ */
+typedef enum
+{
+ ADC_INDEPENDENT_MODE = 0x00, /*!< independent mode */
+ ADC_ORDINARY_SMLT_PREEMPT_SMLT_ONESLAVE_MODE = 0x01, /*!< single slaver combined ordinary simultaneous + preempt simultaneous mode */
+ ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_ONESLAVE_MODE = 0x02, /*!< single slaver combined ordinary simultaneous + preempt interleaved trigger mode */
+ ADC_PREEMPT_SMLT_ONLY_ONESLAVE_MODE = 0x05, /*!< single slaver preempt simultaneous mode only */
+ ADC_ORDINARY_SMLT_ONLY_ONESLAVE_MODE = 0x06, /*!< single slaver ordinary simultaneous mode only */
+ ADC_ORDINARY_SHIFT_ONLY_ONESLAVE_MODE = 0x07, /*!< single slaver ordinary shifting mode only */
+ ADC_PREEMPT_INTERLTRIG_ONLY_ONESLAVE_MODE = 0x09, /*!< single slaver preempt interleaved trigger mode only */
+ ADC_ORDINARY_SMLT_PREEMPT_SMLT_TWOSLAVE_MODE = 0x11, /*!< double slaver combined ordinary simultaneous + preempt simultaneous mode */
+ ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_TWOSLAVE_MODE = 0x12, /*!< double slaver combined ordinary simultaneous + preempt interleaved trigger mode */
+ ADC_PREEMPT_SMLT_ONLY_TWOSLAVE_MODE = 0x15, /*!< double slaver preempt simultaneous mode only */
+ ADC_ORDINARY_SMLT_ONLY_TWOSLAVE_MODE = 0x16, /*!< double slaver ordinary simultaneous mode only */
+ ADC_ORDINARY_SHIFT_ONLY_TWOSLAVE_MODE = 0x17, /*!< double slaver ordinary shifting mode only */
+ ADC_PREEMPT_INTERLTRIG_ONLY_TWOSLAVE_MODE = 0x19 /*!< double slaver preempt interleaved trigger mode only */
+} adc_combine_mode_type;
+
+/**
+ * @brief adc common dma mode type
+ */
+typedef enum
+{
+ ADC_COMMON_DMAMODE_DISABLE = 0x00, /*!< dma mode disabled */
+ ADC_COMMON_DMAMODE_1 = 0x01, /*!< dma mode1: each dma request trans a half-word data(reference manual account the rule of data package) */
+ ADC_COMMON_DMAMODE_2 = 0x02, /*!< dma mode2: each dma request trans two half-word data(reference manual account the rule of data package) */
+ ADC_COMMON_DMAMODE_3 = 0x03, /*!< dma mode3: each dma request trans two bytes data(reference manual account the rule of data package) */
+ ADC_COMMON_DMAMODE_4 = 0x04, /*!< dma mode4: each dma request trans three bytes data(reference manual account the rule of data package) */
+ ADC_COMMON_DMAMODE_5 = 0x05 /*!< dma mode5: odd dma request trans two half-word data,even dma request trans a half-word data(reference manual account the rule of data package) */
+} adc_common_dma_mode_type;
+
+/**
+ * @brief adc common sampling interval type
+ */
+typedef enum
+{
+ ADC_SAMPLING_INTERVAL_5CYCLES = 0x00, /*!< ordinary shifting mode adjacent adc sampling interval 5 adcclk */
+ ADC_SAMPLING_INTERVAL_6CYCLES = 0x01, /*!< ordinary shifting mode adjacent adc sampling interval 6 adcclk */
+ ADC_SAMPLING_INTERVAL_7CYCLES = 0x02, /*!< ordinary shifting mode adjacent adc sampling interval 7 adcclk */
+ ADC_SAMPLING_INTERVAL_8CYCLES = 0x03, /*!< ordinary shifting mode adjacent adc sampling interval 8 adcclk */
+ ADC_SAMPLING_INTERVAL_9CYCLES = 0x04, /*!< ordinary shifting mode adjacent adc sampling interval 9 adcclk */
+ ADC_SAMPLING_INTERVAL_10CYCLES = 0x05, /*!< ordinary shifting mode adjacent adc sampling interval 10 adcclk */
+ ADC_SAMPLING_INTERVAL_11CYCLES = 0x06, /*!< ordinary shifting mode adjacent adc sampling interval 11 adcclk */
+ ADC_SAMPLING_INTERVAL_12CYCLES = 0x07, /*!< ordinary shifting mode adjacent adc sampling interval 12 adcclk */
+ ADC_SAMPLING_INTERVAL_13CYCLES = 0x08, /*!< ordinary shifting mode adjacent adc sampling interval 13 adcclk */
+ ADC_SAMPLING_INTERVAL_14CYCLES = 0x09, /*!< ordinary shifting mode adjacent adc sampling interval 14 adcclk */
+ ADC_SAMPLING_INTERVAL_15CYCLES = 0x0A, /*!< ordinary shifting mode adjacent adc sampling interval 15 adcclk */
+ ADC_SAMPLING_INTERVAL_16CYCLES = 0x0B, /*!< ordinary shifting mode adjacent adc sampling interval 16 adcclk */
+ ADC_SAMPLING_INTERVAL_17CYCLES = 0x0C, /*!< ordinary shifting mode adjacent adc sampling interval 17 adcclk */
+ ADC_SAMPLING_INTERVAL_18CYCLES = 0x0D, /*!< ordinary shifting mode adjacent adc sampling interval 18 adcclk */
+ ADC_SAMPLING_INTERVAL_19CYCLES = 0x0E, /*!< ordinary shifting mode adjacent adc sampling interval 19 adcclk */
+ ADC_SAMPLING_INTERVAL_20CYCLES = 0x0F /*!< ordinary shifting mode adjacent adc sampling interval 20 adcclk */
+} adc_sampling_interval_type;
+
+/**
+ * @brief adc conversion resolution type
+ */
+typedef enum
+{
+ ADC_RESOLUTION_12B = 0x00, /*!< conversion resolution 12 bit */
+ ADC_RESOLUTION_10B = 0x01, /*!< conversion resolution 10 bit */
+ ADC_RESOLUTION_8B = 0x02, /*!< conversion resolution 8 bit */
+ ADC_RESOLUTION_6B = 0x03 /*!< conversion resolution 6 bit */
+} adc_resolution_type;
+
+/**
+ * @brief adc data align type
+ */
+typedef enum
+{
+ ADC_RIGHT_ALIGNMENT = 0x00, /*!< data right alignment */
+ ADC_LEFT_ALIGNMENT = 0x01 /*!< data left alignment */
+} adc_data_align_type;
+
+/**
+ * @brief adc channel select type
+ */
+typedef enum
+{
+ ADC_CHANNEL_0 = 0x00, /*!< adc channel 0 */
+ ADC_CHANNEL_1 = 0x01, /*!< adc channel 1 */
+ ADC_CHANNEL_2 = 0x02, /*!< adc channel 2 */
+ ADC_CHANNEL_3 = 0x03, /*!< adc channel 3 */
+ ADC_CHANNEL_4 = 0x04, /*!< adc channel 4 */
+ ADC_CHANNEL_5 = 0x05, /*!< adc channel 5 */
+ ADC_CHANNEL_6 = 0x06, /*!< adc channel 6 */
+ ADC_CHANNEL_7 = 0x07, /*!< adc channel 7 */
+ ADC_CHANNEL_8 = 0x08, /*!< adc channel 8 */
+ ADC_CHANNEL_9 = 0x09, /*!< adc channel 9 */
+ ADC_CHANNEL_10 = 0x0A, /*!< adc channel 10 */
+ ADC_CHANNEL_11 = 0x0B, /*!< adc channel 11 */
+ ADC_CHANNEL_12 = 0x0C, /*!< adc channel 12 */
+ ADC_CHANNEL_13 = 0x0D, /*!< adc channel 13 */
+ ADC_CHANNEL_14 = 0x0E, /*!< adc channel 14 */
+ ADC_CHANNEL_15 = 0x0F, /*!< adc channel 15 */
+ ADC_CHANNEL_16 = 0x10, /*!< adc channel 16 */
+ ADC_CHANNEL_17 = 0x11, /*!< adc channel 17 */
+ ADC_CHANNEL_18 = 0x12 /*!< adc channel 18 */
+} adc_channel_select_type;
+
+/**
+ * @brief adc sampletime select type
+ */
+typedef enum
+{
+ ADC_SAMPLETIME_2_5 = 0x00, /*!< adc sample time 2.5 cycle */
+ ADC_SAMPLETIME_6_5 = 0x01, /*!< adc sample time 6.5 cycle */
+ ADC_SAMPLETIME_12_5 = 0x02, /*!< adc sample time 12.5 cycle */
+ ADC_SAMPLETIME_24_5 = 0x03, /*!< adc sample time 24.5 cycle */
+ ADC_SAMPLETIME_47_5 = 0x04, /*!< adc sample time 47.5 cycle */
+ ADC_SAMPLETIME_92_5 = 0x05, /*!< adc sample time 92.5 cycle */
+ ADC_SAMPLETIME_247_5 = 0x06, /*!< adc sample time 247.5 cycle */
+ ADC_SAMPLETIME_640_5 = 0x07 /*!< adc sample time 640.5 cycle */
+} adc_sampletime_select_type;
+
+/**
+ * @brief adc ordinary group trigger event select type
+ */
+typedef enum
+{
+ ADC_ORDINARY_TRIG_TMR1CH1 = 0x00, /*!< timer1 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR1CH2 = 0x01, /*!< timer1 ch2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR1CH3 = 0x02, /*!< timer1 ch3 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR2CH2 = 0x03, /*!< timer2 ch2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR2CH3 = 0x04, /*!< timer2 ch3 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR2CH4 = 0x05, /*!< timer2 ch4 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR2TRGOUT = 0x06, /*!< timer2 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR3CH1 = 0x07, /*!< timer3 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR3TRGOUT = 0x08, /*!< timer3 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR4CH4 = 0x09, /*!< timer4 ch4 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR5CH1 = 0x0A, /*!< timer5 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR5CH2 = 0x0B, /*!< timer5 ch2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR5CH3 = 0x0C, /*!< timer5 ch3 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR8CH1 = 0x0D, /*!< timer8 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR8TRGOUT = 0x0E, /*!< timer8 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_EXINT11 = 0x0F, /*!< exint line11 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR20TRGOUT = 0x10, /*!< timer20 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR20TRGOUT2 = 0x11, /*!< timer20 trgout2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR20CH1 = 0x12, /*!< timer20 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR20CH2 = 0x13, /*!< timer20 ch2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR20CH3 = 0x14, /*!< timer20 ch3 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR8TRGOUT2 = 0x15, /*!< timer8 trgout2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR1TRGOUT2 = 0x16, /*!< timer1 trgout2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR4TRGOUT = 0x17, /*!< timer4 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR6TRGOUT = 0x18, /*!< timer6 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR3CH4 = 0x19, /*!< timer3 ch4 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR4CH1 = 0x1A, /*!< timer4 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR1TRGOUT = 0x1B, /*!< timer1 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR2CH1 = 0x1C, /*!< timer2 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR7TRGOUT = 0x1E /*!< timer7 trgout event as trigger source of ordinary sequence */
+} adc_ordinary_trig_select_type;
+
+/**
+ * @brief adc ordinary channel conversion's external_trigger_edge type
+ */
+typedef enum
+{
+ ADC_ORDINARY_TRIG_EDGE_NONE = 0x00, /*!< ordinary channels trigger detection disabled */
+ ADC_ORDINARY_TRIG_EDGE_RISING = 0x01, /*!< ordinary channels trigger detection on the rising edge */
+ ADC_ORDINARY_TRIG_EDGE_FALLING = 0x02, /*!< ordinary channels trigger detection on the falling edge */
+ ADC_ORDINARY_TRIG_EDGE_RISING_FALLING = 0x03 /*!< ordinary channels trigger detection on both the rising and falling edges */
+} adc_ordinary_trig_edge_type;
+
+/**
+ * @brief adc preempt group external trigger event select type
+ */
+typedef enum
+{
+ ADC_PREEMPT_TRIG_TMR1CH4 = 0x00, /*!< timer1 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR1TRGOUT = 0x01, /*!< timer1 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR2CH1 = 0x02, /*!< timer2 ch1 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR2TRGOUT = 0x03, /*!< timer2 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR3CH2 = 0x04, /*!< timer3 ch2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR3CH4 = 0x05, /*!< timer3 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR4CH1 = 0x06, /*!< timer4 ch1 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR4CH2 = 0x07, /*!< timer4 ch2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR4CH3 = 0x08, /*!< timer4 ch3 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR4TRGOUT = 0x09, /*!< timer4 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR5CH4 = 0x0A, /*!< timer5 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR5TRGOUT = 0x0B, /*!< timer5 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR8CH2 = 0x0C, /*!< timer8 ch2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR8CH3 = 0x0D, /*!< timer8 ch3 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR8CH4 = 0x0E, /*!< timer8 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_EXINT15 = 0x0F, /*!< exint line15 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR20TRGOUT = 0x10, /*!< timer20 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR20TRGOUT2 = 0x11, /*!< timer20 trgout2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR20CH4 = 0x12, /*!< timer20 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR1TRGOUT2 = 0x13, /*!< timer1 trgout2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR8TRGOUT = 0x14, /*!< timer8 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR8TRGOUT2 = 0x15, /*!< timer8 trgout2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR3CH3 = 0x16, /*!< timer3 ch3 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR3TRGOUT = 0x17, /*!< timer3 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR3CH1 = 0x18, /*!< timer3 ch1 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR6TRGOUT = 0x19, /*!< timer6 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR4CH4 = 0x1A, /*!< timer4 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR1CH3 = 0x1B, /*!< timer1 ch3 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR20CH2 = 0x1C, /*!< timer20 ch2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR7TRGOUT = 0x1E /*!< timer7 trgout event as trigger source of preempt sequence */
+} adc_preempt_trig_select_type;
+
+/**
+ * @brief adc preempt channel conversion's external_trigger_edge type
+ */
+typedef enum
+{
+ ADC_PREEMPT_TRIG_EDGE_NONE = 0x00, /*!< preempt channels trigger detection disabled */
+ ADC_PREEMPT_TRIG_EDGE_RISING = 0x01, /*!< preempt channels trigger detection on the rising edge */
+ ADC_PREEMPT_TRIG_EDGE_FALLING = 0x02, /*!< preempt channels trigger detection on the falling edge */
+ ADC_PREEMPT_TRIG_EDGE_RISING_FALLING = 0x03 /*!< preempt channels trigger detection on both the rising and falling edges */
+} adc_preempt_trig_edge_type;
+
+/**
+ * @brief adc preempt channel type
+ */
+typedef enum
+{
+ ADC_PREEMPT_CHANNEL_1 = 0x00, /*!< adc preempt channel 1 */
+ ADC_PREEMPT_CHANNEL_2 = 0x01, /*!< adc preempt channel 2 */
+ ADC_PREEMPT_CHANNEL_3 = 0x02, /*!< adc preempt channel 3 */
+ ADC_PREEMPT_CHANNEL_4 = 0x03 /*!< adc preempt channel 4 */
+} adc_preempt_channel_type;
+
+/**
+ * @brief adc voltage_monitoring type
+ */
+typedef enum
+{
+ ADC_VMONITOR_SINGLE_ORDINARY = 0x00800200, /*!< voltage_monitoring on a single ordinary channel */
+ ADC_VMONITOR_SINGLE_PREEMPT = 0x00400200, /*!< voltage_monitoring on a single preempt channel */
+ ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT = 0x00C00200, /*!< voltage_monitoring on a single ordinary or preempt channel */
+ ADC_VMONITOR_ALL_ORDINARY = 0x00800000, /*!< voltage_monitoring on all ordinary channel */
+ ADC_VMONITOR_ALL_PREEMPT = 0x00400000, /*!< voltage_monitoring on all preempt channel */
+ ADC_VMONITOR_ALL_ORDINARY_PREEMPT = 0x00C00000, /*!< voltage_monitoring on all ordinary and preempt channel */
+ ADC_VMONITOR_NONE = 0x00000000 /*!< no channel guarded by the voltage_monitoring */
+} adc_voltage_monitoring_type;
+
+/**
+ * @brief adc oversample ratio type
+ */
+typedef enum
+{
+ ADC_OVERSAMPLE_RATIO_2 = 0x00, /*!< adc oversample ratio 2 */
+ ADC_OVERSAMPLE_RATIO_4 = 0x01, /*!< adc oversample ratio 4 */
+ ADC_OVERSAMPLE_RATIO_8 = 0x02, /*!< adc oversample ratio 8 */
+ ADC_OVERSAMPLE_RATIO_16 = 0x03, /*!< adc oversample ratio 16 */
+ ADC_OVERSAMPLE_RATIO_32 = 0x04, /*!< adc oversample ratio 32 */
+ ADC_OVERSAMPLE_RATIO_64 = 0x05, /*!< adc oversample ratio 64 */
+ ADC_OVERSAMPLE_RATIO_128 = 0x06, /*!< adc oversample ratio 128 */
+ ADC_OVERSAMPLE_RATIO_256 = 0x07 /*!< adc oversample ratio 256 */
+} adc_oversample_ratio_type;
+
+/**
+ * @brief adc oversample shift type
+ */
+typedef enum
+{
+ ADC_OVERSAMPLE_SHIFT_0 = 0x00, /*!< adc oversample shift 0 */
+ ADC_OVERSAMPLE_SHIFT_1 = 0x01, /*!< adc oversample shift 1 */
+ ADC_OVERSAMPLE_SHIFT_2 = 0x02, /*!< adc oversample shift 2 */
+ ADC_OVERSAMPLE_SHIFT_3 = 0x03, /*!< adc oversample shift 3 */
+ ADC_OVERSAMPLE_SHIFT_4 = 0x04, /*!< adc oversample shift 4 */
+ ADC_OVERSAMPLE_SHIFT_5 = 0x05, /*!< adc oversample shift 5 */
+ ADC_OVERSAMPLE_SHIFT_6 = 0x06, /*!< adc oversample shift 6 */
+ ADC_OVERSAMPLE_SHIFT_7 = 0x07, /*!< adc oversample shift 7 */
+ ADC_OVERSAMPLE_SHIFT_8 = 0x08 /*!< adc oversample shift 8 */
+} adc_oversample_shift_type;
+
+/**
+ * @brief adc ordinary oversample recover type
+ */
+typedef enum
+{
+ ADC_OVERSAMPLE_CONTINUE = 0x00, /*!< continue mode:when preempt triggered,oversampling is temporary stopped and continued after preempt sequence */
+ ADC_OVERSAMPLE_RESTART = 0x01 /*!< restart mode:when preempt triggered,oversampling is aborted and resumed from start after preempt sequence */
+} adc_ordinary_oversample_restart_type;
+
+/**
+ * @brief adc common config type
+ */
+typedef struct
+{
+ adc_combine_mode_type combine_mode; /*!< adc combine mode select */
+ adc_div_type div; /*!< adc division select */
+ adc_common_dma_mode_type common_dma_mode; /*!< adc common dma mode select */
+ confirm_state common_dma_request_repeat_state; /*!< adc common dma repeat state */
+ adc_sampling_interval_type sampling_interval; /*!< ordinary shifting mode adjacent adc sampling interval select */
+ confirm_state tempervintrv_state; /*!< adc temperature sensor and vintrv state */
+ confirm_state vbat_state; /*!< adc voltage battery state */
+} adc_common_config_type;
+
+/**
+ * @brief adc base config type
+ */
+typedef struct
+{
+ confirm_state sequence_mode; /*!< adc sequence mode */
+ confirm_state repeat_mode; /*!< adc repeat mode */
+ adc_data_align_type data_align; /*!< adc data alignment */
+ uint8_t ordinary_channel_length; /*!< adc ordinary channel sequence length*/
+} adc_base_config_type;
+
+/**
+ * @brief type define adc register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief adc sts register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t vmor : 1; /* [0] */
+ __IO uint32_t occe : 1; /* [1] */
+ __IO uint32_t pcce : 1; /* [2] */
+ __IO uint32_t pccs : 1; /* [3] */
+ __IO uint32_t occs : 1; /* [4] */
+ __IO uint32_t occo : 1; /* [5] */
+ __IO uint32_t rdy : 1; /* [6] */
+ __IO uint32_t reserved1 : 25;/* [31:7] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief adc ctrl1 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t vmcsel : 5; /* [4:0] */
+ __IO uint32_t occeien : 1; /* [5] */
+ __IO uint32_t vmorien : 1; /* [6] */
+ __IO uint32_t pcceien : 1; /* [7] */
+ __IO uint32_t sqen : 1; /* [8] */
+ __IO uint32_t vmsgen : 1; /* [9] */
+ __IO uint32_t pcautoen : 1; /* [10] */
+ __IO uint32_t ocpen : 1; /* [11] */
+ __IO uint32_t pcpen : 1; /* [12] */
+ __IO uint32_t ocpcnt : 3; /* [15:13] */
+ __IO uint32_t reserved1 : 6; /* [21:16] */
+ __IO uint32_t pcvmen : 1; /* [22] */
+ __IO uint32_t ocvmen : 1; /* [23] */
+ __IO uint32_t crsel : 2; /* [25:24] */
+ __IO uint32_t occoien : 1; /* [26] */
+ __IO uint32_t reserved2 : 5; /* [31:27] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief adc ctrl2 register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t adcen : 1; /* [0] */
+ __IO uint32_t rpen : 1; /* [1] */
+ __IO uint32_t adcal : 1; /* [2] */
+ __IO uint32_t adcalinit : 1; /* [3] */
+ __IO uint32_t adabrt : 1; /* [4] */
+ __IO uint32_t reserved1 : 3; /* [7:5] */
+ __IO uint32_t ocdmaen : 1; /* [8] */
+ __IO uint32_t ocdrcen : 1; /* [9] */
+ __IO uint32_t eocsfen : 1; /* [10] */
+ __IO uint32_t dtalign : 1; /* [11] */
+ __IO uint32_t reserved2 : 4; /* [15:12] */
+ __IO uint32_t pctesel_l : 4; /* [19:16] */
+ __IO uint32_t pcete : 2; /* [21:20] */
+ __IO uint32_t pcswtrg : 1; /* [22] */
+ __IO uint32_t pctesel_h : 1; /* [23] */
+ __IO uint32_t octesel_l : 4; /* [27:24] */
+ __IO uint32_t ocete : 2; /* [29:28] */
+ __IO uint32_t ocswtrg : 1; /* [30] */
+ __IO uint32_t octesel_h : 1; /* [31] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief adc spt1 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t spt1;
+ struct
+ {
+ __IO uint32_t cspt10 : 3; /* [2:0] */
+ __IO uint32_t cspt11 : 3; /* [5:3] */
+ __IO uint32_t cspt12 : 3; /* [8:6] */
+ __IO uint32_t cspt13 : 3; /* [11:9] */
+ __IO uint32_t cspt14 : 3; /* [14:12] */
+ __IO uint32_t cspt15 : 3; /* [17:15] */
+ __IO uint32_t cspt16 : 3; /* [20:18] */
+ __IO uint32_t cspt17 : 3; /* [23:21] */
+ __IO uint32_t cspt18 : 3; /* [26:24] */
+ __IO uint32_t reserved1 : 5;/* [31:27] */
+ } spt1_bit;
+ };
+
+ /**
+ * @brief adc spt2 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t spt2;
+ struct
+ {
+ __IO uint32_t cspt0 : 3;/* [2:0] */
+ __IO uint32_t cspt1 : 3;/* [5:3] */
+ __IO uint32_t cspt2 : 3;/* [8:6] */
+ __IO uint32_t cspt3 : 3;/* [11:9] */
+ __IO uint32_t cspt4 : 3;/* [14:12] */
+ __IO uint32_t cspt5 : 3;/* [17:15] */
+ __IO uint32_t cspt6 : 3;/* [20:18] */
+ __IO uint32_t cspt7 : 3;/* [23:21] */
+ __IO uint32_t cspt8 : 3;/* [26:24] */
+ __IO uint32_t cspt9 : 3;/* [29:27] */
+ __IO uint32_t reserved1 : 2;/* [31:30] */
+ } spt2_bit;
+ };
+
+ /**
+ * @brief adc pcdto1 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t pcdto1;
+ struct
+ {
+ __IO uint32_t pcdto1 : 12; /* [11:0] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } pcdto1_bit;
+ };
+
+ /**
+ * @brief adc pcdto2 register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t pcdto2;
+ struct
+ {
+ __IO uint32_t pcdto2 : 12; /* [11:0] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } pcdto2_bit;
+ };
+
+ /**
+ * @brief adc pcdto3 register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t pcdto3;
+ struct
+ {
+ __IO uint32_t pcdto3 : 12; /* [11:0] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } pcdto3_bit;
+ };
+
+ /**
+ * @brief adc pcdto4 register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t pcdto4;
+ struct
+ {
+ __IO uint32_t pcdto4 : 12; /* [11:0] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } pcdto4_bit;
+ };
+
+ /**
+ * @brief adc vmhb register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t vmhb;
+ struct
+ {
+ __IO uint32_t vmhb : 12; /* [11:0] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } vmhb_bit;
+ };
+
+ /**
+ * @brief adc vmlb register, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t vmlb;
+ struct
+ {
+ __IO uint32_t vmlb : 12; /* [11:0] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } vmlb_bit;
+ };
+
+ /**
+ * @brief adc osq1 register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t osq1;
+ struct
+ {
+ __IO uint32_t osn13 : 5; /* [4:0] */
+ __IO uint32_t osn14 : 5; /* [9:5] */
+ __IO uint32_t osn15 : 5; /* [14:10] */
+ __IO uint32_t osn16 : 5; /* [19:15] */
+ __IO uint32_t oclen : 4; /* [23:20] */
+ __IO uint32_t reserved1 : 8; /* [31:24] */
+ } osq1_bit;
+ };
+
+ /**
+ * @brief adc osq2 register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t osq2;
+ struct
+ {
+ __IO uint32_t osn7 : 5; /* [4:0] */
+ __IO uint32_t osn8 : 5; /* [9:5] */
+ __IO uint32_t osn9 : 5; /* [14:10] */
+ __IO uint32_t osn10 : 5; /* [19:15] */
+ __IO uint32_t osn11 : 5; /* [24:20] */
+ __IO uint32_t osn12 : 5; /* [29:25] */
+ __IO uint32_t reserved1 : 2; /* [31:30] */
+ } osq2_bit;
+ };
+
+ /**
+ * @brief adc osq3 register, offset:0x34
+ */
+ union
+ {
+ __IO uint32_t osq3;
+ struct
+ {
+ __IO uint32_t osn1 : 5; /* [4:0] */
+ __IO uint32_t osn2 : 5; /* [9:5] */
+ __IO uint32_t osn3 : 5; /* [14:10] */
+ __IO uint32_t osn4 : 5; /* [19:15] */
+ __IO uint32_t osn5 : 5; /* [24:20] */
+ __IO uint32_t osn6 : 5; /* [29:25] */
+ __IO uint32_t reserved1 : 2; /* [31:30] */
+ } osq3_bit;
+ };
+
+ /**
+ * @brief adc psq register, offset:0x38
+ */
+ union
+ {
+ __IO uint32_t psq;
+ struct
+ {
+ __IO uint32_t psn1 : 5; /* [4:0] */
+ __IO uint32_t psn2 : 5; /* [9:5] */
+ __IO uint32_t psn3 : 5; /* [14:10] */
+ __IO uint32_t psn4 : 5; /* [19:15] */
+ __IO uint32_t pclen : 2; /* [21:20] */
+ __IO uint32_t reserved1 : 10;/* [31:22] */
+ } psq_bit;
+ };
+
+ /**
+ * @brief adc pdt1 register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t pdt1;
+ struct
+ {
+ __IO uint32_t pdt1 : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } pdt1_bit;
+ };
+
+ /**
+ * @brief adc pdt2 register, offset:0x40
+ */
+ union
+ {
+ __IO uint32_t pdt2;
+ struct
+ {
+ __IO uint32_t pdt2 : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } pdt2_bit;
+ };
+
+ /**
+ * @brief adc pdt3 register, offset:0x44
+ */
+ union
+ {
+ __IO uint32_t pdt3;
+ struct
+ {
+ __IO uint32_t pdt3 : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } pdt3_bit;
+ };
+
+ /**
+ * @brief adc pdt4 register, offset:0x48
+ */
+ union
+ {
+ __IO uint32_t pdt4;
+ struct
+ {
+ __IO uint32_t pdt4 : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } pdt4_bit;
+ };
+
+ /**
+ * @brief adc odt register, offset:0x4C
+ */
+ union
+ {
+ __IO uint32_t odt;
+ struct
+ {
+ __IO uint32_t odt : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } odt_bit;
+ };
+
+ __IO uint32_t reserved1[12];
+
+ /**
+ * @brief adc ovsp register, offset:0x80
+ */
+ union
+ {
+ __IO uint32_t ovsp;
+ struct
+ {
+ __IO uint32_t oosen : 1; /* [0] */
+ __IO uint32_t posen : 1; /* [1] */
+ __IO uint32_t osrsel : 3; /* [4:2] */
+ __IO uint32_t osssel : 4; /* [8:5] */
+ __IO uint32_t oostren : 1; /* [9] */
+ __IO uint32_t oosrsel : 1; /* [10] */
+ __IO uint32_t reserved1 : 21; /* [31:11] */
+ } ovsp_bit;
+ };
+
+ __IO uint32_t reserved2[12];
+
+ /**
+ * @brief adc calval register, offset:0xB4
+ */
+ union
+ {
+ __IO uint32_t calval;
+ struct
+ {
+ __IO uint32_t calval : 7; /* [6:0] */
+ __IO uint32_t reserved1 : 25; /* [31:7] */
+ } calval_bit;
+ };
+} adc_type;
+
+/**
+ * @brief type define adc register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief adc csts register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t csts;
+ struct
+ {
+ __IO uint32_t vmor1 : 1; /* [0] */
+ __IO uint32_t occe1 : 1; /* [1] */
+ __IO uint32_t pcce1 : 1; /* [2] */
+ __IO uint32_t pccs1 : 1; /* [3] */
+ __IO uint32_t occs1 : 1; /* [4] */
+ __IO uint32_t occo1 : 1; /* [5] */
+ __IO uint32_t rdy1 : 1; /* [6] */
+ __IO uint32_t reserved1 : 1; /* [7] */
+ __IO uint32_t vmor2 : 1; /* [8] */
+ __IO uint32_t occe2 : 1; /* [9] */
+ __IO uint32_t pcce2 : 1; /* [10] */
+ __IO uint32_t pccs2 : 1; /* [11] */
+ __IO uint32_t occs2 : 1; /* [12] */
+ __IO uint32_t occo2 : 1; /* [13] */
+ __IO uint32_t rdy2 : 1; /* [14] */
+ __IO uint32_t reserved2 : 1; /* [15] */
+ __IO uint32_t vmor3 : 1; /* [16] */
+ __IO uint32_t occe3 : 1; /* [17] */
+ __IO uint32_t pcce3 : 1; /* [18] */
+ __IO uint32_t pccs3 : 1; /* [19] */
+ __IO uint32_t occs3 : 1; /* [20] */
+ __IO uint32_t occo3 : 1; /* [21] */
+ __IO uint32_t rdy3 : 1; /* [22] */
+ __IO uint32_t reserved3 : 9; /* [31:23] */
+ } csts_bit;
+ };
+
+ /**
+ * @brief adc cctrl register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t cctrl;
+ struct
+ {
+ __IO uint32_t mssel : 5; /* [4_0] */
+ __IO uint32_t reserved1 : 3; /* [7:5] */
+ __IO uint32_t asisel : 4; /* [11:8] */
+ __IO uint32_t reserved2 : 1; /* [12] */
+ __IO uint32_t msdrcen : 1; /* [13] */
+ __IO uint32_t msdmasel_l : 2; /* [15:14] */
+ __IO uint32_t adcdiv : 4; /* [19:16] */
+ __IO uint32_t reserved3 : 2; /* [21:20] */
+ __IO uint32_t vbaten : 1; /* [22] */
+ __IO uint32_t itsrven : 1; /* [23] */
+ __IO uint32_t reserved4 : 4; /* [27:24] */
+ __IO uint32_t msdmasel_h : 1; /* [28] */
+ __IO uint32_t reserved5 : 3; /* [31:29] */
+ } cctrl_bit;
+ };
+
+ /**
+ * @brief adc codt register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t codt;
+ struct
+ {
+ __IO uint32_t codtl : 16; /* [15:0] */
+ __IO uint32_t codth : 16; /* [31:16] */
+ } codt_bit;
+ };
+} adccom_type;
+
+/**
+ * @}
+ */
+
+#define ADC1 ((adc_type *) ADC1_BASE)
+#define ADC2 ((adc_type *) ADC2_BASE)
+#define ADC3 ((adc_type *) ADC3_BASE)
+#define ADCCOM ((adccom_type *) ADCCOM_BASE)
+
+/** @defgroup ADC_exported_functions
+ * @{
+ */
+
+void adc_reset(void);
+void adc_enable(adc_type *adc_x, confirm_state new_state);
+void adc_base_default_para_init(adc_base_config_type *adc_base_struct);
+void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct);
+void adc_common_default_para_init(adc_common_config_type *adc_common_struct);
+void adc_common_config(adc_common_config_type *adc_common_struct);
+void adc_resolution_set(adc_type *adc_x, adc_resolution_type resolution);
+void adc_voltage_battery_enable(confirm_state new_state);
+void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state);
+void adc_dma_request_repeat_enable(adc_type *adc_x, confirm_state new_state);
+void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state);
+void adc_calibration_value_set(adc_type *adc_x, uint8_t adc_calibration_value);
+void adc_calibration_init(adc_type *adc_x);
+flag_status adc_calibration_init_status_get(adc_type *adc_x);
+void adc_calibration_start(adc_type *adc_x);
+flag_status adc_calibration_status_get(adc_type *adc_x);
+void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring);
+void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold);
+void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel);
+void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
+void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght);
+void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
+void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, adc_ordinary_trig_edge_type adc_ordinary_trig_edge);
+void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, adc_preempt_trig_edge_type adc_preempt_trig_edge);
+void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value);
+void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count);
+void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state);
+void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state);
+void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state);
+void adc_conversion_stop(adc_type *adc_x);
+flag_status adc_conversion_stop_status_get(adc_type *adc_x);
+void adc_occe_each_conversion_enable(adc_type *adc_x, confirm_state new_state);
+void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
+flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x);
+void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
+flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x);
+uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
+uint32_t adc_combine_ordinary_conversion_data_get(void);
+uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
+flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
+void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
+void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state);
+void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state);
+void adc_oversample_ratio_shift_set(adc_type *adc_x, adc_oversample_ratio_type adc_oversample_ratio, adc_oversample_shift_type adc_oversample_shift);
+void adc_ordinary_oversample_trig_enable(adc_type *adc_x, confirm_state new_state);
+void adc_ordinary_oversample_restart_set(adc_type *adc_x, adc_ordinary_oversample_restart_type adc_ordinary_oversample_restart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_can.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_can.h
new file mode 100644
index 0000000..ab47b9c
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_can.h
@@ -0,0 +1,1042 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_can.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 can header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_CAN_H
+#define __AT32F435_437_CAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+
+/** @defgroup CAN_timeout_count
+ * @{
+ */
+
+#define FZC_TIMEOUT ((uint32_t)0x0000FFFF) /*!< time out for fzc bit */
+#define DZC_TIMEOUT ((uint32_t)0x0000FFFF) /*!< time out for dzc bit */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags_definition
+ * @brief can flag
+ * @{
+ */
+
+#define CAN_EAF_FLAG ((uint32_t)0x01) /*!< error active flag */
+#define CAN_EPF_FLAG ((uint32_t)0x02) /*!< error passive flag */
+#define CAN_BOF_FLAG ((uint32_t)0x03) /*!< bus-off flag */
+#define CAN_ETR_FLAG ((uint32_t)0x04) /*!< error type record flag */
+#define CAN_EOIF_FLAG ((uint32_t)0x05) /*!< error occur interrupt flag */
+#define CAN_TM0TCF_FLAG ((uint32_t)0x06) /*!< transmit mailbox 0 transmission completed flag */
+#define CAN_TM1TCF_FLAG ((uint32_t)0x07) /*!< transmit mailbox 1 transmission completed flag */
+#define CAN_TM2TCF_FLAG ((uint32_t)0x08) /*!< transmit mailbox 2 transmission completed flag */
+#define CAN_RF0MN_FLAG ((uint32_t)0x09) /*!< receive fifo 0 message num flag */
+#define CAN_RF0FF_FLAG ((uint32_t)0x0A) /*!< receive fifo 0 full flag */
+#define CAN_RF0OF_FLAG ((uint32_t)0x0B) /*!< receive fifo 0 overflow flag */
+#define CAN_RF1MN_FLAG ((uint32_t)0x0C) /*!< receive fifo 1 message num flag */
+#define CAN_RF1FF_FLAG ((uint32_t)0x0D) /*!< receive fifo 1 full flag */
+#define CAN_RF1OF_FLAG ((uint32_t)0x0E) /*!< receive fifo 1 overflow flag */
+#define CAN_QDZIF_FLAG ((uint32_t)0x0F) /*!< quit doze mode interrupt flag */
+#define CAN_EDZC_FLAG ((uint32_t)0x10) /*!< enter doze mode confirm flag */
+#define CAN_TMEF_FLAG ((uint32_t)0x11) /*!< transmit mailbox empty flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_interrupts_definition
+ * @brief can interrupt
+ * @{
+ */
+
+#define CAN_TCIEN_INT ((uint32_t)0x00000001) /*!< transmission complete interrupt */
+#define CAN_RF0MIEN_INT ((uint32_t)0x00000002) /*!< receive fifo 0 message interrupt */
+#define CAN_RF0FIEN_INT ((uint32_t)0x00000004) /*!< receive fifo 0 full interrupt */
+#define CAN_RF0OIEN_INT ((uint32_t)0x00000008) /*!< receive fifo 0 overflow interrupt */
+#define CAN_RF1MIEN_INT ((uint32_t)0x00000010) /*!< receive fifo 1 message interrupt */
+#define CAN_RF1FIEN_INT ((uint32_t)0x00000020) /*!< receive fifo 1 full interrupt */
+#define CAN_RF1OIEN_INT ((uint32_t)0x00000040) /*!< receive fifo 1 overflow interrupt */
+#define CAN_EAIEN_INT ((uint32_t)0x00000100) /*!< error active interrupt */
+#define CAN_EPIEN_INT ((uint32_t)0x00000200) /*!< error passive interrupt */
+#define CAN_BOIEN_INT ((uint32_t)0x00000400) /*!< bus-off interrupt */
+#define CAN_ETRIEN_INT ((uint32_t)0x00000800) /*!< error type record interrupt */
+#define CAN_EOIEN_INT ((uint32_t)0x00008000) /*!< error occur interrupt */
+#define CAN_QDZIEN_INT ((uint32_t)0x00010000) /*!< quit doze mode interrupt */
+#define CAN_EDZIEN_INT ((uint32_t)0x00020000) /*!< enter doze mode confirm interrupt */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief can flag clear operation macro definition val
+ */
+#define CAN_MSTS_EOIF_VAL ((uint32_t)0x00000004) /*!< eoif bit value, it clear by writing 1 */
+#define CAN_MSTS_QDZIF_VAL ((uint32_t)0x00000008) /*!< qdzif bit value, it clear by writing 1 */
+#define CAN_MSTS_EDZIF_VAL ((uint32_t)0x00000010) /*!< edzif bit value, it clear by writing 1 */
+#define CAN_TSTS_TM0TCF_VAL ((uint32_t)0x00000001) /*!< tm0tcf bit value, it clear by writing 1 */
+#define CAN_TSTS_TM1TCF_VAL ((uint32_t)0x00000100) /*!< tm1tcf bit value, it clear by writing 1 */
+#define CAN_TSTS_TM2TCF_VAL ((uint32_t)0x00010000) /*!< tm2tcf bit value, it clear by writing 1 */
+#define CAN_TSTS_TM0CT_VAL ((uint32_t)0x00000080) /*!< tm0ct bit value, it clear by writing 1 */
+#define CAN_TSTS_TM1CT_VAL ((uint32_t)0x00008000) /*!< tm1ct bit value, it clear by writing 1 */
+#define CAN_TSTS_TM2CT_VAL ((uint32_t)0x00800000) /*!< tm2ct bit value, it clear by writing 1 */
+#define CAN_RF0_RF0FF_VAL ((uint32_t)0x00000008) /*!< rf0ff bit value, it clear by writing 1 */
+#define CAN_RF0_RF0OF_VAL ((uint32_t)0x00000010) /*!< rf0of bit value, it clear by writing 1 */
+#define CAN_RF0_RF0R_VAL ((uint32_t)0x00000020) /*!< rf0r bit value, it clear by writing 1 */
+#define CAN_RF1_RF1FF_VAL ((uint32_t)0x00000008) /*!< rf1ff bit value, it clear by writing 1 */
+#define CAN_RF1_RF1OF_VAL ((uint32_t)0x00000010) /*!< rf1of bit value, it clear by writing 1 */
+#define CAN_RF1_RF1R_VAL ((uint32_t)0x00000020) /*!< rf1r bit value, it clear by writing 1 */
+
+/** @defgroup CAN_exported_types
+ * @{
+ */
+
+/**
+ * @brief can filter fifo
+ */
+typedef enum
+{
+ CAN_FILTER_FIFO0 = 0x00, /*!< filter fifo 0 assignment for filter x */
+ CAN_FILTER_FIFO1 = 0x01 /*!< filter fifo 1 assignment for filter x */
+} can_filter_fifo_type;
+
+/**
+ * @brief can filter mode
+ */
+typedef enum
+{
+ CAN_FILTER_MODE_ID_MASK = 0x00, /*!< identifier mask mode */
+ CAN_FILTER_MODE_ID_LIST = 0x01 /*!< identifier list mode */
+} can_filter_mode_type;
+
+/**
+ * @brief can filter bit width select
+ */
+typedef enum
+{
+ CAN_FILTER_16BIT = 0x00, /*!< two 16-bit filters */
+ CAN_FILTER_32BIT = 0x01 /*!< one 32-bit filter */
+} can_filter_bit_width_type;
+
+/**
+ * @brief can mode
+ */
+typedef enum
+{
+ CAN_MODE_COMMUNICATE = 0x00, /*!< communication mode */
+ CAN_MODE_LOOPBACK = 0x01, /*!< loopback mode */
+ CAN_MODE_LISTENONLY = 0x02, /*!< listen-only mode */
+ CAN_MODE_LISTENONLY_LOOPBACK = 0x03 /*!< loopback combined with listen-only mode */
+} can_mode_type;
+
+/**
+ * @brief can operating mode
+ */
+typedef enum
+{
+ CAN_OPERATINGMODE_FREEZE = 0x00, /*!< freeze mode */
+ CAN_OPERATINGMODE_DOZE = 0x01, /*!< doze mode */
+ CAN_OPERATINGMODE_COMMUNICATE = 0x02 /*!< communication mode */
+} can_operating_mode_type;
+
+/**
+ * @brief can resynchronization adjust width
+ */
+typedef enum
+{
+ CAN_RSAW_1TQ = 0x00, /*!< 1 time quantum */
+ CAN_RSAW_2TQ = 0x01, /*!< 2 time quantum */
+ CAN_RSAW_3TQ = 0x02, /*!< 3 time quantum */
+ CAN_RSAW_4TQ = 0x03 /*!< 4 time quantum */
+} can_rsaw_type;
+
+/**
+ * @brief can bit time segment 1
+ */
+typedef enum
+{
+ CAN_BTS1_1TQ = 0x00, /*!< 1 time quantum */
+ CAN_BTS1_2TQ = 0x01, /*!< 2 time quantum */
+ CAN_BTS1_3TQ = 0x02, /*!< 3 time quantum */
+ CAN_BTS1_4TQ = 0x03, /*!< 4 time quantum */
+ CAN_BTS1_5TQ = 0x04, /*!< 5 time quantum */
+ CAN_BTS1_6TQ = 0x05, /*!< 6 time quantum */
+ CAN_BTS1_7TQ = 0x06, /*!< 7 time quantum */
+ CAN_BTS1_8TQ = 0x07, /*!< 8 time quantum */
+ CAN_BTS1_9TQ = 0x08, /*!< 9 time quantum */
+ CAN_BTS1_10TQ = 0x09, /*!< 10 time quantum */
+ CAN_BTS1_11TQ = 0x0A, /*!< 11 time quantum */
+ CAN_BTS1_12TQ = 0x0B, /*!< 12 time quantum */
+ CAN_BTS1_13TQ = 0x0C, /*!< 13 time quantum */
+ CAN_BTS1_14TQ = 0x0D, /*!< 14 time quantum */
+ CAN_BTS1_15TQ = 0x0E, /*!< 15 time quantum */
+ CAN_BTS1_16TQ = 0x0F /*!< 16 time quantum */
+} can_bts1_type;
+
+/**
+ * @brief can bit time segment 2
+ */
+typedef enum
+{
+ CAN_BTS2_1TQ = 0x00, /*!< 1 time quantum */
+ CAN_BTS2_2TQ = 0x01, /*!< 2 time quantum */
+ CAN_BTS2_3TQ = 0x02, /*!< 3 time quantum */
+ CAN_BTS2_4TQ = 0x03, /*!< 4 time quantum */
+ CAN_BTS2_5TQ = 0x04, /*!< 5 time quantum */
+ CAN_BTS2_6TQ = 0x05, /*!< 6 time quantum */
+ CAN_BTS2_7TQ = 0x06, /*!< 7 time quantum */
+ CAN_BTS2_8TQ = 0x07 /*!< 8 time quantum */
+} can_bts2_type;
+
+/**
+ * @brief can identifier type
+ */
+typedef enum
+{
+ CAN_ID_STANDARD = 0x00, /*!< standard Id */
+ CAN_ID_EXTENDED = 0x01 /*!< extended Id */
+} can_identifier_type;
+
+/**
+ * @brief can transmission frame type
+ */
+typedef enum
+{
+ CAN_TFT_DATA = 0x00, /*!< data frame */
+ CAN_TFT_REMOTE = 0x01 /*!< remote frame */
+} can_trans_frame_type;
+
+/**
+ * @brief can tx mailboxes
+ */
+typedef enum
+{
+ CAN_TX_MAILBOX0 = 0x00, /*!< can tx mailbox 0 */
+ CAN_TX_MAILBOX1 = 0x01, /*!< can tx mailbox 1 */
+ CAN_TX_MAILBOX2 = 0x02 /*!< can tx mailbox 2 */
+} can_tx_mailbox_num_type;
+
+/**
+ * @brief can receive fifo
+ */
+typedef enum
+{
+ CAN_RX_FIFO0 = 0x00, /*!< can fifo 0 used to receive */
+ CAN_RX_FIFO1 = 0x01 /*!< can fifo 1 used to receive */
+} can_rx_fifo_num_type;
+
+/**
+ * @brief can transmit status
+ */
+typedef enum
+{
+ CAN_TX_STATUS_FAILED = 0x00, /*!< can transmission failed */
+ CAN_TX_STATUS_SUCCESSFUL = 0x01, /*!< can transmission successful */
+ CAN_TX_STATUS_PENDING = 0x02, /*!< can transmission pending */
+ CAN_TX_STATUS_NO_EMPTY = 0x04 /*!< can transmission no empty mailbox */
+} can_transmit_status_type;
+
+/**
+ * @brief can enter doze mode status
+ */
+typedef enum
+{
+ CAN_ENTER_DOZE_FAILED = 0x00, /*!< can enter the doze mode failed */
+ CAN_ENTER_DOZE_SUCCESSFUL = 0x01 /*!< can enter the doze mode successful */
+} can_enter_doze_status_type;
+
+/**
+ * @brief can quit doze mode status
+ */
+typedef enum
+{
+ CAN_QUIT_DOZE_FAILED = 0x00, /*!< can quit doze mode failed */
+ CAN_QUIT_DOZE_SUCCESSFUL = 0x01 /*!< can quit doze mode successful */
+} can_quit_doze_status_type;
+
+/**
+ * @brief can message discarding rule select when overflow
+ */
+typedef enum
+{
+ CAN_DISCARDING_FIRST_RECEIVED = 0x00, /*!< can discarding the first received message */
+ CAN_DISCARDING_LAST_RECEIVED = 0x01 /*!< can discarding the last received message */
+} can_msg_discarding_rule_type;
+
+/**
+ * @brief can multiple message sending sequence rule
+ */
+typedef enum
+{
+ CAN_SENDING_BY_ID = 0x00, /*!< can sending the minimum id message first*/
+ CAN_SENDING_BY_REQUEST = 0x01 /*!< can sending the first request message first */
+} can_msg_sending_rule_type;
+
+/**
+ * @brief can error type record
+ */
+typedef enum
+{
+ CAN_ERRORRECORD_NOERR = 0x00, /*!< no error */
+ CAN_ERRORRECORD_STUFFERR = 0x01, /*!< stuff error */
+ CAN_ERRORRECORD_FORMERR = 0x02, /*!< form error */
+ CAN_ERRORRECORD_ACKERR = 0x03, /*!< acknowledgment error */
+ CAN_ERRORRECORD_BITRECESSIVEERR = 0x04, /*!< bit recessive error */
+ CAN_ERRORRECORD_BITDOMINANTERR = 0x05, /*!< bit dominant error */
+ CAN_ERRORRECORD_CRCERR = 0x06, /*!< crc error */
+ CAN_ERRORRECORD_SOFTWARESETERR = 0x07 /*!< software set error */
+} can_error_record_type;
+
+/**
+ * @brief can init structure definition
+ */
+typedef struct
+{
+ can_mode_type mode_selection; /*!< specifies the can mode.*/
+
+ confirm_state ttc_enable; /*!< time triggered communication mode enable */
+
+ confirm_state aebo_enable; /*!< automatic exit bus-off enable */
+
+ confirm_state aed_enable; /*!< automatic exit doze mode enable */
+
+ confirm_state prsf_enable; /*!< prohibit retransmission when sending fails enable */
+
+ can_msg_discarding_rule_type mdrsel_selection; /*!< message discarding rule select when overflow */
+
+ can_msg_sending_rule_type mmssr_selection; /*!< multiple message sending sequence rule */
+
+} can_base_type;
+
+/**
+ * @brief can baudrate structure definition
+ */
+typedef struct
+{
+ uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x400.*/
+
+ can_rsaw_type rsaw_size; /*!< resynchronization adjust width */
+
+ can_bts1_type bts1_size; /*!< bit time segment 1 */
+
+ can_bts2_type bts2_size; /*!< bit time segment 2 */
+
+} can_baudrate_type;
+
+/**
+ * @brief can filter init structure definition
+ */
+typedef struct
+{
+ confirm_state filter_activate_enable; /*!< enable or disable the filter activate.*/
+
+ can_filter_mode_type filter_mode; /*!< config the filter mode mask or list.*/
+
+ can_filter_fifo_type filter_fifo; /*!< config the fifo which will be assigned to the filter. */
+
+ uint8_t filter_number; /*!< config the filter number, parameter ranges from 0 to 13. */
+
+ can_filter_bit_width_type filter_bit; /*!< config the filter bit width 16bit or 32bit.*/
+
+ uint16_t filter_id_high; /*!< config the filter identification, for 32-bit configuration
+ it's high 16 bits, for 16-bit configuration it's first. */
+
+ uint16_t filter_id_low; /*!< config the filter identification, for 32-bit configuration
+ it's low 16 bits, for 16-bit configuration it's second. */
+
+ uint16_t filter_mask_high; /*!< config the filter mask or identification, according to the filtering mode,
+ for 32-bit configuration it's high 16 bits, for 16-bit configuration it's first. */
+
+ uint16_t filter_mask_low; /*!< config the filter mask or identification, according to the filtering mode,
+ for 32-bit configuration it's low 16 bits, for 16-bit configuration it's second. */
+} can_filter_init_type;
+
+/**
+ * @brief can tx message structure definition
+ */
+typedef struct
+{
+ uint32_t standard_id; /*!< specifies the 11 bits standard identifier.
+ this parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t extended_id; /*!< specifies the 29 bits extended identifier.
+ this parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ can_identifier_type id_type; /*!< specifies identifier type for the transmit message.*/
+
+ can_trans_frame_type frame_type; /*!< specifies frame type for the transmit message.*/
+
+ uint8_t dlc; /*!< specifies frame data length that will be transmitted.
+ this parameter can be a value between 0 to 8 */
+
+ uint8_t data[8]; /*!< contains the transmit data. it ranges from 0 to 0xFF. */
+
+} can_tx_message_type;
+
+/**
+ * @brief can rx message structure definition
+ */
+typedef struct
+{
+ uint32_t standard_id; /*!< specifies the 11 bits standard identifier
+ this parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t extended_id; /*!< specifies the 29 bits extended identifier.
+ this parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ can_identifier_type id_type; /*!< specifies identifier type for the receive message.*/
+
+ can_trans_frame_type frame_type; /*!< specifies frame type for the receive message.*/
+
+ uint8_t dlc; /*!< specifies the frame data length that will be received.
+ this parameter can be a value between 0 to 8 */
+
+ uint8_t data[8]; /*!< contains the receive data. it ranges from 0 to 0xFF.*/
+
+ uint8_t filter_index; /*!< specifies the message stored in which filter
+ this parameter can be a value between 0 to 0xFF */
+} can_rx_message_type;
+
+/**
+ * @brief can controller area network tx mailbox
+ */
+typedef struct
+{
+ /**
+ * @brief can tmi register
+ */
+ union
+ {
+ __IO uint32_t tmi;
+ struct
+ {
+ __IO uint32_t tmsr : 1; /* [0] */
+ __IO uint32_t tmfrsel : 1; /* [1] */
+ __IO uint32_t tmidsel : 1; /* [2] */
+ __IO uint32_t tmeid : 18;/* [20:3] */
+ __IO uint32_t tmsid : 11;/* [31:21] */
+ } tmi_bit;
+ };
+
+ /**
+ * @brief can tmc register
+ */
+ union
+ {
+ __IO uint32_t tmc;
+ struct
+ {
+ __IO uint32_t tmdtbl : 4; /* [3:0] */
+ __IO uint32_t reserved1 : 4; /* [7:4] */
+ __IO uint32_t tmtsten : 1; /* [8] */
+ __IO uint32_t reserved2 : 7; /* [15:9] */
+ __IO uint32_t tmts : 16;/* [31:16] */
+ } tmc_bit;
+ };
+
+ /**
+ * @brief can tmdtl register
+ */
+ union
+ {
+ __IO uint32_t tmdtl;
+ struct
+ {
+ __IO uint32_t tmdt0 : 8; /* [7:0] */
+ __IO uint32_t tmdt1 : 8; /* [15:8] */
+ __IO uint32_t tmdt2 : 8; /* [23:16] */
+ __IO uint32_t tmdt3 : 8; /* [31:24] */
+ } tmdtl_bit;
+ };
+
+ /**
+ * @brief can tmdth register
+ */
+ union
+ {
+ __IO uint32_t tmdth;
+ struct
+ {
+ __IO uint32_t tmdt4 : 8; /* [7:0] */
+ __IO uint32_t tmdt5 : 8; /* [15:8] */
+ __IO uint32_t tmdt6 : 8; /* [23:16] */
+ __IO uint32_t tmdt7 : 8; /* [31:24] */
+ } tmdth_bit;
+ };
+} can_tx_mailbox_type;
+
+/**
+ * @brief can controller area network fifo mailbox
+ */
+typedef struct
+{
+ /**
+ * @brief can rfi register
+ */
+ union
+ {
+ __IO uint32_t rfi;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t rffri : 1; /* [1] */
+ __IO uint32_t rfidi : 1; /* [2] */
+ __IO uint32_t rfeid : 18;/* [20:3] */
+ __IO uint32_t rfsid : 11;/* [31:21] */
+ } rfi_bit;
+ };
+
+ /**
+ * @brief can rfc register
+ */
+ union
+ {
+ __IO uint32_t rfc;
+ struct
+ {
+ __IO uint32_t rfdtl : 4; /* [3:0] */
+ __IO uint32_t reserved1 : 4; /* [7:4] */
+ __IO uint32_t rffmn : 8; /* [15:8] */
+ __IO uint32_t rfts : 16;/* [31:16] */
+ } rfc_bit;
+ };
+
+ /**
+ * @brief can rfdtl register
+ */
+ union
+ {
+ __IO uint32_t rfdtl;
+ struct
+ {
+ __IO uint32_t rfdt0 : 8; /* [7:0] */
+ __IO uint32_t rfdt1 : 8; /* [15:8] */
+ __IO uint32_t rfdt2 : 8; /* [23:16] */
+ __IO uint32_t rfdt3 : 8; /* [31:24] */
+ } rfdtl_bit;
+ };
+
+ /**
+ * @brief can rfdth register
+ */
+ union
+ {
+ __IO uint32_t rfdth;
+ struct
+ {
+ __IO uint32_t rfdt4 : 8; /* [7:0] */
+ __IO uint32_t rfdt5 : 8; /* [15:8] */
+ __IO uint32_t rfdt6 : 8; /* [23:16] */
+ __IO uint32_t rfdt7 : 8; /* [31:24] */
+ } rfdth_bit;
+ };
+} can_fifo_mailbox_type;
+
+/**
+ * @brief can controller area network filter bit register
+ */
+typedef struct
+{
+ __IO uint32_t ffdb1;
+ __IO uint32_t ffdb2;
+} can_filter_register_type;
+
+/**
+ * @brief type define can register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief can mctrl register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t mctrl;
+ struct
+ {
+ __IO uint32_t fzen : 1; /* [0] */
+ __IO uint32_t dzen : 1; /* [1] */
+ __IO uint32_t mmssr : 1; /* [2] */
+ __IO uint32_t mdrsel : 1; /* [3] */
+ __IO uint32_t prsfen : 1; /* [4] */
+ __IO uint32_t aeden : 1; /* [5] */
+ __IO uint32_t aeboen : 1; /* [6] */
+ __IO uint32_t ttcen : 1; /* [7] */
+ __IO uint32_t reserved1 : 7; /* [14:8] */
+ __IO uint32_t sprst : 1; /* [15] */
+ __IO uint32_t ptd : 1; /* [16] */
+ __IO uint32_t reserved2 : 15;/*[31:17] */
+ } mctrl_bit;
+ };
+
+ /**
+ * @brief can msts register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t msts;
+ struct
+ {
+ __IO uint32_t fzc : 1; /* [0] */
+ __IO uint32_t dzc : 1; /* [1] */
+ __IO uint32_t eoif : 1; /* [2] */
+ __IO uint32_t qdzif : 1; /* [3] */
+ __IO uint32_t edzif : 1; /* [4] */
+ __IO uint32_t reserved1 : 3; /* [7:5] */
+ __IO uint32_t cuss : 1; /* [8] */
+ __IO uint32_t curs : 1; /* [9] */
+ __IO uint32_t lsamprx : 1; /* [10] */
+ __IO uint32_t realrx : 1; /* [11] */
+ __IO uint32_t reserved2 : 20;/*[31:12] */
+ } msts_bit;
+ };
+
+ /**
+ * @brief can tsts register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t tsts;
+ struct
+ {
+ __IO uint32_t tm0tcf : 1; /* [0] */
+ __IO uint32_t tm0tsf : 1; /* [1] */
+ __IO uint32_t tm0alf : 1; /* [2] */
+ __IO uint32_t tm0tef : 1; /* [3] */
+ __IO uint32_t reserved1 : 3; /* [6:4] */
+ __IO uint32_t tm0ct : 1; /* [7] */
+ __IO uint32_t tm1tcf : 1; /* [8] */
+ __IO uint32_t tm1tsf : 1; /* [9] */
+ __IO uint32_t tm1alf : 1; /* [10] */
+ __IO uint32_t tm1tef : 1; /* [11] */
+ __IO uint32_t reserved2 : 3; /* [14:12] */
+ __IO uint32_t tm1ct : 1; /* [15] */
+ __IO uint32_t tm2tcf : 1; /* [16] */
+ __IO uint32_t tm2tsf : 1; /* [17] */
+ __IO uint32_t tm2alf : 1; /* [18] */
+ __IO uint32_t tm2tef : 1; /* [19] */
+ __IO uint32_t reserved3 : 3; /* [22:20] */
+ __IO uint32_t tm2ct : 1; /* [23] */
+ __IO uint32_t tmnr : 2; /* [25:24] */
+ __IO uint32_t tm0ef : 1; /* [26] */
+ __IO uint32_t tm1ef : 1; /* [27] */
+ __IO uint32_t tm2ef : 1; /* [28] */
+ __IO uint32_t tm0lpf : 1; /* [29] */
+ __IO uint32_t tm1lpf : 1; /* [30] */
+ __IO uint32_t tm2lpf : 1; /* [31] */
+ } tsts_bit;
+ };
+
+ /**
+ * @brief can rf0 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t rf0;
+ struct
+ {
+ __IO uint32_t rf0mn : 2; /* [1:0] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t rf0ff : 1; /* [3] */
+ __IO uint32_t rf0of : 1; /* [4] */
+ __IO uint32_t rf0r : 1; /* [5] */
+ __IO uint32_t reserved2 : 26;/* [31:6] */
+ } rf0_bit;
+ };
+
+ /**
+ * @brief can rf1 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t rf1;
+ struct
+ {
+ __IO uint32_t rf1mn : 2; /* [1:0] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t rf1ff : 1; /* [3] */
+ __IO uint32_t rf1of : 1; /* [4] */
+ __IO uint32_t rf1r : 1; /* [5] */
+ __IO uint32_t reserved2 : 26;/* [31:6] */
+ } rf1_bit;
+ };
+
+ /**
+ * @brief can inten register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t inten;
+ struct
+ {
+ __IO uint32_t tcien : 1; /* [0] */
+ __IO uint32_t rf0mien : 1; /* [1] */
+ __IO uint32_t rf0fien : 1; /* [2] */
+ __IO uint32_t rf0oien : 1; /* [3] */
+ __IO uint32_t rf1mien : 1; /* [4] */
+ __IO uint32_t rf1fien : 1; /* [5] */
+ __IO uint32_t rf1oien : 1; /* [6] */
+ __IO uint32_t reserved1 : 1; /* [7] */
+ __IO uint32_t eaien : 1; /* [8] */
+ __IO uint32_t epien : 1; /* [9] */
+ __IO uint32_t boien : 1; /* [10] */
+ __IO uint32_t etrien : 1; /* [11] */
+ __IO uint32_t reserved2 : 3; /* [14:12] */
+ __IO uint32_t eoien : 1; /* [15] */
+ __IO uint32_t qdzien : 1; /* [16] */
+ __IO uint32_t edzien : 1; /* [17] */
+ __IO uint32_t reserved3 : 14;/* [31:18] */
+ } inten_bit;
+ };
+
+ /**
+ * @brief can ests register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t ests;
+ struct
+ {
+ __IO uint32_t eaf : 1; /* [0] */
+ __IO uint32_t epf : 1; /* [1] */
+ __IO uint32_t bof : 1; /* [2] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t etr : 3; /* [6:4] */
+ __IO uint32_t reserved2 : 9; /* [15:7] */
+ __IO uint32_t tec : 8; /* [23:16] */
+ __IO uint32_t rec : 8; /* [31:24] */
+ } ests_bit;
+ };
+
+ /**
+ * @brief can btmg register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t btmg;
+ struct
+ {
+ __IO uint32_t brdiv : 12;/* [11:0] */
+ __IO uint32_t reserved1 : 4; /* [15:12] */
+ __IO uint32_t bts1 : 4; /* [19:16] */
+ __IO uint32_t bts2 : 3; /* [22:20] */
+ __IO uint32_t reserved2 : 1; /* [23] */
+ __IO uint32_t rsaw : 2; /* [25:24] */
+ __IO uint32_t reserved3 : 4; /* [29:26] */
+ __IO uint32_t lben : 1; /* [30] */
+ __IO uint32_t loen : 1; /* [31] */
+ } btmg_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0x20~0x17C
+ */
+ __IO uint32_t reserved1[88];
+
+ /**
+ * @brief can controller area network tx mailbox register, offset:0x180~0x1AC
+ */
+ can_tx_mailbox_type tx_mailbox[3];
+
+ /**
+ * @brief can controller area network fifo mailbox register, offset:0x1B0~0x1CC
+ */
+ can_fifo_mailbox_type fifo_mailbox[2];
+
+ /**
+ * @brief can reserved register, offset:0x1D0~0x1FC
+ */
+ __IO uint32_t reserved2[12];
+
+ /**
+ * @brief can fctrl register, offset:0x200
+ */
+ union
+ {
+ __IO uint32_t fctrl;
+ struct
+ {
+ __IO uint32_t fcs : 1; /* [0] */
+ __IO uint32_t reserved1 : 31;/* [31:1] */
+ } fctrl_bit;
+ };
+
+ /**
+ * @brief can fmcfg register, offset:0x204
+ */
+ union
+ {
+ __IO uint32_t fmcfg;
+ struct
+ {
+ __IO uint32_t fmsel0 : 1; /* [0] */
+ __IO uint32_t fmsel1 : 1; /* [1] */
+ __IO uint32_t fmsel2 : 1; /* [2] */
+ __IO uint32_t fmsel3 : 1; /* [3] */
+ __IO uint32_t fmsel4 : 1; /* [4] */
+ __IO uint32_t fmsel5 : 1; /* [5] */
+ __IO uint32_t fmsel6 : 1; /* [6] */
+ __IO uint32_t fmsel7 : 1; /* [7] */
+ __IO uint32_t fmsel8 : 1; /* [8] */
+ __IO uint32_t fmsel9 : 1; /* [9] */
+ __IO uint32_t fmsel10 : 1; /* [10] */
+ __IO uint32_t fmsel11 : 1; /* [11] */
+ __IO uint32_t fmsel12 : 1; /* [12] */
+ __IO uint32_t fmsel13 : 1; /* [13] */
+ __IO uint32_t fmsel14 : 1; /* [14] */
+ __IO uint32_t fmsel15 : 1; /* [15] */
+ __IO uint32_t fmsel16 : 1; /* [16] */
+ __IO uint32_t fmsel17 : 1; /* [17] */
+ __IO uint32_t fmsel18 : 1; /* [18] */
+ __IO uint32_t fmsel19 : 1; /* [19] */
+ __IO uint32_t fmsel20 : 1; /* [20] */
+ __IO uint32_t fmsel21 : 1; /* [21] */
+ __IO uint32_t fmsel22 : 1; /* [22] */
+ __IO uint32_t fmsel23 : 1; /* [23] */
+ __IO uint32_t fmsel24 : 1; /* [24] */
+ __IO uint32_t fmsel25 : 1; /* [25] */
+ __IO uint32_t fmsel26 : 1; /* [26] */
+ __IO uint32_t fmsel27 : 1; /* [27] */
+ __IO uint32_t reserved1 : 4;/* [31:28] */
+ } fmcfg_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0x208
+ */
+ __IO uint32_t reserved3;
+
+ /**
+ * @brief can fbwcfg register, offset:0x20C
+ */
+ union
+ {
+ __IO uint32_t fbwcfg;
+ struct
+ {
+ __IO uint32_t fbwsel0 : 1; /* [0] */
+ __IO uint32_t fbwsel1 : 1; /* [1] */
+ __IO uint32_t fbwsel2 : 1; /* [2] */
+ __IO uint32_t fbwsel3 : 1; /* [3] */
+ __IO uint32_t fbwsel4 : 1; /* [4] */
+ __IO uint32_t fbwsel5 : 1; /* [5] */
+ __IO uint32_t fbwsel6 : 1; /* [6] */
+ __IO uint32_t fbwsel7 : 1; /* [7] */
+ __IO uint32_t fbwsel8 : 1; /* [8] */
+ __IO uint32_t fbwsel9 : 1; /* [9] */
+ __IO uint32_t fbwsel10 : 1; /* [10] */
+ __IO uint32_t fbwsel11 : 1; /* [11] */
+ __IO uint32_t fbwsel12 : 1; /* [12] */
+ __IO uint32_t fbwsel13 : 1; /* [13] */
+ __IO uint32_t fbwsel14 : 1; /* [14] */
+ __IO uint32_t fbwsel15 : 1; /* [15] */
+ __IO uint32_t fbwsel16 : 1; /* [16] */
+ __IO uint32_t fbwsel17 : 1; /* [17] */
+ __IO uint32_t fbwsel18 : 1; /* [18] */
+ __IO uint32_t fbwsel19 : 1; /* [19] */
+ __IO uint32_t fbwsel20 : 1; /* [20] */
+ __IO uint32_t fbwsel21 : 1; /* [21] */
+ __IO uint32_t fbwsel22 : 1; /* [22] */
+ __IO uint32_t fbwsel23 : 1; /* [23] */
+ __IO uint32_t fbwsel24 : 1; /* [24] */
+ __IO uint32_t fbwsel25 : 1; /* [25] */
+ __IO uint32_t fbwsel26 : 1; /* [26] */
+ __IO uint32_t fbwsel27 : 1; /* [27] */
+ __IO uint32_t reserved1 : 4;/* [31:28] */
+ } fbwcfg_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0x210
+ */
+ __IO uint32_t reserved4;
+
+ /**
+ * @brief can frf register, offset:0x214
+ */
+ union
+ {
+ __IO uint32_t frf;
+ struct
+ {
+ __IO uint32_t frfsel0 : 1; /* [0] */
+ __IO uint32_t frfsel1 : 1; /* [1] */
+ __IO uint32_t frfsel2 : 1; /* [2] */
+ __IO uint32_t frfsel3 : 1; /* [3] */
+ __IO uint32_t frfsel4 : 1; /* [4] */
+ __IO uint32_t frfsel5 : 1; /* [5] */
+ __IO uint32_t frfsel6 : 1; /* [6] */
+ __IO uint32_t frfsel7 : 1; /* [7] */
+ __IO uint32_t frfsel8 : 1; /* [8] */
+ __IO uint32_t frfsel9 : 1; /* [9] */
+ __IO uint32_t frfsel10 : 1; /* [10] */
+ __IO uint32_t frfsel11 : 1; /* [11] */
+ __IO uint32_t frfsel12 : 1; /* [12] */
+ __IO uint32_t frfsel13 : 1; /* [13] */
+ __IO uint32_t frfsel14 : 1; /* [14] */
+ __IO uint32_t frfsel15 : 1; /* [15] */
+ __IO uint32_t frfsel16 : 1; /* [16] */
+ __IO uint32_t frfsel17 : 1; /* [17] */
+ __IO uint32_t frfsel18 : 1; /* [18] */
+ __IO uint32_t frfsel19 : 1; /* [19] */
+ __IO uint32_t frfsel20 : 1; /* [20] */
+ __IO uint32_t frfsel21 : 1; /* [21] */
+ __IO uint32_t frfsel22 : 1; /* [22] */
+ __IO uint32_t frfsel23 : 1; /* [23] */
+ __IO uint32_t frfsel24 : 1; /* [24] */
+ __IO uint32_t frfsel25 : 1; /* [25] */
+ __IO uint32_t frfsel26 : 1; /* [26] */
+ __IO uint32_t frfsel27 : 1; /* [27] */
+ __IO uint32_t reserved1 : 4;/* [31:28] */
+ } frf_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0x218
+ */
+ __IO uint32_t reserved5;
+
+ /**
+ * @brief can facfg register, offset:0x21C
+ */
+ union
+ {
+ __IO uint32_t facfg;
+ struct
+ {
+ __IO uint32_t faen0 : 1; /* [0] */
+ __IO uint32_t faen1 : 1; /* [1] */
+ __IO uint32_t faen2 : 1; /* [2] */
+ __IO uint32_t faen3 : 1; /* [3] */
+ __IO uint32_t faen4 : 1; /* [4] */
+ __IO uint32_t faen5 : 1; /* [5] */
+ __IO uint32_t faen6 : 1; /* [6] */
+ __IO uint32_t faen7 : 1; /* [7] */
+ __IO uint32_t faen8 : 1; /* [8] */
+ __IO uint32_t faen9 : 1; /* [9] */
+ __IO uint32_t faen10 : 1; /* [10] */
+ __IO uint32_t faen11 : 1; /* [11] */
+ __IO uint32_t faen12 : 1; /* [12] */
+ __IO uint32_t faen13 : 1; /* [13] */
+ __IO uint32_t faen14 : 1; /* [14] */
+ __IO uint32_t faen15 : 1; /* [15] */
+ __IO uint32_t faen16 : 1; /* [16] */
+ __IO uint32_t faen17 : 1; /* [17] */
+ __IO uint32_t faen18 : 1; /* [18] */
+ __IO uint32_t faen19 : 1; /* [19] */
+ __IO uint32_t faen20 : 1; /* [20] */
+ __IO uint32_t faen21 : 1; /* [21] */
+ __IO uint32_t faen22 : 1; /* [22] */
+ __IO uint32_t faen23 : 1; /* [23] */
+ __IO uint32_t faen24 : 1; /* [24] */
+ __IO uint32_t faen25 : 1; /* [25] */
+ __IO uint32_t faen26 : 1; /* [26] */
+ __IO uint32_t faen27 : 1; /* [27] */
+ __IO uint32_t reserved1 : 4;/* [31:28] */
+ } facfg_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0x220~0x23C
+ */
+ __IO uint32_t reserved6[8];
+
+ /**
+ * @brief can ffb register, offset:0x240~0x2AC
+ */
+ can_filter_register_type ffb[28];
+} can_type;
+
+/**
+ * @}
+ */
+
+#define CAN1 ((can_type *) CAN1_BASE)
+#define CAN2 ((can_type *) CAN2_BASE)
+
+/** @defgroup CAN_exported_functions
+ * @{
+ */
+
+void can_reset(can_type* can_x);
+void can_baudrate_default_para_init(can_baudrate_type* can_baudrate_struct);
+error_status can_baudrate_set(can_type* can_x, can_baudrate_type* can_baudrate_struct);
+void can_default_para_init(can_base_type* can_base_struct);
+error_status can_base_init(can_type* can_x, can_base_type* can_base_struct);
+void can_filter_default_para_init(can_filter_init_type* can_filter_init_struct);
+void can_filter_init(can_type* can_x, can_filter_init_type* can_filter_init_struct);
+void can_debug_transmission_prohibit(can_type* can_x, confirm_state new_state);
+void can_ttc_mode_enable(can_type* can_x, confirm_state new_state);
+uint8_t can_message_transmit(can_type* can_x, can_tx_message_type* tx_message_struct);
+can_transmit_status_type can_transmit_status_get(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
+void can_transmit_cancel(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
+void can_message_receive(can_type* can_x, can_rx_fifo_num_type fifo_number, can_rx_message_type* rx_message_struct);
+void can_receive_fifo_release(can_type* can_x, can_rx_fifo_num_type fifo_number);
+uint8_t can_receive_message_pending_get(can_type* can_x, can_rx_fifo_num_type fifo_number);
+error_status can_operating_mode_set(can_type* can_x, can_operating_mode_type can_operating_mode);
+can_enter_doze_status_type can_doze_mode_enter(can_type* can_x);
+can_quit_doze_status_type can_doze_mode_exit(can_type* can_x);
+can_error_record_type can_error_type_record_get(can_type* can_x);
+uint8_t can_receive_error_counter_get(can_type* can_x);
+uint8_t can_transmit_error_counter_get(can_type* can_x);
+void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state);
+flag_status can_flag_get(can_type* can_x, uint32_t can_flag);
+void can_flag_clear(can_type* can_x, uint32_t can_flag);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_conf.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_conf.h
new file mode 100644
index 0000000..18e8615
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_conf.h
@@ -0,0 +1,175 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_conf.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 config header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_CONF_H
+#define __AT32F435_437_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief in the following line adjust the value of high speed exernal crystal (hext)
+ * used in your application
+ * tip: to avoid modifying this file each time you need to use different hext, you
+ * can define the hext value in your toolchain compiler preprocessor.
+ */
+#if !defined HEXT_VALUE
+#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed exernal crystal in hz */
+#endif
+
+/**
+ * @brief in the following line adjust the high speed exernal crystal (hext) startup
+ * timeout value
+ */
+#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
+#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
+
+/* module define -------------------------------------------------------------*/
+#define CRM_MODULE_ENABLED
+#define TMR_MODULE_ENABLED
+#define ERTC_MODULE_ENABLED
+#define GPIO_MODULE_ENABLED
+#define I2C_MODULE_ENABLED
+#define USART_MODULE_ENABLED
+#define PWC_MODULE_ENABLED
+#define CAN_MODULE_ENABLED
+#define ADC_MODULE_ENABLED
+#define DAC_MODULE_ENABLED
+#define SPI_MODULE_ENABLED
+#define EDMA_MODULE_ENABLED
+#define DMA_MODULE_ENABLED
+#define DEBUG_MODULE_ENABLED
+#define FLASH_MODULE_ENABLED
+#define CRC_MODULE_ENABLED
+#define WWDT_MODULE_ENABLED
+#define WDT_MODULE_ENABLED
+#define EXINT_MODULE_ENABLED
+#define SDIO_MODULE_ENABLED
+#define XMC_MODULE_ENABLED
+#define USB_MODULE_ENABLED
+#define ACC_MODULE_ENABLED
+#define MISC_MODULE_ENABLED
+#define QSPI_MODULE_ENABLED
+#define DVP_MODULE_ENABLED
+#define SCFG_MODULE_ENABLED
+#define EMAC_MODULE_ENABLED
+
+/* includes ------------------------------------------------------------------*/
+#ifdef CRM_MODULE_ENABLED
+#include "at32f435_437_crm.h"
+#endif
+#ifdef TMR_MODULE_ENABLED
+#include "at32f435_437_tmr.h"
+#endif
+#ifdef ERTC_MODULE_ENABLED
+#include "at32f435_437_ertc.h"
+#endif
+#ifdef GPIO_MODULE_ENABLED
+#include "at32f435_437_gpio.h"
+#endif
+#ifdef I2C_MODULE_ENABLED
+#include "at32f435_437_i2c.h"
+#endif
+#ifdef USART_MODULE_ENABLED
+#include "at32f435_437_usart.h"
+#endif
+#ifdef PWC_MODULE_ENABLED
+#include "at32f435_437_pwc.h"
+#endif
+#ifdef CAN_MODULE_ENABLED
+#include "at32f435_437_can.h"
+#endif
+#ifdef ADC_MODULE_ENABLED
+#include "at32f435_437_adc.h"
+#endif
+#ifdef DAC_MODULE_ENABLED
+#include "at32f435_437_dac.h"
+#endif
+#ifdef SPI_MODULE_ENABLED
+#include "at32f435_437_spi.h"
+#endif
+#ifdef DMA_MODULE_ENABLED
+#include "at32f435_437_dma.h"
+#endif
+#ifdef DEBUG_MODULE_ENABLED
+#include "at32f435_437_debug.h"
+#endif
+#ifdef FLASH_MODULE_ENABLED
+#include "at32f435_437_flash.h"
+#endif
+#ifdef CRC_MODULE_ENABLED
+#include "at32f435_437_crc.h"
+#endif
+#ifdef WWDT_MODULE_ENABLED
+#include "at32f435_437_wwdt.h"
+#endif
+#ifdef WDT_MODULE_ENABLED
+#include "at32f435_437_wdt.h"
+#endif
+#ifdef EXINT_MODULE_ENABLED
+#include "at32f435_437_exint.h"
+#endif
+#ifdef SDIO_MODULE_ENABLED
+#include "at32f435_437_sdio.h"
+#endif
+#ifdef XMC_MODULE_ENABLED
+#include "at32f435_437_xmc.h"
+#endif
+#ifdef ACC_MODULE_ENABLED
+#include "at32f435_437_acc.h"
+#endif
+#ifdef MISC_MODULE_ENABLED
+#include "at32f435_437_misc.h"
+#endif
+#ifdef EDMA_MODULE_ENABLED
+#include "at32f435_437_edma.h"
+#endif
+#ifdef QSPI_MODULE_ENABLED
+#include "at32f435_437_qspi.h"
+#endif
+#ifdef SCFG_MODULE_ENABLED
+#include "at32f435_437_scfg.h"
+#endif
+#ifdef EMAC_MODULE_ENABLED
+#include "at32f435_437_emac.h"
+#endif
+#ifdef DVP_MODULE_ENABLED
+#include "at32f435_437_dvp.h"
+#endif
+#ifdef USB_MODULE_ENABLED
+#include "at32f435_437_usb.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AT32F435_437_CONF_H */
+
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_crc.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_crc.h
new file mode 100644
index 0000000..6fdadc8
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_crc.h
@@ -0,0 +1,172 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_crc.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 crc header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_CRC_H
+#define __AT32F435_437_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/** @defgroup CRC_exported_types
+ * @{
+ */
+
+/**
+ * @brief crc reverse input data
+ */
+typedef enum
+{
+ CRC_REVERSE_INPUT_NO_AFFECTE = 0x00, /*!< input data no reverse */
+ CRC_REVERSE_INPUT_BY_BYTE = 0x01, /*!< input data reverse by byte */
+ CRC_REVERSE_INPUT_BY_HALFWORD = 0x02, /*!< input data reverse by half word */
+ CRC_REVERSE_INPUT_BY_WORD = 0x03 /*!< input data reverse by word */
+} crc_reverse_input_type;
+
+/**
+ * @brief crc reverse output data
+ */
+typedef enum
+{
+ CRC_REVERSE_OUTPUT_NO_AFFECTE = 0x00, /*!< output data no reverse */
+ CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */
+} crc_reverse_output_type;
+
+/**
+ * @brief type define crc register all
+ */
+typedef struct
+{
+ /**
+ * @brief crc dt register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t dt;
+ struct
+ {
+ __IO uint32_t dt : 32; /* [31:0] */
+ } dt_bit;
+ };
+
+ /**
+ * @brief crc cdt register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t cdt;
+ struct
+ {
+ __IO uint32_t cdt : 8 ; /* [7:0] */
+ __IO uint32_t reserved1 : 24 ;/* [31:8] */
+ } cdt_bit;
+ };
+
+ /**
+ * @brief crc ctrl register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t rst : 1 ; /* [0] */
+ __IO uint32_t reserved1 : 4 ; /* [4:1] */
+ __IO uint32_t revid : 2 ; /* [6:5] */
+ __IO uint32_t revod : 1 ; /* [7] */
+ __IO uint32_t reserved2 : 24 ;/* [31:8] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief crm reserved1 register, offset:0x0C
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief crc idt register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t idt;
+ struct
+ {
+ __IO uint32_t idt : 32; /* [31:0] */
+ } idt_bit;
+ };
+
+} crc_type;
+
+/**
+ * @}
+ */
+
+#define CRC ((crc_type *) CRC_BASE)
+
+/** @defgroup CRC_exported_functions
+ * @{
+ */
+
+void crc_data_reset(void);
+uint32_t crc_one_word_calculate(uint32_t data);
+uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length);
+uint32_t crc_data_get(void);
+void crc_common_data_set(uint8_t cdt_value);
+uint8_t crc_common_date_get(void);
+void crc_init_data_set(uint32_t value);
+void crc_reverse_input_data_set(crc_reverse_input_type value);
+void crc_reverse_output_data_set(crc_reverse_output_type value);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_crm.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_crm.h
new file mode 100644
index 0000000..01833a9
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_crm.h
@@ -0,0 +1,1565 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_crm.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 crm header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_CRM_H
+#define __AT32F435_437_CRM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup CRM
+ * @{
+ */
+
+#define CRM_REG(value) PERIPH_REG(CRM_BASE, value)
+#define CRM_REG_BIT(value) PERIPH_REG_BIT(value)
+
+/** @defgroup CRM_flags_definition
+ * @brief crm flag
+ * @{
+ */
+
+#define CRM_HICK_STABLE_FLAG MAKE_VALUE(0x00, 1) /*!< high speed internal clock stable flag */
+#define CRM_HEXT_STABLE_FLAG MAKE_VALUE(0x00, 17) /*!< high speed external crystal stable flag */
+#define CRM_PLL_STABLE_FLAG MAKE_VALUE(0x00, 25) /*!< phase locking loop stable flag */
+#define CRM_LEXT_STABLE_FLAG MAKE_VALUE(0x70, 1) /*!< low speed external crystal stable flag */
+#define CRM_LICK_STABLE_FLAG MAKE_VALUE(0x74, 1) /*!< low speed internal clock stable flag */
+#define CRM_NRST_RESET_FLAG MAKE_VALUE(0x74, 26) /*!< nrst pin reset flag */
+#define CRM_POR_RESET_FLAG MAKE_VALUE(0x74, 27) /*!< power on reset flag */
+#define CRM_SW_RESET_FLAG MAKE_VALUE(0x74, 28) /*!< software reset flag */
+#define CRM_WDT_RESET_FLAG MAKE_VALUE(0x74, 29) /*!< watchdog timer reset flag */
+#define CRM_WWDT_RESET_FLAG MAKE_VALUE(0x74, 30) /*!< window watchdog timer reset flag */
+#define CRM_LOWPOWER_RESET_FLAG MAKE_VALUE(0x74, 31) /*!< low-power reset flag */
+#define CRM_LICK_READY_INT_FLAG MAKE_VALUE(0x0C, 0) /*!< low speed internal clock stable interrupt ready flag */
+#define CRM_LEXT_READY_INT_FLAG MAKE_VALUE(0x0C, 1) /*!< low speed external crystal stable interrupt ready flag */
+#define CRM_HICK_READY_INT_FLAG MAKE_VALUE(0x0C, 2) /*!< high speed internal clock stable interrupt ready flag */
+#define CRM_HEXT_READY_INT_FLAG MAKE_VALUE(0x0C, 3) /*!< high speed external crystal stable interrupt ready flag */
+#define CRM_PLL_READY_INT_FLAG MAKE_VALUE(0x0C, 4) /*!< phase locking loop stable interrupt ready flag */
+#define CRM_CLOCK_FAILURE_INT_FLAG MAKE_VALUE(0x0C, 7) /*!< clock failure interrupt ready flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRM_interrupts_definition
+ * @brief crm interrupt
+ * @{
+ */
+
+#define CRM_LICK_STABLE_INT ((uint32_t)0x00000100) /*!< low speed internal clock stable interrupt */
+#define CRM_LEXT_STABLE_INT ((uint32_t)0x00000200) /*!< low speed external crystal stable interrupt */
+#define CRM_HICK_STABLE_INT ((uint32_t)0x00000400) /*!< high speed internal clock stable interrupt */
+#define CRM_HEXT_STABLE_INT ((uint32_t)0x00000800) /*!< high speed external crystal stable interrupt */
+#define CRM_PLL_STABLE_INT ((uint32_t)0x00001000) /*!< phase locking loop stable interrupt */
+#define CRM_CLOCK_FAILURE_INT ((uint32_t)0x00800000) /*!< clock failure interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRM_exported_types
+ * @{
+ */
+
+/**
+ * @brief crm periph clock
+ */
+typedef enum
+{
+#if defined (AT32F435xx)
+ /* ahb periph1 */
+ CRM_GPIOA_PERIPH_CLOCK = MAKE_VALUE(0x30, 0), /*!< gpioa periph clock */
+ CRM_GPIOB_PERIPH_CLOCK = MAKE_VALUE(0x30, 1), /*!< gpiob periph clock */
+ CRM_GPIOC_PERIPH_CLOCK = MAKE_VALUE(0x30, 2), /*!< gpioc periph clock */
+ CRM_GPIOD_PERIPH_CLOCK = MAKE_VALUE(0x30, 3), /*!< gpiod periph clock */
+ CRM_GPIOE_PERIPH_CLOCK = MAKE_VALUE(0x30, 4), /*!< gpioe periph clock */
+ CRM_GPIOF_PERIPH_CLOCK = MAKE_VALUE(0x30, 5), /*!< gpiof periph clock */
+ CRM_GPIOG_PERIPH_CLOCK = MAKE_VALUE(0x30, 6), /*!< gpiog periph clock */
+ CRM_GPIOH_PERIPH_CLOCK = MAKE_VALUE(0x30, 7), /*!< gpioh periph clock */
+ CRM_CRC_PERIPH_CLOCK = MAKE_VALUE(0x30, 12), /*!< crc periph clock */
+ CRM_EDMA_PERIPH_CLOCK = MAKE_VALUE(0x30, 21), /*!< edma periph clock */
+ CRM_DMA1_PERIPH_CLOCK = MAKE_VALUE(0x30, 22), /*!< dma1 periph clock */
+ CRM_DMA2_PERIPH_CLOCK = MAKE_VALUE(0x30, 24), /*!< dma2 periph clock */
+ CRM_OTGFS2_PERIPH_CLOCK = MAKE_VALUE(0x30, 29), /*!< otgfs2 periph clock */
+ /* ahb periph2 */
+ CRM_DVP_PERIPH_CLOCK = MAKE_VALUE(0x34, 0), /*!< dvp periph clock */
+ CRM_OTGFS1_PERIPH_CLOCK = MAKE_VALUE(0x34, 7), /*!< otgfs1 periph clock */
+ CRM_SDIO1_PERIPH_CLOCK = MAKE_VALUE(0x34, 15), /*!< sdio1 periph clock */
+ /* ahb periph3 */
+ CRM_XMC_PERIPH_CLOCK = MAKE_VALUE(0x38, 0), /*!< xmc periph clock */
+ CRM_QSPI1_PERIPH_CLOCK = MAKE_VALUE(0x38, 1), /*!< qspi1 periph clock */
+ CRM_QSPI2_PERIPH_CLOCK = MAKE_VALUE(0x38, 14), /*!< qspi2 periph clock */
+ CRM_SDIO2_PERIPH_CLOCK = MAKE_VALUE(0x38, 15), /*!< sdio2 periph clock */
+ /* apb1 periph */
+ CRM_TMR2_PERIPH_CLOCK = MAKE_VALUE(0x40, 0), /*!< tmr2 periph clock */
+ CRM_TMR3_PERIPH_CLOCK = MAKE_VALUE(0x40, 1), /*!< tmr3 periph clock */
+ CRM_TMR4_PERIPH_CLOCK = MAKE_VALUE(0x40, 2), /*!< tmr4 periph clock */
+ CRM_TMR5_PERIPH_CLOCK = MAKE_VALUE(0x40, 3), /*!< tmr5 periph clock */
+ CRM_TMR6_PERIPH_CLOCK = MAKE_VALUE(0x40, 4), /*!< tmr6 periph clock */
+ CRM_TMR7_PERIPH_CLOCK = MAKE_VALUE(0x40, 5), /*!< tmr7 periph clock */
+ CRM_TMR12_PERIPH_CLOCK = MAKE_VALUE(0x40, 6), /*!< tmr12 periph clock */
+ CRM_TMR13_PERIPH_CLOCK = MAKE_VALUE(0x40, 7), /*!< tmr13 periph clock */
+ CRM_TMR14_PERIPH_CLOCK = MAKE_VALUE(0x40, 8), /*!< tmr14 periph clock */
+ CRM_WWDT_PERIPH_CLOCK = MAKE_VALUE(0x40, 11), /*!< wwdt periph clock */
+ CRM_SPI2_PERIPH_CLOCK = MAKE_VALUE(0x40, 14), /*!< spi2 periph clock */
+ CRM_SPI3_PERIPH_CLOCK = MAKE_VALUE(0x40, 15), /*!< spi3 periph clock */
+ CRM_USART2_PERIPH_CLOCK = MAKE_VALUE(0x40, 17), /*!< usart2 periph clock */
+ CRM_USART3_PERIPH_CLOCK = MAKE_VALUE(0x40, 18), /*!< usart3 periph clock */
+ CRM_UART4_PERIPH_CLOCK = MAKE_VALUE(0x40, 19), /*!< uart4 periph clock */
+ CRM_UART5_PERIPH_CLOCK = MAKE_VALUE(0x40, 20), /*!< uart5 periph clock */
+ CRM_I2C1_PERIPH_CLOCK = MAKE_VALUE(0x40, 21), /*!< i2c1 periph clock */
+ CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x40, 22), /*!< i2c2 periph clock */
+ CRM_I2C3_PERIPH_CLOCK = MAKE_VALUE(0x40, 23), /*!< i2c3 periph clock */
+ CRM_CAN1_PERIPH_CLOCK = MAKE_VALUE(0x40, 25), /*!< can1 periph clock */
+ CRM_CAN2_PERIPH_CLOCK = MAKE_VALUE(0x40, 26), /*!< can2 periph clock */
+ CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x40, 28), /*!< pwc periph clock */
+ CRM_DAC_PERIPH_CLOCK = MAKE_VALUE(0x40, 29), /*!< dac periph clock */
+ CRM_UART7_PERIPH_CLOCK = MAKE_VALUE(0x40, 30), /*!< uart7 periph clock */
+ CRM_UART8_PERIPH_CLOCK = MAKE_VALUE(0x40, 31), /*!< uart8 periph clock */
+ /* apb2 periph */
+ CRM_TMR1_PERIPH_CLOCK = MAKE_VALUE(0x44, 0), /*!< tmr1 periph clock */
+ CRM_TMR8_PERIPH_CLOCK = MAKE_VALUE(0x44, 1), /*!< tmr8 periph clock */
+ CRM_USART1_PERIPH_CLOCK = MAKE_VALUE(0x44, 4), /*!< usart1 periph clock */
+ CRM_USART6_PERIPH_CLOCK = MAKE_VALUE(0x44, 5), /*!< usart6 periph clock */
+ CRM_ADC1_PERIPH_CLOCK = MAKE_VALUE(0x44, 8), /*!< adc1 periph clock */
+ CRM_ADC2_PERIPH_CLOCK = MAKE_VALUE(0x44, 9), /*!< adc2 periph clock */
+ CRM_ADC3_PERIPH_CLOCK = MAKE_VALUE(0x44, 10), /*!< adc3 periph clock */
+ CRM_SPI1_PERIPH_CLOCK = MAKE_VALUE(0x44, 12), /*!< spi1 periph clock */
+ CRM_SPI4_PERIPH_CLOCK = MAKE_VALUE(0x44, 13), /*!< spi4 periph clock */
+ CRM_SCFG_PERIPH_CLOCK = MAKE_VALUE(0x44, 14), /*!< scfg periph clock */
+ CRM_TMR9_PERIPH_CLOCK = MAKE_VALUE(0x44, 16), /*!< tmr9 periph clock */
+ CRM_TMR10_PERIPH_CLOCK = MAKE_VALUE(0x44, 17), /*!< tmr10 periph clock */
+ CRM_TMR11_PERIPH_CLOCK = MAKE_VALUE(0x44, 18), /*!< tmr11 periph clock */
+ CRM_TMR20_PERIPH_CLOCK = MAKE_VALUE(0x44, 20), /*!< tmr20 periph clock */
+ CRM_ACC_PERIPH_CLOCK = MAKE_VALUE(0x44, 29) /*!< acc periph clock */
+#endif
+
+#if defined (AT32F437xx)
+ /* ahb periph1 */
+ CRM_GPIOA_PERIPH_CLOCK = MAKE_VALUE(0x30, 0), /*!< gpioa periph clock */
+ CRM_GPIOB_PERIPH_CLOCK = MAKE_VALUE(0x30, 1), /*!< gpiob periph clock */
+ CRM_GPIOC_PERIPH_CLOCK = MAKE_VALUE(0x30, 2), /*!< gpioc periph clock */
+ CRM_GPIOD_PERIPH_CLOCK = MAKE_VALUE(0x30, 3), /*!< gpiod periph clock */
+ CRM_GPIOE_PERIPH_CLOCK = MAKE_VALUE(0x30, 4), /*!< gpioe periph clock */
+ CRM_GPIOF_PERIPH_CLOCK = MAKE_VALUE(0x30, 5), /*!< gpiof periph clock */
+ CRM_GPIOG_PERIPH_CLOCK = MAKE_VALUE(0x30, 6), /*!< gpiog periph clock */
+ CRM_GPIOH_PERIPH_CLOCK = MAKE_VALUE(0x30, 7), /*!< gpioh periph clock */
+ CRM_CRC_PERIPH_CLOCK = MAKE_VALUE(0x30, 12), /*!< crc periph clock */
+ CRM_EDMA_PERIPH_CLOCK = MAKE_VALUE(0x30, 21), /*!< edma periph clock */
+ CRM_DMA1_PERIPH_CLOCK = MAKE_VALUE(0x30, 22), /*!< dma1 periph clock */
+ CRM_DMA2_PERIPH_CLOCK = MAKE_VALUE(0x30, 24), /*!< dma2 periph clock */
+ CRM_EMAC_PERIPH_CLOCK = MAKE_VALUE(0x30, 25), /*!< emac periph clock */
+ CRM_EMACTX_PERIPH_CLOCK = MAKE_VALUE(0x30, 26), /*!< emac tx periph clock */
+ CRM_EMACRX_PERIPH_CLOCK = MAKE_VALUE(0x30, 27), /*!< emac rx periph clock */
+ CRM_EMACPTP_PERIPH_CLOCK = MAKE_VALUE(0x30, 28), /*!< emac ptp periph clock */
+ CRM_OTGFS2_PERIPH_CLOCK = MAKE_VALUE(0x30, 29), /*!< otgfs2 periph clock */
+ /* ahb periph2 */
+ CRM_DVP_PERIPH_CLOCK = MAKE_VALUE(0x34, 0), /*!< dvp periph clock */
+ CRM_OTGFS1_PERIPH_CLOCK = MAKE_VALUE(0x34, 7), /*!< otgfs1 periph clock */
+ CRM_SDIO1_PERIPH_CLOCK = MAKE_VALUE(0x34, 15), /*!< sdio1 periph clock */
+ /* ahb periph3 */
+ CRM_XMC_PERIPH_CLOCK = MAKE_VALUE(0x38, 0), /*!< xmc periph clock */
+ CRM_QSPI1_PERIPH_CLOCK = MAKE_VALUE(0x38, 1), /*!< qspi1 periph clock */
+ CRM_QSPI2_PERIPH_CLOCK = MAKE_VALUE(0x38, 14), /*!< qspi2 periph clock */
+ CRM_SDIO2_PERIPH_CLOCK = MAKE_VALUE(0x38, 15), /*!< sdio2 periph clock */
+ /* apb1 periph */
+ CRM_TMR2_PERIPH_CLOCK = MAKE_VALUE(0x40, 0), /*!< tmr2 periph clock */
+ CRM_TMR3_PERIPH_CLOCK = MAKE_VALUE(0x40, 1), /*!< tmr3 periph clock */
+ CRM_TMR4_PERIPH_CLOCK = MAKE_VALUE(0x40, 2), /*!< tmr4 periph clock */
+ CRM_TMR5_PERIPH_CLOCK = MAKE_VALUE(0x40, 3), /*!< tmr5 periph clock */
+ CRM_TMR6_PERIPH_CLOCK = MAKE_VALUE(0x40, 4), /*!< tmr6 periph clock */
+ CRM_TMR7_PERIPH_CLOCK = MAKE_VALUE(0x40, 5), /*!< tmr7 periph clock */
+ CRM_TMR12_PERIPH_CLOCK = MAKE_VALUE(0x40, 6), /*!< tmr12 periph clock */
+ CRM_TMR13_PERIPH_CLOCK = MAKE_VALUE(0x40, 7), /*!< tmr13 periph clock */
+ CRM_TMR14_PERIPH_CLOCK = MAKE_VALUE(0x40, 8), /*!< tmr14 periph clock */
+ CRM_WWDT_PERIPH_CLOCK = MAKE_VALUE(0x40, 11), /*!< wwdt periph clock */
+ CRM_SPI2_PERIPH_CLOCK = MAKE_VALUE(0x40, 14), /*!< spi2 periph clock */
+ CRM_SPI3_PERIPH_CLOCK = MAKE_VALUE(0x40, 15), /*!< spi3 periph clock */
+ CRM_USART2_PERIPH_CLOCK = MAKE_VALUE(0x40, 17), /*!< usart2 periph clock */
+ CRM_USART3_PERIPH_CLOCK = MAKE_VALUE(0x40, 18), /*!< usart3 periph clock */
+ CRM_UART4_PERIPH_CLOCK = MAKE_VALUE(0x40, 19), /*!< uart4 periph clock */
+ CRM_UART5_PERIPH_CLOCK = MAKE_VALUE(0x40, 20), /*!< uart5 periph clock */
+ CRM_I2C1_PERIPH_CLOCK = MAKE_VALUE(0x40, 21), /*!< i2c1 periph clock */
+ CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x40, 22), /*!< i2c2 periph clock */
+ CRM_I2C3_PERIPH_CLOCK = MAKE_VALUE(0x40, 23), /*!< i2c3 periph clock */
+ CRM_CAN1_PERIPH_CLOCK = MAKE_VALUE(0x40, 25), /*!< can1 periph clock */
+ CRM_CAN2_PERIPH_CLOCK = MAKE_VALUE(0x40, 26), /*!< can2 periph clock */
+ CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x40, 28), /*!< pwc periph clock */
+ CRM_DAC_PERIPH_CLOCK = MAKE_VALUE(0x40, 29), /*!< dac periph clock */
+ CRM_UART7_PERIPH_CLOCK = MAKE_VALUE(0x40, 30), /*!< uart7 periph clock */
+ CRM_UART8_PERIPH_CLOCK = MAKE_VALUE(0x40, 31), /*!< uart8 periph clock */
+ /* apb2 periph */
+ CRM_TMR1_PERIPH_CLOCK = MAKE_VALUE(0x44, 0), /*!< tmr1 periph clock */
+ CRM_TMR8_PERIPH_CLOCK = MAKE_VALUE(0x44, 1), /*!< tmr8 periph clock */
+ CRM_USART1_PERIPH_CLOCK = MAKE_VALUE(0x44, 4), /*!< usart1 periph clock */
+ CRM_USART6_PERIPH_CLOCK = MAKE_VALUE(0x44, 5), /*!< usart6 periph clock */
+ CRM_ADC1_PERIPH_CLOCK = MAKE_VALUE(0x44, 8), /*!< adc1 periph clock */
+ CRM_ADC2_PERIPH_CLOCK = MAKE_VALUE(0x44, 9), /*!< adc2 periph clock */
+ CRM_ADC3_PERIPH_CLOCK = MAKE_VALUE(0x44, 10), /*!< adc3 periph clock */
+ CRM_SPI1_PERIPH_CLOCK = MAKE_VALUE(0x44, 12), /*!< spi1 periph clock */
+ CRM_SPI4_PERIPH_CLOCK = MAKE_VALUE(0x44, 13), /*!< spi4 periph clock */
+ CRM_SCFG_PERIPH_CLOCK = MAKE_VALUE(0x44, 14), /*!< scfg periph clock */
+ CRM_TMR9_PERIPH_CLOCK = MAKE_VALUE(0x44, 16), /*!< tmr9 periph clock */
+ CRM_TMR10_PERIPH_CLOCK = MAKE_VALUE(0x44, 17), /*!< tmr10 periph clock */
+ CRM_TMR11_PERIPH_CLOCK = MAKE_VALUE(0x44, 18), /*!< tmr11 periph clock */
+ CRM_TMR20_PERIPH_CLOCK = MAKE_VALUE(0x44, 20), /*!< tmr20 periph clock */
+ CRM_ACC_PERIPH_CLOCK = MAKE_VALUE(0x44, 29) /*!< acc periph clock */
+#endif
+
+} crm_periph_clock_type;
+
+/**
+ * @brief crm periph reset
+ */
+typedef enum
+{
+#if defined (AT32F435xx)
+ /* ahb periph1 */
+ CRM_GPIOA_PERIPH_RESET = MAKE_VALUE(0x10, 0), /*!< gpioa periph reset */
+ CRM_GPIOB_PERIPH_RESET = MAKE_VALUE(0x10, 1), /*!< gpiob periph reset */
+ CRM_GPIOC_PERIPH_RESET = MAKE_VALUE(0x10, 2), /*!< gpioc periph reset */
+ CRM_GPIOD_PERIPH_RESET = MAKE_VALUE(0x10, 3), /*!< gpiod periph reset */
+ CRM_GPIOE_PERIPH_RESET = MAKE_VALUE(0x10, 4), /*!< gpioe periph reset */
+ CRM_GPIOF_PERIPH_RESET = MAKE_VALUE(0x10, 5), /*!< gpiof periph reset */
+ CRM_GPIOG_PERIPH_RESET = MAKE_VALUE(0x10, 6), /*!< gpiog periph reset */
+ CRM_GPIOH_PERIPH_RESET = MAKE_VALUE(0x10, 7), /*!< gpioh periph reset */
+ CRM_CRC_PERIPH_RESET = MAKE_VALUE(0x10, 12), /*!< crc periph reset */
+ CRM_EDMA_PERIPH_RESET = MAKE_VALUE(0x10, 21), /*!< edma periph reset */
+ CRM_DMA1_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< dma1 periph reset */
+ CRM_DMA2_PERIPH_RESET = MAKE_VALUE(0x10, 24), /*!< dma2 periph reset */
+ CRM_OTGFS2_PERIPH_RESET = MAKE_VALUE(0x10, 29), /*!< otgfs2 periph reset */
+ /* ahb periph2 */
+ CRM_DVP_PERIPH_RESET = MAKE_VALUE(0x14, 0), /*!< dvp periph reset */
+ CRM_OTGFS1_PERIPH_RESET = MAKE_VALUE(0x14, 7), /*!< otgfs1 periph reset */
+ CRM_SDIO1_PERIPH_RESET = MAKE_VALUE(0x14, 15), /*!< sdio1 periph reset */
+ /* ahb periph3 */
+ CRM_XMC_PERIPH_RESET = MAKE_VALUE(0x18, 0), /*!< xmc periph reset */
+ CRM_QSPI1_PERIPH_RESET = MAKE_VALUE(0x18, 1), /*!< qspi1 periph reset */
+ CRM_QSPI2_PERIPH_RESET = MAKE_VALUE(0x18, 14), /*!< qspi2 periph reset */
+ CRM_SDIO2_PERIPH_RESET = MAKE_VALUE(0x18, 15), /*!< sdio2 periph reset */
+ /* apb1 periph */
+ CRM_TMR2_PERIPH_RESET = MAKE_VALUE(0x20, 0), /*!< tmr2 periph reset */
+ CRM_TMR3_PERIPH_RESET = MAKE_VALUE(0x20, 1), /*!< tmr3 periph reset */
+ CRM_TMR4_PERIPH_RESET = MAKE_VALUE(0x20, 2), /*!< tmr4 periph reset */
+ CRM_TMR5_PERIPH_RESET = MAKE_VALUE(0x20, 3), /*!< tmr5 periph reset */
+ CRM_TMR6_PERIPH_RESET = MAKE_VALUE(0x20, 4), /*!< tmr6 periph reset */
+ CRM_TMR7_PERIPH_RESET = MAKE_VALUE(0x20, 5), /*!< tmr7 periph reset */
+ CRM_TMR12_PERIPH_RESET = MAKE_VALUE(0x20, 6), /*!< tmr12 periph reset */
+ CRM_TMR13_PERIPH_RESET = MAKE_VALUE(0x20, 7), /*!< tmr13 periph reset */
+ CRM_TMR14_PERIPH_RESET = MAKE_VALUE(0x20, 8), /*!< tmr14 periph reset */
+ CRM_WWDT_PERIPH_RESET = MAKE_VALUE(0x20, 11), /*!< wwdt periph reset */
+ CRM_SPI2_PERIPH_RESET = MAKE_VALUE(0x20, 14), /*!< spi2 periph reset */
+ CRM_SPI3_PERIPH_RESET = MAKE_VALUE(0x20, 15), /*!< spi3 periph reset */
+ CRM_USART2_PERIPH_RESET = MAKE_VALUE(0x20, 17), /*!< usart2 periph reset */
+ CRM_USART3_PERIPH_RESET = MAKE_VALUE(0x20, 18), /*!< usart3 periph reset */
+ CRM_UART4_PERIPH_RESET = MAKE_VALUE(0x20, 19), /*!< uart4 periph reset */
+ CRM_UART5_PERIPH_RESET = MAKE_VALUE(0x20, 20), /*!< uart5 periph reset */
+ CRM_I2C1_PERIPH_RESET = MAKE_VALUE(0x20, 21), /*!< i2c1 periph reset */
+ CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x20, 22), /*!< i2c2 periph reset */
+ CRM_I2C3_PERIPH_RESET = MAKE_VALUE(0x20, 23), /*!< i2c3 periph reset */
+ CRM_CAN1_PERIPH_RESET = MAKE_VALUE(0x20, 25), /*!< can1 periph reset */
+ CRM_CAN2_PERIPH_RESET = MAKE_VALUE(0x20, 26), /*!< can2 periph reset */
+ CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x20, 28), /*!< pwc periph reset */
+ CRM_DAC_PERIPH_RESET = MAKE_VALUE(0x20, 29), /*!< dac periph reset */
+ CRM_UART7_PERIPH_RESET = MAKE_VALUE(0x20, 30), /*!< uart7 periph reset */
+ CRM_UART8_PERIPH_RESET = MAKE_VALUE(0x20, 31), /*!< uart8 periph reset */
+ /* apb2 periph */
+ CRM_TMR1_PERIPH_RESET = MAKE_VALUE(0x24, 0), /*!< tmr1 periph reset */
+ CRM_TMR8_PERIPH_RESET = MAKE_VALUE(0x24, 1), /*!< tmr8 periph reset */
+ CRM_USART1_PERIPH_RESET = MAKE_VALUE(0x24, 4), /*!< usart1 periph reset */
+ CRM_USART6_PERIPH_RESET = MAKE_VALUE(0x24, 5), /*!< usart6 periph reset */
+ CRM_ADC_PERIPH_RESET = MAKE_VALUE(0x24, 8), /*!< adc periph reset */
+ CRM_SPI1_PERIPH_RESET = MAKE_VALUE(0x24, 12), /*!< spi1 periph reset */
+ CRM_SPI4_PERIPH_RESET = MAKE_VALUE(0x24, 13), /*!< spi4 periph reset */
+ CRM_SCFG_PERIPH_RESET = MAKE_VALUE(0x24, 14), /*!< scfg periph reset */
+ CRM_TMR9_PERIPH_RESET = MAKE_VALUE(0x24, 16), /*!< tmr9 periph reset */
+ CRM_TMR10_PERIPH_RESET = MAKE_VALUE(0x24, 17), /*!< tmr10 periph reset */
+ CRM_TMR11_PERIPH_RESET = MAKE_VALUE(0x24, 18), /*!< tmr11 periph reset */
+ CRM_TMR20_PERIPH_RESET = MAKE_VALUE(0x24, 20), /*!< tmr20 periph reset */
+ CRM_ACC_PERIPH_RESET = MAKE_VALUE(0x24, 29) /*!< acc periph reset */
+#endif
+
+#if defined (AT32F437xx)
+ /* ahb periph1 */
+ CRM_GPIOA_PERIPH_RESET = MAKE_VALUE(0x10, 0), /*!< gpioa periph reset */
+ CRM_GPIOB_PERIPH_RESET = MAKE_VALUE(0x10, 1), /*!< gpiob periph reset */
+ CRM_GPIOC_PERIPH_RESET = MAKE_VALUE(0x10, 2), /*!< gpioc periph reset */
+ CRM_GPIOD_PERIPH_RESET = MAKE_VALUE(0x10, 3), /*!< gpiod periph reset */
+ CRM_GPIOE_PERIPH_RESET = MAKE_VALUE(0x10, 4), /*!< gpioe periph reset */
+ CRM_GPIOF_PERIPH_RESET = MAKE_VALUE(0x10, 5), /*!< gpiof periph reset */
+ CRM_GPIOG_PERIPH_RESET = MAKE_VALUE(0x10, 6), /*!< gpiog periph reset */
+ CRM_GPIOH_PERIPH_RESET = MAKE_VALUE(0x10, 7), /*!< gpioh periph reset */
+ CRM_CRC_PERIPH_RESET = MAKE_VALUE(0x10, 12), /*!< crc periph reset */
+ CRM_EDMA_PERIPH_RESET = MAKE_VALUE(0x10, 21), /*!< edma periph reset */
+ CRM_DMA1_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< dma1 periph reset */
+ CRM_DMA2_PERIPH_RESET = MAKE_VALUE(0x10, 24), /*!< dma2 periph reset */
+ CRM_EMAC_PERIPH_RESET = MAKE_VALUE(0x10, 25), /*!< emac periph reset */
+ CRM_OTGFS2_PERIPH_RESET = MAKE_VALUE(0x10, 29), /*!< otgfs2 periph reset */
+ /* ahb periph2 */
+ CRM_DVP_PERIPH_RESET = MAKE_VALUE(0x14, 0), /*!< dvp periph reset */
+ CRM_OTGFS1_PERIPH_RESET = MAKE_VALUE(0x14, 7), /*!< otgfs1 periph reset */
+ CRM_SDIO1_PERIPH_RESET = MAKE_VALUE(0x14, 15), /*!< sdio1 periph reset */
+ /* ahb periph3 */
+ CRM_XMC_PERIPH_RESET = MAKE_VALUE(0x18, 0), /*!< xmc periph reset */
+ CRM_QSPI1_PERIPH_RESET = MAKE_VALUE(0x18, 1), /*!< qspi1 periph reset */
+ CRM_QSPI2_PERIPH_RESET = MAKE_VALUE(0x18, 14), /*!< qspi2 periph reset */
+ CRM_SDIO2_PERIPH_RESET = MAKE_VALUE(0x18, 15), /*!< sdio2 periph reset */
+ /* apb1 periph */
+ CRM_TMR2_PERIPH_RESET = MAKE_VALUE(0x20, 0), /*!< tmr2 periph reset */
+ CRM_TMR3_PERIPH_RESET = MAKE_VALUE(0x20, 1), /*!< tmr3 periph reset */
+ CRM_TMR4_PERIPH_RESET = MAKE_VALUE(0x20, 2), /*!< tmr4 periph reset */
+ CRM_TMR5_PERIPH_RESET = MAKE_VALUE(0x20, 3), /*!< tmr5 periph reset */
+ CRM_TMR6_PERIPH_RESET = MAKE_VALUE(0x20, 4), /*!< tmr6 periph reset */
+ CRM_TMR7_PERIPH_RESET = MAKE_VALUE(0x20, 5), /*!< tmr7 periph reset */
+ CRM_TMR12_PERIPH_RESET = MAKE_VALUE(0x20, 6), /*!< tmr12 periph reset */
+ CRM_TMR13_PERIPH_RESET = MAKE_VALUE(0x20, 7), /*!< tmr13 periph reset */
+ CRM_TMR14_PERIPH_RESET = MAKE_VALUE(0x20, 8), /*!< tmr14 periph reset */
+ CRM_WWDT_PERIPH_RESET = MAKE_VALUE(0x20, 11), /*!< wwdt periph reset */
+ CRM_SPI2_PERIPH_RESET = MAKE_VALUE(0x20, 14), /*!< spi2 periph reset */
+ CRM_SPI3_PERIPH_RESET = MAKE_VALUE(0x20, 15), /*!< spi3 periph reset */
+ CRM_USART2_PERIPH_RESET = MAKE_VALUE(0x20, 17), /*!< usart2 periph reset */
+ CRM_USART3_PERIPH_RESET = MAKE_VALUE(0x20, 18), /*!< usart3 periph reset */
+ CRM_UART4_PERIPH_RESET = MAKE_VALUE(0x20, 19), /*!< uart4 periph reset */
+ CRM_UART5_PERIPH_RESET = MAKE_VALUE(0x20, 20), /*!< uart5 periph reset */
+ CRM_I2C1_PERIPH_RESET = MAKE_VALUE(0x20, 21), /*!< i2c1 periph reset */
+ CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x20, 22), /*!< i2c2 periph reset */
+ CRM_I2C3_PERIPH_RESET = MAKE_VALUE(0x20, 23), /*!< i2c3 periph reset */
+ CRM_CAN1_PERIPH_RESET = MAKE_VALUE(0x20, 25), /*!< can1 periph reset */
+ CRM_CAN2_PERIPH_RESET = MAKE_VALUE(0x20, 26), /*!< can2 periph reset */
+ CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x20, 28), /*!< pwc periph reset */
+ CRM_DAC_PERIPH_RESET = MAKE_VALUE(0x20, 29), /*!< dac periph reset */
+ CRM_UART7_PERIPH_RESET = MAKE_VALUE(0x20, 30), /*!< uart7 periph reset */
+ CRM_UART8_PERIPH_RESET = MAKE_VALUE(0x20, 31), /*!< uart8 periph reset */
+ /* apb2 periph */
+ CRM_TMR1_PERIPH_RESET = MAKE_VALUE(0x24, 0), /*!< tmr1 periph reset */
+ CRM_TMR8_PERIPH_RESET = MAKE_VALUE(0x24, 1), /*!< tmr8 periph reset */
+ CRM_USART1_PERIPH_RESET = MAKE_VALUE(0x24, 4), /*!< usart1 periph reset */
+ CRM_USART6_PERIPH_RESET = MAKE_VALUE(0x24, 5), /*!< usart6 periph reset */
+ CRM_ADC_PERIPH_RESET = MAKE_VALUE(0x24, 8), /*!< adc periph reset */
+ CRM_SPI1_PERIPH_RESET = MAKE_VALUE(0x24, 12), /*!< spi1 periph reset */
+ CRM_SPI4_PERIPH_RESET = MAKE_VALUE(0x24, 13), /*!< spi4 periph reset */
+ CRM_SCFG_PERIPH_RESET = MAKE_VALUE(0x24, 14), /*!< scfg periph reset */
+ CRM_TMR9_PERIPH_RESET = MAKE_VALUE(0x24, 16), /*!< tmr9 periph reset */
+ CRM_TMR10_PERIPH_RESET = MAKE_VALUE(0x24, 17), /*!< tmr10 periph reset */
+ CRM_TMR11_PERIPH_RESET = MAKE_VALUE(0x24, 18), /*!< tmr11 periph reset */
+ CRM_TMR20_PERIPH_RESET = MAKE_VALUE(0x24, 20), /*!< tmr20 periph reset */
+ CRM_ACC_PERIPH_RESET = MAKE_VALUE(0x24, 29) /*!< acc periph reset */
+#endif
+
+} crm_periph_reset_type;
+
+/**
+ * @brief crm periph clock in low power mode
+ */
+typedef enum
+{
+#if defined (AT32F435xx)
+ /* ahb periph1 */
+ CRM_GPIOA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 0), /*!< gpioa sleep mode periph clock */
+ CRM_GPIOB_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 1), /*!< gpiob sleep mode periph clock */
+ CRM_GPIOC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 2), /*!< gpioc sleep mode periph clock */
+ CRM_GPIOD_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 3), /*!< gpiod sleep mode periph clock */
+ CRM_GPIOE_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 4), /*!< gpioe sleep mode periph clock */
+ CRM_GPIOF_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 5), /*!< gpiof sleep mode periph clock */
+ CRM_GPIOG_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 6), /*!< gpiog sleep mode periph clock */
+ CRM_GPIOH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 7), /*!< gpioh sleep mode periph clock */
+ CRM_CRC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 12), /*!< crc sleep mode periph clock */
+ CRM_EDMA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 21), /*!< edma sleep mode periph clock */
+ CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */
+ CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */
+ CRM_EMAC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 25), /*!< emac sleep mode periph clock */
+ CRM_EMACTX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 26), /*!< emac tx sleep mode periph clock */
+ CRM_EMACRX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 27), /*!< emac rx sleep mode periph clock */
+ CRM_EMACPTP_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 28), /*!< emac ptp sleep mode periph clock */
+ CRM_OTGFS2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 29), /*!< otgfs2 sleep mode periph clock */
+ /* ahb periph2 */
+ CRM_DVP_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 0), /*!< dvp sleep mode periph clock */
+ CRM_OTGFS1_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 7), /*!< otgfs1 sleep mode periph clock */
+ CRM_SDIO1_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 15), /*!< sdio1 sleep mode periph clock */
+ /* ahb periph3 */
+ CRM_XMC_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 0), /*!< xmc sleep mode periph clock */
+ CRM_QSPI1_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 1), /*!< qspi1 sleep mode periph clock */
+ CRM_QSPI2_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 14), /*!< qspi2 sleep mode periph clock */
+ CRM_SDIO2_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 15), /*!< sdio2 sleep mode periph clock */
+ /* apb1 periph */
+ CRM_TMR2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 0), /*!< tmr2 sleep mode periph clock */
+ CRM_TMR3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 1), /*!< tmr3 sleep mode periph clock */
+ CRM_TMR4_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 2), /*!< tmr4 sleep mode periph clock */
+ CRM_TMR5_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 3), /*!< tmr5 sleep mode periph clock */
+ CRM_TMR6_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 4), /*!< tmr6 sleep mode periph clock */
+ CRM_TMR7_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 5), /*!< tmr7 sleep mode periph clock */
+ CRM_TMR12_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 6), /*!< tmr12 sleep mode periph clock */
+ CRM_TMR13_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 7), /*!< tmr13 sleep mode periph clock */
+ CRM_TMR14_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 8), /*!< tmr14 sleep mode periph clock */
+ CRM_WWDT_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 11), /*!< wwdt sleep mode periph clock */
+ CRM_SPI2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 14), /*!< spi2 sleep mode periph clock */
+ CRM_SPI3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 15), /*!< spi3 sleep mode periph clock */
+ CRM_USART2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 17), /*!< usart2 sleep mode periph clock */
+ CRM_USART3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 18), /*!< usart3 sleep mode periph clock */
+ CRM_UART4_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 19), /*!< uart4 sleep mode periph clock */
+ CRM_UART5_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 20), /*!< uart5 sleep mode periph clock */
+ CRM_I2C1_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 21), /*!< i2c1 sleep mode periph clock */
+ CRM_I2C2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 22), /*!< i2c2 sleep mode periph clock */
+ CRM_I2C3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 23), /*!< i2c3 sleep mode periph clock */
+ CRM_CAN1_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 25), /*!< can1 sleep mode periph clock */
+ CRM_CAN2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 26), /*!< can2 sleep mode periph clock */
+ CRM_PWC_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 28), /*!< pwc sleep mode periph clock */
+ CRM_DAC_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 29), /*!< dac sleep mode periph clock */
+ CRM_UART7_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 30), /*!< uart7 sleep mode periph clock */
+ CRM_UART8_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 31), /*!< uart8 sleep mode periph clock */
+ /* apb2 periph */
+ CRM_TMR1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 0), /*!< tmr1 sleep mode periph clock */
+ CRM_TMR8_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 1), /*!< tmr8 sleep mode periph clock */
+ CRM_USART1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 4), /*!< usart1 sleep mode periph clock */
+ CRM_USART6_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 5), /*!< usart6 sleep mode periph clock */
+ CRM_ADC1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 8), /*!< adc1 sleep mode periph clock */
+ CRM_ADC2_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 9), /*!< adc2 sleep mode periph clock */
+ CRM_ADC3_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 10), /*!< adc3 sleep mode periph clock */
+ CRM_SPI1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 12), /*!< spi1 sleep mode periph clock */
+ CRM_SPI4_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 13), /*!< spi4 sleep mode periph clock */
+ CRM_SCFG_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 14), /*!< scfg sleep mode periph clock */
+ CRM_TMR9_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 16), /*!< tmr9 sleep mode periph clock */
+ CRM_TMR10_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 17), /*!< tmr10 sleep mode periph clock */
+ CRM_TMR11_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 18), /*!< tmr11 sleep mode periph clock */
+ CRM_TMR20_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 20), /*!< tmr20 sleep mode periph clock */
+ CRM_ACC_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 29) /*!< acc sleep mode periph clock */
+#endif
+
+#if defined (AT32F437xx)
+ /* ahb periph1 */
+ CRM_GPIOA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 0), /*!< gpioa sleep mode periph clock */
+ CRM_GPIOB_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 1), /*!< gpiob sleep mode periph clock */
+ CRM_GPIOC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 2), /*!< gpioc sleep mode periph clock */
+ CRM_GPIOD_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 3), /*!< gpiod sleep mode periph clock */
+ CRM_GPIOE_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 4), /*!< gpioe sleep mode periph clock */
+ CRM_GPIOF_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 5), /*!< gpiof sleep mode periph clock */
+ CRM_GPIOG_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 6), /*!< gpiog sleep mode periph clock */
+ CRM_GPIOH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 7), /*!< gpioh sleep mode periph clock */
+ CRM_CRC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 12), /*!< crc sleep mode periph clock */
+ CRM_EDMA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 21), /*!< edma sleep mode periph clock */
+ CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */
+ CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */
+ CRM_OTGFS2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 29), /*!< otgfs2 sleep mode periph clock */
+ /* ahb periph2 */
+ CRM_DVP_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 0), /*!< dvp sleep mode periph clock */
+ CRM_OTGFS1_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 7), /*!< otgfs1 sleep mode periph clock */
+ CRM_SDIO1_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 15), /*!< sdio1 sleep mode periph clock */
+ /* ahb periph3 */
+ CRM_XMC_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 0), /*!< xmc sleep mode periph clock */
+ CRM_QSPI1_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 1), /*!< qspi1 sleep mode periph clock */
+ CRM_QSPI2_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 14), /*!< qspi2 sleep mode periph clock */
+ CRM_SDIO2_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 15), /*!< sdio2 sleep mode periph clock */
+ /* apb1 periph */
+ CRM_TMR2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 0), /*!< tmr2 sleep mode periph clock */
+ CRM_TMR3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 1), /*!< tmr3 sleep mode periph clock */
+ CRM_TMR4_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 2), /*!< tmr4 sleep mode periph clock */
+ CRM_TMR5_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 3), /*!< tmr5 sleep mode periph clock */
+ CRM_TMR6_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 4), /*!< tmr6 sleep mode periph clock */
+ CRM_TMR7_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 5), /*!< tmr7 sleep mode periph clock */
+ CRM_TMR12_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 6), /*!< tmr12 sleep mode periph clock */
+ CRM_TMR13_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 7), /*!< tmr13 sleep mode periph clock */
+ CRM_TMR14_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 8), /*!< tmr14 sleep mode periph clock */
+ CRM_WWDT_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 11), /*!< wwdt sleep mode periph clock */
+ CRM_SPI2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 14), /*!< spi2 sleep mode periph clock */
+ CRM_SPI3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 15), /*!< spi3 sleep mode periph clock */
+ CRM_USART2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 17), /*!< usart2 sleep mode periph clock */
+ CRM_USART3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 18), /*!< usart3 sleep mode periph clock */
+ CRM_UART4_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 19), /*!< uart4 sleep mode periph clock */
+ CRM_UART5_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 20), /*!< uart5 sleep mode periph clock */
+ CRM_I2C1_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 21), /*!< i2c1 sleep mode periph clock */
+ CRM_I2C2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 22), /*!< i2c2 sleep mode periph clock */
+ CRM_I2C3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 23), /*!< i2c3 sleep mode periph clock */
+ CRM_CAN1_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 25), /*!< can1 sleep mode periph clock */
+ CRM_CAN2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 26), /*!< can2 sleep mode periph clock */
+ CRM_PWC_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 28), /*!< pwc sleep mode periph clock */
+ CRM_DAC_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 29), /*!< dac sleep mode periph clock */
+ CRM_UART7_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 30), /*!< uart7 sleep mode periph clock */
+ CRM_UART8_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 31), /*!< uart8 sleep mode periph clock */
+ /* apb2 periph */
+ CRM_TMR1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 0), /*!< tmr1 sleep mode periph clock */
+ CRM_TMR8_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 1), /*!< tmr8 sleep mode periph clock */
+ CRM_USART1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 4), /*!< usart1 sleep mode periph clock */
+ CRM_USART6_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 5), /*!< usart6 sleep mode periph clock */
+ CRM_ADC1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 8), /*!< adc1 sleep mode periph clock */
+ CRM_ADC2_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 9), /*!< adc2 sleep mode periph clock */
+ CRM_ADC3_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 10), /*!< adc3 sleep mode periph clock */
+ CRM_SPI1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 12), /*!< spi1 sleep mode periph clock */
+ CRM_SPI4_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 13), /*!< spi4 sleep mode periph clock */
+ CRM_SCFG_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 14), /*!< scfg sleep mode periph clock */
+ CRM_TMR9_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 16), /*!< tmr9 sleep mode periph clock */
+ CRM_TMR10_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 17), /*!< tmr10 sleep mode periph clock */
+ CRM_TMR11_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 18), /*!< tmr11 sleep mode periph clock */
+ CRM_TMR20_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 20), /*!< tmr20 sleep mode periph clock */
+ CRM_ACC_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 29) /*!< acc sleep mode periph clock */
+#endif
+
+} crm_periph_clock_lowpower_type;
+
+/**
+ * @brief crm pll clock source
+ */
+typedef enum
+{
+ CRM_PLL_SOURCE_HICK = 0x00, /*!< high speed internal clock as pll reference clock source */
+ CRM_PLL_SOURCE_HEXT = 0x01 /*!< high speed external crystal as pll reference clock source */
+} crm_pll_clock_source_type;
+
+/**
+ * @brief crm pll fr
+ */
+typedef enum
+{
+ CRM_PLL_FR_1 = 0x00, /*!< pll post-division div1 */
+ CRM_PLL_FR_2 = 0x01, /*!< pll post-division div2 */
+ CRM_PLL_FR_4 = 0x02, /*!< pll post-division div4 */
+ CRM_PLL_FR_8 = 0x03, /*!< pll post-division div8 */
+ CRM_PLL_FR_16 = 0x04, /*!< pll post-division div16 */
+ CRM_PLL_FR_32 = 0x05 /*!< pll post-division div32 */
+} crm_pll_fr_type;
+
+/**
+ * @brief crm clock source
+ */
+typedef enum
+{
+ CRM_CLOCK_SOURCE_HICK = 0x00, /*!< high speed internal clock */
+ CRM_CLOCK_SOURCE_HEXT = 0x01, /*!< high speed external crystal */
+ CRM_CLOCK_SOURCE_PLL = 0x02, /*!< phase locking loop */
+ CRM_CLOCK_SOURCE_LEXT = 0x03, /*!< low speed external crystal */
+ CRM_CLOCK_SOURCE_LICK = 0x04 /*!< low speed internal clock */
+} crm_clock_source_type;
+
+/**
+ * @brief crm ahb division
+ */
+typedef enum
+{
+ CRM_AHB_DIV_1 = 0x00, /*!< sclk div1 to ahbclk */
+ CRM_AHB_DIV_2 = 0x08, /*!< sclk div2 to ahbclk */
+ CRM_AHB_DIV_4 = 0x09, /*!< sclk div4 to ahbclk */
+ CRM_AHB_DIV_8 = 0x0A, /*!< sclk div8 to ahbclk */
+ CRM_AHB_DIV_16 = 0x0B, /*!< sclk div16 to ahbclk */
+ CRM_AHB_DIV_64 = 0x0C, /*!< sclk div64 to ahbclk */
+ CRM_AHB_DIV_128 = 0x0D, /*!< sclk div128 to ahbclk */
+ CRM_AHB_DIV_256 = 0x0E, /*!< sclk div256 to ahbclk */
+ CRM_AHB_DIV_512 = 0x0F /*!< sclk div512 to ahbclk */
+} crm_ahb_div_type;
+
+/**
+ * @brief crm apb1 division
+ */
+typedef enum
+{
+ CRM_APB1_DIV_1 = 0x00, /*!< ahbclk div1 to apb1clk */
+ CRM_APB1_DIV_2 = 0x04, /*!< ahbclk div2 to apb1clk */
+ CRM_APB1_DIV_4 = 0x05, /*!< ahbclk div4 to apb1clk */
+ CRM_APB1_DIV_8 = 0x06, /*!< ahbclk div8 to apb1clk */
+ CRM_APB1_DIV_16 = 0x07 /*!< ahbclk div16 to apb1clk */
+} crm_apb1_div_type;
+
+/**
+ * @brief crm apb2 division
+ */
+typedef enum
+{
+ CRM_APB2_DIV_1 = 0x00, /*!< ahbclk div1 to apb2clk */
+ CRM_APB2_DIV_2 = 0x04, /*!< ahbclk div2 to apb2clk */
+ CRM_APB2_DIV_4 = 0x05, /*!< ahbclk div4 to apb2clk */
+ CRM_APB2_DIV_8 = 0x06, /*!< ahbclk div8 to apb2clk */
+ CRM_APB2_DIV_16 = 0x07 /*!< ahbclk div16 to apb2clk */
+} crm_apb2_div_type;
+
+/**
+ * @brief crm usb division
+ */
+typedef enum
+{
+ CRM_USB_DIV_1_5 = 0x00, /*!< pllclk div1.5 to usbclk */
+ CRM_USB_DIV_1 = 0x01, /*!< pllclk div1 to usbclk */
+ CRM_USB_DIV_2_5 = 0x02, /*!< pllclk div2.5 to usbclk */
+ CRM_USB_DIV_2 = 0x03, /*!< pllclk div2 to usbclk */
+ CRM_USB_DIV_3_5 = 0x04, /*!< pllclk div3.5 to usbclk */
+ CRM_USB_DIV_3 = 0x05, /*!< pllclk div3 to usbclk */
+ CRM_USB_DIV_4_5 = 0x06, /*!< pllclk div4.5 to usbclk */
+ CRM_USB_DIV_4 = 0x07, /*!< pllclk div4 to usbclk */
+ CRM_USB_DIV_5_5 = 0x08, /*!< pllclk div5.5 to usbclk */
+ CRM_USB_DIV_5 = 0x09, /*!< pllclk div5 to usbclk */
+ CRM_USB_DIV_6_5 = 0x0A, /*!< pllclk div6.5 to usbclk */
+ CRM_USB_DIV_6 = 0x0B, /*!< pllclk div6 to usbclk */
+ CRM_USB_DIV_7 = 0x0C /*!< pllclk div7 to usbclk */
+} crm_usb_div_type;
+
+/**
+ * @brief crm ertc clock
+ */
+typedef enum
+{
+ CRM_ERTC_CLOCK_NOCLK = 0x000, /*!< no clock as ertc clock source */
+ CRM_ERTC_CLOCK_LEXT = 0x001, /*!< low speed external crystal as ertc clock source */
+ CRM_ERTC_CLOCK_LICK = 0x002, /*!< low speed internal clock as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_2 = 0x023, /*!< high speed external crystal div2 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_3 = 0x033, /*!< high speed external crystal div3 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_4 = 0x043, /*!< high speed external crystal div4 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_5 = 0x053, /*!< high speed external crystal div5 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_6 = 0x063, /*!< high speed external crystal div6 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_7 = 0x073, /*!< high speed external crystal div7 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_8 = 0x083, /*!< high speed external crystal div8 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_9 = 0x093, /*!< high speed external crystal div9 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_10 = 0x0A3, /*!< high speed external crystal div10 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_11 = 0x0B3, /*!< high speed external crystal div11 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_12 = 0x0C3, /*!< high speed external crystal div12 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_13 = 0x0D3, /*!< high speed external crystal div13 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_14 = 0x0E3, /*!< high speed external crystal div14 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_15 = 0x0F3, /*!< high speed external crystal div15 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_16 = 0x103, /*!< high speed external crystal div16 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_17 = 0x113, /*!< high speed external crystal div17 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_18 = 0x123, /*!< high speed external crystal div18 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_19 = 0x133, /*!< high speed external crystal div19 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_20 = 0x143, /*!< high speed external crystal div20 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_21 = 0x153, /*!< high speed external crystal div21 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_22 = 0x163, /*!< high speed external crystal div22 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_23 = 0x173, /*!< high speed external crystal div23 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_24 = 0x183, /*!< high speed external crystal div24 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_25 = 0x193, /*!< high speed external crystal div25 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_26 = 0x1A3, /*!< high speed external crystal div26 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_27 = 0x1B3, /*!< high speed external crystal div27 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_28 = 0x1C3, /*!< high speed external crystal div28 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_29 = 0x1D3, /*!< high speed external crystal div29 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_30 = 0x1E3, /*!< high speed external crystal div30 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_31 = 0x1F3 /*!< high speed external crystal div31 as ertc clock source */
+} crm_ertc_clock_type;
+
+/**
+ * @brief crm hick 48mhz division
+ */
+typedef enum
+{
+ CRM_HICK48_DIV6 = 0x00, /*!< fixed 8 mhz when hick is selected as sclk */
+ CRM_HICK48_NODIV = 0x01 /*!< 8 mhz or 48 mhz depend on hickdiv when hick is selected as sclk */
+} crm_hick_div_6_type;
+
+/**
+ * @brief crm sclk select
+ */
+typedef enum
+{
+ CRM_SCLK_HICK = 0x00, /*!< select high speed internal clock as sclk */
+ CRM_SCLK_HEXT = 0x01, /*!< select high speed external crystal as sclk */
+ CRM_SCLK_PLL = 0x02 /*!< select phase locking loop clock as sclk */
+} crm_sclk_type;
+
+/**
+ * @brief crm clkout index
+ */
+typedef enum
+{
+ CRM_CLKOUT_INDEX_1 = 0x00, /*!< clkout1 */
+ CRM_CLKOUT_INDEX_2 = 0x01 /*!< clkout2 */
+} crm_clkout_index_type;
+
+/**
+ * @brief crm clkout1 select
+ */
+typedef enum
+{
+ CRM_CLKOUT1_HICK = 0x00, /*!< output high speed internal clock to clkout1 pin */
+ CRM_CLKOUT1_LEXT = 0x01, /*!< output low speed external crystal to clkout1 pin */
+ CRM_CLKOUT1_HEXT = 0x02, /*!< output high speed external crystal to clkout1 pin */
+ CRM_CLKOUT1_PLL = 0x03 /*!< output phase locking loop clock to clkout1 pin */
+} crm_clkout1_select_type;
+
+/**
+ * @brief crm clkout2 select
+ */
+typedef enum
+{
+ CRM_CLKOUT2_SCLK = 0x00, /*!< output system clock to clkout2 pin */
+ CRM_CLKOUT2_HEXT = 0x02, /*!< output high speed external crystal to clkout2 pin */
+ CRM_CLKOUT2_PLL = 0x03, /*!< output phase locking loop clock to clkout2 pin */
+ CRM_CLKOUT2_USB = 0x10, /*!< output usbclk to clkout2 pin */
+ CRM_CLKOUT2_ADC = 0x11, /*!< output adcclk to clkout2 pin */
+ CRM_CLKOUT2_HICK = 0x12, /*!< output high speed internal clock to clkout2 pin */
+ CRM_CLKOUT2_LICK = 0x13, /*!< output low speed internal clock to clkout2 pin */
+ CRM_CLKOUT2_LEXT = 0x14 /*!< output low speed external crystal to clkout2 pin */
+} crm_clkout2_select_type;
+
+/**
+ * @brief crm clkout division1
+ */
+typedef enum
+{
+ CRM_CLKOUT_DIV1_1 = 0x00, /*!< clkout division1 div1 */
+ CRM_CLKOUT_DIV1_2 = 0x04, /*!< clkout division1 div2 */
+ CRM_CLKOUT_DIV1_3 = 0x05, /*!< clkout division1 div3 */
+ CRM_CLKOUT_DIV1_4 = 0x06, /*!< clkout division1 div4 */
+ CRM_CLKOUT_DIV1_5 = 0x07 /*!< clkout division1 div5 */
+} crm_clkout_div1_type;
+
+/**
+ * @brief crm clkout division2
+ */
+typedef enum
+{
+ CRM_CLKOUT_DIV2_1 = 0x00, /*!< clkout division2 div1 */
+ CRM_CLKOUT_DIV2_2 = 0x08, /*!< clkout division2 div2 */
+ CRM_CLKOUT_DIV2_4 = 0x09, /*!< clkout division2 div4 */
+ CRM_CLKOUT_DIV2_8 = 0x0A, /*!< clkout division2 div8 */
+ CRM_CLKOUT_DIV2_16 = 0x0B, /*!< clkout division2 div16 */
+ CRM_CLKOUT_DIV2_64 = 0x0C, /*!< clkout division2 div64 */
+ CRM_CLKOUT_DIV2_128 = 0x0D, /*!< clkout division2 div128 */
+ CRM_CLKOUT_DIV2_256 = 0x0E, /*!< clkout division2 div256 */
+ CRM_CLKOUT_DIV2_512 = 0x0F /*!< clkout division2 div512 */
+} crm_clkout_div2_type;
+
+/**
+ * @brief crm auto step mode
+ */
+typedef enum
+{
+ CRM_AUTO_STEP_MODE_DISABLE = 0x00, /*!< disable auto step mode */
+ CRM_AUTO_STEP_MODE_ENABLE = 0x03 /*!< enable auto step mode */
+} crm_auto_step_mode_type;
+
+/**
+ * @brief crm usb 48 mhz clock source select
+ */
+typedef enum
+{
+ CRM_USB_CLOCK_SOURCE_PLL = 0x00, /*!< select phase locking loop clock as usb clock source */
+ CRM_USB_CLOCK_SOURCE_HICK = 0x01 /*!< select high speed internal clock as usb clock source */
+} crm_usb_clock_source_type;
+
+/**
+ * @brief crm hick as system clock frequency select
+ */
+typedef enum
+{
+ CRM_HICK_SCLK_8MHZ = 0x00, /*!< fixed 8 mhz when hick is selected as sclk */
+ CRM_HICK_SCLK_48MHZ = 0x01 /*!< 8 mhz or 48 mhz depend on hickdiv when hick is selected as sclk */
+} crm_hick_sclk_frequency_type;
+
+/**
+ * @brief crm emac output pulse width
+ */
+typedef enum
+{
+ CRM_EMAC_PULSE_125MS = 0x00, /*!< emac output pulse width 125ms */
+ CRM_EMAC_PULSE_1SCLK = 0x01 /*!< emac output pulse width 1 system clock */
+} crm_emac_output_pulse_type;
+
+/**
+ * @brief crm clocks freqency structure
+ */
+typedef struct
+{
+ uint32_t sclk_freq; /*!< system clock frequency */
+ uint32_t ahb_freq; /*!< ahb bus clock frequency */
+ uint32_t apb2_freq; /*!< apb2 bus clock frequency */
+ uint32_t apb1_freq; /*!< apb1 bus clock frequency */
+} crm_clocks_freq_type;
+
+/**
+ * @brief type define crm register all
+ */
+typedef struct
+{
+ /**
+ * @brief crm ctrl register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t hicken : 1; /* [0] */
+ __IO uint32_t hickstbl : 1; /* [1] */
+ __IO uint32_t hicktrim : 6; /* [7:2] */
+ __IO uint32_t hickcal : 8; /* [15:8] */
+ __IO uint32_t hexten : 1; /* [16] */
+ __IO uint32_t hextstbl : 1; /* [17] */
+ __IO uint32_t hextbyps : 1; /* [18] */
+ __IO uint32_t cfden : 1; /* [19] */
+ __IO uint32_t reserved1 : 4; /* [23:20] */
+ __IO uint32_t pllen : 1; /* [24] */
+ __IO uint32_t pllstbl : 1; /* [25] */
+ __IO uint32_t reserved2 : 6; /* [31:26] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief crm pllcfg register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t pllcfg;
+ struct
+ {
+ __IO uint32_t pllms : 4; /* [3:0] */
+ __IO uint32_t reserved1 : 2; /* [5:4] */
+ __IO uint32_t pllns : 9; /* [14:6] */
+ __IO uint32_t reserved2 : 1; /* [15] */
+ __IO uint32_t pllfr : 3; /* [18:16] */
+ __IO uint32_t reserved3 : 3; /* [21:19] */
+ __IO uint32_t pllrcs : 1; /* [22] */
+ __IO uint32_t reserved4 : 9; /* [31:23] */
+ } pllcfg_bit;
+ };
+
+ /**
+ * @brief crm cfg register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t cfg;
+ struct
+ {
+ __IO uint32_t sclksel : 2; /* [1:0] */
+ __IO uint32_t sclksts : 2; /* [3:2] */
+ __IO uint32_t ahbdiv : 4; /* [7:4] */
+ __IO uint32_t reserved1 : 2; /* [9:8] */
+ __IO uint32_t apb1div : 3; /* [12:10] */
+ __IO uint32_t apb2div : 3; /* [15:13] */
+ __IO uint32_t ertcdiv : 5; /* [20:16] */
+ __IO uint32_t clkout1_sel : 2; /* [22:21] */
+ __IO uint32_t reserved2 : 1; /* [23] */
+ __IO uint32_t clkout1div1 : 3; /* [26:24] */
+ __IO uint32_t clkout2div1 : 3; /* [29:27] */
+ __IO uint32_t clkout2_sel1 : 2; /* [31:30] */
+ } cfg_bit;
+ };
+
+ /**
+ * @brief crm clkint register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t clkint;
+ struct
+ {
+ __IO uint32_t lickstblf : 1; /* [0] */
+ __IO uint32_t lextstblf : 1; /* [1] */
+ __IO uint32_t hickstblf : 1; /* [2] */
+ __IO uint32_t hextstblf : 1; /* [3] */
+ __IO uint32_t pllstblf : 1; /* [4] */
+ __IO uint32_t reserved1 : 2; /* [6:5] */
+ __IO uint32_t cfdf : 1; /* [7] */
+ __IO uint32_t lickstblien : 1; /* [8] */
+ __IO uint32_t lextstblien : 1; /* [9] */
+ __IO uint32_t hickstblien : 1; /* [10] */
+ __IO uint32_t hextstblien : 1; /* [11] */
+ __IO uint32_t pllstblien : 1; /* [12] */
+ __IO uint32_t reserved2 : 3; /* [15:13] */
+ __IO uint32_t lickstblfc : 1; /* [16] */
+ __IO uint32_t lextstblfc : 1; /* [17] */
+ __IO uint32_t hickstblfc : 1; /* [18] */
+ __IO uint32_t hextstblfc : 1; /* [19] */
+ __IO uint32_t pllstblfc : 1; /* [20] */
+ __IO uint32_t reserved3 : 2; /* [22:21] */
+ __IO uint32_t cfdfc : 1; /* [23] */
+ __IO uint32_t reserved4 : 8; /* [31:24] */
+ } clkint_bit;
+ };
+
+ /**
+ * @brief crm ahbrst1 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ahbrst1;
+#if defined (AT32F435xx)
+ struct
+ {
+ __IO uint32_t gpioarst : 1; /* [0] */
+ __IO uint32_t gpiobrst : 1; /* [1] */
+ __IO uint32_t gpiocrst : 1; /* [2] */
+ __IO uint32_t gpiodrst : 1; /* [3] */
+ __IO uint32_t gpioerst : 1; /* [4] */
+ __IO uint32_t gpiofrst : 1; /* [5] */
+ __IO uint32_t gpiogrst : 1; /* [6] */
+ __IO uint32_t gpiohrst : 1; /* [7] */
+ __IO uint32_t reserved1 : 4; /* [11:8] */
+ __IO uint32_t crcrst : 1; /* [12] */
+ __IO uint32_t reserved2 : 8; /* [20:13] */
+ __IO uint32_t edmarst : 1; /* [21] */
+ __IO uint32_t dma1rst : 1; /* [22] */
+ __IO uint32_t reserved3 : 1; /* [23] */
+ __IO uint32_t dma2rst : 1; /* [24] */
+ __IO uint32_t reserved4 : 4; /* [28:25] */
+ __IO uint32_t otgfs2rst : 1; /* [29] */
+ __IO uint32_t reserved5 : 2; /* [31:30] */
+ } ahbrst1_bit;
+#endif
+
+#if defined (AT32F437xx)
+ struct
+ {
+ __IO uint32_t gpioarst : 1; /* [0] */
+ __IO uint32_t gpiobrst : 1; /* [1] */
+ __IO uint32_t gpiocrst : 1; /* [2] */
+ __IO uint32_t gpiodrst : 1; /* [3] */
+ __IO uint32_t gpioerst : 1; /* [4] */
+ __IO uint32_t gpiofrst : 1; /* [5] */
+ __IO uint32_t gpiogrst : 1; /* [6] */
+ __IO uint32_t gpiohrst : 1; /* [7] */
+ __IO uint32_t reserved1 : 4; /* [11:8] */
+ __IO uint32_t crcrst : 1; /* [12] */
+ __IO uint32_t reserved2 : 8; /* [20:13] */
+ __IO uint32_t edmarst : 1; /* [21] */
+ __IO uint32_t dma1rst : 1; /* [22] */
+ __IO uint32_t reserved3 : 1; /* [23] */
+ __IO uint32_t dma2rst : 1; /* [24] */
+ __IO uint32_t emacrst : 1; /* [25] */
+ __IO uint32_t reserved4 : 3; /* [28:26] */
+ __IO uint32_t otgfs2rst : 1; /* [29] */
+ __IO uint32_t reserved5 : 2; /* [31:30] */
+ } ahbrst1_bit;
+#endif
+ };
+
+ /**
+ * @brief crm ahbrst2 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t ahbrst2;
+ struct
+ {
+ __IO uint32_t dvprst : 1; /* [0] */
+ __IO uint32_t reserved1 : 6; /* [6:1] */
+ __IO uint32_t otgfs1rst : 1; /* [7] */
+ __IO uint32_t reserved2 : 7; /* [14:8] */
+ __IO uint32_t sdio1rst : 1; /* [15] */
+ __IO uint32_t reserved3 : 16;/* [31:16] */
+ } ahbrst2_bit;
+ };
+
+ /**
+ * @brief crm ahbrst3 register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t ahbrst3;
+ struct
+ {
+ __IO uint32_t xmcrst : 1; /* [0] */
+ __IO uint32_t qspi1rst : 1; /* [1] */
+ __IO uint32_t reserved1 : 12;/* [13:2] */
+ __IO uint32_t qspi2rst : 1; /* [14] */
+ __IO uint32_t sdio2rst : 1; /* [15] */
+ __IO uint32_t reserved3 : 16;/* [31:16] */
+ } ahbrst3_bit;
+ };
+
+ /**
+ * @brief crm reserved1 register, offset:0x1C
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief crm apb1rst register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t apb1rst;
+ struct
+ {
+ __IO uint32_t tmr2rst : 1; /* [0] */
+ __IO uint32_t tmr3rst : 1; /* [1] */
+ __IO uint32_t tmr4rst : 1; /* [2] */
+ __IO uint32_t tmr5rst : 1; /* [3] */
+ __IO uint32_t tmr6rst : 1; /* [4] */
+ __IO uint32_t tmr7rst : 1; /* [5] */
+ __IO uint32_t tmr12rst : 1; /* [6] */
+ __IO uint32_t tmr13rst : 1; /* [7] */
+ __IO uint32_t adc14rst : 1; /* [8] */
+ __IO uint32_t reserved1 : 2; /* [10:9] */
+ __IO uint32_t wwdtrst : 1; /* [11] */
+ __IO uint32_t reserved2 : 2; /* [13:12] */
+ __IO uint32_t spi2rst : 1; /* [14] */
+ __IO uint32_t spi3rst : 1; /* [15] */
+ __IO uint32_t reserved3 : 1; /* [16] */
+ __IO uint32_t usart2rst : 1; /* [17] */
+ __IO uint32_t usart3rst : 1; /* [18] */
+ __IO uint32_t uart4rst : 1; /* [19] */
+ __IO uint32_t uart5rst : 1; /* [20] */
+ __IO uint32_t i2c1rst : 1; /* [21] */
+ __IO uint32_t i2c2rst : 1; /* [22] */
+ __IO uint32_t i2c3rst : 1; /* [23] */
+ __IO uint32_t reserved4 : 1; /* [24] */
+ __IO uint32_t can1rst : 1; /* [25] */
+ __IO uint32_t can2rst : 1; /* [26] */
+ __IO uint32_t reserved5 : 1; /* [27] */
+ __IO uint32_t pwcrst : 1; /* [28] */
+ __IO uint32_t dacrst : 1; /* [29] */
+ __IO uint32_t uart7rst : 1; /* [30] */
+ __IO uint32_t uart8rst : 1; /* [31] */
+ } apb1rst_bit;
+ };
+
+ /**
+ * @brief crm apb2rst register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t apb2rst;
+ struct
+ {
+ __IO uint32_t tmr1rst : 1; /* [0] */
+ __IO uint32_t tmr8rst : 1; /* [1] */
+ __IO uint32_t reserved1 : 2; /* [3:2] */
+ __IO uint32_t usart1rst : 1; /* [4] */
+ __IO uint32_t usart6rst : 1; /* [5] */
+ __IO uint32_t reserved2 : 2; /* [7:6] */
+ __IO uint32_t adcrst : 1; /* [8] */
+ __IO uint32_t reserved3 : 3; /* [11:9] */
+ __IO uint32_t spi1rst : 1; /* [12] */
+ __IO uint32_t spi4rst : 1; /* [13] */
+ __IO uint32_t scfgrst : 1; /* [14] */
+ __IO uint32_t reserved4 : 1; /* [15] */
+ __IO uint32_t tmr9rst : 1; /* [16] */
+ __IO uint32_t tmr10rst : 1; /* [17] */
+ __IO uint32_t tmr11rst : 1; /* [18] */
+ __IO uint32_t reserved5 : 1; /* [19] */
+ __IO uint32_t tmr20rst : 1; /* [20] */
+ __IO uint32_t reserved6 : 8; /* [28:21] */
+ __IO uint32_t accrst : 1; /* [29] */
+ __IO uint32_t reserved7 : 2; /* [31:30] */
+ } apb2rst_bit;
+ };
+
+ /**
+ * @brief crm reserved2 register, offset:0x28~0x2C
+ */
+ __IO uint32_t reserved2[2];
+
+ /**
+ * @brief crm ahben1 register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t ahben1;
+#if defined (AT32F435xx)
+ struct
+ {
+ __IO uint32_t gpioaen : 1; /* [0] */
+ __IO uint32_t gpioben : 1; /* [1] */
+ __IO uint32_t gpiocen : 1; /* [2] */
+ __IO uint32_t gpioden : 1; /* [3] */
+ __IO uint32_t gpioeen : 1; /* [4] */
+ __IO uint32_t gpiofen : 1; /* [5] */
+ __IO uint32_t gpiogen : 1; /* [6] */
+ __IO uint32_t gpiohen : 1; /* [7] */
+ __IO uint32_t reserved1 : 4; /* [11:8] */
+ __IO uint32_t crcen : 1; /* [12] */
+ __IO uint32_t reserved2 : 8; /* [20:13] */
+ __IO uint32_t edmaen : 1; /* [21] */
+ __IO uint32_t dma1en : 1; /* [22] */
+ __IO uint32_t reserved3 : 1; /* [23] */
+ __IO uint32_t dma2en : 1; /* [24] */
+ __IO uint32_t reserved4 : 4; /* [28:25] */
+ __IO uint32_t otgfs2en : 1; /* [29] */
+ __IO uint32_t reserved5 : 2; /* [31:30] */
+ } ahben1_bit;
+#endif
+
+#if defined (AT32F437xx)
+ struct
+ {
+ __IO uint32_t gpioaen : 1; /* [0] */
+ __IO uint32_t gpioben : 1; /* [1] */
+ __IO uint32_t gpiocen : 1; /* [2] */
+ __IO uint32_t gpioden : 1; /* [3] */
+ __IO uint32_t gpioeen : 1; /* [4] */
+ __IO uint32_t gpiofen : 1; /* [5] */
+ __IO uint32_t gpiogen : 1; /* [6] */
+ __IO uint32_t gpiohen : 1; /* [7] */
+ __IO uint32_t reserved1 : 4; /* [11:8] */
+ __IO uint32_t crcen : 1; /* [12] */
+ __IO uint32_t reserved2 : 8; /* [20:13] */
+ __IO uint32_t edmaen : 1; /* [21] */
+ __IO uint32_t dma1en : 1; /* [22] */
+ __IO uint32_t reserved3 : 1; /* [23] */
+ __IO uint32_t dma2en : 1; /* [24] */
+ __IO uint32_t emacen : 1; /* [25] */
+ __IO uint32_t reserved4 : 3; /* [28:26] */
+ __IO uint32_t otgfs2en : 1; /* [29] */
+ __IO uint32_t reserved5 : 2; /* [31:30] */
+ } ahben1_bit;
+#endif
+ };
+
+ /**
+ * @brief crm ahben2 register, offset:0x34
+ */
+ union
+ {
+ __IO uint32_t ahben2;
+ struct
+ {
+ __IO uint32_t dvpen : 1; /* [0] */
+ __IO uint32_t reserved1 : 6; /* [6:1] */
+ __IO uint32_t otgfs1en : 1; /* [7] */
+ __IO uint32_t reserved2 : 7; /* [14:8] */
+ __IO uint32_t sdio1en : 1; /* [15] */
+ __IO uint32_t reserved3 : 16;/* [31:16] */
+ } ahben2_bit;
+ };
+
+ /**
+ * @brief crm ahben3 register, offset:0x38
+ */
+ union
+ {
+ __IO uint32_t ahben3;
+ struct
+ {
+ __IO uint32_t xmcen : 1; /* [0] */
+ __IO uint32_t qspi1en : 1; /* [1] */
+ __IO uint32_t reserved1 : 12;/* [13:2] */
+ __IO uint32_t qspi2en : 1; /* [14] */
+ __IO uint32_t sdio2en : 1; /* [15] */
+ __IO uint32_t reserved3 : 16;/* [31:16] */
+ } ahben3_bit;
+ };
+
+ /**
+ * @brief crm reserved3 register, offset:0x3C
+ */
+ __IO uint32_t reserved3;
+
+ /**
+ * @brief crm apb1en register, offset:0x40
+ */
+ union
+ {
+ __IO uint32_t apb1en;
+ struct
+ {
+ __IO uint32_t tmr2en : 1; /* [0] */
+ __IO uint32_t tmr3en : 1; /* [1] */
+ __IO uint32_t tmr4en : 1; /* [2] */
+ __IO uint32_t tmr5en : 1; /* [3] */
+ __IO uint32_t tmr6en : 1; /* [4] */
+ __IO uint32_t tmr7en : 1; /* [5] */
+ __IO uint32_t tmr12en : 1; /* [6] */
+ __IO uint32_t tmr13en : 1; /* [7] */
+ __IO uint32_t adc14en : 1; /* [8] */
+ __IO uint32_t reserved1 : 2; /* [10:9] */
+ __IO uint32_t wwdten : 1; /* [11] */
+ __IO uint32_t reserved2 : 2; /* [13:12] */
+ __IO uint32_t spi2en : 1; /* [14] */
+ __IO uint32_t spi3en : 1; /* [15] */
+ __IO uint32_t reserved3 : 1; /* [16] */
+ __IO uint32_t usart2en : 1; /* [17] */
+ __IO uint32_t usart3en : 1; /* [18] */
+ __IO uint32_t uart4en : 1; /* [19] */
+ __IO uint32_t uart5en : 1; /* [20] */
+ __IO uint32_t i2c1en : 1; /* [21] */
+ __IO uint32_t i2c2en : 1; /* [22] */
+ __IO uint32_t i2c3en : 1; /* [23] */
+ __IO uint32_t reserved4 : 1; /* [24] */
+ __IO uint32_t can1en : 1; /* [25] */
+ __IO uint32_t can2en : 1; /* [26] */
+ __IO uint32_t reserved5 : 1; /* [27] */
+ __IO uint32_t pwcen : 1; /* [28] */
+ __IO uint32_t dacen : 1; /* [29] */
+ __IO uint32_t uart7en : 1; /* [30] */
+ __IO uint32_t uart8en : 1; /* [31] */
+ } apb1en_bit;
+ };
+
+ /**
+ * @brief crm apb2en register, offset:0x44
+ */
+ union
+ {
+ __IO uint32_t apb2en;
+ struct
+ {
+ __IO uint32_t tmr1en : 1; /* [0] */
+ __IO uint32_t tmr8en : 1; /* [1] */
+ __IO uint32_t reserved1 : 2; /* [3:2] */
+ __IO uint32_t usart1en : 1; /* [4] */
+ __IO uint32_t usart6en : 1; /* [5] */
+ __IO uint32_t reserved2 : 2; /* [7:6] */
+ __IO uint32_t adcen : 1; /* [8] */
+ __IO uint32_t reserved3 : 3; /* [11:9] */
+ __IO uint32_t spi1en : 1; /* [12] */
+ __IO uint32_t spi4en : 1; /* [13] */
+ __IO uint32_t scfgen : 1; /* [14] */
+ __IO uint32_t reserved4 : 1; /* [15] */
+ __IO uint32_t tmr9en : 1; /* [16] */
+ __IO uint32_t tmr10en : 1; /* [17] */
+ __IO uint32_t tmr11en : 1; /* [18] */
+ __IO uint32_t reserved5 : 1; /* [19] */
+ __IO uint32_t tmr20en : 1; /* [20] */
+ __IO uint32_t reserved6 : 8; /* [28:21] */
+ __IO uint32_t accen : 1; /* [29] */
+ __IO uint32_t reserved7 : 2; /* [31:30] */
+ } apb2en_bit;
+ };
+
+ /**
+ * @brief crm reserved4 register, offset:0x48~0x4C
+ */
+ __IO uint32_t reserved4[2];
+
+ /**
+ * @brief crm ahblpen1 register, offset:0x50
+ */
+ union
+ {
+ __IO uint32_t ahblpen1;
+#if defined (AT32F435xx)
+ struct
+ {
+ __IO uint32_t gpioalpen : 1; /* [0] */
+ __IO uint32_t gpioblpen : 1; /* [1] */
+ __IO uint32_t gpioclpen : 1; /* [2] */
+ __IO uint32_t gpiodlpen : 1; /* [3] */
+ __IO uint32_t gpioelpen : 1; /* [4] */
+ __IO uint32_t gpioflpen : 1; /* [5] */
+ __IO uint32_t gpioglpen : 1; /* [6] */
+ __IO uint32_t gpiohlpen : 1; /* [7] */
+ __IO uint32_t reserved1 : 4; /* [11:8] */
+ __IO uint32_t crclpen : 1; /* [12] */
+ __IO uint32_t reserved2 : 8; /* [20:13] */
+ __IO uint32_t edmalpen : 1; /* [21] */
+ __IO uint32_t dma1lpen : 1; /* [22] */
+ __IO uint32_t reserved3 : 1; /* [23] */
+ __IO uint32_t dma2lpen : 1; /* [24] */
+ __IO uint32_t reserved4 : 4; /* [28:25] */
+ __IO uint32_t otgfs2lpen : 1; /* [29] */
+ __IO uint32_t reserved5 : 2; /* [31:30] */
+ } ahblpen1_bit;
+#endif
+
+#if defined (AT32F437xx)
+ struct
+ {
+ __IO uint32_t gpioalpen : 1; /* [0] */
+ __IO uint32_t gpioblpen : 1; /* [1] */
+ __IO uint32_t gpioclpen : 1; /* [2] */
+ __IO uint32_t gpiodlpen : 1; /* [3] */
+ __IO uint32_t gpioelpen : 1; /* [4] */
+ __IO uint32_t gpioflpen : 1; /* [5] */
+ __IO uint32_t gpioglpen : 1; /* [6] */
+ __IO uint32_t gpiohlpen : 1; /* [7] */
+ __IO uint32_t reserved1 : 4; /* [11:8] */
+ __IO uint32_t crclpen : 1; /* [12] */
+ __IO uint32_t reserved2 : 8; /* [20:13] */
+ __IO uint32_t edmalpen : 1; /* [21] */
+ __IO uint32_t dma1lpen : 1; /* [22] */
+ __IO uint32_t reserved3 : 1; /* [23] */
+ __IO uint32_t dma2lpen : 1; /* [24] */
+ __IO uint32_t emaclpen : 1; /* [25] */
+ __IO uint32_t reserved4 : 3; /* [28:26] */
+ __IO uint32_t otgfs2lpen : 1; /* [29] */
+ __IO uint32_t reserved5 : 2; /* [31:30] */
+ } ahblpen1_bit;
+#endif
+ };
+
+ /**
+ * @brief crm ahblpen2 register, offset:0x54
+ */
+ union
+ {
+ __IO uint32_t ahblpen2;
+ struct
+ {
+ __IO uint32_t dvplpen : 1; /* [0] */
+ __IO uint32_t reserved1 : 6; /* [6:1] */
+ __IO uint32_t otgfs1lpen : 1; /* [7] */
+ __IO uint32_t reserved2 : 7; /* [14:8] */
+ __IO uint32_t sdio1lpen : 1; /* [15] */
+ __IO uint32_t reserved3 : 16;/* [31:16] */
+ } ahblpen2_bit;
+ };
+
+ /**
+ * @brief crm ahblpen3 register, offset:0x58
+ */
+ union
+ {
+ __IO uint32_t ahblpen3;
+ struct
+ {
+ __IO uint32_t xmclpen : 1; /* [0] */
+ __IO uint32_t qspi1lpen : 1; /* [1] */
+ __IO uint32_t reserved1 : 12;/* [13:2] */
+ __IO uint32_t qspi2lpen : 1; /* [14] */
+ __IO uint32_t sdio2lpen : 1; /* [15] */
+ __IO uint32_t reserved3 : 16;/* [31:16] */
+ } ahblpen3_bit;
+ };
+
+ /**
+ * @brief crm reserved5 register, offset:0x5C
+ */
+ __IO uint32_t reserved5;
+
+ /**
+ * @brief crm apb1lpen register, offset:0x60
+ */
+ union
+ {
+ __IO uint32_t apb1lpen;
+ struct
+ {
+ __IO uint32_t tmr2lpen : 1; /* [0] */
+ __IO uint32_t tmr3lpen : 1; /* [1] */
+ __IO uint32_t tmr4lpen : 1; /* [2] */
+ __IO uint32_t tmr5lpen : 1; /* [3] */
+ __IO uint32_t tmr6lpen : 1; /* [4] */
+ __IO uint32_t tmr7lpen : 1; /* [5] */
+ __IO uint32_t tmr12lpen : 1; /* [6] */
+ __IO uint32_t tmr13lpen : 1; /* [7] */
+ __IO uint32_t adc14lpen : 1; /* [8] */
+ __IO uint32_t reserved1 : 2; /* [10:9] */
+ __IO uint32_t wwdtlpen : 1; /* [11] */
+ __IO uint32_t reserved2 : 2; /* [13:12] */
+ __IO uint32_t spi2lpen : 1; /* [14] */
+ __IO uint32_t spi3lpen : 1; /* [15] */
+ __IO uint32_t reserved3 : 1; /* [16] */
+ __IO uint32_t usart2lpen : 1; /* [17] */
+ __IO uint32_t usart3lpen : 1; /* [18] */
+ __IO uint32_t uart4lpen : 1; /* [19] */
+ __IO uint32_t uart5lpen : 1; /* [20] */
+ __IO uint32_t i2c1lpen : 1; /* [21] */
+ __IO uint32_t i2c2lpen : 1; /* [22] */
+ __IO uint32_t i2c3lpen : 1; /* [23] */
+ __IO uint32_t reserved4 : 1; /* [24] */
+ __IO uint32_t can1lpen : 1; /* [25] */
+ __IO uint32_t can2lpen : 1; /* [26] */
+ __IO uint32_t reserved5 : 1; /* [27] */
+ __IO uint32_t pwclpen : 1; /* [28] */
+ __IO uint32_t daclpen : 1; /* [29] */
+ __IO uint32_t uart7lpen : 1; /* [30] */
+ __IO uint32_t uart8lpen : 1; /* [31] */
+ } apb1lpen_bit;
+ };
+
+ /**
+ * @brief crm apb2lpen register, offset:0x64
+ */
+ union
+ {
+ __IO uint32_t apb2lpen;
+ struct
+ {
+ __IO uint32_t tmr1lpen : 1; /* [0] */
+ __IO uint32_t tmr8lpen : 1; /* [1] */
+ __IO uint32_t reserved1 : 2; /* [3:2] */
+ __IO uint32_t usart1lpen : 1; /* [4] */
+ __IO uint32_t usart6lpen : 1; /* [5] */
+ __IO uint32_t reserved2 : 2; /* [7:6] */
+ __IO uint32_t adclpen : 1; /* [8] */
+ __IO uint32_t reserved3 : 3; /* [11:9] */
+ __IO uint32_t spi1lpen : 1; /* [12] */
+ __IO uint32_t spi4lpen : 1; /* [13] */
+ __IO uint32_t scfglpen : 1; /* [14] */
+ __IO uint32_t reserved4 : 1; /* [15] */
+ __IO uint32_t tmr9lpen : 1; /* [16] */
+ __IO uint32_t tmr10lpen : 1; /* [17] */
+ __IO uint32_t tmr11lpen : 1; /* [18] */
+ __IO uint32_t reserved5 : 1; /* [19] */
+ __IO uint32_t tmr20lpen : 1; /* [20] */
+ __IO uint32_t reserved6 : 8; /* [28:21] */
+ __IO uint32_t acclpen : 1; /* [29] */
+ __IO uint32_t reserved7 : 2; /* [31:30] */
+ } apb2lpen_bit;
+ };
+
+ /**
+ * @brief crm reserved6 register, offset:0x68~0x6C
+ */
+ __IO uint32_t reserved6[2];
+
+ /**
+ * @brief crm bpdc register, offset:0x70
+ */
+ union
+ {
+ __IO uint32_t bpdc;
+ struct
+ {
+ __IO uint32_t lexten : 1; /* [0] */
+ __IO uint32_t lextstbl : 1; /* [1] */
+ __IO uint32_t lextbyps : 1; /* [2] */
+ __IO uint32_t reserved1 : 5; /* [7:3] */
+ __IO uint32_t ertcsel : 2; /* [9:8] */
+ __IO uint32_t reserved2 : 5; /* [14:10] */
+ __IO uint32_t ertcen : 1; /* [15] */
+ __IO uint32_t bpdrst : 1; /* [16] */
+ __IO uint32_t reserved3 : 15;/* [31:17] */
+ } bpdc_bit;
+ };
+
+ /**
+ * @brief crm ctrlsts register, offset:0x74
+ */
+ union
+ {
+ __IO uint32_t ctrlsts;
+ struct
+ {
+ __IO uint32_t licken : 1; /* [0] */
+ __IO uint32_t lickstbl : 1; /* [1] */
+ __IO uint32_t reserved1 : 22;/* [23:2] */
+ __IO uint32_t rstfc : 1; /* [24] */
+ __IO uint32_t reserved2 : 1; /* [25] */
+ __IO uint32_t nrstf : 1; /* [26] */
+ __IO uint32_t porrstf : 1; /* [27] */
+ __IO uint32_t swrstf : 1; /* [28] */
+ __IO uint32_t wdtrstf : 1; /* [29] */
+ __IO uint32_t wwdtrstf : 1; /* [30] */
+ __IO uint32_t lprstf : 1; /* [31] */
+ } ctrlsts_bit;
+ };
+
+ /**
+ * @brief crm reserved7 register, offset:0x78~0x9C
+ */
+ __IO uint32_t reserved7[10];
+
+ /**
+ * @brief crm misc1 register, offset:0xA0
+ */
+ union
+ {
+ __IO uint32_t misc1;
+ struct
+ {
+ __IO uint32_t hickcal_key : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 4; /* [11:8] */
+ __IO uint32_t hickdiv : 1; /* [12] */
+ __IO uint32_t hick_to_usb : 1; /* [13] */
+ __IO uint32_t hick_to_sclk : 1; /* [14] */
+ __IO uint32_t reserved2 : 1; /* [15] */
+ __IO uint32_t clkout2_sel2 : 4; /* [19:16] */
+ __IO uint32_t reserved3 : 4; /* [23:20] */
+ __IO uint32_t clkout1div2 : 4; /* [27:24] */
+ __IO uint32_t clkout2div2 : 4; /* [31:28] */
+ } misc1_bit;
+ };
+
+ /**
+ * @brief crm misc2 register, offset:0xA4
+ */
+ union
+ {
+ __IO uint32_t misc2;
+ struct
+ {
+ __IO uint32_t reserved1 : 4; /* [3:0] */
+ __IO uint32_t auto_step_en : 2; /* [5:4] */
+ __IO uint32_t reserved2 : 2; /* [7:6] */
+ __IO uint32_t clk_to_tmr : 1; /* [8] */
+ __IO uint32_t emac_pps_sel : 1; /* [9] */
+ __IO uint32_t reserved3 : 2; /* [11:10] */
+ __IO uint32_t usbdiv : 4; /* [15:12] */
+ __IO uint32_t reserved4 : 16;/* [31:16] */
+ } misc2_bit;
+ };
+
+} crm_type;
+
+/**
+ * @}
+ */
+
+#define CRM ((crm_type *) CRM_BASE)
+
+/** @defgroup CRM_exported_functions
+ * @{
+ */
+
+void crm_reset(void);
+void crm_lext_bypass(confirm_state new_state);
+void crm_hext_bypass(confirm_state new_state);
+flag_status crm_flag_get(uint32_t flag);
+error_status crm_hext_stable_wait(void);
+void crm_hick_clock_trimming_set(uint8_t trim_value);
+void crm_hick_clock_calibration_set(uint8_t cali_value);
+void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state);
+void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state);
+void crm_periph_lowpower_mode_enable(crm_periph_clock_lowpower_type value, confirm_state new_state);
+void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state);
+void crm_flag_clear(uint32_t flag);
+void crm_ertc_clock_select(crm_ertc_clock_type value);
+void crm_ertc_clock_enable(confirm_state new_state);
+void crm_ahb_div_set(crm_ahb_div_type value);
+void crm_apb1_div_set(crm_apb1_div_type value);
+void crm_apb2_div_set(crm_apb2_div_type value);
+void crm_usb_clock_div_set(crm_usb_div_type value);
+void crm_clock_failure_detection_enable(confirm_state new_state);
+void crm_battery_powered_domain_reset(confirm_state new_state);
+void crm_auto_step_mode_enable(confirm_state new_state);
+void crm_hick_divider_select(crm_hick_div_6_type value);
+void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value);
+void crm_usb_clock_source_select(crm_usb_clock_source_type value);
+void crm_clkout_to_tmr10_enable(confirm_state new_state);
+void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \
+ uint16_t pll_ms, crm_pll_fr_type pll_fr);
+void crm_sysclk_switch(crm_sclk_type value);
+crm_sclk_type crm_sysclk_switch_status_get(void);
+void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct);
+void crm_clock_out1_set(crm_clkout1_select_type clkout);
+void crm_clock_out2_set(crm_clkout2_select_type clkout);
+void crm_clkout_div_set(crm_clkout_index_type index, crm_clkout_div1_type div1, crm_clkout_div2_type div2);
+void crm_emac_output_pulse_set(crm_emac_output_pulse_type width);
+void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state);
+error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint32_t target_sclk_freq, \
+ uint16_t *ret_ms, uint16_t *ret_ns, uint16_t *ret_fr);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_dac.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_dac.h
new file mode 100644
index 0000000..a7ffee6
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_dac.h
@@ -0,0 +1,394 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_dac.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 dac header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_DAC_H
+#define __AT32F435_437_DAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+#define DAC1_D1DMAUDRF ((uint32_t)(0x00002000))
+#define DAC2_D2DMAUDRF ((uint32_t)(0x20000000))
+
+/** @defgroup DAC_exported_types
+ * @{
+ */
+
+/**
+ * @brief dac select type
+ */
+typedef enum
+{
+ DAC1_SELECT = 0x01, /*!< dac1 select */
+ DAC2_SELECT = 0x02 /*!< dac2 select */
+} dac_select_type;
+
+/**
+ * @brief dac trigger type
+ */
+typedef enum
+{
+ DAC_TMR6_TRGOUT_EVENT = 0x00, /*!< dac trigger selection:timer6 trgout event */
+ DAC_TMR8_TRGOUT_EVENT = 0x01, /*!< dac trigger selection:timer8 trgout event */
+ DAC_TMR7_TRGOUT_EVENT = 0x02, /*!< dac trigger selection:timer7 trgout event */
+ DAC_TMR5_TRGOUT_EVENT = 0x03, /*!< dac trigger selection:timer5 trgout event */
+ DAC_TMR2_TRGOUT_EVENT = 0x04, /*!< dac trigger selection:timer2 trgout event */
+ DAC_TMR4_TRGOUT_EVENT = 0x05, /*!< dac trigger selection:timer4 trgout event */
+ DAC_EXTERNAL_INTERRUPT_LINE_9 = 0x06, /*!< dac trigger selection:external line9 */
+ DAC_SOFTWARE_TRIGGER = 0x07 /*!< dac trigger selection:software trigger */
+} dac_trigger_type;
+
+/**
+ * @brief dac wave type
+ */
+typedef enum
+{
+ DAC_WAVE_GENERATE_NONE = 0x00, /*!< dac wave generation disabled */
+ DAC_WAVE_GENERATE_NOISE = 0x01, /*!< dac noise wave generation enabled */
+ DAC_WAVE_GENERATE_TRIANGLE = 0x02 /*!< dac triangle wave generation enabled */
+} dac_wave_type;
+
+/**
+ * @brief dac mask amplitude type
+ */
+typedef enum
+{
+ DAC_LSFR_BIT0_AMPLITUDE_1 = 0x00, /*!< unmask bit0/ triangle amplitude equal to 1 */
+ DAC_LSFR_BIT10_AMPLITUDE_3 = 0x01, /*!< unmask bit[1:0]/ triangle amplitude equal to 3 */
+ DAC_LSFR_BIT20_AMPLITUDE_7 = 0x02, /*!< unmask bit[2:0]/ triangle amplitude equal to 7 */
+ DAC_LSFR_BIT30_AMPLITUDE_15 = 0x03, /*!< unmask bit[3:0]/ triangle amplitude equal to 15 */
+ DAC_LSFR_BIT40_AMPLITUDE_31 = 0x04, /*!< unmask bit[4:0]/ triangle amplitude equal to 31 */
+ DAC_LSFR_BIT50_AMPLITUDE_63 = 0x05, /*!< unmask bit[5:0]/ triangle amplitude equal to 63 */
+ DAC_LSFR_BIT60_AMPLITUDE_127 = 0x06, /*!< unmask bit[6:0]/ triangle amplitude equal to 127 */
+ DAC_LSFR_BIT70_AMPLITUDE_255 = 0x07, /*!< unmask bit[7:0]/ triangle amplitude equal to 255 */
+ DAC_LSFR_BIT80_AMPLITUDE_511 = 0x08, /*!< unmask bit[8:0]/ triangle amplitude equal to 511 */
+ DAC_LSFR_BIT90_AMPLITUDE_1023 = 0x09, /*!< unmask bit[9:0]/ triangle amplitude equal to 1023 */
+ DAC_LSFR_BITA0_AMPLITUDE_2047 = 0x0A, /*!< unmask bit[10:0]/ triangle amplitude equal to 2047 */
+ DAC_LSFR_BITB0_AMPLITUDE_4095 = 0x0B /*!< unmask bit[11:0]/ triangle amplitude equal to 4095 */
+} dac_mask_amplitude_type;
+
+/**
+ * @brief dac1 aligned data type
+ */
+typedef enum
+{
+ DAC1_12BIT_RIGHT = 0x40007408, /*!< dac1 12-bit data right-aligned */
+ DAC1_12BIT_LEFT = 0x4000740C, /*!< dac1 12-bit data left-aligned */
+ DAC1_8BIT_RIGHT = 0x40007410 /*!< dac1 8-bit data right-aligned */
+} dac1_aligned_data_type;
+
+/**
+ * @brief dac2 aligned data type
+ */
+typedef enum
+{
+ DAC2_12BIT_RIGHT = 0x40007414, /*!< dac2 12-bit data right-aligned */
+ DAC2_12BIT_LEFT = 0x40007418, /*!< dac2 12-bit data left-aligned */
+ DAC2_8BIT_RIGHT = 0x4000741C /*!< dac2 8-bit data right-aligned */
+} dac2_aligned_data_type;
+
+/**
+ * @brief dac dual data type
+ */
+typedef enum
+{
+ DAC_DUAL_12BIT_RIGHT = 0x40007420, /*!divr_bit.fdiv = div)
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_exported_types
+ * @{
+ */
+
+/**
+ * @brief flash usd eopb0 type
+ */
+typedef enum
+{
+ FLASH_EOPB0_SRAM_512K = 0x00, /*!< sram 512k, flash zw area 128k */
+ FLASH_EOPB0_SRAM_448K = 0x01, /*!< sram 448k, flash zw area 192k */
+ FLASH_EOPB0_SRAM_384K = 0x02, /*!< sram 384k, flash zw area 256k */
+ FLASH_EOPB0_SRAM_320K = 0x03, /*!< sram 320k, flash zw area 320k */
+ FLASH_EOPB0_SRAM_256K = 0x04, /*!< sram 256k, flash zw area 384k */
+ FLASH_EOPB0_SRAM_192K = 0x05, /*!< sram 192k, flash zw area 448k */
+ FLASH_EOPB0_SRAM_128K = 0x06 /*!< sram 128k, flash zw area 512k */
+} flash_usd_eopb0_type;
+
+/**
+ * @brief flash clock divider type
+ */
+typedef enum
+{
+ FLASH_CLOCK_DIV_2 = 0x00, /*!< flash clock divide by 2 */
+ FLASH_CLOCK_DIV_3 = 0x01, /*!< flash clock divide by 3 */
+ FLASH_CLOCK_DIV_4 = 0x02 /*!< flash clock divide by 4 */
+} flash_clock_divider_type;
+
+/**
+ * @brief flash status type
+ */
+typedef enum
+{
+ FLASH_OPERATE_BUSY = 0x00, /*!< flash status is operate busy */
+ FLASH_PROGRAM_ERROR = 0x01, /*!< flash status is program error */
+ FLASH_EPP_ERROR = 0x02, /*!< flash status is epp error */
+ FLASH_OPERATE_DONE = 0x03, /*!< flash status is operate done */
+ FLASH_OPERATE_TIMEOUT = 0x04 /*!< flash status is operate timeout */
+} flash_status_type;
+
+/**
+ * @brief type define flash register all
+ */
+typedef struct
+{
+ /**
+ * @brief flash psr register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t psr;
+ struct
+ {
+ __IO uint32_t reserved1 : 12;/* [11:0] */
+ __IO uint32_t nzw_bst : 1; /* [12] */
+ __IO uint32_t nzw_bst_sts : 1; /* [13] */
+ __IO uint32_t reserved2 : 18;/* [31:14] */
+ } psr_bit;
+ };
+
+ /**
+ * @brief flash unlock register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t unlock;
+ struct
+ {
+ __IO uint32_t ukval : 32;/* [31:0] */
+ } unlock_bit;
+ };
+
+ /**
+ * @brief flash usd unlock register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t usd_unlock;
+ struct
+ {
+ __IO uint32_t usd_ukval : 32;/* [31:0] */
+ } usd_unlock_bit;
+ };
+
+ /**
+ * @brief flash sts register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t obf : 1; /* [0] */
+ __IO uint32_t reserved1 : 1; /* [1] */
+ __IO uint32_t prgmerr : 1; /* [2] */
+ __IO uint32_t reserved2 : 1; /* [3] */
+ __IO uint32_t epperr : 1; /* [4] */
+ __IO uint32_t odf : 1; /* [5] */
+ __IO uint32_t reserved3 : 26;/* [31:6] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief flash ctrl register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t fprgm : 1; /* [0] */
+ __IO uint32_t secers : 1; /* [1] */
+ __IO uint32_t bankers : 1; /* [2] */
+ __IO uint32_t blkers : 1; /* [3] */
+ __IO uint32_t usdprgm : 1; /* [4] */
+ __IO uint32_t usders : 1; /* [5] */
+ __IO uint32_t erstr : 1; /* [6] */
+ __IO uint32_t oplk : 1; /* [7] */
+ __IO uint32_t reserved1 : 1; /* [8] */
+ __IO uint32_t usdulks : 1; /* [9] */
+ __IO uint32_t errie : 1; /* [10] */
+ __IO uint32_t reserved2 : 1; /* [11] */
+ __IO uint32_t odfie : 1; /* [12] */
+ __IO uint32_t reserved3 : 19;/* [31:13] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief flash addr register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t addr;
+ struct
+ {
+ __IO uint32_t fa : 32;/* [31:0] */
+ } addr_bit;
+ };
+
+ /**
+ * @brief flash reserved1 register, offset:0x18
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief flash usd register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t usd;
+ struct
+ {
+ __IO uint32_t usderr : 1; /* [0] */
+ __IO uint32_t fap : 1; /* [1] */
+ __IO uint32_t wdt_ato_en : 1; /* [2] */
+ __IO uint32_t depslp_rst : 1; /* [3] */
+ __IO uint32_t stdby_rst : 1; /* [4] */
+ __IO uint32_t btopt : 1; /* [5] */
+ __IO uint32_t reserved1 : 1; /* [6] */
+ __IO uint32_t wdt_depslp : 1; /* [7] */
+ __IO uint32_t wdt_stdby : 1; /* [8] */
+ __IO uint32_t reserved2 : 1; /* [9] */
+ __IO uint32_t user_d0 : 8; /* [17:10] */
+ __IO uint32_t user_d1 : 8; /* [25:18] */
+ __IO uint32_t reserved3 : 6; /* [31:26] */
+ } usd_bit;
+ };
+
+ /**
+ * @brief flash epps0 register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t epps0;
+ struct
+ {
+ __IO uint32_t epps : 32;/* [31:0] */
+ } epps0_bit;
+ };
+
+ /**
+ * @brief flash reserved2 register, offset:0x28~0x24
+ */
+ __IO uint32_t reserved2[2];
+
+ /**
+ * @brief flash epps1 register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t epps1;
+ struct
+ {
+ __IO uint32_t epps : 32;/* [31:0] */
+ } epps1_bit;
+ };
+
+ /**
+ * @brief flash reserved3 register, offset:0x40~0x30
+ */
+ __IO uint32_t reserved3[5];
+
+ /**
+ * @brief flash unlock2 register, offset:0x44
+ */
+ union
+ {
+ __IO uint32_t unlock2;
+ struct
+ {
+ __IO uint32_t ukval : 32;/* [31:0] */
+ } unlock2_bit;
+ };
+
+ /**
+ * @brief flash reserved4 register, offset:0x48
+ */
+ __IO uint32_t reserved4;
+
+ /**
+ * @brief flash sts2 register, offset:0x4C
+ */
+ union
+ {
+ __IO uint32_t sts2;
+ struct
+ {
+ __IO uint32_t obf : 1; /* [0] */
+ __IO uint32_t reserved1 : 1; /* [1] */
+ __IO uint32_t prgmerr : 1; /* [2] */
+ __IO uint32_t reserved2 : 1; /* [3] */
+ __IO uint32_t epperr : 1; /* [4] */
+ __IO uint32_t odf : 1; /* [5] */
+ __IO uint32_t reserved3 : 26;/* [31:6] */
+ } sts2_bit;
+ };
+
+ /**
+ * @brief flash ctrl2 register, offset:0x50
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t fprgm : 1; /* [0] */
+ __IO uint32_t secers : 1; /* [1] */
+ __IO uint32_t bankers : 1; /* [2] */
+ __IO uint32_t blkers : 1; /* [3] */
+ __IO uint32_t reserved1 : 2; /* [5:4] */
+ __IO uint32_t erstr : 1; /* [6] */
+ __IO uint32_t oplk : 1; /* [7] */
+ __IO uint32_t reserved2 : 2; /* [9:8] */
+ __IO uint32_t errie : 1; /* [10] */
+ __IO uint32_t reserved3 : 1; /* [11] */
+ __IO uint32_t odfie : 1; /* [12] */
+ __IO uint32_t reserved4 : 19;/* [31:13] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief flash addr2 register, offset:0x54
+ */
+ union
+ {
+ __IO uint32_t addr2;
+ struct
+ {
+ __IO uint32_t fa : 32;/* [31:0] */
+ } addr2_bit;
+ };
+
+ /**
+ * @brief flash contr register, offset:0x58
+ */
+ union
+ {
+ __IO uint32_t contr;
+ struct
+ {
+ __IO uint32_t reserved1 : 31;/* [30:0] */
+ __IO uint32_t fcontr_en : 1; /* [31] */
+ } contr_bit;
+ };
+
+ /**
+ * @brief flash reserved5 register, offset:0x5C
+ */
+ __IO uint32_t reserved5;
+
+ /**
+ * @brief flash divr register, offset:0x60
+ */
+ union
+ {
+ __IO uint32_t divr;
+ struct
+ {
+ __IO uint32_t fdiv : 2; /* [1:0] */
+ __IO uint32_t reserved1 : 2; /* [3:2] */
+ __IO uint32_t fdiv_sts : 2; /* [5:4] */
+ __IO uint32_t reserved2 : 26;/* [31:6] */
+ } divr_bit;
+ };
+
+ /**
+ * @brief flash reserved6 register, offset:0xC4~0x64
+ */
+ __IO uint32_t reserved6[25];
+
+ /**
+ * @brief flash slib_sts2 register, offset:0xC8
+ */
+ union
+ {
+ __IO uint32_t slib_sts2;
+ struct
+ {
+ __IO uint32_t slib_inst_ss : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } slib_sts2_bit;
+ };
+
+ /**
+ * @brief flash slib_sts0 register, offset:0xCC
+ */
+ union
+ {
+ __IO uint32_t slib_sts0;
+ struct
+ {
+ __IO uint32_t reserved1 : 3; /* [2:0] */
+ __IO uint32_t slib_enf : 1; /* [3] */
+ __IO uint32_t reserved2 : 28;/* [31:4] */
+ } slib_sts0_bit;
+ };
+
+ /**
+ * @brief flash slib_sts1 register, offset:0xD0
+ */
+ union
+ {
+ __IO uint32_t slib_sts1;
+ struct
+ {
+ __IO uint32_t slib_ss : 16;/* [15:0] */
+ __IO uint32_t slib_es : 16;/* [31:16] */
+ } slib_sts1_bit;
+ };
+
+ /**
+ * @brief flash slib_pwd_clr register, offset:0xD4
+ */
+ union
+ {
+ __IO uint32_t slib_pwd_clr;
+ struct
+ {
+ __IO uint32_t slib_pclr_val : 32;/* [31:0] */
+ } slib_pwd_clr_bit;
+ };
+
+ /**
+ * @brief flash slib_misc_sts register, offset:0xD8
+ */
+ union
+ {
+ __IO uint32_t slib_misc_sts;
+ struct
+ {
+ __IO uint32_t slib_pwd_err : 1; /* [0] */
+ __IO uint32_t slib_pwd_ok : 1; /* [1] */
+ __IO uint32_t slib_ulkf : 1; /* [2] */
+ __IO uint32_t reserved1 : 13;/* [15:3] */
+ __IO uint32_t slib_rcnt : 9; /* [24:16] */
+ __IO uint32_t reserved2 : 7; /* [31:25] */
+ } slib_misc_sts_bit;
+ };
+
+ /**
+ * @brief flash slib_set_pwd register, offset:0xDC
+ */
+ union
+ {
+ __IO uint32_t slib_set_pwd;
+ struct
+ {
+ __IO uint32_t slib_pset_val : 32;/* [31:0] */
+ } slib_set_pwd_bit;
+ };
+
+ /**
+ * @brief flash slib_set_range0 register, offset:0xE0
+ */
+ union
+ {
+ __IO uint32_t slib_set_range0;
+ struct
+ {
+ __IO uint32_t slib_ss_set : 16;/* [15:0] */
+ __IO uint32_t slib_es_set : 16;/* [31:16] */
+ } slib_set_range0_bit;
+ };
+
+ /**
+ * @brief flash slib_set_range1 register, offset:0xE4
+ */
+ union
+ {
+ __IO uint32_t slib_set_range1;
+ struct
+ {
+ __IO uint32_t slib_iss_set : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 15;/* [30:16] */
+ __IO uint32_t set_slib_strt : 1; /* [31] */
+ } slib_set_range1_bit;
+ };
+
+ /**
+ * @brief flash reserved7 register, offset:0xEC~0xE8
+ */
+ __IO uint32_t reserved7[2];
+
+ /**
+ * @brief flash slib_unlock register, offset:0xF0
+ */
+ union
+ {
+ __IO uint32_t slib_unlock;
+ struct
+ {
+ __IO uint32_t slib_ukval : 32;/* [31:0] */
+ } slib_unlock_bit;
+ };
+
+ /**
+ * @brief flash crc_ctrl register, offset:0xF4
+ */
+ union
+ {
+ __IO uint32_t crc_ctrl;
+ struct
+ {
+ __IO uint32_t crc_ss : 12;/* [11:0] */
+ __IO uint32_t crc_sn : 12;/* [23:12] */
+ __IO uint32_t reserved1 : 7; /* [30:24] */
+ __IO uint32_t crc_strt : 1; /* [31] */
+ } crc_ctrl_bit;
+ };
+
+ /**
+ * @brief flash crc_chkr register, offset:0xF8
+ */
+ union
+ {
+ __IO uint32_t crc_chkr;
+ struct
+ {
+ __IO uint32_t crc_chkr : 32;/* [31:0] */
+ } crc_chkr_bit;
+ };
+
+} flash_type;
+
+/**
+ * @brief user system data
+ */
+typedef struct
+{
+ __IO uint16_t fap;
+ __IO uint16_t ssb;
+ __IO uint16_t data0;
+ __IO uint16_t data1;
+ __IO uint16_t epp0;
+ __IO uint16_t epp1;
+ __IO uint16_t epp2;
+ __IO uint16_t epp3;
+ __IO uint16_t eopb0;
+ __IO uint16_t reserved1;
+ __IO uint16_t epp4;
+ __IO uint16_t epp5;
+ __IO uint16_t epp6;
+ __IO uint16_t epp7;
+ __IO uint16_t reserved2[12];
+ __IO uint16_t qspikey[8];
+} usd_type;
+
+/**
+ * @}
+ */
+
+#define FLASH ((flash_type *) FLASH_REG_BASE)
+#define USD ((usd_type *) USD_BASE)
+
+/** @defgroup FLASH_exported_functions
+ * @{
+ */
+
+flag_status flash_flag_get(uint32_t flash_flag);
+void flash_flag_clear(uint32_t flash_flag);
+flash_status_type flash_operation_status_get(void);
+flash_status_type flash_bank1_operation_status_get(void);
+flash_status_type flash_bank2_operation_status_get(void);
+flash_status_type flash_operation_wait_for(uint32_t time_out);
+flash_status_type flash_bank1_operation_wait_for(uint32_t time_out);
+flash_status_type flash_bank2_operation_wait_for(uint32_t time_out);
+void flash_unlock(void);
+void flash_bank1_unlock(void);
+void flash_bank2_unlock(void);
+void flash_lock(void);
+void flash_bank1_lock(void);
+void flash_bank2_lock(void);
+flash_status_type flash_sector_erase(uint32_t sector_address);
+flash_status_type flash_block_erase(uint32_t block_address);
+flash_status_type flash_internal_all_erase(void);
+flash_status_type flash_bank1_erase(void);
+flash_status_type flash_bank2_erase(void);
+flash_status_type flash_user_system_data_erase(void);
+flash_status_type flash_eopb0_config(flash_usd_eopb0_type data);
+flash_status_type flash_word_program(uint32_t address, uint32_t data);
+flash_status_type flash_halfword_program(uint32_t address, uint16_t data);
+flash_status_type flash_byte_program(uint32_t address, uint8_t data);
+flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data);
+flash_status_type flash_epp_set(uint32_t *sector_bits);
+void flash_epp_status_get(uint32_t *sector_bits);
+flash_status_type flash_fap_enable(confirm_state new_state);
+flag_status flash_fap_status_get(void);
+flash_status_type flash_ssb_set(uint8_t usd_ssb);
+uint8_t flash_ssb_status_get(void);
+void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state);
+flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t inst_start_sector, uint16_t end_sector);
+error_status flash_slib_disable(uint32_t pwd);
+uint32_t flash_slib_remaining_count_get(void);
+flag_status flash_slib_state_get(void);
+uint16_t flash_slib_start_sector_get(void);
+uint16_t flash_slib_inststart_sector_get(void);
+uint16_t flash_slib_end_sector_get(void);
+uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt);
+void flash_nzw_boost_enable(confirm_state new_state);
+void flash_continue_read_enable(confirm_state new_state);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_gpio.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_gpio.h
new file mode 100644
index 0000000..edc2b06
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_gpio.h
@@ -0,0 +1,565 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_gpio.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 gpio header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_GPIO_H
+#define __AT32F435_437_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/** @defgroup GPIO_pins_number_definition
+ * @{
+ */
+
+#define GPIO_PINS_0 0x0001 /*!< gpio pins number 0 */
+#define GPIO_PINS_1 0x0002 /*!< gpio pins number 1 */
+#define GPIO_PINS_2 0x0004 /*!< gpio pins number 2 */
+#define GPIO_PINS_3 0x0008 /*!< gpio pins number 3 */
+#define GPIO_PINS_4 0x0010 /*!< gpio pins number 4 */
+#define GPIO_PINS_5 0x0020 /*!< gpio pins number 5 */
+#define GPIO_PINS_6 0x0040 /*!< gpio pins number 6 */
+#define GPIO_PINS_7 0x0080 /*!< gpio pins number 7 */
+#define GPIO_PINS_8 0x0100 /*!< gpio pins number 8 */
+#define GPIO_PINS_9 0x0200 /*!< gpio pins number 9 */
+#define GPIO_PINS_10 0x0400 /*!< gpio pins number 10 */
+#define GPIO_PINS_11 0x0800 /*!< gpio pins number 11 */
+#define GPIO_PINS_12 0x1000 /*!< gpio pins number 12 */
+#define GPIO_PINS_13 0x2000 /*!< gpio pins number 13 */
+#define GPIO_PINS_14 0x4000 /*!< gpio pins number 14 */
+#define GPIO_PINS_15 0x8000 /*!< gpio pins number 15 */
+#define GPIO_PINS_ALL 0xFFFF /*!< gpio all pins */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_exported_types
+ * @{
+ */
+
+/**
+ * @brief gpio mode select
+ */
+typedef enum
+{
+ GPIO_MODE_INPUT = 0x00, /*!< gpio input mode */
+ GPIO_MODE_OUTPUT = 0x01, /*!< gpio output mode */
+ GPIO_MODE_MUX = 0x02, /*!< gpio mux function mode */
+ GPIO_MODE_ANALOG = 0x03 /*!< gpio analog in/out mode */
+} gpio_mode_type;
+
+/**
+ * @brief gpio output drive strength select
+ */
+typedef enum
+{
+ GPIO_DRIVE_STRENGTH_STRONGER = 0x01, /*!< stronger sourcing/sinking strength */
+ GPIO_DRIVE_STRENGTH_MODERATE = 0x02 /*!< moderate sourcing/sinking strength */
+} gpio_drive_type;
+
+/**
+ * @brief gpio output type
+ */
+typedef enum
+{
+ GPIO_OUTPUT_PUSH_PULL = 0x00, /*!< output push-pull */
+ GPIO_OUTPUT_OPEN_DRAIN = 0x01 /*!< output open-drain */
+} gpio_output_type;
+
+/**
+ * @brief gpio pull type
+ */
+typedef enum
+{
+ GPIO_PULL_NONE = 0x00, /*!< floating for input, no pull for output */
+ GPIO_PULL_UP = 0x01, /*!< pull-up */
+ GPIO_PULL_DOWN = 0x02 /*!< pull-down */
+} gpio_pull_type;
+
+/**
+ * @brief gpio init type
+ */
+typedef struct
+{
+ uint32_t gpio_pins; /*!< pins number selection */
+ gpio_output_type gpio_out_type; /*!< output type selection */
+ gpio_pull_type gpio_pull; /*!< pull type selection */
+ gpio_mode_type gpio_mode; /*!< mode selection */
+ gpio_drive_type gpio_drive_strength; /*!< drive strength selection */
+} gpio_init_type;
+
+/**
+ * @brief gpio pins source type
+ */
+typedef enum
+{
+ GPIO_PINS_SOURCE0 = 0x00, /*!< gpio pins source number 0 */
+ GPIO_PINS_SOURCE1 = 0x01, /*!< gpio pins source number 1 */
+ GPIO_PINS_SOURCE2 = 0x02, /*!< gpio pins source number 2 */
+ GPIO_PINS_SOURCE3 = 0x03, /*!< gpio pins source number 3 */
+ GPIO_PINS_SOURCE4 = 0x04, /*!< gpio pins source number 4 */
+ GPIO_PINS_SOURCE5 = 0x05, /*!< gpio pins source number 5 */
+ GPIO_PINS_SOURCE6 = 0x06, /*!< gpio pins source number 6 */
+ GPIO_PINS_SOURCE7 = 0x07, /*!< gpio pins source number 7 */
+ GPIO_PINS_SOURCE8 = 0x08, /*!< gpio pins source number 8 */
+ GPIO_PINS_SOURCE9 = 0x09, /*!< gpio pins source number 9 */
+ GPIO_PINS_SOURCE10 = 0x0A, /*!< gpio pins source number 10 */
+ GPIO_PINS_SOURCE11 = 0x0B, /*!< gpio pins source number 11 */
+ GPIO_PINS_SOURCE12 = 0x0C, /*!< gpio pins source number 12 */
+ GPIO_PINS_SOURCE13 = 0x0D, /*!< gpio pins source number 13 */
+ GPIO_PINS_SOURCE14 = 0x0E, /*!< gpio pins source number 14 */
+ GPIO_PINS_SOURCE15 = 0x0F /*!< gpio pins source number 15 */
+} gpio_pins_source_type;
+
+/**
+ * @brief gpio muxing function selection type
+ */
+typedef enum
+{
+ GPIO_MUX_0 = 0x00, /*!< gpio muxing function selection 0 */
+ GPIO_MUX_1 = 0x01, /*!< gpio muxing function selection 1 */
+ GPIO_MUX_2 = 0x02, /*!< gpio muxing function selection 2 */
+ GPIO_MUX_3 = 0x03, /*!< gpio muxing function selection 3 */
+ GPIO_MUX_4 = 0x04, /*!< gpio muxing function selection 4 */
+ GPIO_MUX_5 = 0x05, /*!< gpio muxing function selection 5 */
+ GPIO_MUX_6 = 0x06, /*!< gpio muxing function selection 6 */
+ GPIO_MUX_7 = 0x07, /*!< gpio muxing function selection 7 */
+ GPIO_MUX_8 = 0x08, /*!< gpio muxing function selection 8 */
+ GPIO_MUX_9 = 0x09, /*!< gpio muxing function selection 9 */
+ GPIO_MUX_10 = 0x0A, /*!< gpio muxing function selection 10 */
+ GPIO_MUX_11 = 0x0B, /*!< gpio muxing function selection 11 */
+ GPIO_MUX_12 = 0x0C, /*!< gpio muxing function selection 12 */
+ GPIO_MUX_13 = 0x0D, /*!< gpio muxing function selection 13 */
+ GPIO_MUX_14 = 0x0E, /*!< gpio muxing function selection 14 */
+ GPIO_MUX_15 = 0x0F /*!< gpio muxing function selection 15 */
+} gpio_mux_sel_type;
+
+/**
+ * @brief type define gpio register all
+ */
+typedef struct
+{
+ /**
+ * @brief gpio mode register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t cfgr;
+ struct
+ {
+ __IO uint32_t iomc0 : 2; /* [1:0] */
+ __IO uint32_t iomc1 : 2; /* [3:2] */
+ __IO uint32_t iomc2 : 2; /* [5:4] */
+ __IO uint32_t iomc3 : 2; /* [7:6] */
+ __IO uint32_t iomc4 : 2; /* [9:8] */
+ __IO uint32_t iomc5 : 2; /* [11:10] */
+ __IO uint32_t iomc6 : 2; /* [13:12] */
+ __IO uint32_t iomc7 : 2; /* [15:14] */
+ __IO uint32_t iomc8 : 2; /* [17:16] */
+ __IO uint32_t iomc9 : 2; /* [19:18] */
+ __IO uint32_t iomc10 : 2; /* [21:20] */
+ __IO uint32_t iomc11 : 2; /* [23:22] */
+ __IO uint32_t iomc12 : 2; /* [25:24] */
+ __IO uint32_t iomc13 : 2; /* [27:26] */
+ __IO uint32_t iomc14 : 2; /* [29:28] */
+ __IO uint32_t iomc15 : 2; /* [31:30] */
+ } cfgr_bit;
+ };
+
+ /**
+ * @brief gpio output type register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t omode;
+ struct
+ {
+ __IO uint32_t om0 : 1; /* [0] */
+ __IO uint32_t om1 : 1; /* [1] */
+ __IO uint32_t om2 : 1; /* [2] */
+ __IO uint32_t om3 : 1; /* [3] */
+ __IO uint32_t om4 : 1; /* [4] */
+ __IO uint32_t om5 : 1; /* [5] */
+ __IO uint32_t om6 : 1; /* [6] */
+ __IO uint32_t om7 : 1; /* [7] */
+ __IO uint32_t om8 : 1; /* [8] */
+ __IO uint32_t om9 : 1; /* [9] */
+ __IO uint32_t om10 : 1; /* [10] */
+ __IO uint32_t om11 : 1; /* [11] */
+ __IO uint32_t om12 : 1; /* [12] */
+ __IO uint32_t om13 : 1; /* [13] */
+ __IO uint32_t om14 : 1; /* [14] */
+ __IO uint32_t om15 : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } omode_bit;
+ };
+
+ /**
+ * @brief gpio output driver register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t odrvr;
+ struct
+ {
+ __IO uint32_t odrv0 : 2; /* [1:0] */
+ __IO uint32_t odrv1 : 2; /* [3:2] */
+ __IO uint32_t odrv2 : 2; /* [5:4] */
+ __IO uint32_t odrv3 : 2; /* [7:6] */
+ __IO uint32_t odrv4 : 2; /* [9:8] */
+ __IO uint32_t odrv5 : 2; /* [11:10] */
+ __IO uint32_t odrv6 : 2; /* [13:12] */
+ __IO uint32_t odrv7 : 2; /* [15:14] */
+ __IO uint32_t odrv8 : 2; /* [17:16] */
+ __IO uint32_t odrv9 : 2; /* [19:18] */
+ __IO uint32_t odrv10 : 2; /* [21:20] */
+ __IO uint32_t odrv11 : 2; /* [23:22] */
+ __IO uint32_t odrv12 : 2; /* [25:24] */
+ __IO uint32_t odrv13 : 2; /* [27:26] */
+ __IO uint32_t odrv14 : 2; /* [29:28] */
+ __IO uint32_t odrv15 : 2; /* [31:30] */
+ } odrvr_bit;
+ };
+
+ /**
+ * @brief gpio pull up/down register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t pull;
+ struct
+ {
+ __IO uint32_t pull0 : 2; /* [1:0] */
+ __IO uint32_t pull1 : 2; /* [3:2] */
+ __IO uint32_t pull2 : 2; /* [5:4] */
+ __IO uint32_t pull3 : 2; /* [7:6] */
+ __IO uint32_t pull4 : 2; /* [9:8] */
+ __IO uint32_t pull5 : 2; /* [11:10] */
+ __IO uint32_t pull6 : 2; /* [13:12] */
+ __IO uint32_t pull7 : 2; /* [15:14] */
+ __IO uint32_t pull8 : 2; /* [17:16] */
+ __IO uint32_t pull9 : 2; /* [19:18] */
+ __IO uint32_t pull10 : 2; /* [21:20] */
+ __IO uint32_t pull11 : 2; /* [23:22] */
+ __IO uint32_t pull12 : 2; /* [25:24] */
+ __IO uint32_t pull13 : 2; /* [27:26] */
+ __IO uint32_t pull14 : 2; /* [29:28] */
+ __IO uint32_t pull15 : 2; /* [31:30] */
+ } pull_bit;
+ };
+
+ /**
+ * @brief gpio input data register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t idt;
+ struct
+ {
+ __IO uint32_t idt0 : 1; /* [0] */
+ __IO uint32_t idt1 : 1; /* [1] */
+ __IO uint32_t idt2 : 1; /* [2] */
+ __IO uint32_t idt3 : 1; /* [3] */
+ __IO uint32_t idt4 : 1; /* [4] */
+ __IO uint32_t idt5 : 1; /* [5] */
+ __IO uint32_t idt6 : 1; /* [6] */
+ __IO uint32_t idt7 : 1; /* [7] */
+ __IO uint32_t idt8 : 1; /* [8] */
+ __IO uint32_t idt9 : 1; /* [9] */
+ __IO uint32_t idt10 : 1; /* [10] */
+ __IO uint32_t idt11 : 1; /* [11] */
+ __IO uint32_t idt12 : 1; /* [12] */
+ __IO uint32_t idt13 : 1; /* [13] */
+ __IO uint32_t idt14 : 1; /* [14] */
+ __IO uint32_t idt15 : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } idt_bit;
+ };
+
+ /**
+ * @brief gpio output data register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t odt;
+ struct
+ {
+ __IO uint32_t odt0 : 1; /* [0] */
+ __IO uint32_t odt1 : 1; /* [1] */
+ __IO uint32_t odt2 : 1; /* [2] */
+ __IO uint32_t odt3 : 1; /* [3] */
+ __IO uint32_t odt4 : 1; /* [4] */
+ __IO uint32_t odt5 : 1; /* [5] */
+ __IO uint32_t odt6 : 1; /* [6] */
+ __IO uint32_t odt7 : 1; /* [7] */
+ __IO uint32_t odt8 : 1; /* [8] */
+ __IO uint32_t odt9 : 1; /* [9] */
+ __IO uint32_t odt10 : 1; /* [10] */
+ __IO uint32_t odt11 : 1; /* [11] */
+ __IO uint32_t odt12 : 1; /* [12] */
+ __IO uint32_t odt13 : 1; /* [13] */
+ __IO uint32_t odt14 : 1; /* [14] */
+ __IO uint32_t odt15 : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } odt_bit;
+ };
+
+ /**
+ * @brief gpio scr register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t scr;
+ struct
+ {
+ __IO uint32_t iosb0 : 1; /* [0] */
+ __IO uint32_t iosb1 : 1; /* [1] */
+ __IO uint32_t iosb2 : 1; /* [2] */
+ __IO uint32_t iosb3 : 1; /* [3] */
+ __IO uint32_t iosb4 : 1; /* [4] */
+ __IO uint32_t iosb5 : 1; /* [5] */
+ __IO uint32_t iosb6 : 1; /* [6] */
+ __IO uint32_t iosb7 : 1; /* [7] */
+ __IO uint32_t iosb8 : 1; /* [8] */
+ __IO uint32_t iosb9 : 1; /* [9] */
+ __IO uint32_t iosb10 : 1; /* [10] */
+ __IO uint32_t iosb11 : 1; /* [11] */
+ __IO uint32_t iosb12 : 1; /* [12] */
+ __IO uint32_t iosb13 : 1; /* [13] */
+ __IO uint32_t iosb14 : 1; /* [14] */
+ __IO uint32_t iosb15 : 1; /* [15] */
+ __IO uint32_t iocb0 : 1; /* [16] */
+ __IO uint32_t iocb1 : 1; /* [17] */
+ __IO uint32_t iocb2 : 1; /* [18] */
+ __IO uint32_t iocb3 : 1; /* [19] */
+ __IO uint32_t iocb4 : 1; /* [20] */
+ __IO uint32_t iocb5 : 1; /* [21] */
+ __IO uint32_t iocb6 : 1; /* [22] */
+ __IO uint32_t iocb7 : 1; /* [23] */
+ __IO uint32_t iocb8 : 1; /* [24] */
+ __IO uint32_t iocb9 : 1; /* [25] */
+ __IO uint32_t iocb10 : 1; /* [26] */
+ __IO uint32_t iocb11 : 1; /* [27] */
+ __IO uint32_t iocb12 : 1; /* [28] */
+ __IO uint32_t iocb13 : 1; /* [29] */
+ __IO uint32_t iocb14 : 1; /* [30] */
+ __IO uint32_t iocb15 : 1; /* [31] */
+ } scr_bit;
+ };
+
+ /**
+ * @brief gpio wpen register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t wpr;
+ struct
+ {
+ __IO uint32_t wpen0 : 1; /* [0] */
+ __IO uint32_t wpen1 : 1; /* [1] */
+ __IO uint32_t wpen2 : 1; /* [2] */
+ __IO uint32_t wpen3 : 1; /* [3] */
+ __IO uint32_t wpen4 : 1; /* [4] */
+ __IO uint32_t wpen5 : 1; /* [5] */
+ __IO uint32_t wpen6 : 1; /* [6] */
+ __IO uint32_t wpen7 : 1; /* [7] */
+ __IO uint32_t wpen8 : 1; /* [8] */
+ __IO uint32_t wpen9 : 1; /* [9] */
+ __IO uint32_t wpen10 : 1; /* [10] */
+ __IO uint32_t wpen11 : 1; /* [11] */
+ __IO uint32_t wpen12 : 1; /* [12] */
+ __IO uint32_t wpen13 : 1; /* [13] */
+ __IO uint32_t wpen14 : 1; /* [14] */
+ __IO uint32_t wpen15 : 1; /* [15] */
+ __IO uint32_t wpseq : 1; /* [16] */
+ __IO uint32_t reserved1 : 15;/* [31:17] */
+ } wpr_bit;
+ };
+
+ /**
+ * @brief gpio muxl register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t muxl;
+ struct
+ {
+ __IO uint32_t muxl0 : 4; /* [3:0] */
+ __IO uint32_t muxl1 : 4; /* [7:4] */
+ __IO uint32_t muxl2 : 4; /* [11:8] */
+ __IO uint32_t muxl3 : 4; /* [15:12] */
+ __IO uint32_t muxl4 : 4; /* [19:16] */
+ __IO uint32_t muxl5 : 4; /* [23:20] */
+ __IO uint32_t muxl6 : 4; /* [27:24] */
+ __IO uint32_t muxl7 : 4; /* [31:28] */
+ } muxl_bit;
+ };
+
+ /**
+ * @brief gpio muxh register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t muxh;
+ struct
+ {
+ __IO uint32_t muxh8 : 4; /* [3:0] */
+ __IO uint32_t muxh9 : 4; /* [7:4] */
+ __IO uint32_t muxh10 : 4; /* [11:8] */
+ __IO uint32_t muxh11 : 4; /* [15:12] */
+ __IO uint32_t muxh12 : 4; /* [19:16] */
+ __IO uint32_t muxh13 : 4; /* [23:20] */
+ __IO uint32_t muxh14 : 4; /* [27:24] */
+ __IO uint32_t muxh15 : 4; /* [31:28] */
+ } muxh_bit;
+ };
+
+ /**
+ * @brief gpio clr register, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t clr;
+ struct
+ {
+ __IO uint32_t iocb0 : 1; /* [0] */
+ __IO uint32_t iocb1 : 1; /* [1] */
+ __IO uint32_t iocb2 : 1; /* [2] */
+ __IO uint32_t iocb3 : 1; /* [3] */
+ __IO uint32_t iocb4 : 1; /* [4] */
+ __IO uint32_t iocb5 : 1; /* [5] */
+ __IO uint32_t iocb6 : 1; /* [6] */
+ __IO uint32_t iocb7 : 1; /* [7] */
+ __IO uint32_t iocb8 : 1; /* [8] */
+ __IO uint32_t iocb9 : 1; /* [9] */
+ __IO uint32_t iocb10 : 1; /* [10] */
+ __IO uint32_t iocb11 : 1; /* [11] */
+ __IO uint32_t iocb12 : 1; /* [12] */
+ __IO uint32_t iocb13 : 1; /* [13] */
+ __IO uint32_t iocb14 : 1; /* [14] */
+ __IO uint32_t iocb15 : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } clr_bit;
+ };
+
+ /**
+ * @brief gpio reserved1 register, offset:0x2C~0x38
+ */
+ __IO uint32_t reserved1[4];
+
+ /**
+ * @brief gpio hdrv register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t hdrv;
+ struct
+ {
+ __IO uint32_t hdrv0 : 1; /* [0] */
+ __IO uint32_t hdrv1 : 1; /* [1] */
+ __IO uint32_t hdrv2 : 1; /* [2] */
+ __IO uint32_t hdrv3 : 1; /* [3] */
+ __IO uint32_t hdrv4 : 1; /* [4] */
+ __IO uint32_t hdrv5 : 1; /* [5] */
+ __IO uint32_t hdrv6 : 1; /* [6] */
+ __IO uint32_t hdrv7 : 1; /* [7] */
+ __IO uint32_t hdrv8 : 1; /* [8] */
+ __IO uint32_t hdrv9 : 1; /* [9] */
+ __IO uint32_t hdrv10 : 1; /* [10] */
+ __IO uint32_t hdrv11 : 1; /* [11] */
+ __IO uint32_t hdrv12 : 1; /* [12] */
+ __IO uint32_t hdrv13 : 1; /* [13] */
+ __IO uint32_t hdrv14 : 1; /* [14] */
+ __IO uint32_t hdrv15 : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } hdrv_bit;
+ };
+
+} gpio_type;
+
+/**
+ * @}
+ */
+
+#define GPIOA ((gpio_type *) GPIOA_BASE)
+#define GPIOB ((gpio_type *) GPIOB_BASE)
+#define GPIOC ((gpio_type *) GPIOC_BASE)
+#define GPIOD ((gpio_type *) GPIOD_BASE)
+#define GPIOE ((gpio_type *) GPIOE_BASE)
+#define GPIOF ((gpio_type *) GPIOF_BASE)
+#define GPIOG ((gpio_type *) GPIOG_BASE)
+#define GPIOH ((gpio_type *) GPIOH_BASE)
+
+/** @defgroup GPIO_exported_functions
+ * @{
+ */
+
+void gpio_reset(gpio_type *gpio_x);
+void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct);
+void gpio_default_para_init(gpio_init_type *gpio_init_struct);
+flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins);
+uint16_t gpio_input_data_read(gpio_type *gpio_x);
+flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins);
+uint16_t gpio_output_data_read(gpio_type *gpio_x);
+void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
+void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
+void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
+void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value);
+void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
+void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state);
+void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_i2c.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_i2c.h
new file mode 100644
index 0000000..b5a136c
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_i2c.h
@@ -0,0 +1,479 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_i2c.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 i2c header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_I2C_H
+#define __AT32F435_437_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/**
+ * @brief maximum number of single transfers
+ */
+#define MAX_TRANSFER_CNT 255 /*!< maximum number of single transfers */
+
+/** @defgroup I2C_interrupts_definition
+ * @brief i2c interrupt
+ * @{
+ */
+
+#define I2C_TD_INT ((uint32_t)0x00000002) /*!< i2c transmit data interrupt */
+#define I2C_RD_INT ((uint32_t)0x00000004) /*!< i2c receive data interrupt */
+#define I2C_ADDR_INT ((uint32_t)0x00000008) /*!< i2c address match interrupt */
+#define I2C_ACKFIAL_INT ((uint32_t)0x00000010) /*!< i2c ack fail interrupt */
+#define I2C_STOP_INT ((uint32_t)0x00000020) /*!< i2c stop detect interrupt */
+#define I2C_TDC_INT ((uint32_t)0x00000040) /*!< i2c transmit data complete interrupt */
+#define I2C_ERR_INT ((uint32_t)0x00000080) /*!< i2c bus error interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_flags_definition
+ * @brief i2c flag
+ * @{
+ */
+
+#define I2C_TDBE_FLAG ((uint32_t)0x00000001) /*!< i2c transmit data buffer empty flag */
+#define I2C_TDIS_FLAG ((uint32_t)0x00000002) /*!< i2c send interrupt status */
+#define I2C_RDBF_FLAG ((uint32_t)0x00000004) /*!< i2c receive data buffer full flag */
+#define I2C_ADDRF_FLAG ((uint32_t)0x00000008) /*!< i2c 0~7 bit address match flag */
+#define I2C_ACKFAIL_FLAG ((uint32_t)0x00000010) /*!< i2c acknowledge failure flag */
+#define I2C_STOPF_FLAG ((uint32_t)0x00000020) /*!< i2c stop condition generation complete flag */
+#define I2C_TDC_FLAG ((uint32_t)0x00000040) /*!< i2c transmit data complete flag */
+#define I2C_TCRLD_FLAG ((uint32_t)0x00000080) /*!< i2c transmission is complete, waiting to load data */
+#define I2C_BUSERR_FLAG ((uint32_t)0x00000100) /*!< i2c bus error flag */
+#define I2C_ARLOST_FLAG ((uint32_t)0x00000200) /*!< i2c arbitration lost flag */
+#define I2C_OUF_FLAG ((uint32_t)0x00000400) /*!< i2c overflow or underflow flag */
+#define I2C_PECERR_FLAG ((uint32_t)0x00000800) /*!< i2c pec receive error flag */
+#define I2C_TMOUT_FLAG ((uint32_t)0x00001000) /*!< i2c smbus timeout flag */
+#define I2C_ALERTF_FLAG ((uint32_t)0x00002000) /*!< i2c smbus alert flag */
+#define I2C_BUSYF_FLAG ((uint32_t)0x00008000) /*!< i2c bus busy flag transmission mode */
+#define I2C_SDIR_FLAG ((uint32_t)0x00010000) /*!< i2c slave data transmit direction */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_exported_types
+ * @{
+ */
+
+/**
+ * @brief i2c smbus mode set
+ */
+typedef enum
+{
+ I2C_SMBUS_MODE_DEVICE = 0x00, /*!< smbus device mode */
+ I2C_SMBUS_MODE_HOST = 0x01 /*!< smbus host mode */
+} i2c_smbus_mode_type;
+
+/**
+ * @brief i2c address mode
+ */
+typedef enum
+{
+ I2C_ADDRESS_MODE_7BIT = 0x00, /*!< 7bit address mode */
+ I2C_ADDRESS_MODE_10BIT = 0x01 /*!< 10bit address mode */
+} i2c_address_mode_type;
+
+/**
+ * @brief i2c transfer direction
+ */
+typedef enum
+{
+ I2C_DIR_TRANSMIT = 0x00, /*!< master request a write transfer */
+ I2C_DIR_RECEIVE = 0x01 /*!< master request a read transfer */
+} i2c_transfer_dir_type;
+
+/**
+ * @brief i2c dma requests direction
+ */
+typedef enum
+{
+ I2C_DMA_REQUEST_TX = 0x00, /*!< dma transmit request */
+ I2C_DMA_REQUEST_RX = 0x01 /*!< dma receive request */
+} i2c_dma_request_type;
+
+/**
+ * @brief i2c smbus alert pin set
+ */
+typedef enum
+{
+ I2C_SMBUS_ALERT_HIGH = 0x00, /*!< smbus alert pin set high */
+ I2C_SMBUS_ALERT_LOW = 0x01 /*!< smbus alert pin set low */
+} i2c_smbus_alert_set_type;
+
+/**
+ * @brief i2c clock timeout detection mode
+ */
+typedef enum
+{
+ I2C_TIMEOUT_DETCET_LOW = 0x00, /*!< detect low level timeout */
+ I2C_TIMEOUT_DETCET_HIGH = 0x01 /*!< detect high level timeout */
+} i2c_timeout_detcet_type;
+
+/**
+ * @brief i2c own address2 mask
+ */
+typedef enum
+{
+ I2C_ADDR2_NOMASK = 0x00, /*!< compare bit [7:1] */
+ I2C_ADDR2_MASK01 = 0x01, /*!< only compare bit [7:2] */
+ I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:2] */
+ I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:3] */
+ I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:4] */
+ I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:5] */
+ I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7:6] */
+ I2C_ADDR2_MASK07 = 0x07 /*!< only compare bit [7] */
+} i2c_addr2_mask_type;
+
+/**
+ * @brief i2c reload end mode
+ */
+typedef enum
+{
+ I2C_AUTO_STOP_MODE = 0x00, /*!< auto generate stop mode */
+ I2C_SOFT_STOP_MODE = 0x01, /*!< soft generate stop mode */
+ I2C_RELOAD_MODE = 0x02 /*!< reload mode */
+} i2c_reload_stop_mode_type;
+
+/**
+ * @brief i2c start stop mode
+ */
+typedef enum
+{
+ I2C_WITHOUT_START = 0x00, /*!< transfer data without start condition */
+ I2C_GEN_START_READ = 0x01, /*!< read data and generate start */
+ I2C_GEN_START_WRITE = 0x02 /*!< send data and generate start */
+} i2c_start_stop_mode_type;
+
+/**
+ * @brief type define i2c register all
+ */
+typedef struct
+{
+ /**
+ * @brief i2c ctrl1 register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t i2cen : 1; /* [0] */
+ __IO uint32_t tdien : 1; /* [1] */
+ __IO uint32_t rdien : 1; /* [2] */
+ __IO uint32_t addrien : 1; /* [3] */
+ __IO uint32_t ackfailien : 1; /* [4] */
+ __IO uint32_t stopien : 1; /* [5] */
+ __IO uint32_t tdcien : 1; /* [6] */
+ __IO uint32_t errien : 1; /* [7] */
+ __IO uint32_t dflt : 4; /* [11:8] */
+ __IO uint32_t reserved1 : 2; /* [13:12] */
+ __IO uint32_t dmaten : 1; /* [14] */
+ __IO uint32_t dmaren : 1; /* [15] */
+ __IO uint32_t sctrl : 1; /* [16] */
+ __IO uint32_t stretch : 1; /* [17] */
+ __IO uint32_t reserved2 : 1; /* [18] */
+ __IO uint32_t gcaen : 1; /* [19] */
+ __IO uint32_t haddren : 1; /* [20] */
+ __IO uint32_t devaddren : 1; /* [21] */
+ __IO uint32_t smbalert : 1; /* [22] */
+ __IO uint32_t pecen : 1; /* [23] */
+ __IO uint32_t reserved3 : 8; /* [31:24] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief i2c ctrl2 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t saddr : 10;/* [9:0] */
+ __IO uint32_t dir : 1; /* [10] */
+ __IO uint32_t addr10 : 1; /* [11] */
+ __IO uint32_t readh10 : 1; /* [12] */
+ __IO uint32_t genstart : 1; /* [13] */
+ __IO uint32_t genstop : 1; /* [14] */
+ __IO uint32_t nacken : 1; /* [15] */
+ __IO uint32_t cnt : 8; /* [23:16] */
+ __IO uint32_t rlden : 1; /* [24] */
+ __IO uint32_t astopen : 1; /* [25] */
+ __IO uint32_t pecten : 1; /* [26] */
+ __IO uint32_t reserved1 : 5; /* [31:27] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief i2c oaddr1 register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t oaddr1;
+ struct
+ {
+ __IO uint32_t addr1 : 10;/* [9:0] */
+ __IO uint32_t addr1mode : 1; /* [10] */
+ __IO uint32_t reserved1 : 4; /* [14:11] */
+ __IO uint32_t addr1en : 1; /* [15] */
+ __IO uint32_t reserved2 : 16;/* [31:16] */
+ } oaddr1_bit;
+ };
+
+ /**
+ * @brief i2c oaddr2 register, offset:0x0c
+ */
+ union
+ {
+ __IO uint32_t oaddr2;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t addr2 : 7; /* [7:1] */
+ __IO uint32_t addr2mask : 3; /* [10:8] */
+ __IO uint32_t reserved2 : 4; /* [14:11] */
+ __IO uint32_t addr2en : 1; /* [15] */
+ __IO uint32_t reserved3 : 16;/* [31:16] */
+ } oaddr2_bit;
+ };
+
+ /**
+ * @brief i2c clkctrl register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t clkctrl;
+ struct
+ {
+ __IO uint32_t scll : 8; /* [7:0] */
+ __IO uint32_t sclh : 8; /* [15:8] */
+ __IO uint32_t sdad : 4; /* [19:16] */
+ __IO uint32_t scld : 4; /* [23:20] */
+ __IO uint32_t divh : 4; /* [27:24] */
+ __IO uint32_t divl : 4; /* [31:28] */
+ } clkctrl_bit;
+ };
+
+ /**
+ * @brief i2c timeout register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t timeout;
+ struct
+ {
+ __IO uint32_t totime : 12;/* [11:0] */
+ __IO uint32_t tomode : 1; /* [12] */
+ __IO uint32_t reserved1 : 2; /* [14:13] */
+ __IO uint32_t toen : 1; /* [15] */
+ __IO uint32_t exttime : 12;/* [27:16] */
+ __IO uint32_t reserved2 : 3; /* [30:28] */
+ __IO uint32_t exten : 1; /* [31] */
+ } timeout_bit;
+ };
+
+ /**
+ * @brief i2c sts register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t tdbe : 1; /* [0] */
+ __IO uint32_t tdis : 1; /* [1] */
+ __IO uint32_t rdbf : 1; /* [2] */
+ __IO uint32_t addrf : 1; /* [3] */
+ __IO uint32_t ackfail : 1; /* [4] */
+ __IO uint32_t stopf : 1; /* [5] */
+ __IO uint32_t tdc : 1; /* [6] */
+ __IO uint32_t tcrld : 1; /* [7] */
+ __IO uint32_t buserr : 1; /* [8] */
+ __IO uint32_t arlost : 1; /* [9] */
+ __IO uint32_t ouf : 1; /* [10] */
+ __IO uint32_t pecerr : 1; /* [11] */
+ __IO uint32_t tmout : 1; /* [12] */
+ __IO uint32_t alertf : 1; /* [13] */
+ __IO uint32_t reserved1 : 1; /* [14] */
+ __IO uint32_t busyf : 1; /* [15] */
+ __IO uint32_t sdir : 1; /* [16] */
+ __IO uint32_t addr : 7; /* [23:17] */
+ __IO uint32_t reserved2 : 8; /* [31:24] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief i2c clr register, offset:0x1c
+ */
+ union
+ {
+ __IO uint32_t clr;
+ struct
+ {
+ __IO uint32_t reserved1 : 3; /* [2:0] */
+ __IO uint32_t addrc : 1; /* [3] */
+ __IO uint32_t ackfailc : 1; /* [4] */
+ __IO uint32_t stopc : 1; /* [5] */
+ __IO uint32_t reserved2 : 2; /* [6:7] */
+ __IO uint32_t buserrc : 1; /* [8] */
+ __IO uint32_t arlostc : 1; /* [9] */
+ __IO uint32_t oufc : 1; /* [10] */
+ __IO uint32_t pecerrc : 1; /* [11] */
+ __IO uint32_t tmoutc : 1; /* [12] */
+ __IO uint32_t alertc : 1; /* [13] */
+ __IO uint32_t reserved3 : 18;/* [31:14] */
+ } clr_bit;
+ };
+
+ /**
+ * @brief i2c pec register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t pec;
+ struct
+ {
+ __IO uint32_t pecval : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } pec_bit;
+ };
+
+ /**
+ * @brief i2c rxdt register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t rxdt;
+ struct
+ {
+ __IO uint32_t dt : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } rxdt_bit;
+ };
+
+ /**
+ * @brief i2c txdt register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t txdt;
+ struct
+ {
+ __IO uint32_t dt : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } txdt_bit;
+ };
+
+} i2c_type;
+
+/**
+ * @}
+ */
+
+#define I2C1 ((i2c_type *) I2C1_BASE)
+#define I2C2 ((i2c_type *) I2C2_BASE)
+#define I2C3 ((i2c_type *) I2C3_BASE)
+
+/** @defgroup I2C_exported_functions
+ * @{
+ */
+
+void i2c_reset(i2c_type *i2c_x);
+void i2c_init(i2c_type *i2c_x, uint8_t dfilters, uint32_t clk);
+void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address);
+void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask);
+void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_smbus_enable(i2c_type *i2c_x, i2c_smbus_mode_type mode, confirm_state new_state);
+void i2c_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_addr10_mode_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_transfer_addr_set(i2c_type *i2c_x, uint16_t address);
+uint16_t i2c_transfer_addr_get(i2c_type *i2c_x);
+void i2c_transfer_dir_set(i2c_type *i2c_x, i2c_transfer_dir_type i2c_direction);
+i2c_transfer_dir_type i2c_transfer_dir_get(i2c_type *i2c_x);
+uint8_t i2c_matched_addr_get(i2c_type *i2c_x);
+void i2c_auto_stop_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_reload_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_cnt_set(i2c_type *i2c_x, uint8_t cnt);
+void i2c_addr10_header_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level);
+void i2c_slave_data_ctrl_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state);
+uint8_t i2c_pec_value_get(i2c_type *i2c_x);
+void i2c_timeout_set(i2c_type *i2c_x, uint16_t timeout);
+void i2c_timeout_detcet_set(i2c_type *i2c_x, i2c_timeout_detcet_type mode);
+void i2c_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_ext_timeout_set(i2c_type *i2c_x, uint16_t timeout);
+void i2c_ext_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_interrupt_enable(i2c_type *i2c_x, uint32_t source, confirm_state new_state);
+flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source);
+void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state new_state);
+void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_stop_mode_type start_stop);
+void i2c_start_generate(i2c_type *i2c_x);
+void i2c_stop_generate(i2c_type *i2c_x);
+void i2c_data_send(i2c_type *i2c_x, uint8_t data);
+uint8_t i2c_data_receive(i2c_type *i2c_x);
+flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
+void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_misc.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_misc.h
new file mode 100644
index 0000000..9c5edaa
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_misc.h
@@ -0,0 +1,125 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_misc.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 misc header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_MISC_H
+#define __AT32F435_437_MISC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/** @defgroup MISC_vector_table_base_address
+ * @{
+ */
+
+#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< nvic vector table based ram address */
+#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< nvic vector table based flash address */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_exported_types
+ * @{
+ */
+
+/**
+ * @brief nvic interrupt priority group
+ */
+typedef enum
+{
+ NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
+ NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
+ NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
+ NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
+ NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3) /*!< 4 bits for preemption priority, 0 bits for subpriority */
+} nvic_priority_group_type;
+
+/**
+ * @brief nvic low power mode
+ */
+typedef enum
+{
+ NVIC_LP_SLEEPONEXIT = 0x02, /*!< send event on pending */
+ NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */
+ NVIC_LP_SEVONPEND = 0x10 /*!< enable sleep-on-exit feature */
+} nvic_lowpower_mode_type;
+
+/**
+ * @brief systick clock source
+ */
+typedef enum
+{
+ SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8 = ((uint32_t)0x00000000), /*!< systick clock source from core clock div8 */
+ SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV = ((uint32_t)0x00000004) /*!< systick clock source from core clock */
+} systick_clock_source_type;
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_exported_functions
+ * @{
+ */
+
+void nvic_system_reset(void);
+void nvic_irq_enable(uint32_t irqn, uint32_t preempt_priority, uint32_t sub_priority);
+void nvic_irq_disable(uint32_t irqn);
+void nvic_priority_group_config(nvic_priority_group_type priority_group);
+void nvic_vector_table_set(uint32_t base, uint32_t offset);
+void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state);
+void systick_clock_source_config(systick_clock_source_type source);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_pwc.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_pwc.h
new file mode 100644
index 0000000..76b5e4b
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_pwc.h
@@ -0,0 +1,230 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_pwc.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 pwr header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_PWC_H
+#define __AT32F435_437_PWC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup PWC
+ * @{
+ */
+
+/** @defgroup PWC_flags_definition
+ * @brief pwc flag
+ * @{
+ */
+
+#define PWC_WAKEUP_FLAG ((uint32_t)0x00000001) /*!< wakeup flag */
+#define PWC_STANDBY_FLAG ((uint32_t)0x00000002) /*!< standby flag */
+#define PWC_PVM_OUTPUT_FLAG ((uint32_t)0x00000004) /*!< pvm output flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief pwc wakeup pin num definition
+ */
+#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */
+#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2 */
+
+/**
+ * @brief select ldo output voltage.
+ * @param val: set the ldo output voltage.
+ * this parameter can be one of the following values:
+ * - PWC_LDO_OUTPUT_1V2
+ * - PWC_LDO_OUTPUT_1V3
+ * - PWC_LDO_OUTPUT_1V1
+ * - PWC_LDO_OUTPUT_1V0
+ */
+#define pwc_ldo_output_voltage_set(val) (PWC->ldoov_bit.ldoovsel = val)
+
+/** @defgroup PWC_exported_types
+ * @{
+ */
+
+/**
+ * @brief pwc pvm voltage type
+ */
+typedef enum
+{
+ PWC_PVM_VOLTAGE_2V3 = 0x01, /*!< power voltage monitoring boundary 2.3v */
+ PWC_PVM_VOLTAGE_2V4 = 0x02, /*!< power voltage monitoring boundary 2.4v */
+ PWC_PVM_VOLTAGE_2V5 = 0x03, /*!< power voltage monitoring boundary 2.5v */
+ PWC_PVM_VOLTAGE_2V6 = 0x04, /*!< power voltage monitoring boundary 2.6v */
+ PWC_PVM_VOLTAGE_2V7 = 0x05, /*!< power voltage monitoring boundary 2.7v */
+ PWC_PVM_VOLTAGE_2V8 = 0x06, /*!< power voltage monitoring boundary 2.8v */
+ PWC_PVM_VOLTAGE_2V9 = 0x07 /*!< power voltage monitoring boundary 2.9v */
+} pwc_pvm_voltage_type;
+
+/**
+ * @brief pwc ldo output voltage type
+ */
+typedef enum
+{
+ PWC_LDO_OUTPUT_1V2 = 0x00, /*!< ldo output voltage is 1.2v */
+ PWC_LDO_OUTPUT_1V3 = 0x01, /*!< ldo output voltage is 1.3v */
+ PWC_LDO_OUTPUT_1V1 = 0x04, /*!< ldo output voltage is 1.1v */
+ PWC_LDO_OUTPUT_1V0 = 0x05, /*!< ldo output voltage is 1.0v */
+} pwc_ldo_output_voltage_type;
+
+/**
+ * @brief pwc sleep enter type
+ */
+typedef enum
+{
+ PWC_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter sleep mode */
+ PWC_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter sleep mode */
+} pwc_sleep_enter_type ;
+
+/**
+ * @brief pwc deep sleep enter type
+ */
+typedef enum
+{
+ PWC_DEEP_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter deepsleep mode */
+ PWC_DEEP_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter deepsleep mode */
+} pwc_deep_sleep_enter_type ;
+
+/**
+ * @brief pwc regulator type
+ */
+typedef enum
+{
+ PWC_REGULATOR_ON = 0x00, /*!< voltage regulator state on when deepsleep mode */
+ PWC_REGULATOR_LOW_POWER = 0x01 /*!< voltage regulator state low power when deepsleep mode */
+} pwc_regulator_type ;
+
+/**
+ * @brief type define pwc register all
+ */
+typedef struct
+{
+ /**
+ * @brief pwc ctrl register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t vrsel : 1; /* [0] */
+ __IO uint32_t lpsel : 1; /* [1] */
+ __IO uint32_t clswef : 1; /* [2] */
+ __IO uint32_t clsef : 1; /* [3] */
+ __IO uint32_t pvmen : 1; /* [4] */
+ __IO uint32_t pvmsel : 3; /* [7:5] */
+ __IO uint32_t bpwen : 1; /* [8] */
+ __IO uint32_t reserved1 : 23;/* [31:9] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief pwc ctrlsts register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrlsts;
+ struct
+ {
+ __IO uint32_t swef : 1; /* [0] */
+ __IO uint32_t sef : 1; /* [1] */
+ __IO uint32_t pvmof : 1; /* [2] */
+ __IO uint32_t reserved1 : 5; /* [7:3] */
+ __IO uint32_t swpen1 : 1; /* [8] */
+ __IO uint32_t swpen2 : 1; /* [9] */
+ __IO uint32_t reserved2 : 22;/* [31:10] */
+ } ctrlsts_bit;
+ };
+
+ __IO uint32_t reserved1[2];
+
+ /**
+ * @brief pwc ldoov register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ldoov;
+ struct
+ {
+ __IO uint32_t ldoovsel : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 29;/* [31:3] */
+ } ldoov_bit;
+ };
+
+} pwc_type;
+
+/**
+ * @}
+ */
+
+#define PWC ((pwc_type *) PWC_BASE)
+
+/** @defgroup PWC_exported_functions
+ * @{
+ */
+
+void pwc_reset(void);
+void pwc_battery_powered_domain_access(confirm_state new_state);
+void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage);
+void pwc_power_voltage_monitor_enable(confirm_state new_state);
+void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state);
+void pwc_flag_clear(uint32_t pwc_flag);
+flag_status pwc_flag_get(uint32_t pwc_flag);
+void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter);
+void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter);
+void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator);
+void pwc_standby_mode_enter(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_qspi.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_qspi.h
new file mode 100644
index 0000000..d73e823
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_qspi.h
@@ -0,0 +1,555 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_qspi.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 qspi header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_QSPI_H
+#define __AT32F435_437_QSPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup QSPI
+ * @{
+ */
+
+/** @defgroup QSPI_flags_definition
+ * @brief qspi flag
+ * @{
+ */
+
+#define QSPI_CMDSTS_FLAG ((uint32_t)0x00000001) /*!< qspi command complete status flag */
+#define QSPI_RXFIFORDY_FLAG ((uint32_t)0x00000002) /*!< qspi rxfifo ready status flag */
+#define QSPI_TXFIFORDY_FLAG ((uint32_t)0x00000004) /*!< qspi txfifo ready status flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_exported_types
+ * @{
+ */
+
+/**
+ * @brief qspi xip read access mode type
+ */
+typedef enum
+{
+ QSPI_XIPR_SEL_MODED = 0x00, /*!< qspi xip read select mode d */
+ QSPI_XIPR_SEL_MODET = 0x01 /*!< qspi xip read select mode t */
+} qspi_xip_read_sel_type;
+
+/**
+ * @brief qspi xip write access mode type
+ */
+typedef enum
+{
+ QSPI_XIPW_SEL_MODED = 0x00, /*!< qspi xip write select mode d */
+ QSPI_XIPW_SEL_MODET = 0x01 /*!< qspi xip write select mode t */
+} qspi_xip_write_sel_type;
+
+/**
+ * @brief qspi busy bit offset position in status register type
+ */
+typedef enum
+{
+ QSPI_BUSY_OFFSET_0 = 0x00, /*!< qspi busy bit offset position 0 */
+ QSPI_BUSY_OFFSET_1 = 0x01, /*!< qspi busy bit offset position 1 */
+ QSPI_BUSY_OFFSET_2 = 0x02, /*!< qspi busy bit offset position 2 */
+ QSPI_BUSY_OFFSET_3 = 0x03, /*!< qspi busy bit offset position 3 */
+ QSPI_BUSY_OFFSET_4 = 0x04, /*!< qspi busy bit offset position 4 */
+ QSPI_BUSY_OFFSET_5 = 0x05, /*!< qspi busy bit offset position 5 */
+ QSPI_BUSY_OFFSET_6 = 0x06, /*!< qspi busy bit offset position 6 */
+ QSPI_BUSY_OFFSET_7 = 0x07 /*!< qspi busy bit offset position 7 */
+} qspi_busy_pos_type;
+
+/**
+ * @brief qspi read status configure type
+ */
+typedef enum
+{
+ QSPI_RSTSC_HW_AUTO = 0x00, /*!< qspi read status by hardware */
+ QSPI_RSTSC_SW_ONCE = 0x01 /*!< qspi read status by software */
+} qspi_read_status_conf_type;
+
+/**
+ * @brief qspi operate mode type
+ */
+typedef enum
+{
+ QSPI_OPERATE_MODE_111 = 0x00, /*!< qspi serial mode */
+ QSPI_OPERATE_MODE_112 = 0x01, /*!< qspi dual mode */
+ QSPI_OPERATE_MODE_114 = 0x02, /*!< qspi quad mode */
+ QSPI_OPERATE_MODE_122 = 0x03, /*!< qspi dual i/o mode */
+ QSPI_OPERATE_MODE_144 = 0x04, /*!< qspi quad i/o mode */
+ QSPI_OPERATE_MODE_222 = 0x05, /*!< qspi instruction 2-bit mode */
+ QSPI_OPERATE_MODE_444 = 0x06 /*!< qspi instruction 4-bit mode(qpi) */
+} qspi_operate_mode_type;
+
+/**
+ * @brief qspi clock division type
+ */
+typedef enum
+{
+ QSPI_CLK_DIV_2 = 0x00, /*!< qspi clk divide by 2 */
+ QSPI_CLK_DIV_4 = 0x01, /*!< qspi clk divide by 4 */
+ QSPI_CLK_DIV_6 = 0x02, /*!< qspi clk divide by 6 */
+ QSPI_CLK_DIV_8 = 0x03, /*!< qspi clk divide by 8 */
+ QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */
+ QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */
+ QSPI_CLK_DIV_10 = 0x06, /*!< qspi clk divide by 10 */
+ QSPI_CLK_DIV_12 = 0x07 /*!< qspi clk divide by 12 */
+} qspi_clk_div_type;
+
+/**
+ * @brief qspi command port address length type
+ */
+typedef enum
+{
+ QSPI_CMD_ADRLEN_0_BYTE = 0x00, /*!< qspi no address */
+ QSPI_CMD_ADRLEN_1_BYTE = 0x01, /*!< qspi address length 1 byte */
+ QSPI_CMD_ADRLEN_2_BYTE = 0x02, /*!< qspi address length 2 byte */
+ QSPI_CMD_ADRLEN_3_BYTE = 0x03, /*!< qspi address length 3 byte */
+ QSPI_CMD_ADRLEN_4_BYTE = 0x04 /*!< qspi address length 4 byte */
+} qspi_cmd_adrlen_type;
+
+/**
+ * @brief qspi command port instruction length type
+ */
+typedef enum
+{
+ QSPI_CMD_INSLEN_0_BYTE = 0x00, /*!< qspi no instruction code */
+ QSPI_CMD_INSLEN_1_BYTE = 0x01, /*!< qspi instruction code 1 byte */
+ QSPI_CMD_INSLEN_2_BYTE = 0x02 /*!< qspi instruction code 2 byte(repeat) */
+} qspi_cmd_inslen_type;
+
+/**
+ * @brief qspi xip r/w address length type
+ */
+typedef enum
+{
+ QSPI_XIP_ADDRLEN_3_BYTE = 0x00, /*!< qspi xip address length 3 byte */
+ QSPI_XIP_ADDRLEN_4_BYTE = 0x01 /*!< qspi xip address length 4 byte */
+} qspi_xip_addrlen_type;
+
+/**
+ * @brief qspi sckout mode type
+ */
+typedef enum
+{
+ QSPI_SCK_MODE_0 = 0x00, /*!< qspi sck mode 0 */
+ QSPI_SCK_MODE_3 = 0x01 /*!< qspi sck mode 3 */
+} qspi_clk_mode_type;
+
+/**
+ * @brief qspi dma tx/rx fifo threshold type
+ */
+typedef enum
+{
+ QSPI_DMA_FIFO_THOD_WORD08 = 0x00, /*!< qspi dma fifo threshold 8 words */
+ QSPI_DMA_FIFO_THOD_WORD16 = 0x01, /*!< qspi dma fifo threshold 16 words */
+ QSPI_DMA_FIFO_THOD_WORD32 = 0x02 /*!< qspi dma fifo threshold 32 words */
+} qspi_dma_fifo_thod_type;
+
+/**
+ * @brief qspi cmd type
+ */
+typedef struct
+{
+ confirm_state pe_mode_enable; /*!< perfornance enhance mode enable */
+ uint8_t pe_mode_operate_code; /*!< performance enhance mode operate code */
+ uint8_t instruction_code; /*!< instruction code */
+ qspi_cmd_inslen_type instruction_length; /*!< instruction code length */
+ uint32_t address_code; /*!< address code */
+ qspi_cmd_adrlen_type address_length; /*!< address legnth */
+ uint32_t data_counter; /*!< read/write data counter */
+ uint8_t second_dummy_cycle_num; /*!< number of second dummy state cycle 0~32 */
+ qspi_operate_mode_type operation_mode; /*!< operation mode */
+ qspi_read_status_conf_type read_status_config; /*!< config to read status */
+ confirm_state read_status_enable; /*!< config to read status */
+ confirm_state write_data_enable; /*!< enable to write data */
+} qspi_cmd_type;
+
+/**
+ * @brief qspi xip type
+ */
+typedef struct
+{
+ uint8_t read_instruction_code; /*!< read instruction code */
+ qspi_xip_addrlen_type read_address_length; /*!< read address legnth */
+ qspi_operate_mode_type read_operation_mode; /*!< read operation mode */
+ uint8_t read_second_dummy_cycle_num; /*!< read number of second dummy state cycle 0~32 */
+ uint8_t write_instruction_code; /*!< write instruction code */
+ qspi_xip_addrlen_type write_address_length; /*!< write address legnth */
+ qspi_operate_mode_type write_operation_mode; /*!< write operation mode */
+ uint8_t write_second_dummy_cycle_num; /*!< write number of second dummy state cycle 0~32 */
+ qspi_xip_write_sel_type write_select_mode; /*!< write mode d or mode t selection */
+ uint8_t write_time_counter; /*!< write count for mode t */
+ uint8_t write_data_counter; /*!< write count for mode d */
+ qspi_xip_read_sel_type read_select_mode; /*!< read mode d or mode t selection */
+ uint8_t read_time_counter; /*!< read count for mode t */
+ uint8_t read_data_counter; /*!< read count for mode d */
+} qspi_xip_type;
+
+/**
+ * @brief type define qspi register all
+ */
+typedef struct
+{
+ /**
+ * @brief qspi cmd_w0 register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t cmd_w0;
+ struct
+ {
+
+ __IO uint32_t spiadr : 32;/* [31:0] */
+ } cmd_w0_bit;
+ };
+
+ /**
+ * @brief qspi cmd_w1 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t cmd_w1;
+ struct
+ {
+ __IO uint32_t adrlen : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 13;/* [15:3] */
+ __IO uint32_t dum2 : 8; /* [23:16] */
+ __IO uint32_t inslen : 2; /* [25:24] */
+ __IO uint32_t reserved2 : 2; /* [27:26] */
+ __IO uint32_t pemen : 1; /* [28] */
+ __IO uint32_t reserved3 : 3; /* [31:29] */
+ } cmd_w1_bit;
+ };
+
+ /**
+ * @brief qspi cmd_w2 register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t cmd_w2;
+ struct
+ {
+ __IO uint32_t dcnt : 32;/* [31:0] */
+ } cmd_w2_bit;
+ };
+
+ /**
+ * @brief qspi cmd_w3 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t cmd_w3;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t wen : 1; /* [1] */
+ __IO uint32_t rstsen : 1; /* [2] */
+ __IO uint32_t rstsc : 1; /* [3] */
+ __IO uint32_t reserved2 : 1; /* [4] */
+ __IO uint32_t opmode : 3; /* [7:5] */
+ __IO uint32_t reserved3 : 8; /* [15:8] */
+ __IO uint32_t pemopc : 8; /* [23:16] */
+ __IO uint32_t insc : 8; /* [31:24] */
+ } cmd_w3_bit;
+ };
+
+ /**
+ * @brief qspi ctrl register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t clkdiv : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t sckmode : 1; /* [4] */
+ __IO uint32_t reserved2 : 2; /* [6:5] */
+ __IO uint32_t xipidle : 1; /* [7] */
+ __IO uint32_t abort : 1; /* [8] */
+ __IO uint32_t reserved3 : 7; /* [15:9] */
+ __IO uint32_t busy : 3; /* [18:16] */
+ __IO uint32_t xiprcmdf : 1; /* [19] */
+ __IO uint32_t xipsel : 1; /* [20] */
+ __IO uint32_t keyen : 1; /* [21] */
+ __IO uint32_t reserved4 : 10;/* [31:22] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief qspi actr register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t actr;
+ struct
+ {
+ __IO uint32_t csdly : 4; /* [3:0] */
+ __IO uint32_t reserved1 : 28;/* [31:4] */
+ } actr_bit;
+ };
+
+ /**
+ * @brief qspi fifosts register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t fifosts;
+ struct
+ {
+ __IO uint32_t txfifordy : 1; /* [0] */
+ __IO uint32_t rxfifordy : 1; /* [1] */
+ __IO uint32_t reserved1 : 30;/* [31:2] */
+ } fifosts_bit;
+ };
+
+ /**
+ * @brief qspi reserved register, offset:0x1C
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief qspi ctrl2 register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t dmaen : 1; /* [0] */
+ __IO uint32_t cmdie : 1; /* [1] */
+ __IO uint32_t reserved1 : 6; /* [7:2] */
+ __IO uint32_t txfifo_thod : 2; /* [9:8] */
+ __IO uint32_t reserved2 : 2; /* [11:10] */
+ __IO uint32_t rxfifo_thod : 2; /* [13:12] */
+ __IO uint32_t reserved3 : 18;/* [31:14] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief qspi cmdsts register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t cmdsts;
+ struct
+ {
+ __IO uint32_t cmdsts : 1; /* [0] */
+ __IO uint32_t reserved1 : 31;/* [31:1] */
+ } cmdsts_bit;
+ };
+
+ /**
+ * @brief qspi rsts register, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t rsts;
+ struct
+ {
+ __IO uint32_t spists : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } rsts_bit;
+ };
+
+ /**
+ * @brief qspi fsize register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t fsize;
+ struct
+ {
+ __IO uint32_t spifsize : 32;/* [31:0] */
+ } fsize_bit;
+ };
+
+ /**
+ * @brief qspi xip_cmd_w0 register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t xip_cmd_w0;
+ struct
+ {
+ __IO uint32_t xipr_dum2 : 8; /* [7:0] */
+ __IO uint32_t xipr_opmode : 3; /* [10:8] */
+ __IO uint32_t xipr_adrlen : 1; /* [11] */
+ __IO uint32_t xipr_insc : 8; /* [19:12] */
+ __IO uint32_t reserved1 : 12;/* [31:20] */
+ } xip_cmd_w0_bit;
+ };
+
+ /**
+ * @brief qspi xip_cmd_w1 register, offset:0x34
+ */
+ union
+ {
+ __IO uint32_t xip_cmd_w1;
+ struct
+ {
+ __IO uint32_t xipr_dum2 : 8; /* [7:0] */
+ __IO uint32_t xipr_opmode : 3; /* [10:8] */
+ __IO uint32_t xipr_adrlen : 1; /* [11] */
+ __IO uint32_t xipr_insc : 8; /* [19:12] */
+ __IO uint32_t reserved1 : 12;/* [31:20] */
+ } xip_cmd_w1_bit;
+ };
+
+ /**
+ * @brief qspi xip_cmd_w2 register, offset:0x38
+ */
+ union
+ {
+ __IO uint32_t xip_cmd_w2;
+ struct
+ {
+ __IO uint32_t xipr_dcnt : 6; /* [5:0] */
+ __IO uint32_t reserved1 : 2; /* [7:6] */
+ __IO uint32_t xipr_tcnt : 7; /* [14:8] */
+ __IO uint32_t xipr_sel : 1; /* [15] */
+ __IO uint32_t xipw_dcnt : 6; /* [21:16] */
+ __IO uint32_t reserved2 : 2; /* [23:22] */
+ __IO uint32_t xipw_tcnt : 7; /* [30:24] */
+ __IO uint32_t xipw_sel : 1; /* [31] */
+ } xip_cmd_w2_bit;
+ };
+
+ /**
+ * @brief qspi xip_cmd_w3 register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t xip_cmd_w3;
+ struct
+ {
+ __IO uint32_t bypassc : 1; /* [0] */
+ __IO uint32_t reserved1 : 2; /* [2:1] */
+ __IO uint32_t csts : 1; /* [3] */
+ __IO uint32_t reserved2 : 28;/* [31:4] */
+ } xip_cmd_w3_bit;
+ };
+
+ /**
+ * @brief qspi reserved register, offset:0x40~4C
+ */
+ __IO uint32_t reserved2[4];
+
+ /**
+ * @brief qspi rev register, offset:0x50
+ */
+ union
+ {
+ __IO uint32_t rev;
+ struct
+ {
+ __IO uint32_t rev : 32;/* [31:0] */
+ } rev_bit;
+ };
+
+ /**
+ * @brief qspi reserved register, offset:0x54~FC
+ */
+ __IO uint32_t reserved3[43];
+
+ /**
+ * @brief qspi dt register, offset:0x100
+ */
+ union
+ {
+ __IO uint8_t dt_u8;
+ __IO uint16_t dt_u16;
+ __IO uint32_t dt;
+ struct
+ {
+ __IO uint32_t dt : 32;/* [31:0] */
+ } dt_bit;
+ };
+
+} qspi_type;
+
+/**
+ * @}
+ */
+
+#define QSPI1 ((qspi_type*)QSPI1_REG_BASE)
+#define QSPI2 ((qspi_type*)QSPI2_REG_BASE)
+
+/** @defgroup QSPI_exported_functions
+ * @{
+ */
+
+void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state);
+void qspi_sck_mode_set( qspi_type* qspi_x, qspi_clk_mode_type new_mode);
+void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv);
+void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state);
+void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state);
+flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag);
+void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag);
+void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
+void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
+void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state);
+void qspi_busy_config(qspi_type* qspi_x, qspi_busy_pos_type busy_pos);
+void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state);
+void qspi_cmd_operation_kick(qspi_type* qspi_x, qspi_cmd_type* qspi_cmd_struct);
+void qspi_xip_init(qspi_type* qspi_x, qspi_xip_type* xip_init_struct);
+uint8_t qspi_byte_read(qspi_type* qspi_x);
+uint16_t qspi_half_word_read(qspi_type* qspi_x);
+uint32_t qspi_word_read(qspi_type* qspi_x);
+void qspi_word_write(qspi_type* qspi_x, uint32_t value);
+void qspi_half_word_write(qspi_type* qspi_x, uint16_t value);
+void qspi_byte_write(qspi_type* qspi_x, uint8_t value);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_scfg.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_scfg.h
new file mode 100644
index 0000000..332098f
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_scfg.h
@@ -0,0 +1,323 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_scfg.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 system config header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_SCFG_H
+#define __AT32F435_437_SCFG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup SCFG
+ * @{
+ */
+
+#define SCFG_REG(value) PERIPH_REG(SCFG_BASE, value)
+#define SCFG_REG_BIT(value) PERIPH_REG_BIT(value)
+
+/** @defgroup SCFG_exported_types
+ * @{
+ */
+
+/**
+ * @brief scfg xmc addres mapping swap type
+ */
+typedef enum
+{
+ SCFG_XMC_SWAP_NONE = 0x00, /* no swap */
+ SCFG_XMC_SWAP_MODE1 = 0x01, /* sdram nor psram sram nand2 swap */
+ SCFG_XMC_SWAP_MODE2 = 0x02, /* nand3 qspi2 swap */
+ SCFG_XMC_SWAP_MODE3 = 0x03 /* sdram nor psram sram nand2 nand3 qspi2 swap */
+} scfg_xmc_swap_type;
+
+/**
+ * @brief scfg infrared modulation signal source selecting type
+ */
+typedef enum
+{
+ SCFG_IR_SOURCE_TMR10 = 0x00, /* infrared signal source select tmr10 */
+ SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */
+ SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */
+} scfg_ir_source_type;
+
+/**
+ * @brief scfg infrared output polarity selecting type
+ */
+typedef enum
+{
+ SCFG_IR_POLARITY_NO_AFFECTE = 0x00, /* infrared output polarity no affecte */
+ SCFG_IR_POLARITY_REVERSE = 0x01 /* infrared output polarity reverse */
+} scfg_ir_polarity_type;
+
+/**
+ * @brief scfg memory address mapping selecting type
+ */
+typedef enum
+{
+ SCFG_MEM_MAP_MAIN_MEMORY = 0x00, /* 0x00000000 address mapping from main memory */
+ SCFG_MEM_MAP_BOOT_MEMORY = 0x01, /* 0x00000000 address mapping from boot memory */
+ SCFG_MEM_MAP_XMC_BANK1 = 0x02, /* 0x00000000 address mapping from xmc bank1 */
+ SCFG_MEM_MAP_INTERNAL_SRAM = 0x03, /* 0x00000000 address mapping from internal sram */
+ SCFG_MEM_MAP_XMC_SDRAM_BANK1 = 0x04 /* 0x00000000 address mapping from xmc sdram bank1 */
+} scfg_mem_map_type;
+
+/**
+ * @brief scfg pin source type
+ */
+typedef enum
+{
+ SCFG_PINS_SOURCE0 = 0x00,
+ SCFG_PINS_SOURCE1 = 0x01,
+ SCFG_PINS_SOURCE2 = 0x02,
+ SCFG_PINS_SOURCE3 = 0x03,
+ SCFG_PINS_SOURCE4 = 0x04,
+ SCFG_PINS_SOURCE5 = 0x05,
+ SCFG_PINS_SOURCE6 = 0x06,
+ SCFG_PINS_SOURCE7 = 0x07,
+ SCFG_PINS_SOURCE8 = 0x08,
+ SCFG_PINS_SOURCE9 = 0x09,
+ SCFG_PINS_SOURCE10 = 0x0A,
+ SCFG_PINS_SOURCE11 = 0x0B,
+ SCFG_PINS_SOURCE12 = 0x0C,
+ SCFG_PINS_SOURCE13 = 0x0D,
+ SCFG_PINS_SOURCE14 = 0x0E,
+ SCFG_PINS_SOURCE15 = 0x0F
+} scfg_pins_source_type;
+
+/**
+ * @brief gpio port source type
+ */
+typedef enum
+{
+ SCFG_PORT_SOURCE_GPIOA = 0x00,
+ SCFG_PORT_SOURCE_GPIOB = 0x01,
+ SCFG_PORT_SOURCE_GPIOC = 0x02,
+ SCFG_PORT_SOURCE_GPIOD = 0x03,
+ SCFG_PORT_SOURCE_GPIOE = 0x04,
+ SCFG_PORT_SOURCE_GPIOF = 0x05,
+ SCFG_PORT_SOURCE_GPIOG = 0x06,
+ SCFG_PORT_SOURCE_GPIOH = 0x07
+} scfg_port_source_type;
+
+/**
+ * @brief scfg emac interface selecting type
+ */
+typedef enum
+{
+ SCFG_EMAC_SELECT_MII = 0x00, /* emac interface select mii mode */
+ SCFG_EMAC_SELECT_RMII = 0x01 /* emac interface select rmii mode */
+} scfg_emac_interface_type;
+
+/**
+ * @brief scfg ultra high sourcing/sinking strength pins type
+ */
+typedef enum
+{
+ SCFG_ULTRA_DRIVEN_PB3 = MAKE_VALUE(0x2C, 0),
+ SCFG_ULTRA_DRIVEN_PB9 = MAKE_VALUE(0x2C, 1),
+ SCFG_ULTRA_DRIVEN_PB10 = MAKE_VALUE(0x2C, 2),
+ SCFG_ULTRA_DRIVEN_PD12 = MAKE_VALUE(0x2C, 5),
+ SCFG_ULTRA_DRIVEN_PD13 = MAKE_VALUE(0x2C, 6),
+ SCFG_ULTRA_DRIVEN_PD14 = MAKE_VALUE(0x2C, 7),
+ SCFG_ULTRA_DRIVEN_PD15 = MAKE_VALUE(0x2C, 8),
+ SCFG_ULTRA_DRIVEN_PF14 = MAKE_VALUE(0x2C, 9),
+ SCFG_ULTRA_DRIVEN_PF15 = MAKE_VALUE(0x2C, 10)
+} scfg_ultra_driven_pins_type;
+
+/**
+ * @brief type define system config register all
+ */
+typedef struct
+{
+ /**
+ * @brief scfg cfg1 register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t cfg1;
+ struct
+ {
+ __IO uint32_t mem_map_sel : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 2; /* [4:3] */
+ __IO uint32_t ir_pol : 1; /* [5] */
+ __IO uint32_t ir_src_sel : 2; /* [7:6] */
+ __IO uint32_t reserved2 : 2; /* [9:8] */
+ __IO uint32_t swap_xmc : 2; /* [11:10] */
+ __IO uint32_t reserved3 : 20;/* [31:12] */
+ } cfg1_bit;
+ };
+
+ /**
+ * @brief scfg cfg2 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t cfg2;
+ struct
+ {
+ __IO uint32_t reserved1 : 23;/* [22:0] */
+ __IO uint32_t mii_rmii_sel : 1; /* [23] */
+ __IO uint32_t reserved2 : 8; /* [31:24] */
+ } cfg2_bit;
+ };
+
+ /**
+ * @brief scfg exintc1 register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t exintc1;
+ struct
+ {
+ __IO uint32_t exint0 : 4; /* [3:0] */
+ __IO uint32_t exint1 : 4; /* [7:4] */
+ __IO uint32_t exint2 : 4; /* [11:8] */
+ __IO uint32_t exint3 : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } exintc1_bit;
+ };
+
+ /**
+ * @brief scfg exintc2 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t exintc2;
+ struct
+ {
+ __IO uint32_t exint4 : 4; /* [3:0] */
+ __IO uint32_t exint5 : 4; /* [7:4] */
+ __IO uint32_t exint6 : 4; /* [11:8] */
+ __IO uint32_t exint7 : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } exintc2_bit;
+ };
+
+ /**
+ * @brief scfg exintc3 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t exintc3;
+ struct
+ {
+ __IO uint32_t exint8 : 4; /* [3:0] */
+ __IO uint32_t exint9 : 4; /* [7:4] */
+ __IO uint32_t exint10 : 4; /* [11:8] */
+ __IO uint32_t exint11 : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } exintc3_bit;
+ };
+
+ /**
+ * @brief scfg exintc4 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t exintc4;
+ struct
+ {
+ __IO uint32_t exint12 : 4; /* [3:0] */
+ __IO uint32_t exint13 : 4; /* [7:4] */
+ __IO uint32_t exint14 : 4; /* [11:8] */
+ __IO uint32_t exint15 : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } exintc4_bit;
+ };
+
+ /**
+ * @brief crm reserved1 register, offset:0x18~0x28
+ */
+ __IO uint32_t reserved1[5];
+
+ /**
+ * @brief scfg uhdrv register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t uhdrv;
+ struct
+ {
+ __IO uint32_t pb3_uh : 1; /* [0] */
+ __IO uint32_t pb9_uh : 1; /* [1] */
+ __IO uint32_t pb10_uh : 1; /* [2] */
+ __IO uint32_t reserved1 : 2; /* [4:3] */
+ __IO uint32_t pd12_uh : 1; /* [5] */
+ __IO uint32_t pd13_uh : 1; /* [6] */
+ __IO uint32_t pd14_uh : 1; /* [7] */
+ __IO uint32_t pd15_uh : 1; /* [8] */
+ __IO uint32_t pf14_uh : 1; /* [9] */
+ __IO uint32_t pf15_uh : 1; /* [10] */
+ __IO uint32_t reserved2 : 21;/* [31:11] */
+ } uhdrv_bit;
+ };
+
+} scfg_type;
+
+/**
+ * @}
+ */
+
+#define SCFG ((scfg_type *) SCFG_BASE)
+
+/** @defgroup SCFG_exported_functions
+ * @{
+ */
+
+void scfg_reset(void);
+void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap);
+void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity);
+void scfg_mem_map_set(scfg_mem_map_type mem_map);
+void scfg_emac_interface_set(scfg_emac_interface_type mode);
+void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source);
+void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_sdio.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_sdio.h
new file mode 100644
index 0000000..babd040
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_sdio.h
@@ -0,0 +1,624 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_sdio.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 sdio header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_SDIO_H
+#define __AT32F435_437_SDIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup SDIO
+ * @{
+ */
+
+/** @defgroup SDIO_interrupts_definition
+ * @brief sdio interrupt
+ * @{
+ */
+
+#define SDIO_CMDFAIL_INT ((uint32_t)0x00000001) /*!< command response received check failed interrupt */
+#define SDIO_DTFAIL_INT ((uint32_t)0x00000002) /*!< data block sent/received check failed interrupt */
+#define SDIO_CMDTIMEOUT_INT ((uint32_t)0x00000004) /*!< command response timerout interrupt */
+#define SDIO_DTTIMEOUT_INT ((uint32_t)0x00000008) /*!< data timeout interrupt */
+#define SDIO_TXERRU_INT ((uint32_t)0x00000010) /*!< transmit underrun error interrupt */
+#define SDIO_RXERRO_INT ((uint32_t)0x00000020) /*!< received overrun error interrupt */
+#define SDIO_CMDRSPCMPL_INT ((uint32_t)0x00000040) /*!< command response received interrupt */
+#define SDIO_CMDCMPL_INT ((uint32_t)0x00000080) /*!< command sent interrupt */
+#define SDIO_DTCMP_INT ((uint32_t)0x00000100) /*!< data sent interrupt */
+#define SDIO_SBITERR_INT ((uint32_t)0x00000200) /*!< start bit not detected on data bus interrupt */
+#define SDIO_DTBLKCMPL_INT ((uint32_t)0x00000400) /*!< data block sent/received interrupt */
+#define SDIO_DOCMD_INT ((uint32_t)0x00000800) /*!< command transfer in progress interrupt */
+#define SDIO_DOTX_INT ((uint32_t)0x00001000) /*!< data transmit in progress interrupt */
+#define SDIO_DORX_INT ((uint32_t)0x00002000) /*!< data receive in progress interrupt */
+#define SDIO_TXBUFH_INT ((uint32_t)0x00004000) /*!< transmit buf half empty interrupt */
+#define SDIO_RXBUFH_INT ((uint32_t)0x00008000) /*!< receive buf half full interrupt */
+#define SDIO_TXBUFF_INT ((uint32_t)0x00010000) /*!< transmit buf full interrupt */
+#define SDIO_RXBUFF_INT ((uint32_t)0x00020000) /*!< receive buf full interrupt */
+#define SDIO_TXBUFE_INT ((uint32_t)0x00040000) /*!< transmit buf empty interrupt */
+#define SDIO_RXBUFE_INT ((uint32_t)0x00080000) /*!< receive buf empty interrupt */
+#define SDIO_TXBUF_INT ((uint32_t)0x00100000) /*!< data available in transmit interrupt */
+#define SDIO_RXBUF_INT ((uint32_t)0x00200000) /*!< data available in receive interrupt */
+#define SDIO_SDIOIF_INT ((uint32_t)0x00400000) /*!< sdio interface received interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_flags_definition
+ * @brief sdio flag
+ * @{
+ */
+
+#define SDIO_CMDFAIL_FLAG ((uint32_t)0x00000001) /*!< command response received check failed flag */
+#define SDIO_DTFAIL_FLAG ((uint32_t)0x00000002) /*!< data block sent/received check failed flag */
+#define SDIO_CMDTIMEOUT_FLAG ((uint32_t)0x00000004) /*!< command response timerout flag */
+#define SDIO_DTTIMEOUT_FLAG ((uint32_t)0x00000008) /*!< data timeout flag */
+#define SDIO_TXERRU_FLAG ((uint32_t)0x00000010) /*!< transmit underrun error flag */
+#define SDIO_RXERRO_FLAG ((uint32_t)0x00000020) /*!< received overrun error flag */
+#define SDIO_CMDRSPCMPL_FLAG ((uint32_t)0x00000040) /*!< command response received flag */
+#define SDIO_CMDCMPL_FLAG ((uint32_t)0x00000080) /*!< command sent flag */
+#define SDIO_DTCMPL_FLAG ((uint32_t)0x00000100) /*!< data sent flag */
+#define SDIO_SBITERR_FLAG ((uint32_t)0x00000200) /*!< start bit not detected on data bus flag */
+#define SDIO_DTBLKCMPL_FLAG ((uint32_t)0x00000400) /*!< data block sent/received flag */
+#define SDIO_DOCMD_FLAG ((uint32_t)0x00000800) /*!< command transfer in progress flag */
+#define SDIO_DOTX_FLAG ((uint32_t)0x00001000) /*!< data transmit in progress flag */
+#define SDIO_DORX_FLAG ((uint32_t)0x00002000) /*!< data receive in progress flag */
+#define SDIO_TXBUFH_FLAG ((uint32_t)0x00004000) /*!< transmit buf half empty flag */
+#define SDIO_RXBUFH_FLAG ((uint32_t)0x00008000) /*!< receive buf half full flag */
+#define SDIO_TXBUFF_FLAG ((uint32_t)0x00010000) /*!< transmit buf full flag */
+#define SDIO_RXBUFF_FLAG ((uint32_t)0x00020000) /*!< receive buf full flag */
+#define SDIO_TXBUFE_FLAG ((uint32_t)0x00040000) /*!< transmit buf empty flag */
+#define SDIO_RXBUFE_FLAG ((uint32_t)0x00080000) /*!< receive buf empty flag */
+#define SDIO_TXBUF_FLAG ((uint32_t)0x00100000) /*!< data available in transmit flag */
+#define SDIO_RXBUF_FLAG ((uint32_t)0x00200000) /*!< data available in receive flag */
+#define SDIO_SDIOIF_FLAG ((uint32_t)0x00400000) /*!< sdio interface received flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_exported_types
+ * @{
+ */
+
+/**
+ * @brief sdio power state
+ */
+typedef enum
+{
+ SDIO_POWER_OFF = 0x00, /*!< power-off, clock to card is stopped */
+ SDIO_POWER_ON = 0x03 /*!< power-on, the card is clocked */
+} sdio_power_state_type;
+
+/**
+ * @brief sdio edge phase
+ */
+typedef enum
+{
+ SDIO_CLOCK_EDGE_RISING = 0x00, /*!< sdio bus clock generated on the rising edge of the master clock */
+ SDIO_CLOCK_EDGE_FALLING = 0x01 /*!< sdio bus clock generated on the falling edge of the master clock */
+} sdio_edge_phase_type;
+
+/**
+ * @brief sdio bus width
+ */
+typedef enum
+{
+ SDIO_BUS_WIDTH_D1 = 0x00, /*!< sdio wide bus select 1-bit */
+ SDIO_BUS_WIDTH_D4 = 0x01, /*!< sdio wide bus select 4-bit */
+ SDIO_BUS_WIDTH_D8 = 0x02 /*!< sdio wide bus select 8-bit */
+} sdio_bus_width_type;
+
+/**
+ * @brief sdio response type
+ */
+typedef enum
+{
+ SDIO_RESPONSE_NO = 0x00, /*!< no response */
+ SDIO_RESPONSE_SHORT = 0x01, /*!< short response */
+ SDIO_RESPONSE_LONG = 0x03 /*!< long response */
+} sdio_reponse_type;
+
+/**
+ * @brief sdio wait type
+ */
+typedef enum
+{
+ SDIO_WAIT_FOR_NO = 0x00, /*!< no wait */
+ SDIO_WAIT_FOR_INT = 0x01, /*!< wait interrupt request */
+ SDIO_WAIT_FOR_PEND = 0x02 /*!< wait end of transfer */
+} sdio_wait_type;
+
+/**
+ * @brief sdio response register index
+ */
+typedef enum
+{
+ SDIO_RSP1_INDEX = 0x00, /*!< response index 1, corresponding to sdio_rsp register 1 */
+ SDIO_RSP2_INDEX = 0x01, /*!< response index 2, corresponding to sdio_rsp register 2 */
+ SDIO_RSP3_INDEX = 0x02, /*!< response index 3, corresponding to sdio_rsp register 3 */
+ SDIO_RSP4_INDEX = 0x03 /*!< response index 4, corresponding to sdio_rsp register 4 */
+} sdio_rsp_index_type;
+
+/**
+ * @brief sdio data block size
+ */
+typedef enum
+{
+ SDIO_DATA_BLOCK_SIZE_1B = 0x00, /*!< data block size 1 byte */
+ SDIO_DATA_BLOCK_SIZE_2B = 0x01, /*!< data block size 2 bytes */
+ SDIO_DATA_BLOCK_SIZE_4B = 0x02, /*!< data block size 4 bytes */
+ SDIO_DATA_BLOCK_SIZE_8B = 0x03, /*!< data block size 8 bytes */
+ SDIO_DATA_BLOCK_SIZE_16B = 0x04, /*!< data block size 16 bytes */
+ SDIO_DATA_BLOCK_SIZE_32B = 0x05, /*!< data block size 32 bytes */
+ SDIO_DATA_BLOCK_SIZE_64B = 0x06, /*!< data block size 64 bytes */
+ SDIO_DATA_BLOCK_SIZE_128B = 0x07, /*!< data block size 128 bytes */
+ SDIO_DATA_BLOCK_SIZE_256B = 0x08, /*!< data block size 256 bytes */
+ SDIO_DATA_BLOCK_SIZE_512B = 0x09, /*!< data block size 512 bytes */
+ SDIO_DATA_BLOCK_SIZE_1024B = 0x0A, /*!< data block size 1024 bytes */
+ SDIO_DATA_BLOCK_SIZE_2048B = 0x0B, /*!< data block size 2048 bytes */
+ SDIO_DATA_BLOCK_SIZE_4096B = 0x0C, /*!< data block size 4096 bytes */
+ SDIO_DATA_BLOCK_SIZE_8192B = 0x0D, /*!< data block size 8192 bytes */
+ SDIO_DATA_BLOCK_SIZE_16384B = 0x0E /*!< data block size 16384 bytes */
+} sdio_block_size_type;
+
+/**
+ * @brief sdio data transfer mode
+ */
+typedef enum
+{
+ SDIO_DATA_BLOCK_TRANSFER = 0x00, /*!< the sdio block transfer mode */
+ SDIO_DATA_STREAM_TRANSFER = 0x01 /*!< the sdio stream transfer mode */
+} sdio_transfer_mode_type;
+
+/**
+ * @brief sdio data transfer direction
+ */
+typedef enum
+{
+ SDIO_DATA_TRANSFER_TO_CARD = 0x00, /*!< the sdio controller write */
+ SDIO_DATA_TRANSFER_TO_CONTROLLER = 0x01 /*!< the sdio controller read */
+} sdio_transfer_direction_type;
+
+/**
+ * @brief sdio read wait mode
+ */
+typedef enum
+{
+ SDIO_READ_WAIT_CONTROLLED_BY_D2 = 0x00, /*!< the sdio read wait on data2 line */
+ SDIO_READ_WAIT_CONTROLLED_BY_CK = 0x01 /*!< the sdio read wait on clock line */
+} sdio_read_wait_mode_type;
+
+/**
+ * @brief sdio command structure
+ */
+typedef struct
+{
+ uint32_t argument; /*!< the sdio command argument is sent to a card as part of command message */
+ uint8_t cmd_index; /*!< the sdio command index */
+ sdio_reponse_type rsp_type; /*!< the sdio response type */
+ sdio_wait_type wait_type; /*!< the sdio wait for interrupt request is enabled or disable */
+} sdio_command_struct_type;
+
+/**
+ * @brief sdio data structure
+ */
+typedef struct
+{
+ uint32_t timeout; /*!< the sdio data timeout period in car bus clock periods */
+ uint32_t data_length; /*!< the sdio data length */
+ sdio_block_size_type block_size; /*!< the sdio data block size of block transfer mode */
+ sdio_transfer_mode_type transfer_mode; /*!< the sdio transfer mode, block or stream */
+ sdio_transfer_direction_type transfer_direction; /*!< the sdio data transfer direction */
+} sdio_data_struct_type;
+
+/**
+ * @brief type define sdio register all
+ */
+typedef struct
+{
+ /**
+ * @brief sdio pwrctrl register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t pwrctrl;
+ struct
+ {
+ __IO uint32_t ps : 2; /* [1:0] */
+ __IO uint32_t reserved1 : 30;/* [31:2] */
+ } pwrctrl_bit;
+ };
+
+ /**
+ * @brief sdio clkctrl register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t clkctrl;
+ struct
+ {
+ __IO uint32_t clkdiv_l : 8; /* [7:0] */
+ __IO uint32_t clkoen : 1; /* [8] */
+ __IO uint32_t pwrsven : 1; /* [9] */
+ __IO uint32_t bypsen : 1; /* [10] */
+ __IO uint32_t busws : 2; /* [12:11] */
+ __IO uint32_t clkegs : 1; /* [13] */
+ __IO uint32_t hfcen : 1; /* [14] */
+ __IO uint32_t clkdiv_h : 2; /* [16:15] */
+ __IO uint32_t reserved1 : 15;/* [31:17] */
+ } clkctrl_bit;
+ };
+
+ /**
+ * @brief sdio argu register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t argu;
+ struct
+ {
+ __IO uint32_t argu : 32;/* [31:0] */
+ } argu_bit;
+ };
+
+ /**
+ * @brief sdio cmdctrl register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t cmdctrl;
+ struct
+ {
+ __IO uint32_t cmdidx : 6; /* [5:0] */
+ __IO uint32_t rspwt : 2; /* [7:6] */
+ __IO uint32_t intwt : 1; /* [8] */
+ __IO uint32_t pndwt : 1; /* [9] */
+ __IO uint32_t ccsmen : 1; /* [10] */
+ __IO uint32_t iosusp : 1; /* [11] */
+ __IO uint32_t reserved1 : 20;/* [31:12] */
+ } cmdctrl_bit;
+ };
+
+ /**
+ * @brief sdio rspcmd register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t rspcmd;
+ struct
+ {
+ __IO uint32_t rspcmd : 6; /* [5:0] */
+ __IO uint32_t reserved1 : 26;/* [31:6] */
+ } rspcmd_bit;
+ };
+
+ /**
+ * @brief sdio rsp1 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t rsp1;
+ struct
+ {
+ __IO uint32_t cardsts1 : 32;/* [31:0] */
+ } rsp1_bit;
+ };
+
+ /**
+ * @brief sdio rsp2 register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t rsp2;
+ struct
+ {
+ __IO uint32_t cardsts2 : 32;/* [31:0] */
+ } rsp2_bit;
+ };
+
+ /**
+ * @brief sdio rsp3 register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t rsp3;
+ struct
+ {
+ __IO uint32_t cardsts3 : 32;/* [31:0] */
+ } rsp3_bit;
+ };
+
+ /**
+ * @brief sdio rsp4 register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t rsp4;
+ struct
+ {
+ __IO uint32_t cardsts4 : 32;/* [31:0] */
+ } rsp4_bit;
+ };
+
+ /**
+ * @brief sdio dttmr register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t dttmr;
+ struct
+ {
+ __IO uint32_t timeout : 32;/* [31:0] */
+ } dttmr_bit;
+ };
+
+ /**
+ * @brief sdio dtlen register, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t dtlen;
+ struct
+ {
+ __IO uint32_t dtlen : 25;/* [24:0] */
+ __IO uint32_t reserved1 : 7; /* [31:25] */
+ } dtlen_bit;
+ };
+
+ /**
+ * @brief sdio dtctrl register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t dtctrl;
+ struct
+ {
+ __IO uint32_t tfren : 1; /* [0] */
+ __IO uint32_t tfrdir : 1; /* [1] */
+ __IO uint32_t tfrmode : 1; /* [2] */
+ __IO uint32_t dmaen : 1; /* [3] */
+ __IO uint32_t blksize : 4; /* [7:4] */
+ __IO uint32_t rdwtstart : 1; /* [8] */
+ __IO uint32_t rdwtstop : 1; /* [9] */
+ __IO uint32_t rdwtmode : 1; /* [10] */
+ __IO uint32_t ioen : 1; /* [11] */
+ __IO uint32_t reserved1 : 20;/* [31:12] */
+ } dtctrl_bit;
+ };
+
+ /**
+ * @brief sdio dtcnt register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t dtcnt;
+ struct
+ {
+ __IO uint32_t cnt : 25;/* [24:0] */
+ __IO uint32_t reserved1 : 7; /* [31:25] */
+ } dtcnt_bit;
+ };
+
+ /**
+ * @brief sdio sts register, offset:0x34
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t cmdfail : 1; /* [0] */
+ __IO uint32_t dtfail : 1; /* [1] */
+ __IO uint32_t cmdtimeout : 1; /* [2] */
+ __IO uint32_t dttimeout : 1; /* [3] */
+ __IO uint32_t txerru : 1; /* [4] */
+ __IO uint32_t rxerro : 1; /* [5] */
+ __IO uint32_t cmdrspcmpl : 1; /* [6] */
+ __IO uint32_t cmdcmpl : 1; /* [7] */
+ __IO uint32_t dtcmpl : 1; /* [8] */
+ __IO uint32_t sbiterr : 1; /* [9] */
+ __IO uint32_t dtblkcmpl : 1; /* [10] */
+ __IO uint32_t docmd : 1; /* [11] */
+ __IO uint32_t dotx : 1; /* [12] */
+ __IO uint32_t dorx : 1; /* [13] */
+ __IO uint32_t txbufh : 1; /* [14] */
+ __IO uint32_t rxbufh : 1; /* [15] */
+ __IO uint32_t txbuff : 1; /* [16] */
+ __IO uint32_t rxbuff : 1; /* [17] */
+ __IO uint32_t txbufe : 1; /* [18] */
+ __IO uint32_t rxbufe : 1; /* [19] */
+ __IO uint32_t txbuf : 1; /* [20] */
+ __IO uint32_t rxbuf : 1; /* [21] */
+ __IO uint32_t ioif : 1; /* [22] */
+ __IO uint32_t reserved1 : 9; /* [31:23] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief sdio intclr register, offset:0x38
+ */
+ union
+ {
+ __IO uint32_t intclr;
+ struct
+ {
+ __IO uint32_t cmdfail : 1; /* [0] */
+ __IO uint32_t dtfail : 1; /* [1] */
+ __IO uint32_t cmdtimeout : 1; /* [2] */
+ __IO uint32_t dttimeout : 1; /* [3] */
+ __IO uint32_t txerru : 1; /* [4] */
+ __IO uint32_t rxerro : 1; /* [5] */
+ __IO uint32_t cmdrspcmpl : 1; /* [6] */
+ __IO uint32_t cmdcmpl : 1; /* [7] */
+ __IO uint32_t dtcmpl : 1; /* [8] */
+ __IO uint32_t sbiterr : 1; /* [9] */
+ __IO uint32_t dtblkcmpl : 1; /* [10] */
+ __IO uint32_t reserved1 : 11;/* [21:11] */
+ __IO uint32_t ioif : 1; /* [22] */
+ __IO uint32_t reserved2 : 9; /* [31:23] */
+ } intclr_bit;
+ };
+
+ /**
+ * @brief sdio inten register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t inten;
+ struct
+ {
+ __IO uint32_t cmdfailien : 1; /* [0] */
+ __IO uint32_t dtfailien : 1; /* [1] */
+ __IO uint32_t cmdtimeoutien : 1; /* [2] */
+ __IO uint32_t dttimeoutien : 1; /* [3] */
+ __IO uint32_t txerruien : 1; /* [4] */
+ __IO uint32_t rxerroien : 1; /* [5] */
+ __IO uint32_t cmdrspcmplien : 1; /* [6] */
+ __IO uint32_t cmdcmplien : 1; /* [7] */
+ __IO uint32_t dtcmplien : 1; /* [8] */
+ __IO uint32_t sbiterrien : 1; /* [9] */
+ __IO uint32_t dtblkcmplien : 1; /* [10] */
+ __IO uint32_t docmdien : 1; /* [11] */
+ __IO uint32_t dotxien : 1; /* [12] */
+ __IO uint32_t dorxien : 1; /* [13] */
+ __IO uint32_t txbufhien : 1; /* [14] */
+ __IO uint32_t rxbufhien : 1; /* [15] */
+ __IO uint32_t txbuffien : 1; /* [16] */
+ __IO uint32_t rxbuffien : 1; /* [17] */
+ __IO uint32_t txbufeien : 1; /* [18] */
+ __IO uint32_t rxbufeien : 1; /* [19] */
+ __IO uint32_t txbufien : 1; /* [20] */
+ __IO uint32_t rxbufien : 1; /* [21] */
+ __IO uint32_t ioifien : 1; /* [22] */
+ __IO uint32_t reserved1 : 9; /* [31:23] */
+ } inten_bit;
+ };
+
+ /**
+ * @brief sdio reserved1 register, offset:0x40~0x44
+ */
+ __IO uint32_t reserved1[2];
+
+ /**
+ * @brief sdio bufcnt register, offset:0x48
+ */
+ union
+ {
+ __IO uint32_t bufcnt;
+ struct
+ {
+ __IO uint32_t cnt : 24;/* [23:0] */
+ __IO uint32_t reserved1 : 8; /* [31:24] */
+ } bufcnt_bit;
+ };
+
+ /**
+ * @brief sdio reserved2 register, offset:0x4C~0x7C
+ */
+ __IO uint32_t reserved2[13];
+
+ /**
+ * @brief sdio buf register, offset:0x80
+ */
+ union
+ {
+ __IO uint32_t buf;
+ struct
+ {
+ __IO uint32_t dt : 32;/* [31:0] */
+ } buf_bit;
+ };
+
+} sdio_type;
+
+/**
+ * @}
+ */
+
+#define SDIO1 ((sdio_type *) SDIO1_BASE)
+#define SDIO2 ((sdio_type *) SDIO2_BASE)
+
+/** @defgroup SDIO_exported_functions
+ * @{
+ */
+
+void sdio_reset(sdio_type *sdio_x);
+void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state);
+flag_status sdio_power_status_get(sdio_type *sdio_x);
+void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg);
+void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width);
+void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state);
+void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state);
+flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag);
+void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag);
+void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct);
+void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
+uint8_t sdio_command_response_get(sdio_type *sdio_x);
+uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index);
+void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct);
+void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
+uint32_t sdio_data_counter_get(sdio_type *sdio_x);
+uint32_t sdio_data_read(sdio_type *sdio_x);
+uint32_t sdio_buffer_counter_get(sdio_type *sdio_x);
+void sdio_data_write(sdio_type *sdio_x, uint32_t data);
+void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode);
+void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state);
+void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state);
+void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_spi.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_spi.h
new file mode 100644
index 0000000..6c65846
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_spi.h
@@ -0,0 +1,505 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_spi.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 spi header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_SPI_H
+#define __AT32F435_437_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/**
+ * @defgroup SPI_I2S_flags_definition
+ * @brief spi i2s flag
+ * @{
+ */
+
+#define SPI_I2S_RDBF_FLAG 0x0001 /*!< spi or i2s receive data buffer full flag */
+#define SPI_I2S_TDBE_FLAG 0x0002 /*!< spi or i2s transmit data buffer empty flag */
+#define I2S_ACS_FLAG 0x0004 /*!< i2s audio channel state flag */
+#define I2S_TUERR_FLAG 0x0008 /*!< i2s transmitter underload error flag */
+#define SPI_CCERR_FLAG 0x0010 /*!< spi crc calculation error flag */
+#define SPI_MMERR_FLAG 0x0020 /*!< spi master mode error flag */
+#define SPI_I2S_ROERR_FLAG 0x0040 /*!< spi or i2s receiver overflow error flag */
+#define SPI_I2S_BF_FLAG 0x0080 /*!< spi or i2s busy flag */
+#define SPI_CSPAS_FLAG 0x0100 /*!< spi cs pulse abnormal setting fiag */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_I2S_interrupts_definition
+ * @brief spi i2s interrupt
+ * @{
+ */
+
+#define SPI_I2S_ERROR_INT 0x0020 /*!< error interrupt */
+#define SPI_I2S_RDBF_INT 0x0040 /*!< receive data buffer full interrupt */
+#define SPI_I2S_TDBE_INT 0x0080 /*!< transmit data buffer empty interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_exported_types
+ * @{
+ */
+
+/**
+ * @brief spi frame bit num type
+ */
+typedef enum
+{
+ SPI_FRAME_8BIT = 0x00, /*!< 8-bit data frame format */
+ SPI_FRAME_16BIT = 0x01 /*!< 16-bit data frame format */
+} spi_frame_bit_num_type;
+
+/**
+ * @brief spi master/slave mode type
+ */
+typedef enum
+{
+ SPI_MODE_SLAVE = 0x00, /*!< select as slave mode */
+ SPI_MODE_MASTER = 0x01 /*!< select as master mode */
+} spi_master_slave_mode_type;
+
+/**
+ * @brief spi clock polarity (clkpol) type
+ */
+typedef enum
+{
+ SPI_CLOCK_POLARITY_LOW = 0x00, /*!< sck keeps low at idle state */
+ SPI_CLOCK_POLARITY_HIGH = 0x01 /*!< sck keeps high at idle state */
+} spi_clock_polarity_type;
+
+/**
+ * @brief spi clock phase (clkpha) type
+ */
+typedef enum
+{
+ SPI_CLOCK_PHASE_1EDGE = 0x00, /*!< data capture start from the first clock edge */
+ SPI_CLOCK_PHASE_2EDGE = 0x01 /*!< data capture start from the second clock edge */
+} spi_clock_phase_type;
+
+/**
+ * @brief spi cs mode type
+ */
+typedef enum
+{
+ SPI_CS_HARDWARE_MODE = 0x00, /*!< cs is hardware mode */
+ SPI_CS_SOFTWARE_MODE = 0x01 /*!< cs is software mode */
+} spi_cs_mode_type;
+
+/**
+ * @brief spi master clock frequency division type
+ */
+typedef enum
+{
+ SPI_MCLK_DIV_2 = 0x00, /*!< master clock frequency division 2 */
+ SPI_MCLK_DIV_3 = 0x0A, /*!< master clock frequency division 3 */
+ SPI_MCLK_DIV_4 = 0x01, /*!< master clock frequency division 4 */
+ SPI_MCLK_DIV_8 = 0x02, /*!< master clock frequency division 8 */
+ SPI_MCLK_DIV_16 = 0x03, /*!< master clock frequency division 16 */
+ SPI_MCLK_DIV_32 = 0x04, /*!< master clock frequency division 32 */
+ SPI_MCLK_DIV_64 = 0x05, /*!< master clock frequency division 64 */
+ SPI_MCLK_DIV_128 = 0x06, /*!< master clock frequency division 128 */
+ SPI_MCLK_DIV_256 = 0x07, /*!< master clock frequency division 256 */
+ SPI_MCLK_DIV_512 = 0x08, /*!< master clock frequency division 512 */
+ SPI_MCLK_DIV_1024 = 0x09 /*!< master clock frequency division 1024 */
+} spi_mclk_freq_div_type;
+
+/**
+ * @brief spi transmit first bit (lsb/msb) type
+ */
+typedef enum
+{
+ SPI_FIRST_BIT_MSB = 0x00, /*!< the frame format is msb first */
+ SPI_FIRST_BIT_LSB = 0x01 /*!< the frame format is lsb first */
+} spi_first_bit_type;
+
+/**
+ * @brief spi transmission mode type
+ */
+typedef enum
+{
+ SPI_TRANSMIT_FULL_DUPLEX = 0x00, /*!< dual line unidirectional full-duplex mode(slben = 0 and ora = 0) */
+ SPI_TRANSMIT_SIMPLEX_RX = 0x01, /*!< dual line unidirectional simplex receive-only mode(slben = 0 and ora = 1) */
+ SPI_TRANSMIT_HALF_DUPLEX_RX = 0x02, /*!< single line bidirectional half duplex mode-receiving(slben = 1 and slbtd = 0) */
+ SPI_TRANSMIT_HALF_DUPLEX_TX = 0x03 /*!< single line bidirectional half duplex mode-transmitting(slben = 1 and slbtd = 1) */
+} spi_transmission_mode_type;
+
+/**
+ * @brief spi crc direction type
+ */
+typedef enum
+{
+ SPI_CRC_RX = 0x0014, /*!< crc direction is rx */
+ SPI_CRC_TX = 0x0018 /*!< crc direction is tx */
+} spi_crc_direction_type;
+
+/**
+ * @brief spi single line bidirectional direction type
+ */
+typedef enum
+{
+ SPI_HALF_DUPLEX_DIRECTION_RX = 0x00, /*!< single line bidirectional half duplex mode direction: receive(slbtd = 0) */
+ SPI_HALF_DUPLEX_DIRECTION_TX = 0x01 /*!< single line bidirectional half duplex mode direction: transmit(slbtd = 1) */
+} spi_half_duplex_direction_type;
+
+/**
+ * @brief spi software cs internal level type
+ */
+typedef enum
+{
+ SPI_SWCS_INTERNAL_LEVEL_LOW = 0x00, /*!< internal level low */
+ SPI_SWCS_INTERNAL_LEVEL_HIGHT = 0x01 /*!< internal level high */
+} spi_software_cs_level_type;
+
+/**
+ * @brief i2s audio protocol type
+ */
+typedef enum
+{
+ I2S_AUDIO_PROTOCOL_PHILLIPS = 0x00, /*!< i2s philip standard */
+ I2S_AUDIO_PROTOCOL_MSB = 0x01, /*!< msb-justified standard */
+ I2S_AUDIO_PROTOCOL_LSB = 0x02, /*!< lsb-justified standard */
+ I2S_AUDIO_PROTOCOL_PCM_SHORT = 0x03, /*!< pcm standard-short frame */
+ I2S_AUDIO_PROTOCOL_PCM_LONG = 0x04 /*!< pcm standard-long frame */
+} i2s_audio_protocol_type;
+
+/**
+ * @brief i2s audio frequency type
+ */
+typedef enum
+{
+ I2S_AUDIO_FREQUENCY_DEFAULT = 2, /*!< i2s audio sampling frequency default */
+ I2S_AUDIO_FREQUENCY_8K = 8000, /*!< i2s audio sampling frequency 8k */
+ I2S_AUDIO_FREQUENCY_11_025K = 11025, /*!< i2s audio sampling frequency 11.025k */
+ I2S_AUDIO_FREQUENCY_16K = 16000, /*!< i2s audio sampling frequency 16k */
+ I2S_AUDIO_FREQUENCY_22_05K = 22050, /*!< i2s audio sampling frequency 22.05k */
+ I2S_AUDIO_FREQUENCY_32K = 32000, /*!< i2s audio sampling frequency 32k */
+ I2S_AUDIO_FREQUENCY_44_1K = 44100, /*!< i2s audio sampling frequency 44.1k */
+ I2S_AUDIO_FREQUENCY_48K = 48000, /*!< i2s audio sampling frequency 48k */
+ I2S_AUDIO_FREQUENCY_96K = 96000, /*!< i2s audio sampling frequency 96k */
+ I2S_AUDIO_FREQUENCY_192K = 192000 /*!< i2s audio sampling frequency 192k */
+} i2s_audio_sampling_freq_type;
+
+/**
+ * @brief i2s data bit num and channel bit num type
+ */
+typedef enum
+{
+ I2S_DATA_16BIT_CHANNEL_16BIT = 0x01, /*!< 16-bit data packed in 16-bit channel frame */
+ I2S_DATA_16BIT_CHANNEL_32BIT = 0x02, /*!< 16-bit data packed in 32-bit channel frame */
+ I2S_DATA_24BIT_CHANNEL_32BIT = 0x03, /*!< 24-bit data packed in 32-bit channel frame */
+ I2S_DATA_32BIT_CHANNEL_32BIT = 0x04 /*!< 32-bit data packed in 32-bit channel frame */
+} i2s_data_channel_format_type;
+
+/**
+ * @brief i2s operation mode type
+ */
+typedef enum
+{
+ I2S_MODE_SLAVE_TX = 0x00, /*!< slave transmission mode */
+ I2S_MODE_SLAVE_RX = 0x01, /*!< slave reception mode */
+ I2S_MODE_MASTER_TX = 0x02, /*!< master transmission mode */
+ I2S_MODE_MASTER_RX = 0x03 /*!< master reception mode */
+} i2s_operation_mode_type;
+
+/**
+ * @brief i2s clock polarity type
+ */
+typedef enum
+{
+ I2S_CLOCK_POLARITY_LOW = 0x00, /*!< i2s clock steady state is low level */
+ I2S_CLOCK_POLARITY_HIGH = 0x01 /*!< i2s clock steady state is high level */
+} i2s_clock_polarity_type;
+
+/**
+ * @brief spi init type
+ */
+typedef struct
+{
+ spi_transmission_mode_type transmission_mode; /*!< transmission mode selection */
+ spi_master_slave_mode_type master_slave_mode; /*!< master or slave mode selection */
+ spi_mclk_freq_div_type mclk_freq_division; /*!< master clock frequency division selection */
+ spi_first_bit_type first_bit_transmission;/*!< transmit lsb or msb selection */
+ spi_frame_bit_num_type frame_bit_num; /*!< frame bit num 8 or 16 bit selection */
+ spi_clock_polarity_type clock_polarity; /*!< clock polarity selection */
+ spi_clock_phase_type clock_phase; /*!< clock phase selection */
+ spi_cs_mode_type cs_mode_selection; /*!< hardware or software cs mode selection */
+} spi_init_type;
+
+/**
+ * @brief i2s init type
+ */
+typedef struct
+{
+ i2s_operation_mode_type operation_mode; /*!< operation mode selection */
+ i2s_audio_protocol_type audio_protocol; /*!< audio protocol selection */
+ i2s_audio_sampling_freq_type audio_sampling_freq; /*!< audio frequency selection */
+ i2s_data_channel_format_type data_channel_format; /*!< data bit num and channel bit num selection */
+ i2s_clock_polarity_type clock_polarity; /*!< clock polarity selection */
+ confirm_state mclk_output_enable; /*!< mclk_output selection */
+} i2s_init_type;
+
+/**
+ * @brief type define spi register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief spi ctrl1 register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t clkpha : 1; /* [0] */
+ __IO uint32_t clkpol : 1; /* [1] */
+ __IO uint32_t msten : 1; /* [2] */
+ __IO uint32_t mdiv_l : 3; /* [5:3] */
+ __IO uint32_t spien : 1; /* [6] */
+ __IO uint32_t ltf : 1; /* [7] */
+ __IO uint32_t swcsil : 1; /* [8] */
+ __IO uint32_t swcsen : 1; /* [9] */
+ __IO uint32_t ora : 1; /* [10] */
+ __IO uint32_t fbn : 1; /* [11] */
+ __IO uint32_t ntc : 1; /* [12] */
+ __IO uint32_t ccen : 1; /* [13] */
+ __IO uint32_t slbtd : 1; /* [14] */
+ __IO uint32_t slben : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief spi ctrl2 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t dmaren : 1; /* [0] */
+ __IO uint32_t dmaten : 1; /* [1] */
+ __IO uint32_t hwcsoe : 1; /* [2] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t tien : 1; /* [4] */
+ __IO uint32_t errie : 1; /* [5] */
+ __IO uint32_t rdbfie : 1; /* [6] */
+ __IO uint32_t tdbeie : 1; /* [7] */
+ __IO uint32_t mdiv_h : 1; /* [8] */
+ __IO uint32_t mdiv3en : 1; /* [9] */
+ __IO uint32_t reserved2 : 22;/* [31:10] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief spi sts register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t rdbf : 1; /* [0] */
+ __IO uint32_t tdbe : 1; /* [1] */
+ __IO uint32_t acs : 1; /* [2] */
+ __IO uint32_t tuerr : 1; /* [3] */
+ __IO uint32_t ccerr : 1; /* [4] */
+ __IO uint32_t mmerr : 1; /* [5] */
+ __IO uint32_t roerr : 1; /* [6] */
+ __IO uint32_t bf : 1; /* [7] */
+ __IO uint32_t cspas : 1; /* [8] */
+ __IO uint32_t reserved1 : 23;/* [31:9] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief spi dt register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t dt;
+ struct
+ {
+ __IO uint32_t dt : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } dt_bit;
+ };
+
+ /**
+ * @brief spi cpoly register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t cpoly;
+ struct
+ {
+ __IO uint32_t cpoly : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cpoly_bit;
+ };
+
+ /**
+ * @brief spi rcrc register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t rcrc;
+ struct
+ {
+ __IO uint32_t rcrc : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } rcrc_bit;
+ };
+
+ /**
+ * @brief spi tcrc register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t tcrc;
+ struct
+ {
+ __IO uint32_t tcrc : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } tcrc_bit;
+ };
+
+ /**
+ * @brief spi i2sctrl register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t i2sctrl;
+ struct
+ {
+ __IO uint32_t i2scbn : 1; /* [0] */
+ __IO uint32_t i2sdbn : 2; /* [2:1] */
+ __IO uint32_t i2sclkpol : 1; /* [3] */
+ __IO uint32_t stdsel : 2; /* [5:4] */
+ __IO uint32_t reserved1 : 1; /* [6] */
+ __IO uint32_t pcmfssel : 1; /* [7] */
+ __IO uint32_t opersel : 2; /* [9:8] */
+ __IO uint32_t i2sen : 1; /* [10] */
+ __IO uint32_t i2smsel : 1; /* [11] */
+ __IO uint32_t reserved2 : 20;/* [31:12] */
+ } i2sctrl_bit;
+ };
+
+ /**
+ * @brief spi i2sclk register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t i2sclk;
+ struct
+ {
+ __IO uint32_t i2sdiv_l : 8; /* [7:0] */
+ __IO uint32_t i2sodd : 1; /* [8] */
+ __IO uint32_t i2smclkoe : 1; /* [9] */
+ __IO uint32_t i2sdiv_h : 2; /* [11:10] */
+ __IO uint32_t reserved1 : 20;/* [31:12] */
+ } i2sclk_bit;
+ };
+
+} spi_type;
+
+/**
+ * @}
+ */
+
+#define SPI1 ((spi_type *) SPI1_BASE)
+#define SPI2 ((spi_type *) SPI2_BASE)
+#define SPI3 ((spi_type *) SPI3_BASE)
+#define SPI4 ((spi_type *) SPI4_BASE)
+#define I2S2EXT ((spi_type *) I2S2EXT_BASE)
+#define I2S3EXT ((spi_type *) I2S3EXT_BASE)
+
+/** @defgroup SPI_exported_functions
+ * @{
+ */
+
+void spi_i2s_reset(spi_type *spi_x);
+void spi_default_para_init(spi_init_type* spi_init_struct);
+void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct);
+void spi_ti_mode_enable(spi_type* spi_x, confirm_state new_state);
+void spi_crc_next_transmit(spi_type* spi_x);
+void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly);
+uint16_t spi_crc_polynomial_get(spi_type* spi_x);
+void spi_crc_enable(spi_type* spi_x, confirm_state new_state);
+uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction);
+void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state);
+void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level);
+void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num);
+void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction);
+void spi_enable(spi_type* spi_x, confirm_state new_state);
+void i2s_default_para_init(i2s_init_type* i2s_init_struct);
+void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct);
+void i2s_enable(spi_type* spi_x, confirm_state new_state);
+void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state);
+void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state);
+void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state);
+void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data);
+uint16_t spi_i2s_data_receive(spi_type* spi_x);
+flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
+void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_tmr.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_tmr.h
new file mode 100644
index 0000000..4e5e86b
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_tmr.h
@@ -0,0 +1,1017 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_tmr.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 tmr header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_TMR_H
+#define __AT32F435_437_TMR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup TMR
+ * @{
+ */
+
+/** @defgroup TMR_flags_definition
+ * @brief tmr flag
+ * @{
+ */
+
+#define TMR_OVF_FLAG ((uint32_t)0x000001) /*!< tmr flag overflow */
+#define TMR_C1_FLAG ((uint32_t)0x000002) /*!< tmr flag channel 1 */
+#define TMR_C2_FLAG ((uint32_t)0x000004) /*!< tmr flag channel 2 */
+#define TMR_C3_FLAG ((uint32_t)0x000008) /*!< tmr flag channel 3 */
+#define TMR_C4_FLAG ((uint32_t)0x000010) /*!< tmr flag channel 4 */
+#define TMR_HALL_FLAG ((uint32_t)0x000020) /*!< tmr flag hall */
+#define TMR_TRIGGER_FLAG ((uint32_t)0x000040) /*!< tmr flag trigger */
+#define TMR_BRK_FLAG ((uint32_t)0x000080) /*!< tmr flag brake */
+#define TMR_C1_RECAPTURE_FLAG ((uint32_t)0x000200) /*!< tmr flag channel 1 recapture */
+#define TMR_C2_RECAPTURE_FLAG ((uint32_t)0x000400) /*!< tmr flag channel 2 recapture */
+#define TMR_C3_RECAPTURE_FLAG ((uint32_t)0x000800) /*!< tmr flag channel 3 recapture */
+#define TMR_C4_RECAPTURE_FLAG ((uint32_t)0x001000) /*!< tmr flag channel 4 recapture */
+
+/**
+ * @}
+ */
+
+/** @defgroup TMR_interrupt_select_type_definition
+ * @brief tmr interrupt select type
+ * @{
+ */
+
+#define TMR_OVF_INT ((uint32_t)0x000001) /*!< tmr interrupt overflow */
+#define TMR_C1_INT ((uint32_t)0x000002) /*!< tmr interrupt channel 1 */
+#define TMR_C2_INT ((uint32_t)0x000004) /*!< tmr interrupt channel 2 */
+#define TMR_C3_INT ((uint32_t)0x000008) /*!< tmr interrupt channel 3 */
+#define TMR_C4_INT ((uint32_t)0x000010) /*!< tmr interrupt channel 4 */
+#define TMR_HALL_INT ((uint32_t)0x000020) /*!< tmr interrupt hall */
+#define TMR_TRIGGER_INT ((uint32_t)0x000040) /*!< tmr interrupt trigger */
+#define TMR_BRK_INT ((uint32_t)0x000080) /*!< tmr interrupt brake */
+
+/**
+ * @}
+ */
+
+/** @defgroup TMR_exported_types
+ * @{
+ */
+
+/**
+ * @brief tmr clock division type
+ */
+typedef enum
+{
+ TMR_CLOCK_DIV1 = 0x00, /*!< tmr clock division 1 */
+ TMR_CLOCK_DIV2 = 0x01, /*!< tmr clock division 2 */
+ TMR_CLOCK_DIV4 = 0x02 /*!< tmr clock division 4 */
+} tmr_clock_division_type;
+
+/**
+ * @brief tmr counter mode type
+ */
+typedef enum
+{
+ TMR_COUNT_UP = 0x00, /*!< tmr counter mode up */
+ TMR_COUNT_DOWN = 0x01, /*!< tmr counter mode down */
+ TMR_COUNT_TWO_WAY_1 = 0x02, /*!< tmr counter mode two way 1 */
+ TMR_COUNT_TWO_WAY_2 = 0x04, /*!< tmr counter mode two way 2 */
+ TMR_COUNT_TWO_WAY_3 = 0x06 /*!< tmr counter mode two way 3 */
+} tmr_count_mode_type;
+
+/**
+ * @brief tmr primary mode select type
+ */
+typedef enum
+{
+ TMR_PRIMARY_SEL_RESET = 0x00, /*!< tmr primary mode select reset */
+ TMR_PRIMARY_SEL_ENABLE = 0x01, /*!< tmr primary mode select enable */
+ TMR_PRIMARY_SEL_OVERFLOW = 0x02, /*!< tmr primary mode select overflow */
+ TMR_PRIMARY_SEL_COMPARE = 0x03, /*!< tmr primary mode select compare */
+ TMR_PRIMARY_SEL_C1ORAW = 0x04, /*!< tmr primary mode select c1oraw */
+ TMR_PRIMARY_SEL_C2ORAW = 0x05, /*!< tmr primary mode select c2oraw */
+ TMR_PRIMARY_SEL_C3ORAW = 0x06, /*!< tmr primary mode select c3oraw */
+ TMR_PRIMARY_SEL_C4ORAW = 0x07 /*!< tmr primary mode select c4oraw */
+} tmr_primary_select_type;
+
+/**
+ * @brief tmr subordinate mode input select type
+ */
+typedef enum
+{
+ TMR_SUB_INPUT_SEL_IS0 = 0x00, /*!< subordinate mode input select is0 */
+ TMR_SUB_INPUT_SEL_IS1 = 0x01, /*!< subordinate mode input select is1 */
+ TMR_SUB_INPUT_SEL_IS2 = 0x02, /*!< subordinate mode input select is2 */
+ TMR_SUB_INPUT_SEL_IS3 = 0x03, /*!< subordinate mode input select is3 */
+ TMR_SUB_INPUT_SEL_C1INC = 0x04, /*!< subordinate mode input select c1inc */
+ TMR_SUB_INPUT_SEL_C1DF1 = 0x05, /*!< subordinate mode input select c1df1 */
+ TMR_SUB_INPUT_SEL_C2DF2 = 0x06, /*!< subordinate mode input select c2df2 */
+ TMR_SUB_INPUT_SEL_EXTIN = 0x07 /*!< subordinate mode input select extin */
+} sub_tmr_input_sel_type;
+
+/**
+ * @brief tmr subordinate mode select type
+ */
+typedef enum
+{
+ TMR_SUB_MODE_DIABLE = 0x00, /*!< subordinate mode disable */
+ TMR_SUB_ENCODER_MODE_A = 0x01, /*!< subordinate mode select encoder mode a */
+ TMR_SUB_ENCODER_MODE_B = 0x02, /*!< subordinate mode select encoder mode b */
+ TMR_SUB_ENCODER_MODE_C = 0x03, /*!< subordinate mode select encoder mode c */
+ TMR_SUB_RESET_MODE = 0x04, /*!< subordinate mode select reset */
+ TMR_SUB_HANG_MODE = 0x05, /*!< subordinate mode select hang */
+ TMR_SUB_TRIGGER_MODE = 0x06, /*!< subordinate mode select trigger */
+ TMR_SUB_EXTERNAL_CLOCK_MODE_A = 0x07 /*!< subordinate mode external clock mode a */
+} tmr_sub_mode_select_type;
+
+/**
+ * @brief tmr encoder mode type
+ */
+typedef enum
+{
+ TMR_ENCODER_MODE_A = TMR_SUB_ENCODER_MODE_A, /*!< tmr encoder mode a */
+ TMR_ENCODER_MODE_B = TMR_SUB_ENCODER_MODE_B, /*!< tmr encoder mode b */
+ TMR_ENCODER_MODE_C = TMR_SUB_ENCODER_MODE_C /*!< tmr encoder mode c */
+} tmr_encoder_mode_type;
+
+/**
+ * @brief tmr output control mode type
+ */
+typedef enum
+{
+ TMR_OUTPUT_CONTROL_OFF = 0x00, /*!< tmr output control mode off */
+ TMR_OUTPUT_CONTROL_HIGH = 0x01, /*!< tmr output control mode high */
+ TMR_OUTPUT_CONTROL_LOW = 0x02, /*!< tmr output control mode low */
+ TMR_OUTPUT_CONTROL_SWITCH = 0x03, /*!< tmr output control mode switch */
+ TMR_OUTPUT_CONTROL_FORCE_HIGH = 0x04, /*!< tmr output control mode force high */
+ TMR_OUTPUT_CONTROL_FORCE_LOW = 0x05, /*!< tmr output control mode force low */
+ TMR_OUTPUT_CONTROL_PWM_MODE_A = 0x06, /*!< tmr output control mode pwm a */
+ TMR_OUTPUT_CONTROL_PWM_MODE_B = 0x07 /*!< tmr output control mode pwm b */
+} tmr_output_control_mode_type;
+
+/**
+ * @brief tmr force output type
+ */
+typedef enum
+{
+ TMR_FORCE_OUTPUT_HIGH = TMR_OUTPUT_CONTROL_FORCE_HIGH, /*!< tmr force output high */
+ TMR_FORCE_OUTPUT_LOW = TMR_OUTPUT_CONTROL_FORCE_LOW /*!< tmr force output low */
+} tmr_force_output_type;
+
+/**
+ * @brief tmr output channel polarity type
+ */
+typedef enum
+{
+ TMR_OUTPUT_ACTIVE_HIGH = 0x00, /*!< tmr output channel polarity high */
+ TMR_OUTPUT_ACTIVE_LOW = 0x01 /*!< tmr output channel polarity low */
+} tmr_output_polarity_type;
+
+/**
+ * @brief tmr input channel polarity type
+ */
+typedef enum
+{
+ TMR_INPUT_RISING_EDGE = 0x00, /*!< tmr input channel polarity rising */
+ TMR_INPUT_FALLING_EDGE = 0x01, /*!< tmr input channel polarity falling */
+ TMR_INPUT_BOTH_EDGE = 0x03 /*!< tmr input channel polarity both edge */
+} tmr_input_polarity_type;
+
+/**
+ * @brief tmr channel select type
+ */
+typedef enum
+{
+ TMR_SELECT_CHANNEL_1 = 0x00, /*!< tmr channel select channel 1 */
+ TMR_SELECT_CHANNEL_1C = 0x01, /*!< tmr channel select channel 1 complementary */
+ TMR_SELECT_CHANNEL_2 = 0x02, /*!< tmr channel select channel 2 */
+ TMR_SELECT_CHANNEL_2C = 0x03, /*!< tmr channel select channel 2 complementary */
+ TMR_SELECT_CHANNEL_3 = 0x04, /*!< tmr channel select channel 3 */
+ TMR_SELECT_CHANNEL_3C = 0x05, /*!< tmr channel select channel 3 complementary */
+ TMR_SELECT_CHANNEL_4 = 0x06, /*!< tmr channel select channel 4 */
+ TMR_SELECT_CHANNEL_5 = 0x07 /*!< tmr channel select channel 5 */
+} tmr_channel_select_type;
+
+/**
+ * @brief tmr channel1 input connected type
+ */
+typedef enum
+{
+ TMR_CHANEL1_CONNECTED_C1IRAW = 0x00, /*!< channel1 pins is only connected to C1IRAW input */
+ TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR = 0x01 /*!< channel1/2/3 pins are connected to C1IRAW input after xored */
+} tmr_channel1_input_connected_type;
+
+/**
+ * @brief tmr input channel mapped type channel direction
+ */
+typedef enum
+{
+ TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */
+ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */
+ TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */
+} tmr_input_direction_mapped_type;
+
+/**
+ * @brief tmr input divider type
+ */
+typedef enum
+{
+ TMR_CHANNEL_INPUT_DIV_1 = 0x00, /*!< tmr channel input divider 1 */
+ TMR_CHANNEL_INPUT_DIV_2 = 0x01, /*!< tmr channel input divider 2 */
+ TMR_CHANNEL_INPUT_DIV_4 = 0x02, /*!< tmr channel input divider 4 */
+ TMR_CHANNEL_INPUT_DIV_8 = 0x03 /*!< tmr channel input divider 8 */
+} tmr_channel_input_divider_type;
+
+/**
+ * @brief tmr dma request source select type
+ */
+typedef enum
+{
+ TMR_DMA_REQUEST_BY_CHANNEL = 0x00, /*!< tmr dma request source select channel */
+ TMR_DMA_REQUEST_BY_OVERFLOW = 0x01 /*!< tmr dma request source select overflow */
+} tmr_dma_request_source_type;
+
+/**
+ * @brief tmr dma request type
+ */
+typedef enum
+{
+ TMR_OVERFLOW_DMA_REQUEST = 0x00000100, /*!< tmr dma request select overflow */
+ TMR_C1_DMA_REQUEST = 0x00000200, /*!< tmr dma request select channel 1 */
+ TMR_C2_DMA_REQUEST = 0x00000400, /*!< tmr dma request select channel 2 */
+ TMR_C3_DMA_REQUEST = 0x00000800, /*!< tmr dma request select channel 3 */
+ TMR_C4_DMA_REQUEST = 0x00001000, /*!< tmr dma request select channel 4 */
+ TMR_HALL_DMA_REQUEST = 0x00002000, /*!< tmr dma request select hall */
+ TMR_TRIGGER_DMA_REQUEST = 0x00004000 /*!< tmr dma request select trigger */
+} tmr_dma_request_type;
+
+/**
+ * @brief tmr event triggered by software type
+ */
+typedef enum
+{
+ TMR_OVERFLOW_SWTRIG = 0x00000001, /*!< tmr event triggered by software of overflow */
+ TMR_C1_SWTRIG = 0x00000002, /*!< tmr event triggered by software of channel 1 */
+ TMR_C2_SWTRIG = 0x00000004, /*!< tmr event triggered by software of channel 2 */
+ TMR_C3_SWTRIG = 0x00000008, /*!< tmr event triggered by software of channel 3 */
+ TMR_C4_SWTRIG = 0x00000010, /*!< tmr event triggered by software of channel 4 */
+ TMR_HALL_SWTRIG = 0x00000020, /*!< tmr event triggered by software of hall */
+ TMR_TRIGGER_SWTRIG = 0x00000040, /*!< tmr event triggered by software of trigger */
+ TMR_BRK_SWTRIG = 0x00000080 /*!< tmr event triggered by software of brake */
+}tmr_event_trigger_type;
+
+/**
+ * @brief tmr channel output fast type
+ */
+typedef enum
+{
+ TMR_CHANNEL1_OUTPUT_FAST = MAKE_VALUE(0x18, 2), /*!< tmr channel 1 output fast mode */
+ TMR_CHANNEL2_OUTPUT_FAST = MAKE_VALUE(0x18, 10), /*!< tmr channel 2 output fast mode */
+ TMR_CHANNEL3_OUTPUT_FAST = MAKE_VALUE(0x1c, 2), /*!< tmr channel 3 output fast mode */
+ TMR_CHANNEL4_OUTPUT_FAST = MAKE_VALUE(0x1c, 10) /*!< tmr channel 4 output fast mode */
+}tmr_channel_output_fast_type;
+
+/**
+ * @brief tmr polarity active type
+ */
+typedef enum
+{
+ TMR_POLARITY_ACTIVE_HIGH = 0x00, /*!< tmr polarity active high */
+ TMR_POLARITY_ACTIVE_LOW = 0x01, /*!< tmr polarity active low */
+ TMR_POLARITY_ACTIVE_BOTH = 0x02 /*!< tmr polarity active both high ande low */
+}tmr_polarity_active_type;
+
+/**
+ * @brief tmr external signal divider type
+ */
+typedef enum
+{
+ TMR_ES_FREQUENCY_DIV_1 = 0x00, /*!< tmr external signal frequency divider 1 */
+ TMR_ES_FREQUENCY_DIV_2 = 0x01, /*!< tmr external signal frequency divider 2 */
+ TMR_ES_FREQUENCY_DIV_4 = 0x02, /*!< tmr external signal frequency divider 4 */
+ TMR_ES_FREQUENCY_DIV_8 = 0x03 /*!< tmr external signal frequency divider 8 */
+}tmr_external_signal_divider_type;
+
+/**
+ * @brief tmr external signal polarity type
+ */
+typedef enum
+{
+ TMR_ES_POLARITY_NON_INVERTED = 0x00, /*!< tmr external signal polarity non-inerted */
+ TMR_ES_POLARITY_INVERTED = 0x01 /*!< tmr external signal polarity inerted */
+}tmr_external_signal_polarity_type;
+
+/**
+ * @brief tmr dma transfer length type
+ */
+typedef enum
+{
+ TMR_DMA_TRANSFER_1BYTE = 0x00, /*!< tmr dma transfer length 1 byte */
+ TMR_DMA_TRANSFER_2BYTES = 0x01, /*!< tmr dma transfer length 2 bytes */
+ TMR_DMA_TRANSFER_3BYTES = 0x02, /*!< tmr dma transfer length 3 bytes */
+ TMR_DMA_TRANSFER_4BYTES = 0x03, /*!< tmr dma transfer length 4 bytes */
+ TMR_DMA_TRANSFER_5BYTES = 0x04, /*!< tmr dma transfer length 5 bytes */
+ TMR_DMA_TRANSFER_6BYTES = 0x05, /*!< tmr dma transfer length 6 bytes */
+ TMR_DMA_TRANSFER_7BYTES = 0x06, /*!< tmr dma transfer length 7 bytes */
+ TMR_DMA_TRANSFER_8BYTES = 0x07, /*!< tmr dma transfer length 8 bytes */
+ TMR_DMA_TRANSFER_9BYTES = 0x08, /*!< tmr dma transfer length 9 bytes */
+ TMR_DMA_TRANSFER_10BYTES = 0x09, /*!< tmr dma transfer length 10 bytes */
+ TMR_DMA_TRANSFER_11BYTES = 0x0A, /*!< tmr dma transfer length 11 bytes */
+ TMR_DMA_TRANSFER_12BYTES = 0x0B, /*!< tmr dma transfer length 12 bytes */
+ TMR_DMA_TRANSFER_13BYTES = 0x0C, /*!< tmr dma transfer length 13 bytes */
+ TMR_DMA_TRANSFER_14BYTES = 0x0D, /*!< tmr dma transfer length 14 bytes */
+ TMR_DMA_TRANSFER_15BYTES = 0x0E, /*!< tmr dma transfer length 15 bytes */
+ TMR_DMA_TRANSFER_16BYTES = 0x0F, /*!< tmr dma transfer length 16 bytes */
+ TMR_DMA_TRANSFER_17BYTES = 0x10, /*!< tmr dma transfer length 17 bytes */
+ TMR_DMA_TRANSFER_18BYTES = 0x11 /*!< tmr dma transfer length 18 bytes */
+}tmr_dma_transfer_length_type;
+
+/**
+ * @brief tmr dma base address type
+ */
+typedef enum
+{
+ TMR_CTRL1_ADDRESS = 0x0000, /*!< tmr dma base address ctrl1 */
+ TMR_CTRL2_ADDRESS = 0x0001, /*!< tmr dma base address ctrl2 */
+ TMR_STCTRL_ADDRESS = 0x0002, /*!< tmr dma base address stctrl */
+ TMR_IDEN_ADDRESS = 0x0003, /*!< tmr dma base address iden */
+ TMR_ISTS_ADDRESS = 0x0004, /*!< tmr dma base address ists */
+ TMR_SWEVT_ADDRESS = 0x0005, /*!< tmr dma base address swevt */
+ TMR_CM1_ADDRESS = 0x0006, /*!< tmr dma base address cm1 */
+ TMR_CM2_ADDRESS = 0x0007, /*!< tmr dma base address cm2 */
+ TMR_CCTRL_ADDRESS = 0x0008, /*!< tmr dma base address cctrl */
+ TMR_CVAL_ADDRESS = 0x0009, /*!< tmr dma base address cval */
+ TMR_DIV_ADDRESS = 0x000A, /*!< tmr dma base address div */
+ TMR_PR_ADDRESS = 0x000B, /*!< tmr dma base address pr */
+ TMR_RPR_ADDRESS = 0x000C, /*!< tmr dma base address rpr */
+ TMR_C1DT_ADDRESS = 0x000D, /*!< tmr dma base address c1dt */
+ TMR_C2DT_ADDRESS = 0x000E, /*!< tmr dma base address c2dt */
+ TMR_C3DT_ADDRESS = 0x000F, /*!< tmr dma base address c3dt */
+ TMR_C4DT_ADDRESS = 0x0010, /*!< tmr dma base address c4dt */
+ TMR_BRK_ADDRESS = 0x0011, /*!< tmr dma base address brake */
+ TMR_DMACTRL_ADDRESS = 0x0012 /*!< tmr dma base address dmactrl */
+}tmr_dma_address_type;
+
+/**
+ * @brief tmr brk polarity type
+ */
+typedef enum
+{
+ TMR_BRK_INPUT_ACTIVE_LOW = 0x00, /*!< tmr brk input channel active low */
+ TMR_BRK_INPUT_ACTIVE_HIGH = 0x01 /*!< tmr brk input channel active high */
+}tmr_brk_polarity_type;
+
+/**
+ * @brief tmr write protect level type
+ */
+typedef enum
+{
+ TMR_WP_OFF = 0x00, /*!< tmr write protect off */
+ TMR_WP_LEVEL_3 = 0x01, /*!< tmr write protect level 3 */
+ TMR_WP_LEVEL_2 = 0x02, /*!< tmr write protect level 2 */
+ TMR_WP_LEVEL_1 = 0x03 /*!< tmr write protect level 1 */
+}tmr_wp_level_type;
+
+/**
+ * @brief tmr input remap type
+ */
+typedef enum
+{
+ TMR2_TMR8TRGOUT_TMR5_GPIO = 0x00, /*!< tmr2 input remap to tmr8_trgout or tmr5 remap to gpio */
+ TMR2_PTP_TMR5_LICK = 0x01, /*!< tmr2 input remap to ptp or tmr5 remap to lick */
+ TMR2_OTG1FS_TMR5_LEXT = 0x02, /*!< tmr2 input remap to otg1fs or tmr5 remap to lext */
+ TMR2_OTG2FS_TMR5_ERTC = 0x03 /*!< tmr2 input remap to otg2fs or tmr5 remap to ertc */
+}tmr_input_remap_type ;
+/**
+
+ * @brief tmr output config type
+ */
+typedef struct
+{
+ tmr_output_control_mode_type oc_mode; /*!< output channel mode */
+ confirm_state oc_idle_state; /*!< output channel idle state */
+ confirm_state occ_idle_state; /*!< output channel complementary idle state */
+ tmr_output_polarity_type oc_polarity; /*!< output channel polarity */
+ tmr_output_polarity_type occ_polarity; /*!< output channel complementary polarity */
+ confirm_state oc_output_state; /*!< output channel enable */
+ confirm_state occ_output_state; /*!< output channel complementary enable */
+} tmr_output_config_type;
+
+/**
+ * @brief tmr input capture config type
+ */
+typedef struct
+{
+ tmr_channel_select_type input_channel_select; /*!< tmr input channel select */
+ tmr_input_polarity_type input_polarity_select; /*!< tmr input polarity select */
+ tmr_input_direction_mapped_type input_mapped_select; /*!< tmr channel mapped direct or indirect */
+ uint8_t input_filter_value; /*!< tmr channel filter value */
+} tmr_input_config_type;
+
+/**
+ * @brief tmr brkdt config type
+ */
+typedef struct
+{
+ uint8_t deadtime; /*!< dead-time generator setup */
+ tmr_brk_polarity_type brk_polarity; /*!< tmr brake polarity */
+ tmr_wp_level_type wp_level; /*!< write protect configuration */
+ confirm_state auto_output_enable; /*!< automatic output enable */
+ confirm_state fcsoen_state; /*!< frozen channel status when output enable */
+ confirm_state fcsodis_state; /*!< frozen channel status when output disable */
+ confirm_state brk_enable; /*!< tmr brk enale */
+} tmr_brkdt_config_type;
+
+/**
+ * @brief type define tmr register all
+ */
+typedef struct
+{
+ /**
+ * @brief tmr ctrl1 register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t tmren : 1; /* [0] */
+ __IO uint32_t ovfen : 1; /* [1] */
+ __IO uint32_t ovfs : 1; /* [2] */
+ __IO uint32_t ocmen : 1; /* [3] */
+ __IO uint32_t cnt_dir : 3; /* [6:4] */
+ __IO uint32_t prben : 1; /* [7] */
+ __IO uint32_t clkdiv : 2; /* [9:8] */
+ __IO uint32_t pmen : 1; /* [10] */
+ __IO uint32_t reserved1 : 21;/* [31:11] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief tmr ctrl2 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t cbctrl : 1; /* [0] */
+ __IO uint32_t reserved1 : 1; /* [1] */
+ __IO uint32_t ccfs : 1; /* [2] */
+ __IO uint32_t drs : 1; /* [3] */
+ __IO uint32_t ptos : 3; /* [6:4] */
+ __IO uint32_t c1insel : 1; /* [7] */
+ __IO uint32_t c1ios : 1; /* [8] */
+ __IO uint32_t c1cios : 1; /* [9] */
+ __IO uint32_t c2ios : 1; /* [10] */
+ __IO uint32_t c2cios : 1; /* [11] */
+ __IO uint32_t c3ios : 1; /* [12] */
+ __IO uint32_t c3cios : 1; /* [13] */
+ __IO uint32_t c4ios : 1; /* [14] */
+ __IO uint32_t reserved2 : 16;/* [30:15] */
+ __IO uint32_t trgout2en : 1; /* [31] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief tmr smc register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t stctrl;
+ struct
+ {
+ __IO uint32_t smsel : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t stis : 3; /* [6:4] */
+ __IO uint32_t sts : 1; /* [7] */
+ __IO uint32_t esf : 4; /* [11:8] */
+ __IO uint32_t esdiv : 2; /* [13:12] */
+ __IO uint32_t ecmben : 1; /* [14] */
+ __IO uint32_t esp : 1; /* [15] */
+ __IO uint32_t reserved2 : 16;/* [31:16] */
+ } stctrl_bit;
+ };
+
+ /**
+ * @brief tmr die register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t iden;
+ struct
+ {
+ __IO uint32_t ovfien : 1; /* [0] */
+ __IO uint32_t c1ien : 1; /* [1] */
+ __IO uint32_t c2ien : 1; /* [2] */
+ __IO uint32_t c3ien : 1; /* [3] */
+ __IO uint32_t c4ien : 1; /* [4] */
+ __IO uint32_t hallien : 1; /* [5] */
+ __IO uint32_t tien : 1; /* [6] */
+ __IO uint32_t brkie : 1; /* [7] */
+ __IO uint32_t ovfden : 1; /* [8] */
+ __IO uint32_t c1den : 1; /* [9] */
+ __IO uint32_t c2den : 1; /* [10] */
+ __IO uint32_t c3den : 1; /* [11] */
+ __IO uint32_t c4den : 1; /* [12] */
+ __IO uint32_t hallde : 1; /* [13] */
+ __IO uint32_t tden : 1; /* [14] */
+ __IO uint32_t reserved1 : 17;/* [31:15] */
+ } iden_bit;
+ };
+
+ /**
+ * @brief tmr ists register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ists;
+ struct
+ {
+ __IO uint32_t ovfif : 1; /* [0] */
+ __IO uint32_t c1if : 1; /* [1] */
+ __IO uint32_t c2if : 1; /* [2] */
+ __IO uint32_t c3if : 1; /* [3] */
+ __IO uint32_t c4if : 1; /* [4] */
+ __IO uint32_t hallif : 1; /* [5] */
+ __IO uint32_t trgif : 1; /* [6] */
+ __IO uint32_t brkif : 1; /* [7] */
+ __IO uint32_t reserved1 : 1; /* [8] */
+ __IO uint32_t c1rf : 1; /* [9] */
+ __IO uint32_t c2rf : 1; /* [10] */
+ __IO uint32_t c3rf : 1; /* [11] */
+ __IO uint32_t c4rf : 1; /* [12] */
+ __IO uint32_t reserved2 : 19;/* [31:13] */
+ } ists_bit;
+ };
+
+ /**
+ * @brief tmr eveg register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t swevt;
+ struct
+ {
+ __IO uint32_t ovfswtr : 1; /* [0] */
+ __IO uint32_t c1swtr : 1; /* [1] */
+ __IO uint32_t c2swtr : 1; /* [2] */
+ __IO uint32_t c3swtr : 1; /* [3] */
+ __IO uint32_t c4swtr : 1; /* [4] */
+ __IO uint32_t hallswtr : 1; /* [5] */
+ __IO uint32_t trgswtr : 1; /* [6] */
+ __IO uint32_t brkswtr : 1; /* [7] */
+ __IO uint32_t reserved : 24;/* [31:8] */
+ } swevt_bit;
+ };
+
+ /**
+ * @brief tmr ccm1 register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t cm1;
+
+ /**
+ * @brief channel mode
+ */
+ struct
+ {
+ __IO uint32_t c1c : 2; /* [1:0] */
+ __IO uint32_t c1oien : 1; /* [2] */
+ __IO uint32_t c1oben : 1; /* [3] */
+ __IO uint32_t c1octrl : 3; /* [6:4] */
+ __IO uint32_t c1osen : 1; /* [7] */
+ __IO uint32_t c2c : 2; /* [9:8] */
+ __IO uint32_t c2oien : 1; /* [10] */
+ __IO uint32_t c2oben : 1; /* [11] */
+ __IO uint32_t c2octrl : 3; /* [14:12] */
+ __IO uint32_t c2osen : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cm1_output_bit;
+
+ /**
+ * @brief input capture mode
+ */
+ struct
+ {
+ __IO uint32_t c1c : 2; /* [1:0] */
+ __IO uint32_t c1idiv : 2; /* [3:2] */
+ __IO uint32_t c1df : 4; /* [7:4] */
+ __IO uint32_t c2c : 2; /* [9:8] */
+ __IO uint32_t c2idiv : 2; /* [11:10] */
+ __IO uint32_t c2df : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cm1_input_bit;
+ };
+
+ /**
+ * @brief tmr ccm2 register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t cm2;
+
+ /**
+ * @brief channel mode
+ */
+ struct
+ {
+ __IO uint32_t c3c : 2; /* [1:0] */
+ __IO uint32_t c3oien : 1; /* [2] */
+ __IO uint32_t c3oben : 1; /* [3] */
+ __IO uint32_t c3octrl : 3; /* [6:4] */
+ __IO uint32_t c3osen : 1; /* [7] */
+ __IO uint32_t c4c : 2; /* [9:8] */
+ __IO uint32_t c4oien : 1; /* [10] */
+ __IO uint32_t c4oben : 1; /* [11] */
+ __IO uint32_t c4octrl : 3; /* [14:12] */
+ __IO uint32_t c4osen : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cm2_output_bit;
+
+ /**
+ * @brief input capture mode
+ */
+ struct
+ {
+ __IO uint32_t c3c : 2; /* [1:0] */
+ __IO uint32_t c3idiv : 2; /* [3:2] */
+ __IO uint32_t c3df : 4; /* [7:4] */
+ __IO uint32_t c4c : 2; /* [9:8] */
+ __IO uint32_t c4idiv : 2; /* [11:10] */
+ __IO uint32_t c4df : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cm2_input_bit;
+ };
+
+ /**
+ * @brief tmr cce register, offset:0x20
+ */
+ union
+ {
+ uint32_t cctrl;
+ struct
+ {
+ __IO uint32_t c1en : 1; /* [0] */
+ __IO uint32_t c1p : 1; /* [1] */
+ __IO uint32_t c1cen : 1; /* [2] */
+ __IO uint32_t c1cp : 1; /* [3] */
+ __IO uint32_t c2en : 1; /* [4] */
+ __IO uint32_t c2p : 1; /* [5] */
+ __IO uint32_t c2cen : 1; /* [6] */
+ __IO uint32_t c2cp : 1; /* [7] */
+ __IO uint32_t c3en : 1; /* [8] */
+ __IO uint32_t c3p : 1; /* [9] */
+ __IO uint32_t c3cen : 1; /* [10] */
+ __IO uint32_t c3cp : 1; /* [11] */
+ __IO uint32_t c4en : 1; /* [12] */
+ __IO uint32_t c4p : 1; /* [13] */
+ __IO uint32_t reserved1 : 18;/* [31:14] */
+ } cctrl_bit;
+ };
+
+ /**
+ * @brief tmr cnt register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t cval;
+ struct
+ {
+ __IO uint32_t cval : 32;/* [31:0] */
+ } cval_bit;
+ };
+
+ /**
+ * @brief tmr div, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t div;
+ struct
+ {
+ __IO uint32_t div : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } div_bit;
+ };
+
+ /**
+ * @brief tmr pr register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t pr;
+ struct
+ {
+ __IO uint32_t pr : 32;/* [31:0] */
+ } pr_bit;
+ };
+
+ /**
+ * @brief tmr rpr register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t rpr;
+ struct
+ {
+ __IO uint32_t rpr : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } rpr_bit;
+ };
+
+ /**
+ * @brief tmr c1dt register, offset:0x34
+ */
+ union
+ {
+ uint32_t c1dt;
+ struct
+ {
+ __IO uint32_t c1dt : 32;/* [31:0] */
+ } c1dt_bit;
+ };
+
+ /**
+ * @brief tmr c2dt register, offset:0x38
+ */
+ union
+ {
+ uint32_t c2dt;
+ struct
+ {
+ __IO uint32_t c2dt : 32;/* [31:0] */
+ } c2dt_bit;
+ };
+
+ /**
+ * @brief tmr c3dt register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t c3dt;
+ struct
+ {
+ __IO uint32_t c3dt : 32;/* [31:0] */
+ } c3dt_bit;
+ };
+
+ /**
+ * @brief tmr c4dt register, offset:0x40
+ */
+ union
+ {
+ __IO uint32_t c4dt;
+ struct
+ {
+ __IO uint32_t c4dt : 32;/* [31:0] */
+ } c4dt_bit;
+ };
+
+ /**
+ * @brief tmr brk register, offset:0x44
+ */
+ union
+ {
+ __IO uint32_t brk;
+ struct
+ {
+ __IO uint32_t dtc : 8; /* [7:0] */
+ __IO uint32_t wpc : 2; /* [9:8] */
+ __IO uint32_t fcsodis : 1; /* [10] */
+ __IO uint32_t fcsoen : 1; /* [11] */
+ __IO uint32_t brken : 1; /* [12] */
+ __IO uint32_t brkv : 1; /* [13] */
+ __IO uint32_t aoen : 1; /* [14] */
+ __IO uint32_t oen : 1; /* [15] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } brk_bit;
+ };
+ /**
+ * @brief tmr dmactrl register, offset:0x48
+ */
+ union
+ {
+ __IO uint32_t dmactrl;
+ struct
+ {
+ __IO uint32_t addr : 5; /* [4:0] */
+ __IO uint32_t reserved1 : 3; /* [7:5] */
+ __IO uint32_t dtb : 5; /* [12:8] */
+ __IO uint32_t reserved2 : 19;/* [31:13] */
+ } dmactrl_bit;
+ };
+
+ /**
+ * @brief tmr dmadt register, offset:0x4C
+ */
+ union
+ {
+ __IO uint32_t dmadt;
+ struct
+ {
+ __IO uint32_t dmadt : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } dmadt_bit;
+ };
+
+ /**
+ * @brief tmr rmp register, offset:0x50
+ */
+ union
+ {
+ __IO uint32_t rmp;
+ struct
+ {
+ __IO uint32_t reserved1 : 6; /* [5:0] */
+ __IO uint32_t tmr5_ch4_irmp : 2; /* [7:6] */
+ __IO uint32_t reserved2 : 2; /* [9:8] */
+ __IO uint32_t tmr2_ch1_irmp : 2; /* [11:10] */
+ __IO uint32_t reserved3 : 20;/* [31:16] */
+ } rmp_bit;
+ };
+
+ /**
+ * @brief tmr reserved0 register, offset:0x54-0x6C
+ */
+ __IO uint32_t reserved1[7];
+
+ /**
+ * @brief tmr cm3 register, offset:0x70
+ */
+ union
+ {
+ __IO uint32_t cm3;
+ struct
+ {
+ __IO uint32_t reserved1 : 2; /* [1:0] */
+ __IO uint32_t c5oien : 1; /* [2] */
+ __IO uint32_t c5oben : 1; /* [3] */
+ __IO uint32_t c5octrl : 3; /* [6:4] */
+ __IO uint32_t c5osen : 1; /* [7] */
+ __IO uint32_t reserved2 : 24;/* [31:8] */
+ } cm3_output_bit;
+ };
+
+ /**
+ * @brief tmr c5dt register, offset:0x74
+ */
+ union
+ {
+ __IO uint32_t c5dt;
+ struct
+ {
+ __IO uint32_t c5dt : 32;/* [31:0] */
+ } c5dt_bit;
+ };
+} tmr_type;
+
+/**
+ * @}
+ */
+
+#define TMR1 ((tmr_type *) TMR1_BASE)
+#define TMR2 ((tmr_type *) TMR2_BASE)
+#define TMR3 ((tmr_type *) TMR3_BASE)
+#define TMR4 ((tmr_type *) TMR4_BASE)
+#define TMR5 ((tmr_type *) TMR5_BASE)
+#define TMR6 ((tmr_type *) TMR6_BASE)
+#define TMR7 ((tmr_type *) TMR7_BASE)
+#define TMR8 ((tmr_type *) TMR8_BASE)
+#define TMR9 ((tmr_type *) TMR9_BASE)
+#define TMR10 ((tmr_type *) TMR10_BASE)
+#define TMR11 ((tmr_type *) TMR11_BASE)
+#define TMR12 ((tmr_type *) TMR12_BASE)
+#define TMR13 ((tmr_type *) TMR13_BASE)
+#define TMR14 ((tmr_type *) TMR14_BASE)
+#define TMR20 ((tmr_type *) TMR20_BASE)
+
+/** @defgroup TMR_exported_functions
+ * @{
+ */
+
+void tmr_reset(tmr_type *tmr_x);
+void tmr_counter_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_output_default_para_init(tmr_output_config_type *tmr_output_struct);
+void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct);
+void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct);
+void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div);
+void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div);
+void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir);
+void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value);
+void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value);
+uint32_t tmr_counter_value_get(tmr_type *tmr_x);
+void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value);
+uint32_t tmr_div_value_get(tmr_type *tmr_x);
+void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_output_config_type *tmr_output_struct);
+void tmr_output_channel_mode_select(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_output_control_mode_type oc_mode);
+void tmr_period_value_set(tmr_type *tmr_x, uint32_t tmr_pr_value);
+uint32_t tmr_period_value_get(tmr_type *tmr_x);
+void tmr_channel_value_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ uint32_t tmr_channel_value);
+uint32_t tmr_channel_value_get(tmr_type *tmr_x, tmr_channel_select_type tmr_channel);
+void tmr_period_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ confirm_state new_state);
+void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ confirm_state new_state);
+void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ confirm_state new_state);
+void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_32_bit_function_enable (tmr_type *tmr_x, confirm_state new_state);
+void tmr_overflow_request_source_set(tmr_type *tmr_x, confirm_state new_state);
+void tmr_overflow_event_disable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
+ tmr_channel_input_divider_type divider_factor);
+void tmr_channel_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state);
+void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ uint16_t filter_value);
+void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
+ tmr_channel_input_divider_type divider_factor);
+void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect);
+void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_channel_input_divider_type divider_factor);
+void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode);
+void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode);
+void tmr_channel_dma_select(tmr_type *tmr_x, tmr_dma_request_source_type cc_dma_select);
+void tmr_hall_select(tmr_type *tmr_x, confirm_state new_state);
+void tmr_channel_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_trgout2_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_select);
+void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state);
+void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state);
+void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state);
+flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
+void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag);
+void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event);
+void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_internal_clock_set(tmr_type *tmr_x);
+void tmr_output_channel_fast_set(tmr_type *tmr_x, tmr_channel_output_fast_type oc_fast);
+void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_polarity_active_type oc_polarity);
+void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+ tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
+void tmr_external_clock_mode1_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+ tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
+void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+ tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
+void tmr_encoder_mode_config(tmr_type *tmr_x, tmr_encoder_mode_type encoder_mode, tmr_input_polarity_type \
+ ic1_polarity, tmr_input_polarity_type ic2_polarity);
+void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_force_output_type force_output);
+void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \
+ tmr_dma_address_type dma_base_address);
+void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct);
+void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_usart.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_usart.h
new file mode 100644
index 0000000..d7c6176
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_usart.h
@@ -0,0 +1,412 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_usart.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 usart header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_USART_H
+#define __AT32F435_437_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/** @defgroup USART_flags_definition
+ * @brief usart flag
+ * @{
+ */
+
+#define USART_PERR_FLAG ((uint32_t)0x00000001) /*!< usart parity error flag */
+#define USART_FERR_FLAG ((uint32_t)0x00000002) /*!< usart framing error flag */
+#define USART_NERR_FLAG ((uint32_t)0x00000004) /*!< usart noise error flag */
+#define USART_ROERR_FLAG ((uint32_t)0x00000008) /*!< usart receiver overflow error flag */
+#define USART_IDLEF_FLAG ((uint32_t)0x00000010) /*!< usart idle flag */
+#define USART_RDBF_FLAG ((uint32_t)0x00000020) /*!< usart receive data buffer full flag */
+#define USART_TDC_FLAG ((uint32_t)0x00000040) /*!< usart transmit data complete flag */
+#define USART_TDBE_FLAG ((uint32_t)0x00000080) /*!< usart transmit data buffer empty flag */
+#define USART_BFF_FLAG ((uint32_t)0x00000100) /*!< usart break frame flag */
+#define USART_CTSCF_FLAG ((uint32_t)0x00000200) /*!< usart cts change flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_interrupts_definition
+ * @brief usart interrupt
+ * @{
+ */
+
+#define USART_IDLE_INT MAKE_VALUE(0x0C,0x04) /*!< usart idle interrupt */
+#define USART_RDBF_INT MAKE_VALUE(0x0C,0x05) /*!< usart receive data buffer full interrupt */
+#define USART_TDC_INT MAKE_VALUE(0x0C,0x06) /*!< usart transmit data complete interrupt */
+#define USART_TDBE_INT MAKE_VALUE(0x0C,0x07) /*!< usart transmit data buffer empty interrupt */
+#define USART_PERR_INT MAKE_VALUE(0x0C,0x08) /*!< usart parity error interrupt */
+#define USART_BF_INT MAKE_VALUE(0x10,0x06) /*!< usart break frame interrupt */
+#define USART_ERR_INT MAKE_VALUE(0x14,0x00) /*!< usart error interrupt */
+#define USART_CTSCF_INT MAKE_VALUE(0x14,0x0A) /*!< usart cts change interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_exported_types
+ * @{
+ */
+
+/**
+ * @brief usart parity selection type
+ */
+typedef enum
+{
+ USART_PARITY_NONE = 0x00, /*!< usart no parity */
+ USART_PARITY_EVEN = 0x01, /*!< usart even parity */
+ USART_PARITY_ODD = 0x02 /*!< usart odd parity */
+} usart_parity_selection_type;
+
+/**
+ * @brief usart wakeup mode type
+ */
+typedef enum
+{
+ USART_WAKEUP_BY_IDLE_FRAME = 0x00, /*!< usart wakeup by idle frame */
+ USART_WAKEUP_BY_MATCHING_ID = 0x01 /*!< usart wakeup by matching id */
+} usart_wakeup_mode_type;
+
+/**
+ * @brief usart data bit num type
+ */
+typedef enum
+{
+ USART_DATA_7BITS = 0x00, /*!< usart data size is 7 bits */
+ USART_DATA_8BITS = 0x01, /*!< usart data size is 8 bits */
+ USART_DATA_9BITS = 0x02 /*!< usart data size is 9 bits */
+} usart_data_bit_num_type;
+
+/**
+ * @brief usart break frame bit num type
+ */
+typedef enum
+{
+ USART_BREAK_10BITS = 0x00, /*!< usart lin mode berak frame detection 10 bits */
+ USART_BREAK_11BITS = 0x01 /*!< usart lin mode berak frame detection 11 bits */
+} usart_break_bit_num_type;
+
+/**
+ * @brief usart phase of the clock type
+ */
+typedef enum
+{
+ USART_CLOCK_PHASE_1EDGE = 0x00, /*!< usart data capture is done on the clock leading edge */
+ USART_CLOCK_PHASE_2EDGE = 0x01 /*!< usart data capture is done on the clock trailing edge */
+} usart_clock_phase_type;
+
+/**
+ * @brief usart polarity of the clock type
+ */
+typedef enum
+{
+ USART_CLOCK_POLARITY_LOW = 0x00, /*!< usart clock stay low level outside transmission window */
+ USART_CLOCK_POLARITY_HIGH = 0x01 /*!< usart clock stay high level outside transmission window */
+} usart_clock_polarity_type;
+
+/**
+ * @brief usart last bit clock pulse type
+ */
+typedef enum
+{
+ USART_CLOCK_LAST_BIT_NONE = 0x00, /*!< usart clock pulse of the last data bit is not outputted */
+ USART_CLOCK_LAST_BIT_OUTPUT = 0x01 /*!< usart clock pulse of the last data bit is outputted */
+} usart_lbcp_type;
+
+/**
+ * @brief usart stop bit num type
+ */
+typedef enum
+{
+ USART_STOP_1_BIT = 0x00, /*!< usart stop bits num is 1 */
+ USART_STOP_0_5_BIT = 0x01, /*!< usart stop bits num is 0.5 */
+ USART_STOP_2_BIT = 0x02, /*!< usart stop bits num is 2 */
+ USART_STOP_1_5_BIT = 0x03 /*!< usart stop bits num is 1.5 */
+} usart_stop_bit_num_type;
+
+/**
+ * @brief usart hardware flow control type
+ */
+typedef enum
+{
+ USART_HARDWARE_FLOW_NONE = 0x00, /*!< usart without hardware flow */
+ USART_HARDWARE_FLOW_RTS = 0x01, /*!< usart hardware flow only rts */
+ USART_HARDWARE_FLOW_CTS = 0x02, /*!< usart hardware flow only cts */
+ USART_HARDWARE_FLOW_RTS_CTS = 0x03 /*!< usart hardware flow both rts and cts */
+} usart_hardware_flow_control_type;
+
+/**
+ * @brief usart identification bit num type
+ */
+typedef enum
+{
+ USART_ID_FIXED_4_BIT = 0x00, /*!< usart id bit num fixed 4 bits */
+ USART_ID_RELATED_DATA_BIT = 0x01 /*!< usart id bit num related data bits */
+} usart_identification_bit_num_type;
+
+/**
+ * @brief usart de polarity type
+ */
+typedef enum
+{
+ USART_DE_POLARITY_HIGH = 0x00, /*!< usart de polarity high */
+ USART_DE_POLARITY_LOW = 0x01 /*!< usart de polarity low */
+} usart_de_polarity_type;
+
+/**
+ * @brief type define usart register all
+ */
+typedef struct
+{
+ /**
+ * @brief usart sts register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t perr : 1; /* [0] */
+ __IO uint32_t ferr : 1; /* [1] */
+ __IO uint32_t nerr : 1; /* [2] */
+ __IO uint32_t roerr : 1; /* [3] */
+ __IO uint32_t idlef : 1; /* [4] */
+ __IO uint32_t rdbf : 1; /* [5] */
+ __IO uint32_t tdc : 1; /* [6] */
+ __IO uint32_t tdbe : 1; /* [7] */
+ __IO uint32_t bff : 1; /* [8] */
+ __IO uint32_t ctscf : 1; /* [9] */
+ __IO uint32_t reserved1 : 22;/* [31:10] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief usart dt register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t dt;
+ struct
+ {
+ __IO uint32_t dt : 9; /* [8:0] */
+ __IO uint32_t reserved1 : 23;/* [31:9] */
+ } dt_bit;
+ };
+
+ /**
+ * @brief usart baudr register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t baudr;
+ struct
+ {
+ __IO uint32_t div : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } baudr_bit;
+ };
+
+ /**
+ * @brief usart ctrl1 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t sbf : 1; /* [0] */
+ __IO uint32_t rm : 1; /* [1] */
+ __IO uint32_t ren : 1; /* [2] */
+ __IO uint32_t ten : 1; /* [3] */
+ __IO uint32_t idleien : 1; /* [4] */
+ __IO uint32_t rdbfien : 1; /* [5] */
+ __IO uint32_t tdcien : 1; /* [6] */
+ __IO uint32_t tdbeien : 1; /* [7] */
+ __IO uint32_t perrien : 1; /* [8] */
+ __IO uint32_t psel : 1; /* [9] */
+ __IO uint32_t pen : 1; /* [10] */
+ __IO uint32_t wum : 1; /* [11] */
+ __IO uint32_t dbn_l : 1; /* [12] */
+ __IO uint32_t uen : 1; /* [13] */
+ __IO uint32_t reserved1 : 2; /* [15:14] */
+ __IO uint32_t tcdt : 5; /* [20:16] */
+ __IO uint32_t tsdt : 5; /* [25:21] */
+ __IO uint32_t reserved2 : 2; /* [27:26] */
+ __IO uint32_t dbn_h : 1; /* [28] */
+ __IO uint32_t reserved3 : 3; /* [31:29] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief usart ctrl2 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t id_l : 4; /* [3:0] */
+ __IO uint32_t idbn : 1; /* [4] */
+ __IO uint32_t bfbn : 1; /* [5] */
+ __IO uint32_t bfien : 1; /* [6] */
+ __IO uint32_t reserved1 : 1; /* [7] */
+ __IO uint32_t lbcp : 1; /* [8] */
+ __IO uint32_t clkpha : 1; /* [9] */
+ __IO uint32_t clkpol : 1; /* [10] */
+ __IO uint32_t clken : 1; /* [11] */
+ __IO uint32_t stopbn : 2; /* [13:12] */
+ __IO uint32_t linen : 1; /* [14] */
+ __IO uint32_t trpswap : 1; /* [15] */
+ __IO uint32_t reserved2 : 12;/* [27:16] */
+ __IO uint32_t id_h : 4; /* [31:28] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief usart ctrl3 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t ctrl3;
+ struct
+ {
+ __IO uint32_t errien : 1; /* [0] */
+ __IO uint32_t irdaen : 1; /* [1] */
+ __IO uint32_t irdalp : 1; /* [2] */
+ __IO uint32_t slben : 1; /* [3] */
+ __IO uint32_t scnacken : 1; /* [4] */
+ __IO uint32_t scmen : 1; /* [5] */
+ __IO uint32_t dmaren : 1; /* [6] */
+ __IO uint32_t dmaten : 1; /* [7] */
+ __IO uint32_t rtsen : 1; /* [8] */
+ __IO uint32_t ctsen : 1; /* [9] */
+ __IO uint32_t ctscfien : 1; /* [10] */
+ __IO uint32_t reserved1 : 3; /* [13:11] */
+ __IO uint32_t rs485en : 1; /* [14] */
+ __IO uint32_t dep : 1; /* [15] */
+ __IO uint32_t reserved2 : 16;/* [31:16] */
+ } ctrl3_bit;
+ };
+
+ /**
+ * @brief usart gdiv register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t gdiv;
+ struct
+ {
+ __IO uint32_t isdiv : 8; /* [7:0] */
+ __IO uint32_t scgt : 8; /* [15:8] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } gdiv_bit;
+ };
+} usart_type;
+
+/**
+ * @}
+ */
+
+#define USART1 ((usart_type *) USART1_BASE)
+#define USART2 ((usart_type *) USART2_BASE)
+#define USART3 ((usart_type *) USART3_BASE)
+#define UART4 ((usart_type *) UART4_BASE)
+#define UART5 ((usart_type *) UART5_BASE)
+#define USART6 ((usart_type *) USART6_BASE)
+#define UART7 ((usart_type *) UART7_BASE)
+#define UART8 ((usart_type *) UART8_BASE)
+
+/** @defgroup USART_exported_functions
+ * @{
+ */
+
+void usart_reset(usart_type* usart_x);
+void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit);
+void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity);
+void usart_enable(usart_type* usart_x, confirm_state new_state);
+void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state);
+void usart_receiver_enable(usart_type* usart_x, confirm_state new_state);
+void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb);
+void usart_clock_enable(usart_type* usart_x, confirm_state new_state);
+void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state);
+void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state);
+void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state);
+void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id);
+void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode);
+void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state);
+void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit);
+void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state);
+void usart_data_transmit(usart_type* usart_x, uint16_t data);
+uint16_t usart_data_receive(usart_type* usart_x);
+void usart_break_send(usart_type* usart_x);
+void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val);
+void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val);
+void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state);
+void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state);
+void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state);
+void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state);
+void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state);
+void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state);
+flag_status usart_flag_get(usart_type* usart_x, uint32_t flag);
+void usart_flag_clear(usart_type* usart_x, uint32_t flag);
+void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time);
+void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state);
+void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type id_bit_num);
+void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity);
+void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_usb.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_usb.h
new file mode 100644
index 0000000..c5fb3fc
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_usb.h
@@ -0,0 +1,1422 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_usb.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 usb header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_USB_H
+#define __AT32F435_437_USB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup USB
+ * @{
+ */
+
+/** @defgroup USB_global_interrupts_definition
+ * @brief usb global interrupt mask
+ * @{
+ */
+
+#define USB_OTG_MODEMIS_INT ((uint32_t)0x00000002) /*!< usb otg mode mismatch interrupt */
+#define USB_OTG_OTGINT_INT ((uint32_t)0x00000004) /*!< usb otg interrupt */
+#define USB_OTG_SOF_INT ((uint32_t)0x00000008) /*!< usb otg sof interrupt */
+#define USB_OTG_RXFLVL_INT ((uint32_t)0x00000010) /*!< usb otg receive fifo non-empty interrupt */
+#define USB_OTG_NPTXFEMP_INT ((uint32_t)0x00000020) /*!< usb otg non-periodic tx fifo empty interrupt */
+#define USB_OTG_GINNAKEFF_INT ((uint32_t)0x00000040) /*!< usb otg global non-periodic in nak effective interrupt */
+#define USB_OTG_GOUTNAKEFF_INT ((uint32_t)0x00000080) /*!< usb otg global out nak effective interrupt */
+#define USB_OTG_ERLYSUSP_INT ((uint32_t)0x00000400) /*!< usb otg early suspend interrupt */
+#define USB_OTG_USBSUSP_INT ((uint32_t)0x00000800) /*!< usb otg suspend interrupt */
+#define USB_OTG_USBRST_INT ((uint32_t)0x00001000) /*!< usb otg reset interrupt */
+#define USB_OTG_ENUMDONE_INT ((uint32_t)0x00002000) /*!< usb otg enumeration done interrupt */
+#define USB_OTG_ISOOUTDROP_INT ((uint32_t)0x00004000) /*!< usb otg isochronous out packet dropped interrut */
+#define USB_OTG_EOPF_INT ((uint32_t)0x00008000) /*!< usb otg eop interrupt */
+#define USB_OTG_IEPT_INT ((uint32_t)0x00040000) /*!< usb otg in endpoint interrupt */
+#define USB_OTG_OEPT_INT ((uint32_t)0x00080000) /*!< usb otg out endpoint interrupt */
+#define USB_OTG_INCOMISOIN_INT ((uint32_t)0x00100000) /*!< usb otg incomplete isochronous in transfer interrupt */
+#define USB_OTG_INCOMPIP_INCOMPISOOUT_INT ((uint32_t)0x00200000) /*!< usb otg incomplete periodic transfer/isochronous out interrupt */
+#define USB_OTG_PRT_INT ((uint32_t)0x01000000) /*!< usb otg host port interrupt */
+#define USB_OTG_HCH_INT ((uint32_t)0x02000000) /*!< usb otg host channel interrupt */
+#define USB_OTG_PTXFEMP_INT ((uint32_t)0x04000000) /*!< usb otg periodic txfifo empty interrupt */
+#define USB_OTG_CONIDSCHG_INT ((uint32_t)0x10000000) /*!< usb otg connector id status change interrupt */
+#define USB_OTG_DISCON_INT ((uint32_t)0x20000000) /*!< usb otg disconnect detected interrupt */
+#define USB_OTG_WKUP_INT ((uint32_t)0x80000000) /*!< usb otg wakeup interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup USB_global_interrupt_flags_definition
+ * @brief usb global interrupt flag
+ * @{
+ */
+
+#define USB_OTG_CURMODE ((uint32_t)0x00000001) /*!< usb otg current mode */
+#define USB_OTG_MODEMIS_FLAG ((uint32_t)0x00000002) /*!< usb otg mode mismatch flag */
+#define USB_OTG_OTGINT_FLAG ((uint32_t)0x00000004) /*!< usb otg flag */
+#define USB_OTG_SOF_FLAG ((uint32_t)0x00000008) /*!< usb otg sof flag */
+#define USB_OTG_RXFLVL_FLAG ((uint32_t)0x00000010) /*!< usb otg receive fifo non-empty flag */
+#define USB_OTG_NPTXFEMP_FLAG ((uint32_t)0x00000020) /*!< usb otg non-periodic tx fifo empty flag */
+#define USB_OTG_GINNAKEFF_FLAG ((uint32_t)0x00000040) /*!< usb otg global non-periodic in nak effective flag */
+#define USB_OTG_GOUTNAKEFF_FLAG ((uint32_t)0x00000080) /*!< usb otg global out nak effective flag */
+#define USB_OTG_ERLYSUSP_FLAG ((uint32_t)0x00000400) /*!< usb otg early suspend flag */
+#define USB_OTG_USBSUSP_FLAG ((uint32_t)0x00000800) /*!< usb otg suspend flag */
+#define USB_OTG_USBRST_FLAG ((uint32_t)0x00001000) /*!< usb otg reset flag */
+#define USB_OTG_ENUMDONE_FLAG ((uint32_t)0x00002000) /*!< usb otg enumeration done flag */
+#define USB_OTG_ISOOUTDROP_FLAG ((uint32_t)0x00004000) /*!< usb otg isochronous out packet dropped flag */
+#define USB_OTG_EOPF_FLAG ((uint32_t)0x00008000) /*!< usb otg eop flag */
+#define USB_OTG_IEPT_FLAG ((uint32_t)0x00040000) /*!< usb otg in endpoint flag */
+#define USB_OTG_OEPT_FLAG ((uint32_t)0x00080000) /*!< usb otg out endpoint flag */
+#define USB_OTG_INCOMISOIN_FLAG ((uint32_t)0x00100000) /*!< usb otg incomplete isochronous in transfer flag */
+#define USB_OTG_INCOMPIP_INCOMPISOOUT_FLAG ((uint32_t)0x00200000) /*!< usb otg incomplete periodic transfer/isochronous out flag */
+#define USB_OTG_PRT_FLAG ((uint32_t)0x01000000) /*!< usb otg host port flag */
+#define USB_OTG_HCH_FLAG ((uint32_t)0x02000000) /*!< usb otg host channel flag */
+#define USB_OTG_PTXFEMP_FLAG ((uint32_t)0x04000000) /*!< usb otg periodic txfifo empty flag */
+#define USB_OTG_CONIDSCHG_FLAG ((uint32_t)0x10000000) /*!< usb otg connector id status change flag */
+#define USB_OTG_DISCON_FLAG ((uint32_t)0x20000000) /*!< usb otg disconnect detected flag */
+#define USB_OTG_WKUP_FLAG ((uint32_t)0x80000000) /*!< usb otg wakeup flag */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup USB_global_setting_definition
+ * @brief usb global setting
+ * @{
+ */
+
+/**
+ * @brief usb turnaround time
+ */
+#define USB_TRDTIM_8 0x9 /*!< usb turn around time 8 */
+#define USB_TRDTIM_16 0x5 /*!< usb turn around time 16 */
+
+/**
+ * @brief usb receive status
+ */
+#define USB_OTG_GRXSTSP_EPTNUM ((uint32_t)0x0000000F) /*!< usb device receive packet endpoint number*/
+#define USB_OTG_GRXSTSP_CHNUM ((uint32_t)0x0000000F) /*!< usb host receive packet channel number*/
+#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< usb receive packet byte count */
+#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< usb receive packet pid */
+#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< usb receive packet status */
+
+/**
+ * @brief usb host packet status
+ */
+#define PKTSTS_IN_DATA_PACKET_RECV 0x2 /*!< usb host in data packet received */
+#define PKTSTS_IN_TRANSFER_COMPLETE 0x3 /*!< usb host in transfer completed */
+#define PKTSTS_DATA_BIT_ERROR 0x5 /*!< usb host data toggle error */
+#define PKTSTS_CHANNEL_STOP 0x7 /*!< usb host channel halted */
+
+/**
+ * @brief usb device packet status
+ */
+#define USB_OUT_STS_NAK 0x1 /*!< usb device global out nak */
+#define USB_OUT_STS_DATA 0x2 /*!< usb device out data packet received */
+#define USB_OUT_STS_COMP 0x3 /*!< usb device out transfer completed */
+#define USB_SETUP_STS_COMP 0x4 /*!< usb device setup transcation completed */
+#define USB_SETUP_STS_DATA 0x6 /*!< usb device setup data packet received */
+
+/**
+ * @}
+ */
+
+/** @defgroup USB_host_config_definition
+ * @{
+ */
+
+/**
+ * @brief usb host phy clock
+ */
+#define USB_HCFG_CLK_60M 0 /*!< usb host phy clock 60mhz */
+#define USB_HCFG_CLK_48M 1 /*!< usb host phy clock 48mhz */
+#define USB_HCFG_CLK_6M 2 /*!< usb host phy clock 6mhz */
+
+/**
+ * @brief usb host port status
+ */
+#define USB_OTG_HPRT_PRTCONSTS ((uint32_t)0x00000001) /*!< usb host port connect status */
+#define USB_OTG_HPRT_PRTCONDET ((uint32_t)0x00000002) /*!< usb host port connect detected */
+#define USB_OTG_HPRT_PRTENA ((uint32_t)0x00000004) /*!< usb host port enable */
+#define USB_OTG_HPRT_PRTENCHNG ((uint32_t)0x00000008) /*!< usb host port enable/disable change */
+#define USB_OTG_HPRT_PRTOVRCACT ((uint32_t)0x00000010) /*!< usb host port overcurrent active */
+#define USB_OTG_HPRT_PRTOVRCCHNG ((uint32_t)0x00000020) /*!< usb host port overcurrent change */
+#define USB_OTG_HPRT_PRTRES ((uint32_t)0x00000040) /*!< usb host port resume */
+#define USB_OTG_HPRT_PRTSUSP ((uint32_t)0x00000080) /*!< usb host port suspend */
+#define USB_OTG_HPRT_PRTRST ((uint32_t)0x00000100) /*!< usb host port reset */
+#define USB_OTG_HPRT_PRTLNSTS ((uint32_t)0x00000C00) /*!< usb host port line status */
+#define USB_OTG_HPRT_PRTPWR ((uint32_t)0x00001000) /*!< usb host port power */
+#define USB_OTG_HPRT_PRTSPD ((uint32_t)0x00060000) /*!< usb host port speed */
+
+/**
+ * @brief usb port speed
+ */
+#define USB_PRTSPD_HIGH_SPEED 0 /*!< usb host port high speed */
+#define USB_PRTSPD_FULL_SPEED 1 /*!< usb host port full speed */
+#define USB_PRTSPD_LOW_SPEED 2 /*!< usb host port low speed */
+
+/**
+ * @brief usb host register hcchar bit define
+ */
+#define USB_OTG_HCCHAR_MPS ((uint32_t)0x000007FF) /*!< channel maximum packet size */
+#define USB_OTG_HCCHAR_EPTNUM ((uint32_t)0x00007800) /*!< endpoint number */
+#define USB_OTG_HCCHAR_EPTDIR ((uint32_t)0x00008000) /*!< endpoint direction */
+#define USB_OTG_HCCHAR_LSPDDEV ((uint32_t)0x00020000) /*!< low speed device */
+#define USB_OTG_HCCHAR_EPTYPE ((uint32_t)0x000C0000) /*!< endpoint type */
+#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< multi count */
+#define USB_OTG_HCCHAR_DEVADDR ((uint32_t)0x1FC00000) /*!< device address */
+#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< odd frame */
+#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< channel disable */
+#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< channel enable */
+
+/**
+ * @brief usb host register hctsiz bit define
+ */
+#define USB_OTG_HCTSIZ_XFERSIZE ((uint32_t)0x0007FFFF) /*!< channel transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< channel packet count */
+#define USB_OTG_HCTSIZ_PID ((uint32_t)0x60000000) /*!< channel pid */
+
+/**
+ * @brief usb host channel interrupt mask
+ */
+#define USB_OTG_HC_XFERCM_INT ((uint32_t)0x00000001) /*!< channel transfer complete interrupt */
+#define USB_OTG_HC_CHHLTDM_INT ((uint32_t)0x00000002) /*!< channel halted interrupt */
+#define USB_OTG_HC_STALLM_INT ((uint32_t)0x00000008) /*!< channel stall interrupt */
+#define USB_OTG_HC_NAKM_INT ((uint32_t)0x00000010) /*!< channel nak interrupt */
+#define USB_OTG_HC_ACKM_INT ((uint32_t)0x00000020) /*!< channel ack interrupt */
+#define USB_OTG_HC_NYETM_INT ((uint32_t)0x00000040) /*!< channel nyet interrupt */
+#define USB_OTG_HC_XACTERRM_INT ((uint32_t)0x00000080) /*!< channel transaction error interrupt */
+#define USB_OTG_HC_BBLERRM_INT ((uint32_t)0x00000100) /*!< channel babble error interrupt */
+#define USB_OTG_HC_FRMOVRRUN_INT ((uint32_t)0x00000200) /*!< channel frame overrun interrupt */
+#define USB_OTG_HC_DTGLERRM_INT ((uint32_t)0x00000400) /*!< channel data toggle interrupt */
+
+/**
+ * @brief usb host channel interrupt flag
+ */
+#define USB_OTG_HC_XFERC_FLAG ((uint32_t)0x00000001) /*!< channel transfer complete flag */
+#define USB_OTG_HC_CHHLTD_FLAG ((uint32_t)0x00000002) /*!< channel halted flag */
+#define USB_OTG_HC_STALL_FLAG ((uint32_t)0x00000008) /*!< channel stall flag */
+#define USB_OTG_HC_NAK_FLAG ((uint32_t)0x00000010) /*!< channel nak flag */
+#define USB_OTG_HC_ACK_FLAG ((uint32_t)0x00000020) /*!< channel ack flag */
+#define USB_OTG_HC_NYET_FLAG ((uint32_t)0x00000040) /*!< channel nyet flag */
+#define USB_OTG_HC_XACTERR_FLAG ((uint32_t)0x00000080) /*!< channel transaction error flag */
+#define USB_OTG_HC_BBLERR_FLAG ((uint32_t)0x00000100) /*!< channel babble error flag */
+#define USB_OTG_HC_FRMOVRRUN_FLAG ((uint32_t)0x00000200) /*!< channel frame overrun flag */
+#define USB_OTG_HC_DTGLERR_FLAG ((uint32_t)0x00000400) /*!< channel data toggle flag */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup USB_device_config_definition
+ * @{
+ */
+/**
+ * @brief usb device periodic frame interval
+ */
+typedef enum
+{
+ DCFG_PERFRINT_80 = 0x00, /*!< periodic frame interval 80% */
+ DCFG_PERFRINT_85 = 0x01, /*!< periodic frame interval 85% */
+ DCFG_PERFRINT_90 = 0x02, /*!< periodic frame interval 90% */
+ DCFG_PERFRINT_95 = 0x03 /*!< periodic frame interval 95% */
+} dcfg_perfrint_type;
+
+
+/**
+ * @brief usb device full speed
+ */
+#define USB_DCFG_FULL_SPEED 3 /*!< device full speed */
+
+/**
+ * @brief usb device ctrl define
+ */
+#define USB_OTG_DCTL_RWKUPSIG ((uint32_t)0x00000001) /*!< usb device remote wakeup signaling */
+#define USB_OTG_DCTL_SFTDISCON ((uint32_t)0x00000002) /*!< usb device soft disconnect */
+#define USB_OTG_DCTL_GNPINNAKSTS ((uint32_t)0x00000004) /*!< usb device global non-periodic in nak status */
+#define USB_OTG_DCTL_GOUTNAKSTS ((uint32_t)0x00000008) /*!< usb device global out nak status */
+#define USB_OTG_DCTL_SGNPINNAK ((uint32_t)0x00000080) /*!< usb device set global non-periodic in nak */
+#define USB_OTG_DCTL_CGNPINNAK ((uint32_t)0x00000100) /*!< usb device clear global non-periodic in nak */
+#define USB_OTG_DCTL_SGOUTNAK ((uint32_t)0x00000200) /*!< usb device set global out nak status */
+#define USB_OTG_DCTL_CGOUTNAK ((uint32_t)0x00000400) /*!< usb device clear global out nak status */
+#define USB_OTG_DCTL_PWROPRGDNE ((uint32_t)0x00000800) /*!< usb device power on programming done */
+
+/**
+ * @brief usb device in endpoint flag
+ */
+#define USB_OTG_DIEPINT_XFERC_FLAG ((uint32_t)0x00000001) /*!< usb device in transfer completed flag */
+#define USB_OTG_DIEPINT_EPTDISD_FLAG ((uint32_t)0x00000002) /*!< usb device endpoint disable flag */
+#define USB_OTG_DIEPINT_TIMEOUT_FLAG ((uint32_t)0x00000008) /*!< usb device in timeout */
+#define USB_OTG_DIEPINT_INTKNTXFEMP_FLAG ((uint32_t)0x00000010) /*!< usb device in token received when tx fifo is empty flag */
+#define USB_OTG_DIEPINT_INEPTNAK_FLAG ((uint32_t)0x00000040) /*!< usb device in endpoint nak effective flag */
+#define USB_OTG_DIEPINT_TXFEMP_FLAG ((uint32_t)0x00000080) /*!< usb device transmit fifo empty flag */
+
+/**
+ * @brief usb device out endpoint flag
+ */
+#define USB_OTG_DOEPINT_XFERC_FLAG ((uint32_t)0x00000001) /*!< usb device out transfer completed flag */
+#define USB_OTG_DOEPINT_EPTDISD_FLAG ((uint32_t)0x00000002) /*!< usb device endpoint disable flag */
+#define USB_OTG_DOEPINT_SETUP_FLAG ((uint32_t)0x00000008) /*!< usb device setup flag */
+#define USB_OTG_DOEPINT_OUTTEPD_FLAG ((uint32_t)0x00000010) /*!< usb device out token recevied when endpoint disable flag */
+#define USB_OTG_DOEPINT_B2BSTUP_FLAG ((uint32_t)0x00000040) /*!< back-to-back setup packets received */
+
+/**
+ * @brief usb device in endpoint fifo space mask
+ */
+#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< usb device in endpoint tx fifo space avail */
+
+/**
+ * @brief endpoint0 maximum packet size
+ */
+#define USB_EPT0_MPS_64 0 /*!< usb device endpoint 0 maximum packet size 64byte */
+#define USB_EPT0_MPS_32 1 /*!< usb device endpoint 0 maximum packet size 32byte */
+#define USB_EPT0_MPS_16 2 /*!< usb device endpoint 0 maximum packet size 16byte */
+#define USB_EPT0_MPS_8 3 /*!< usb device endpoint 0 maximum packet size 8byte */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief otg fifo size (word)
+ */
+#define OTG_FIFO_SIZE 320 /*!< otg usb total fifo size */
+
+/**
+ * @brief otg host max buffer length (byte)
+ */
+#define USB_MAX_DATA_LENGTH 0x200 /*!< usb host maximum buffer size */
+
+#define OTGFS_USB_GLOBAL
+#define OTGFS_USB_DEVICE
+#define OTGFS_USB_HOST
+
+/** @defgroup USB_exported_enum_types
+ * @{
+ */
+
+/**
+ * @brief usb mode define(device, host, drd)
+ */
+typedef enum
+{
+ OTG_DEVICE_MODE, /*!< usb device mode */
+ OTG_HOST_MODE, /*!< usb host mode */
+ OTG_DRD_MODE /*!< usb drd mode */
+} otg_mode_type;
+
+/**
+ * @brief endpoint type define
+ */
+typedef enum
+{
+ EPT_CONTROL_TYPE = 0x00, /*!< usb endpoint type control */
+ EPT_ISO_TYPE = 0x01, /*!< usb endpoint type iso */
+ EPT_BULK_TYPE = 0x02, /*!< usb endpoint type bulk */
+ EPT_INT_TYPE = 0x03 /*!< usb endpoint type interrupt */
+} endpoint_trans_type;
+
+/**
+ * @brief usb endpoint number define type
+ */
+typedef enum
+{
+ USB_EPT0 = 0x00, /*!< usb endpoint 0 */
+ USB_EPT1 = 0x01, /*!< usb endpoint 1 */
+ USB_EPT2 = 0x02, /*!< usb endpoint 2 */
+ USB_EPT3 = 0x03, /*!< usb endpoint 3 */
+ USB_EPT4 = 0x04, /*!< usb endpoint 4 */
+ USB_EPT5 = 0x05, /*!< usb endpoint 5 */
+ USB_EPT6 = 0x06, /*!< usb endpoint 6 */
+ USB_EPT7 = 0x07 /*!< usb endpoint 7 */
+} usb_endpoint_number_type;
+
+/**
+ * @brief usb endpoint max num define
+ */
+#ifndef USB_EPT_MAX_NUM
+#define USB_EPT_MAX_NUM 8 /*!< usb device support endpoint number */
+#endif
+/**
+ * @brief usb channel max num define
+ */
+#ifndef USB_HOST_CHANNEL_NUM
+#define USB_HOST_CHANNEL_NUM 16 /*!< usb host support channel number */
+#endif
+
+/**
+ * @brief endpoint trans dir type
+ */
+typedef enum
+{
+ EPT_DIR_IN = 0x00, /*!< usb transfer direction in */
+ EPT_DIR_OUT = 0x01 /*!< usb transfer direction out */
+} endpoint_dir_type;
+
+/**
+ * @brief otgfs1 and otgfs2 select type
+ */
+typedef enum
+{
+ USB_OTG1_ID, /*!< usb otg 1 id */
+ USB_OTG2_ID /*!< usb otg 2 id */
+} otg_id_type;
+
+/**
+ * @brief usb clock select
+ */
+typedef enum
+{
+ USB_CLK_HICK, /*!< usb clock use hick */
+ USB_CLK_HEXT /*!< usb clock use hext */
+}usb_clk48_s;
+
+/**
+ * @}
+ */
+
+
+
+/** @defgroup USB_exported_types
+ * @{
+ */
+
+/**
+ * @brief usb endpoint infomation structure definition
+ */
+typedef struct
+{
+ uint8_t eptn; /*!< endpoint register number (0~7) */
+ uint8_t ept_address; /*!< endpoint address */
+ uint8_t inout; /*!< endpoint dir EPT_DIR_IN or EPT_DIR_OUT */
+ uint8_t trans_type; /*!< endpoint type:
+ EPT_CONTROL_TYPE, EPT_BULK_TYPE, EPT_INT_TYPE, EPT_ISO_TYPE*/
+ uint16_t tx_addr; /*!< endpoint tx buffer offset address */
+ uint16_t rx_addr; /*!< endpoint rx buffer offset address */
+ uint32_t maxpacket; /*!< endpoint max packet*/
+ uint8_t is_double_buffer; /*!< endpoint double buffer flag */
+ uint8_t stall; /*!< endpoint is stall state */
+ uint32_t status;
+
+ /* transmission buffer and count */
+ uint8_t *trans_buf; /*!< endpoint transmission buffer */
+ uint32_t total_len; /*!< endpoint transmission lengtg */
+ uint32_t trans_len; /*!< endpoint transmission length*/
+
+ uint32_t last_len; /*!< last transfer length */
+ uint32_t ept0_slen; /*!< endpoint 0 transfer sum length */
+} usb_ept_info;
+
+
+/**
+ * @brief usb host channel infomation structure definition
+ */
+typedef struct
+{
+ uint8_t ch_num; /*!< host channel number */
+ uint8_t address; /*!< device address */
+ uint8_t dir; /*!< transmission direction */
+ uint8_t ept_num; /*!< device endpoint number */
+ uint8_t ept_type; /*!< channel transmission type */
+ uint32_t maxpacket; /*!< support max packet size */
+ uint8_t data_pid; /*!< data pid */
+ uint8_t speed; /*!< usb speed */
+ uint8_t stall; /*!< channel stall flag */
+ uint32_t status; /*!< channel status */
+ uint32_t state; /*!< channel state */
+ uint32_t urb_sts; /*!< usb channel request block state */
+
+ uint8_t toggle_in; /*!< channel in transfer toggle */
+ uint8_t toggle_out; /*!< channel out transfer toggle */
+
+ /* transmission buffer and count */
+ uint8_t *trans_buf; /* host channel buffer */
+ uint32_t trans_len; /* host channel transmission len */
+ uint32_t trans_count; /* host channel transmission count*/
+} usb_hch_type;
+
+
+typedef struct
+{
+ /**
+ * @brief otgfs control and status register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t gotgctrl;
+ struct
+ {
+ __IO uint32_t reserved1 : 16; /* [15:0] */
+ __IO uint32_t cidsts : 1; /* [16] */
+ __IO uint32_t reserved2 : 4; /* [20:17] */
+ __IO uint32_t curmod : 1; /* [21] */
+ __IO uint32_t reserved3 : 10; /* [31:22] */
+ } gotgctrl_bit;
+ };
+
+ /**
+ * @brief otgfs interrupt register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t gotgint;
+ struct
+ {
+ __IO uint32_t reserved1 : 2; /* [1:0] */
+ __IO uint32_t sesenddet : 1; /* [2] */
+ __IO uint32_t reserved2 : 29; /* [31:3] */
+
+ } gotgint_bit;
+ };
+
+ /**
+ * @brief otgfs gahbcfg configuration register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t gahbcfg;
+ struct
+ {
+ __IO uint32_t glbintmsk : 1; /* [0] */
+ __IO uint32_t reserved1 : 6; /* [6:1] */
+ __IO uint32_t nptxfemplvl : 1; /* [7] */
+ __IO uint32_t ptxfemplvl : 1; /* [8] */
+ __IO uint32_t reserved2 : 23; /* [31:9] */
+ } gahbcfg_bit;
+ };
+
+ /**
+ * @brief otgfs usb configuration register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t gusbcfg;
+ struct
+ {
+ __IO uint32_t toutcal : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 7; /* [9:3] */
+ __IO uint32_t usbtrdtim : 4; /* [13:10] */
+ __IO uint32_t reserved2 : 15; /* [28:14] */
+ __IO uint32_t fhstmode : 1; /* [29] */
+ __IO uint32_t fdevmode : 1; /* [30] */
+ __IO uint32_t cotxpkt : 1; /* [31] */
+ } gusbcfg_bit;
+ };
+
+ /**
+ * @brief otgfs reset register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t grstctl;
+ struct
+ {
+ __IO uint32_t csftrst : 1; /* [0] */
+ __IO uint32_t piusftrst : 1; /* [1] */
+ __IO uint32_t frmcntrst : 1; /* [2] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t rxfflsh : 1; /* [4] */
+ __IO uint32_t txfflsh : 1; /* [5] */
+ __IO uint32_t txfnum : 5; /* [10:6] */
+ __IO uint32_t reserved2 : 20; /* [30:11] */
+ __IO uint32_t ahbidle : 1; /* [31] */
+ } grstctl_bit;
+ };
+
+ /**
+ * @brief otgfs core interrupt register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t gintsts;
+ struct
+ {
+ __IO uint32_t curmode : 1; /* [0] */
+ __IO uint32_t modemis : 1; /* [1] */
+ __IO uint32_t otgint : 1; /* [2] */
+ __IO uint32_t sof : 1; /* [3] */
+ __IO uint32_t rxflvl : 1; /* [4] */
+ __IO uint32_t nptxfemp : 1; /* [5] */
+ __IO uint32_t ginnakeff : 1; /* [6] */
+ __IO uint32_t goutnakeff : 1; /* [7] */
+ __IO uint32_t reserved1 : 2; /* [9:8]] */
+ __IO uint32_t erlysusp : 1; /* [10] */
+ __IO uint32_t usbsusp : 1; /* [11] */
+ __IO uint32_t usbrst : 1; /* [12] */
+ __IO uint32_t enumdone : 1; /* [13] */
+ __IO uint32_t isooutdrop : 1; /* [14] */
+ __IO uint32_t eopf : 1; /* [15] */
+ __IO uint32_t reserved2 : 2; /* [17:16]] */
+ __IO uint32_t ieptint : 1; /* [18] */
+ __IO uint32_t oeptint : 1; /* [19] */
+ __IO uint32_t incompisoin : 1; /* [20] */
+ __IO uint32_t incompip_incompisoout : 1; /* [21] */
+ __IO uint32_t reserved3 : 2; /* [23:22] */
+ __IO uint32_t prtint : 1; /* [24] */
+ __IO uint32_t hchint : 1; /* [25] */
+ __IO uint32_t ptxfemp : 1; /* [26] */
+ __IO uint32_t reserved4 : 1; /* [27] */
+ __IO uint32_t conidschg : 1; /* [28] */
+ __IO uint32_t disconint : 1; /* [29] */
+ __IO uint32_t reserved5 : 1; /* [30] */
+ __IO uint32_t wkupint : 1; /* [31] */
+ } gintsts_bit;
+ };
+
+ /**
+ * @brief otgfs interrupt mask register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t gintmsk;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t modemismsk : 1; /* [1] */
+ __IO uint32_t otgintmsk : 1; /* [2] */
+ __IO uint32_t sofmsk : 1; /* [3] */
+ __IO uint32_t rxflvlmsk : 1; /* [4] */
+ __IO uint32_t nptxfempmsk : 1; /* [5] */
+ __IO uint32_t ginnakeffmsk : 1; /* [6] */
+ __IO uint32_t goutnakeffmsk : 1; /* [7] */
+ __IO uint32_t reserved2 : 2; /* [9:8]] */
+ __IO uint32_t erlysuspmsk : 1; /* [10] */
+ __IO uint32_t usbsuspmsk : 1; /* [11] */
+ __IO uint32_t usbrstmsk : 1; /* [12] */
+ __IO uint32_t enumdonemsk : 1; /* [13] */
+ __IO uint32_t isooutdropmsk : 1; /* [14] */
+ __IO uint32_t eopfmsk : 1; /* [15] */
+ __IO uint32_t reserved3 : 2; /* [17:16]] */
+ __IO uint32_t ieptintmsk : 1; /* [18] */
+ __IO uint32_t oeptintmsk : 1; /* [19] */
+ __IO uint32_t incompisoinmsk : 1; /* [20] */
+ __IO uint32_t incompip_incompisooutmsk : 1; /* [21] */
+ __IO uint32_t reserved4 : 2; /* [23:22] */
+ __IO uint32_t prtintmsk : 1; /* [24] */
+ __IO uint32_t hchintmsk : 1; /* [25] */
+ __IO uint32_t ptxfempmsk : 1; /* [26] */
+ __IO uint32_t reserved5 : 1; /* [27] */
+ __IO uint32_t conidschgmsk : 1; /* [28] */
+ __IO uint32_t disconintmsk : 1; /* [29] */
+ __IO uint32_t reserved6 : 1; /* [30] */
+ __IO uint32_t wkupintmsk : 1; /* [31] */
+ } gintmsk_bit;
+ };
+
+ /**
+ * @brief otgfs rx status debug read register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t grxstsr;
+ struct
+ {
+ __IO uint32_t eptnum : 4; /* [3:0] */
+ __IO uint32_t bcnt : 11; /* [14:4] */
+ __IO uint32_t dpid : 2; /* [16:15] */
+ __IO uint32_t pktsts : 4; /* [20:17] */
+ __IO uint32_t fn : 4; /* [24:21] */
+ __IO uint32_t reserved1 : 7; /* [31:25] */
+ } grxstsr_bit;
+ };
+
+ /**
+ * @brief otgfs rx status read and pop register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t grxstsp;
+ struct
+ {
+ __IO uint32_t chnum : 4; /* [3:0] */
+ __IO uint32_t bcnt : 11; /* [14:4] */
+ __IO uint32_t dpid : 2; /* [16:15] */
+ __IO uint32_t pktsts : 4; /* [20:17] */
+ __IO uint32_t reserved1 : 11; /* [31:21] */
+ } grxstsp_bit;
+ };
+
+ /**
+ * @brief otgfs rx fifo size register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t grxfsiz;
+ struct
+ {
+ __IO uint32_t rxfdep : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } grxfsiz_bit;
+ };
+
+ /**
+ * @brief otgfs non-periodic and ept0 tx fifo size register, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t gnptxfsiz_ept0tx;
+ struct
+ {
+ __IO uint32_t nptxfstaddr : 16; /* [15:0] */
+ __IO uint32_t nptxfdep : 16; /* [31:16] */
+ } gnptxfsiz_ept0tx_bit;
+ };
+
+ /**
+ * @brief otgfs non-periodic tx fifo request queue status register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t gnptxsts;
+ struct
+ {
+ __IO uint32_t nptxfspcavail : 16; /* [15:0] */
+ __IO uint32_t nptxqspcavail : 8; /* [23:16] */
+ __IO uint32_t nptxqtop : 7; /* [30:24] */
+ } gnptxsts_bit;
+ };
+
+ __IO uint32_t reserved2[2];
+
+ /**
+ * @brief otgfs general core configuration register, offset:0x38
+ */
+ union
+ {
+ __IO uint32_t gccfg;
+ struct
+ {
+ __IO uint32_t reserved1 : 16; /* [15:0] */
+ __IO uint32_t pwrdown : 1; /* [16] */
+ __IO uint32_t lp_mode : 1; /* [17] */
+ __IO uint32_t reserved2 : 2; /* [19:18] */
+ __IO uint32_t sofouten : 1; /* [20] */
+ __IO uint32_t vbusig : 1; /* [21] */
+ __IO uint32_t reserved3 : 10; /* [31:22] */
+ } gccfg_bit;
+ };
+
+ /**
+ * @brief otgfs core id register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t guid;
+ struct
+ {
+ __IO uint32_t userid : 32; /* [31:0] */
+ } guid_bit;
+ };
+
+ __IO uint32_t reserved3[48];
+
+ /**
+ * @brief otgfs host periodic tx fifo size register, offset:0x100
+ */
+ union
+ {
+ __IO uint32_t hptxfsiz;
+ struct
+ {
+ __IO uint32_t ptxfstaddr : 16; /* [15:0] */
+ __IO uint32_t ptxfsize : 16; /* [31:16] */
+ } hptxfsiz_bit;
+ };
+
+ /**
+ * @brief otgfs host periodic tx fifo size register, offset:0x100
+ */
+ union
+ {
+ __IO uint32_t dieptxfn[7];
+ struct
+ {
+ __IO uint32_t ineptxfstaddr : 16; /* [15:0] */
+ __IO uint32_t ineptxfdep : 16; /* [31:16] */
+ } dieptxfn_bit[7];
+ };
+} otg_global_type;
+
+
+typedef struct
+{
+ /**
+ * @brief otgfs host mode configuration register, offset:0x400
+ */
+ union
+ {
+ __IO uint32_t hcfg;
+ struct
+ {
+ __IO uint32_t fslspclksel : 2; /* [1:0] */
+ __IO uint32_t fslssupp : 1; /* [2] */
+ __IO uint32_t reserved1 : 29; /* [31:3] */
+ } hcfg_bit;
+ };
+
+ /**
+ * @brief otgfs host frame interval register, offset:0x404
+ */
+ union
+ {
+ __IO uint32_t hfir;
+ struct
+ {
+ __IO uint32_t frint : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:15] */
+ } hfir_bit;
+ };
+
+ /**
+ * @brief otgfs host frame number and time remaining register, offset:0x408
+ */
+ union
+ {
+ __IO uint32_t hfnum;
+ struct
+ {
+ __IO uint32_t frnum : 16; /* [15:0] */
+ __IO uint32_t ftrem : 16; /* [31:15] */
+ } hfnum_bit;
+ };
+
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief otgfs host periodic tx fifo request queue register, offset:0x410
+ */
+ union
+ {
+ __IO uint32_t hptxsts;
+ struct
+ {
+ __IO uint32_t ptxfspcavil : 16; /* [15:0] */
+ __IO uint32_t ptxqspcavil : 8; /* [23:16] */
+ __IO uint32_t ptxqtop : 8; /* [31:24] */
+ } hptxsts_bit;
+ };
+
+ /**
+ * @brief otgfs host all channel interrupt register, offset:0x414
+ */
+ union
+ {
+ __IO uint32_t haint;
+ struct
+ {
+ __IO uint32_t haint : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [32:16] */
+ } haint_bit;
+ };
+
+ /**
+ * @brief otgfs host all channel interrupt mask register, offset:0x418
+ */
+ union
+ {
+ __IO uint32_t haintmsk;
+ struct
+ {
+ __IO uint32_t haintmsk : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [32:16] */
+ } haintmsk_bit;
+ };
+
+ __IO uint32_t reserved2[9];
+
+ /**
+ * @brief otgfs host port control and status register, offset:0x440
+ */
+ union
+ {
+ __IO uint32_t hprt;
+ struct
+ {
+ __IO uint32_t prtconsts : 1; /* [0] */
+ __IO uint32_t prtcondet : 1; /* [1] */
+ __IO uint32_t prtena : 1; /* [2] */
+ __IO uint32_t prtenchng : 1; /* [3] */
+ __IO uint32_t prtovrcact : 1; /* [4] */
+ __IO uint32_t prtovrcchng : 1; /* [5] */
+ __IO uint32_t prtres : 1; /* [6] */
+ __IO uint32_t prtsusp : 1; /* [7] */
+ __IO uint32_t prtrst : 1; /* [8] */
+ __IO uint32_t reserved1 : 1; /* [9] */
+ __IO uint32_t prtlnsts : 2; /* [11:10] */
+ __IO uint32_t prtpwr : 1; /* [12] */
+ __IO uint32_t prttsctl : 4; /* [16:13] */
+ __IO uint32_t prtspd : 2; /* [18:17] */
+ __IO uint32_t reserved2 : 13; /* [31:19] */
+
+ } hprt_bit;
+ };
+} otg_host_type;
+
+typedef struct
+{
+ /**
+ * @brief otgfs host channel x characterisic register, offset:0x500
+ */
+ union
+ {
+ __IO uint32_t hcchar;
+ struct
+ {
+ __IO uint32_t mps : 11; /* [10:0] */
+ __IO uint32_t eptnum : 4; /* [14:11] */
+ __IO uint32_t eptdir : 1; /* [15] */
+ __IO uint32_t reserved1 : 1; /* [16] */
+ __IO uint32_t lspddev : 1; /* [17] */
+ __IO uint32_t eptype : 2; /* [19:18] */
+ __IO uint32_t mc : 2; /* [21:20] */
+ __IO uint32_t devaddr : 7; /* [28:22] */
+ __IO uint32_t oddfrm : 1; /* [29] */
+ __IO uint32_t chdis : 1; /* [30] */
+ __IO uint32_t chena : 1; /* [31] */
+ } hcchar_bit;
+ };
+
+ /**
+ * @brief otgfs host channel split control register, offset:0x504
+ */
+ union
+ {
+ __IO uint32_t hcsplt;
+ struct
+ {
+ __IO uint32_t prtaddr : 7; /* [6:0] */
+ __IO uint32_t hubaddr : 7; /* [13:7] */
+ __IO uint32_t xactpos : 2; /* [15:14] */
+ __IO uint32_t compsplt : 1; /* [16] */
+ __IO uint32_t reserved1 : 14; /* [30:17] */
+ __IO uint32_t spltena : 1; /* [31] */
+ } hcsplt_bit;
+ };
+
+ /**
+ * @brief otgfs host channel interrupt register, offset:0x508
+ */
+ union
+ {
+ __IO uint32_t hcint;
+ struct
+ {
+ __IO uint32_t xferc : 1; /* [0] */
+ __IO uint32_t chhltd : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t stall : 1; /* [3] */
+ __IO uint32_t nak : 1; /* [4] */
+ __IO uint32_t ack : 1; /* [5] */
+ __IO uint32_t reserved2 : 1; /* [6] */
+ __IO uint32_t xacterr : 1; /* [7] */
+ __IO uint32_t bblerr : 1; /* [8] */
+ __IO uint32_t frmovrun : 1; /* [9] */
+ __IO uint32_t dtglerr : 1; /* [10] */
+ __IO uint32_t reserved3 : 21; /* [31:11] */
+ } hcint_bit;
+ };
+
+ /**
+ * @brief otgfs host channel interrupt mask register, offset:0x50C
+ */
+ union
+ {
+ __IO uint32_t hcintmsk;
+ struct
+ {
+ __IO uint32_t xfercmsk : 1; /* [0] */
+ __IO uint32_t chhltdmsk : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t stallmsk : 1; /* [3] */
+ __IO uint32_t nakmsk : 1; /* [4] */
+ __IO uint32_t ackmsk : 1; /* [5] */
+ __IO uint32_t reserved2 : 1; /* [6] */
+ __IO uint32_t xacterrmsk : 1; /* [7] */
+ __IO uint32_t bblerrmsk : 1; /* [8] */
+ __IO uint32_t frmovrunmsk : 1; /* [9] */
+ __IO uint32_t dtglerrmsk : 1; /* [10] */
+ __IO uint32_t reserved3 : 21; /* [31:11] */
+ } hcintmsk_bit;
+ };
+
+ /**
+ * @brief otgfs host channel transfer size register, offset:0x510
+ */
+ union
+ {
+ __IO uint32_t hctsiz;
+ struct
+ {
+ __IO uint32_t xfersize : 19; /* [18:0] */
+ __IO uint32_t pktcnt : 10; /* [28:19] */
+ __IO uint32_t pid : 2; /* [30:29] */
+ __IO uint32_t reserved1 : 1; /* [31] */
+ } hctsiz_bit;
+ };
+ __IO uint32_t reserved3[3];
+
+}otg_hchannel_type;
+
+
+typedef struct
+{
+ /**
+ * @brief otgfs device configuration register, offset:0x800
+ */
+ union
+ {
+ __IO uint32_t dcfg;
+ struct
+ {
+ __IO uint32_t devspd : 2; /* [1:0] */
+ __IO uint32_t nzstsouthshk : 1; /* [2] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t devaddr : 7; /* [10:4] */
+ __IO uint32_t perfrint : 2; /* [12:11] */
+ __IO uint32_t reserved2 : 19; /* [31:13] */
+ } dcfg_bit;
+ };
+
+ /**
+ * @brief otgfs device controls register, offset:0x804
+ */
+ union
+ {
+ __IO uint32_t dctl;
+ struct
+ {
+ __IO uint32_t rwkupsig : 1; /* [0] */
+ __IO uint32_t sftdiscon : 1; /* [1] */
+ __IO uint32_t gnpinnaksts : 1; /* [2] */
+ __IO uint32_t goutnaksts : 1; /* [3] */
+ __IO uint32_t tstctl : 3; /* [6:4] */
+ __IO uint32_t sgnpinak : 1; /* [7] */
+ __IO uint32_t cgnpinak : 1; /* [8] */
+ __IO uint32_t sgoutnak : 1; /* [9] */
+ __IO uint32_t cgoutnak : 1; /* [10] */
+ __IO uint32_t pwroprgdne : 1; /* [11] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } dctl_bit;
+ };
+
+ /**
+ * @brief otgfs device status register, offset:0x80C
+ */
+ union
+ {
+ __IO uint32_t dsts;
+ struct
+ {
+ __IO uint32_t suspsts : 1; /* [0] */
+ __IO uint32_t enumspd : 2; /* [2:1] */
+ __IO uint32_t eticerr : 1; /* [3] */
+ __IO uint32_t reserved1 : 4; /* [7:4] */
+ __IO uint32_t soffn : 14; /* [21:8] */
+ __IO uint32_t reserved2 : 10; /* [31:22] */
+ } dsts_bit;
+ };
+
+ __IO uint32_t reserved1;
+ /**
+ * @brief otgfs device in endpoint general interrupt mask register, offset:0x810
+ */
+ union
+ {
+ __IO uint32_t diepmsk;
+ struct
+ {
+ __IO uint32_t xfercmsk : 1; /* [0] */
+ __IO uint32_t eptdismsk : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t timeoutmsk : 1; /* [3] */
+ __IO uint32_t intkntxfempmsk : 1; /* [4] */
+ __IO uint32_t intkneptmismsk : 1; /* [5] */
+ __IO uint32_t ineptnakmsk : 1; /* [6] */
+ __IO uint32_t reserved2 : 1; /* [7] */
+ __IO uint32_t txfifoudrmsk : 1; /* [8] */
+ __IO uint32_t bnainmsk : 1; /* [9] */
+ __IO uint32_t reserved3 : 22; /* [31:10] */
+ } diepmsk_bit;
+ };
+
+ /**
+ * @brief otgfs device out endpoint general interrupt mask register, offset:0x814
+ */
+ union
+ {
+ __IO uint32_t doepmsk;
+ struct
+ {
+ __IO uint32_t xfercmsk : 1; /* [0] */
+ __IO uint32_t eptdismsk : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t setupmsk : 1; /* [3] */
+ __IO uint32_t outtepdmsk : 1; /* [4] */
+ __IO uint32_t reserved2 : 1; /* [5] */
+ __IO uint32_t b2bsetupmsk : 1; /* [6] */
+ __IO uint32_t reserved3 : 1; /* [7] */
+ __IO uint32_t outperrmsk : 1; /* [8] */
+ __IO uint32_t bnaoutmsk : 1; /* [9] */
+ __IO uint32_t reserved4 : 22; /* [31:10] */
+ } doepmsk_bit;
+ };
+
+ /**
+ * @brief otgfs device all endpoint interrupt register, offset:0x818
+ */
+ union
+ {
+ __IO uint32_t daint;
+ struct
+ {
+ __IO uint32_t ineptint : 16; /* [15:0] */
+ __IO uint32_t outeptint : 16; /* [31:16] */
+ } daint_bit;
+ };
+
+ /**
+ * @brief otgfs device all endpoint interrupt mask register, offset:0x81C
+ */
+ union
+ {
+ __IO uint32_t daintmsk;
+ struct
+ {
+ __IO uint32_t ineptmsk : 16; /* [15:0] */
+ __IO uint32_t outeptmsk : 16; /* [31:16] */
+ } daintmsk_bit;
+ };
+
+ __IO uint32_t reserved2[5];
+
+ /**
+ * @brief otgfs device in endpoint fifo empty interrupt mask register, offset:0x834
+ */
+ union
+ {
+ __IO uint32_t diepempmsk;
+ struct
+ {
+ __IO uint32_t ineptxfemsk : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } diepempmsk_bit;
+ };
+
+} otg_device_type;
+
+typedef struct
+{
+ /**
+ * @brief otgfs device out endpoint control register, offset:0x900
+ */
+ union
+ {
+ __IO uint32_t diepctl;
+ struct
+ {
+ __IO uint32_t mps : 11; /* [10:0] */
+ __IO uint32_t reserved1 : 4; /* [14:11] */
+ __IO uint32_t usbacept : 1; /* [15] */
+ __IO uint32_t dpid : 1; /* [16] */
+ __IO uint32_t naksts : 1; /* [17] */
+ __IO uint32_t eptype : 2; /* [19:18] */
+ __IO uint32_t reserved2 : 1; /* [20] */
+ __IO uint32_t stall : 1; /* [21] */
+ __IO uint32_t txfnum : 4; /* [25:22] */
+ __IO uint32_t cnak : 1; /* [26] */
+ __IO uint32_t snak : 1; /* [27] */
+ __IO uint32_t setd0pid : 1; /* [28] */
+ __IO uint32_t setd1pid : 1; /* [29] */
+ __IO uint32_t eptdis : 1; /* [30] */
+ __IO uint32_t eptena : 1; /* [31] */
+ } diepctl_bit;
+ };
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief otgfs device in endpoint interrupt register, offset:0x908
+ */
+ union
+ {
+ __IO uint32_t diepint;
+ struct
+ {
+ __IO uint32_t xferc : 1; /* [0] */
+ __IO uint32_t epdisd : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t timeout : 1; /* [3] */
+ __IO uint32_t intkntxfemp : 1; /* [4] */
+ __IO uint32_t reserved2 : 1; /* [5] */
+ __IO uint32_t ineptnak : 1; /* [6] */
+ __IO uint32_t txfemp : 1; /* [7] */
+ __IO uint32_t reserved3 : 24; /* [31:8] */
+ } diepint_bit;
+ };
+ __IO uint32_t reserved2;
+
+ /**
+ * @brief otgfs device in endpoint transfer size register, offset:0x910 + endpoint number * 0x20
+ */
+ union
+ {
+ __IO uint32_t dieptsiz;
+ struct
+ {
+ __IO uint32_t xfersize : 19; /* [18:0] */
+ __IO uint32_t pktcnt : 10; /* [28:19] */
+ __IO uint32_t mc : 2; /* [30:29] */
+ __IO uint32_t reserved1 : 1; /* [31] */
+ } dieptsiz_bit;
+ };
+
+ __IO uint32_t reserved3;
+
+ /**
+ * @brief otgfs device in endpoint tx fifo status register, offset:0x918 + endpoint number * 0x20
+ */
+ union
+ {
+ __IO uint32_t dtxfsts;
+ struct
+ {
+ __IO uint32_t ineptxfsav : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } dtxfsts_bit;
+ };
+
+} otg_eptin_type;
+
+typedef struct
+{
+ /**
+ * @brief otgfs device out endpoint control register, offset:0xb00 + endpoint number * 0x20
+ */
+ union
+ {
+ __IO uint32_t doepctl;
+ struct
+ {
+ __IO uint32_t mps : 11; /* [10:0] */
+ __IO uint32_t reserved1 : 4; /* [14:11] */
+ __IO uint32_t usbacept : 1; /* [15] */
+ __IO uint32_t dpid : 1; /* [16] */
+ __IO uint32_t naksts : 1; /* [17] */
+ __IO uint32_t eptype : 2; /* [19:18] */
+ __IO uint32_t snpm : 1; /* [20] */
+ __IO uint32_t stall : 1; /* [21] */
+ __IO uint32_t reserved2 : 4; /* [25:22] */
+ __IO uint32_t cnak : 1; /* [26] */
+ __IO uint32_t snak : 1; /* [27] */
+ __IO uint32_t setd0pid : 1; /* [28] */
+ __IO uint32_t setd1pid : 1; /* [29] */
+ __IO uint32_t eptdis : 1; /* [30] */
+ __IO uint32_t eptena : 1; /* [31] */
+ } doepctl_bit;
+ };
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief otgfs device out endpoint interrupt register, offset:0xb08 + endpoint number * 0x20
+ */
+ union
+ {
+ __IO uint32_t doepint;
+ struct
+ {
+ __IO uint32_t xferc : 1; /* [0] */
+ __IO uint32_t epdisd : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t setup : 1; /* [3] */
+ __IO uint32_t outtepd : 1; /* [4] */
+ __IO uint32_t reserved2 : 1; /* [5] */
+ __IO uint32_t b2pstup : 1; /* [6] */
+ __IO uint32_t reserved3 : 25; /* [31:7] */
+ } doepint_bit;
+ };
+ __IO uint32_t reserved2;
+
+ /**
+ * @brief otgfs device out endpoint transfer size register, offset:0xb10 + endpoint number * 0x20
+ */
+ union
+ {
+ __IO uint32_t doeptsiz;
+ struct
+ {
+ __IO uint32_t xfersize : 19; /* [18:0] */
+ __IO uint32_t pktcnt : 10; /* [28:19] */
+ __IO uint32_t rxdpid_setupcnt : 2; /* [30:29] */
+ __IO uint32_t reserved1 : 1; /* [31] */
+ } doeptsiz_bit;
+ };
+} otg_eptout_type;
+
+typedef struct
+{
+ /**
+ * @brief otgfs power and clock gating control registers, offset:0xe00
+ */
+ union
+ {
+ __IO uint32_t pcgcctl;
+ struct
+ {
+ __IO uint32_t stoppclk : 1; /* [0] */
+ __IO uint32_t reserved1 : 3; /* [3:1] */
+ __IO uint32_t suspendm : 1; /* [4] */
+ __IO uint32_t reserved2 : 27; /* [31:5] */
+ } pcgcctl_bit;
+ };
+} otg_pcgcctl_type;
+
+/**
+ * @}
+ */
+
+/** @defgroup USB_exported_functions
+ * @{
+ */
+
+/**
+ * @brief usb host and device offset address
+ */
+#define OTG_HOST_ADDR_OFFSET 0x400 /*!< usb host register offset address */
+#define OTG_HOST_CHANNEL_ADDR_OFFSET 0x500 /*!< usb host channel register offset address */
+#define OTG_DEVICE_ADDR_OFFSET 0x800 /*!< usb device register offset address */
+#define OTG_DEVICE_EPTIN_ADDR_OFFSET 0x900 /*!< usb device endpoint in register offset address */
+#define OTG_DEVICE_EPTOUT_ADDR_OFFSET 0xB00 /*!< usb device endpoint out register offset address */
+#define OTG_PCGCCTL_ADDR_OFFSET 0xE00 /*!< usb power and clock control register offset address */
+#define OTG_FIFO_ADDR_OFFSET 0x1000 /*!< usb fifo offset address */
+
+/**
+ * @brief usb host and device register define
+ */
+#define OTG1_GLOBAL ((otg_global_type *)(OTGFS1_BASE)) /*!< usb otg1 global register */
+#define OTG2_GLOBAL ((otg_global_type *)(OTGFS2_BASE)) /*!< usb otg2 global register */
+#define OTG_PCGCCTL(usbx) ((otg_pcgcctl_type *)((uint32_t)usbx + OTG_PCGCCTL_ADDR_OFFSET)) /*!< usb power and clock control register */
+#define OTG_DEVICE(usbx) ((otg_device_type *)((uint32_t)usbx + OTG_DEVICE_ADDR_OFFSET)) /*!< usb device register */
+#define OTG_HOST(usbx) ((otg_host_type *)((uint32_t)usbx + OTG_HOST_ADDR_OFFSET)) /*!< usb host register */
+#define USB_CHL(usbx, n) ((otg_hchannel_type *)((uint32_t)usbx + OTG_HOST_CHANNEL_ADDR_OFFSET + n * 0x20)) /*!< usb channel n register */
+#define USB_INEPT(usbx, eptn) ((otg_eptin_type *)((uint32_t)usbx + OTG_DEVICE_EPTIN_ADDR_OFFSET + eptn * 0x20)) /*!< usb device endpoint in register */
+#define USB_OUTEPT(usbx, eptn) ((otg_eptout_type *)((uint32_t)usbx + OTG_DEVICE_EPTOUT_ADDR_OFFSET + eptn * 0x20)) /*!< usb device endpoint out register */
+#define USB_FIFO(usbx, eptn) *(__IO uint32_t *)((uint32_t)usbx + OTG_FIFO_ADDR_OFFSET + eptn * 0x1000) /*!< usb fifo address */
+
+
+
+typedef otg_global_type usb_reg_type;
+
+/** @defgroup USB_exported_functions
+ * @{
+ */
+
+#ifdef OTGFS_USB_GLOBAL
+error_status usb_global_reset(otg_global_type *usbx);
+void usb_global_init(otg_global_type *usbx);
+otg_global_type *usb_global_select_core(uint8_t usb_id);
+void usb_flush_tx_fifo(otg_global_type *usbx, uint32_t fifo_num);
+void usb_flush_rx_fifo(otg_global_type *usbx);
+void usb_global_interrupt_enable(otg_global_type *usbx, uint16_t interrupt, confirm_state new_state);
+uint32_t usb_global_get_all_interrupt(otg_global_type *usbx);
+void usb_global_clear_interrupt(otg_global_type *usbx, uint32_t flag);
+void usb_interrupt_enable(otg_global_type *usbx);
+void usb_interrupt_disable(otg_global_type *usbx);
+void usb_set_rx_fifo(otg_global_type *usbx, uint16_t size);
+void usb_set_tx_fifo(otg_global_type *usbx, uint8_t txfifo, uint16_t size);
+void usb_global_set_mode(otg_global_type *usbx, uint32_t mode);
+void usb_global_power_on(otg_global_type *usbx);
+void usb_write_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uint16_t nbytes);
+void usb_read_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uint16_t nbytes);
+void usb_stop_phy_clk(otg_global_type *usbx);
+void usb_open_phy_clk(otg_global_type *usbx);
+#endif
+
+#ifdef OTGFS_USB_DEVICE
+void usb_ept_open(otg_global_type *usbx, usb_ept_info *ept_info);
+void usb_ept_close(otg_global_type *usbx, usb_ept_info *ept_info);
+void usb_ept_stall(otg_global_type *usbx, usb_ept_info *ept_info);
+void usb_ept_clear_stall(otg_global_type *usbx, usb_ept_info *ept_info);
+uint32_t usb_get_all_out_interrupt(otg_global_type *usbx);
+uint32_t usb_get_all_in_interrupt(otg_global_type *usbx);
+uint32_t usb_ept_out_interrupt(otg_global_type *usbx, uint32_t eptn);
+uint32_t usb_ept_in_interrupt(otg_global_type *usbx, uint32_t eptn);
+void usb_ept_out_clear(otg_global_type *usbx, uint32_t eptn, uint32_t flag);
+void usb_ept_in_clear(otg_global_type *usbx, uint32_t eptn, uint32_t flag);
+void usb_set_address(otg_global_type *usbx, uint8_t address);
+void usb_ept0_start(otg_global_type *usbx);
+void usb_ept0_setup(otg_global_type *usbx);
+void usb_connect(otg_global_type *usbx);
+void usb_disconnect(otg_global_type *usbx);
+void usb_remote_wkup_set(otg_global_type *usbx);
+void usb_remote_wkup_clear(otg_global_type *usbx);
+uint8_t usb_suspend_status_get(otg_global_type *usbx);
+#endif
+
+#ifdef OTGFS_USB_HOST
+void usb_port_power_on(otg_global_type *usbx, confirm_state state);
+uint32_t usbh_get_frame(otg_global_type *usbx);
+void usb_hc_enable(otg_global_type *usbx,
+ uint8_t chn,
+ uint8_t ept_num,
+ uint8_t dev_address,
+ uint8_t type,
+ uint8_t maxpacket,
+ uint8_t speed);
+uint32_t usb_hch_read_interrupt(otg_global_type *usbx);
+void usb_host_disable(otg_global_type *usbx);
+void usb_hch_halt(otg_global_type *usbx, uint8_t chn);
+void usbh_fsls_clksel(otg_global_type *usbx, uint8_t clk);
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_wdt.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_wdt.h
new file mode 100644
index 0000000..e217c84
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_wdt.h
@@ -0,0 +1,197 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_wdt.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 wdt header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_WDT_H
+#define __AT32F435_437_WDT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup WDT
+ * @{
+ */
+
+
+/** @defgroup WDT_flags_definition
+ * @brief wdt flag
+ * @{
+ */
+
+#define WDT_DIVF_UPDATE_FLAG ((uint16_t)0x0001) /*!< wdt division value update complete flag */
+#define WDT_RLDF_UPDATE_FLAG ((uint16_t)0x0002) /*!< wdt reload value update complete flag */
+#define WDT_WINF_UPDATE_FLAG ((uint16_t)0x0004) /*!< wdt window value update complete flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup WDT_exported_types
+ * @{
+ */
+
+/**
+ * @brief wdt division value type
+ */
+typedef enum
+{
+ WDT_CLK_DIV_4 = 0x00, /*!< wdt clock divider value is 4 */
+ WDT_CLK_DIV_8 = 0x01, /*!< wdt clock divider value is 8 */
+ WDT_CLK_DIV_16 = 0x02, /*!< wdt clock divider value is 16 */
+ WDT_CLK_DIV_32 = 0x03, /*!< wdt clock divider value is 32 */
+ WDT_CLK_DIV_64 = 0x04, /*!< wdt clock divider value is 64 */
+ WDT_CLK_DIV_128 = 0x05, /*!< wdt clock divider value is 128 */
+ WDT_CLK_DIV_256 = 0x06 /*!< wdt clock divider value is 256 */
+} wdt_division_type;
+
+/**
+ * @brief wdt cmd value type
+ */
+typedef enum
+{
+ WDT_CMD_LOCK = 0x0000, /*!< disable write protection command */
+ WDT_CMD_UNLOCK = 0x5555, /*!< enable write protection command */
+ WDT_CMD_ENABLE = 0xCCCC, /*!< enable wdt command */
+ WDT_CMD_RELOAD = 0xAAAA /*!< reload command */
+} wdt_cmd_value_type;
+
+/**
+ * @brief type define wdt register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief wdt cmd register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t cmd;
+ struct
+ {
+ __IO uint32_t cmd : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cmd_bit;
+ };
+
+ /**
+ * @brief wdt div register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t div;
+ struct
+ {
+ __IO uint32_t div : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 29;/* [31:3] */
+ } div_bit;
+ };
+
+ /**
+ * @brief wdt rld register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t rld;
+ struct
+ {
+ __IO uint32_t rld : 12;/* [11:0] */
+ __IO uint32_t reserved1 : 20;/* [31:12] */
+ } rld_bit;
+ };
+
+ /**
+ * @brief wdt sts register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t divf : 1; /* [0] */
+ __IO uint32_t rldf : 1; /* [1] */
+ __IO uint32_t reserved1 : 30;/* [31:2] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief wdt win register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t win;
+ struct
+ {
+ __IO uint32_t win : 12;/* [11:0] */
+ __IO uint32_t reserved1 : 20;/* [31:12] */
+ } win_bit;
+ };
+} wdt_type;
+
+/**
+ * @}
+ */
+
+#define WDT ((wdt_type *) WDT_BASE)
+
+/** @defgroup WDT_exported_functions
+ * @{
+ */
+
+void wdt_enable(void);
+void wdt_counter_reload(void);
+void wdt_reload_value_set(uint16_t reload_value);
+void wdt_divider_set(wdt_division_type division);
+void wdt_register_write_enable( confirm_state new_state);
+flag_status wdt_flag_get(uint16_t wdt_flag);
+void wdt_window_counter_set(uint16_t window_cnt);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_wwdt.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_wwdt.h
new file mode 100644
index 0000000..01ab449
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_wwdt.h
@@ -0,0 +1,158 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_wwdt.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 wwdt header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_WWDT_H
+#define __AT32F435_437_WWDT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup WWDT
+ * @{
+ */
+
+/** @defgroup WWDT_enable_bit_definition
+ * @brief wwdt enable bit
+ * @{
+ */
+
+#define WWDT_EN_BIT ((uint32_t)0x00000080) /*!< wwdt enable bit */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDT_exported_types
+ * @{
+ */
+
+/**
+ * @brief wwdt division type
+ */
+typedef enum
+{
+ WWDT_PCLK1_DIV_4096 = 0x00, /*!< wwdt counter clock = (pclk1/4096)/1) */
+ WWDT_PCLK1_DIV_8192 = 0x01, /*!< wwdt counter clock = (pclk1/4096)/2) */
+ WWDT_PCLK1_DIV_16384 = 0x02, /*!< wwdt counter clock = (pclk1/4096)/4) */
+ WWDT_PCLK1_DIV_32768 = 0x03 /*!< wwdt counter clock = (pclk1/4096)/8) */
+} wwdt_division_type;
+
+/**
+ * @brief type define wwdt register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief wwdt ctrl register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t cnt : 7; /* [6:0] */
+ __IO uint32_t wwdten : 1; /* [7] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief wwdt cfg register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t cfg;
+ struct
+ {
+ __IO uint32_t win : 7; /* [6:0] */
+ __IO uint32_t div : 2; /* [8:7] */
+ __IO uint32_t rldien : 1; /* [9] */
+ __IO uint32_t reserved1 : 22;/* [31:10] */
+ } cfg_bit;
+ };
+
+ /**
+ * @brief wwdt cfg register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t rldf : 1; /* [0] */
+ __IO uint32_t reserved1 : 31;/* [31:1] */
+ } sts_bit;
+ };
+
+} wwdt_type;
+
+/**
+ * @}
+ */
+
+#define WWDT ((wwdt_type *) WWDT_BASE)
+
+/** @defgroup WWDT_exported_functions
+ * @{
+ */
+
+void wwdt_reset(void);
+void wwdt_divider_set(wwdt_division_type division);
+void wwdt_flag_clear(void);
+void wwdt_enable(uint8_t wwdt_cnt);
+void wwdt_interrupt_enable(void);
+flag_status wwdt_flag_get(void);
+void wwdt_counter_set(uint8_t wwdt_cnt);
+void wwdt_window_counter_set(uint8_t window_cnt);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_xmc.h b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_xmc.h
new file mode 100644
index 0000000..1c9bbca
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/at32f435_437_xmc.h
@@ -0,0 +1,1075 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_xmc.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 xmc header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_XMC_H
+#define __AT32F435_437_XMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup XMC
+ * @{
+ */
+
+/** @defgroup XMC_exported_types
+ * @{
+ */
+
+/**
+ * @brief xmc data address bus multiplexing type
+ */
+typedef enum
+{
+ XMC_DATA_ADDR_MUX_DISABLE = 0x00000000, /*!< xmc address/data multiplexing disable */
+ XMC_DATA_ADDR_MUX_ENABLE = 0x00000002 /*!< xmc address/data multiplexing enable */
+} xmc_data_addr_mux_type;
+
+/**
+ * @brief xmc burst access mode type
+ */
+typedef enum
+{
+ XMC_BURST_MODE_DISABLE = 0x00000000, /*!< xmc burst mode disable */
+ XMC_BURST_MODE_ENABLE = 0x00000100 /*!< xmc burst mode enable */
+} xmc_burst_access_mode_type;
+
+/**
+ * @brief xmc asynchronous wait type
+ */
+typedef enum
+{
+ XMC_ASYN_WAIT_DISABLE = 0x00000000, /*!< xmc wait signal during asynchronous transfers disbale */
+ XMC_ASYN_WAIT_ENABLE = 0x00008000 /*!< xmc wait signal during asynchronous transfers enable */
+} xmc_asyn_wait_type;
+
+/**
+ * @brief xmc wrapped mode type
+ */
+typedef enum
+{
+ XMC_WRAPPED_MODE_DISABLE = 0x00000000, /*!< xmc direct wrapped burst is disbale */
+ XMC_WRAPPED_MODE_ENABLE = 0x00000400 /*!< xmc direct wrapped burst is enable */
+} xmc_wrap_mode_type;
+
+/**
+ * @brief xmc write operation type
+ */
+typedef enum
+{
+ XMC_WRITE_OPERATION_DISABLE = 0x00000000, /*!< xmc write operations is disable */
+ XMC_WRITE_OPERATION_ENABLE = 0x00001000 /*!< xmc write operations is enable */
+} xmc_write_operation_type;
+
+/**
+ * @brief xmc wait signal type
+ */
+typedef enum
+{
+ XMC_WAIT_SIGNAL_DISABLE = 0x00000000, /*!< xmc nwait signal is disable */
+ XMC_WAIT_SIGNAL_ENABLE = 0x00002000 /*!< xmc nwait signal is enable */
+} xmc_wait_signal_type;
+
+/**
+ * @brief xmc write burst type
+ */
+typedef enum
+{
+ XMC_WRITE_BURST_SYN_DISABLE = 0x00000000, /*!< xmc write operations are always performed in asynchronous mode */
+ XMC_WRITE_BURST_SYN_ENABLE = 0x00080000 /*!< xmc write operations are performed in synchronous mode */
+} xmc_write_burst_type;
+
+/**
+ * @brief xmc extended mode type
+ */
+typedef enum
+{
+ XMC_WRITE_TIMING_DISABLE = 0x00000000, /*!< xmc write timing disable */
+ XMC_WRITE_TIMING_ENABLE = 0x00004000 /*!< xmc write timing enable */
+} xmc_extended_mode_type;
+
+/**
+ * @brief xmc pccard wait type
+ */
+typedef enum
+{
+ XMC_WAIT_OPERATION_DISABLE = 0x00000000, /*!< xmc wait operation for the pc card/nand flash memory bank disable */
+ XMC_WAIT_OPERATION_ENABLE = 0x00000002 /*!< xmc wait operation for the pc card/nand flash memory bank enable */
+} xmc_nand_pccard_wait_type;
+
+/**
+ * @brief xmc ecc enable type
+ */
+typedef enum
+{
+ XMC_ECC_OPERATION_DISABLE = 0x00000000, /*!< xmc ecc module disable */
+ XMC_ECC_OPERATION_ENABLE = 0x00000040 /*!< xmc ecc module enable */
+} xmc_ecc_enable_type;
+
+/**
+ * @brief xmc nor/sram subbank type
+ */
+typedef enum
+{
+ XMC_BANK1_NOR_SRAM1 = 0x00000000, /*!< xmc nor/sram subbank1 */
+ XMC_BANK1_NOR_SRAM2 = 0x00000001, /*!< xmc nor/sram subbank2 */
+ XMC_BANK1_NOR_SRAM3 = 0x00000002, /*!< xmc nor/sram subbank3 */
+ XMC_BANK1_NOR_SRAM4 = 0x00000003 /*!< xmc nor/sram subbank4 */
+} xmc_nor_sram_subbank_type;
+
+/**
+ * @brief xmc class bank type
+ */
+typedef enum
+{
+ XMC_BANK2_NAND = 0x00000000, /*!< xmc nand flash bank2 */
+ XMC_BANK3_NAND = 0x00000001, /*!< xmc nand flash bank3 */
+ XMC_BANK4_PCCARD = 0x00000002, /*!< xmc pc card bank4 */
+ XMC_BANK5_6_SDRAM = 0x00000003 /*!< xmc sdram bank5/6 */
+} xmc_class_bank_type;
+
+/**
+ * @brief xmc memory type
+ */
+typedef enum
+{
+ XMC_DEVICE_SRAM = 0x00000000, /*!< xmc device choice sram */
+ XMC_DEVICE_PSRAM = 0x00000004, /*!< xmc device choice psram */
+ XMC_DEVICE_NOR = 0x00000008 /*!< xmc device choice nor flash */
+} xmc_memory_type;
+
+/**
+ * @brief xmc data width type
+ */
+typedef enum
+{
+ XMC_BUSTYPE_8_BITS = 0x00000000, /*!< xmc databuss width 8bits */
+ XMC_BUSTYPE_16_BITS = 0x00000010 /*!< xmc databuss width 16bits */
+} xmc_data_width_type;
+
+/**
+ * @brief xmc wait signal polarity type
+ */
+typedef enum
+{
+ XMC_WAIT_SIGNAL_LEVEL_LOW = 0x00000000, /*!< xmc nwait active low */
+ XMC_WAIT_SIGNAL_LEVEL_HIGH = 0x00000200 /*!< xmc nwait active high */
+} xmc_wait_signal_polarity_type;
+
+/**
+ * @brief xmc wait timing type
+ */
+typedef enum
+{
+ XMC_WAIT_SIGNAL_SYN_BEFORE = 0x00000000, /*!< xmc nwait signal is active one data cycle before wait state */
+ XMC_WAIT_SIGNAL_SYN_DURING = 0x00000800 /*!< xmc nwait signal is active during wait state */
+} xmc_wait_timing_type;
+
+/**
+ * @brief xmc access mode type
+ */
+typedef enum
+{
+ XMC_ACCESS_MODE_A = 0x00000000, /*!< xmc access mode A */
+ XMC_ACCESS_MODE_B = 0x10000000, /*!< xmc access mode B */
+ XMC_ACCESS_MODE_C = 0x20000000, /*!< xmc access mode C */
+ XMC_ACCESS_MODE_D = 0x30000000 /*!< xmc access mode D */
+} xmc_access_mode_type;
+
+/**
+ * @brief xmc ecc page size type
+ */
+typedef enum
+{
+ XMC_ECC_PAGESIZE_256_BYTES = 0x00000000, /*!< xmc ecc page size 256 bytes */
+ XMC_ECC_PAGESIZE_512_BYTES = 0x00020000, /*!< xmc ecc page size 512 bytes */
+ XMC_ECC_PAGESIZE_1024_BYTES = 0x00040000, /*!< xmc ecc page size 1024 bytes */
+ XMC_ECC_PAGESIZE_2048_BYTES = 0x00060000, /*!< xmc ecc page size 2048 bytes */
+ XMC_ECC_PAGESIZE_4096_BYTES = 0x00080000, /*!< xmc ecc page size 4096 bytes */
+ XMC_ECC_PAGESIZE_8192_BYTES = 0x000A0000 /*!< xmc ecc page size 8192 bytes */
+} xmc_ecc_pagesize_type;
+
+/**
+ * @brief xmc interrupt sources type
+ */
+typedef enum
+{
+ XMC_INT_RISING_EDGE = 0x00000008, /*!< xmc rising edge detection interrupt enable */
+ XMC_INT_LEVEL = 0x00000010, /*!< xmc high-level edge detection interrupt enable */
+ XMC_INT_FALLING_EDGE = 0x00000020, /*!< xmc falling edge detection interrupt enable */
+ XMC_INT_ERR = 0x00004000 /*!< xmc sdram error interrupt enable */
+} xmc_interrupt_sources_type;
+
+/**
+ * @brief xmc interrupt flag type
+ */
+typedef enum
+{
+ XMC_RISINGEDGE_FLAG = 0x00000001, /*!< xmc interrupt rising edge detection flag */
+ XMC_LEVEL_FLAG = 0x00000002, /*!< xmc interrupt high-level edge detection flag */
+ XMC_FALLINGEDGE_FLAG = 0x00000004, /*!< xmc interrupt falling edge detection flag */
+ XMC_FEMPT_FLAG = 0x00000040, /*!< xmc fifo empty flag */
+ XMC_ERR_FLAG = 0x00000001, /*!< xmc sdram error flag */
+ XMC_BUSY_FLAG = 0x00000020 /*!< xmc sdram busy flag */
+} xmc_interrupt_flag_type;
+
+/**
+ * @brief xmc sdram number of column address type
+ */
+typedef enum
+{
+ XMC_COLUMN_8 = 0x00000000, /*!< xmc sdram column address 8bit */
+ XMC_COLUMN_9 = 0x00000001, /*!< xmc sdram column address 9bit */
+ XMC_COLUMN_10 = 0x00000002, /*!< xmc sdram column address 10bit */
+ XMC_COLUMN_11 = 0x00000003 /*!< xmc sdram column address 11bit */
+}xmc_sdram_column_type;
+
+/**
+ * @brief xmc sdram number of row address type
+ */
+typedef enum
+{
+ XMC_ROW_11 = 0x00000000, /*!< xmc sdram row address 11bit */
+ XMC_ROW_12 = 0x00000001, /*!< xmc sdram row address 12bit */
+ XMC_ROW_13 = 0x00000002 /*!< xmc sdram row address 13bit */
+}xmc_sdram_row_type;
+
+/**
+ * @brief xmc sdram memory data bus width type
+ */
+typedef enum
+{
+ XMC_MEM_WIDTH_8 = 0x00000000, /*!< xmc sdram data bus width 8 */
+ XMC_MEM_WIDTH_16 = 0x00000001 /*!< xmc sdram data bus width 16 */
+}xmc_sdram_width_type;
+
+/**
+ * @brief xmc sdram number of internal banks type
+ */
+typedef enum
+{
+ XMC_INBK_2 = 0x00000000, /*!< xmc sdram 2 internal banks */
+ XMC_INBK_4 = 0x00000001 /*!< xmc sdram 4 internal banks */
+}xmc_sdram_inbk_type;
+
+/**
+ * @brief xmc sdram cas latency type
+ */
+typedef enum
+{
+ XMC_CAS_1 = 0x00000001, /*!< xmc sdram cas 1 */
+ XMC_CAS_2 = 0x00000002, /*!< xmc sdram cas 2 */
+ XMC_CAS_3 = 0x00000003 /*!< xmc sdram cas 3 */
+}xmc_sdram_cas_type;
+
+/**
+ * @brief xmc sdram clock div type
+ */
+typedef enum
+{
+ XMC_NO_CLK = 0x00000000, /*!< xmc sdram disable clock */
+ XMC_CLKDIV_2 = 0x00000002, /*!< xmc sdram clock div 2 */
+ XMC_CLKDIV_3 = 0x00000003, /*!< xmc sdram clock div 3 */
+ XMC_CLKDIV_4 = 0x00000001 /*!< xmc sdram clock div 4 */
+}xmc_sdram_clkdiv_type;
+
+/**
+ * @brief xmc sdram read delay
+ */
+typedef enum
+{
+ XMC_READ_DELAY_0 = 0x00000000, /*!< xmc sdram no delay */
+ XMC_READ_DELAY_1 = 0x00000001, /*!< xmc sdram delay 1 clock*/
+ XMC_READ_DELAY_2 = 0x00000002, /*!< xmc sdram delay 2 clock */
+}xmc_sdram_rd_delay_type;
+
+/**
+ * @brief xmc sdram bank type
+ */
+typedef enum
+{
+ XMC_SDRAM_BANK1 = 0x00000000, /*!< xmc sdram bank 1 */
+ XMC_SDRAM_BANK2 = 0x00000001 /*!< xmc sdram bank 2 */
+}xmc_sdram_bank_type;
+
+
+/**
+ * @brief xmc sdram timing delay cycle type
+ */
+typedef enum
+{
+ XMC_DELAY_CYCLE_1 = 0x00000000, /*!< xmc sdram timming delay 1 cycle */
+ XMC_DELAY_CYCLE_2 = 0x00000001, /*!< xmc sdram timming delay 2 cycle */
+ XMC_DELAY_CYCLE_3 = 0x00000002, /*!< xmc sdram timming delay 3 cycle */
+ XMC_DELAY_CYCLE_4 = 0x00000003, /*!< xmc sdram timming delay 4 cycle */
+ XMC_DELAY_CYCLE_5 = 0x00000004, /*!< xmc sdram timming delay 5 cycle */
+ XMC_DELAY_CYCLE_6 = 0x00000005, /*!< xmc sdram timming delay 6 cycle */
+ XMC_DELAY_CYCLE_7 = 0x00000006, /*!< xmc sdram timming delay 7 cycle */
+ XMC_DELAY_CYCLE_8 = 0x00000007, /*!< xmc sdram timming delay 8 cycle */
+ XMC_DELAY_CYCLE_9 = 0x00000008, /*!< xmc sdram timming delay 9 cycle */
+ XMC_DELAY_CYCLE_10 = 0x00000009, /*!< xmc sdram timming delay 10 cycle */
+ XMC_DELAY_CYCLE_11 = 0x0000000A, /*!< xmc sdram timming delay 11 cycle */
+ XMC_DELAY_CYCLE_12 = 0x0000000B, /*!< xmc sdram timming delay 12 cycle */
+ XMC_DELAY_CYCLE_13 = 0x0000000C, /*!< xmc sdram timming delay 13 cycle */
+ XMC_DELAY_CYCLE_14 = 0x0000000D, /*!< xmc sdram timming delay 14 cycle */
+ XMC_DELAY_CYCLE_15 = 0x0000000E, /*!< xmc sdram timming delay 15 cycle */
+ XMC_DELAY_CYCLE_16 = 0x0000000F /*!< xmc sdram timming delay 16 cycle */
+}xmc_sdram_delay_type;
+
+
+/**
+ * @brief xmc sdram command type
+ */
+typedef enum
+{
+ XMC_CMD_NORMAL = 0x00000000, /*!< xmc sdram command normal */
+ XMC_CMD_CLK = 0x00000001, /*!< xmc sdram command clock enable */
+ XMC_CMD_PRECHARG_ALL = 0x00000002, /*!< xmc sdram command precharg all bank */
+ XMC_CMD_AUTO_REFRESH = 0x00000003, /*!< xmc sdram command auto refresh */
+ XMC_CMD_LOAD_MODE = 0x00000004, /*!< xmc sdram command load mode register */
+ XMC_CMD_SELF_REFRESH = 0x00000005, /*!< xmc sdram command self refresh */
+ XMC_CMD_POWER_DOWN = 0x00000006 /*!< xmc sdram command power down */
+}xmc_command_type;
+
+/**
+ * @brief xmc sdram command bank select type
+ */
+typedef enum
+{
+ XMC_CMD_BANK1 = 0x00000010, /*!< send xmc sdram command to bank1 */
+ XMC_CMD_BANK2 = 0x00000008, /*!< send xmc sdram command to bank2 */
+ XMC_CMD_BANK1_2 = 0x00000018 /*!< send xmc sdram command to bank1 and bank2 */
+}xmc_cmd_bank1_2_type;
+
+
+/**
+ * @brief xmc sdram bank status type
+ */
+typedef enum
+{
+ XMC_STATUS_NORMAL = 0x00000000, /*!< xmc sdram status normal */
+ XMC_STATUS_SELF_REFRESH = 0x00000001, /*!< xmc sdram status self refresh */
+ XMC_STATUS_POWER_DOWN = 0x00000002, /*!< xmc sdram power down */
+ XMC_STATUS_MASK = 0x00000003 /*!< xmc sdram mask */
+}xmc_bank_status_type;
+
+
+/**
+ * @brief nor/sram banks timing parameters
+ */
+typedef struct
+{
+ xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
+ xmc_extended_mode_type write_timing_enable; /*!< xmc nor/sram write timing enable */
+ uint32_t addr_setup_time; /*!< xmc nor/sram address setup time */
+ uint32_t addr_hold_time; /*!< xmc nor/sram address hold time */
+ uint32_t data_setup_time; /*!< xmc nor/sram data setup time */
+ uint32_t bus_latency_time; /*!< xmc nor/sram bus latency time */
+ uint32_t clk_psc; /*!< xmc nor/sram clock prescale */
+ uint32_t data_latency_time; /*!< xmc nor/sram data latency time */
+ xmc_access_mode_type mode; /*!< xmc nor/sram access mode */
+} xmc_norsram_timing_init_type;
+
+/**
+ * @brief xmc nor/sram init structure definition
+ */
+typedef struct
+{
+ xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
+ xmc_data_addr_mux_type data_addr_multiplex; /*!< xmc nor/sram address/data multiplexing enable */
+ xmc_memory_type device; /*!< xmc nor/sram memory device */
+ xmc_data_width_type bus_type; /*!< xmc nor/sram data bus width */
+ xmc_burst_access_mode_type burst_mode_enable; /*!< xmc nor/sram burst mode enable */
+ xmc_asyn_wait_type asynwait_enable; /*!< xmc nor/sram nwait in asynchronous transfer enable */
+ xmc_wait_signal_polarity_type wait_signal_lv; /*!< xmc nor/sram nwait polarity */
+ xmc_wrap_mode_type wrapped_mode_enable; /*!< xmc nor/sram wrapped enable */
+ xmc_wait_timing_type wait_signal_config; /*!< xmc nor/sram nwait timing configuration */
+ xmc_write_operation_type write_enable; /*!< xmc nor/sram write enable */
+ xmc_wait_signal_type wait_signal_enable; /*!< xmc nor/sram nwait in synchronous transfer enable */
+ xmc_extended_mode_type write_timing_enable; /*!< xmc nor/sram read-write timing different */
+ xmc_write_burst_type write_burst_syn; /*!< xmc nor/sram memory write mode control */
+} xmc_norsram_init_type;
+
+/**
+ * @brief nand and pccard timing parameters xmc
+ */
+
+typedef struct
+{
+ xmc_class_bank_type class_bank; /*!< xmc nand/pccard bank */
+ uint32_t mem_setup_time; /*!< xmc nand/pccard memory setup time */
+ uint32_t mem_waite_time; /*!< xmc nand/pccard memory wait time */
+ uint32_t mem_hold_time; /*!< xmc nand/pccard memory hold time */
+ uint32_t mem_hiz_time; /*!< xmc nand/pccard memory databus high resistance time */
+} xmc_nand_pccard_timinginit_type;
+
+/**
+ * @brief xmc nand init structure definition
+ */
+
+typedef struct
+{
+ xmc_class_bank_type nand_bank; /*!< xmc nand bank */
+ xmc_nand_pccard_wait_type wait_enable; /*!< xmc wait feature enable */
+ xmc_data_width_type bus_type; /*!< xmc nand bus width */
+ xmc_ecc_enable_type ecc_enable; /*!< xmc nand ecc enable */
+ xmc_ecc_pagesize_type ecc_pagesize; /*!< xmc nand ecc page size */
+ uint32_t delay_time_cycle; /*!< xmc nand cle to re delay */
+ uint32_t delay_time_ar; /*!< xmc nand ale to re delay */
+} xmc_nand_init_type;
+
+/**
+ * @brief xmc pccard init structure definition
+ */
+
+typedef struct
+{
+ xmc_nand_pccard_wait_type enable_wait; /*!< xmc pccard wait feature enable */
+ uint32_t delay_time_cr; /*!< xmc pccard cle to re delay */
+ uint32_t delay_time_ar; /*!< xmc pccard ale to re delay */
+} xmc_pccard_init_type;
+
+/**
+ * @brief xmc sdram init structure definition
+ */
+
+typedef struct
+{
+ xmc_sdram_bank_type sdram_bank; /*!< xmc sdram bank bype */
+ xmc_sdram_inbk_type internel_banks; /*!< xmc sdram internal banks */
+ xmc_sdram_clkdiv_type clkdiv; /*!< xmc sdram clock div */
+ uint8_t write_protection; /*!< xmc sdram write protection */
+ uint8_t burst_read; /*!< xmc sdram burst read */
+ uint8_t read_delay; /*!< xmc sdram read delay */
+ xmc_sdram_column_type column_address; /*!< xmc sdram column address */
+ xmc_sdram_row_type row_address; /*!< xmc sdram row address */
+ xmc_sdram_cas_type cas; /*!< xmc sdram cas */
+ xmc_sdram_width_type width; /*!< xmc sdram data width */
+} xmc_sdram_init_type;
+
+/**
+ * @brief xmc sdram timing structure definition
+ */
+
+typedef struct
+{
+ xmc_sdram_delay_type tmrd; /*!< mode register program to active delay */
+ xmc_sdram_delay_type txsr; /*!< exit self-refresh to active delay */
+ xmc_sdram_delay_type tras; /*!< self refresh */
+ xmc_sdram_delay_type trc; /*!< refresh to active delay */
+ xmc_sdram_delay_type twr; /*!< write recovery delay */
+ xmc_sdram_delay_type trp; /*!< precharge to active delay */
+ xmc_sdram_delay_type trcd; /*!< row active to read/write delay */
+} xmc_sdram_timing_type;
+
+/**
+ * @brief xmc sdram command structure definition
+ */
+
+typedef struct
+{
+ xmc_command_type cmd; /*!< sdram command */
+ xmc_cmd_bank1_2_type cmd_banks; /*!< which bank send command */
+ uint32_t auto_refresh; /*!< auto refresh times */
+ uint32_t data; /*!< mode register data */
+} xmc_sdram_cmd_type;
+
+typedef struct
+{
+ /**
+ * @brief xmc bank1 bk1ctrl register, offset:0x00+0x08*(x-1) x= 1...4
+ */
+ union
+ {
+ __IO uint32_t bk1ctrl;
+ struct
+ {
+ __IO uint32_t en : 1; /* [0] */
+ __IO uint32_t admuxen : 1; /* [1] */
+ __IO uint32_t dev : 2; /* [3:2] */
+ __IO uint32_t extmdbw : 2; /* [5:4] */
+ __IO uint32_t noren : 1; /* [6] */
+ __IO uint32_t reserved1 : 1; /* [7] */
+ __IO uint32_t syncben : 1; /* [8] */
+ __IO uint32_t nwpol : 1; /* [9] */
+ __IO uint32_t wrapen : 1; /* [10] */
+ __IO uint32_t nwtcfg : 1; /* [11] */
+ __IO uint32_t wen : 1; /* [12] */
+ __IO uint32_t nwsen : 1; /* [13] */
+ __IO uint32_t rwtd : 1; /* [14] */
+ __IO uint32_t nwasen : 1; /* [15] */
+ __IO uint32_t crpgs : 3; /* [18:16] */
+ __IO uint32_t mwmc : 1; /* [19] */
+ __IO uint32_t reserved2 : 12;/* [31:20] */
+ } bk1ctrl_bit;
+ };
+
+ /**
+ * @brief xmc bank1 bk1tmg register, offset:0x04+0x08*(x-1) x= 1...4
+ */
+ union
+ {
+ __IO uint32_t bk1tmg;
+ struct
+ {
+ __IO uint32_t addrst : 4; /* [3:0] */
+ __IO uint32_t addrht : 4; /* [7:4] */
+ __IO uint32_t dtst : 8; /* [15:8] */
+ __IO uint32_t buslat : 4; /* [19:16] */
+ __IO uint32_t clkpsc : 4; /* [23:20] */
+ __IO uint32_t dtlat : 4; /* [27:24] */
+ __IO uint32_t asyncm : 2; /* [29:28] */
+ __IO uint32_t reserved1 : 2; /* [31:30] */
+ } bk1tmg_bit;
+ };
+
+} xmc_bank1_ctrl_tmg_reg_type;
+
+typedef struct
+{
+ /**
+ * @brief xmc bank1 bk1tmgwr register, offset:0x104+0x08*(x-1) x= 1...4
+ */
+ union
+ {
+ __IO uint32_t bk1tmgwr;
+ struct
+ {
+ __IO uint32_t addrst : 4; /* [3:0] */
+ __IO uint32_t addrht : 4; /* [7:4] */
+ __IO uint32_t dtst : 8; /* [15:8] */
+ __IO uint32_t buslat : 4; /* [19:16] */
+ __IO uint32_t reserved1 : 8; /* [27:20] */
+ __IO uint32_t asyncm : 2; /* [29:28] */
+ __IO uint32_t reserved2 : 2; /* [31:30] */
+ } bk1tmgwr_bit;
+ };
+
+ /**
+ * @brief xmc bank1 reserved register
+ */
+ __IO uint32_t reserved1;
+
+} xmc_bank1_tmgwr_reg_type;
+
+/**
+ * @brief xmc bank1 registers
+ */
+typedef struct
+{
+ /**
+ * @brief xmc bank1 ctrl and tmg register, offset:0x00~0x1C
+ */
+ xmc_bank1_ctrl_tmg_reg_type ctrl_tmg_group[4];
+
+ /**
+ * @brief xmc bank1 reserved register, offset:0x20~0x100
+ */
+ __IO uint32_t reserved1[57];
+
+ /**
+ * @brief xmc bank1 tmgwr register, offset:0x104~0x11C
+ */
+ xmc_bank1_tmgwr_reg_type tmgwr_group[4];
+
+ /**
+ * @brief xmc bank1 reserved register, offset:0x120~0x21C
+ */
+ __IO uint32_t reserved2[64];
+
+ /**
+ * @brief xmc bank1 ext register, offset:0x220~0x22C
+ */
+ union
+ {
+ __IO uint32_t ext[4];
+ struct
+ {
+ __IO uint32_t buslatw2w : 8; /* [7:0] */
+ __IO uint32_t buslatr2r : 8; /* [15:8] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } ext_bit[4];
+ };
+
+} xmc_bank1_type;
+
+/**
+ * @brief xmc bank2 registers
+ */
+typedef struct
+{
+ /**
+ * @brief xmc bk2ctrl register, offset:0x60
+ */
+ union
+ {
+ __IO uint32_t bk2ctrl;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t nwen : 1; /* [1] */
+ __IO uint32_t en : 1; /* [2] */
+ __IO uint32_t dev : 1; /* [3] */
+ __IO uint32_t extmdbw : 2; /* [5:4] */
+ __IO uint32_t eccen : 1; /* [6] */
+ __IO uint32_t reserved2 : 2; /* [8:7] */
+ __IO uint32_t tcr : 4; /* [12:9] */
+ __IO uint32_t tar : 4; /* [16:13] */
+ __IO uint32_t eccpgs : 3; /* [19:17] */
+ __IO uint32_t reserved3 : 12;/* [31:20] */
+ } bk2ctrl_bit;
+ };
+
+ /**
+ * @brief xmc bk2is register, offset:0x64
+ */
+ union
+ {
+ __IO uint32_t bk2is;
+ struct
+ {
+ __IO uint32_t res : 1; /* [0] */
+ __IO uint32_t hls : 1; /* [1] */
+ __IO uint32_t fes : 1; /* [2] */
+ __IO uint32_t reien : 1; /* [3] */
+ __IO uint32_t hlien : 1; /* [4] */
+ __IO uint32_t feien : 1; /* [5] */
+ __IO uint32_t fifoe : 1; /* [6] */
+ __IO uint32_t reserved1 : 25;/* [31:7] */
+ } bk2is_bit;
+ };
+
+ /**
+ * @brief xmc bk2tmgmem register, offset:0x68
+ */
+ union
+ {
+ __IO uint32_t bk2tmgmem;
+ struct
+ {
+ __IO uint32_t cmst : 8; /* [7:0] */
+ __IO uint32_t cmwt : 8; /* [15:8] */
+ __IO uint32_t cmht : 8; /* [23:16] */
+ __IO uint32_t cmdhizt : 8; /* [31:24] */
+ } bk2tmgmem_bit;
+ };
+
+ /**
+ * @brief xmc bk2tmgatt register, offset:0x6C
+ */
+ union
+ {
+ __IO uint32_t bk2tmgatt;
+ struct
+ {
+ __IO uint32_t amst : 8; /* [7:0] */
+ __IO uint32_t amwt : 8; /* [15:8] */
+ __IO uint32_t amht : 8; /* [23:16] */
+ __IO uint32_t amdhizt : 8; /* [31:24] */
+ } bk2tmgatt_bit;
+ };
+
+ /**
+ * @brief xmc reserved register, offset:0x70
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief xmc bk2ecc register, offset:0x74
+ */
+ union
+ {
+ __IO uint32_t bk2ecc;
+ struct
+ {
+ __IO uint32_t ecc : 32; /* [31:0] */
+ } bk2ecc_bit;
+ };
+
+} xmc_bank2_type;
+
+/**
+ * @brief xmc bank3 registers
+ */
+typedef struct
+{
+ /**
+ * @brief xmc bk3ctrl register, offset:0x80
+ */
+ union
+ {
+ __IO uint32_t bk3ctrl;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t nwen : 1; /* [1] */
+ __IO uint32_t en : 1; /* [2] */
+ __IO uint32_t dev : 1; /* [3] */
+ __IO uint32_t extmdbw : 2; /* [5:4] */
+ __IO uint32_t eccen : 1; /* [6] */
+ __IO uint32_t reserved2 : 2; /* [8:7] */
+ __IO uint32_t tcr : 4; /* [12:9] */
+ __IO uint32_t tar : 4; /* [16:13] */
+ __IO uint32_t eccpgs : 3; /* [19:17] */
+ __IO uint32_t reserved3 : 12;/* [31:20] */
+ } bk3ctrl_bit;
+ };
+
+ /**
+ * @brief xmc bk3is register, offset:0x84
+ */
+ union
+ {
+ __IO uint32_t bk3is;
+ struct
+ {
+ __IO uint32_t res : 1; /* [0] */
+ __IO uint32_t hls : 1; /* [1] */
+ __IO uint32_t fes : 1; /* [2] */
+ __IO uint32_t reien : 1; /* [3] */
+ __IO uint32_t hlien : 1; /* [4] */
+ __IO uint32_t feien : 1; /* [5] */
+ __IO uint32_t fifoe : 1; /* [6] */
+ __IO uint32_t reserved1 : 25;/* [31:7] */
+ } bk3is_bit;
+ };
+
+ /**
+ * @brief xmc bk3tmgmem register, offset:0x88
+ */
+ union
+ {
+ __IO uint32_t bk3tmgmem;
+ struct
+ {
+ __IO uint32_t cmst : 8; /* [7:0] */
+ __IO uint32_t cmwt : 8; /* [15:8] */
+ __IO uint32_t cmht : 8; /* [23:16] */
+ __IO uint32_t cmdhizt : 8; /* [31:24] */
+ } bk3tmgmem_bit;
+ };
+
+ /**
+ * @brief xmc bk3tmgatt register, offset:0x8C
+ */
+ union
+ {
+ __IO uint32_t bk3tmgatt;
+ struct
+ {
+ __IO uint32_t amst : 8; /* [7:0] */
+ __IO uint32_t amwt : 8; /* [15:8] */
+ __IO uint32_t amht : 8; /* [23:16] */
+ __IO uint32_t amdhizt : 8; /* [31:24] */
+ } bk3tmgatt_bit;
+ };
+
+ /**
+ * @brief xmc reserved register, offset:0x90
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief xmc bk3ecc register, offset:0x94
+ */
+ union
+ {
+ __IO uint32_t bk3ecc;
+ struct
+ {
+ __IO uint32_t ecc : 32; /* [31:0] */
+ } bk3ecc_bit;
+ };
+} xmc_bank3_type;
+
+/**
+ * @brief xmc bank4 registers
+ */
+typedef struct
+{
+
+ /**
+ * @brief xmc bk4ctrl register, offset:0xA0
+ */
+ union
+ {
+ __IO uint32_t bk4ctrl;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t nwen : 1; /* [1] */
+ __IO uint32_t en : 1; /* [2] */
+ __IO uint32_t dev : 1; /* [3] */
+ __IO uint32_t extmdbw : 2; /* [5:4] */
+ __IO uint32_t eccen : 1; /* [6] */
+ __IO uint32_t reserved2 : 2; /* [8:7] */
+ __IO uint32_t tcr : 4; /* [12:9] */
+ __IO uint32_t tar : 4; /* [16:13] */
+ __IO uint32_t eccpgs : 3; /* [19:17] */
+ __IO uint32_t reserved3 : 12;/* [31:20] */
+ } bk4ctrl_bit;
+ };
+
+ /**
+ * @brief xmc bk4is register, offset:0xA4
+ */
+ union
+ {
+ __IO uint32_t bk4is;
+ struct
+ {
+ __IO uint32_t res : 1; /* [0] */
+ __IO uint32_t hls : 1; /* [1] */
+ __IO uint32_t fes : 1; /* [2] */
+ __IO uint32_t reien : 1; /* [3] */
+ __IO uint32_t hlien : 1; /* [4] */
+ __IO uint32_t feien : 1; /* [5] */
+ __IO uint32_t fifoe : 1; /* [6] */
+ __IO uint32_t reserved1 : 25;/* [31:7] */
+ } bk4is_bit;
+ };
+
+ /**
+ * @brief xmc bk4tmgmem register, offset:0xA8
+ */
+ union
+ {
+ __IO uint32_t bk4tmgmem;
+ struct
+ {
+ __IO uint32_t cmst : 8; /* [7:0] */
+ __IO uint32_t cmwt : 8; /* [15:8] */
+ __IO uint32_t cmht : 8; /* [23:16] */
+ __IO uint32_t cmdhizt : 8; /* [31:24] */
+ } bk4tmgmem_bit;
+ };
+
+ /**
+ * @brief xmc bk4tmgatt register, offset:0xAC
+ */
+ union
+ {
+ __IO uint32_t bk4tmgatt;
+ struct
+ {
+ __IO uint32_t amst : 8; /* [7:0] */
+ __IO uint32_t amwt : 8; /* [15:8] */
+ __IO uint32_t amht : 8; /* [23:16] */
+ __IO uint32_t amdhizt : 8; /* [31:24] */
+ } bk4tmgatt_bit;
+ };
+
+ /**
+ * @brief xmc bk4tmgio register, offset:0xB0
+ */
+ union
+ {
+ __IO uint32_t bk4tmgio;
+ struct
+ {
+ __IO uint32_t iost : 8; /* [7:0] */
+ __IO uint32_t iowt : 8; /* [15:8] */
+ __IO uint32_t ioht : 8; /* [23:16] */
+ __IO uint32_t iohizt : 8; /* [31:24] */
+ } bk4tmgio_bit;
+ };
+} xmc_bank4_type;
+
+/**
+ * @brief xmc sdram type
+ */
+typedef struct
+{
+ /**
+ * @brief xmc sdram ctrl register, offset:0x140~0x144
+ */
+ union
+ {
+ __IO uint32_t ctrl[2];
+ struct
+ {
+ __IO uint32_t ca : 2; /* [1:0] */
+ __IO uint32_t ra : 2; /* [3:2] */
+ __IO uint32_t db : 2; /* [5:4] */
+ __IO uint32_t inbk : 1; /* [6] */
+ __IO uint32_t cas : 2; /* [8:7] */
+ __IO uint32_t wrp : 1; /* [9] */
+ __IO uint32_t clkdiv : 2; /* [11:10] */
+ __IO uint32_t bstr : 1; /* [12] */
+ __IO uint32_t rd : 2; /* [14:13] */
+ __IO uint32_t reserved1 : 17;/* [31:15] */
+ } ctrl_bit[2];
+ };
+
+ /**
+ * @brief xmc sdram tm register, offset:0x148~0x14C
+ */
+ union
+ {
+ __IO uint32_t tm[2];
+ struct
+ {
+ __IO uint32_t tmrd : 4; /* [3:0] */
+ __IO uint32_t txsr : 4; /* [7:4] */
+ __IO uint32_t tras : 4; /* [11:8] */
+ __IO uint32_t trc : 4; /* [15:12] */
+ __IO uint32_t twr : 4; /* [19:16] */
+ __IO uint32_t trp : 4; /* [23:20] */
+ __IO uint32_t trcd : 4; /* [27:24] */
+ __IO uint32_t reserved1 : 4; /* [31:28] */
+ } tm_bit[2];
+
+ };
+
+/**
+ * @brief xmc sdram cmd register, offset:0x150
+ */
+ union
+ {
+ __IO uint32_t cmd;
+ struct
+ {
+ __IO uint32_t cmd : 3; /* [2:0] */
+ __IO uint32_t bk2 : 1; /* [3] */
+ __IO uint32_t bk1 : 1; /* [4] */
+ __IO uint32_t art : 4; /* [8:5] */
+ __IO uint32_t mrd : 13;/* [21:9] */
+ __IO uint32_t reserved1 : 10;/* [31:22] */
+ } cmd_bit;
+ };
+
+ /**
+ * @brief xmc sdram rcnt register, offset:0x154
+ */
+ union
+ {
+ __IO uint32_t rcnt;
+ struct
+ {
+ __IO uint32_t errc : 1; /* [0] */
+ __IO uint32_t rc : 13;/* [13:1] */
+ __IO uint32_t erien : 1; /* [14] */
+ __IO uint32_t reserved1 : 17;/* [31:15] */
+ } rcnt_bit;
+ };
+
+ /**
+ * @brief xmc sdram sts register, offset:0x158
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t err : 1; /* [0] */
+ __IO uint32_t bk1sts : 2; /* [2:1] */
+ __IO uint32_t bk2sts : 2; /* [4:3] */
+ __IO uint32_t busy : 1; /* [5] */
+ __IO uint32_t reserved1 : 26;/* [31:6] */
+ } sts_bit;
+ };
+}xmc_sdram_type;
+
+/**
+ * @}
+ */
+
+#define XMC_BANK1 ((xmc_bank1_type *) XMC_BANK1_REG_BASE)
+#define XMC_BANK2 ((xmc_bank2_type *) XMC_BANK2_REG_BASE)
+#define XMC_BANK3 ((xmc_bank3_type *) XMC_BANK3_REG_BASE)
+#define XMC_BANK4 ((xmc_bank4_type *) XMC_BANK4_REG_BASE)
+#define XMC_SDRAM ((xmc_sdram_type *) XMC_SDRAM_REG_BASE)
+
+/** @defgroup XMC_exported_functions
+ * @{
+ */
+
+void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank);
+void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct);
+void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
+ xmc_norsram_timing_init_type* xmc_w_timing_struct);
+void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct);
+void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
+ xmc_norsram_timing_init_type* xmc_w_timing_struct);
+void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state);
+void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing);
+void xmc_nand_reset(xmc_class_bank_type xmc_bank);
+void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct);
+void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct);
+void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct);
+void xmc_nand_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct);
+void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
+void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
+uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank);
+void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state);
+flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
+void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
+void xmc_pccard_reset(void);
+void xmc_pccard_init(xmc_pccard_init_type* xmc_pccard_init_struct);
+void xmc_pccard_timing_config(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct);
+void xmc_pccard_default_para_init(xmc_pccard_init_type* xmc_pccard_init_struct);
+void xmc_pccard_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct);
+void xmc_pccard_enable(confirm_state new_state);
+void xmc_sdram_reset(xmc_sdram_bank_type xmc_bank);
+void xmc_sdram_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct);
+void xmc_sdram_default_para_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct);
+void xmc_sdram_cmd(xmc_sdram_cmd_type *xmc_sdram_cmd_struct);
+uint32_t xmc_sdram_status_get(xmc_sdram_bank_type xmc_bank);
+void xmc_sdram_refresh_counter_set(uint32_t counter);
+void xmc_sdram_auto_refresh_set(uint32_t number);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/Include/system_at32f435_437.h b/.platformio/packages/framework-cmsis-at32f43/Include/system_at32f435_437.h
new file mode 100644
index 0000000..eedeb0b
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Include/system_at32f435_437.h
@@ -0,0 +1,75 @@
+/**
+ **************************************************************************
+ * @file system_at32f435_437.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief cmsis cortex-m4 system header file.
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#ifndef __SYSTEM_AT32F435_437_H
+#define __SYSTEM_AT32F435_437_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup AT32F435_437_system
+ * @{
+ */
+
+/** @defgroup AT32F435_437_system_exported_variables
+ * @{
+ */
+extern unsigned int system_core_clock; /*!< system clock frequency (core clock) */
+
+/**
+ * @}
+ */
+
+/** @defgroup AT32F435_437_system_exported_functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void system_core_clock_update(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/License.md b/.platformio/packages/framework-cmsis-at32f43/License.md
new file mode 100644
index 0000000..1d233f6
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/License.md
@@ -0,0 +1,84 @@
+Apache License
+ Version 2.0, January 2004
+ http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+1. Definitions.
+
+"License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document.
+
+"Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License.
+
+"Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. For the purposes of this definition, "control" means (i) the power, direct or indirect, to cause the direction or management of such entity, whether by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity.
+
+"You" (or "Your") shall mean an individual or Legal Entity exercising permissions granted by this License.
+
+"Source" form shall mean the preferred form for making modifications, including but not limited to software source code, documentation source, and configuration files.
+
+"Object" form shall mean any form resulting from mechanical transformation or translation of a Source form, including but not limited to compiled object code, generated documentation, and conversions to other media types.
+
+"Work" shall mean the work of authorship, whether in Source or Object form, made available under the License, as indicated by a copyright notice that is included in or attached to the work (an example is provided in the Appendix below).
+
+"Derivative Works" shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, annotations, elaborations, or other modifications represent, as a whole, an original work of authorship. For the purposes of this License, Derivative Works shall not include works that remain separable from, or merely link (or bind by name) to the interfaces of, the Work and Derivative Works thereof.
+
+"Contribution" shall mean any work of authorship, including the original version of the Work and any modifications or additions to that Work or Derivative Works thereof, that is intentionally submitted to Licensor for inclusion in the Work by the copyright owner or by an individual or Legal Entity authorized to submit on behalf of the copyright owner. For the purposes of this definition, "submitted" means any form of electronic, verbal, or written communication sent to the Licensor or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue tracking systems that are managed by, or on behalf of, the Licensor for the purpose of discussing and improving the Work, but excluding communication that is conspicuously marked or otherwise designated in writing by the copyright owner as "Not a Contribution."
+
+"Contributor" shall mean Licensor and any individual or Legal Entity on behalf of whom a Contribution has been received by Licensor and subsequently incorporated within the Work.
+
+2. Grant of Copyright License.
+
+Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare Derivative Works of, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form.
+
+3. Grant of Patent License.
+
+Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable (except as stated in this section) patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the Work, where such license applies only to those patent claims licensable by such Contributor that are necessarily infringed by their Contribution(s) alone or by combination of their Contribution(s) with the Work to which such Contribution(s) was submitted. If You institute patent litigation against any entity (including a cross-claim or counterclaim in a lawsuit) alleging that the Work or a Contribution incorporated within the Work constitutes direct or contributory patent infringement, then any patent licenses granted to You under this License for that Work shall terminate as of the date such litigation is filed.
+
+4. Redistribution.
+
+You may reproduce and distribute copies of the Work or Derivative Works thereof in any medium, with or without modifications, and in Source or Object form, provided that You meet the following conditions:
+1.You must give any other recipients of the Work or Derivative Works a copy of this License; and
+2.You must cause any modified files to carry prominent notices stating that You changed the files; and
+3.You must retain, in the Source form of any Derivative Works that You distribute, all copyright, patent, trademark, and attribution notices from the Source form of the Work, excluding those notices that do not pertain to any part of the Derivative Works; and
+4.If the Work includes a "NOTICE" text file as part of its distribution, then any Derivative Works that You distribute must include a readable copy of the attribution notices contained within such NOTICE file, excluding those notices that do not pertain to any part of the Derivative Works, in at least one of the following places: within a NOTICE text file distributed as part of the Derivative Works; within the Source form or documentation, if provided along with the Derivative Works; or, within a display generated by the Derivative Works, if and wherever such third-party notices normally appear. The contents of the NOTICE file are for informational purposes only and do not modify the License. You may add Your own attribution notices within Derivative Works that You distribute, alongside or as an addendum to the NOTICE text from the Work, provided that such additional attribution notices cannot be construed as modifying the License.
+
+You may add Your own copyright statement to Your modifications and may provide additional or different license terms and conditions for use, reproduction, or distribution of Your modifications, or for any such Derivative Works as a whole, provided Your use, reproduction, and distribution of the Work otherwise complies with the conditions stated in this License.
+
+5. Submission of Contributions.
+
+Unless You explicitly state otherwise, any Contribution intentionally submitted for inclusion in the Work by You to the Licensor shall be under the terms and conditions of this License, without any additional terms or conditions. Notwithstanding the above, nothing herein shall supersede or modify the terms of any separate license agreement you may have executed with Licensor regarding such Contributions.
+
+6. Trademarks.
+
+This License does not grant permission to use the trade names, trademarks, service marks, or product names of the Licensor, except as required for reasonable and customary use in describing the origin of the Work and reproducing the content of the NOTICE file.
+
+7. Disclaimer of Warranty.
+
+Unless required by applicable law or agreed to in writing, Licensor provides the Work (and each Contributor provides its Contributions) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are solely responsible for determining the appropriateness of using or redistributing the Work and assume any risks associated with Your exercise of permissions under this License.
+
+8. Limitation of Liability.
+
+In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been advised of the possibility of such damages.
+
+9. Accepting Warranty or Additional Liability.
+
+While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability.
+
+END OF TERMS AND CONDITIONS
+
+APPENDIX:
+
+ Copyright [2021] [Artery]
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/README.md b/.platformio/packages/framework-cmsis-at32f43/README.md
new file mode 100644
index 0000000..fe89b5a
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/README.md
@@ -0,0 +1,19 @@
+# AT32F43x CMSIS Device MCU Component
+
+## Overview
+
+ * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this AT32 product
+ * The BSP Drivers of each evaluation or demonstration board provided by this AT32 series
+ * A consistent set of middlewares components such as RTOS, USB, FatFS ...
+ * A full set of software projects (basic examples, applications or demonstrations) provided by this AT32 series
+
+## Description
+
+
+
+## Compatibility information
+
+
+
+## Troubleshooting
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/Startup/gcc/startup_at32f435_437.s b/.platformio/packages/framework-cmsis-at32f43/Startup/gcc/startup_at32f435_437.s
new file mode 100644
index 0000000..d8f7024
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/Startup/gcc/startup_at32f435_437.s
@@ -0,0 +1,571 @@
+/**
+ ******************************************************************************
+ * @file startup_at32f435_437.s
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 devices vector table for gcc toolchain.
+ * this module performs:
+ * - set the initial sp
+ * - set the initial pc == reset_handler,
+ * - set the vector table entries with the exceptions isr address
+ * - configure the clock system and the external sram to
+ * be used as data memory (optional, to be enabled by user)
+ * - branches to main in the c library (which eventually
+ * calls main()).
+ * after reset the cortex-m4 processor is in thread mode,
+ * priority is privileged, and the stack is set to main.
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDT_IRQHandler /* Window Watchdog Timer */
+ .word PVM_IRQHandler /* PVM through EXINT Line detect */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */
+ .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */
+ .word FLASH_IRQHandler /* Flash */
+ .word CRM_IRQHandler /* CRM */
+ .word EXINT0_IRQHandler /* EXINT Line 0 */
+ .word EXINT1_IRQHandler /* EXINT Line 1 */
+ .word EXINT2_IRQHandler /* EXINT Line 2 */
+ .word EXINT3_IRQHandler /* EXINT Line 3 */
+ .word EXINT4_IRQHandler /* EXINT Line 4 */
+ .word EDMA_Stream1_IRQHandler /* EDMA Stream 1 */
+ .word EDMA_Stream2_IRQHandler /* EDMA Stream 2 */
+ .word EDMA_Stream3_IRQHandler /* EDMA Stream 3 */
+ .word EDMA_Stream4_IRQHandler /* EDMA Stream 4 */
+ .word EDMA_Stream5_IRQHandler /* EDMA Stream 5 */
+ .word EDMA_Stream6_IRQHandler /* EDMA Stream 6 */
+ .word EDMA_Stream7_IRQHandler /* EDMA Stream 7 */
+ .word ADC1_2_3_IRQHandler /* ADC1 & ADC2 & ADC3 */
+ .word CAN1_TX_IRQHandler /* CAN1 TX */
+ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
+ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
+ .word CAN1_SE_IRQHandler /* CAN1 SE */
+ .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */
+ .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */
+ .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */
+ .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */
+ .word TMR1_CH_IRQHandler /* TMR1 Channel */
+ .word TMR2_GLOBAL_IRQHandler /* TMR2 */
+ .word TMR3_GLOBAL_IRQHandler /* TMR3 */
+ .word TMR4_GLOBAL_IRQHandler /* TMR4 */
+ .word I2C1_EVT_IRQHandler /* I2C1 Event */
+ .word I2C1_ERR_IRQHandler /* I2C1 Error */
+ .word I2C2_EVT_IRQHandler /* I2C2 Event */
+ .word I2C2_ERR_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_I2S2EXT_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */
+ .word ERTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */
+ .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */
+ .word TMR8_BRK_TMR12_IRQHandler /* TMR8 Brake and TMR12 */
+ .word TMR8_OVF_TMR13_IRQHandler /* TMR8 Overflow and TMR13 */
+ .word TMR8_TRG_HALL_TMR14_IRQHandler /* TMR8 Trigger and hall and TMR14 */
+ .word TMR8_CH_IRQHandler /* TMR8 Channel */
+ .word EDMA_Stream8_IRQHandler /* EDMA Stream 8 */
+ .word XMC_IRQHandler /* XMC */
+ .word SDIO1_IRQHandler /* SDIO1 */
+ .word TMR5_GLOBAL_IRQHandler /* TMR5 */
+ .word SPI3_I2S3EXT_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TMR6_DAC_GLOBAL_IRQHandler /* TMR6 & DAC */
+ .word TMR7_GLOBAL_IRQHandler /* TMR7 */
+ .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
+ .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
+ .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
+ .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
+ .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
+ .word EMAC_IRQHandler /* EMAC */
+ .word EMAC_WKUP_IRQHandler /* EMAC Wakeup */
+ .word CAN2_TX_IRQHandler /* CAN2 TX */
+ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
+ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
+ .word CAN2_SE_IRQHandler /* CAN2 SE */
+ .word OTGFS1_IRQHandler /* OTGFS1 */
+ .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
+ .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
+ .word 0 /* Reserved */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EVT_IRQHandler /* I2C3 Event */
+ .word I2C3_ERR_IRQHandler /* I2C3 Error */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word OTGFS2_WKUP_IRQHandler /* OTGFS2 Wakeup from suspend */
+ .word OTGFS2_IRQHandler /* OTGFS2 */
+ .word DVP_IRQHandler /* DVP */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word QSPI2_IRQHandler /* QSPI2 */
+ .word QSPI1_IRQHandler /* QSPI1 */
+ .word 0 /* Reserved */
+ .word DMAMUX_IRQHandler /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word SDIO2_IRQHandler /* SDIO2 */
+ .word ACC_IRQHandler /* ACC */
+ .word TMR20_BRK_IRQHandler /* TMR20 Brake */
+ .word TMR20_OVF_IRQHandler /* TMR20 Overflow */
+ .word TMR20_TRG_HALL_IRQHandler /* TMR20 Trigger and hall */
+ .word TMR20_CH_IRQHandler /* TMR20 Channel */
+ .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */
+ .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */
+ .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */
+ .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */
+ .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */
+ .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */
+ .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDT_IRQHandler
+ .thumb_set WWDT_IRQHandler,Default_Handler
+
+ .weak PVM_IRQHandler
+ .thumb_set PVM_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak ERTC_WKUP_IRQHandler
+ .thumb_set ERTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak CRM_IRQHandler
+ .thumb_set CRM_IRQHandler,Default_Handler
+
+ .weak EXINT0_IRQHandler
+ .thumb_set EXINT0_IRQHandler,Default_Handler
+
+ .weak EXINT1_IRQHandler
+ .thumb_set EXINT1_IRQHandler,Default_Handler
+
+ .weak EXINT2_IRQHandler
+ .thumb_set EXINT2_IRQHandler,Default_Handler
+
+ .weak EXINT3_IRQHandler
+ .thumb_set EXINT3_IRQHandler,Default_Handler
+
+ .weak EXINT4_IRQHandler
+ .thumb_set EXINT4_IRQHandler,Default_Handler
+
+ .weak EDMA_Stream1_IRQHandler
+ .thumb_set EDMA_Stream1_IRQHandler,Default_Handler
+
+ .weak EDMA_Stream2_IRQHandler
+ .thumb_set EDMA_Stream2_IRQHandler,Default_Handler
+
+ .weak EDMA_Stream3_IRQHandler
+ .thumb_set EDMA_Stream3_IRQHandler,Default_Handler
+
+ .weak EDMA_Stream4_IRQHandler
+ .thumb_set EDMA_Stream4_IRQHandler,Default_Handler
+
+ .weak EDMA_Stream5_IRQHandler
+ .thumb_set EDMA_Stream5_IRQHandler,Default_Handler
+
+ .weak EDMA_Stream6_IRQHandler
+ .thumb_set EDMA_Stream6_IRQHandler,Default_Handler
+
+ .weak EDMA_Stream7_IRQHandler
+ .thumb_set EDMA_Stream7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_3_IRQHandler
+ .thumb_set ADC1_2_3_IRQHandler,Default_Handler
+
+ .weak CAN1_TX_IRQHandler
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+ .weak CAN1_RX0_IRQHandler
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SE_IRQHandler
+ .thumb_set CAN1_SE_IRQHandler,Default_Handler
+
+ .weak EXINT9_5_IRQHandler
+ .thumb_set EXINT9_5_IRQHandler,Default_Handler
+
+ .weak TMR1_BRK_TMR9_IRQHandler
+ .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+ .weak TMR1_OVF_TMR10_IRQHandler
+ .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler
+
+ .weak TMR1_TRG_HALL_TMR11_IRQHandler
+ .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
+
+ .weak TMR1_CH_IRQHandler
+ .thumb_set TMR1_CH_IRQHandler,Default_Handler
+
+ .weak TMR2_GLOBAL_IRQHandler
+ .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+ .weak TMR3_GLOBAL_IRQHandler
+ .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+ .weak TMR4_GLOBAL_IRQHandler
+ .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+ .weak I2C1_EVT_IRQHandler
+ .thumb_set I2C1_EVT_IRQHandler,Default_Handler
+
+ .weak I2C1_ERR_IRQHandler
+ .thumb_set I2C1_ERR_IRQHandler,Default_Handler
+
+ .weak I2C2_EVT_IRQHandler
+ .thumb_set I2C2_EVT_IRQHandler,Default_Handler
+
+ .weak I2C2_ERR_IRQHandler
+ .thumb_set I2C2_ERR_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_I2S2EXT_IRQHandler
+ .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXINT15_10_IRQHandler
+ .thumb_set EXINT15_10_IRQHandler,Default_Handler
+
+ .weak ERTCAlarm_IRQHandler
+ .thumb_set ERTCAlarm_IRQHandler,Default_Handler
+
+ .weak OTGFS1_WKUP_IRQHandler
+ .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler
+
+ .weak TMR8_BRK_TMR12_IRQHandler
+ .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+ .weak TMR8_OVF_TMR13_IRQHandler
+ .thumb_set TMR8_OVF_TMR13_IRQHandler,Default_Handler
+
+ .weak TMR8_TRG_HALL_TMR14_IRQHandler
+ .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler
+
+ .weak TMR8_CH_IRQHandler
+ .thumb_set TMR8_CH_IRQHandler,Default_Handler
+
+ .weak EDMA_Stream8_IRQHandler
+ .thumb_set EDMA_Stream8_IRQHandler,Default_Handler
+
+ .weak XMC_IRQHandler
+ .thumb_set XMC_IRQHandler,Default_Handler
+
+ .weak SDIO1_IRQHandler
+ .thumb_set SDIO1_IRQHandler,Default_Handler
+
+ .weak TMR5_GLOBAL_IRQHandler
+ .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+ .weak SPI3_I2S3EXT_IRQHandler
+ .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TMR6_DAC_GLOBAL_IRQHandler
+ .thumb_set TMR6_DAC_GLOBAL_IRQHandler,Default_Handler
+
+ .weak TMR7_GLOBAL_IRQHandler
+ .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak EMAC_IRQHandler
+ .thumb_set EMAC_IRQHandler,Default_Handler
+
+ .weak EMAC_WKUP_IRQHandler
+ .thumb_set EMAC_WKUP_IRQHandler,Default_Handler
+
+ .weak CAN2_TX_IRQHandler
+ .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+ .weak CAN2_RX0_IRQHandler
+ .thumb_set CAN2_RX0_IRQHandler ,Default_Handler
+
+ .weak CAN2_RX1_IRQHandler
+ .thumb_set CAN2_RX1_IRQHandler ,Default_Handler
+
+ .weak CAN2_SE_IRQHandler
+ .thumb_set CAN2_SE_IRQHandler,Default_Handler
+
+ .weak OTGFS1_IRQHandler
+ .thumb_set OTGFS1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EVT_IRQHandler
+ .thumb_set I2C3_EVT_IRQHandler,Default_Handler
+
+ .weak I2C3_ERR_IRQHandler
+ .thumb_set I2C3_ERR_IRQHandler,Default_Handler
+
+ .weak OTGFS2_WKUP_IRQHandler
+ .thumb_set OTGFS2_WKUP_IRQHandler,Default_Handler
+
+ .weak OTGFS2_IRQHandler
+ .thumb_set OTGFS2_IRQHandler,Default_Handler
+
+ .weak DVP_IRQHandler
+ .thumb_set DVP_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak QSPI2_IRQHandler
+ .thumb_set QSPI2_IRQHandler,Default_Handler
+
+ .weak QSPI1_IRQHandler
+ .thumb_set QSPI1_IRQHandler,Default_Handler
+
+ .weak DMAMUX_IRQHandler
+ .thumb_set DMAMUX_IRQHandler ,Default_Handler
+
+ .weak SDIO2_IRQHandler
+ .thumb_set SDIO2_IRQHandler ,Default_Handler
+
+ .weak ACC_IRQHandler
+ .thumb_set ACC_IRQHandler,Default_Handler
+
+ .weak TMR20_BRK_IRQHandler
+ .thumb_set TMR20_BRK_IRQHandler,Default_Handler
+
+ .weak TMR20_OVF_IRQHandler
+ .thumb_set TMR20_OVF_IRQHandler,Default_Handler
+
+ .weak TMR20_TRG_HALL_IRQHandler
+ .thumb_set TMR20_TRG_HALL_IRQHandler,Default_Handler
+
+ .weak TMR20_CH_IRQHandler
+ .thumb_set TMR20_CH_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel6_IRQHandler
+ .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel7_IRQHandler
+ .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_acc.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_acc.h
new file mode 100644
index 0000000..061da6e
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_acc.h
@@ -0,0 +1,205 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_acc.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 acc header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_ACC_H
+#define __AT32F435_437_ACC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup ACC
+ * @{
+ */
+
+/** @defgroup ACC_exported_constants
+ * @{
+ */
+
+#define ACC_CAL_HICKCAL ((uint16_t)0x0000) /*!< acc hick calibration */
+#define ACC_CAL_HICKTRIM ((uint16_t)0x0002) /*!< acc hick trim */
+
+#define ACC_RSLOST_FLAG ((uint16_t)0x0002) /*!< acc reference signal lost error flag */
+#define ACC_CALRDY_FLAG ((uint16_t)0x0001) /*!< acc internal high-speed clock calibration ready error flag */
+
+#define ACC_CALRDYIEN_INT ((uint16_t)0x0020) /*!< acc internal high-speed clock calibration ready interrupt enable */
+#define ACC_EIEN_INT ((uint16_t)0x0010) /*!< acc reference signal lost interrupt enable */
+
+#define ACC_SOF_OTG1 ((uint16_t)0x0000) /*!< acc sof signal select: otg1 */
+#define ACC_SOF_OTG2 ((uint16_t)0x0004) /*!< acc sof signal select: otg2 */
+
+/**
+ * @}
+ */
+
+/** @defgroup ACC_exported_types
+ * @{
+ */
+
+/**
+ * @brief type define acc register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief acc sts register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t calrdy : 1; /* [0] */
+ __IO uint32_t rslost : 1; /* [1] */
+ __IO uint32_t reserved1 : 30;/* [31:2] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief acc ctrl1 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t calon : 1; /* [0] */
+ __IO uint32_t entrim : 1; /* [1] */
+ __IO uint32_t reserved1 : 2; /* [3:2] */
+ __IO uint32_t eien : 1; /* [4] */
+ __IO uint32_t calrdyien : 1; /* [5] */
+ __IO uint32_t reserved2 : 2; /* [7:6] */
+ __IO uint32_t step : 4; /* [11:8] */
+ __IO uint32_t reserved3 : 20;/* [31:12] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief acc ctrl2 register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t hickcal : 8; /* [7:0] */
+ __IO uint32_t hicktrim : 6; /* [13:8] */
+ __IO uint32_t reserved1 : 18;/* [31:14] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief acc acc_c1 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t c1;
+ struct
+ {
+ __IO uint32_t c1 : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } c1_bit;
+ };
+
+ /**
+ * @brief acc acc_c2 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t c2;
+ struct
+ {
+ __IO uint32_t c2 : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } c2_bit;
+ };
+
+ /**
+ * @brief acc acc_c3 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t c3;
+ struct
+ {
+ __IO uint32_t c3 : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } c3_bit;
+ };
+} acc_type;
+
+/**
+ * @}
+ */
+
+#define ACC ((acc_type *) ACC_BASE)
+
+/** @defgroup ACC_exported_functions
+ * @{
+ */
+
+void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state);
+void acc_step_set(uint8_t step_value);
+void acc_sof_select(uint16_t sof_sel);
+void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state);
+uint8_t acc_hicktrim_get(void);
+uint8_t acc_hickcal_get(void);
+void acc_write_c1(uint16_t acc_c1_value);
+void acc_write_c2(uint16_t acc_c2_value);
+void acc_write_c3(uint16_t acc_c3_value);
+uint16_t acc_read_c1(void);
+uint16_t acc_read_c2(void);
+uint16_t acc_read_c3(void);
+flag_status acc_flag_get(uint16_t acc_flag);
+void acc_flag_clear(uint16_t acc_flag);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_adc.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_adc.h
new file mode 100644
index 0000000..53510b9
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_adc.h
@@ -0,0 +1,938 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_adc.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 adc header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_ADC_H
+#define __AT32F435_437_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/** @defgroup ADC_interrupts_definition
+ * @brief adc interrupt
+ * @{
+ */
+
+#define ADC_OCCE_INT ((uint32_t)0x00000020) /*!< ordinary channels conversion end interrupt */
+#define ADC_VMOR_INT ((uint32_t)0x00000040) /*!< voltage monitoring out of range interrupt */
+#define ADC_PCCE_INT ((uint32_t)0x00000080) /*!< preempt channels conversion end interrupt */
+#define ADC_OCCO_INT ((uint32_t)0x04000000) /*!< ordinary channel conversion overflow interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition
+ * @brief adc flag
+ * @{
+ */
+
+#define ADC_VMOR_FLAG ((uint8_t)0x01) /*!< voltage monitoring out of range flag */
+#define ADC_OCCE_FLAG ((uint8_t)0x02) /*!< ordinary channels conversion end flag */
+#define ADC_PCCE_FLAG ((uint8_t)0x04) /*!< preempt channels conversion end flag */
+#define ADC_PCCS_FLAG ((uint8_t)0x08) /*!< preempt channel conversion start flag */
+#define ADC_OCCS_FLAG ((uint8_t)0x10) /*!< ordinary channel conversion start flag */
+#define ADC_OCCO_FLAG ((uint8_t)0x20) /*!< ordinary channel conversion overflow flag */
+#define ADC_RDY_FLAG ((uint8_t)0x40) /*!< adc ready to conversion flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_exported_types
+ * @{
+ */
+
+/**
+ * @brief adc division type
+ */
+typedef enum
+{
+ ADC_HCLK_DIV_2 = 0x00, /*!< adcclk is hclk/2 */
+ ADC_HCLK_DIV_3 = 0x01, /*!< adcclk is hclk/3 */
+ ADC_HCLK_DIV_4 = 0x02, /*!< adcclk is hclk/4 */
+ ADC_HCLK_DIV_5 = 0x03, /*!< adcclk is hclk/5 */
+ ADC_HCLK_DIV_6 = 0x04, /*!< adcclk is hclk/6 */
+ ADC_HCLK_DIV_7 = 0x05, /*!< adcclk is hclk/7 */
+ ADC_HCLK_DIV_8 = 0x06, /*!< adcclk is hclk/8 */
+ ADC_HCLK_DIV_9 = 0x07, /*!< adcclk is hclk/9 */
+ ADC_HCLK_DIV_10 = 0x08, /*!< adcclk is hclk/10 */
+ ADC_HCLK_DIV_11 = 0x09, /*!< adcclk is hclk/11 */
+ ADC_HCLK_DIV_12 = 0x0A, /*!< adcclk is hclk/12 */
+ ADC_HCLK_DIV_13 = 0x0B, /*!< adcclk is hclk/13 */
+ ADC_HCLK_DIV_14 = 0x0C, /*!< adcclk is hclk/14 */
+ ADC_HCLK_DIV_15 = 0x0D, /*!< adcclk is hclk/15 */
+ ADC_HCLK_DIV_16 = 0x0E, /*!< adcclk is hclk/16 */
+ ADC_HCLK_DIV_17 = 0x0F /*!< adcclk is hclk/17 */
+} adc_div_type;
+
+/**
+ * @brief adc combine mode type
+ */
+typedef enum
+{
+ ADC_INDEPENDENT_MODE = 0x00, /*!< independent mode */
+ ADC_ORDINARY_SMLT_PREEMPT_SMLT_ONESLAVE_MODE = 0x01, /*!< single slaver combined ordinary simultaneous + preempt simultaneous mode */
+ ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_ONESLAVE_MODE = 0x02, /*!< single slaver combined ordinary simultaneous + preempt interleaved trigger mode */
+ ADC_PREEMPT_SMLT_ONLY_ONESLAVE_MODE = 0x05, /*!< single slaver preempt simultaneous mode only */
+ ADC_ORDINARY_SMLT_ONLY_ONESLAVE_MODE = 0x06, /*!< single slaver ordinary simultaneous mode only */
+ ADC_ORDINARY_SHIFT_ONLY_ONESLAVE_MODE = 0x07, /*!< single slaver ordinary shifting mode only */
+ ADC_PREEMPT_INTERLTRIG_ONLY_ONESLAVE_MODE = 0x09, /*!< single slaver preempt interleaved trigger mode only */
+ ADC_ORDINARY_SMLT_PREEMPT_SMLT_TWOSLAVE_MODE = 0x11, /*!< double slaver combined ordinary simultaneous + preempt simultaneous mode */
+ ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_TWOSLAVE_MODE = 0x12, /*!< double slaver combined ordinary simultaneous + preempt interleaved trigger mode */
+ ADC_PREEMPT_SMLT_ONLY_TWOSLAVE_MODE = 0x15, /*!< double slaver preempt simultaneous mode only */
+ ADC_ORDINARY_SMLT_ONLY_TWOSLAVE_MODE = 0x16, /*!< double slaver ordinary simultaneous mode only */
+ ADC_ORDINARY_SHIFT_ONLY_TWOSLAVE_MODE = 0x17, /*!< double slaver ordinary shifting mode only */
+ ADC_PREEMPT_INTERLTRIG_ONLY_TWOSLAVE_MODE = 0x19 /*!< double slaver preempt interleaved trigger mode only */
+} adc_combine_mode_type;
+
+/**
+ * @brief adc common dma mode type
+ */
+typedef enum
+{
+ ADC_COMMON_DMAMODE_DISABLE = 0x00, /*!< dma mode disabled */
+ ADC_COMMON_DMAMODE_1 = 0x01, /*!< dma mode1: each dma request trans a half-word data(reference manual account the rule of data package) */
+ ADC_COMMON_DMAMODE_2 = 0x02, /*!< dma mode2: each dma request trans two half-word data(reference manual account the rule of data package) */
+ ADC_COMMON_DMAMODE_3 = 0x03, /*!< dma mode3: each dma request trans two bytes data(reference manual account the rule of data package) */
+ ADC_COMMON_DMAMODE_4 = 0x04, /*!< dma mode4: each dma request trans three bytes data(reference manual account the rule of data package) */
+ ADC_COMMON_DMAMODE_5 = 0x05 /*!< dma mode5: odd dma request trans two half-word data,even dma request trans a half-word data(reference manual account the rule of data package) */
+} adc_common_dma_mode_type;
+
+/**
+ * @brief adc common sampling interval type
+ */
+typedef enum
+{
+ ADC_SAMPLING_INTERVAL_5CYCLES = 0x00, /*!< ordinary shifting mode adjacent adc sampling interval 5 adcclk */
+ ADC_SAMPLING_INTERVAL_6CYCLES = 0x01, /*!< ordinary shifting mode adjacent adc sampling interval 6 adcclk */
+ ADC_SAMPLING_INTERVAL_7CYCLES = 0x02, /*!< ordinary shifting mode adjacent adc sampling interval 7 adcclk */
+ ADC_SAMPLING_INTERVAL_8CYCLES = 0x03, /*!< ordinary shifting mode adjacent adc sampling interval 8 adcclk */
+ ADC_SAMPLING_INTERVAL_9CYCLES = 0x04, /*!< ordinary shifting mode adjacent adc sampling interval 9 adcclk */
+ ADC_SAMPLING_INTERVAL_10CYCLES = 0x05, /*!< ordinary shifting mode adjacent adc sampling interval 10 adcclk */
+ ADC_SAMPLING_INTERVAL_11CYCLES = 0x06, /*!< ordinary shifting mode adjacent adc sampling interval 11 adcclk */
+ ADC_SAMPLING_INTERVAL_12CYCLES = 0x07, /*!< ordinary shifting mode adjacent adc sampling interval 12 adcclk */
+ ADC_SAMPLING_INTERVAL_13CYCLES = 0x08, /*!< ordinary shifting mode adjacent adc sampling interval 13 adcclk */
+ ADC_SAMPLING_INTERVAL_14CYCLES = 0x09, /*!< ordinary shifting mode adjacent adc sampling interval 14 adcclk */
+ ADC_SAMPLING_INTERVAL_15CYCLES = 0x0A, /*!< ordinary shifting mode adjacent adc sampling interval 15 adcclk */
+ ADC_SAMPLING_INTERVAL_16CYCLES = 0x0B, /*!< ordinary shifting mode adjacent adc sampling interval 16 adcclk */
+ ADC_SAMPLING_INTERVAL_17CYCLES = 0x0C, /*!< ordinary shifting mode adjacent adc sampling interval 17 adcclk */
+ ADC_SAMPLING_INTERVAL_18CYCLES = 0x0D, /*!< ordinary shifting mode adjacent adc sampling interval 18 adcclk */
+ ADC_SAMPLING_INTERVAL_19CYCLES = 0x0E, /*!< ordinary shifting mode adjacent adc sampling interval 19 adcclk */
+ ADC_SAMPLING_INTERVAL_20CYCLES = 0x0F /*!< ordinary shifting mode adjacent adc sampling interval 20 adcclk */
+} adc_sampling_interval_type;
+
+/**
+ * @brief adc conversion resolution type
+ */
+typedef enum
+{
+ ADC_RESOLUTION_12B = 0x00, /*!< conversion resolution 12 bit */
+ ADC_RESOLUTION_10B = 0x01, /*!< conversion resolution 10 bit */
+ ADC_RESOLUTION_8B = 0x02, /*!< conversion resolution 8 bit */
+ ADC_RESOLUTION_6B = 0x03 /*!< conversion resolution 6 bit */
+} adc_resolution_type;
+
+/**
+ * @brief adc data align type
+ */
+typedef enum
+{
+ ADC_RIGHT_ALIGNMENT = 0x00, /*!< data right alignment */
+ ADC_LEFT_ALIGNMENT = 0x01 /*!< data left alignment */
+} adc_data_align_type;
+
+/**
+ * @brief adc channel select type
+ */
+typedef enum
+{
+ ADC_CHANNEL_0 = 0x00, /*!< adc channel 0 */
+ ADC_CHANNEL_1 = 0x01, /*!< adc channel 1 */
+ ADC_CHANNEL_2 = 0x02, /*!< adc channel 2 */
+ ADC_CHANNEL_3 = 0x03, /*!< adc channel 3 */
+ ADC_CHANNEL_4 = 0x04, /*!< adc channel 4 */
+ ADC_CHANNEL_5 = 0x05, /*!< adc channel 5 */
+ ADC_CHANNEL_6 = 0x06, /*!< adc channel 6 */
+ ADC_CHANNEL_7 = 0x07, /*!< adc channel 7 */
+ ADC_CHANNEL_8 = 0x08, /*!< adc channel 8 */
+ ADC_CHANNEL_9 = 0x09, /*!< adc channel 9 */
+ ADC_CHANNEL_10 = 0x0A, /*!< adc channel 10 */
+ ADC_CHANNEL_11 = 0x0B, /*!< adc channel 11 */
+ ADC_CHANNEL_12 = 0x0C, /*!< adc channel 12 */
+ ADC_CHANNEL_13 = 0x0D, /*!< adc channel 13 */
+ ADC_CHANNEL_14 = 0x0E, /*!< adc channel 14 */
+ ADC_CHANNEL_15 = 0x0F, /*!< adc channel 15 */
+ ADC_CHANNEL_16 = 0x10, /*!< adc channel 16 */
+ ADC_CHANNEL_17 = 0x11, /*!< adc channel 17 */
+ ADC_CHANNEL_18 = 0x12 /*!< adc channel 18 */
+} adc_channel_select_type;
+
+/**
+ * @brief adc sampletime select type
+ */
+typedef enum
+{
+ ADC_SAMPLETIME_2_5 = 0x00, /*!< adc sample time 2.5 cycle */
+ ADC_SAMPLETIME_6_5 = 0x01, /*!< adc sample time 6.5 cycle */
+ ADC_SAMPLETIME_12_5 = 0x02, /*!< adc sample time 12.5 cycle */
+ ADC_SAMPLETIME_24_5 = 0x03, /*!< adc sample time 24.5 cycle */
+ ADC_SAMPLETIME_47_5 = 0x04, /*!< adc sample time 47.5 cycle */
+ ADC_SAMPLETIME_92_5 = 0x05, /*!< adc sample time 92.5 cycle */
+ ADC_SAMPLETIME_247_5 = 0x06, /*!< adc sample time 247.5 cycle */
+ ADC_SAMPLETIME_640_5 = 0x07 /*!< adc sample time 640.5 cycle */
+} adc_sampletime_select_type;
+
+/**
+ * @brief adc ordinary group trigger event select type
+ */
+typedef enum
+{
+ ADC_ORDINARY_TRIG_TMR1CH1 = 0x00, /*!< timer1 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR1CH2 = 0x01, /*!< timer1 ch2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR1CH3 = 0x02, /*!< timer1 ch3 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR2CH2 = 0x03, /*!< timer2 ch2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR2CH3 = 0x04, /*!< timer2 ch3 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR2CH4 = 0x05, /*!< timer2 ch4 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR2TRGOUT = 0x06, /*!< timer2 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR3CH1 = 0x07, /*!< timer3 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR3TRGOUT = 0x08, /*!< timer3 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR4CH4 = 0x09, /*!< timer4 ch4 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR5CH1 = 0x0A, /*!< timer5 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR5CH2 = 0x0B, /*!< timer5 ch2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR5CH3 = 0x0C, /*!< timer5 ch3 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR8CH1 = 0x0D, /*!< timer8 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR8TRGOUT = 0x0E, /*!< timer8 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_EXINT11 = 0x0F, /*!< exint line11 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR20TRGOUT = 0x10, /*!< timer20 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR20TRGOUT2 = 0x11, /*!< timer20 trgout2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR20CH1 = 0x12, /*!< timer20 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR20CH2 = 0x13, /*!< timer20 ch2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR20CH3 = 0x14, /*!< timer20 ch3 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR8TRGOUT2 = 0x15, /*!< timer8 trgout2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR1TRGOUT2 = 0x16, /*!< timer1 trgout2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR4TRGOUT = 0x17, /*!< timer4 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR6TRGOUT = 0x18, /*!< timer6 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR3CH4 = 0x19, /*!< timer3 ch4 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR4CH1 = 0x1A, /*!< timer4 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR1TRGOUT = 0x1B, /*!< timer1 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR2CH1 = 0x1C, /*!< timer2 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR7TRGOUT = 0x1E /*!< timer7 trgout event as trigger source of ordinary sequence */
+} adc_ordinary_trig_select_type;
+
+/**
+ * @brief adc ordinary channel conversion's external_trigger_edge type
+ */
+typedef enum
+{
+ ADC_ORDINARY_TRIG_EDGE_NONE = 0x00, /*!< ordinary channels trigger detection disabled */
+ ADC_ORDINARY_TRIG_EDGE_RISING = 0x01, /*!< ordinary channels trigger detection on the rising edge */
+ ADC_ORDINARY_TRIG_EDGE_FALLING = 0x02, /*!< ordinary channels trigger detection on the falling edge */
+ ADC_ORDINARY_TRIG_EDGE_RISING_FALLING = 0x03 /*!< ordinary channels trigger detection on both the rising and falling edges */
+} adc_ordinary_trig_edge_type;
+
+/**
+ * @brief adc preempt group external trigger event select type
+ */
+typedef enum
+{
+ ADC_PREEMPT_TRIG_TMR1CH4 = 0x00, /*!< timer1 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR1TRGOUT = 0x01, /*!< timer1 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR2CH1 = 0x02, /*!< timer2 ch1 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR2TRGOUT = 0x03, /*!< timer2 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR3CH2 = 0x04, /*!< timer3 ch2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR3CH4 = 0x05, /*!< timer3 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR4CH1 = 0x06, /*!< timer4 ch1 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR4CH2 = 0x07, /*!< timer4 ch2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR4CH3 = 0x08, /*!< timer4 ch3 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR4TRGOUT = 0x09, /*!< timer4 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR5CH4 = 0x0A, /*!< timer5 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR5TRGOUT = 0x0B, /*!< timer5 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR8CH2 = 0x0C, /*!< timer8 ch2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR8CH3 = 0x0D, /*!< timer8 ch3 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR8CH4 = 0x0E, /*!< timer8 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_EXINT15 = 0x0F, /*!< exint line15 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR20TRGOUT = 0x10, /*!< timer20 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR20TRGOUT2 = 0x11, /*!< timer20 trgout2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR20CH4 = 0x12, /*!< timer20 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR1TRGOUT2 = 0x13, /*!< timer1 trgout2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR8TRGOUT = 0x14, /*!< timer8 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR8TRGOUT2 = 0x15, /*!< timer8 trgout2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR3CH3 = 0x16, /*!< timer3 ch3 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR3TRGOUT = 0x17, /*!< timer3 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR3CH1 = 0x18, /*!< timer3 ch1 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR6TRGOUT = 0x19, /*!< timer6 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR4CH4 = 0x1A, /*!< timer4 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR1CH3 = 0x1B, /*!< timer1 ch3 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR20CH2 = 0x1C, /*!< timer20 ch2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR7TRGOUT = 0x1E /*!< timer7 trgout event as trigger source of preempt sequence */
+} adc_preempt_trig_select_type;
+
+/**
+ * @brief adc preempt channel conversion's external_trigger_edge type
+ */
+typedef enum
+{
+ ADC_PREEMPT_TRIG_EDGE_NONE = 0x00, /*!< preempt channels trigger detection disabled */
+ ADC_PREEMPT_TRIG_EDGE_RISING = 0x01, /*!< preempt channels trigger detection on the rising edge */
+ ADC_PREEMPT_TRIG_EDGE_FALLING = 0x02, /*!< preempt channels trigger detection on the falling edge */
+ ADC_PREEMPT_TRIG_EDGE_RISING_FALLING = 0x03 /*!< preempt channels trigger detection on both the rising and falling edges */
+} adc_preempt_trig_edge_type;
+
+/**
+ * @brief adc preempt channel type
+ */
+typedef enum
+{
+ ADC_PREEMPT_CHANNEL_1 = 0x00, /*!< adc preempt channel 1 */
+ ADC_PREEMPT_CHANNEL_2 = 0x01, /*!< adc preempt channel 2 */
+ ADC_PREEMPT_CHANNEL_3 = 0x02, /*!< adc preempt channel 3 */
+ ADC_PREEMPT_CHANNEL_4 = 0x03 /*!< adc preempt channel 4 */
+} adc_preempt_channel_type;
+
+/**
+ * @brief adc voltage_monitoring type
+ */
+typedef enum
+{
+ ADC_VMONITOR_SINGLE_ORDINARY = 0x00800200, /*!< voltage_monitoring on a single ordinary channel */
+ ADC_VMONITOR_SINGLE_PREEMPT = 0x00400200, /*!< voltage_monitoring on a single preempt channel */
+ ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT = 0x00C00200, /*!< voltage_monitoring on a single ordinary or preempt channel */
+ ADC_VMONITOR_ALL_ORDINARY = 0x00800000, /*!< voltage_monitoring on all ordinary channel */
+ ADC_VMONITOR_ALL_PREEMPT = 0x00400000, /*!< voltage_monitoring on all preempt channel */
+ ADC_VMONITOR_ALL_ORDINARY_PREEMPT = 0x00C00000, /*!< voltage_monitoring on all ordinary and preempt channel */
+ ADC_VMONITOR_NONE = 0x00000000 /*!< no channel guarded by the voltage_monitoring */
+} adc_voltage_monitoring_type;
+
+/**
+ * @brief adc oversample ratio type
+ */
+typedef enum
+{
+ ADC_OVERSAMPLE_RATIO_2 = 0x00, /*!< adc oversample ratio 2 */
+ ADC_OVERSAMPLE_RATIO_4 = 0x01, /*!< adc oversample ratio 4 */
+ ADC_OVERSAMPLE_RATIO_8 = 0x02, /*!< adc oversample ratio 8 */
+ ADC_OVERSAMPLE_RATIO_16 = 0x03, /*!< adc oversample ratio 16 */
+ ADC_OVERSAMPLE_RATIO_32 = 0x04, /*!< adc oversample ratio 32 */
+ ADC_OVERSAMPLE_RATIO_64 = 0x05, /*!< adc oversample ratio 64 */
+ ADC_OVERSAMPLE_RATIO_128 = 0x06, /*!< adc oversample ratio 128 */
+ ADC_OVERSAMPLE_RATIO_256 = 0x07 /*!< adc oversample ratio 256 */
+} adc_oversample_ratio_type;
+
+/**
+ * @brief adc oversample shift type
+ */
+typedef enum
+{
+ ADC_OVERSAMPLE_SHIFT_0 = 0x00, /*!< adc oversample shift 0 */
+ ADC_OVERSAMPLE_SHIFT_1 = 0x01, /*!< adc oversample shift 1 */
+ ADC_OVERSAMPLE_SHIFT_2 = 0x02, /*!< adc oversample shift 2 */
+ ADC_OVERSAMPLE_SHIFT_3 = 0x03, /*!< adc oversample shift 3 */
+ ADC_OVERSAMPLE_SHIFT_4 = 0x04, /*!< adc oversample shift 4 */
+ ADC_OVERSAMPLE_SHIFT_5 = 0x05, /*!< adc oversample shift 5 */
+ ADC_OVERSAMPLE_SHIFT_6 = 0x06, /*!< adc oversample shift 6 */
+ ADC_OVERSAMPLE_SHIFT_7 = 0x07, /*!< adc oversample shift 7 */
+ ADC_OVERSAMPLE_SHIFT_8 = 0x08 /*!< adc oversample shift 8 */
+} adc_oversample_shift_type;
+
+/**
+ * @brief adc ordinary oversample recover type
+ */
+typedef enum
+{
+ ADC_OVERSAMPLE_CONTINUE = 0x00, /*!< continue mode:when preempt triggered,oversampling is temporary stopped and continued after preempt sequence */
+ ADC_OVERSAMPLE_RESTART = 0x01 /*!< restart mode:when preempt triggered,oversampling is aborted and resumed from start after preempt sequence */
+} adc_ordinary_oversample_restart_type;
+
+/**
+ * @brief adc common config type
+ */
+typedef struct
+{
+ adc_combine_mode_type combine_mode; /*!< adc combine mode select */
+ adc_div_type div; /*!< adc division select */
+ adc_common_dma_mode_type common_dma_mode; /*!< adc common dma mode select */
+ confirm_state common_dma_request_repeat_state; /*!< adc common dma repeat state */
+ adc_sampling_interval_type sampling_interval; /*!< ordinary shifting mode adjacent adc sampling interval select */
+ confirm_state tempervintrv_state; /*!< adc temperature sensor and vintrv state */
+ confirm_state vbat_state; /*!< adc voltage battery state */
+} adc_common_config_type;
+
+/**
+ * @brief adc base config type
+ */
+typedef struct
+{
+ confirm_state sequence_mode; /*!< adc sequence mode */
+ confirm_state repeat_mode; /*!< adc repeat mode */
+ adc_data_align_type data_align; /*!< adc data alignment */
+ uint8_t ordinary_channel_length; /*!< adc ordinary channel sequence length*/
+} adc_base_config_type;
+
+/**
+ * @brief type define adc register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief adc sts register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t vmor : 1; /* [0] */
+ __IO uint32_t occe : 1; /* [1] */
+ __IO uint32_t pcce : 1; /* [2] */
+ __IO uint32_t pccs : 1; /* [3] */
+ __IO uint32_t occs : 1; /* [4] */
+ __IO uint32_t occo : 1; /* [5] */
+ __IO uint32_t rdy : 1; /* [6] */
+ __IO uint32_t reserved1 : 25;/* [31:7] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief adc ctrl1 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t vmcsel : 5; /* [4:0] */
+ __IO uint32_t occeien : 1; /* [5] */
+ __IO uint32_t vmorien : 1; /* [6] */
+ __IO uint32_t pcceien : 1; /* [7] */
+ __IO uint32_t sqen : 1; /* [8] */
+ __IO uint32_t vmsgen : 1; /* [9] */
+ __IO uint32_t pcautoen : 1; /* [10] */
+ __IO uint32_t ocpen : 1; /* [11] */
+ __IO uint32_t pcpen : 1; /* [12] */
+ __IO uint32_t ocpcnt : 3; /* [15:13] */
+ __IO uint32_t reserved1 : 6; /* [21:16] */
+ __IO uint32_t pcvmen : 1; /* [22] */
+ __IO uint32_t ocvmen : 1; /* [23] */
+ __IO uint32_t crsel : 2; /* [25:24] */
+ __IO uint32_t occoien : 1; /* [26] */
+ __IO uint32_t reserved2 : 5; /* [31:27] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief adc ctrl2 register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t adcen : 1; /* [0] */
+ __IO uint32_t rpen : 1; /* [1] */
+ __IO uint32_t adcal : 1; /* [2] */
+ __IO uint32_t adcalinit : 1; /* [3] */
+ __IO uint32_t adabrt : 1; /* [4] */
+ __IO uint32_t reserved1 : 3; /* [7:5] */
+ __IO uint32_t ocdmaen : 1; /* [8] */
+ __IO uint32_t ocdrcen : 1; /* [9] */
+ __IO uint32_t eocsfen : 1; /* [10] */
+ __IO uint32_t dtalign : 1; /* [11] */
+ __IO uint32_t reserved2 : 4; /* [15:12] */
+ __IO uint32_t pctesel_l : 4; /* [19:16] */
+ __IO uint32_t pcete : 2; /* [21:20] */
+ __IO uint32_t pcswtrg : 1; /* [22] */
+ __IO uint32_t pctesel_h : 1; /* [23] */
+ __IO uint32_t octesel_l : 4; /* [27:24] */
+ __IO uint32_t ocete : 2; /* [29:28] */
+ __IO uint32_t ocswtrg : 1; /* [30] */
+ __IO uint32_t octesel_h : 1; /* [31] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief adc spt1 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t spt1;
+ struct
+ {
+ __IO uint32_t cspt10 : 3; /* [2:0] */
+ __IO uint32_t cspt11 : 3; /* [5:3] */
+ __IO uint32_t cspt12 : 3; /* [8:6] */
+ __IO uint32_t cspt13 : 3; /* [11:9] */
+ __IO uint32_t cspt14 : 3; /* [14:12] */
+ __IO uint32_t cspt15 : 3; /* [17:15] */
+ __IO uint32_t cspt16 : 3; /* [20:18] */
+ __IO uint32_t cspt17 : 3; /* [23:21] */
+ __IO uint32_t cspt18 : 3; /* [26:24] */
+ __IO uint32_t reserved1 : 5;/* [31:27] */
+ } spt1_bit;
+ };
+
+ /**
+ * @brief adc spt2 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t spt2;
+ struct
+ {
+ __IO uint32_t cspt0 : 3;/* [2:0] */
+ __IO uint32_t cspt1 : 3;/* [5:3] */
+ __IO uint32_t cspt2 : 3;/* [8:6] */
+ __IO uint32_t cspt3 : 3;/* [11:9] */
+ __IO uint32_t cspt4 : 3;/* [14:12] */
+ __IO uint32_t cspt5 : 3;/* [17:15] */
+ __IO uint32_t cspt6 : 3;/* [20:18] */
+ __IO uint32_t cspt7 : 3;/* [23:21] */
+ __IO uint32_t cspt8 : 3;/* [26:24] */
+ __IO uint32_t cspt9 : 3;/* [29:27] */
+ __IO uint32_t reserved1 : 2;/* [31:30] */
+ } spt2_bit;
+ };
+
+ /**
+ * @brief adc pcdto1 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t pcdto1;
+ struct
+ {
+ __IO uint32_t pcdto1 : 12; /* [11:0] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } pcdto1_bit;
+ };
+
+ /**
+ * @brief adc pcdto2 register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t pcdto2;
+ struct
+ {
+ __IO uint32_t pcdto2 : 12; /* [11:0] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } pcdto2_bit;
+ };
+
+ /**
+ * @brief adc pcdto3 register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t pcdto3;
+ struct
+ {
+ __IO uint32_t pcdto3 : 12; /* [11:0] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } pcdto3_bit;
+ };
+
+ /**
+ * @brief adc pcdto4 register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t pcdto4;
+ struct
+ {
+ __IO uint32_t pcdto4 : 12; /* [11:0] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } pcdto4_bit;
+ };
+
+ /**
+ * @brief adc vmhb register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t vmhb;
+ struct
+ {
+ __IO uint32_t vmhb : 12; /* [11:0] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } vmhb_bit;
+ };
+
+ /**
+ * @brief adc vmlb register, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t vmlb;
+ struct
+ {
+ __IO uint32_t vmlb : 12; /* [11:0] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } vmlb_bit;
+ };
+
+ /**
+ * @brief adc osq1 register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t osq1;
+ struct
+ {
+ __IO uint32_t osn13 : 5; /* [4:0] */
+ __IO uint32_t osn14 : 5; /* [9:5] */
+ __IO uint32_t osn15 : 5; /* [14:10] */
+ __IO uint32_t osn16 : 5; /* [19:15] */
+ __IO uint32_t oclen : 4; /* [23:20] */
+ __IO uint32_t reserved1 : 8; /* [31:24] */
+ } osq1_bit;
+ };
+
+ /**
+ * @brief adc osq2 register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t osq2;
+ struct
+ {
+ __IO uint32_t osn7 : 5; /* [4:0] */
+ __IO uint32_t osn8 : 5; /* [9:5] */
+ __IO uint32_t osn9 : 5; /* [14:10] */
+ __IO uint32_t osn10 : 5; /* [19:15] */
+ __IO uint32_t osn11 : 5; /* [24:20] */
+ __IO uint32_t osn12 : 5; /* [29:25] */
+ __IO uint32_t reserved1 : 2; /* [31:30] */
+ } osq2_bit;
+ };
+
+ /**
+ * @brief adc osq3 register, offset:0x34
+ */
+ union
+ {
+ __IO uint32_t osq3;
+ struct
+ {
+ __IO uint32_t osn1 : 5; /* [4:0] */
+ __IO uint32_t osn2 : 5; /* [9:5] */
+ __IO uint32_t osn3 : 5; /* [14:10] */
+ __IO uint32_t osn4 : 5; /* [19:15] */
+ __IO uint32_t osn5 : 5; /* [24:20] */
+ __IO uint32_t osn6 : 5; /* [29:25] */
+ __IO uint32_t reserved1 : 2; /* [31:30] */
+ } osq3_bit;
+ };
+
+ /**
+ * @brief adc psq register, offset:0x38
+ */
+ union
+ {
+ __IO uint32_t psq;
+ struct
+ {
+ __IO uint32_t psn1 : 5; /* [4:0] */
+ __IO uint32_t psn2 : 5; /* [9:5] */
+ __IO uint32_t psn3 : 5; /* [14:10] */
+ __IO uint32_t psn4 : 5; /* [19:15] */
+ __IO uint32_t pclen : 2; /* [21:20] */
+ __IO uint32_t reserved1 : 10;/* [31:22] */
+ } psq_bit;
+ };
+
+ /**
+ * @brief adc pdt1 register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t pdt1;
+ struct
+ {
+ __IO uint32_t pdt1 : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } pdt1_bit;
+ };
+
+ /**
+ * @brief adc pdt2 register, offset:0x40
+ */
+ union
+ {
+ __IO uint32_t pdt2;
+ struct
+ {
+ __IO uint32_t pdt2 : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } pdt2_bit;
+ };
+
+ /**
+ * @brief adc pdt3 register, offset:0x44
+ */
+ union
+ {
+ __IO uint32_t pdt3;
+ struct
+ {
+ __IO uint32_t pdt3 : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } pdt3_bit;
+ };
+
+ /**
+ * @brief adc pdt4 register, offset:0x48
+ */
+ union
+ {
+ __IO uint32_t pdt4;
+ struct
+ {
+ __IO uint32_t pdt4 : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } pdt4_bit;
+ };
+
+ /**
+ * @brief adc odt register, offset:0x4C
+ */
+ union
+ {
+ __IO uint32_t odt;
+ struct
+ {
+ __IO uint32_t odt : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } odt_bit;
+ };
+
+ __IO uint32_t reserved1[12];
+
+ /**
+ * @brief adc ovsp register, offset:0x80
+ */
+ union
+ {
+ __IO uint32_t ovsp;
+ struct
+ {
+ __IO uint32_t oosen : 1; /* [0] */
+ __IO uint32_t posen : 1; /* [1] */
+ __IO uint32_t osrsel : 3; /* [4:2] */
+ __IO uint32_t osssel : 4; /* [8:5] */
+ __IO uint32_t oostren : 1; /* [9] */
+ __IO uint32_t oosrsel : 1; /* [10] */
+ __IO uint32_t reserved1 : 21; /* [31:11] */
+ } ovsp_bit;
+ };
+
+ __IO uint32_t reserved2[12];
+
+ /**
+ * @brief adc calval register, offset:0xB4
+ */
+ union
+ {
+ __IO uint32_t calval;
+ struct
+ {
+ __IO uint32_t calval : 7; /* [6:0] */
+ __IO uint32_t reserved1 : 25; /* [31:7] */
+ } calval_bit;
+ };
+} adc_type;
+
+/**
+ * @brief type define adc register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief adc csts register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t csts;
+ struct
+ {
+ __IO uint32_t vmor1 : 1; /* [0] */
+ __IO uint32_t occe1 : 1; /* [1] */
+ __IO uint32_t pcce1 : 1; /* [2] */
+ __IO uint32_t pccs1 : 1; /* [3] */
+ __IO uint32_t occs1 : 1; /* [4] */
+ __IO uint32_t occo1 : 1; /* [5] */
+ __IO uint32_t rdy1 : 1; /* [6] */
+ __IO uint32_t reserved1 : 1; /* [7] */
+ __IO uint32_t vmor2 : 1; /* [8] */
+ __IO uint32_t occe2 : 1; /* [9] */
+ __IO uint32_t pcce2 : 1; /* [10] */
+ __IO uint32_t pccs2 : 1; /* [11] */
+ __IO uint32_t occs2 : 1; /* [12] */
+ __IO uint32_t occo2 : 1; /* [13] */
+ __IO uint32_t rdy2 : 1; /* [14] */
+ __IO uint32_t reserved2 : 1; /* [15] */
+ __IO uint32_t vmor3 : 1; /* [16] */
+ __IO uint32_t occe3 : 1; /* [17] */
+ __IO uint32_t pcce3 : 1; /* [18] */
+ __IO uint32_t pccs3 : 1; /* [19] */
+ __IO uint32_t occs3 : 1; /* [20] */
+ __IO uint32_t occo3 : 1; /* [21] */
+ __IO uint32_t rdy3 : 1; /* [22] */
+ __IO uint32_t reserved3 : 9; /* [31:23] */
+ } csts_bit;
+ };
+
+ /**
+ * @brief adc cctrl register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t cctrl;
+ struct
+ {
+ __IO uint32_t mssel : 5; /* [4_0] */
+ __IO uint32_t reserved1 : 3; /* [7:5] */
+ __IO uint32_t asisel : 4; /* [11:8] */
+ __IO uint32_t reserved2 : 1; /* [12] */
+ __IO uint32_t msdrcen : 1; /* [13] */
+ __IO uint32_t msdmasel_l : 2; /* [15:14] */
+ __IO uint32_t adcdiv : 4; /* [19:16] */
+ __IO uint32_t reserved3 : 2; /* [21:20] */
+ __IO uint32_t vbaten : 1; /* [22] */
+ __IO uint32_t itsrven : 1; /* [23] */
+ __IO uint32_t reserved4 : 4; /* [27:24] */
+ __IO uint32_t msdmasel_h : 1; /* [28] */
+ __IO uint32_t reserved5 : 3; /* [31:29] */
+ } cctrl_bit;
+ };
+
+ /**
+ * @brief adc codt register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t codt;
+ struct
+ {
+ __IO uint32_t codtl : 16; /* [15:0] */
+ __IO uint32_t codth : 16; /* [31:16] */
+ } codt_bit;
+ };
+} adccom_type;
+
+/**
+ * @}
+ */
+
+#define ADC1 ((adc_type *) ADC1_BASE)
+#define ADC2 ((adc_type *) ADC2_BASE)
+#define ADC3 ((adc_type *) ADC3_BASE)
+#define ADCCOM ((adccom_type *) ADCCOM_BASE)
+
+/** @defgroup ADC_exported_functions
+ * @{
+ */
+
+void adc_reset(void);
+void adc_enable(adc_type *adc_x, confirm_state new_state);
+void adc_base_default_para_init(adc_base_config_type *adc_base_struct);
+void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct);
+void adc_common_default_para_init(adc_common_config_type *adc_common_struct);
+void adc_common_config(adc_common_config_type *adc_common_struct);
+void adc_resolution_set(adc_type *adc_x, adc_resolution_type resolution);
+void adc_voltage_battery_enable(confirm_state new_state);
+void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state);
+void adc_dma_request_repeat_enable(adc_type *adc_x, confirm_state new_state);
+void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state);
+void adc_calibration_value_set(adc_type *adc_x, uint8_t adc_calibration_value);
+void adc_calibration_init(adc_type *adc_x);
+flag_status adc_calibration_init_status_get(adc_type *adc_x);
+void adc_calibration_start(adc_type *adc_x);
+flag_status adc_calibration_status_get(adc_type *adc_x);
+void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring);
+void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold);
+void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel);
+void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
+void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght);
+void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
+void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, adc_ordinary_trig_edge_type adc_ordinary_trig_edge);
+void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, adc_preempt_trig_edge_type adc_preempt_trig_edge);
+void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value);
+void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count);
+void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state);
+void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state);
+void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state);
+void adc_conversion_stop(adc_type *adc_x);
+flag_status adc_conversion_stop_status_get(adc_type *adc_x);
+void adc_occe_each_conversion_enable(adc_type *adc_x, confirm_state new_state);
+void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
+flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x);
+void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
+flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x);
+uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
+uint32_t adc_combine_ordinary_conversion_data_get(void);
+uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
+flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
+void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
+void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state);
+void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state);
+void adc_oversample_ratio_shift_set(adc_type *adc_x, adc_oversample_ratio_type adc_oversample_ratio, adc_oversample_shift_type adc_oversample_shift);
+void adc_ordinary_oversample_trig_enable(adc_type *adc_x, confirm_state new_state);
+void adc_ordinary_oversample_restart_set(adc_type *adc_x, adc_ordinary_oversample_restart_type adc_ordinary_oversample_restart);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_can.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_can.h
new file mode 100644
index 0000000..ab47b9c
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_can.h
@@ -0,0 +1,1042 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_can.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 can header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_CAN_H
+#define __AT32F435_437_CAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+
+/** @defgroup CAN_timeout_count
+ * @{
+ */
+
+#define FZC_TIMEOUT ((uint32_t)0x0000FFFF) /*!< time out for fzc bit */
+#define DZC_TIMEOUT ((uint32_t)0x0000FFFF) /*!< time out for dzc bit */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags_definition
+ * @brief can flag
+ * @{
+ */
+
+#define CAN_EAF_FLAG ((uint32_t)0x01) /*!< error active flag */
+#define CAN_EPF_FLAG ((uint32_t)0x02) /*!< error passive flag */
+#define CAN_BOF_FLAG ((uint32_t)0x03) /*!< bus-off flag */
+#define CAN_ETR_FLAG ((uint32_t)0x04) /*!< error type record flag */
+#define CAN_EOIF_FLAG ((uint32_t)0x05) /*!< error occur interrupt flag */
+#define CAN_TM0TCF_FLAG ((uint32_t)0x06) /*!< transmit mailbox 0 transmission completed flag */
+#define CAN_TM1TCF_FLAG ((uint32_t)0x07) /*!< transmit mailbox 1 transmission completed flag */
+#define CAN_TM2TCF_FLAG ((uint32_t)0x08) /*!< transmit mailbox 2 transmission completed flag */
+#define CAN_RF0MN_FLAG ((uint32_t)0x09) /*!< receive fifo 0 message num flag */
+#define CAN_RF0FF_FLAG ((uint32_t)0x0A) /*!< receive fifo 0 full flag */
+#define CAN_RF0OF_FLAG ((uint32_t)0x0B) /*!< receive fifo 0 overflow flag */
+#define CAN_RF1MN_FLAG ((uint32_t)0x0C) /*!< receive fifo 1 message num flag */
+#define CAN_RF1FF_FLAG ((uint32_t)0x0D) /*!< receive fifo 1 full flag */
+#define CAN_RF1OF_FLAG ((uint32_t)0x0E) /*!< receive fifo 1 overflow flag */
+#define CAN_QDZIF_FLAG ((uint32_t)0x0F) /*!< quit doze mode interrupt flag */
+#define CAN_EDZC_FLAG ((uint32_t)0x10) /*!< enter doze mode confirm flag */
+#define CAN_TMEF_FLAG ((uint32_t)0x11) /*!< transmit mailbox empty flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_interrupts_definition
+ * @brief can interrupt
+ * @{
+ */
+
+#define CAN_TCIEN_INT ((uint32_t)0x00000001) /*!< transmission complete interrupt */
+#define CAN_RF0MIEN_INT ((uint32_t)0x00000002) /*!< receive fifo 0 message interrupt */
+#define CAN_RF0FIEN_INT ((uint32_t)0x00000004) /*!< receive fifo 0 full interrupt */
+#define CAN_RF0OIEN_INT ((uint32_t)0x00000008) /*!< receive fifo 0 overflow interrupt */
+#define CAN_RF1MIEN_INT ((uint32_t)0x00000010) /*!< receive fifo 1 message interrupt */
+#define CAN_RF1FIEN_INT ((uint32_t)0x00000020) /*!< receive fifo 1 full interrupt */
+#define CAN_RF1OIEN_INT ((uint32_t)0x00000040) /*!< receive fifo 1 overflow interrupt */
+#define CAN_EAIEN_INT ((uint32_t)0x00000100) /*!< error active interrupt */
+#define CAN_EPIEN_INT ((uint32_t)0x00000200) /*!< error passive interrupt */
+#define CAN_BOIEN_INT ((uint32_t)0x00000400) /*!< bus-off interrupt */
+#define CAN_ETRIEN_INT ((uint32_t)0x00000800) /*!< error type record interrupt */
+#define CAN_EOIEN_INT ((uint32_t)0x00008000) /*!< error occur interrupt */
+#define CAN_QDZIEN_INT ((uint32_t)0x00010000) /*!< quit doze mode interrupt */
+#define CAN_EDZIEN_INT ((uint32_t)0x00020000) /*!< enter doze mode confirm interrupt */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief can flag clear operation macro definition val
+ */
+#define CAN_MSTS_EOIF_VAL ((uint32_t)0x00000004) /*!< eoif bit value, it clear by writing 1 */
+#define CAN_MSTS_QDZIF_VAL ((uint32_t)0x00000008) /*!< qdzif bit value, it clear by writing 1 */
+#define CAN_MSTS_EDZIF_VAL ((uint32_t)0x00000010) /*!< edzif bit value, it clear by writing 1 */
+#define CAN_TSTS_TM0TCF_VAL ((uint32_t)0x00000001) /*!< tm0tcf bit value, it clear by writing 1 */
+#define CAN_TSTS_TM1TCF_VAL ((uint32_t)0x00000100) /*!< tm1tcf bit value, it clear by writing 1 */
+#define CAN_TSTS_TM2TCF_VAL ((uint32_t)0x00010000) /*!< tm2tcf bit value, it clear by writing 1 */
+#define CAN_TSTS_TM0CT_VAL ((uint32_t)0x00000080) /*!< tm0ct bit value, it clear by writing 1 */
+#define CAN_TSTS_TM1CT_VAL ((uint32_t)0x00008000) /*!< tm1ct bit value, it clear by writing 1 */
+#define CAN_TSTS_TM2CT_VAL ((uint32_t)0x00800000) /*!< tm2ct bit value, it clear by writing 1 */
+#define CAN_RF0_RF0FF_VAL ((uint32_t)0x00000008) /*!< rf0ff bit value, it clear by writing 1 */
+#define CAN_RF0_RF0OF_VAL ((uint32_t)0x00000010) /*!< rf0of bit value, it clear by writing 1 */
+#define CAN_RF0_RF0R_VAL ((uint32_t)0x00000020) /*!< rf0r bit value, it clear by writing 1 */
+#define CAN_RF1_RF1FF_VAL ((uint32_t)0x00000008) /*!< rf1ff bit value, it clear by writing 1 */
+#define CAN_RF1_RF1OF_VAL ((uint32_t)0x00000010) /*!< rf1of bit value, it clear by writing 1 */
+#define CAN_RF1_RF1R_VAL ((uint32_t)0x00000020) /*!< rf1r bit value, it clear by writing 1 */
+
+/** @defgroup CAN_exported_types
+ * @{
+ */
+
+/**
+ * @brief can filter fifo
+ */
+typedef enum
+{
+ CAN_FILTER_FIFO0 = 0x00, /*!< filter fifo 0 assignment for filter x */
+ CAN_FILTER_FIFO1 = 0x01 /*!< filter fifo 1 assignment for filter x */
+} can_filter_fifo_type;
+
+/**
+ * @brief can filter mode
+ */
+typedef enum
+{
+ CAN_FILTER_MODE_ID_MASK = 0x00, /*!< identifier mask mode */
+ CAN_FILTER_MODE_ID_LIST = 0x01 /*!< identifier list mode */
+} can_filter_mode_type;
+
+/**
+ * @brief can filter bit width select
+ */
+typedef enum
+{
+ CAN_FILTER_16BIT = 0x00, /*!< two 16-bit filters */
+ CAN_FILTER_32BIT = 0x01 /*!< one 32-bit filter */
+} can_filter_bit_width_type;
+
+/**
+ * @brief can mode
+ */
+typedef enum
+{
+ CAN_MODE_COMMUNICATE = 0x00, /*!< communication mode */
+ CAN_MODE_LOOPBACK = 0x01, /*!< loopback mode */
+ CAN_MODE_LISTENONLY = 0x02, /*!< listen-only mode */
+ CAN_MODE_LISTENONLY_LOOPBACK = 0x03 /*!< loopback combined with listen-only mode */
+} can_mode_type;
+
+/**
+ * @brief can operating mode
+ */
+typedef enum
+{
+ CAN_OPERATINGMODE_FREEZE = 0x00, /*!< freeze mode */
+ CAN_OPERATINGMODE_DOZE = 0x01, /*!< doze mode */
+ CAN_OPERATINGMODE_COMMUNICATE = 0x02 /*!< communication mode */
+} can_operating_mode_type;
+
+/**
+ * @brief can resynchronization adjust width
+ */
+typedef enum
+{
+ CAN_RSAW_1TQ = 0x00, /*!< 1 time quantum */
+ CAN_RSAW_2TQ = 0x01, /*!< 2 time quantum */
+ CAN_RSAW_3TQ = 0x02, /*!< 3 time quantum */
+ CAN_RSAW_4TQ = 0x03 /*!< 4 time quantum */
+} can_rsaw_type;
+
+/**
+ * @brief can bit time segment 1
+ */
+typedef enum
+{
+ CAN_BTS1_1TQ = 0x00, /*!< 1 time quantum */
+ CAN_BTS1_2TQ = 0x01, /*!< 2 time quantum */
+ CAN_BTS1_3TQ = 0x02, /*!< 3 time quantum */
+ CAN_BTS1_4TQ = 0x03, /*!< 4 time quantum */
+ CAN_BTS1_5TQ = 0x04, /*!< 5 time quantum */
+ CAN_BTS1_6TQ = 0x05, /*!< 6 time quantum */
+ CAN_BTS1_7TQ = 0x06, /*!< 7 time quantum */
+ CAN_BTS1_8TQ = 0x07, /*!< 8 time quantum */
+ CAN_BTS1_9TQ = 0x08, /*!< 9 time quantum */
+ CAN_BTS1_10TQ = 0x09, /*!< 10 time quantum */
+ CAN_BTS1_11TQ = 0x0A, /*!< 11 time quantum */
+ CAN_BTS1_12TQ = 0x0B, /*!< 12 time quantum */
+ CAN_BTS1_13TQ = 0x0C, /*!< 13 time quantum */
+ CAN_BTS1_14TQ = 0x0D, /*!< 14 time quantum */
+ CAN_BTS1_15TQ = 0x0E, /*!< 15 time quantum */
+ CAN_BTS1_16TQ = 0x0F /*!< 16 time quantum */
+} can_bts1_type;
+
+/**
+ * @brief can bit time segment 2
+ */
+typedef enum
+{
+ CAN_BTS2_1TQ = 0x00, /*!< 1 time quantum */
+ CAN_BTS2_2TQ = 0x01, /*!< 2 time quantum */
+ CAN_BTS2_3TQ = 0x02, /*!< 3 time quantum */
+ CAN_BTS2_4TQ = 0x03, /*!< 4 time quantum */
+ CAN_BTS2_5TQ = 0x04, /*!< 5 time quantum */
+ CAN_BTS2_6TQ = 0x05, /*!< 6 time quantum */
+ CAN_BTS2_7TQ = 0x06, /*!< 7 time quantum */
+ CAN_BTS2_8TQ = 0x07 /*!< 8 time quantum */
+} can_bts2_type;
+
+/**
+ * @brief can identifier type
+ */
+typedef enum
+{
+ CAN_ID_STANDARD = 0x00, /*!< standard Id */
+ CAN_ID_EXTENDED = 0x01 /*!< extended Id */
+} can_identifier_type;
+
+/**
+ * @brief can transmission frame type
+ */
+typedef enum
+{
+ CAN_TFT_DATA = 0x00, /*!< data frame */
+ CAN_TFT_REMOTE = 0x01 /*!< remote frame */
+} can_trans_frame_type;
+
+/**
+ * @brief can tx mailboxes
+ */
+typedef enum
+{
+ CAN_TX_MAILBOX0 = 0x00, /*!< can tx mailbox 0 */
+ CAN_TX_MAILBOX1 = 0x01, /*!< can tx mailbox 1 */
+ CAN_TX_MAILBOX2 = 0x02 /*!< can tx mailbox 2 */
+} can_tx_mailbox_num_type;
+
+/**
+ * @brief can receive fifo
+ */
+typedef enum
+{
+ CAN_RX_FIFO0 = 0x00, /*!< can fifo 0 used to receive */
+ CAN_RX_FIFO1 = 0x01 /*!< can fifo 1 used to receive */
+} can_rx_fifo_num_type;
+
+/**
+ * @brief can transmit status
+ */
+typedef enum
+{
+ CAN_TX_STATUS_FAILED = 0x00, /*!< can transmission failed */
+ CAN_TX_STATUS_SUCCESSFUL = 0x01, /*!< can transmission successful */
+ CAN_TX_STATUS_PENDING = 0x02, /*!< can transmission pending */
+ CAN_TX_STATUS_NO_EMPTY = 0x04 /*!< can transmission no empty mailbox */
+} can_transmit_status_type;
+
+/**
+ * @brief can enter doze mode status
+ */
+typedef enum
+{
+ CAN_ENTER_DOZE_FAILED = 0x00, /*!< can enter the doze mode failed */
+ CAN_ENTER_DOZE_SUCCESSFUL = 0x01 /*!< can enter the doze mode successful */
+} can_enter_doze_status_type;
+
+/**
+ * @brief can quit doze mode status
+ */
+typedef enum
+{
+ CAN_QUIT_DOZE_FAILED = 0x00, /*!< can quit doze mode failed */
+ CAN_QUIT_DOZE_SUCCESSFUL = 0x01 /*!< can quit doze mode successful */
+} can_quit_doze_status_type;
+
+/**
+ * @brief can message discarding rule select when overflow
+ */
+typedef enum
+{
+ CAN_DISCARDING_FIRST_RECEIVED = 0x00, /*!< can discarding the first received message */
+ CAN_DISCARDING_LAST_RECEIVED = 0x01 /*!< can discarding the last received message */
+} can_msg_discarding_rule_type;
+
+/**
+ * @brief can multiple message sending sequence rule
+ */
+typedef enum
+{
+ CAN_SENDING_BY_ID = 0x00, /*!< can sending the minimum id message first*/
+ CAN_SENDING_BY_REQUEST = 0x01 /*!< can sending the first request message first */
+} can_msg_sending_rule_type;
+
+/**
+ * @brief can error type record
+ */
+typedef enum
+{
+ CAN_ERRORRECORD_NOERR = 0x00, /*!< no error */
+ CAN_ERRORRECORD_STUFFERR = 0x01, /*!< stuff error */
+ CAN_ERRORRECORD_FORMERR = 0x02, /*!< form error */
+ CAN_ERRORRECORD_ACKERR = 0x03, /*!< acknowledgment error */
+ CAN_ERRORRECORD_BITRECESSIVEERR = 0x04, /*!< bit recessive error */
+ CAN_ERRORRECORD_BITDOMINANTERR = 0x05, /*!< bit dominant error */
+ CAN_ERRORRECORD_CRCERR = 0x06, /*!< crc error */
+ CAN_ERRORRECORD_SOFTWARESETERR = 0x07 /*!< software set error */
+} can_error_record_type;
+
+/**
+ * @brief can init structure definition
+ */
+typedef struct
+{
+ can_mode_type mode_selection; /*!< specifies the can mode.*/
+
+ confirm_state ttc_enable; /*!< time triggered communication mode enable */
+
+ confirm_state aebo_enable; /*!< automatic exit bus-off enable */
+
+ confirm_state aed_enable; /*!< automatic exit doze mode enable */
+
+ confirm_state prsf_enable; /*!< prohibit retransmission when sending fails enable */
+
+ can_msg_discarding_rule_type mdrsel_selection; /*!< message discarding rule select when overflow */
+
+ can_msg_sending_rule_type mmssr_selection; /*!< multiple message sending sequence rule */
+
+} can_base_type;
+
+/**
+ * @brief can baudrate structure definition
+ */
+typedef struct
+{
+ uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x400.*/
+
+ can_rsaw_type rsaw_size; /*!< resynchronization adjust width */
+
+ can_bts1_type bts1_size; /*!< bit time segment 1 */
+
+ can_bts2_type bts2_size; /*!< bit time segment 2 */
+
+} can_baudrate_type;
+
+/**
+ * @brief can filter init structure definition
+ */
+typedef struct
+{
+ confirm_state filter_activate_enable; /*!< enable or disable the filter activate.*/
+
+ can_filter_mode_type filter_mode; /*!< config the filter mode mask or list.*/
+
+ can_filter_fifo_type filter_fifo; /*!< config the fifo which will be assigned to the filter. */
+
+ uint8_t filter_number; /*!< config the filter number, parameter ranges from 0 to 13. */
+
+ can_filter_bit_width_type filter_bit; /*!< config the filter bit width 16bit or 32bit.*/
+
+ uint16_t filter_id_high; /*!< config the filter identification, for 32-bit configuration
+ it's high 16 bits, for 16-bit configuration it's first. */
+
+ uint16_t filter_id_low; /*!< config the filter identification, for 32-bit configuration
+ it's low 16 bits, for 16-bit configuration it's second. */
+
+ uint16_t filter_mask_high; /*!< config the filter mask or identification, according to the filtering mode,
+ for 32-bit configuration it's high 16 bits, for 16-bit configuration it's first. */
+
+ uint16_t filter_mask_low; /*!< config the filter mask or identification, according to the filtering mode,
+ for 32-bit configuration it's low 16 bits, for 16-bit configuration it's second. */
+} can_filter_init_type;
+
+/**
+ * @brief can tx message structure definition
+ */
+typedef struct
+{
+ uint32_t standard_id; /*!< specifies the 11 bits standard identifier.
+ this parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t extended_id; /*!< specifies the 29 bits extended identifier.
+ this parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ can_identifier_type id_type; /*!< specifies identifier type for the transmit message.*/
+
+ can_trans_frame_type frame_type; /*!< specifies frame type for the transmit message.*/
+
+ uint8_t dlc; /*!< specifies frame data length that will be transmitted.
+ this parameter can be a value between 0 to 8 */
+
+ uint8_t data[8]; /*!< contains the transmit data. it ranges from 0 to 0xFF. */
+
+} can_tx_message_type;
+
+/**
+ * @brief can rx message structure definition
+ */
+typedef struct
+{
+ uint32_t standard_id; /*!< specifies the 11 bits standard identifier
+ this parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t extended_id; /*!< specifies the 29 bits extended identifier.
+ this parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ can_identifier_type id_type; /*!< specifies identifier type for the receive message.*/
+
+ can_trans_frame_type frame_type; /*!< specifies frame type for the receive message.*/
+
+ uint8_t dlc; /*!< specifies the frame data length that will be received.
+ this parameter can be a value between 0 to 8 */
+
+ uint8_t data[8]; /*!< contains the receive data. it ranges from 0 to 0xFF.*/
+
+ uint8_t filter_index; /*!< specifies the message stored in which filter
+ this parameter can be a value between 0 to 0xFF */
+} can_rx_message_type;
+
+/**
+ * @brief can controller area network tx mailbox
+ */
+typedef struct
+{
+ /**
+ * @brief can tmi register
+ */
+ union
+ {
+ __IO uint32_t tmi;
+ struct
+ {
+ __IO uint32_t tmsr : 1; /* [0] */
+ __IO uint32_t tmfrsel : 1; /* [1] */
+ __IO uint32_t tmidsel : 1; /* [2] */
+ __IO uint32_t tmeid : 18;/* [20:3] */
+ __IO uint32_t tmsid : 11;/* [31:21] */
+ } tmi_bit;
+ };
+
+ /**
+ * @brief can tmc register
+ */
+ union
+ {
+ __IO uint32_t tmc;
+ struct
+ {
+ __IO uint32_t tmdtbl : 4; /* [3:0] */
+ __IO uint32_t reserved1 : 4; /* [7:4] */
+ __IO uint32_t tmtsten : 1; /* [8] */
+ __IO uint32_t reserved2 : 7; /* [15:9] */
+ __IO uint32_t tmts : 16;/* [31:16] */
+ } tmc_bit;
+ };
+
+ /**
+ * @brief can tmdtl register
+ */
+ union
+ {
+ __IO uint32_t tmdtl;
+ struct
+ {
+ __IO uint32_t tmdt0 : 8; /* [7:0] */
+ __IO uint32_t tmdt1 : 8; /* [15:8] */
+ __IO uint32_t tmdt2 : 8; /* [23:16] */
+ __IO uint32_t tmdt3 : 8; /* [31:24] */
+ } tmdtl_bit;
+ };
+
+ /**
+ * @brief can tmdth register
+ */
+ union
+ {
+ __IO uint32_t tmdth;
+ struct
+ {
+ __IO uint32_t tmdt4 : 8; /* [7:0] */
+ __IO uint32_t tmdt5 : 8; /* [15:8] */
+ __IO uint32_t tmdt6 : 8; /* [23:16] */
+ __IO uint32_t tmdt7 : 8; /* [31:24] */
+ } tmdth_bit;
+ };
+} can_tx_mailbox_type;
+
+/**
+ * @brief can controller area network fifo mailbox
+ */
+typedef struct
+{
+ /**
+ * @brief can rfi register
+ */
+ union
+ {
+ __IO uint32_t rfi;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t rffri : 1; /* [1] */
+ __IO uint32_t rfidi : 1; /* [2] */
+ __IO uint32_t rfeid : 18;/* [20:3] */
+ __IO uint32_t rfsid : 11;/* [31:21] */
+ } rfi_bit;
+ };
+
+ /**
+ * @brief can rfc register
+ */
+ union
+ {
+ __IO uint32_t rfc;
+ struct
+ {
+ __IO uint32_t rfdtl : 4; /* [3:0] */
+ __IO uint32_t reserved1 : 4; /* [7:4] */
+ __IO uint32_t rffmn : 8; /* [15:8] */
+ __IO uint32_t rfts : 16;/* [31:16] */
+ } rfc_bit;
+ };
+
+ /**
+ * @brief can rfdtl register
+ */
+ union
+ {
+ __IO uint32_t rfdtl;
+ struct
+ {
+ __IO uint32_t rfdt0 : 8; /* [7:0] */
+ __IO uint32_t rfdt1 : 8; /* [15:8] */
+ __IO uint32_t rfdt2 : 8; /* [23:16] */
+ __IO uint32_t rfdt3 : 8; /* [31:24] */
+ } rfdtl_bit;
+ };
+
+ /**
+ * @brief can rfdth register
+ */
+ union
+ {
+ __IO uint32_t rfdth;
+ struct
+ {
+ __IO uint32_t rfdt4 : 8; /* [7:0] */
+ __IO uint32_t rfdt5 : 8; /* [15:8] */
+ __IO uint32_t rfdt6 : 8; /* [23:16] */
+ __IO uint32_t rfdt7 : 8; /* [31:24] */
+ } rfdth_bit;
+ };
+} can_fifo_mailbox_type;
+
+/**
+ * @brief can controller area network filter bit register
+ */
+typedef struct
+{
+ __IO uint32_t ffdb1;
+ __IO uint32_t ffdb2;
+} can_filter_register_type;
+
+/**
+ * @brief type define can register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief can mctrl register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t mctrl;
+ struct
+ {
+ __IO uint32_t fzen : 1; /* [0] */
+ __IO uint32_t dzen : 1; /* [1] */
+ __IO uint32_t mmssr : 1; /* [2] */
+ __IO uint32_t mdrsel : 1; /* [3] */
+ __IO uint32_t prsfen : 1; /* [4] */
+ __IO uint32_t aeden : 1; /* [5] */
+ __IO uint32_t aeboen : 1; /* [6] */
+ __IO uint32_t ttcen : 1; /* [7] */
+ __IO uint32_t reserved1 : 7; /* [14:8] */
+ __IO uint32_t sprst : 1; /* [15] */
+ __IO uint32_t ptd : 1; /* [16] */
+ __IO uint32_t reserved2 : 15;/*[31:17] */
+ } mctrl_bit;
+ };
+
+ /**
+ * @brief can msts register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t msts;
+ struct
+ {
+ __IO uint32_t fzc : 1; /* [0] */
+ __IO uint32_t dzc : 1; /* [1] */
+ __IO uint32_t eoif : 1; /* [2] */
+ __IO uint32_t qdzif : 1; /* [3] */
+ __IO uint32_t edzif : 1; /* [4] */
+ __IO uint32_t reserved1 : 3; /* [7:5] */
+ __IO uint32_t cuss : 1; /* [8] */
+ __IO uint32_t curs : 1; /* [9] */
+ __IO uint32_t lsamprx : 1; /* [10] */
+ __IO uint32_t realrx : 1; /* [11] */
+ __IO uint32_t reserved2 : 20;/*[31:12] */
+ } msts_bit;
+ };
+
+ /**
+ * @brief can tsts register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t tsts;
+ struct
+ {
+ __IO uint32_t tm0tcf : 1; /* [0] */
+ __IO uint32_t tm0tsf : 1; /* [1] */
+ __IO uint32_t tm0alf : 1; /* [2] */
+ __IO uint32_t tm0tef : 1; /* [3] */
+ __IO uint32_t reserved1 : 3; /* [6:4] */
+ __IO uint32_t tm0ct : 1; /* [7] */
+ __IO uint32_t tm1tcf : 1; /* [8] */
+ __IO uint32_t tm1tsf : 1; /* [9] */
+ __IO uint32_t tm1alf : 1; /* [10] */
+ __IO uint32_t tm1tef : 1; /* [11] */
+ __IO uint32_t reserved2 : 3; /* [14:12] */
+ __IO uint32_t tm1ct : 1; /* [15] */
+ __IO uint32_t tm2tcf : 1; /* [16] */
+ __IO uint32_t tm2tsf : 1; /* [17] */
+ __IO uint32_t tm2alf : 1; /* [18] */
+ __IO uint32_t tm2tef : 1; /* [19] */
+ __IO uint32_t reserved3 : 3; /* [22:20] */
+ __IO uint32_t tm2ct : 1; /* [23] */
+ __IO uint32_t tmnr : 2; /* [25:24] */
+ __IO uint32_t tm0ef : 1; /* [26] */
+ __IO uint32_t tm1ef : 1; /* [27] */
+ __IO uint32_t tm2ef : 1; /* [28] */
+ __IO uint32_t tm0lpf : 1; /* [29] */
+ __IO uint32_t tm1lpf : 1; /* [30] */
+ __IO uint32_t tm2lpf : 1; /* [31] */
+ } tsts_bit;
+ };
+
+ /**
+ * @brief can rf0 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t rf0;
+ struct
+ {
+ __IO uint32_t rf0mn : 2; /* [1:0] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t rf0ff : 1; /* [3] */
+ __IO uint32_t rf0of : 1; /* [4] */
+ __IO uint32_t rf0r : 1; /* [5] */
+ __IO uint32_t reserved2 : 26;/* [31:6] */
+ } rf0_bit;
+ };
+
+ /**
+ * @brief can rf1 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t rf1;
+ struct
+ {
+ __IO uint32_t rf1mn : 2; /* [1:0] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t rf1ff : 1; /* [3] */
+ __IO uint32_t rf1of : 1; /* [4] */
+ __IO uint32_t rf1r : 1; /* [5] */
+ __IO uint32_t reserved2 : 26;/* [31:6] */
+ } rf1_bit;
+ };
+
+ /**
+ * @brief can inten register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t inten;
+ struct
+ {
+ __IO uint32_t tcien : 1; /* [0] */
+ __IO uint32_t rf0mien : 1; /* [1] */
+ __IO uint32_t rf0fien : 1; /* [2] */
+ __IO uint32_t rf0oien : 1; /* [3] */
+ __IO uint32_t rf1mien : 1; /* [4] */
+ __IO uint32_t rf1fien : 1; /* [5] */
+ __IO uint32_t rf1oien : 1; /* [6] */
+ __IO uint32_t reserved1 : 1; /* [7] */
+ __IO uint32_t eaien : 1; /* [8] */
+ __IO uint32_t epien : 1; /* [9] */
+ __IO uint32_t boien : 1; /* [10] */
+ __IO uint32_t etrien : 1; /* [11] */
+ __IO uint32_t reserved2 : 3; /* [14:12] */
+ __IO uint32_t eoien : 1; /* [15] */
+ __IO uint32_t qdzien : 1; /* [16] */
+ __IO uint32_t edzien : 1; /* [17] */
+ __IO uint32_t reserved3 : 14;/* [31:18] */
+ } inten_bit;
+ };
+
+ /**
+ * @brief can ests register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t ests;
+ struct
+ {
+ __IO uint32_t eaf : 1; /* [0] */
+ __IO uint32_t epf : 1; /* [1] */
+ __IO uint32_t bof : 1; /* [2] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t etr : 3; /* [6:4] */
+ __IO uint32_t reserved2 : 9; /* [15:7] */
+ __IO uint32_t tec : 8; /* [23:16] */
+ __IO uint32_t rec : 8; /* [31:24] */
+ } ests_bit;
+ };
+
+ /**
+ * @brief can btmg register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t btmg;
+ struct
+ {
+ __IO uint32_t brdiv : 12;/* [11:0] */
+ __IO uint32_t reserved1 : 4; /* [15:12] */
+ __IO uint32_t bts1 : 4; /* [19:16] */
+ __IO uint32_t bts2 : 3; /* [22:20] */
+ __IO uint32_t reserved2 : 1; /* [23] */
+ __IO uint32_t rsaw : 2; /* [25:24] */
+ __IO uint32_t reserved3 : 4; /* [29:26] */
+ __IO uint32_t lben : 1; /* [30] */
+ __IO uint32_t loen : 1; /* [31] */
+ } btmg_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0x20~0x17C
+ */
+ __IO uint32_t reserved1[88];
+
+ /**
+ * @brief can controller area network tx mailbox register, offset:0x180~0x1AC
+ */
+ can_tx_mailbox_type tx_mailbox[3];
+
+ /**
+ * @brief can controller area network fifo mailbox register, offset:0x1B0~0x1CC
+ */
+ can_fifo_mailbox_type fifo_mailbox[2];
+
+ /**
+ * @brief can reserved register, offset:0x1D0~0x1FC
+ */
+ __IO uint32_t reserved2[12];
+
+ /**
+ * @brief can fctrl register, offset:0x200
+ */
+ union
+ {
+ __IO uint32_t fctrl;
+ struct
+ {
+ __IO uint32_t fcs : 1; /* [0] */
+ __IO uint32_t reserved1 : 31;/* [31:1] */
+ } fctrl_bit;
+ };
+
+ /**
+ * @brief can fmcfg register, offset:0x204
+ */
+ union
+ {
+ __IO uint32_t fmcfg;
+ struct
+ {
+ __IO uint32_t fmsel0 : 1; /* [0] */
+ __IO uint32_t fmsel1 : 1; /* [1] */
+ __IO uint32_t fmsel2 : 1; /* [2] */
+ __IO uint32_t fmsel3 : 1; /* [3] */
+ __IO uint32_t fmsel4 : 1; /* [4] */
+ __IO uint32_t fmsel5 : 1; /* [5] */
+ __IO uint32_t fmsel6 : 1; /* [6] */
+ __IO uint32_t fmsel7 : 1; /* [7] */
+ __IO uint32_t fmsel8 : 1; /* [8] */
+ __IO uint32_t fmsel9 : 1; /* [9] */
+ __IO uint32_t fmsel10 : 1; /* [10] */
+ __IO uint32_t fmsel11 : 1; /* [11] */
+ __IO uint32_t fmsel12 : 1; /* [12] */
+ __IO uint32_t fmsel13 : 1; /* [13] */
+ __IO uint32_t fmsel14 : 1; /* [14] */
+ __IO uint32_t fmsel15 : 1; /* [15] */
+ __IO uint32_t fmsel16 : 1; /* [16] */
+ __IO uint32_t fmsel17 : 1; /* [17] */
+ __IO uint32_t fmsel18 : 1; /* [18] */
+ __IO uint32_t fmsel19 : 1; /* [19] */
+ __IO uint32_t fmsel20 : 1; /* [20] */
+ __IO uint32_t fmsel21 : 1; /* [21] */
+ __IO uint32_t fmsel22 : 1; /* [22] */
+ __IO uint32_t fmsel23 : 1; /* [23] */
+ __IO uint32_t fmsel24 : 1; /* [24] */
+ __IO uint32_t fmsel25 : 1; /* [25] */
+ __IO uint32_t fmsel26 : 1; /* [26] */
+ __IO uint32_t fmsel27 : 1; /* [27] */
+ __IO uint32_t reserved1 : 4;/* [31:28] */
+ } fmcfg_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0x208
+ */
+ __IO uint32_t reserved3;
+
+ /**
+ * @brief can fbwcfg register, offset:0x20C
+ */
+ union
+ {
+ __IO uint32_t fbwcfg;
+ struct
+ {
+ __IO uint32_t fbwsel0 : 1; /* [0] */
+ __IO uint32_t fbwsel1 : 1; /* [1] */
+ __IO uint32_t fbwsel2 : 1; /* [2] */
+ __IO uint32_t fbwsel3 : 1; /* [3] */
+ __IO uint32_t fbwsel4 : 1; /* [4] */
+ __IO uint32_t fbwsel5 : 1; /* [5] */
+ __IO uint32_t fbwsel6 : 1; /* [6] */
+ __IO uint32_t fbwsel7 : 1; /* [7] */
+ __IO uint32_t fbwsel8 : 1; /* [8] */
+ __IO uint32_t fbwsel9 : 1; /* [9] */
+ __IO uint32_t fbwsel10 : 1; /* [10] */
+ __IO uint32_t fbwsel11 : 1; /* [11] */
+ __IO uint32_t fbwsel12 : 1; /* [12] */
+ __IO uint32_t fbwsel13 : 1; /* [13] */
+ __IO uint32_t fbwsel14 : 1; /* [14] */
+ __IO uint32_t fbwsel15 : 1; /* [15] */
+ __IO uint32_t fbwsel16 : 1; /* [16] */
+ __IO uint32_t fbwsel17 : 1; /* [17] */
+ __IO uint32_t fbwsel18 : 1; /* [18] */
+ __IO uint32_t fbwsel19 : 1; /* [19] */
+ __IO uint32_t fbwsel20 : 1; /* [20] */
+ __IO uint32_t fbwsel21 : 1; /* [21] */
+ __IO uint32_t fbwsel22 : 1; /* [22] */
+ __IO uint32_t fbwsel23 : 1; /* [23] */
+ __IO uint32_t fbwsel24 : 1; /* [24] */
+ __IO uint32_t fbwsel25 : 1; /* [25] */
+ __IO uint32_t fbwsel26 : 1; /* [26] */
+ __IO uint32_t fbwsel27 : 1; /* [27] */
+ __IO uint32_t reserved1 : 4;/* [31:28] */
+ } fbwcfg_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0x210
+ */
+ __IO uint32_t reserved4;
+
+ /**
+ * @brief can frf register, offset:0x214
+ */
+ union
+ {
+ __IO uint32_t frf;
+ struct
+ {
+ __IO uint32_t frfsel0 : 1; /* [0] */
+ __IO uint32_t frfsel1 : 1; /* [1] */
+ __IO uint32_t frfsel2 : 1; /* [2] */
+ __IO uint32_t frfsel3 : 1; /* [3] */
+ __IO uint32_t frfsel4 : 1; /* [4] */
+ __IO uint32_t frfsel5 : 1; /* [5] */
+ __IO uint32_t frfsel6 : 1; /* [6] */
+ __IO uint32_t frfsel7 : 1; /* [7] */
+ __IO uint32_t frfsel8 : 1; /* [8] */
+ __IO uint32_t frfsel9 : 1; /* [9] */
+ __IO uint32_t frfsel10 : 1; /* [10] */
+ __IO uint32_t frfsel11 : 1; /* [11] */
+ __IO uint32_t frfsel12 : 1; /* [12] */
+ __IO uint32_t frfsel13 : 1; /* [13] */
+ __IO uint32_t frfsel14 : 1; /* [14] */
+ __IO uint32_t frfsel15 : 1; /* [15] */
+ __IO uint32_t frfsel16 : 1; /* [16] */
+ __IO uint32_t frfsel17 : 1; /* [17] */
+ __IO uint32_t frfsel18 : 1; /* [18] */
+ __IO uint32_t frfsel19 : 1; /* [19] */
+ __IO uint32_t frfsel20 : 1; /* [20] */
+ __IO uint32_t frfsel21 : 1; /* [21] */
+ __IO uint32_t frfsel22 : 1; /* [22] */
+ __IO uint32_t frfsel23 : 1; /* [23] */
+ __IO uint32_t frfsel24 : 1; /* [24] */
+ __IO uint32_t frfsel25 : 1; /* [25] */
+ __IO uint32_t frfsel26 : 1; /* [26] */
+ __IO uint32_t frfsel27 : 1; /* [27] */
+ __IO uint32_t reserved1 : 4;/* [31:28] */
+ } frf_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0x218
+ */
+ __IO uint32_t reserved5;
+
+ /**
+ * @brief can facfg register, offset:0x21C
+ */
+ union
+ {
+ __IO uint32_t facfg;
+ struct
+ {
+ __IO uint32_t faen0 : 1; /* [0] */
+ __IO uint32_t faen1 : 1; /* [1] */
+ __IO uint32_t faen2 : 1; /* [2] */
+ __IO uint32_t faen3 : 1; /* [3] */
+ __IO uint32_t faen4 : 1; /* [4] */
+ __IO uint32_t faen5 : 1; /* [5] */
+ __IO uint32_t faen6 : 1; /* [6] */
+ __IO uint32_t faen7 : 1; /* [7] */
+ __IO uint32_t faen8 : 1; /* [8] */
+ __IO uint32_t faen9 : 1; /* [9] */
+ __IO uint32_t faen10 : 1; /* [10] */
+ __IO uint32_t faen11 : 1; /* [11] */
+ __IO uint32_t faen12 : 1; /* [12] */
+ __IO uint32_t faen13 : 1; /* [13] */
+ __IO uint32_t faen14 : 1; /* [14] */
+ __IO uint32_t faen15 : 1; /* [15] */
+ __IO uint32_t faen16 : 1; /* [16] */
+ __IO uint32_t faen17 : 1; /* [17] */
+ __IO uint32_t faen18 : 1; /* [18] */
+ __IO uint32_t faen19 : 1; /* [19] */
+ __IO uint32_t faen20 : 1; /* [20] */
+ __IO uint32_t faen21 : 1; /* [21] */
+ __IO uint32_t faen22 : 1; /* [22] */
+ __IO uint32_t faen23 : 1; /* [23] */
+ __IO uint32_t faen24 : 1; /* [24] */
+ __IO uint32_t faen25 : 1; /* [25] */
+ __IO uint32_t faen26 : 1; /* [26] */
+ __IO uint32_t faen27 : 1; /* [27] */
+ __IO uint32_t reserved1 : 4;/* [31:28] */
+ } facfg_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0x220~0x23C
+ */
+ __IO uint32_t reserved6[8];
+
+ /**
+ * @brief can ffb register, offset:0x240~0x2AC
+ */
+ can_filter_register_type ffb[28];
+} can_type;
+
+/**
+ * @}
+ */
+
+#define CAN1 ((can_type *) CAN1_BASE)
+#define CAN2 ((can_type *) CAN2_BASE)
+
+/** @defgroup CAN_exported_functions
+ * @{
+ */
+
+void can_reset(can_type* can_x);
+void can_baudrate_default_para_init(can_baudrate_type* can_baudrate_struct);
+error_status can_baudrate_set(can_type* can_x, can_baudrate_type* can_baudrate_struct);
+void can_default_para_init(can_base_type* can_base_struct);
+error_status can_base_init(can_type* can_x, can_base_type* can_base_struct);
+void can_filter_default_para_init(can_filter_init_type* can_filter_init_struct);
+void can_filter_init(can_type* can_x, can_filter_init_type* can_filter_init_struct);
+void can_debug_transmission_prohibit(can_type* can_x, confirm_state new_state);
+void can_ttc_mode_enable(can_type* can_x, confirm_state new_state);
+uint8_t can_message_transmit(can_type* can_x, can_tx_message_type* tx_message_struct);
+can_transmit_status_type can_transmit_status_get(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
+void can_transmit_cancel(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
+void can_message_receive(can_type* can_x, can_rx_fifo_num_type fifo_number, can_rx_message_type* rx_message_struct);
+void can_receive_fifo_release(can_type* can_x, can_rx_fifo_num_type fifo_number);
+uint8_t can_receive_message_pending_get(can_type* can_x, can_rx_fifo_num_type fifo_number);
+error_status can_operating_mode_set(can_type* can_x, can_operating_mode_type can_operating_mode);
+can_enter_doze_status_type can_doze_mode_enter(can_type* can_x);
+can_quit_doze_status_type can_doze_mode_exit(can_type* can_x);
+can_error_record_type can_error_type_record_get(can_type* can_x);
+uint8_t can_receive_error_counter_get(can_type* can_x);
+uint8_t can_transmit_error_counter_get(can_type* can_x);
+void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state);
+flag_status can_flag_get(can_type* can_x, uint32_t can_flag);
+void can_flag_clear(can_type* can_x, uint32_t can_flag);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_crc.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_crc.h
new file mode 100644
index 0000000..6fdadc8
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_crc.h
@@ -0,0 +1,172 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_crc.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 crc header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_CRC_H
+#define __AT32F435_437_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/** @defgroup CRC_exported_types
+ * @{
+ */
+
+/**
+ * @brief crc reverse input data
+ */
+typedef enum
+{
+ CRC_REVERSE_INPUT_NO_AFFECTE = 0x00, /*!< input data no reverse */
+ CRC_REVERSE_INPUT_BY_BYTE = 0x01, /*!< input data reverse by byte */
+ CRC_REVERSE_INPUT_BY_HALFWORD = 0x02, /*!< input data reverse by half word */
+ CRC_REVERSE_INPUT_BY_WORD = 0x03 /*!< input data reverse by word */
+} crc_reverse_input_type;
+
+/**
+ * @brief crc reverse output data
+ */
+typedef enum
+{
+ CRC_REVERSE_OUTPUT_NO_AFFECTE = 0x00, /*!< output data no reverse */
+ CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */
+} crc_reverse_output_type;
+
+/**
+ * @brief type define crc register all
+ */
+typedef struct
+{
+ /**
+ * @brief crc dt register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t dt;
+ struct
+ {
+ __IO uint32_t dt : 32; /* [31:0] */
+ } dt_bit;
+ };
+
+ /**
+ * @brief crc cdt register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t cdt;
+ struct
+ {
+ __IO uint32_t cdt : 8 ; /* [7:0] */
+ __IO uint32_t reserved1 : 24 ;/* [31:8] */
+ } cdt_bit;
+ };
+
+ /**
+ * @brief crc ctrl register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t rst : 1 ; /* [0] */
+ __IO uint32_t reserved1 : 4 ; /* [4:1] */
+ __IO uint32_t revid : 2 ; /* [6:5] */
+ __IO uint32_t revod : 1 ; /* [7] */
+ __IO uint32_t reserved2 : 24 ;/* [31:8] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief crm reserved1 register, offset:0x0C
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief crc idt register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t idt;
+ struct
+ {
+ __IO uint32_t idt : 32; /* [31:0] */
+ } idt_bit;
+ };
+
+} crc_type;
+
+/**
+ * @}
+ */
+
+#define CRC ((crc_type *) CRC_BASE)
+
+/** @defgroup CRC_exported_functions
+ * @{
+ */
+
+void crc_data_reset(void);
+uint32_t crc_one_word_calculate(uint32_t data);
+uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length);
+uint32_t crc_data_get(void);
+void crc_common_data_set(uint8_t cdt_value);
+uint8_t crc_common_date_get(void);
+void crc_init_data_set(uint32_t value);
+void crc_reverse_input_data_set(crc_reverse_input_type value);
+void crc_reverse_output_data_set(crc_reverse_output_type value);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_crm.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_crm.h
new file mode 100644
index 0000000..01833a9
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_crm.h
@@ -0,0 +1,1565 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_crm.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 crm header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_CRM_H
+#define __AT32F435_437_CRM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup CRM
+ * @{
+ */
+
+#define CRM_REG(value) PERIPH_REG(CRM_BASE, value)
+#define CRM_REG_BIT(value) PERIPH_REG_BIT(value)
+
+/** @defgroup CRM_flags_definition
+ * @brief crm flag
+ * @{
+ */
+
+#define CRM_HICK_STABLE_FLAG MAKE_VALUE(0x00, 1) /*!< high speed internal clock stable flag */
+#define CRM_HEXT_STABLE_FLAG MAKE_VALUE(0x00, 17) /*!< high speed external crystal stable flag */
+#define CRM_PLL_STABLE_FLAG MAKE_VALUE(0x00, 25) /*!< phase locking loop stable flag */
+#define CRM_LEXT_STABLE_FLAG MAKE_VALUE(0x70, 1) /*!< low speed external crystal stable flag */
+#define CRM_LICK_STABLE_FLAG MAKE_VALUE(0x74, 1) /*!< low speed internal clock stable flag */
+#define CRM_NRST_RESET_FLAG MAKE_VALUE(0x74, 26) /*!< nrst pin reset flag */
+#define CRM_POR_RESET_FLAG MAKE_VALUE(0x74, 27) /*!< power on reset flag */
+#define CRM_SW_RESET_FLAG MAKE_VALUE(0x74, 28) /*!< software reset flag */
+#define CRM_WDT_RESET_FLAG MAKE_VALUE(0x74, 29) /*!< watchdog timer reset flag */
+#define CRM_WWDT_RESET_FLAG MAKE_VALUE(0x74, 30) /*!< window watchdog timer reset flag */
+#define CRM_LOWPOWER_RESET_FLAG MAKE_VALUE(0x74, 31) /*!< low-power reset flag */
+#define CRM_LICK_READY_INT_FLAG MAKE_VALUE(0x0C, 0) /*!< low speed internal clock stable interrupt ready flag */
+#define CRM_LEXT_READY_INT_FLAG MAKE_VALUE(0x0C, 1) /*!< low speed external crystal stable interrupt ready flag */
+#define CRM_HICK_READY_INT_FLAG MAKE_VALUE(0x0C, 2) /*!< high speed internal clock stable interrupt ready flag */
+#define CRM_HEXT_READY_INT_FLAG MAKE_VALUE(0x0C, 3) /*!< high speed external crystal stable interrupt ready flag */
+#define CRM_PLL_READY_INT_FLAG MAKE_VALUE(0x0C, 4) /*!< phase locking loop stable interrupt ready flag */
+#define CRM_CLOCK_FAILURE_INT_FLAG MAKE_VALUE(0x0C, 7) /*!< clock failure interrupt ready flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRM_interrupts_definition
+ * @brief crm interrupt
+ * @{
+ */
+
+#define CRM_LICK_STABLE_INT ((uint32_t)0x00000100) /*!< low speed internal clock stable interrupt */
+#define CRM_LEXT_STABLE_INT ((uint32_t)0x00000200) /*!< low speed external crystal stable interrupt */
+#define CRM_HICK_STABLE_INT ((uint32_t)0x00000400) /*!< high speed internal clock stable interrupt */
+#define CRM_HEXT_STABLE_INT ((uint32_t)0x00000800) /*!< high speed external crystal stable interrupt */
+#define CRM_PLL_STABLE_INT ((uint32_t)0x00001000) /*!< phase locking loop stable interrupt */
+#define CRM_CLOCK_FAILURE_INT ((uint32_t)0x00800000) /*!< clock failure interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRM_exported_types
+ * @{
+ */
+
+/**
+ * @brief crm periph clock
+ */
+typedef enum
+{
+#if defined (AT32F435xx)
+ /* ahb periph1 */
+ CRM_GPIOA_PERIPH_CLOCK = MAKE_VALUE(0x30, 0), /*!< gpioa periph clock */
+ CRM_GPIOB_PERIPH_CLOCK = MAKE_VALUE(0x30, 1), /*!< gpiob periph clock */
+ CRM_GPIOC_PERIPH_CLOCK = MAKE_VALUE(0x30, 2), /*!< gpioc periph clock */
+ CRM_GPIOD_PERIPH_CLOCK = MAKE_VALUE(0x30, 3), /*!< gpiod periph clock */
+ CRM_GPIOE_PERIPH_CLOCK = MAKE_VALUE(0x30, 4), /*!< gpioe periph clock */
+ CRM_GPIOF_PERIPH_CLOCK = MAKE_VALUE(0x30, 5), /*!< gpiof periph clock */
+ CRM_GPIOG_PERIPH_CLOCK = MAKE_VALUE(0x30, 6), /*!< gpiog periph clock */
+ CRM_GPIOH_PERIPH_CLOCK = MAKE_VALUE(0x30, 7), /*!< gpioh periph clock */
+ CRM_CRC_PERIPH_CLOCK = MAKE_VALUE(0x30, 12), /*!< crc periph clock */
+ CRM_EDMA_PERIPH_CLOCK = MAKE_VALUE(0x30, 21), /*!< edma periph clock */
+ CRM_DMA1_PERIPH_CLOCK = MAKE_VALUE(0x30, 22), /*!< dma1 periph clock */
+ CRM_DMA2_PERIPH_CLOCK = MAKE_VALUE(0x30, 24), /*!< dma2 periph clock */
+ CRM_OTGFS2_PERIPH_CLOCK = MAKE_VALUE(0x30, 29), /*!< otgfs2 periph clock */
+ /* ahb periph2 */
+ CRM_DVP_PERIPH_CLOCK = MAKE_VALUE(0x34, 0), /*!< dvp periph clock */
+ CRM_OTGFS1_PERIPH_CLOCK = MAKE_VALUE(0x34, 7), /*!< otgfs1 periph clock */
+ CRM_SDIO1_PERIPH_CLOCK = MAKE_VALUE(0x34, 15), /*!< sdio1 periph clock */
+ /* ahb periph3 */
+ CRM_XMC_PERIPH_CLOCK = MAKE_VALUE(0x38, 0), /*!< xmc periph clock */
+ CRM_QSPI1_PERIPH_CLOCK = MAKE_VALUE(0x38, 1), /*!< qspi1 periph clock */
+ CRM_QSPI2_PERIPH_CLOCK = MAKE_VALUE(0x38, 14), /*!< qspi2 periph clock */
+ CRM_SDIO2_PERIPH_CLOCK = MAKE_VALUE(0x38, 15), /*!< sdio2 periph clock */
+ /* apb1 periph */
+ CRM_TMR2_PERIPH_CLOCK = MAKE_VALUE(0x40, 0), /*!< tmr2 periph clock */
+ CRM_TMR3_PERIPH_CLOCK = MAKE_VALUE(0x40, 1), /*!< tmr3 periph clock */
+ CRM_TMR4_PERIPH_CLOCK = MAKE_VALUE(0x40, 2), /*!< tmr4 periph clock */
+ CRM_TMR5_PERIPH_CLOCK = MAKE_VALUE(0x40, 3), /*!< tmr5 periph clock */
+ CRM_TMR6_PERIPH_CLOCK = MAKE_VALUE(0x40, 4), /*!< tmr6 periph clock */
+ CRM_TMR7_PERIPH_CLOCK = MAKE_VALUE(0x40, 5), /*!< tmr7 periph clock */
+ CRM_TMR12_PERIPH_CLOCK = MAKE_VALUE(0x40, 6), /*!< tmr12 periph clock */
+ CRM_TMR13_PERIPH_CLOCK = MAKE_VALUE(0x40, 7), /*!< tmr13 periph clock */
+ CRM_TMR14_PERIPH_CLOCK = MAKE_VALUE(0x40, 8), /*!< tmr14 periph clock */
+ CRM_WWDT_PERIPH_CLOCK = MAKE_VALUE(0x40, 11), /*!< wwdt periph clock */
+ CRM_SPI2_PERIPH_CLOCK = MAKE_VALUE(0x40, 14), /*!< spi2 periph clock */
+ CRM_SPI3_PERIPH_CLOCK = MAKE_VALUE(0x40, 15), /*!< spi3 periph clock */
+ CRM_USART2_PERIPH_CLOCK = MAKE_VALUE(0x40, 17), /*!< usart2 periph clock */
+ CRM_USART3_PERIPH_CLOCK = MAKE_VALUE(0x40, 18), /*!< usart3 periph clock */
+ CRM_UART4_PERIPH_CLOCK = MAKE_VALUE(0x40, 19), /*!< uart4 periph clock */
+ CRM_UART5_PERIPH_CLOCK = MAKE_VALUE(0x40, 20), /*!< uart5 periph clock */
+ CRM_I2C1_PERIPH_CLOCK = MAKE_VALUE(0x40, 21), /*!< i2c1 periph clock */
+ CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x40, 22), /*!< i2c2 periph clock */
+ CRM_I2C3_PERIPH_CLOCK = MAKE_VALUE(0x40, 23), /*!< i2c3 periph clock */
+ CRM_CAN1_PERIPH_CLOCK = MAKE_VALUE(0x40, 25), /*!< can1 periph clock */
+ CRM_CAN2_PERIPH_CLOCK = MAKE_VALUE(0x40, 26), /*!< can2 periph clock */
+ CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x40, 28), /*!< pwc periph clock */
+ CRM_DAC_PERIPH_CLOCK = MAKE_VALUE(0x40, 29), /*!< dac periph clock */
+ CRM_UART7_PERIPH_CLOCK = MAKE_VALUE(0x40, 30), /*!< uart7 periph clock */
+ CRM_UART8_PERIPH_CLOCK = MAKE_VALUE(0x40, 31), /*!< uart8 periph clock */
+ /* apb2 periph */
+ CRM_TMR1_PERIPH_CLOCK = MAKE_VALUE(0x44, 0), /*!< tmr1 periph clock */
+ CRM_TMR8_PERIPH_CLOCK = MAKE_VALUE(0x44, 1), /*!< tmr8 periph clock */
+ CRM_USART1_PERIPH_CLOCK = MAKE_VALUE(0x44, 4), /*!< usart1 periph clock */
+ CRM_USART6_PERIPH_CLOCK = MAKE_VALUE(0x44, 5), /*!< usart6 periph clock */
+ CRM_ADC1_PERIPH_CLOCK = MAKE_VALUE(0x44, 8), /*!< adc1 periph clock */
+ CRM_ADC2_PERIPH_CLOCK = MAKE_VALUE(0x44, 9), /*!< adc2 periph clock */
+ CRM_ADC3_PERIPH_CLOCK = MAKE_VALUE(0x44, 10), /*!< adc3 periph clock */
+ CRM_SPI1_PERIPH_CLOCK = MAKE_VALUE(0x44, 12), /*!< spi1 periph clock */
+ CRM_SPI4_PERIPH_CLOCK = MAKE_VALUE(0x44, 13), /*!< spi4 periph clock */
+ CRM_SCFG_PERIPH_CLOCK = MAKE_VALUE(0x44, 14), /*!< scfg periph clock */
+ CRM_TMR9_PERIPH_CLOCK = MAKE_VALUE(0x44, 16), /*!< tmr9 periph clock */
+ CRM_TMR10_PERIPH_CLOCK = MAKE_VALUE(0x44, 17), /*!< tmr10 periph clock */
+ CRM_TMR11_PERIPH_CLOCK = MAKE_VALUE(0x44, 18), /*!< tmr11 periph clock */
+ CRM_TMR20_PERIPH_CLOCK = MAKE_VALUE(0x44, 20), /*!< tmr20 periph clock */
+ CRM_ACC_PERIPH_CLOCK = MAKE_VALUE(0x44, 29) /*!< acc periph clock */
+#endif
+
+#if defined (AT32F437xx)
+ /* ahb periph1 */
+ CRM_GPIOA_PERIPH_CLOCK = MAKE_VALUE(0x30, 0), /*!< gpioa periph clock */
+ CRM_GPIOB_PERIPH_CLOCK = MAKE_VALUE(0x30, 1), /*!< gpiob periph clock */
+ CRM_GPIOC_PERIPH_CLOCK = MAKE_VALUE(0x30, 2), /*!< gpioc periph clock */
+ CRM_GPIOD_PERIPH_CLOCK = MAKE_VALUE(0x30, 3), /*!< gpiod periph clock */
+ CRM_GPIOE_PERIPH_CLOCK = MAKE_VALUE(0x30, 4), /*!< gpioe periph clock */
+ CRM_GPIOF_PERIPH_CLOCK = MAKE_VALUE(0x30, 5), /*!< gpiof periph clock */
+ CRM_GPIOG_PERIPH_CLOCK = MAKE_VALUE(0x30, 6), /*!< gpiog periph clock */
+ CRM_GPIOH_PERIPH_CLOCK = MAKE_VALUE(0x30, 7), /*!< gpioh periph clock */
+ CRM_CRC_PERIPH_CLOCK = MAKE_VALUE(0x30, 12), /*!< crc periph clock */
+ CRM_EDMA_PERIPH_CLOCK = MAKE_VALUE(0x30, 21), /*!< edma periph clock */
+ CRM_DMA1_PERIPH_CLOCK = MAKE_VALUE(0x30, 22), /*!< dma1 periph clock */
+ CRM_DMA2_PERIPH_CLOCK = MAKE_VALUE(0x30, 24), /*!< dma2 periph clock */
+ CRM_EMAC_PERIPH_CLOCK = MAKE_VALUE(0x30, 25), /*!< emac periph clock */
+ CRM_EMACTX_PERIPH_CLOCK = MAKE_VALUE(0x30, 26), /*!< emac tx periph clock */
+ CRM_EMACRX_PERIPH_CLOCK = MAKE_VALUE(0x30, 27), /*!< emac rx periph clock */
+ CRM_EMACPTP_PERIPH_CLOCK = MAKE_VALUE(0x30, 28), /*!< emac ptp periph clock */
+ CRM_OTGFS2_PERIPH_CLOCK = MAKE_VALUE(0x30, 29), /*!< otgfs2 periph clock */
+ /* ahb periph2 */
+ CRM_DVP_PERIPH_CLOCK = MAKE_VALUE(0x34, 0), /*!< dvp periph clock */
+ CRM_OTGFS1_PERIPH_CLOCK = MAKE_VALUE(0x34, 7), /*!< otgfs1 periph clock */
+ CRM_SDIO1_PERIPH_CLOCK = MAKE_VALUE(0x34, 15), /*!< sdio1 periph clock */
+ /* ahb periph3 */
+ CRM_XMC_PERIPH_CLOCK = MAKE_VALUE(0x38, 0), /*!< xmc periph clock */
+ CRM_QSPI1_PERIPH_CLOCK = MAKE_VALUE(0x38, 1), /*!< qspi1 periph clock */
+ CRM_QSPI2_PERIPH_CLOCK = MAKE_VALUE(0x38, 14), /*!< qspi2 periph clock */
+ CRM_SDIO2_PERIPH_CLOCK = MAKE_VALUE(0x38, 15), /*!< sdio2 periph clock */
+ /* apb1 periph */
+ CRM_TMR2_PERIPH_CLOCK = MAKE_VALUE(0x40, 0), /*!< tmr2 periph clock */
+ CRM_TMR3_PERIPH_CLOCK = MAKE_VALUE(0x40, 1), /*!< tmr3 periph clock */
+ CRM_TMR4_PERIPH_CLOCK = MAKE_VALUE(0x40, 2), /*!< tmr4 periph clock */
+ CRM_TMR5_PERIPH_CLOCK = MAKE_VALUE(0x40, 3), /*!< tmr5 periph clock */
+ CRM_TMR6_PERIPH_CLOCK = MAKE_VALUE(0x40, 4), /*!< tmr6 periph clock */
+ CRM_TMR7_PERIPH_CLOCK = MAKE_VALUE(0x40, 5), /*!< tmr7 periph clock */
+ CRM_TMR12_PERIPH_CLOCK = MAKE_VALUE(0x40, 6), /*!< tmr12 periph clock */
+ CRM_TMR13_PERIPH_CLOCK = MAKE_VALUE(0x40, 7), /*!< tmr13 periph clock */
+ CRM_TMR14_PERIPH_CLOCK = MAKE_VALUE(0x40, 8), /*!< tmr14 periph clock */
+ CRM_WWDT_PERIPH_CLOCK = MAKE_VALUE(0x40, 11), /*!< wwdt periph clock */
+ CRM_SPI2_PERIPH_CLOCK = MAKE_VALUE(0x40, 14), /*!< spi2 periph clock */
+ CRM_SPI3_PERIPH_CLOCK = MAKE_VALUE(0x40, 15), /*!< spi3 periph clock */
+ CRM_USART2_PERIPH_CLOCK = MAKE_VALUE(0x40, 17), /*!< usart2 periph clock */
+ CRM_USART3_PERIPH_CLOCK = MAKE_VALUE(0x40, 18), /*!< usart3 periph clock */
+ CRM_UART4_PERIPH_CLOCK = MAKE_VALUE(0x40, 19), /*!< uart4 periph clock */
+ CRM_UART5_PERIPH_CLOCK = MAKE_VALUE(0x40, 20), /*!< uart5 periph clock */
+ CRM_I2C1_PERIPH_CLOCK = MAKE_VALUE(0x40, 21), /*!< i2c1 periph clock */
+ CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x40, 22), /*!< i2c2 periph clock */
+ CRM_I2C3_PERIPH_CLOCK = MAKE_VALUE(0x40, 23), /*!< i2c3 periph clock */
+ CRM_CAN1_PERIPH_CLOCK = MAKE_VALUE(0x40, 25), /*!< can1 periph clock */
+ CRM_CAN2_PERIPH_CLOCK = MAKE_VALUE(0x40, 26), /*!< can2 periph clock */
+ CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x40, 28), /*!< pwc periph clock */
+ CRM_DAC_PERIPH_CLOCK = MAKE_VALUE(0x40, 29), /*!< dac periph clock */
+ CRM_UART7_PERIPH_CLOCK = MAKE_VALUE(0x40, 30), /*!< uart7 periph clock */
+ CRM_UART8_PERIPH_CLOCK = MAKE_VALUE(0x40, 31), /*!< uart8 periph clock */
+ /* apb2 periph */
+ CRM_TMR1_PERIPH_CLOCK = MAKE_VALUE(0x44, 0), /*!< tmr1 periph clock */
+ CRM_TMR8_PERIPH_CLOCK = MAKE_VALUE(0x44, 1), /*!< tmr8 periph clock */
+ CRM_USART1_PERIPH_CLOCK = MAKE_VALUE(0x44, 4), /*!< usart1 periph clock */
+ CRM_USART6_PERIPH_CLOCK = MAKE_VALUE(0x44, 5), /*!< usart6 periph clock */
+ CRM_ADC1_PERIPH_CLOCK = MAKE_VALUE(0x44, 8), /*!< adc1 periph clock */
+ CRM_ADC2_PERIPH_CLOCK = MAKE_VALUE(0x44, 9), /*!< adc2 periph clock */
+ CRM_ADC3_PERIPH_CLOCK = MAKE_VALUE(0x44, 10), /*!< adc3 periph clock */
+ CRM_SPI1_PERIPH_CLOCK = MAKE_VALUE(0x44, 12), /*!< spi1 periph clock */
+ CRM_SPI4_PERIPH_CLOCK = MAKE_VALUE(0x44, 13), /*!< spi4 periph clock */
+ CRM_SCFG_PERIPH_CLOCK = MAKE_VALUE(0x44, 14), /*!< scfg periph clock */
+ CRM_TMR9_PERIPH_CLOCK = MAKE_VALUE(0x44, 16), /*!< tmr9 periph clock */
+ CRM_TMR10_PERIPH_CLOCK = MAKE_VALUE(0x44, 17), /*!< tmr10 periph clock */
+ CRM_TMR11_PERIPH_CLOCK = MAKE_VALUE(0x44, 18), /*!< tmr11 periph clock */
+ CRM_TMR20_PERIPH_CLOCK = MAKE_VALUE(0x44, 20), /*!< tmr20 periph clock */
+ CRM_ACC_PERIPH_CLOCK = MAKE_VALUE(0x44, 29) /*!< acc periph clock */
+#endif
+
+} crm_periph_clock_type;
+
+/**
+ * @brief crm periph reset
+ */
+typedef enum
+{
+#if defined (AT32F435xx)
+ /* ahb periph1 */
+ CRM_GPIOA_PERIPH_RESET = MAKE_VALUE(0x10, 0), /*!< gpioa periph reset */
+ CRM_GPIOB_PERIPH_RESET = MAKE_VALUE(0x10, 1), /*!< gpiob periph reset */
+ CRM_GPIOC_PERIPH_RESET = MAKE_VALUE(0x10, 2), /*!< gpioc periph reset */
+ CRM_GPIOD_PERIPH_RESET = MAKE_VALUE(0x10, 3), /*!< gpiod periph reset */
+ CRM_GPIOE_PERIPH_RESET = MAKE_VALUE(0x10, 4), /*!< gpioe periph reset */
+ CRM_GPIOF_PERIPH_RESET = MAKE_VALUE(0x10, 5), /*!< gpiof periph reset */
+ CRM_GPIOG_PERIPH_RESET = MAKE_VALUE(0x10, 6), /*!< gpiog periph reset */
+ CRM_GPIOH_PERIPH_RESET = MAKE_VALUE(0x10, 7), /*!< gpioh periph reset */
+ CRM_CRC_PERIPH_RESET = MAKE_VALUE(0x10, 12), /*!< crc periph reset */
+ CRM_EDMA_PERIPH_RESET = MAKE_VALUE(0x10, 21), /*!< edma periph reset */
+ CRM_DMA1_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< dma1 periph reset */
+ CRM_DMA2_PERIPH_RESET = MAKE_VALUE(0x10, 24), /*!< dma2 periph reset */
+ CRM_OTGFS2_PERIPH_RESET = MAKE_VALUE(0x10, 29), /*!< otgfs2 periph reset */
+ /* ahb periph2 */
+ CRM_DVP_PERIPH_RESET = MAKE_VALUE(0x14, 0), /*!< dvp periph reset */
+ CRM_OTGFS1_PERIPH_RESET = MAKE_VALUE(0x14, 7), /*!< otgfs1 periph reset */
+ CRM_SDIO1_PERIPH_RESET = MAKE_VALUE(0x14, 15), /*!< sdio1 periph reset */
+ /* ahb periph3 */
+ CRM_XMC_PERIPH_RESET = MAKE_VALUE(0x18, 0), /*!< xmc periph reset */
+ CRM_QSPI1_PERIPH_RESET = MAKE_VALUE(0x18, 1), /*!< qspi1 periph reset */
+ CRM_QSPI2_PERIPH_RESET = MAKE_VALUE(0x18, 14), /*!< qspi2 periph reset */
+ CRM_SDIO2_PERIPH_RESET = MAKE_VALUE(0x18, 15), /*!< sdio2 periph reset */
+ /* apb1 periph */
+ CRM_TMR2_PERIPH_RESET = MAKE_VALUE(0x20, 0), /*!< tmr2 periph reset */
+ CRM_TMR3_PERIPH_RESET = MAKE_VALUE(0x20, 1), /*!< tmr3 periph reset */
+ CRM_TMR4_PERIPH_RESET = MAKE_VALUE(0x20, 2), /*!< tmr4 periph reset */
+ CRM_TMR5_PERIPH_RESET = MAKE_VALUE(0x20, 3), /*!< tmr5 periph reset */
+ CRM_TMR6_PERIPH_RESET = MAKE_VALUE(0x20, 4), /*!< tmr6 periph reset */
+ CRM_TMR7_PERIPH_RESET = MAKE_VALUE(0x20, 5), /*!< tmr7 periph reset */
+ CRM_TMR12_PERIPH_RESET = MAKE_VALUE(0x20, 6), /*!< tmr12 periph reset */
+ CRM_TMR13_PERIPH_RESET = MAKE_VALUE(0x20, 7), /*!< tmr13 periph reset */
+ CRM_TMR14_PERIPH_RESET = MAKE_VALUE(0x20, 8), /*!< tmr14 periph reset */
+ CRM_WWDT_PERIPH_RESET = MAKE_VALUE(0x20, 11), /*!< wwdt periph reset */
+ CRM_SPI2_PERIPH_RESET = MAKE_VALUE(0x20, 14), /*!< spi2 periph reset */
+ CRM_SPI3_PERIPH_RESET = MAKE_VALUE(0x20, 15), /*!< spi3 periph reset */
+ CRM_USART2_PERIPH_RESET = MAKE_VALUE(0x20, 17), /*!< usart2 periph reset */
+ CRM_USART3_PERIPH_RESET = MAKE_VALUE(0x20, 18), /*!< usart3 periph reset */
+ CRM_UART4_PERIPH_RESET = MAKE_VALUE(0x20, 19), /*!< uart4 periph reset */
+ CRM_UART5_PERIPH_RESET = MAKE_VALUE(0x20, 20), /*!< uart5 periph reset */
+ CRM_I2C1_PERIPH_RESET = MAKE_VALUE(0x20, 21), /*!< i2c1 periph reset */
+ CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x20, 22), /*!< i2c2 periph reset */
+ CRM_I2C3_PERIPH_RESET = MAKE_VALUE(0x20, 23), /*!< i2c3 periph reset */
+ CRM_CAN1_PERIPH_RESET = MAKE_VALUE(0x20, 25), /*!< can1 periph reset */
+ CRM_CAN2_PERIPH_RESET = MAKE_VALUE(0x20, 26), /*!< can2 periph reset */
+ CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x20, 28), /*!< pwc periph reset */
+ CRM_DAC_PERIPH_RESET = MAKE_VALUE(0x20, 29), /*!< dac periph reset */
+ CRM_UART7_PERIPH_RESET = MAKE_VALUE(0x20, 30), /*!< uart7 periph reset */
+ CRM_UART8_PERIPH_RESET = MAKE_VALUE(0x20, 31), /*!< uart8 periph reset */
+ /* apb2 periph */
+ CRM_TMR1_PERIPH_RESET = MAKE_VALUE(0x24, 0), /*!< tmr1 periph reset */
+ CRM_TMR8_PERIPH_RESET = MAKE_VALUE(0x24, 1), /*!< tmr8 periph reset */
+ CRM_USART1_PERIPH_RESET = MAKE_VALUE(0x24, 4), /*!< usart1 periph reset */
+ CRM_USART6_PERIPH_RESET = MAKE_VALUE(0x24, 5), /*!< usart6 periph reset */
+ CRM_ADC_PERIPH_RESET = MAKE_VALUE(0x24, 8), /*!< adc periph reset */
+ CRM_SPI1_PERIPH_RESET = MAKE_VALUE(0x24, 12), /*!< spi1 periph reset */
+ CRM_SPI4_PERIPH_RESET = MAKE_VALUE(0x24, 13), /*!< spi4 periph reset */
+ CRM_SCFG_PERIPH_RESET = MAKE_VALUE(0x24, 14), /*!< scfg periph reset */
+ CRM_TMR9_PERIPH_RESET = MAKE_VALUE(0x24, 16), /*!< tmr9 periph reset */
+ CRM_TMR10_PERIPH_RESET = MAKE_VALUE(0x24, 17), /*!< tmr10 periph reset */
+ CRM_TMR11_PERIPH_RESET = MAKE_VALUE(0x24, 18), /*!< tmr11 periph reset */
+ CRM_TMR20_PERIPH_RESET = MAKE_VALUE(0x24, 20), /*!< tmr20 periph reset */
+ CRM_ACC_PERIPH_RESET = MAKE_VALUE(0x24, 29) /*!< acc periph reset */
+#endif
+
+#if defined (AT32F437xx)
+ /* ahb periph1 */
+ CRM_GPIOA_PERIPH_RESET = MAKE_VALUE(0x10, 0), /*!< gpioa periph reset */
+ CRM_GPIOB_PERIPH_RESET = MAKE_VALUE(0x10, 1), /*!< gpiob periph reset */
+ CRM_GPIOC_PERIPH_RESET = MAKE_VALUE(0x10, 2), /*!< gpioc periph reset */
+ CRM_GPIOD_PERIPH_RESET = MAKE_VALUE(0x10, 3), /*!< gpiod periph reset */
+ CRM_GPIOE_PERIPH_RESET = MAKE_VALUE(0x10, 4), /*!< gpioe periph reset */
+ CRM_GPIOF_PERIPH_RESET = MAKE_VALUE(0x10, 5), /*!< gpiof periph reset */
+ CRM_GPIOG_PERIPH_RESET = MAKE_VALUE(0x10, 6), /*!< gpiog periph reset */
+ CRM_GPIOH_PERIPH_RESET = MAKE_VALUE(0x10, 7), /*!< gpioh periph reset */
+ CRM_CRC_PERIPH_RESET = MAKE_VALUE(0x10, 12), /*!< crc periph reset */
+ CRM_EDMA_PERIPH_RESET = MAKE_VALUE(0x10, 21), /*!< edma periph reset */
+ CRM_DMA1_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< dma1 periph reset */
+ CRM_DMA2_PERIPH_RESET = MAKE_VALUE(0x10, 24), /*!< dma2 periph reset */
+ CRM_EMAC_PERIPH_RESET = MAKE_VALUE(0x10, 25), /*!< emac periph reset */
+ CRM_OTGFS2_PERIPH_RESET = MAKE_VALUE(0x10, 29), /*!< otgfs2 periph reset */
+ /* ahb periph2 */
+ CRM_DVP_PERIPH_RESET = MAKE_VALUE(0x14, 0), /*!< dvp periph reset */
+ CRM_OTGFS1_PERIPH_RESET = MAKE_VALUE(0x14, 7), /*!< otgfs1 periph reset */
+ CRM_SDIO1_PERIPH_RESET = MAKE_VALUE(0x14, 15), /*!< sdio1 periph reset */
+ /* ahb periph3 */
+ CRM_XMC_PERIPH_RESET = MAKE_VALUE(0x18, 0), /*!< xmc periph reset */
+ CRM_QSPI1_PERIPH_RESET = MAKE_VALUE(0x18, 1), /*!< qspi1 periph reset */
+ CRM_QSPI2_PERIPH_RESET = MAKE_VALUE(0x18, 14), /*!< qspi2 periph reset */
+ CRM_SDIO2_PERIPH_RESET = MAKE_VALUE(0x18, 15), /*!< sdio2 periph reset */
+ /* apb1 periph */
+ CRM_TMR2_PERIPH_RESET = MAKE_VALUE(0x20, 0), /*!< tmr2 periph reset */
+ CRM_TMR3_PERIPH_RESET = MAKE_VALUE(0x20, 1), /*!< tmr3 periph reset */
+ CRM_TMR4_PERIPH_RESET = MAKE_VALUE(0x20, 2), /*!< tmr4 periph reset */
+ CRM_TMR5_PERIPH_RESET = MAKE_VALUE(0x20, 3), /*!< tmr5 periph reset */
+ CRM_TMR6_PERIPH_RESET = MAKE_VALUE(0x20, 4), /*!< tmr6 periph reset */
+ CRM_TMR7_PERIPH_RESET = MAKE_VALUE(0x20, 5), /*!< tmr7 periph reset */
+ CRM_TMR12_PERIPH_RESET = MAKE_VALUE(0x20, 6), /*!< tmr12 periph reset */
+ CRM_TMR13_PERIPH_RESET = MAKE_VALUE(0x20, 7), /*!< tmr13 periph reset */
+ CRM_TMR14_PERIPH_RESET = MAKE_VALUE(0x20, 8), /*!< tmr14 periph reset */
+ CRM_WWDT_PERIPH_RESET = MAKE_VALUE(0x20, 11), /*!< wwdt periph reset */
+ CRM_SPI2_PERIPH_RESET = MAKE_VALUE(0x20, 14), /*!< spi2 periph reset */
+ CRM_SPI3_PERIPH_RESET = MAKE_VALUE(0x20, 15), /*!< spi3 periph reset */
+ CRM_USART2_PERIPH_RESET = MAKE_VALUE(0x20, 17), /*!< usart2 periph reset */
+ CRM_USART3_PERIPH_RESET = MAKE_VALUE(0x20, 18), /*!< usart3 periph reset */
+ CRM_UART4_PERIPH_RESET = MAKE_VALUE(0x20, 19), /*!< uart4 periph reset */
+ CRM_UART5_PERIPH_RESET = MAKE_VALUE(0x20, 20), /*!< uart5 periph reset */
+ CRM_I2C1_PERIPH_RESET = MAKE_VALUE(0x20, 21), /*!< i2c1 periph reset */
+ CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x20, 22), /*!< i2c2 periph reset */
+ CRM_I2C3_PERIPH_RESET = MAKE_VALUE(0x20, 23), /*!< i2c3 periph reset */
+ CRM_CAN1_PERIPH_RESET = MAKE_VALUE(0x20, 25), /*!< can1 periph reset */
+ CRM_CAN2_PERIPH_RESET = MAKE_VALUE(0x20, 26), /*!< can2 periph reset */
+ CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x20, 28), /*!< pwc periph reset */
+ CRM_DAC_PERIPH_RESET = MAKE_VALUE(0x20, 29), /*!< dac periph reset */
+ CRM_UART7_PERIPH_RESET = MAKE_VALUE(0x20, 30), /*!< uart7 periph reset */
+ CRM_UART8_PERIPH_RESET = MAKE_VALUE(0x20, 31), /*!< uart8 periph reset */
+ /* apb2 periph */
+ CRM_TMR1_PERIPH_RESET = MAKE_VALUE(0x24, 0), /*!< tmr1 periph reset */
+ CRM_TMR8_PERIPH_RESET = MAKE_VALUE(0x24, 1), /*!< tmr8 periph reset */
+ CRM_USART1_PERIPH_RESET = MAKE_VALUE(0x24, 4), /*!< usart1 periph reset */
+ CRM_USART6_PERIPH_RESET = MAKE_VALUE(0x24, 5), /*!< usart6 periph reset */
+ CRM_ADC_PERIPH_RESET = MAKE_VALUE(0x24, 8), /*!< adc periph reset */
+ CRM_SPI1_PERIPH_RESET = MAKE_VALUE(0x24, 12), /*!< spi1 periph reset */
+ CRM_SPI4_PERIPH_RESET = MAKE_VALUE(0x24, 13), /*!< spi4 periph reset */
+ CRM_SCFG_PERIPH_RESET = MAKE_VALUE(0x24, 14), /*!< scfg periph reset */
+ CRM_TMR9_PERIPH_RESET = MAKE_VALUE(0x24, 16), /*!< tmr9 periph reset */
+ CRM_TMR10_PERIPH_RESET = MAKE_VALUE(0x24, 17), /*!< tmr10 periph reset */
+ CRM_TMR11_PERIPH_RESET = MAKE_VALUE(0x24, 18), /*!< tmr11 periph reset */
+ CRM_TMR20_PERIPH_RESET = MAKE_VALUE(0x24, 20), /*!< tmr20 periph reset */
+ CRM_ACC_PERIPH_RESET = MAKE_VALUE(0x24, 29) /*!< acc periph reset */
+#endif
+
+} crm_periph_reset_type;
+
+/**
+ * @brief crm periph clock in low power mode
+ */
+typedef enum
+{
+#if defined (AT32F435xx)
+ /* ahb periph1 */
+ CRM_GPIOA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 0), /*!< gpioa sleep mode periph clock */
+ CRM_GPIOB_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 1), /*!< gpiob sleep mode periph clock */
+ CRM_GPIOC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 2), /*!< gpioc sleep mode periph clock */
+ CRM_GPIOD_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 3), /*!< gpiod sleep mode periph clock */
+ CRM_GPIOE_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 4), /*!< gpioe sleep mode periph clock */
+ CRM_GPIOF_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 5), /*!< gpiof sleep mode periph clock */
+ CRM_GPIOG_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 6), /*!< gpiog sleep mode periph clock */
+ CRM_GPIOH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 7), /*!< gpioh sleep mode periph clock */
+ CRM_CRC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 12), /*!< crc sleep mode periph clock */
+ CRM_EDMA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 21), /*!< edma sleep mode periph clock */
+ CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */
+ CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */
+ CRM_EMAC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 25), /*!< emac sleep mode periph clock */
+ CRM_EMACTX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 26), /*!< emac tx sleep mode periph clock */
+ CRM_EMACRX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 27), /*!< emac rx sleep mode periph clock */
+ CRM_EMACPTP_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 28), /*!< emac ptp sleep mode periph clock */
+ CRM_OTGFS2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 29), /*!< otgfs2 sleep mode periph clock */
+ /* ahb periph2 */
+ CRM_DVP_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 0), /*!< dvp sleep mode periph clock */
+ CRM_OTGFS1_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 7), /*!< otgfs1 sleep mode periph clock */
+ CRM_SDIO1_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 15), /*!< sdio1 sleep mode periph clock */
+ /* ahb periph3 */
+ CRM_XMC_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 0), /*!< xmc sleep mode periph clock */
+ CRM_QSPI1_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 1), /*!< qspi1 sleep mode periph clock */
+ CRM_QSPI2_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 14), /*!< qspi2 sleep mode periph clock */
+ CRM_SDIO2_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 15), /*!< sdio2 sleep mode periph clock */
+ /* apb1 periph */
+ CRM_TMR2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 0), /*!< tmr2 sleep mode periph clock */
+ CRM_TMR3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 1), /*!< tmr3 sleep mode periph clock */
+ CRM_TMR4_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 2), /*!< tmr4 sleep mode periph clock */
+ CRM_TMR5_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 3), /*!< tmr5 sleep mode periph clock */
+ CRM_TMR6_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 4), /*!< tmr6 sleep mode periph clock */
+ CRM_TMR7_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 5), /*!< tmr7 sleep mode periph clock */
+ CRM_TMR12_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 6), /*!< tmr12 sleep mode periph clock */
+ CRM_TMR13_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 7), /*!< tmr13 sleep mode periph clock */
+ CRM_TMR14_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 8), /*!< tmr14 sleep mode periph clock */
+ CRM_WWDT_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 11), /*!< wwdt sleep mode periph clock */
+ CRM_SPI2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 14), /*!< spi2 sleep mode periph clock */
+ CRM_SPI3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 15), /*!< spi3 sleep mode periph clock */
+ CRM_USART2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 17), /*!< usart2 sleep mode periph clock */
+ CRM_USART3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 18), /*!< usart3 sleep mode periph clock */
+ CRM_UART4_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 19), /*!< uart4 sleep mode periph clock */
+ CRM_UART5_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 20), /*!< uart5 sleep mode periph clock */
+ CRM_I2C1_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 21), /*!< i2c1 sleep mode periph clock */
+ CRM_I2C2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 22), /*!< i2c2 sleep mode periph clock */
+ CRM_I2C3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 23), /*!< i2c3 sleep mode periph clock */
+ CRM_CAN1_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 25), /*!< can1 sleep mode periph clock */
+ CRM_CAN2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 26), /*!< can2 sleep mode periph clock */
+ CRM_PWC_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 28), /*!< pwc sleep mode periph clock */
+ CRM_DAC_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 29), /*!< dac sleep mode periph clock */
+ CRM_UART7_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 30), /*!< uart7 sleep mode periph clock */
+ CRM_UART8_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 31), /*!< uart8 sleep mode periph clock */
+ /* apb2 periph */
+ CRM_TMR1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 0), /*!< tmr1 sleep mode periph clock */
+ CRM_TMR8_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 1), /*!< tmr8 sleep mode periph clock */
+ CRM_USART1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 4), /*!< usart1 sleep mode periph clock */
+ CRM_USART6_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 5), /*!< usart6 sleep mode periph clock */
+ CRM_ADC1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 8), /*!< adc1 sleep mode periph clock */
+ CRM_ADC2_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 9), /*!< adc2 sleep mode periph clock */
+ CRM_ADC3_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 10), /*!< adc3 sleep mode periph clock */
+ CRM_SPI1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 12), /*!< spi1 sleep mode periph clock */
+ CRM_SPI4_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 13), /*!< spi4 sleep mode periph clock */
+ CRM_SCFG_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 14), /*!< scfg sleep mode periph clock */
+ CRM_TMR9_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 16), /*!< tmr9 sleep mode periph clock */
+ CRM_TMR10_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 17), /*!< tmr10 sleep mode periph clock */
+ CRM_TMR11_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 18), /*!< tmr11 sleep mode periph clock */
+ CRM_TMR20_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 20), /*!< tmr20 sleep mode periph clock */
+ CRM_ACC_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 29) /*!< acc sleep mode periph clock */
+#endif
+
+#if defined (AT32F437xx)
+ /* ahb periph1 */
+ CRM_GPIOA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 0), /*!< gpioa sleep mode periph clock */
+ CRM_GPIOB_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 1), /*!< gpiob sleep mode periph clock */
+ CRM_GPIOC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 2), /*!< gpioc sleep mode periph clock */
+ CRM_GPIOD_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 3), /*!< gpiod sleep mode periph clock */
+ CRM_GPIOE_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 4), /*!< gpioe sleep mode periph clock */
+ CRM_GPIOF_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 5), /*!< gpiof sleep mode periph clock */
+ CRM_GPIOG_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 6), /*!< gpiog sleep mode periph clock */
+ CRM_GPIOH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 7), /*!< gpioh sleep mode periph clock */
+ CRM_CRC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 12), /*!< crc sleep mode periph clock */
+ CRM_EDMA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 21), /*!< edma sleep mode periph clock */
+ CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */
+ CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */
+ CRM_OTGFS2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 29), /*!< otgfs2 sleep mode periph clock */
+ /* ahb periph2 */
+ CRM_DVP_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 0), /*!< dvp sleep mode periph clock */
+ CRM_OTGFS1_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 7), /*!< otgfs1 sleep mode periph clock */
+ CRM_SDIO1_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 15), /*!< sdio1 sleep mode periph clock */
+ /* ahb periph3 */
+ CRM_XMC_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 0), /*!< xmc sleep mode periph clock */
+ CRM_QSPI1_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 1), /*!< qspi1 sleep mode periph clock */
+ CRM_QSPI2_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 14), /*!< qspi2 sleep mode periph clock */
+ CRM_SDIO2_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 15), /*!< sdio2 sleep mode periph clock */
+ /* apb1 periph */
+ CRM_TMR2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 0), /*!< tmr2 sleep mode periph clock */
+ CRM_TMR3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 1), /*!< tmr3 sleep mode periph clock */
+ CRM_TMR4_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 2), /*!< tmr4 sleep mode periph clock */
+ CRM_TMR5_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 3), /*!< tmr5 sleep mode periph clock */
+ CRM_TMR6_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 4), /*!< tmr6 sleep mode periph clock */
+ CRM_TMR7_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 5), /*!< tmr7 sleep mode periph clock */
+ CRM_TMR12_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 6), /*!< tmr12 sleep mode periph clock */
+ CRM_TMR13_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 7), /*!< tmr13 sleep mode periph clock */
+ CRM_TMR14_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 8), /*!< tmr14 sleep mode periph clock */
+ CRM_WWDT_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 11), /*!< wwdt sleep mode periph clock */
+ CRM_SPI2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 14), /*!< spi2 sleep mode periph clock */
+ CRM_SPI3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 15), /*!< spi3 sleep mode periph clock */
+ CRM_USART2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 17), /*!< usart2 sleep mode periph clock */
+ CRM_USART3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 18), /*!< usart3 sleep mode periph clock */
+ CRM_UART4_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 19), /*!< uart4 sleep mode periph clock */
+ CRM_UART5_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 20), /*!< uart5 sleep mode periph clock */
+ CRM_I2C1_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 21), /*!< i2c1 sleep mode periph clock */
+ CRM_I2C2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 22), /*!< i2c2 sleep mode periph clock */
+ CRM_I2C3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 23), /*!< i2c3 sleep mode periph clock */
+ CRM_CAN1_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 25), /*!< can1 sleep mode periph clock */
+ CRM_CAN2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 26), /*!< can2 sleep mode periph clock */
+ CRM_PWC_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 28), /*!< pwc sleep mode periph clock */
+ CRM_DAC_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 29), /*!< dac sleep mode periph clock */
+ CRM_UART7_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 30), /*!< uart7 sleep mode periph clock */
+ CRM_UART8_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 31), /*!< uart8 sleep mode periph clock */
+ /* apb2 periph */
+ CRM_TMR1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 0), /*!< tmr1 sleep mode periph clock */
+ CRM_TMR8_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 1), /*!< tmr8 sleep mode periph clock */
+ CRM_USART1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 4), /*!< usart1 sleep mode periph clock */
+ CRM_USART6_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 5), /*!< usart6 sleep mode periph clock */
+ CRM_ADC1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 8), /*!< adc1 sleep mode periph clock */
+ CRM_ADC2_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 9), /*!< adc2 sleep mode periph clock */
+ CRM_ADC3_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 10), /*!< adc3 sleep mode periph clock */
+ CRM_SPI1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 12), /*!< spi1 sleep mode periph clock */
+ CRM_SPI4_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 13), /*!< spi4 sleep mode periph clock */
+ CRM_SCFG_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 14), /*!< scfg sleep mode periph clock */
+ CRM_TMR9_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 16), /*!< tmr9 sleep mode periph clock */
+ CRM_TMR10_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 17), /*!< tmr10 sleep mode periph clock */
+ CRM_TMR11_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 18), /*!< tmr11 sleep mode periph clock */
+ CRM_TMR20_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 20), /*!< tmr20 sleep mode periph clock */
+ CRM_ACC_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 29) /*!< acc sleep mode periph clock */
+#endif
+
+} crm_periph_clock_lowpower_type;
+
+/**
+ * @brief crm pll clock source
+ */
+typedef enum
+{
+ CRM_PLL_SOURCE_HICK = 0x00, /*!< high speed internal clock as pll reference clock source */
+ CRM_PLL_SOURCE_HEXT = 0x01 /*!< high speed external crystal as pll reference clock source */
+} crm_pll_clock_source_type;
+
+/**
+ * @brief crm pll fr
+ */
+typedef enum
+{
+ CRM_PLL_FR_1 = 0x00, /*!< pll post-division div1 */
+ CRM_PLL_FR_2 = 0x01, /*!< pll post-division div2 */
+ CRM_PLL_FR_4 = 0x02, /*!< pll post-division div4 */
+ CRM_PLL_FR_8 = 0x03, /*!< pll post-division div8 */
+ CRM_PLL_FR_16 = 0x04, /*!< pll post-division div16 */
+ CRM_PLL_FR_32 = 0x05 /*!< pll post-division div32 */
+} crm_pll_fr_type;
+
+/**
+ * @brief crm clock source
+ */
+typedef enum
+{
+ CRM_CLOCK_SOURCE_HICK = 0x00, /*!< high speed internal clock */
+ CRM_CLOCK_SOURCE_HEXT = 0x01, /*!< high speed external crystal */
+ CRM_CLOCK_SOURCE_PLL = 0x02, /*!< phase locking loop */
+ CRM_CLOCK_SOURCE_LEXT = 0x03, /*!< low speed external crystal */
+ CRM_CLOCK_SOURCE_LICK = 0x04 /*!< low speed internal clock */
+} crm_clock_source_type;
+
+/**
+ * @brief crm ahb division
+ */
+typedef enum
+{
+ CRM_AHB_DIV_1 = 0x00, /*!< sclk div1 to ahbclk */
+ CRM_AHB_DIV_2 = 0x08, /*!< sclk div2 to ahbclk */
+ CRM_AHB_DIV_4 = 0x09, /*!< sclk div4 to ahbclk */
+ CRM_AHB_DIV_8 = 0x0A, /*!< sclk div8 to ahbclk */
+ CRM_AHB_DIV_16 = 0x0B, /*!< sclk div16 to ahbclk */
+ CRM_AHB_DIV_64 = 0x0C, /*!< sclk div64 to ahbclk */
+ CRM_AHB_DIV_128 = 0x0D, /*!< sclk div128 to ahbclk */
+ CRM_AHB_DIV_256 = 0x0E, /*!< sclk div256 to ahbclk */
+ CRM_AHB_DIV_512 = 0x0F /*!< sclk div512 to ahbclk */
+} crm_ahb_div_type;
+
+/**
+ * @brief crm apb1 division
+ */
+typedef enum
+{
+ CRM_APB1_DIV_1 = 0x00, /*!< ahbclk div1 to apb1clk */
+ CRM_APB1_DIV_2 = 0x04, /*!< ahbclk div2 to apb1clk */
+ CRM_APB1_DIV_4 = 0x05, /*!< ahbclk div4 to apb1clk */
+ CRM_APB1_DIV_8 = 0x06, /*!< ahbclk div8 to apb1clk */
+ CRM_APB1_DIV_16 = 0x07 /*!< ahbclk div16 to apb1clk */
+} crm_apb1_div_type;
+
+/**
+ * @brief crm apb2 division
+ */
+typedef enum
+{
+ CRM_APB2_DIV_1 = 0x00, /*!< ahbclk div1 to apb2clk */
+ CRM_APB2_DIV_2 = 0x04, /*!< ahbclk div2 to apb2clk */
+ CRM_APB2_DIV_4 = 0x05, /*!< ahbclk div4 to apb2clk */
+ CRM_APB2_DIV_8 = 0x06, /*!< ahbclk div8 to apb2clk */
+ CRM_APB2_DIV_16 = 0x07 /*!< ahbclk div16 to apb2clk */
+} crm_apb2_div_type;
+
+/**
+ * @brief crm usb division
+ */
+typedef enum
+{
+ CRM_USB_DIV_1_5 = 0x00, /*!< pllclk div1.5 to usbclk */
+ CRM_USB_DIV_1 = 0x01, /*!< pllclk div1 to usbclk */
+ CRM_USB_DIV_2_5 = 0x02, /*!< pllclk div2.5 to usbclk */
+ CRM_USB_DIV_2 = 0x03, /*!< pllclk div2 to usbclk */
+ CRM_USB_DIV_3_5 = 0x04, /*!< pllclk div3.5 to usbclk */
+ CRM_USB_DIV_3 = 0x05, /*!< pllclk div3 to usbclk */
+ CRM_USB_DIV_4_5 = 0x06, /*!< pllclk div4.5 to usbclk */
+ CRM_USB_DIV_4 = 0x07, /*!< pllclk div4 to usbclk */
+ CRM_USB_DIV_5_5 = 0x08, /*!< pllclk div5.5 to usbclk */
+ CRM_USB_DIV_5 = 0x09, /*!< pllclk div5 to usbclk */
+ CRM_USB_DIV_6_5 = 0x0A, /*!< pllclk div6.5 to usbclk */
+ CRM_USB_DIV_6 = 0x0B, /*!< pllclk div6 to usbclk */
+ CRM_USB_DIV_7 = 0x0C /*!< pllclk div7 to usbclk */
+} crm_usb_div_type;
+
+/**
+ * @brief crm ertc clock
+ */
+typedef enum
+{
+ CRM_ERTC_CLOCK_NOCLK = 0x000, /*!< no clock as ertc clock source */
+ CRM_ERTC_CLOCK_LEXT = 0x001, /*!< low speed external crystal as ertc clock source */
+ CRM_ERTC_CLOCK_LICK = 0x002, /*!< low speed internal clock as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_2 = 0x023, /*!< high speed external crystal div2 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_3 = 0x033, /*!< high speed external crystal div3 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_4 = 0x043, /*!< high speed external crystal div4 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_5 = 0x053, /*!< high speed external crystal div5 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_6 = 0x063, /*!< high speed external crystal div6 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_7 = 0x073, /*!< high speed external crystal div7 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_8 = 0x083, /*!< high speed external crystal div8 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_9 = 0x093, /*!< high speed external crystal div9 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_10 = 0x0A3, /*!< high speed external crystal div10 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_11 = 0x0B3, /*!< high speed external crystal div11 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_12 = 0x0C3, /*!< high speed external crystal div12 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_13 = 0x0D3, /*!< high speed external crystal div13 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_14 = 0x0E3, /*!< high speed external crystal div14 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_15 = 0x0F3, /*!< high speed external crystal div15 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_16 = 0x103, /*!< high speed external crystal div16 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_17 = 0x113, /*!< high speed external crystal div17 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_18 = 0x123, /*!< high speed external crystal div18 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_19 = 0x133, /*!< high speed external crystal div19 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_20 = 0x143, /*!< high speed external crystal div20 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_21 = 0x153, /*!< high speed external crystal div21 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_22 = 0x163, /*!< high speed external crystal div22 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_23 = 0x173, /*!< high speed external crystal div23 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_24 = 0x183, /*!< high speed external crystal div24 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_25 = 0x193, /*!< high speed external crystal div25 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_26 = 0x1A3, /*!< high speed external crystal div26 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_27 = 0x1B3, /*!< high speed external crystal div27 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_28 = 0x1C3, /*!< high speed external crystal div28 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_29 = 0x1D3, /*!< high speed external crystal div29 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_30 = 0x1E3, /*!< high speed external crystal div30 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_31 = 0x1F3 /*!< high speed external crystal div31 as ertc clock source */
+} crm_ertc_clock_type;
+
+/**
+ * @brief crm hick 48mhz division
+ */
+typedef enum
+{
+ CRM_HICK48_DIV6 = 0x00, /*!< fixed 8 mhz when hick is selected as sclk */
+ CRM_HICK48_NODIV = 0x01 /*!< 8 mhz or 48 mhz depend on hickdiv when hick is selected as sclk */
+} crm_hick_div_6_type;
+
+/**
+ * @brief crm sclk select
+ */
+typedef enum
+{
+ CRM_SCLK_HICK = 0x00, /*!< select high speed internal clock as sclk */
+ CRM_SCLK_HEXT = 0x01, /*!< select high speed external crystal as sclk */
+ CRM_SCLK_PLL = 0x02 /*!< select phase locking loop clock as sclk */
+} crm_sclk_type;
+
+/**
+ * @brief crm clkout index
+ */
+typedef enum
+{
+ CRM_CLKOUT_INDEX_1 = 0x00, /*!< clkout1 */
+ CRM_CLKOUT_INDEX_2 = 0x01 /*!< clkout2 */
+} crm_clkout_index_type;
+
+/**
+ * @brief crm clkout1 select
+ */
+typedef enum
+{
+ CRM_CLKOUT1_HICK = 0x00, /*!< output high speed internal clock to clkout1 pin */
+ CRM_CLKOUT1_LEXT = 0x01, /*!< output low speed external crystal to clkout1 pin */
+ CRM_CLKOUT1_HEXT = 0x02, /*!< output high speed external crystal to clkout1 pin */
+ CRM_CLKOUT1_PLL = 0x03 /*!< output phase locking loop clock to clkout1 pin */
+} crm_clkout1_select_type;
+
+/**
+ * @brief crm clkout2 select
+ */
+typedef enum
+{
+ CRM_CLKOUT2_SCLK = 0x00, /*!< output system clock to clkout2 pin */
+ CRM_CLKOUT2_HEXT = 0x02, /*!< output high speed external crystal to clkout2 pin */
+ CRM_CLKOUT2_PLL = 0x03, /*!< output phase locking loop clock to clkout2 pin */
+ CRM_CLKOUT2_USB = 0x10, /*!< output usbclk to clkout2 pin */
+ CRM_CLKOUT2_ADC = 0x11, /*!< output adcclk to clkout2 pin */
+ CRM_CLKOUT2_HICK = 0x12, /*!< output high speed internal clock to clkout2 pin */
+ CRM_CLKOUT2_LICK = 0x13, /*!< output low speed internal clock to clkout2 pin */
+ CRM_CLKOUT2_LEXT = 0x14 /*!< output low speed external crystal to clkout2 pin */
+} crm_clkout2_select_type;
+
+/**
+ * @brief crm clkout division1
+ */
+typedef enum
+{
+ CRM_CLKOUT_DIV1_1 = 0x00, /*!< clkout division1 div1 */
+ CRM_CLKOUT_DIV1_2 = 0x04, /*!< clkout division1 div2 */
+ CRM_CLKOUT_DIV1_3 = 0x05, /*!< clkout division1 div3 */
+ CRM_CLKOUT_DIV1_4 = 0x06, /*!< clkout division1 div4 */
+ CRM_CLKOUT_DIV1_5 = 0x07 /*!< clkout division1 div5 */
+} crm_clkout_div1_type;
+
+/**
+ * @brief crm clkout division2
+ */
+typedef enum
+{
+ CRM_CLKOUT_DIV2_1 = 0x00, /*!< clkout division2 div1 */
+ CRM_CLKOUT_DIV2_2 = 0x08, /*!< clkout division2 div2 */
+ CRM_CLKOUT_DIV2_4 = 0x09, /*!< clkout division2 div4 */
+ CRM_CLKOUT_DIV2_8 = 0x0A, /*!< clkout division2 div8 */
+ CRM_CLKOUT_DIV2_16 = 0x0B, /*!< clkout division2 div16 */
+ CRM_CLKOUT_DIV2_64 = 0x0C, /*!< clkout division2 div64 */
+ CRM_CLKOUT_DIV2_128 = 0x0D, /*!< clkout division2 div128 */
+ CRM_CLKOUT_DIV2_256 = 0x0E, /*!< clkout division2 div256 */
+ CRM_CLKOUT_DIV2_512 = 0x0F /*!< clkout division2 div512 */
+} crm_clkout_div2_type;
+
+/**
+ * @brief crm auto step mode
+ */
+typedef enum
+{
+ CRM_AUTO_STEP_MODE_DISABLE = 0x00, /*!< disable auto step mode */
+ CRM_AUTO_STEP_MODE_ENABLE = 0x03 /*!< enable auto step mode */
+} crm_auto_step_mode_type;
+
+/**
+ * @brief crm usb 48 mhz clock source select
+ */
+typedef enum
+{
+ CRM_USB_CLOCK_SOURCE_PLL = 0x00, /*!< select phase locking loop clock as usb clock source */
+ CRM_USB_CLOCK_SOURCE_HICK = 0x01 /*!< select high speed internal clock as usb clock source */
+} crm_usb_clock_source_type;
+
+/**
+ * @brief crm hick as system clock frequency select
+ */
+typedef enum
+{
+ CRM_HICK_SCLK_8MHZ = 0x00, /*!< fixed 8 mhz when hick is selected as sclk */
+ CRM_HICK_SCLK_48MHZ = 0x01 /*!< 8 mhz or 48 mhz depend on hickdiv when hick is selected as sclk */
+} crm_hick_sclk_frequency_type;
+
+/**
+ * @brief crm emac output pulse width
+ */
+typedef enum
+{
+ CRM_EMAC_PULSE_125MS = 0x00, /*!< emac output pulse width 125ms */
+ CRM_EMAC_PULSE_1SCLK = 0x01 /*!< emac output pulse width 1 system clock */
+} crm_emac_output_pulse_type;
+
+/**
+ * @brief crm clocks freqency structure
+ */
+typedef struct
+{
+ uint32_t sclk_freq; /*!< system clock frequency */
+ uint32_t ahb_freq; /*!< ahb bus clock frequency */
+ uint32_t apb2_freq; /*!< apb2 bus clock frequency */
+ uint32_t apb1_freq; /*!< apb1 bus clock frequency */
+} crm_clocks_freq_type;
+
+/**
+ * @brief type define crm register all
+ */
+typedef struct
+{
+ /**
+ * @brief crm ctrl register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t hicken : 1; /* [0] */
+ __IO uint32_t hickstbl : 1; /* [1] */
+ __IO uint32_t hicktrim : 6; /* [7:2] */
+ __IO uint32_t hickcal : 8; /* [15:8] */
+ __IO uint32_t hexten : 1; /* [16] */
+ __IO uint32_t hextstbl : 1; /* [17] */
+ __IO uint32_t hextbyps : 1; /* [18] */
+ __IO uint32_t cfden : 1; /* [19] */
+ __IO uint32_t reserved1 : 4; /* [23:20] */
+ __IO uint32_t pllen : 1; /* [24] */
+ __IO uint32_t pllstbl : 1; /* [25] */
+ __IO uint32_t reserved2 : 6; /* [31:26] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief crm pllcfg register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t pllcfg;
+ struct
+ {
+ __IO uint32_t pllms : 4; /* [3:0] */
+ __IO uint32_t reserved1 : 2; /* [5:4] */
+ __IO uint32_t pllns : 9; /* [14:6] */
+ __IO uint32_t reserved2 : 1; /* [15] */
+ __IO uint32_t pllfr : 3; /* [18:16] */
+ __IO uint32_t reserved3 : 3; /* [21:19] */
+ __IO uint32_t pllrcs : 1; /* [22] */
+ __IO uint32_t reserved4 : 9; /* [31:23] */
+ } pllcfg_bit;
+ };
+
+ /**
+ * @brief crm cfg register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t cfg;
+ struct
+ {
+ __IO uint32_t sclksel : 2; /* [1:0] */
+ __IO uint32_t sclksts : 2; /* [3:2] */
+ __IO uint32_t ahbdiv : 4; /* [7:4] */
+ __IO uint32_t reserved1 : 2; /* [9:8] */
+ __IO uint32_t apb1div : 3; /* [12:10] */
+ __IO uint32_t apb2div : 3; /* [15:13] */
+ __IO uint32_t ertcdiv : 5; /* [20:16] */
+ __IO uint32_t clkout1_sel : 2; /* [22:21] */
+ __IO uint32_t reserved2 : 1; /* [23] */
+ __IO uint32_t clkout1div1 : 3; /* [26:24] */
+ __IO uint32_t clkout2div1 : 3; /* [29:27] */
+ __IO uint32_t clkout2_sel1 : 2; /* [31:30] */
+ } cfg_bit;
+ };
+
+ /**
+ * @brief crm clkint register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t clkint;
+ struct
+ {
+ __IO uint32_t lickstblf : 1; /* [0] */
+ __IO uint32_t lextstblf : 1; /* [1] */
+ __IO uint32_t hickstblf : 1; /* [2] */
+ __IO uint32_t hextstblf : 1; /* [3] */
+ __IO uint32_t pllstblf : 1; /* [4] */
+ __IO uint32_t reserved1 : 2; /* [6:5] */
+ __IO uint32_t cfdf : 1; /* [7] */
+ __IO uint32_t lickstblien : 1; /* [8] */
+ __IO uint32_t lextstblien : 1; /* [9] */
+ __IO uint32_t hickstblien : 1; /* [10] */
+ __IO uint32_t hextstblien : 1; /* [11] */
+ __IO uint32_t pllstblien : 1; /* [12] */
+ __IO uint32_t reserved2 : 3; /* [15:13] */
+ __IO uint32_t lickstblfc : 1; /* [16] */
+ __IO uint32_t lextstblfc : 1; /* [17] */
+ __IO uint32_t hickstblfc : 1; /* [18] */
+ __IO uint32_t hextstblfc : 1; /* [19] */
+ __IO uint32_t pllstblfc : 1; /* [20] */
+ __IO uint32_t reserved3 : 2; /* [22:21] */
+ __IO uint32_t cfdfc : 1; /* [23] */
+ __IO uint32_t reserved4 : 8; /* [31:24] */
+ } clkint_bit;
+ };
+
+ /**
+ * @brief crm ahbrst1 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ahbrst1;
+#if defined (AT32F435xx)
+ struct
+ {
+ __IO uint32_t gpioarst : 1; /* [0] */
+ __IO uint32_t gpiobrst : 1; /* [1] */
+ __IO uint32_t gpiocrst : 1; /* [2] */
+ __IO uint32_t gpiodrst : 1; /* [3] */
+ __IO uint32_t gpioerst : 1; /* [4] */
+ __IO uint32_t gpiofrst : 1; /* [5] */
+ __IO uint32_t gpiogrst : 1; /* [6] */
+ __IO uint32_t gpiohrst : 1; /* [7] */
+ __IO uint32_t reserved1 : 4; /* [11:8] */
+ __IO uint32_t crcrst : 1; /* [12] */
+ __IO uint32_t reserved2 : 8; /* [20:13] */
+ __IO uint32_t edmarst : 1; /* [21] */
+ __IO uint32_t dma1rst : 1; /* [22] */
+ __IO uint32_t reserved3 : 1; /* [23] */
+ __IO uint32_t dma2rst : 1; /* [24] */
+ __IO uint32_t reserved4 : 4; /* [28:25] */
+ __IO uint32_t otgfs2rst : 1; /* [29] */
+ __IO uint32_t reserved5 : 2; /* [31:30] */
+ } ahbrst1_bit;
+#endif
+
+#if defined (AT32F437xx)
+ struct
+ {
+ __IO uint32_t gpioarst : 1; /* [0] */
+ __IO uint32_t gpiobrst : 1; /* [1] */
+ __IO uint32_t gpiocrst : 1; /* [2] */
+ __IO uint32_t gpiodrst : 1; /* [3] */
+ __IO uint32_t gpioerst : 1; /* [4] */
+ __IO uint32_t gpiofrst : 1; /* [5] */
+ __IO uint32_t gpiogrst : 1; /* [6] */
+ __IO uint32_t gpiohrst : 1; /* [7] */
+ __IO uint32_t reserved1 : 4; /* [11:8] */
+ __IO uint32_t crcrst : 1; /* [12] */
+ __IO uint32_t reserved2 : 8; /* [20:13] */
+ __IO uint32_t edmarst : 1; /* [21] */
+ __IO uint32_t dma1rst : 1; /* [22] */
+ __IO uint32_t reserved3 : 1; /* [23] */
+ __IO uint32_t dma2rst : 1; /* [24] */
+ __IO uint32_t emacrst : 1; /* [25] */
+ __IO uint32_t reserved4 : 3; /* [28:26] */
+ __IO uint32_t otgfs2rst : 1; /* [29] */
+ __IO uint32_t reserved5 : 2; /* [31:30] */
+ } ahbrst1_bit;
+#endif
+ };
+
+ /**
+ * @brief crm ahbrst2 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t ahbrst2;
+ struct
+ {
+ __IO uint32_t dvprst : 1; /* [0] */
+ __IO uint32_t reserved1 : 6; /* [6:1] */
+ __IO uint32_t otgfs1rst : 1; /* [7] */
+ __IO uint32_t reserved2 : 7; /* [14:8] */
+ __IO uint32_t sdio1rst : 1; /* [15] */
+ __IO uint32_t reserved3 : 16;/* [31:16] */
+ } ahbrst2_bit;
+ };
+
+ /**
+ * @brief crm ahbrst3 register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t ahbrst3;
+ struct
+ {
+ __IO uint32_t xmcrst : 1; /* [0] */
+ __IO uint32_t qspi1rst : 1; /* [1] */
+ __IO uint32_t reserved1 : 12;/* [13:2] */
+ __IO uint32_t qspi2rst : 1; /* [14] */
+ __IO uint32_t sdio2rst : 1; /* [15] */
+ __IO uint32_t reserved3 : 16;/* [31:16] */
+ } ahbrst3_bit;
+ };
+
+ /**
+ * @brief crm reserved1 register, offset:0x1C
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief crm apb1rst register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t apb1rst;
+ struct
+ {
+ __IO uint32_t tmr2rst : 1; /* [0] */
+ __IO uint32_t tmr3rst : 1; /* [1] */
+ __IO uint32_t tmr4rst : 1; /* [2] */
+ __IO uint32_t tmr5rst : 1; /* [3] */
+ __IO uint32_t tmr6rst : 1; /* [4] */
+ __IO uint32_t tmr7rst : 1; /* [5] */
+ __IO uint32_t tmr12rst : 1; /* [6] */
+ __IO uint32_t tmr13rst : 1; /* [7] */
+ __IO uint32_t adc14rst : 1; /* [8] */
+ __IO uint32_t reserved1 : 2; /* [10:9] */
+ __IO uint32_t wwdtrst : 1; /* [11] */
+ __IO uint32_t reserved2 : 2; /* [13:12] */
+ __IO uint32_t spi2rst : 1; /* [14] */
+ __IO uint32_t spi3rst : 1; /* [15] */
+ __IO uint32_t reserved3 : 1; /* [16] */
+ __IO uint32_t usart2rst : 1; /* [17] */
+ __IO uint32_t usart3rst : 1; /* [18] */
+ __IO uint32_t uart4rst : 1; /* [19] */
+ __IO uint32_t uart5rst : 1; /* [20] */
+ __IO uint32_t i2c1rst : 1; /* [21] */
+ __IO uint32_t i2c2rst : 1; /* [22] */
+ __IO uint32_t i2c3rst : 1; /* [23] */
+ __IO uint32_t reserved4 : 1; /* [24] */
+ __IO uint32_t can1rst : 1; /* [25] */
+ __IO uint32_t can2rst : 1; /* [26] */
+ __IO uint32_t reserved5 : 1; /* [27] */
+ __IO uint32_t pwcrst : 1; /* [28] */
+ __IO uint32_t dacrst : 1; /* [29] */
+ __IO uint32_t uart7rst : 1; /* [30] */
+ __IO uint32_t uart8rst : 1; /* [31] */
+ } apb1rst_bit;
+ };
+
+ /**
+ * @brief crm apb2rst register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t apb2rst;
+ struct
+ {
+ __IO uint32_t tmr1rst : 1; /* [0] */
+ __IO uint32_t tmr8rst : 1; /* [1] */
+ __IO uint32_t reserved1 : 2; /* [3:2] */
+ __IO uint32_t usart1rst : 1; /* [4] */
+ __IO uint32_t usart6rst : 1; /* [5] */
+ __IO uint32_t reserved2 : 2; /* [7:6] */
+ __IO uint32_t adcrst : 1; /* [8] */
+ __IO uint32_t reserved3 : 3; /* [11:9] */
+ __IO uint32_t spi1rst : 1; /* [12] */
+ __IO uint32_t spi4rst : 1; /* [13] */
+ __IO uint32_t scfgrst : 1; /* [14] */
+ __IO uint32_t reserved4 : 1; /* [15] */
+ __IO uint32_t tmr9rst : 1; /* [16] */
+ __IO uint32_t tmr10rst : 1; /* [17] */
+ __IO uint32_t tmr11rst : 1; /* [18] */
+ __IO uint32_t reserved5 : 1; /* [19] */
+ __IO uint32_t tmr20rst : 1; /* [20] */
+ __IO uint32_t reserved6 : 8; /* [28:21] */
+ __IO uint32_t accrst : 1; /* [29] */
+ __IO uint32_t reserved7 : 2; /* [31:30] */
+ } apb2rst_bit;
+ };
+
+ /**
+ * @brief crm reserved2 register, offset:0x28~0x2C
+ */
+ __IO uint32_t reserved2[2];
+
+ /**
+ * @brief crm ahben1 register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t ahben1;
+#if defined (AT32F435xx)
+ struct
+ {
+ __IO uint32_t gpioaen : 1; /* [0] */
+ __IO uint32_t gpioben : 1; /* [1] */
+ __IO uint32_t gpiocen : 1; /* [2] */
+ __IO uint32_t gpioden : 1; /* [3] */
+ __IO uint32_t gpioeen : 1; /* [4] */
+ __IO uint32_t gpiofen : 1; /* [5] */
+ __IO uint32_t gpiogen : 1; /* [6] */
+ __IO uint32_t gpiohen : 1; /* [7] */
+ __IO uint32_t reserved1 : 4; /* [11:8] */
+ __IO uint32_t crcen : 1; /* [12] */
+ __IO uint32_t reserved2 : 8; /* [20:13] */
+ __IO uint32_t edmaen : 1; /* [21] */
+ __IO uint32_t dma1en : 1; /* [22] */
+ __IO uint32_t reserved3 : 1; /* [23] */
+ __IO uint32_t dma2en : 1; /* [24] */
+ __IO uint32_t reserved4 : 4; /* [28:25] */
+ __IO uint32_t otgfs2en : 1; /* [29] */
+ __IO uint32_t reserved5 : 2; /* [31:30] */
+ } ahben1_bit;
+#endif
+
+#if defined (AT32F437xx)
+ struct
+ {
+ __IO uint32_t gpioaen : 1; /* [0] */
+ __IO uint32_t gpioben : 1; /* [1] */
+ __IO uint32_t gpiocen : 1; /* [2] */
+ __IO uint32_t gpioden : 1; /* [3] */
+ __IO uint32_t gpioeen : 1; /* [4] */
+ __IO uint32_t gpiofen : 1; /* [5] */
+ __IO uint32_t gpiogen : 1; /* [6] */
+ __IO uint32_t gpiohen : 1; /* [7] */
+ __IO uint32_t reserved1 : 4; /* [11:8] */
+ __IO uint32_t crcen : 1; /* [12] */
+ __IO uint32_t reserved2 : 8; /* [20:13] */
+ __IO uint32_t edmaen : 1; /* [21] */
+ __IO uint32_t dma1en : 1; /* [22] */
+ __IO uint32_t reserved3 : 1; /* [23] */
+ __IO uint32_t dma2en : 1; /* [24] */
+ __IO uint32_t emacen : 1; /* [25] */
+ __IO uint32_t reserved4 : 3; /* [28:26] */
+ __IO uint32_t otgfs2en : 1; /* [29] */
+ __IO uint32_t reserved5 : 2; /* [31:30] */
+ } ahben1_bit;
+#endif
+ };
+
+ /**
+ * @brief crm ahben2 register, offset:0x34
+ */
+ union
+ {
+ __IO uint32_t ahben2;
+ struct
+ {
+ __IO uint32_t dvpen : 1; /* [0] */
+ __IO uint32_t reserved1 : 6; /* [6:1] */
+ __IO uint32_t otgfs1en : 1; /* [7] */
+ __IO uint32_t reserved2 : 7; /* [14:8] */
+ __IO uint32_t sdio1en : 1; /* [15] */
+ __IO uint32_t reserved3 : 16;/* [31:16] */
+ } ahben2_bit;
+ };
+
+ /**
+ * @brief crm ahben3 register, offset:0x38
+ */
+ union
+ {
+ __IO uint32_t ahben3;
+ struct
+ {
+ __IO uint32_t xmcen : 1; /* [0] */
+ __IO uint32_t qspi1en : 1; /* [1] */
+ __IO uint32_t reserved1 : 12;/* [13:2] */
+ __IO uint32_t qspi2en : 1; /* [14] */
+ __IO uint32_t sdio2en : 1; /* [15] */
+ __IO uint32_t reserved3 : 16;/* [31:16] */
+ } ahben3_bit;
+ };
+
+ /**
+ * @brief crm reserved3 register, offset:0x3C
+ */
+ __IO uint32_t reserved3;
+
+ /**
+ * @brief crm apb1en register, offset:0x40
+ */
+ union
+ {
+ __IO uint32_t apb1en;
+ struct
+ {
+ __IO uint32_t tmr2en : 1; /* [0] */
+ __IO uint32_t tmr3en : 1; /* [1] */
+ __IO uint32_t tmr4en : 1; /* [2] */
+ __IO uint32_t tmr5en : 1; /* [3] */
+ __IO uint32_t tmr6en : 1; /* [4] */
+ __IO uint32_t tmr7en : 1; /* [5] */
+ __IO uint32_t tmr12en : 1; /* [6] */
+ __IO uint32_t tmr13en : 1; /* [7] */
+ __IO uint32_t adc14en : 1; /* [8] */
+ __IO uint32_t reserved1 : 2; /* [10:9] */
+ __IO uint32_t wwdten : 1; /* [11] */
+ __IO uint32_t reserved2 : 2; /* [13:12] */
+ __IO uint32_t spi2en : 1; /* [14] */
+ __IO uint32_t spi3en : 1; /* [15] */
+ __IO uint32_t reserved3 : 1; /* [16] */
+ __IO uint32_t usart2en : 1; /* [17] */
+ __IO uint32_t usart3en : 1; /* [18] */
+ __IO uint32_t uart4en : 1; /* [19] */
+ __IO uint32_t uart5en : 1; /* [20] */
+ __IO uint32_t i2c1en : 1; /* [21] */
+ __IO uint32_t i2c2en : 1; /* [22] */
+ __IO uint32_t i2c3en : 1; /* [23] */
+ __IO uint32_t reserved4 : 1; /* [24] */
+ __IO uint32_t can1en : 1; /* [25] */
+ __IO uint32_t can2en : 1; /* [26] */
+ __IO uint32_t reserved5 : 1; /* [27] */
+ __IO uint32_t pwcen : 1; /* [28] */
+ __IO uint32_t dacen : 1; /* [29] */
+ __IO uint32_t uart7en : 1; /* [30] */
+ __IO uint32_t uart8en : 1; /* [31] */
+ } apb1en_bit;
+ };
+
+ /**
+ * @brief crm apb2en register, offset:0x44
+ */
+ union
+ {
+ __IO uint32_t apb2en;
+ struct
+ {
+ __IO uint32_t tmr1en : 1; /* [0] */
+ __IO uint32_t tmr8en : 1; /* [1] */
+ __IO uint32_t reserved1 : 2; /* [3:2] */
+ __IO uint32_t usart1en : 1; /* [4] */
+ __IO uint32_t usart6en : 1; /* [5] */
+ __IO uint32_t reserved2 : 2; /* [7:6] */
+ __IO uint32_t adcen : 1; /* [8] */
+ __IO uint32_t reserved3 : 3; /* [11:9] */
+ __IO uint32_t spi1en : 1; /* [12] */
+ __IO uint32_t spi4en : 1; /* [13] */
+ __IO uint32_t scfgen : 1; /* [14] */
+ __IO uint32_t reserved4 : 1; /* [15] */
+ __IO uint32_t tmr9en : 1; /* [16] */
+ __IO uint32_t tmr10en : 1; /* [17] */
+ __IO uint32_t tmr11en : 1; /* [18] */
+ __IO uint32_t reserved5 : 1; /* [19] */
+ __IO uint32_t tmr20en : 1; /* [20] */
+ __IO uint32_t reserved6 : 8; /* [28:21] */
+ __IO uint32_t accen : 1; /* [29] */
+ __IO uint32_t reserved7 : 2; /* [31:30] */
+ } apb2en_bit;
+ };
+
+ /**
+ * @brief crm reserved4 register, offset:0x48~0x4C
+ */
+ __IO uint32_t reserved4[2];
+
+ /**
+ * @brief crm ahblpen1 register, offset:0x50
+ */
+ union
+ {
+ __IO uint32_t ahblpen1;
+#if defined (AT32F435xx)
+ struct
+ {
+ __IO uint32_t gpioalpen : 1; /* [0] */
+ __IO uint32_t gpioblpen : 1; /* [1] */
+ __IO uint32_t gpioclpen : 1; /* [2] */
+ __IO uint32_t gpiodlpen : 1; /* [3] */
+ __IO uint32_t gpioelpen : 1; /* [4] */
+ __IO uint32_t gpioflpen : 1; /* [5] */
+ __IO uint32_t gpioglpen : 1; /* [6] */
+ __IO uint32_t gpiohlpen : 1; /* [7] */
+ __IO uint32_t reserved1 : 4; /* [11:8] */
+ __IO uint32_t crclpen : 1; /* [12] */
+ __IO uint32_t reserved2 : 8; /* [20:13] */
+ __IO uint32_t edmalpen : 1; /* [21] */
+ __IO uint32_t dma1lpen : 1; /* [22] */
+ __IO uint32_t reserved3 : 1; /* [23] */
+ __IO uint32_t dma2lpen : 1; /* [24] */
+ __IO uint32_t reserved4 : 4; /* [28:25] */
+ __IO uint32_t otgfs2lpen : 1; /* [29] */
+ __IO uint32_t reserved5 : 2; /* [31:30] */
+ } ahblpen1_bit;
+#endif
+
+#if defined (AT32F437xx)
+ struct
+ {
+ __IO uint32_t gpioalpen : 1; /* [0] */
+ __IO uint32_t gpioblpen : 1; /* [1] */
+ __IO uint32_t gpioclpen : 1; /* [2] */
+ __IO uint32_t gpiodlpen : 1; /* [3] */
+ __IO uint32_t gpioelpen : 1; /* [4] */
+ __IO uint32_t gpioflpen : 1; /* [5] */
+ __IO uint32_t gpioglpen : 1; /* [6] */
+ __IO uint32_t gpiohlpen : 1; /* [7] */
+ __IO uint32_t reserved1 : 4; /* [11:8] */
+ __IO uint32_t crclpen : 1; /* [12] */
+ __IO uint32_t reserved2 : 8; /* [20:13] */
+ __IO uint32_t edmalpen : 1; /* [21] */
+ __IO uint32_t dma1lpen : 1; /* [22] */
+ __IO uint32_t reserved3 : 1; /* [23] */
+ __IO uint32_t dma2lpen : 1; /* [24] */
+ __IO uint32_t emaclpen : 1; /* [25] */
+ __IO uint32_t reserved4 : 3; /* [28:26] */
+ __IO uint32_t otgfs2lpen : 1; /* [29] */
+ __IO uint32_t reserved5 : 2; /* [31:30] */
+ } ahblpen1_bit;
+#endif
+ };
+
+ /**
+ * @brief crm ahblpen2 register, offset:0x54
+ */
+ union
+ {
+ __IO uint32_t ahblpen2;
+ struct
+ {
+ __IO uint32_t dvplpen : 1; /* [0] */
+ __IO uint32_t reserved1 : 6; /* [6:1] */
+ __IO uint32_t otgfs1lpen : 1; /* [7] */
+ __IO uint32_t reserved2 : 7; /* [14:8] */
+ __IO uint32_t sdio1lpen : 1; /* [15] */
+ __IO uint32_t reserved3 : 16;/* [31:16] */
+ } ahblpen2_bit;
+ };
+
+ /**
+ * @brief crm ahblpen3 register, offset:0x58
+ */
+ union
+ {
+ __IO uint32_t ahblpen3;
+ struct
+ {
+ __IO uint32_t xmclpen : 1; /* [0] */
+ __IO uint32_t qspi1lpen : 1; /* [1] */
+ __IO uint32_t reserved1 : 12;/* [13:2] */
+ __IO uint32_t qspi2lpen : 1; /* [14] */
+ __IO uint32_t sdio2lpen : 1; /* [15] */
+ __IO uint32_t reserved3 : 16;/* [31:16] */
+ } ahblpen3_bit;
+ };
+
+ /**
+ * @brief crm reserved5 register, offset:0x5C
+ */
+ __IO uint32_t reserved5;
+
+ /**
+ * @brief crm apb1lpen register, offset:0x60
+ */
+ union
+ {
+ __IO uint32_t apb1lpen;
+ struct
+ {
+ __IO uint32_t tmr2lpen : 1; /* [0] */
+ __IO uint32_t tmr3lpen : 1; /* [1] */
+ __IO uint32_t tmr4lpen : 1; /* [2] */
+ __IO uint32_t tmr5lpen : 1; /* [3] */
+ __IO uint32_t tmr6lpen : 1; /* [4] */
+ __IO uint32_t tmr7lpen : 1; /* [5] */
+ __IO uint32_t tmr12lpen : 1; /* [6] */
+ __IO uint32_t tmr13lpen : 1; /* [7] */
+ __IO uint32_t adc14lpen : 1; /* [8] */
+ __IO uint32_t reserved1 : 2; /* [10:9] */
+ __IO uint32_t wwdtlpen : 1; /* [11] */
+ __IO uint32_t reserved2 : 2; /* [13:12] */
+ __IO uint32_t spi2lpen : 1; /* [14] */
+ __IO uint32_t spi3lpen : 1; /* [15] */
+ __IO uint32_t reserved3 : 1; /* [16] */
+ __IO uint32_t usart2lpen : 1; /* [17] */
+ __IO uint32_t usart3lpen : 1; /* [18] */
+ __IO uint32_t uart4lpen : 1; /* [19] */
+ __IO uint32_t uart5lpen : 1; /* [20] */
+ __IO uint32_t i2c1lpen : 1; /* [21] */
+ __IO uint32_t i2c2lpen : 1; /* [22] */
+ __IO uint32_t i2c3lpen : 1; /* [23] */
+ __IO uint32_t reserved4 : 1; /* [24] */
+ __IO uint32_t can1lpen : 1; /* [25] */
+ __IO uint32_t can2lpen : 1; /* [26] */
+ __IO uint32_t reserved5 : 1; /* [27] */
+ __IO uint32_t pwclpen : 1; /* [28] */
+ __IO uint32_t daclpen : 1; /* [29] */
+ __IO uint32_t uart7lpen : 1; /* [30] */
+ __IO uint32_t uart8lpen : 1; /* [31] */
+ } apb1lpen_bit;
+ };
+
+ /**
+ * @brief crm apb2lpen register, offset:0x64
+ */
+ union
+ {
+ __IO uint32_t apb2lpen;
+ struct
+ {
+ __IO uint32_t tmr1lpen : 1; /* [0] */
+ __IO uint32_t tmr8lpen : 1; /* [1] */
+ __IO uint32_t reserved1 : 2; /* [3:2] */
+ __IO uint32_t usart1lpen : 1; /* [4] */
+ __IO uint32_t usart6lpen : 1; /* [5] */
+ __IO uint32_t reserved2 : 2; /* [7:6] */
+ __IO uint32_t adclpen : 1; /* [8] */
+ __IO uint32_t reserved3 : 3; /* [11:9] */
+ __IO uint32_t spi1lpen : 1; /* [12] */
+ __IO uint32_t spi4lpen : 1; /* [13] */
+ __IO uint32_t scfglpen : 1; /* [14] */
+ __IO uint32_t reserved4 : 1; /* [15] */
+ __IO uint32_t tmr9lpen : 1; /* [16] */
+ __IO uint32_t tmr10lpen : 1; /* [17] */
+ __IO uint32_t tmr11lpen : 1; /* [18] */
+ __IO uint32_t reserved5 : 1; /* [19] */
+ __IO uint32_t tmr20lpen : 1; /* [20] */
+ __IO uint32_t reserved6 : 8; /* [28:21] */
+ __IO uint32_t acclpen : 1; /* [29] */
+ __IO uint32_t reserved7 : 2; /* [31:30] */
+ } apb2lpen_bit;
+ };
+
+ /**
+ * @brief crm reserved6 register, offset:0x68~0x6C
+ */
+ __IO uint32_t reserved6[2];
+
+ /**
+ * @brief crm bpdc register, offset:0x70
+ */
+ union
+ {
+ __IO uint32_t bpdc;
+ struct
+ {
+ __IO uint32_t lexten : 1; /* [0] */
+ __IO uint32_t lextstbl : 1; /* [1] */
+ __IO uint32_t lextbyps : 1; /* [2] */
+ __IO uint32_t reserved1 : 5; /* [7:3] */
+ __IO uint32_t ertcsel : 2; /* [9:8] */
+ __IO uint32_t reserved2 : 5; /* [14:10] */
+ __IO uint32_t ertcen : 1; /* [15] */
+ __IO uint32_t bpdrst : 1; /* [16] */
+ __IO uint32_t reserved3 : 15;/* [31:17] */
+ } bpdc_bit;
+ };
+
+ /**
+ * @brief crm ctrlsts register, offset:0x74
+ */
+ union
+ {
+ __IO uint32_t ctrlsts;
+ struct
+ {
+ __IO uint32_t licken : 1; /* [0] */
+ __IO uint32_t lickstbl : 1; /* [1] */
+ __IO uint32_t reserved1 : 22;/* [23:2] */
+ __IO uint32_t rstfc : 1; /* [24] */
+ __IO uint32_t reserved2 : 1; /* [25] */
+ __IO uint32_t nrstf : 1; /* [26] */
+ __IO uint32_t porrstf : 1; /* [27] */
+ __IO uint32_t swrstf : 1; /* [28] */
+ __IO uint32_t wdtrstf : 1; /* [29] */
+ __IO uint32_t wwdtrstf : 1; /* [30] */
+ __IO uint32_t lprstf : 1; /* [31] */
+ } ctrlsts_bit;
+ };
+
+ /**
+ * @brief crm reserved7 register, offset:0x78~0x9C
+ */
+ __IO uint32_t reserved7[10];
+
+ /**
+ * @brief crm misc1 register, offset:0xA0
+ */
+ union
+ {
+ __IO uint32_t misc1;
+ struct
+ {
+ __IO uint32_t hickcal_key : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 4; /* [11:8] */
+ __IO uint32_t hickdiv : 1; /* [12] */
+ __IO uint32_t hick_to_usb : 1; /* [13] */
+ __IO uint32_t hick_to_sclk : 1; /* [14] */
+ __IO uint32_t reserved2 : 1; /* [15] */
+ __IO uint32_t clkout2_sel2 : 4; /* [19:16] */
+ __IO uint32_t reserved3 : 4; /* [23:20] */
+ __IO uint32_t clkout1div2 : 4; /* [27:24] */
+ __IO uint32_t clkout2div2 : 4; /* [31:28] */
+ } misc1_bit;
+ };
+
+ /**
+ * @brief crm misc2 register, offset:0xA4
+ */
+ union
+ {
+ __IO uint32_t misc2;
+ struct
+ {
+ __IO uint32_t reserved1 : 4; /* [3:0] */
+ __IO uint32_t auto_step_en : 2; /* [5:4] */
+ __IO uint32_t reserved2 : 2; /* [7:6] */
+ __IO uint32_t clk_to_tmr : 1; /* [8] */
+ __IO uint32_t emac_pps_sel : 1; /* [9] */
+ __IO uint32_t reserved3 : 2; /* [11:10] */
+ __IO uint32_t usbdiv : 4; /* [15:12] */
+ __IO uint32_t reserved4 : 16;/* [31:16] */
+ } misc2_bit;
+ };
+
+} crm_type;
+
+/**
+ * @}
+ */
+
+#define CRM ((crm_type *) CRM_BASE)
+
+/** @defgroup CRM_exported_functions
+ * @{
+ */
+
+void crm_reset(void);
+void crm_lext_bypass(confirm_state new_state);
+void crm_hext_bypass(confirm_state new_state);
+flag_status crm_flag_get(uint32_t flag);
+error_status crm_hext_stable_wait(void);
+void crm_hick_clock_trimming_set(uint8_t trim_value);
+void crm_hick_clock_calibration_set(uint8_t cali_value);
+void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state);
+void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state);
+void crm_periph_lowpower_mode_enable(crm_periph_clock_lowpower_type value, confirm_state new_state);
+void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state);
+void crm_flag_clear(uint32_t flag);
+void crm_ertc_clock_select(crm_ertc_clock_type value);
+void crm_ertc_clock_enable(confirm_state new_state);
+void crm_ahb_div_set(crm_ahb_div_type value);
+void crm_apb1_div_set(crm_apb1_div_type value);
+void crm_apb2_div_set(crm_apb2_div_type value);
+void crm_usb_clock_div_set(crm_usb_div_type value);
+void crm_clock_failure_detection_enable(confirm_state new_state);
+void crm_battery_powered_domain_reset(confirm_state new_state);
+void crm_auto_step_mode_enable(confirm_state new_state);
+void crm_hick_divider_select(crm_hick_div_6_type value);
+void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value);
+void crm_usb_clock_source_select(crm_usb_clock_source_type value);
+void crm_clkout_to_tmr10_enable(confirm_state new_state);
+void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \
+ uint16_t pll_ms, crm_pll_fr_type pll_fr);
+void crm_sysclk_switch(crm_sclk_type value);
+crm_sclk_type crm_sysclk_switch_status_get(void);
+void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct);
+void crm_clock_out1_set(crm_clkout1_select_type clkout);
+void crm_clock_out2_set(crm_clkout2_select_type clkout);
+void crm_clkout_div_set(crm_clkout_index_type index, crm_clkout_div1_type div1, crm_clkout_div2_type div2);
+void crm_emac_output_pulse_set(crm_emac_output_pulse_type width);
+void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state);
+error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint32_t target_sclk_freq, \
+ uint16_t *ret_ms, uint16_t *ret_ns, uint16_t *ret_fr);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_dac.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_dac.h
new file mode 100644
index 0000000..a7ffee6
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_dac.h
@@ -0,0 +1,394 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_dac.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 dac header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_DAC_H
+#define __AT32F435_437_DAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+#define DAC1_D1DMAUDRF ((uint32_t)(0x00002000))
+#define DAC2_D2DMAUDRF ((uint32_t)(0x20000000))
+
+/** @defgroup DAC_exported_types
+ * @{
+ */
+
+/**
+ * @brief dac select type
+ */
+typedef enum
+{
+ DAC1_SELECT = 0x01, /*!< dac1 select */
+ DAC2_SELECT = 0x02 /*!< dac2 select */
+} dac_select_type;
+
+/**
+ * @brief dac trigger type
+ */
+typedef enum
+{
+ DAC_TMR6_TRGOUT_EVENT = 0x00, /*!< dac trigger selection:timer6 trgout event */
+ DAC_TMR8_TRGOUT_EVENT = 0x01, /*!< dac trigger selection:timer8 trgout event */
+ DAC_TMR7_TRGOUT_EVENT = 0x02, /*!< dac trigger selection:timer7 trgout event */
+ DAC_TMR5_TRGOUT_EVENT = 0x03, /*!< dac trigger selection:timer5 trgout event */
+ DAC_TMR2_TRGOUT_EVENT = 0x04, /*!< dac trigger selection:timer2 trgout event */
+ DAC_TMR4_TRGOUT_EVENT = 0x05, /*!< dac trigger selection:timer4 trgout event */
+ DAC_EXTERNAL_INTERRUPT_LINE_9 = 0x06, /*!< dac trigger selection:external line9 */
+ DAC_SOFTWARE_TRIGGER = 0x07 /*!< dac trigger selection:software trigger */
+} dac_trigger_type;
+
+/**
+ * @brief dac wave type
+ */
+typedef enum
+{
+ DAC_WAVE_GENERATE_NONE = 0x00, /*!< dac wave generation disabled */
+ DAC_WAVE_GENERATE_NOISE = 0x01, /*!< dac noise wave generation enabled */
+ DAC_WAVE_GENERATE_TRIANGLE = 0x02 /*!< dac triangle wave generation enabled */
+} dac_wave_type;
+
+/**
+ * @brief dac mask amplitude type
+ */
+typedef enum
+{
+ DAC_LSFR_BIT0_AMPLITUDE_1 = 0x00, /*!< unmask bit0/ triangle amplitude equal to 1 */
+ DAC_LSFR_BIT10_AMPLITUDE_3 = 0x01, /*!< unmask bit[1:0]/ triangle amplitude equal to 3 */
+ DAC_LSFR_BIT20_AMPLITUDE_7 = 0x02, /*!< unmask bit[2:0]/ triangle amplitude equal to 7 */
+ DAC_LSFR_BIT30_AMPLITUDE_15 = 0x03, /*!< unmask bit[3:0]/ triangle amplitude equal to 15 */
+ DAC_LSFR_BIT40_AMPLITUDE_31 = 0x04, /*!< unmask bit[4:0]/ triangle amplitude equal to 31 */
+ DAC_LSFR_BIT50_AMPLITUDE_63 = 0x05, /*!< unmask bit[5:0]/ triangle amplitude equal to 63 */
+ DAC_LSFR_BIT60_AMPLITUDE_127 = 0x06, /*!< unmask bit[6:0]/ triangle amplitude equal to 127 */
+ DAC_LSFR_BIT70_AMPLITUDE_255 = 0x07, /*!< unmask bit[7:0]/ triangle amplitude equal to 255 */
+ DAC_LSFR_BIT80_AMPLITUDE_511 = 0x08, /*!< unmask bit[8:0]/ triangle amplitude equal to 511 */
+ DAC_LSFR_BIT90_AMPLITUDE_1023 = 0x09, /*!< unmask bit[9:0]/ triangle amplitude equal to 1023 */
+ DAC_LSFR_BITA0_AMPLITUDE_2047 = 0x0A, /*!< unmask bit[10:0]/ triangle amplitude equal to 2047 */
+ DAC_LSFR_BITB0_AMPLITUDE_4095 = 0x0B /*!< unmask bit[11:0]/ triangle amplitude equal to 4095 */
+} dac_mask_amplitude_type;
+
+/**
+ * @brief dac1 aligned data type
+ */
+typedef enum
+{
+ DAC1_12BIT_RIGHT = 0x40007408, /*!< dac1 12-bit data right-aligned */
+ DAC1_12BIT_LEFT = 0x4000740C, /*!< dac1 12-bit data left-aligned */
+ DAC1_8BIT_RIGHT = 0x40007410 /*!< dac1 8-bit data right-aligned */
+} dac1_aligned_data_type;
+
+/**
+ * @brief dac2 aligned data type
+ */
+typedef enum
+{
+ DAC2_12BIT_RIGHT = 0x40007414, /*!< dac2 12-bit data right-aligned */
+ DAC2_12BIT_LEFT = 0x40007418, /*!< dac2 12-bit data left-aligned */
+ DAC2_8BIT_RIGHT = 0x4000741C /*!< dac2 8-bit data right-aligned */
+} dac2_aligned_data_type;
+
+/**
+ * @brief dac dual data type
+ */
+typedef enum
+{
+ DAC_DUAL_12BIT_RIGHT = 0x40007420, /*!divr_bit.fdiv = div)
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_exported_types
+ * @{
+ */
+
+/**
+ * @brief flash usd eopb0 type
+ */
+typedef enum
+{
+ FLASH_EOPB0_SRAM_512K = 0x00, /*!< sram 512k, flash zw area 128k */
+ FLASH_EOPB0_SRAM_448K = 0x01, /*!< sram 448k, flash zw area 192k */
+ FLASH_EOPB0_SRAM_384K = 0x02, /*!< sram 384k, flash zw area 256k */
+ FLASH_EOPB0_SRAM_320K = 0x03, /*!< sram 320k, flash zw area 320k */
+ FLASH_EOPB0_SRAM_256K = 0x04, /*!< sram 256k, flash zw area 384k */
+ FLASH_EOPB0_SRAM_192K = 0x05, /*!< sram 192k, flash zw area 448k */
+ FLASH_EOPB0_SRAM_128K = 0x06 /*!< sram 128k, flash zw area 512k */
+} flash_usd_eopb0_type;
+
+/**
+ * @brief flash clock divider type
+ */
+typedef enum
+{
+ FLASH_CLOCK_DIV_2 = 0x00, /*!< flash clock divide by 2 */
+ FLASH_CLOCK_DIV_3 = 0x01, /*!< flash clock divide by 3 */
+ FLASH_CLOCK_DIV_4 = 0x02 /*!< flash clock divide by 4 */
+} flash_clock_divider_type;
+
+/**
+ * @brief flash status type
+ */
+typedef enum
+{
+ FLASH_OPERATE_BUSY = 0x00, /*!< flash status is operate busy */
+ FLASH_PROGRAM_ERROR = 0x01, /*!< flash status is program error */
+ FLASH_EPP_ERROR = 0x02, /*!< flash status is epp error */
+ FLASH_OPERATE_DONE = 0x03, /*!< flash status is operate done */
+ FLASH_OPERATE_TIMEOUT = 0x04 /*!< flash status is operate timeout */
+} flash_status_type;
+
+/**
+ * @brief type define flash register all
+ */
+typedef struct
+{
+ /**
+ * @brief flash psr register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t psr;
+ struct
+ {
+ __IO uint32_t reserved1 : 12;/* [11:0] */
+ __IO uint32_t nzw_bst : 1; /* [12] */
+ __IO uint32_t nzw_bst_sts : 1; /* [13] */
+ __IO uint32_t reserved2 : 18;/* [31:14] */
+ } psr_bit;
+ };
+
+ /**
+ * @brief flash unlock register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t unlock;
+ struct
+ {
+ __IO uint32_t ukval : 32;/* [31:0] */
+ } unlock_bit;
+ };
+
+ /**
+ * @brief flash usd unlock register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t usd_unlock;
+ struct
+ {
+ __IO uint32_t usd_ukval : 32;/* [31:0] */
+ } usd_unlock_bit;
+ };
+
+ /**
+ * @brief flash sts register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t obf : 1; /* [0] */
+ __IO uint32_t reserved1 : 1; /* [1] */
+ __IO uint32_t prgmerr : 1; /* [2] */
+ __IO uint32_t reserved2 : 1; /* [3] */
+ __IO uint32_t epperr : 1; /* [4] */
+ __IO uint32_t odf : 1; /* [5] */
+ __IO uint32_t reserved3 : 26;/* [31:6] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief flash ctrl register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t fprgm : 1; /* [0] */
+ __IO uint32_t secers : 1; /* [1] */
+ __IO uint32_t bankers : 1; /* [2] */
+ __IO uint32_t blkers : 1; /* [3] */
+ __IO uint32_t usdprgm : 1; /* [4] */
+ __IO uint32_t usders : 1; /* [5] */
+ __IO uint32_t erstr : 1; /* [6] */
+ __IO uint32_t oplk : 1; /* [7] */
+ __IO uint32_t reserved1 : 1; /* [8] */
+ __IO uint32_t usdulks : 1; /* [9] */
+ __IO uint32_t errie : 1; /* [10] */
+ __IO uint32_t reserved2 : 1; /* [11] */
+ __IO uint32_t odfie : 1; /* [12] */
+ __IO uint32_t reserved3 : 19;/* [31:13] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief flash addr register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t addr;
+ struct
+ {
+ __IO uint32_t fa : 32;/* [31:0] */
+ } addr_bit;
+ };
+
+ /**
+ * @brief flash reserved1 register, offset:0x18
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief flash usd register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t usd;
+ struct
+ {
+ __IO uint32_t usderr : 1; /* [0] */
+ __IO uint32_t fap : 1; /* [1] */
+ __IO uint32_t wdt_ato_en : 1; /* [2] */
+ __IO uint32_t depslp_rst : 1; /* [3] */
+ __IO uint32_t stdby_rst : 1; /* [4] */
+ __IO uint32_t btopt : 1; /* [5] */
+ __IO uint32_t reserved1 : 1; /* [6] */
+ __IO uint32_t wdt_depslp : 1; /* [7] */
+ __IO uint32_t wdt_stdby : 1; /* [8] */
+ __IO uint32_t reserved2 : 1; /* [9] */
+ __IO uint32_t user_d0 : 8; /* [17:10] */
+ __IO uint32_t user_d1 : 8; /* [25:18] */
+ __IO uint32_t reserved3 : 6; /* [31:26] */
+ } usd_bit;
+ };
+
+ /**
+ * @brief flash epps0 register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t epps0;
+ struct
+ {
+ __IO uint32_t epps : 32;/* [31:0] */
+ } epps0_bit;
+ };
+
+ /**
+ * @brief flash reserved2 register, offset:0x28~0x24
+ */
+ __IO uint32_t reserved2[2];
+
+ /**
+ * @brief flash epps1 register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t epps1;
+ struct
+ {
+ __IO uint32_t epps : 32;/* [31:0] */
+ } epps1_bit;
+ };
+
+ /**
+ * @brief flash reserved3 register, offset:0x40~0x30
+ */
+ __IO uint32_t reserved3[5];
+
+ /**
+ * @brief flash unlock2 register, offset:0x44
+ */
+ union
+ {
+ __IO uint32_t unlock2;
+ struct
+ {
+ __IO uint32_t ukval : 32;/* [31:0] */
+ } unlock2_bit;
+ };
+
+ /**
+ * @brief flash reserved4 register, offset:0x48
+ */
+ __IO uint32_t reserved4;
+
+ /**
+ * @brief flash sts2 register, offset:0x4C
+ */
+ union
+ {
+ __IO uint32_t sts2;
+ struct
+ {
+ __IO uint32_t obf : 1; /* [0] */
+ __IO uint32_t reserved1 : 1; /* [1] */
+ __IO uint32_t prgmerr : 1; /* [2] */
+ __IO uint32_t reserved2 : 1; /* [3] */
+ __IO uint32_t epperr : 1; /* [4] */
+ __IO uint32_t odf : 1; /* [5] */
+ __IO uint32_t reserved3 : 26;/* [31:6] */
+ } sts2_bit;
+ };
+
+ /**
+ * @brief flash ctrl2 register, offset:0x50
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t fprgm : 1; /* [0] */
+ __IO uint32_t secers : 1; /* [1] */
+ __IO uint32_t bankers : 1; /* [2] */
+ __IO uint32_t blkers : 1; /* [3] */
+ __IO uint32_t reserved1 : 2; /* [5:4] */
+ __IO uint32_t erstr : 1; /* [6] */
+ __IO uint32_t oplk : 1; /* [7] */
+ __IO uint32_t reserved2 : 2; /* [9:8] */
+ __IO uint32_t errie : 1; /* [10] */
+ __IO uint32_t reserved3 : 1; /* [11] */
+ __IO uint32_t odfie : 1; /* [12] */
+ __IO uint32_t reserved4 : 19;/* [31:13] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief flash addr2 register, offset:0x54
+ */
+ union
+ {
+ __IO uint32_t addr2;
+ struct
+ {
+ __IO uint32_t fa : 32;/* [31:0] */
+ } addr2_bit;
+ };
+
+ /**
+ * @brief flash contr register, offset:0x58
+ */
+ union
+ {
+ __IO uint32_t contr;
+ struct
+ {
+ __IO uint32_t reserved1 : 31;/* [30:0] */
+ __IO uint32_t fcontr_en : 1; /* [31] */
+ } contr_bit;
+ };
+
+ /**
+ * @brief flash reserved5 register, offset:0x5C
+ */
+ __IO uint32_t reserved5;
+
+ /**
+ * @brief flash divr register, offset:0x60
+ */
+ union
+ {
+ __IO uint32_t divr;
+ struct
+ {
+ __IO uint32_t fdiv : 2; /* [1:0] */
+ __IO uint32_t reserved1 : 2; /* [3:2] */
+ __IO uint32_t fdiv_sts : 2; /* [5:4] */
+ __IO uint32_t reserved2 : 26;/* [31:6] */
+ } divr_bit;
+ };
+
+ /**
+ * @brief flash reserved6 register, offset:0xC4~0x64
+ */
+ __IO uint32_t reserved6[25];
+
+ /**
+ * @brief flash slib_sts2 register, offset:0xC8
+ */
+ union
+ {
+ __IO uint32_t slib_sts2;
+ struct
+ {
+ __IO uint32_t slib_inst_ss : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } slib_sts2_bit;
+ };
+
+ /**
+ * @brief flash slib_sts0 register, offset:0xCC
+ */
+ union
+ {
+ __IO uint32_t slib_sts0;
+ struct
+ {
+ __IO uint32_t reserved1 : 3; /* [2:0] */
+ __IO uint32_t slib_enf : 1; /* [3] */
+ __IO uint32_t reserved2 : 28;/* [31:4] */
+ } slib_sts0_bit;
+ };
+
+ /**
+ * @brief flash slib_sts1 register, offset:0xD0
+ */
+ union
+ {
+ __IO uint32_t slib_sts1;
+ struct
+ {
+ __IO uint32_t slib_ss : 16;/* [15:0] */
+ __IO uint32_t slib_es : 16;/* [31:16] */
+ } slib_sts1_bit;
+ };
+
+ /**
+ * @brief flash slib_pwd_clr register, offset:0xD4
+ */
+ union
+ {
+ __IO uint32_t slib_pwd_clr;
+ struct
+ {
+ __IO uint32_t slib_pclr_val : 32;/* [31:0] */
+ } slib_pwd_clr_bit;
+ };
+
+ /**
+ * @brief flash slib_misc_sts register, offset:0xD8
+ */
+ union
+ {
+ __IO uint32_t slib_misc_sts;
+ struct
+ {
+ __IO uint32_t slib_pwd_err : 1; /* [0] */
+ __IO uint32_t slib_pwd_ok : 1; /* [1] */
+ __IO uint32_t slib_ulkf : 1; /* [2] */
+ __IO uint32_t reserved1 : 13;/* [15:3] */
+ __IO uint32_t slib_rcnt : 9; /* [24:16] */
+ __IO uint32_t reserved2 : 7; /* [31:25] */
+ } slib_misc_sts_bit;
+ };
+
+ /**
+ * @brief flash slib_set_pwd register, offset:0xDC
+ */
+ union
+ {
+ __IO uint32_t slib_set_pwd;
+ struct
+ {
+ __IO uint32_t slib_pset_val : 32;/* [31:0] */
+ } slib_set_pwd_bit;
+ };
+
+ /**
+ * @brief flash slib_set_range0 register, offset:0xE0
+ */
+ union
+ {
+ __IO uint32_t slib_set_range0;
+ struct
+ {
+ __IO uint32_t slib_ss_set : 16;/* [15:0] */
+ __IO uint32_t slib_es_set : 16;/* [31:16] */
+ } slib_set_range0_bit;
+ };
+
+ /**
+ * @brief flash slib_set_range1 register, offset:0xE4
+ */
+ union
+ {
+ __IO uint32_t slib_set_range1;
+ struct
+ {
+ __IO uint32_t slib_iss_set : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 15;/* [30:16] */
+ __IO uint32_t set_slib_strt : 1; /* [31] */
+ } slib_set_range1_bit;
+ };
+
+ /**
+ * @brief flash reserved7 register, offset:0xEC~0xE8
+ */
+ __IO uint32_t reserved7[2];
+
+ /**
+ * @brief flash slib_unlock register, offset:0xF0
+ */
+ union
+ {
+ __IO uint32_t slib_unlock;
+ struct
+ {
+ __IO uint32_t slib_ukval : 32;/* [31:0] */
+ } slib_unlock_bit;
+ };
+
+ /**
+ * @brief flash crc_ctrl register, offset:0xF4
+ */
+ union
+ {
+ __IO uint32_t crc_ctrl;
+ struct
+ {
+ __IO uint32_t crc_ss : 12;/* [11:0] */
+ __IO uint32_t crc_sn : 12;/* [23:12] */
+ __IO uint32_t reserved1 : 7; /* [30:24] */
+ __IO uint32_t crc_strt : 1; /* [31] */
+ } crc_ctrl_bit;
+ };
+
+ /**
+ * @brief flash crc_chkr register, offset:0xF8
+ */
+ union
+ {
+ __IO uint32_t crc_chkr;
+ struct
+ {
+ __IO uint32_t crc_chkr : 32;/* [31:0] */
+ } crc_chkr_bit;
+ };
+
+} flash_type;
+
+/**
+ * @brief user system data
+ */
+typedef struct
+{
+ __IO uint16_t fap;
+ __IO uint16_t ssb;
+ __IO uint16_t data0;
+ __IO uint16_t data1;
+ __IO uint16_t epp0;
+ __IO uint16_t epp1;
+ __IO uint16_t epp2;
+ __IO uint16_t epp3;
+ __IO uint16_t eopb0;
+ __IO uint16_t reserved1;
+ __IO uint16_t epp4;
+ __IO uint16_t epp5;
+ __IO uint16_t epp6;
+ __IO uint16_t epp7;
+ __IO uint16_t reserved2[12];
+ __IO uint16_t qspikey[8];
+} usd_type;
+
+/**
+ * @}
+ */
+
+#define FLASH ((flash_type *) FLASH_REG_BASE)
+#define USD ((usd_type *) USD_BASE)
+
+/** @defgroup FLASH_exported_functions
+ * @{
+ */
+
+flag_status flash_flag_get(uint32_t flash_flag);
+void flash_flag_clear(uint32_t flash_flag);
+flash_status_type flash_operation_status_get(void);
+flash_status_type flash_bank1_operation_status_get(void);
+flash_status_type flash_bank2_operation_status_get(void);
+flash_status_type flash_operation_wait_for(uint32_t time_out);
+flash_status_type flash_bank1_operation_wait_for(uint32_t time_out);
+flash_status_type flash_bank2_operation_wait_for(uint32_t time_out);
+void flash_unlock(void);
+void flash_bank1_unlock(void);
+void flash_bank2_unlock(void);
+void flash_lock(void);
+void flash_bank1_lock(void);
+void flash_bank2_lock(void);
+flash_status_type flash_sector_erase(uint32_t sector_address);
+flash_status_type flash_block_erase(uint32_t block_address);
+flash_status_type flash_internal_all_erase(void);
+flash_status_type flash_bank1_erase(void);
+flash_status_type flash_bank2_erase(void);
+flash_status_type flash_user_system_data_erase(void);
+flash_status_type flash_eopb0_config(flash_usd_eopb0_type data);
+flash_status_type flash_word_program(uint32_t address, uint32_t data);
+flash_status_type flash_halfword_program(uint32_t address, uint16_t data);
+flash_status_type flash_byte_program(uint32_t address, uint8_t data);
+flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data);
+flash_status_type flash_epp_set(uint32_t *sector_bits);
+void flash_epp_status_get(uint32_t *sector_bits);
+flash_status_type flash_fap_enable(confirm_state new_state);
+flag_status flash_fap_status_get(void);
+flash_status_type flash_ssb_set(uint8_t usd_ssb);
+uint8_t flash_ssb_status_get(void);
+void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state);
+flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t inst_start_sector, uint16_t end_sector);
+error_status flash_slib_disable(uint32_t pwd);
+uint32_t flash_slib_remaining_count_get(void);
+flag_status flash_slib_state_get(void);
+uint16_t flash_slib_start_sector_get(void);
+uint16_t flash_slib_inststart_sector_get(void);
+uint16_t flash_slib_end_sector_get(void);
+uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt);
+void flash_nzw_boost_enable(confirm_state new_state);
+void flash_continue_read_enable(confirm_state new_state);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_gpio.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_gpio.h
new file mode 100644
index 0000000..edc2b06
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_gpio.h
@@ -0,0 +1,565 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_gpio.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 gpio header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_GPIO_H
+#define __AT32F435_437_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/** @defgroup GPIO_pins_number_definition
+ * @{
+ */
+
+#define GPIO_PINS_0 0x0001 /*!< gpio pins number 0 */
+#define GPIO_PINS_1 0x0002 /*!< gpio pins number 1 */
+#define GPIO_PINS_2 0x0004 /*!< gpio pins number 2 */
+#define GPIO_PINS_3 0x0008 /*!< gpio pins number 3 */
+#define GPIO_PINS_4 0x0010 /*!< gpio pins number 4 */
+#define GPIO_PINS_5 0x0020 /*!< gpio pins number 5 */
+#define GPIO_PINS_6 0x0040 /*!< gpio pins number 6 */
+#define GPIO_PINS_7 0x0080 /*!< gpio pins number 7 */
+#define GPIO_PINS_8 0x0100 /*!< gpio pins number 8 */
+#define GPIO_PINS_9 0x0200 /*!< gpio pins number 9 */
+#define GPIO_PINS_10 0x0400 /*!< gpio pins number 10 */
+#define GPIO_PINS_11 0x0800 /*!< gpio pins number 11 */
+#define GPIO_PINS_12 0x1000 /*!< gpio pins number 12 */
+#define GPIO_PINS_13 0x2000 /*!< gpio pins number 13 */
+#define GPIO_PINS_14 0x4000 /*!< gpio pins number 14 */
+#define GPIO_PINS_15 0x8000 /*!< gpio pins number 15 */
+#define GPIO_PINS_ALL 0xFFFF /*!< gpio all pins */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_exported_types
+ * @{
+ */
+
+/**
+ * @brief gpio mode select
+ */
+typedef enum
+{
+ GPIO_MODE_INPUT = 0x00, /*!< gpio input mode */
+ GPIO_MODE_OUTPUT = 0x01, /*!< gpio output mode */
+ GPIO_MODE_MUX = 0x02, /*!< gpio mux function mode */
+ GPIO_MODE_ANALOG = 0x03 /*!< gpio analog in/out mode */
+} gpio_mode_type;
+
+/**
+ * @brief gpio output drive strength select
+ */
+typedef enum
+{
+ GPIO_DRIVE_STRENGTH_STRONGER = 0x01, /*!< stronger sourcing/sinking strength */
+ GPIO_DRIVE_STRENGTH_MODERATE = 0x02 /*!< moderate sourcing/sinking strength */
+} gpio_drive_type;
+
+/**
+ * @brief gpio output type
+ */
+typedef enum
+{
+ GPIO_OUTPUT_PUSH_PULL = 0x00, /*!< output push-pull */
+ GPIO_OUTPUT_OPEN_DRAIN = 0x01 /*!< output open-drain */
+} gpio_output_type;
+
+/**
+ * @brief gpio pull type
+ */
+typedef enum
+{
+ GPIO_PULL_NONE = 0x00, /*!< floating for input, no pull for output */
+ GPIO_PULL_UP = 0x01, /*!< pull-up */
+ GPIO_PULL_DOWN = 0x02 /*!< pull-down */
+} gpio_pull_type;
+
+/**
+ * @brief gpio init type
+ */
+typedef struct
+{
+ uint32_t gpio_pins; /*!< pins number selection */
+ gpio_output_type gpio_out_type; /*!< output type selection */
+ gpio_pull_type gpio_pull; /*!< pull type selection */
+ gpio_mode_type gpio_mode; /*!< mode selection */
+ gpio_drive_type gpio_drive_strength; /*!< drive strength selection */
+} gpio_init_type;
+
+/**
+ * @brief gpio pins source type
+ */
+typedef enum
+{
+ GPIO_PINS_SOURCE0 = 0x00, /*!< gpio pins source number 0 */
+ GPIO_PINS_SOURCE1 = 0x01, /*!< gpio pins source number 1 */
+ GPIO_PINS_SOURCE2 = 0x02, /*!< gpio pins source number 2 */
+ GPIO_PINS_SOURCE3 = 0x03, /*!< gpio pins source number 3 */
+ GPIO_PINS_SOURCE4 = 0x04, /*!< gpio pins source number 4 */
+ GPIO_PINS_SOURCE5 = 0x05, /*!< gpio pins source number 5 */
+ GPIO_PINS_SOURCE6 = 0x06, /*!< gpio pins source number 6 */
+ GPIO_PINS_SOURCE7 = 0x07, /*!< gpio pins source number 7 */
+ GPIO_PINS_SOURCE8 = 0x08, /*!< gpio pins source number 8 */
+ GPIO_PINS_SOURCE9 = 0x09, /*!< gpio pins source number 9 */
+ GPIO_PINS_SOURCE10 = 0x0A, /*!< gpio pins source number 10 */
+ GPIO_PINS_SOURCE11 = 0x0B, /*!< gpio pins source number 11 */
+ GPIO_PINS_SOURCE12 = 0x0C, /*!< gpio pins source number 12 */
+ GPIO_PINS_SOURCE13 = 0x0D, /*!< gpio pins source number 13 */
+ GPIO_PINS_SOURCE14 = 0x0E, /*!< gpio pins source number 14 */
+ GPIO_PINS_SOURCE15 = 0x0F /*!< gpio pins source number 15 */
+} gpio_pins_source_type;
+
+/**
+ * @brief gpio muxing function selection type
+ */
+typedef enum
+{
+ GPIO_MUX_0 = 0x00, /*!< gpio muxing function selection 0 */
+ GPIO_MUX_1 = 0x01, /*!< gpio muxing function selection 1 */
+ GPIO_MUX_2 = 0x02, /*!< gpio muxing function selection 2 */
+ GPIO_MUX_3 = 0x03, /*!< gpio muxing function selection 3 */
+ GPIO_MUX_4 = 0x04, /*!< gpio muxing function selection 4 */
+ GPIO_MUX_5 = 0x05, /*!< gpio muxing function selection 5 */
+ GPIO_MUX_6 = 0x06, /*!< gpio muxing function selection 6 */
+ GPIO_MUX_7 = 0x07, /*!< gpio muxing function selection 7 */
+ GPIO_MUX_8 = 0x08, /*!< gpio muxing function selection 8 */
+ GPIO_MUX_9 = 0x09, /*!< gpio muxing function selection 9 */
+ GPIO_MUX_10 = 0x0A, /*!< gpio muxing function selection 10 */
+ GPIO_MUX_11 = 0x0B, /*!< gpio muxing function selection 11 */
+ GPIO_MUX_12 = 0x0C, /*!< gpio muxing function selection 12 */
+ GPIO_MUX_13 = 0x0D, /*!< gpio muxing function selection 13 */
+ GPIO_MUX_14 = 0x0E, /*!< gpio muxing function selection 14 */
+ GPIO_MUX_15 = 0x0F /*!< gpio muxing function selection 15 */
+} gpio_mux_sel_type;
+
+/**
+ * @brief type define gpio register all
+ */
+typedef struct
+{
+ /**
+ * @brief gpio mode register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t cfgr;
+ struct
+ {
+ __IO uint32_t iomc0 : 2; /* [1:0] */
+ __IO uint32_t iomc1 : 2; /* [3:2] */
+ __IO uint32_t iomc2 : 2; /* [5:4] */
+ __IO uint32_t iomc3 : 2; /* [7:6] */
+ __IO uint32_t iomc4 : 2; /* [9:8] */
+ __IO uint32_t iomc5 : 2; /* [11:10] */
+ __IO uint32_t iomc6 : 2; /* [13:12] */
+ __IO uint32_t iomc7 : 2; /* [15:14] */
+ __IO uint32_t iomc8 : 2; /* [17:16] */
+ __IO uint32_t iomc9 : 2; /* [19:18] */
+ __IO uint32_t iomc10 : 2; /* [21:20] */
+ __IO uint32_t iomc11 : 2; /* [23:22] */
+ __IO uint32_t iomc12 : 2; /* [25:24] */
+ __IO uint32_t iomc13 : 2; /* [27:26] */
+ __IO uint32_t iomc14 : 2; /* [29:28] */
+ __IO uint32_t iomc15 : 2; /* [31:30] */
+ } cfgr_bit;
+ };
+
+ /**
+ * @brief gpio output type register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t omode;
+ struct
+ {
+ __IO uint32_t om0 : 1; /* [0] */
+ __IO uint32_t om1 : 1; /* [1] */
+ __IO uint32_t om2 : 1; /* [2] */
+ __IO uint32_t om3 : 1; /* [3] */
+ __IO uint32_t om4 : 1; /* [4] */
+ __IO uint32_t om5 : 1; /* [5] */
+ __IO uint32_t om6 : 1; /* [6] */
+ __IO uint32_t om7 : 1; /* [7] */
+ __IO uint32_t om8 : 1; /* [8] */
+ __IO uint32_t om9 : 1; /* [9] */
+ __IO uint32_t om10 : 1; /* [10] */
+ __IO uint32_t om11 : 1; /* [11] */
+ __IO uint32_t om12 : 1; /* [12] */
+ __IO uint32_t om13 : 1; /* [13] */
+ __IO uint32_t om14 : 1; /* [14] */
+ __IO uint32_t om15 : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } omode_bit;
+ };
+
+ /**
+ * @brief gpio output driver register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t odrvr;
+ struct
+ {
+ __IO uint32_t odrv0 : 2; /* [1:0] */
+ __IO uint32_t odrv1 : 2; /* [3:2] */
+ __IO uint32_t odrv2 : 2; /* [5:4] */
+ __IO uint32_t odrv3 : 2; /* [7:6] */
+ __IO uint32_t odrv4 : 2; /* [9:8] */
+ __IO uint32_t odrv5 : 2; /* [11:10] */
+ __IO uint32_t odrv6 : 2; /* [13:12] */
+ __IO uint32_t odrv7 : 2; /* [15:14] */
+ __IO uint32_t odrv8 : 2; /* [17:16] */
+ __IO uint32_t odrv9 : 2; /* [19:18] */
+ __IO uint32_t odrv10 : 2; /* [21:20] */
+ __IO uint32_t odrv11 : 2; /* [23:22] */
+ __IO uint32_t odrv12 : 2; /* [25:24] */
+ __IO uint32_t odrv13 : 2; /* [27:26] */
+ __IO uint32_t odrv14 : 2; /* [29:28] */
+ __IO uint32_t odrv15 : 2; /* [31:30] */
+ } odrvr_bit;
+ };
+
+ /**
+ * @brief gpio pull up/down register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t pull;
+ struct
+ {
+ __IO uint32_t pull0 : 2; /* [1:0] */
+ __IO uint32_t pull1 : 2; /* [3:2] */
+ __IO uint32_t pull2 : 2; /* [5:4] */
+ __IO uint32_t pull3 : 2; /* [7:6] */
+ __IO uint32_t pull4 : 2; /* [9:8] */
+ __IO uint32_t pull5 : 2; /* [11:10] */
+ __IO uint32_t pull6 : 2; /* [13:12] */
+ __IO uint32_t pull7 : 2; /* [15:14] */
+ __IO uint32_t pull8 : 2; /* [17:16] */
+ __IO uint32_t pull9 : 2; /* [19:18] */
+ __IO uint32_t pull10 : 2; /* [21:20] */
+ __IO uint32_t pull11 : 2; /* [23:22] */
+ __IO uint32_t pull12 : 2; /* [25:24] */
+ __IO uint32_t pull13 : 2; /* [27:26] */
+ __IO uint32_t pull14 : 2; /* [29:28] */
+ __IO uint32_t pull15 : 2; /* [31:30] */
+ } pull_bit;
+ };
+
+ /**
+ * @brief gpio input data register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t idt;
+ struct
+ {
+ __IO uint32_t idt0 : 1; /* [0] */
+ __IO uint32_t idt1 : 1; /* [1] */
+ __IO uint32_t idt2 : 1; /* [2] */
+ __IO uint32_t idt3 : 1; /* [3] */
+ __IO uint32_t idt4 : 1; /* [4] */
+ __IO uint32_t idt5 : 1; /* [5] */
+ __IO uint32_t idt6 : 1; /* [6] */
+ __IO uint32_t idt7 : 1; /* [7] */
+ __IO uint32_t idt8 : 1; /* [8] */
+ __IO uint32_t idt9 : 1; /* [9] */
+ __IO uint32_t idt10 : 1; /* [10] */
+ __IO uint32_t idt11 : 1; /* [11] */
+ __IO uint32_t idt12 : 1; /* [12] */
+ __IO uint32_t idt13 : 1; /* [13] */
+ __IO uint32_t idt14 : 1; /* [14] */
+ __IO uint32_t idt15 : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } idt_bit;
+ };
+
+ /**
+ * @brief gpio output data register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t odt;
+ struct
+ {
+ __IO uint32_t odt0 : 1; /* [0] */
+ __IO uint32_t odt1 : 1; /* [1] */
+ __IO uint32_t odt2 : 1; /* [2] */
+ __IO uint32_t odt3 : 1; /* [3] */
+ __IO uint32_t odt4 : 1; /* [4] */
+ __IO uint32_t odt5 : 1; /* [5] */
+ __IO uint32_t odt6 : 1; /* [6] */
+ __IO uint32_t odt7 : 1; /* [7] */
+ __IO uint32_t odt8 : 1; /* [8] */
+ __IO uint32_t odt9 : 1; /* [9] */
+ __IO uint32_t odt10 : 1; /* [10] */
+ __IO uint32_t odt11 : 1; /* [11] */
+ __IO uint32_t odt12 : 1; /* [12] */
+ __IO uint32_t odt13 : 1; /* [13] */
+ __IO uint32_t odt14 : 1; /* [14] */
+ __IO uint32_t odt15 : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } odt_bit;
+ };
+
+ /**
+ * @brief gpio scr register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t scr;
+ struct
+ {
+ __IO uint32_t iosb0 : 1; /* [0] */
+ __IO uint32_t iosb1 : 1; /* [1] */
+ __IO uint32_t iosb2 : 1; /* [2] */
+ __IO uint32_t iosb3 : 1; /* [3] */
+ __IO uint32_t iosb4 : 1; /* [4] */
+ __IO uint32_t iosb5 : 1; /* [5] */
+ __IO uint32_t iosb6 : 1; /* [6] */
+ __IO uint32_t iosb7 : 1; /* [7] */
+ __IO uint32_t iosb8 : 1; /* [8] */
+ __IO uint32_t iosb9 : 1; /* [9] */
+ __IO uint32_t iosb10 : 1; /* [10] */
+ __IO uint32_t iosb11 : 1; /* [11] */
+ __IO uint32_t iosb12 : 1; /* [12] */
+ __IO uint32_t iosb13 : 1; /* [13] */
+ __IO uint32_t iosb14 : 1; /* [14] */
+ __IO uint32_t iosb15 : 1; /* [15] */
+ __IO uint32_t iocb0 : 1; /* [16] */
+ __IO uint32_t iocb1 : 1; /* [17] */
+ __IO uint32_t iocb2 : 1; /* [18] */
+ __IO uint32_t iocb3 : 1; /* [19] */
+ __IO uint32_t iocb4 : 1; /* [20] */
+ __IO uint32_t iocb5 : 1; /* [21] */
+ __IO uint32_t iocb6 : 1; /* [22] */
+ __IO uint32_t iocb7 : 1; /* [23] */
+ __IO uint32_t iocb8 : 1; /* [24] */
+ __IO uint32_t iocb9 : 1; /* [25] */
+ __IO uint32_t iocb10 : 1; /* [26] */
+ __IO uint32_t iocb11 : 1; /* [27] */
+ __IO uint32_t iocb12 : 1; /* [28] */
+ __IO uint32_t iocb13 : 1; /* [29] */
+ __IO uint32_t iocb14 : 1; /* [30] */
+ __IO uint32_t iocb15 : 1; /* [31] */
+ } scr_bit;
+ };
+
+ /**
+ * @brief gpio wpen register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t wpr;
+ struct
+ {
+ __IO uint32_t wpen0 : 1; /* [0] */
+ __IO uint32_t wpen1 : 1; /* [1] */
+ __IO uint32_t wpen2 : 1; /* [2] */
+ __IO uint32_t wpen3 : 1; /* [3] */
+ __IO uint32_t wpen4 : 1; /* [4] */
+ __IO uint32_t wpen5 : 1; /* [5] */
+ __IO uint32_t wpen6 : 1; /* [6] */
+ __IO uint32_t wpen7 : 1; /* [7] */
+ __IO uint32_t wpen8 : 1; /* [8] */
+ __IO uint32_t wpen9 : 1; /* [9] */
+ __IO uint32_t wpen10 : 1; /* [10] */
+ __IO uint32_t wpen11 : 1; /* [11] */
+ __IO uint32_t wpen12 : 1; /* [12] */
+ __IO uint32_t wpen13 : 1; /* [13] */
+ __IO uint32_t wpen14 : 1; /* [14] */
+ __IO uint32_t wpen15 : 1; /* [15] */
+ __IO uint32_t wpseq : 1; /* [16] */
+ __IO uint32_t reserved1 : 15;/* [31:17] */
+ } wpr_bit;
+ };
+
+ /**
+ * @brief gpio muxl register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t muxl;
+ struct
+ {
+ __IO uint32_t muxl0 : 4; /* [3:0] */
+ __IO uint32_t muxl1 : 4; /* [7:4] */
+ __IO uint32_t muxl2 : 4; /* [11:8] */
+ __IO uint32_t muxl3 : 4; /* [15:12] */
+ __IO uint32_t muxl4 : 4; /* [19:16] */
+ __IO uint32_t muxl5 : 4; /* [23:20] */
+ __IO uint32_t muxl6 : 4; /* [27:24] */
+ __IO uint32_t muxl7 : 4; /* [31:28] */
+ } muxl_bit;
+ };
+
+ /**
+ * @brief gpio muxh register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t muxh;
+ struct
+ {
+ __IO uint32_t muxh8 : 4; /* [3:0] */
+ __IO uint32_t muxh9 : 4; /* [7:4] */
+ __IO uint32_t muxh10 : 4; /* [11:8] */
+ __IO uint32_t muxh11 : 4; /* [15:12] */
+ __IO uint32_t muxh12 : 4; /* [19:16] */
+ __IO uint32_t muxh13 : 4; /* [23:20] */
+ __IO uint32_t muxh14 : 4; /* [27:24] */
+ __IO uint32_t muxh15 : 4; /* [31:28] */
+ } muxh_bit;
+ };
+
+ /**
+ * @brief gpio clr register, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t clr;
+ struct
+ {
+ __IO uint32_t iocb0 : 1; /* [0] */
+ __IO uint32_t iocb1 : 1; /* [1] */
+ __IO uint32_t iocb2 : 1; /* [2] */
+ __IO uint32_t iocb3 : 1; /* [3] */
+ __IO uint32_t iocb4 : 1; /* [4] */
+ __IO uint32_t iocb5 : 1; /* [5] */
+ __IO uint32_t iocb6 : 1; /* [6] */
+ __IO uint32_t iocb7 : 1; /* [7] */
+ __IO uint32_t iocb8 : 1; /* [8] */
+ __IO uint32_t iocb9 : 1; /* [9] */
+ __IO uint32_t iocb10 : 1; /* [10] */
+ __IO uint32_t iocb11 : 1; /* [11] */
+ __IO uint32_t iocb12 : 1; /* [12] */
+ __IO uint32_t iocb13 : 1; /* [13] */
+ __IO uint32_t iocb14 : 1; /* [14] */
+ __IO uint32_t iocb15 : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } clr_bit;
+ };
+
+ /**
+ * @brief gpio reserved1 register, offset:0x2C~0x38
+ */
+ __IO uint32_t reserved1[4];
+
+ /**
+ * @brief gpio hdrv register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t hdrv;
+ struct
+ {
+ __IO uint32_t hdrv0 : 1; /* [0] */
+ __IO uint32_t hdrv1 : 1; /* [1] */
+ __IO uint32_t hdrv2 : 1; /* [2] */
+ __IO uint32_t hdrv3 : 1; /* [3] */
+ __IO uint32_t hdrv4 : 1; /* [4] */
+ __IO uint32_t hdrv5 : 1; /* [5] */
+ __IO uint32_t hdrv6 : 1; /* [6] */
+ __IO uint32_t hdrv7 : 1; /* [7] */
+ __IO uint32_t hdrv8 : 1; /* [8] */
+ __IO uint32_t hdrv9 : 1; /* [9] */
+ __IO uint32_t hdrv10 : 1; /* [10] */
+ __IO uint32_t hdrv11 : 1; /* [11] */
+ __IO uint32_t hdrv12 : 1; /* [12] */
+ __IO uint32_t hdrv13 : 1; /* [13] */
+ __IO uint32_t hdrv14 : 1; /* [14] */
+ __IO uint32_t hdrv15 : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } hdrv_bit;
+ };
+
+} gpio_type;
+
+/**
+ * @}
+ */
+
+#define GPIOA ((gpio_type *) GPIOA_BASE)
+#define GPIOB ((gpio_type *) GPIOB_BASE)
+#define GPIOC ((gpio_type *) GPIOC_BASE)
+#define GPIOD ((gpio_type *) GPIOD_BASE)
+#define GPIOE ((gpio_type *) GPIOE_BASE)
+#define GPIOF ((gpio_type *) GPIOF_BASE)
+#define GPIOG ((gpio_type *) GPIOG_BASE)
+#define GPIOH ((gpio_type *) GPIOH_BASE)
+
+/** @defgroup GPIO_exported_functions
+ * @{
+ */
+
+void gpio_reset(gpio_type *gpio_x);
+void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct);
+void gpio_default_para_init(gpio_init_type *gpio_init_struct);
+flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins);
+uint16_t gpio_input_data_read(gpio_type *gpio_x);
+flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins);
+uint16_t gpio_output_data_read(gpio_type *gpio_x);
+void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
+void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
+void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
+void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value);
+void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
+void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state);
+void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_i2c.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_i2c.h
new file mode 100644
index 0000000..b5a136c
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_i2c.h
@@ -0,0 +1,479 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_i2c.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 i2c header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_I2C_H
+#define __AT32F435_437_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/**
+ * @brief maximum number of single transfers
+ */
+#define MAX_TRANSFER_CNT 255 /*!< maximum number of single transfers */
+
+/** @defgroup I2C_interrupts_definition
+ * @brief i2c interrupt
+ * @{
+ */
+
+#define I2C_TD_INT ((uint32_t)0x00000002) /*!< i2c transmit data interrupt */
+#define I2C_RD_INT ((uint32_t)0x00000004) /*!< i2c receive data interrupt */
+#define I2C_ADDR_INT ((uint32_t)0x00000008) /*!< i2c address match interrupt */
+#define I2C_ACKFIAL_INT ((uint32_t)0x00000010) /*!< i2c ack fail interrupt */
+#define I2C_STOP_INT ((uint32_t)0x00000020) /*!< i2c stop detect interrupt */
+#define I2C_TDC_INT ((uint32_t)0x00000040) /*!< i2c transmit data complete interrupt */
+#define I2C_ERR_INT ((uint32_t)0x00000080) /*!< i2c bus error interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_flags_definition
+ * @brief i2c flag
+ * @{
+ */
+
+#define I2C_TDBE_FLAG ((uint32_t)0x00000001) /*!< i2c transmit data buffer empty flag */
+#define I2C_TDIS_FLAG ((uint32_t)0x00000002) /*!< i2c send interrupt status */
+#define I2C_RDBF_FLAG ((uint32_t)0x00000004) /*!< i2c receive data buffer full flag */
+#define I2C_ADDRF_FLAG ((uint32_t)0x00000008) /*!< i2c 0~7 bit address match flag */
+#define I2C_ACKFAIL_FLAG ((uint32_t)0x00000010) /*!< i2c acknowledge failure flag */
+#define I2C_STOPF_FLAG ((uint32_t)0x00000020) /*!< i2c stop condition generation complete flag */
+#define I2C_TDC_FLAG ((uint32_t)0x00000040) /*!< i2c transmit data complete flag */
+#define I2C_TCRLD_FLAG ((uint32_t)0x00000080) /*!< i2c transmission is complete, waiting to load data */
+#define I2C_BUSERR_FLAG ((uint32_t)0x00000100) /*!< i2c bus error flag */
+#define I2C_ARLOST_FLAG ((uint32_t)0x00000200) /*!< i2c arbitration lost flag */
+#define I2C_OUF_FLAG ((uint32_t)0x00000400) /*!< i2c overflow or underflow flag */
+#define I2C_PECERR_FLAG ((uint32_t)0x00000800) /*!< i2c pec receive error flag */
+#define I2C_TMOUT_FLAG ((uint32_t)0x00001000) /*!< i2c smbus timeout flag */
+#define I2C_ALERTF_FLAG ((uint32_t)0x00002000) /*!< i2c smbus alert flag */
+#define I2C_BUSYF_FLAG ((uint32_t)0x00008000) /*!< i2c bus busy flag transmission mode */
+#define I2C_SDIR_FLAG ((uint32_t)0x00010000) /*!< i2c slave data transmit direction */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_exported_types
+ * @{
+ */
+
+/**
+ * @brief i2c smbus mode set
+ */
+typedef enum
+{
+ I2C_SMBUS_MODE_DEVICE = 0x00, /*!< smbus device mode */
+ I2C_SMBUS_MODE_HOST = 0x01 /*!< smbus host mode */
+} i2c_smbus_mode_type;
+
+/**
+ * @brief i2c address mode
+ */
+typedef enum
+{
+ I2C_ADDRESS_MODE_7BIT = 0x00, /*!< 7bit address mode */
+ I2C_ADDRESS_MODE_10BIT = 0x01 /*!< 10bit address mode */
+} i2c_address_mode_type;
+
+/**
+ * @brief i2c transfer direction
+ */
+typedef enum
+{
+ I2C_DIR_TRANSMIT = 0x00, /*!< master request a write transfer */
+ I2C_DIR_RECEIVE = 0x01 /*!< master request a read transfer */
+} i2c_transfer_dir_type;
+
+/**
+ * @brief i2c dma requests direction
+ */
+typedef enum
+{
+ I2C_DMA_REQUEST_TX = 0x00, /*!< dma transmit request */
+ I2C_DMA_REQUEST_RX = 0x01 /*!< dma receive request */
+} i2c_dma_request_type;
+
+/**
+ * @brief i2c smbus alert pin set
+ */
+typedef enum
+{
+ I2C_SMBUS_ALERT_HIGH = 0x00, /*!< smbus alert pin set high */
+ I2C_SMBUS_ALERT_LOW = 0x01 /*!< smbus alert pin set low */
+} i2c_smbus_alert_set_type;
+
+/**
+ * @brief i2c clock timeout detection mode
+ */
+typedef enum
+{
+ I2C_TIMEOUT_DETCET_LOW = 0x00, /*!< detect low level timeout */
+ I2C_TIMEOUT_DETCET_HIGH = 0x01 /*!< detect high level timeout */
+} i2c_timeout_detcet_type;
+
+/**
+ * @brief i2c own address2 mask
+ */
+typedef enum
+{
+ I2C_ADDR2_NOMASK = 0x00, /*!< compare bit [7:1] */
+ I2C_ADDR2_MASK01 = 0x01, /*!< only compare bit [7:2] */
+ I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:2] */
+ I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:3] */
+ I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:4] */
+ I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:5] */
+ I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7:6] */
+ I2C_ADDR2_MASK07 = 0x07 /*!< only compare bit [7] */
+} i2c_addr2_mask_type;
+
+/**
+ * @brief i2c reload end mode
+ */
+typedef enum
+{
+ I2C_AUTO_STOP_MODE = 0x00, /*!< auto generate stop mode */
+ I2C_SOFT_STOP_MODE = 0x01, /*!< soft generate stop mode */
+ I2C_RELOAD_MODE = 0x02 /*!< reload mode */
+} i2c_reload_stop_mode_type;
+
+/**
+ * @brief i2c start stop mode
+ */
+typedef enum
+{
+ I2C_WITHOUT_START = 0x00, /*!< transfer data without start condition */
+ I2C_GEN_START_READ = 0x01, /*!< read data and generate start */
+ I2C_GEN_START_WRITE = 0x02 /*!< send data and generate start */
+} i2c_start_stop_mode_type;
+
+/**
+ * @brief type define i2c register all
+ */
+typedef struct
+{
+ /**
+ * @brief i2c ctrl1 register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t i2cen : 1; /* [0] */
+ __IO uint32_t tdien : 1; /* [1] */
+ __IO uint32_t rdien : 1; /* [2] */
+ __IO uint32_t addrien : 1; /* [3] */
+ __IO uint32_t ackfailien : 1; /* [4] */
+ __IO uint32_t stopien : 1; /* [5] */
+ __IO uint32_t tdcien : 1; /* [6] */
+ __IO uint32_t errien : 1; /* [7] */
+ __IO uint32_t dflt : 4; /* [11:8] */
+ __IO uint32_t reserved1 : 2; /* [13:12] */
+ __IO uint32_t dmaten : 1; /* [14] */
+ __IO uint32_t dmaren : 1; /* [15] */
+ __IO uint32_t sctrl : 1; /* [16] */
+ __IO uint32_t stretch : 1; /* [17] */
+ __IO uint32_t reserved2 : 1; /* [18] */
+ __IO uint32_t gcaen : 1; /* [19] */
+ __IO uint32_t haddren : 1; /* [20] */
+ __IO uint32_t devaddren : 1; /* [21] */
+ __IO uint32_t smbalert : 1; /* [22] */
+ __IO uint32_t pecen : 1; /* [23] */
+ __IO uint32_t reserved3 : 8; /* [31:24] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief i2c ctrl2 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t saddr : 10;/* [9:0] */
+ __IO uint32_t dir : 1; /* [10] */
+ __IO uint32_t addr10 : 1; /* [11] */
+ __IO uint32_t readh10 : 1; /* [12] */
+ __IO uint32_t genstart : 1; /* [13] */
+ __IO uint32_t genstop : 1; /* [14] */
+ __IO uint32_t nacken : 1; /* [15] */
+ __IO uint32_t cnt : 8; /* [23:16] */
+ __IO uint32_t rlden : 1; /* [24] */
+ __IO uint32_t astopen : 1; /* [25] */
+ __IO uint32_t pecten : 1; /* [26] */
+ __IO uint32_t reserved1 : 5; /* [31:27] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief i2c oaddr1 register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t oaddr1;
+ struct
+ {
+ __IO uint32_t addr1 : 10;/* [9:0] */
+ __IO uint32_t addr1mode : 1; /* [10] */
+ __IO uint32_t reserved1 : 4; /* [14:11] */
+ __IO uint32_t addr1en : 1; /* [15] */
+ __IO uint32_t reserved2 : 16;/* [31:16] */
+ } oaddr1_bit;
+ };
+
+ /**
+ * @brief i2c oaddr2 register, offset:0x0c
+ */
+ union
+ {
+ __IO uint32_t oaddr2;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t addr2 : 7; /* [7:1] */
+ __IO uint32_t addr2mask : 3; /* [10:8] */
+ __IO uint32_t reserved2 : 4; /* [14:11] */
+ __IO uint32_t addr2en : 1; /* [15] */
+ __IO uint32_t reserved3 : 16;/* [31:16] */
+ } oaddr2_bit;
+ };
+
+ /**
+ * @brief i2c clkctrl register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t clkctrl;
+ struct
+ {
+ __IO uint32_t scll : 8; /* [7:0] */
+ __IO uint32_t sclh : 8; /* [15:8] */
+ __IO uint32_t sdad : 4; /* [19:16] */
+ __IO uint32_t scld : 4; /* [23:20] */
+ __IO uint32_t divh : 4; /* [27:24] */
+ __IO uint32_t divl : 4; /* [31:28] */
+ } clkctrl_bit;
+ };
+
+ /**
+ * @brief i2c timeout register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t timeout;
+ struct
+ {
+ __IO uint32_t totime : 12;/* [11:0] */
+ __IO uint32_t tomode : 1; /* [12] */
+ __IO uint32_t reserved1 : 2; /* [14:13] */
+ __IO uint32_t toen : 1; /* [15] */
+ __IO uint32_t exttime : 12;/* [27:16] */
+ __IO uint32_t reserved2 : 3; /* [30:28] */
+ __IO uint32_t exten : 1; /* [31] */
+ } timeout_bit;
+ };
+
+ /**
+ * @brief i2c sts register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t tdbe : 1; /* [0] */
+ __IO uint32_t tdis : 1; /* [1] */
+ __IO uint32_t rdbf : 1; /* [2] */
+ __IO uint32_t addrf : 1; /* [3] */
+ __IO uint32_t ackfail : 1; /* [4] */
+ __IO uint32_t stopf : 1; /* [5] */
+ __IO uint32_t tdc : 1; /* [6] */
+ __IO uint32_t tcrld : 1; /* [7] */
+ __IO uint32_t buserr : 1; /* [8] */
+ __IO uint32_t arlost : 1; /* [9] */
+ __IO uint32_t ouf : 1; /* [10] */
+ __IO uint32_t pecerr : 1; /* [11] */
+ __IO uint32_t tmout : 1; /* [12] */
+ __IO uint32_t alertf : 1; /* [13] */
+ __IO uint32_t reserved1 : 1; /* [14] */
+ __IO uint32_t busyf : 1; /* [15] */
+ __IO uint32_t sdir : 1; /* [16] */
+ __IO uint32_t addr : 7; /* [23:17] */
+ __IO uint32_t reserved2 : 8; /* [31:24] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief i2c clr register, offset:0x1c
+ */
+ union
+ {
+ __IO uint32_t clr;
+ struct
+ {
+ __IO uint32_t reserved1 : 3; /* [2:0] */
+ __IO uint32_t addrc : 1; /* [3] */
+ __IO uint32_t ackfailc : 1; /* [4] */
+ __IO uint32_t stopc : 1; /* [5] */
+ __IO uint32_t reserved2 : 2; /* [6:7] */
+ __IO uint32_t buserrc : 1; /* [8] */
+ __IO uint32_t arlostc : 1; /* [9] */
+ __IO uint32_t oufc : 1; /* [10] */
+ __IO uint32_t pecerrc : 1; /* [11] */
+ __IO uint32_t tmoutc : 1; /* [12] */
+ __IO uint32_t alertc : 1; /* [13] */
+ __IO uint32_t reserved3 : 18;/* [31:14] */
+ } clr_bit;
+ };
+
+ /**
+ * @brief i2c pec register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t pec;
+ struct
+ {
+ __IO uint32_t pecval : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } pec_bit;
+ };
+
+ /**
+ * @brief i2c rxdt register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t rxdt;
+ struct
+ {
+ __IO uint32_t dt : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } rxdt_bit;
+ };
+
+ /**
+ * @brief i2c txdt register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t txdt;
+ struct
+ {
+ __IO uint32_t dt : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } txdt_bit;
+ };
+
+} i2c_type;
+
+/**
+ * @}
+ */
+
+#define I2C1 ((i2c_type *) I2C1_BASE)
+#define I2C2 ((i2c_type *) I2C2_BASE)
+#define I2C3 ((i2c_type *) I2C3_BASE)
+
+/** @defgroup I2C_exported_functions
+ * @{
+ */
+
+void i2c_reset(i2c_type *i2c_x);
+void i2c_init(i2c_type *i2c_x, uint8_t dfilters, uint32_t clk);
+void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address);
+void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask);
+void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_smbus_enable(i2c_type *i2c_x, i2c_smbus_mode_type mode, confirm_state new_state);
+void i2c_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_addr10_mode_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_transfer_addr_set(i2c_type *i2c_x, uint16_t address);
+uint16_t i2c_transfer_addr_get(i2c_type *i2c_x);
+void i2c_transfer_dir_set(i2c_type *i2c_x, i2c_transfer_dir_type i2c_direction);
+i2c_transfer_dir_type i2c_transfer_dir_get(i2c_type *i2c_x);
+uint8_t i2c_matched_addr_get(i2c_type *i2c_x);
+void i2c_auto_stop_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_reload_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_cnt_set(i2c_type *i2c_x, uint8_t cnt);
+void i2c_addr10_header_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level);
+void i2c_slave_data_ctrl_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state);
+uint8_t i2c_pec_value_get(i2c_type *i2c_x);
+void i2c_timeout_set(i2c_type *i2c_x, uint16_t timeout);
+void i2c_timeout_detcet_set(i2c_type *i2c_x, i2c_timeout_detcet_type mode);
+void i2c_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_ext_timeout_set(i2c_type *i2c_x, uint16_t timeout);
+void i2c_ext_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_interrupt_enable(i2c_type *i2c_x, uint32_t source, confirm_state new_state);
+flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source);
+void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state new_state);
+void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_stop_mode_type start_stop);
+void i2c_start_generate(i2c_type *i2c_x);
+void i2c_stop_generate(i2c_type *i2c_x);
+void i2c_data_send(i2c_type *i2c_x, uint8_t data);
+uint8_t i2c_data_receive(i2c_type *i2c_x);
+flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
+void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_misc.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_misc.h
new file mode 100644
index 0000000..9c5edaa
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_misc.h
@@ -0,0 +1,125 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_misc.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 misc header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_MISC_H
+#define __AT32F435_437_MISC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/** @defgroup MISC_vector_table_base_address
+ * @{
+ */
+
+#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< nvic vector table based ram address */
+#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< nvic vector table based flash address */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_exported_types
+ * @{
+ */
+
+/**
+ * @brief nvic interrupt priority group
+ */
+typedef enum
+{
+ NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
+ NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
+ NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
+ NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
+ NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3) /*!< 4 bits for preemption priority, 0 bits for subpriority */
+} nvic_priority_group_type;
+
+/**
+ * @brief nvic low power mode
+ */
+typedef enum
+{
+ NVIC_LP_SLEEPONEXIT = 0x02, /*!< send event on pending */
+ NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */
+ NVIC_LP_SEVONPEND = 0x10 /*!< enable sleep-on-exit feature */
+} nvic_lowpower_mode_type;
+
+/**
+ * @brief systick clock source
+ */
+typedef enum
+{
+ SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8 = ((uint32_t)0x00000000), /*!< systick clock source from core clock div8 */
+ SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV = ((uint32_t)0x00000004) /*!< systick clock source from core clock */
+} systick_clock_source_type;
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_exported_functions
+ * @{
+ */
+
+void nvic_system_reset(void);
+void nvic_irq_enable(uint32_t irqn, uint32_t preempt_priority, uint32_t sub_priority);
+void nvic_irq_disable(uint32_t irqn);
+void nvic_priority_group_config(nvic_priority_group_type priority_group);
+void nvic_vector_table_set(uint32_t base, uint32_t offset);
+void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state);
+void systick_clock_source_config(systick_clock_source_type source);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_pwc.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_pwc.h
new file mode 100644
index 0000000..76b5e4b
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_pwc.h
@@ -0,0 +1,230 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_pwc.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 pwr header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_PWC_H
+#define __AT32F435_437_PWC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup PWC
+ * @{
+ */
+
+/** @defgroup PWC_flags_definition
+ * @brief pwc flag
+ * @{
+ */
+
+#define PWC_WAKEUP_FLAG ((uint32_t)0x00000001) /*!< wakeup flag */
+#define PWC_STANDBY_FLAG ((uint32_t)0x00000002) /*!< standby flag */
+#define PWC_PVM_OUTPUT_FLAG ((uint32_t)0x00000004) /*!< pvm output flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief pwc wakeup pin num definition
+ */
+#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */
+#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2 */
+
+/**
+ * @brief select ldo output voltage.
+ * @param val: set the ldo output voltage.
+ * this parameter can be one of the following values:
+ * - PWC_LDO_OUTPUT_1V2
+ * - PWC_LDO_OUTPUT_1V3
+ * - PWC_LDO_OUTPUT_1V1
+ * - PWC_LDO_OUTPUT_1V0
+ */
+#define pwc_ldo_output_voltage_set(val) (PWC->ldoov_bit.ldoovsel = val)
+
+/** @defgroup PWC_exported_types
+ * @{
+ */
+
+/**
+ * @brief pwc pvm voltage type
+ */
+typedef enum
+{
+ PWC_PVM_VOLTAGE_2V3 = 0x01, /*!< power voltage monitoring boundary 2.3v */
+ PWC_PVM_VOLTAGE_2V4 = 0x02, /*!< power voltage monitoring boundary 2.4v */
+ PWC_PVM_VOLTAGE_2V5 = 0x03, /*!< power voltage monitoring boundary 2.5v */
+ PWC_PVM_VOLTAGE_2V6 = 0x04, /*!< power voltage monitoring boundary 2.6v */
+ PWC_PVM_VOLTAGE_2V7 = 0x05, /*!< power voltage monitoring boundary 2.7v */
+ PWC_PVM_VOLTAGE_2V8 = 0x06, /*!< power voltage monitoring boundary 2.8v */
+ PWC_PVM_VOLTAGE_2V9 = 0x07 /*!< power voltage monitoring boundary 2.9v */
+} pwc_pvm_voltage_type;
+
+/**
+ * @brief pwc ldo output voltage type
+ */
+typedef enum
+{
+ PWC_LDO_OUTPUT_1V2 = 0x00, /*!< ldo output voltage is 1.2v */
+ PWC_LDO_OUTPUT_1V3 = 0x01, /*!< ldo output voltage is 1.3v */
+ PWC_LDO_OUTPUT_1V1 = 0x04, /*!< ldo output voltage is 1.1v */
+ PWC_LDO_OUTPUT_1V0 = 0x05, /*!< ldo output voltage is 1.0v */
+} pwc_ldo_output_voltage_type;
+
+/**
+ * @brief pwc sleep enter type
+ */
+typedef enum
+{
+ PWC_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter sleep mode */
+ PWC_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter sleep mode */
+} pwc_sleep_enter_type ;
+
+/**
+ * @brief pwc deep sleep enter type
+ */
+typedef enum
+{
+ PWC_DEEP_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter deepsleep mode */
+ PWC_DEEP_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter deepsleep mode */
+} pwc_deep_sleep_enter_type ;
+
+/**
+ * @brief pwc regulator type
+ */
+typedef enum
+{
+ PWC_REGULATOR_ON = 0x00, /*!< voltage regulator state on when deepsleep mode */
+ PWC_REGULATOR_LOW_POWER = 0x01 /*!< voltage regulator state low power when deepsleep mode */
+} pwc_regulator_type ;
+
+/**
+ * @brief type define pwc register all
+ */
+typedef struct
+{
+ /**
+ * @brief pwc ctrl register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t vrsel : 1; /* [0] */
+ __IO uint32_t lpsel : 1; /* [1] */
+ __IO uint32_t clswef : 1; /* [2] */
+ __IO uint32_t clsef : 1; /* [3] */
+ __IO uint32_t pvmen : 1; /* [4] */
+ __IO uint32_t pvmsel : 3; /* [7:5] */
+ __IO uint32_t bpwen : 1; /* [8] */
+ __IO uint32_t reserved1 : 23;/* [31:9] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief pwc ctrlsts register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrlsts;
+ struct
+ {
+ __IO uint32_t swef : 1; /* [0] */
+ __IO uint32_t sef : 1; /* [1] */
+ __IO uint32_t pvmof : 1; /* [2] */
+ __IO uint32_t reserved1 : 5; /* [7:3] */
+ __IO uint32_t swpen1 : 1; /* [8] */
+ __IO uint32_t swpen2 : 1; /* [9] */
+ __IO uint32_t reserved2 : 22;/* [31:10] */
+ } ctrlsts_bit;
+ };
+
+ __IO uint32_t reserved1[2];
+
+ /**
+ * @brief pwc ldoov register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ldoov;
+ struct
+ {
+ __IO uint32_t ldoovsel : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 29;/* [31:3] */
+ } ldoov_bit;
+ };
+
+} pwc_type;
+
+/**
+ * @}
+ */
+
+#define PWC ((pwc_type *) PWC_BASE)
+
+/** @defgroup PWC_exported_functions
+ * @{
+ */
+
+void pwc_reset(void);
+void pwc_battery_powered_domain_access(confirm_state new_state);
+void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage);
+void pwc_power_voltage_monitor_enable(confirm_state new_state);
+void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state);
+void pwc_flag_clear(uint32_t pwc_flag);
+flag_status pwc_flag_get(uint32_t pwc_flag);
+void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter);
+void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter);
+void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator);
+void pwc_standby_mode_enter(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_qspi.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_qspi.h
new file mode 100644
index 0000000..d73e823
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_qspi.h
@@ -0,0 +1,555 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_qspi.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 qspi header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_QSPI_H
+#define __AT32F435_437_QSPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup QSPI
+ * @{
+ */
+
+/** @defgroup QSPI_flags_definition
+ * @brief qspi flag
+ * @{
+ */
+
+#define QSPI_CMDSTS_FLAG ((uint32_t)0x00000001) /*!< qspi command complete status flag */
+#define QSPI_RXFIFORDY_FLAG ((uint32_t)0x00000002) /*!< qspi rxfifo ready status flag */
+#define QSPI_TXFIFORDY_FLAG ((uint32_t)0x00000004) /*!< qspi txfifo ready status flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_exported_types
+ * @{
+ */
+
+/**
+ * @brief qspi xip read access mode type
+ */
+typedef enum
+{
+ QSPI_XIPR_SEL_MODED = 0x00, /*!< qspi xip read select mode d */
+ QSPI_XIPR_SEL_MODET = 0x01 /*!< qspi xip read select mode t */
+} qspi_xip_read_sel_type;
+
+/**
+ * @brief qspi xip write access mode type
+ */
+typedef enum
+{
+ QSPI_XIPW_SEL_MODED = 0x00, /*!< qspi xip write select mode d */
+ QSPI_XIPW_SEL_MODET = 0x01 /*!< qspi xip write select mode t */
+} qspi_xip_write_sel_type;
+
+/**
+ * @brief qspi busy bit offset position in status register type
+ */
+typedef enum
+{
+ QSPI_BUSY_OFFSET_0 = 0x00, /*!< qspi busy bit offset position 0 */
+ QSPI_BUSY_OFFSET_1 = 0x01, /*!< qspi busy bit offset position 1 */
+ QSPI_BUSY_OFFSET_2 = 0x02, /*!< qspi busy bit offset position 2 */
+ QSPI_BUSY_OFFSET_3 = 0x03, /*!< qspi busy bit offset position 3 */
+ QSPI_BUSY_OFFSET_4 = 0x04, /*!< qspi busy bit offset position 4 */
+ QSPI_BUSY_OFFSET_5 = 0x05, /*!< qspi busy bit offset position 5 */
+ QSPI_BUSY_OFFSET_6 = 0x06, /*!< qspi busy bit offset position 6 */
+ QSPI_BUSY_OFFSET_7 = 0x07 /*!< qspi busy bit offset position 7 */
+} qspi_busy_pos_type;
+
+/**
+ * @brief qspi read status configure type
+ */
+typedef enum
+{
+ QSPI_RSTSC_HW_AUTO = 0x00, /*!< qspi read status by hardware */
+ QSPI_RSTSC_SW_ONCE = 0x01 /*!< qspi read status by software */
+} qspi_read_status_conf_type;
+
+/**
+ * @brief qspi operate mode type
+ */
+typedef enum
+{
+ QSPI_OPERATE_MODE_111 = 0x00, /*!< qspi serial mode */
+ QSPI_OPERATE_MODE_112 = 0x01, /*!< qspi dual mode */
+ QSPI_OPERATE_MODE_114 = 0x02, /*!< qspi quad mode */
+ QSPI_OPERATE_MODE_122 = 0x03, /*!< qspi dual i/o mode */
+ QSPI_OPERATE_MODE_144 = 0x04, /*!< qspi quad i/o mode */
+ QSPI_OPERATE_MODE_222 = 0x05, /*!< qspi instruction 2-bit mode */
+ QSPI_OPERATE_MODE_444 = 0x06 /*!< qspi instruction 4-bit mode(qpi) */
+} qspi_operate_mode_type;
+
+/**
+ * @brief qspi clock division type
+ */
+typedef enum
+{
+ QSPI_CLK_DIV_2 = 0x00, /*!< qspi clk divide by 2 */
+ QSPI_CLK_DIV_4 = 0x01, /*!< qspi clk divide by 4 */
+ QSPI_CLK_DIV_6 = 0x02, /*!< qspi clk divide by 6 */
+ QSPI_CLK_DIV_8 = 0x03, /*!< qspi clk divide by 8 */
+ QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */
+ QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */
+ QSPI_CLK_DIV_10 = 0x06, /*!< qspi clk divide by 10 */
+ QSPI_CLK_DIV_12 = 0x07 /*!< qspi clk divide by 12 */
+} qspi_clk_div_type;
+
+/**
+ * @brief qspi command port address length type
+ */
+typedef enum
+{
+ QSPI_CMD_ADRLEN_0_BYTE = 0x00, /*!< qspi no address */
+ QSPI_CMD_ADRLEN_1_BYTE = 0x01, /*!< qspi address length 1 byte */
+ QSPI_CMD_ADRLEN_2_BYTE = 0x02, /*!< qspi address length 2 byte */
+ QSPI_CMD_ADRLEN_3_BYTE = 0x03, /*!< qspi address length 3 byte */
+ QSPI_CMD_ADRLEN_4_BYTE = 0x04 /*!< qspi address length 4 byte */
+} qspi_cmd_adrlen_type;
+
+/**
+ * @brief qspi command port instruction length type
+ */
+typedef enum
+{
+ QSPI_CMD_INSLEN_0_BYTE = 0x00, /*!< qspi no instruction code */
+ QSPI_CMD_INSLEN_1_BYTE = 0x01, /*!< qspi instruction code 1 byte */
+ QSPI_CMD_INSLEN_2_BYTE = 0x02 /*!< qspi instruction code 2 byte(repeat) */
+} qspi_cmd_inslen_type;
+
+/**
+ * @brief qspi xip r/w address length type
+ */
+typedef enum
+{
+ QSPI_XIP_ADDRLEN_3_BYTE = 0x00, /*!< qspi xip address length 3 byte */
+ QSPI_XIP_ADDRLEN_4_BYTE = 0x01 /*!< qspi xip address length 4 byte */
+} qspi_xip_addrlen_type;
+
+/**
+ * @brief qspi sckout mode type
+ */
+typedef enum
+{
+ QSPI_SCK_MODE_0 = 0x00, /*!< qspi sck mode 0 */
+ QSPI_SCK_MODE_3 = 0x01 /*!< qspi sck mode 3 */
+} qspi_clk_mode_type;
+
+/**
+ * @brief qspi dma tx/rx fifo threshold type
+ */
+typedef enum
+{
+ QSPI_DMA_FIFO_THOD_WORD08 = 0x00, /*!< qspi dma fifo threshold 8 words */
+ QSPI_DMA_FIFO_THOD_WORD16 = 0x01, /*!< qspi dma fifo threshold 16 words */
+ QSPI_DMA_FIFO_THOD_WORD32 = 0x02 /*!< qspi dma fifo threshold 32 words */
+} qspi_dma_fifo_thod_type;
+
+/**
+ * @brief qspi cmd type
+ */
+typedef struct
+{
+ confirm_state pe_mode_enable; /*!< perfornance enhance mode enable */
+ uint8_t pe_mode_operate_code; /*!< performance enhance mode operate code */
+ uint8_t instruction_code; /*!< instruction code */
+ qspi_cmd_inslen_type instruction_length; /*!< instruction code length */
+ uint32_t address_code; /*!< address code */
+ qspi_cmd_adrlen_type address_length; /*!< address legnth */
+ uint32_t data_counter; /*!< read/write data counter */
+ uint8_t second_dummy_cycle_num; /*!< number of second dummy state cycle 0~32 */
+ qspi_operate_mode_type operation_mode; /*!< operation mode */
+ qspi_read_status_conf_type read_status_config; /*!< config to read status */
+ confirm_state read_status_enable; /*!< config to read status */
+ confirm_state write_data_enable; /*!< enable to write data */
+} qspi_cmd_type;
+
+/**
+ * @brief qspi xip type
+ */
+typedef struct
+{
+ uint8_t read_instruction_code; /*!< read instruction code */
+ qspi_xip_addrlen_type read_address_length; /*!< read address legnth */
+ qspi_operate_mode_type read_operation_mode; /*!< read operation mode */
+ uint8_t read_second_dummy_cycle_num; /*!< read number of second dummy state cycle 0~32 */
+ uint8_t write_instruction_code; /*!< write instruction code */
+ qspi_xip_addrlen_type write_address_length; /*!< write address legnth */
+ qspi_operate_mode_type write_operation_mode; /*!< write operation mode */
+ uint8_t write_second_dummy_cycle_num; /*!< write number of second dummy state cycle 0~32 */
+ qspi_xip_write_sel_type write_select_mode; /*!< write mode d or mode t selection */
+ uint8_t write_time_counter; /*!< write count for mode t */
+ uint8_t write_data_counter; /*!< write count for mode d */
+ qspi_xip_read_sel_type read_select_mode; /*!< read mode d or mode t selection */
+ uint8_t read_time_counter; /*!< read count for mode t */
+ uint8_t read_data_counter; /*!< read count for mode d */
+} qspi_xip_type;
+
+/**
+ * @brief type define qspi register all
+ */
+typedef struct
+{
+ /**
+ * @brief qspi cmd_w0 register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t cmd_w0;
+ struct
+ {
+
+ __IO uint32_t spiadr : 32;/* [31:0] */
+ } cmd_w0_bit;
+ };
+
+ /**
+ * @brief qspi cmd_w1 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t cmd_w1;
+ struct
+ {
+ __IO uint32_t adrlen : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 13;/* [15:3] */
+ __IO uint32_t dum2 : 8; /* [23:16] */
+ __IO uint32_t inslen : 2; /* [25:24] */
+ __IO uint32_t reserved2 : 2; /* [27:26] */
+ __IO uint32_t pemen : 1; /* [28] */
+ __IO uint32_t reserved3 : 3; /* [31:29] */
+ } cmd_w1_bit;
+ };
+
+ /**
+ * @brief qspi cmd_w2 register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t cmd_w2;
+ struct
+ {
+ __IO uint32_t dcnt : 32;/* [31:0] */
+ } cmd_w2_bit;
+ };
+
+ /**
+ * @brief qspi cmd_w3 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t cmd_w3;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t wen : 1; /* [1] */
+ __IO uint32_t rstsen : 1; /* [2] */
+ __IO uint32_t rstsc : 1; /* [3] */
+ __IO uint32_t reserved2 : 1; /* [4] */
+ __IO uint32_t opmode : 3; /* [7:5] */
+ __IO uint32_t reserved3 : 8; /* [15:8] */
+ __IO uint32_t pemopc : 8; /* [23:16] */
+ __IO uint32_t insc : 8; /* [31:24] */
+ } cmd_w3_bit;
+ };
+
+ /**
+ * @brief qspi ctrl register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t clkdiv : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t sckmode : 1; /* [4] */
+ __IO uint32_t reserved2 : 2; /* [6:5] */
+ __IO uint32_t xipidle : 1; /* [7] */
+ __IO uint32_t abort : 1; /* [8] */
+ __IO uint32_t reserved3 : 7; /* [15:9] */
+ __IO uint32_t busy : 3; /* [18:16] */
+ __IO uint32_t xiprcmdf : 1; /* [19] */
+ __IO uint32_t xipsel : 1; /* [20] */
+ __IO uint32_t keyen : 1; /* [21] */
+ __IO uint32_t reserved4 : 10;/* [31:22] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief qspi actr register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t actr;
+ struct
+ {
+ __IO uint32_t csdly : 4; /* [3:0] */
+ __IO uint32_t reserved1 : 28;/* [31:4] */
+ } actr_bit;
+ };
+
+ /**
+ * @brief qspi fifosts register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t fifosts;
+ struct
+ {
+ __IO uint32_t txfifordy : 1; /* [0] */
+ __IO uint32_t rxfifordy : 1; /* [1] */
+ __IO uint32_t reserved1 : 30;/* [31:2] */
+ } fifosts_bit;
+ };
+
+ /**
+ * @brief qspi reserved register, offset:0x1C
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief qspi ctrl2 register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t dmaen : 1; /* [0] */
+ __IO uint32_t cmdie : 1; /* [1] */
+ __IO uint32_t reserved1 : 6; /* [7:2] */
+ __IO uint32_t txfifo_thod : 2; /* [9:8] */
+ __IO uint32_t reserved2 : 2; /* [11:10] */
+ __IO uint32_t rxfifo_thod : 2; /* [13:12] */
+ __IO uint32_t reserved3 : 18;/* [31:14] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief qspi cmdsts register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t cmdsts;
+ struct
+ {
+ __IO uint32_t cmdsts : 1; /* [0] */
+ __IO uint32_t reserved1 : 31;/* [31:1] */
+ } cmdsts_bit;
+ };
+
+ /**
+ * @brief qspi rsts register, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t rsts;
+ struct
+ {
+ __IO uint32_t spists : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } rsts_bit;
+ };
+
+ /**
+ * @brief qspi fsize register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t fsize;
+ struct
+ {
+ __IO uint32_t spifsize : 32;/* [31:0] */
+ } fsize_bit;
+ };
+
+ /**
+ * @brief qspi xip_cmd_w0 register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t xip_cmd_w0;
+ struct
+ {
+ __IO uint32_t xipr_dum2 : 8; /* [7:0] */
+ __IO uint32_t xipr_opmode : 3; /* [10:8] */
+ __IO uint32_t xipr_adrlen : 1; /* [11] */
+ __IO uint32_t xipr_insc : 8; /* [19:12] */
+ __IO uint32_t reserved1 : 12;/* [31:20] */
+ } xip_cmd_w0_bit;
+ };
+
+ /**
+ * @brief qspi xip_cmd_w1 register, offset:0x34
+ */
+ union
+ {
+ __IO uint32_t xip_cmd_w1;
+ struct
+ {
+ __IO uint32_t xipr_dum2 : 8; /* [7:0] */
+ __IO uint32_t xipr_opmode : 3; /* [10:8] */
+ __IO uint32_t xipr_adrlen : 1; /* [11] */
+ __IO uint32_t xipr_insc : 8; /* [19:12] */
+ __IO uint32_t reserved1 : 12;/* [31:20] */
+ } xip_cmd_w1_bit;
+ };
+
+ /**
+ * @brief qspi xip_cmd_w2 register, offset:0x38
+ */
+ union
+ {
+ __IO uint32_t xip_cmd_w2;
+ struct
+ {
+ __IO uint32_t xipr_dcnt : 6; /* [5:0] */
+ __IO uint32_t reserved1 : 2; /* [7:6] */
+ __IO uint32_t xipr_tcnt : 7; /* [14:8] */
+ __IO uint32_t xipr_sel : 1; /* [15] */
+ __IO uint32_t xipw_dcnt : 6; /* [21:16] */
+ __IO uint32_t reserved2 : 2; /* [23:22] */
+ __IO uint32_t xipw_tcnt : 7; /* [30:24] */
+ __IO uint32_t xipw_sel : 1; /* [31] */
+ } xip_cmd_w2_bit;
+ };
+
+ /**
+ * @brief qspi xip_cmd_w3 register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t xip_cmd_w3;
+ struct
+ {
+ __IO uint32_t bypassc : 1; /* [0] */
+ __IO uint32_t reserved1 : 2; /* [2:1] */
+ __IO uint32_t csts : 1; /* [3] */
+ __IO uint32_t reserved2 : 28;/* [31:4] */
+ } xip_cmd_w3_bit;
+ };
+
+ /**
+ * @brief qspi reserved register, offset:0x40~4C
+ */
+ __IO uint32_t reserved2[4];
+
+ /**
+ * @brief qspi rev register, offset:0x50
+ */
+ union
+ {
+ __IO uint32_t rev;
+ struct
+ {
+ __IO uint32_t rev : 32;/* [31:0] */
+ } rev_bit;
+ };
+
+ /**
+ * @brief qspi reserved register, offset:0x54~FC
+ */
+ __IO uint32_t reserved3[43];
+
+ /**
+ * @brief qspi dt register, offset:0x100
+ */
+ union
+ {
+ __IO uint8_t dt_u8;
+ __IO uint16_t dt_u16;
+ __IO uint32_t dt;
+ struct
+ {
+ __IO uint32_t dt : 32;/* [31:0] */
+ } dt_bit;
+ };
+
+} qspi_type;
+
+/**
+ * @}
+ */
+
+#define QSPI1 ((qspi_type*)QSPI1_REG_BASE)
+#define QSPI2 ((qspi_type*)QSPI2_REG_BASE)
+
+/** @defgroup QSPI_exported_functions
+ * @{
+ */
+
+void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state);
+void qspi_sck_mode_set( qspi_type* qspi_x, qspi_clk_mode_type new_mode);
+void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv);
+void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state);
+void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state);
+flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag);
+void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag);
+void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
+void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
+void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state);
+void qspi_busy_config(qspi_type* qspi_x, qspi_busy_pos_type busy_pos);
+void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state);
+void qspi_cmd_operation_kick(qspi_type* qspi_x, qspi_cmd_type* qspi_cmd_struct);
+void qspi_xip_init(qspi_type* qspi_x, qspi_xip_type* xip_init_struct);
+uint8_t qspi_byte_read(qspi_type* qspi_x);
+uint16_t qspi_half_word_read(qspi_type* qspi_x);
+uint32_t qspi_word_read(qspi_type* qspi_x);
+void qspi_word_write(qspi_type* qspi_x, uint32_t value);
+void qspi_half_word_write(qspi_type* qspi_x, uint16_t value);
+void qspi_byte_write(qspi_type* qspi_x, uint8_t value);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_scfg.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_scfg.h
new file mode 100644
index 0000000..332098f
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_scfg.h
@@ -0,0 +1,323 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_scfg.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 system config header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_SCFG_H
+#define __AT32F435_437_SCFG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup SCFG
+ * @{
+ */
+
+#define SCFG_REG(value) PERIPH_REG(SCFG_BASE, value)
+#define SCFG_REG_BIT(value) PERIPH_REG_BIT(value)
+
+/** @defgroup SCFG_exported_types
+ * @{
+ */
+
+/**
+ * @brief scfg xmc addres mapping swap type
+ */
+typedef enum
+{
+ SCFG_XMC_SWAP_NONE = 0x00, /* no swap */
+ SCFG_XMC_SWAP_MODE1 = 0x01, /* sdram nor psram sram nand2 swap */
+ SCFG_XMC_SWAP_MODE2 = 0x02, /* nand3 qspi2 swap */
+ SCFG_XMC_SWAP_MODE3 = 0x03 /* sdram nor psram sram nand2 nand3 qspi2 swap */
+} scfg_xmc_swap_type;
+
+/**
+ * @brief scfg infrared modulation signal source selecting type
+ */
+typedef enum
+{
+ SCFG_IR_SOURCE_TMR10 = 0x00, /* infrared signal source select tmr10 */
+ SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */
+ SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */
+} scfg_ir_source_type;
+
+/**
+ * @brief scfg infrared output polarity selecting type
+ */
+typedef enum
+{
+ SCFG_IR_POLARITY_NO_AFFECTE = 0x00, /* infrared output polarity no affecte */
+ SCFG_IR_POLARITY_REVERSE = 0x01 /* infrared output polarity reverse */
+} scfg_ir_polarity_type;
+
+/**
+ * @brief scfg memory address mapping selecting type
+ */
+typedef enum
+{
+ SCFG_MEM_MAP_MAIN_MEMORY = 0x00, /* 0x00000000 address mapping from main memory */
+ SCFG_MEM_MAP_BOOT_MEMORY = 0x01, /* 0x00000000 address mapping from boot memory */
+ SCFG_MEM_MAP_XMC_BANK1 = 0x02, /* 0x00000000 address mapping from xmc bank1 */
+ SCFG_MEM_MAP_INTERNAL_SRAM = 0x03, /* 0x00000000 address mapping from internal sram */
+ SCFG_MEM_MAP_XMC_SDRAM_BANK1 = 0x04 /* 0x00000000 address mapping from xmc sdram bank1 */
+} scfg_mem_map_type;
+
+/**
+ * @brief scfg pin source type
+ */
+typedef enum
+{
+ SCFG_PINS_SOURCE0 = 0x00,
+ SCFG_PINS_SOURCE1 = 0x01,
+ SCFG_PINS_SOURCE2 = 0x02,
+ SCFG_PINS_SOURCE3 = 0x03,
+ SCFG_PINS_SOURCE4 = 0x04,
+ SCFG_PINS_SOURCE5 = 0x05,
+ SCFG_PINS_SOURCE6 = 0x06,
+ SCFG_PINS_SOURCE7 = 0x07,
+ SCFG_PINS_SOURCE8 = 0x08,
+ SCFG_PINS_SOURCE9 = 0x09,
+ SCFG_PINS_SOURCE10 = 0x0A,
+ SCFG_PINS_SOURCE11 = 0x0B,
+ SCFG_PINS_SOURCE12 = 0x0C,
+ SCFG_PINS_SOURCE13 = 0x0D,
+ SCFG_PINS_SOURCE14 = 0x0E,
+ SCFG_PINS_SOURCE15 = 0x0F
+} scfg_pins_source_type;
+
+/**
+ * @brief gpio port source type
+ */
+typedef enum
+{
+ SCFG_PORT_SOURCE_GPIOA = 0x00,
+ SCFG_PORT_SOURCE_GPIOB = 0x01,
+ SCFG_PORT_SOURCE_GPIOC = 0x02,
+ SCFG_PORT_SOURCE_GPIOD = 0x03,
+ SCFG_PORT_SOURCE_GPIOE = 0x04,
+ SCFG_PORT_SOURCE_GPIOF = 0x05,
+ SCFG_PORT_SOURCE_GPIOG = 0x06,
+ SCFG_PORT_SOURCE_GPIOH = 0x07
+} scfg_port_source_type;
+
+/**
+ * @brief scfg emac interface selecting type
+ */
+typedef enum
+{
+ SCFG_EMAC_SELECT_MII = 0x00, /* emac interface select mii mode */
+ SCFG_EMAC_SELECT_RMII = 0x01 /* emac interface select rmii mode */
+} scfg_emac_interface_type;
+
+/**
+ * @brief scfg ultra high sourcing/sinking strength pins type
+ */
+typedef enum
+{
+ SCFG_ULTRA_DRIVEN_PB3 = MAKE_VALUE(0x2C, 0),
+ SCFG_ULTRA_DRIVEN_PB9 = MAKE_VALUE(0x2C, 1),
+ SCFG_ULTRA_DRIVEN_PB10 = MAKE_VALUE(0x2C, 2),
+ SCFG_ULTRA_DRIVEN_PD12 = MAKE_VALUE(0x2C, 5),
+ SCFG_ULTRA_DRIVEN_PD13 = MAKE_VALUE(0x2C, 6),
+ SCFG_ULTRA_DRIVEN_PD14 = MAKE_VALUE(0x2C, 7),
+ SCFG_ULTRA_DRIVEN_PD15 = MAKE_VALUE(0x2C, 8),
+ SCFG_ULTRA_DRIVEN_PF14 = MAKE_VALUE(0x2C, 9),
+ SCFG_ULTRA_DRIVEN_PF15 = MAKE_VALUE(0x2C, 10)
+} scfg_ultra_driven_pins_type;
+
+/**
+ * @brief type define system config register all
+ */
+typedef struct
+{
+ /**
+ * @brief scfg cfg1 register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t cfg1;
+ struct
+ {
+ __IO uint32_t mem_map_sel : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 2; /* [4:3] */
+ __IO uint32_t ir_pol : 1; /* [5] */
+ __IO uint32_t ir_src_sel : 2; /* [7:6] */
+ __IO uint32_t reserved2 : 2; /* [9:8] */
+ __IO uint32_t swap_xmc : 2; /* [11:10] */
+ __IO uint32_t reserved3 : 20;/* [31:12] */
+ } cfg1_bit;
+ };
+
+ /**
+ * @brief scfg cfg2 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t cfg2;
+ struct
+ {
+ __IO uint32_t reserved1 : 23;/* [22:0] */
+ __IO uint32_t mii_rmii_sel : 1; /* [23] */
+ __IO uint32_t reserved2 : 8; /* [31:24] */
+ } cfg2_bit;
+ };
+
+ /**
+ * @brief scfg exintc1 register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t exintc1;
+ struct
+ {
+ __IO uint32_t exint0 : 4; /* [3:0] */
+ __IO uint32_t exint1 : 4; /* [7:4] */
+ __IO uint32_t exint2 : 4; /* [11:8] */
+ __IO uint32_t exint3 : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } exintc1_bit;
+ };
+
+ /**
+ * @brief scfg exintc2 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t exintc2;
+ struct
+ {
+ __IO uint32_t exint4 : 4; /* [3:0] */
+ __IO uint32_t exint5 : 4; /* [7:4] */
+ __IO uint32_t exint6 : 4; /* [11:8] */
+ __IO uint32_t exint7 : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } exintc2_bit;
+ };
+
+ /**
+ * @brief scfg exintc3 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t exintc3;
+ struct
+ {
+ __IO uint32_t exint8 : 4; /* [3:0] */
+ __IO uint32_t exint9 : 4; /* [7:4] */
+ __IO uint32_t exint10 : 4; /* [11:8] */
+ __IO uint32_t exint11 : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } exintc3_bit;
+ };
+
+ /**
+ * @brief scfg exintc4 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t exintc4;
+ struct
+ {
+ __IO uint32_t exint12 : 4; /* [3:0] */
+ __IO uint32_t exint13 : 4; /* [7:4] */
+ __IO uint32_t exint14 : 4; /* [11:8] */
+ __IO uint32_t exint15 : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } exintc4_bit;
+ };
+
+ /**
+ * @brief crm reserved1 register, offset:0x18~0x28
+ */
+ __IO uint32_t reserved1[5];
+
+ /**
+ * @brief scfg uhdrv register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t uhdrv;
+ struct
+ {
+ __IO uint32_t pb3_uh : 1; /* [0] */
+ __IO uint32_t pb9_uh : 1; /* [1] */
+ __IO uint32_t pb10_uh : 1; /* [2] */
+ __IO uint32_t reserved1 : 2; /* [4:3] */
+ __IO uint32_t pd12_uh : 1; /* [5] */
+ __IO uint32_t pd13_uh : 1; /* [6] */
+ __IO uint32_t pd14_uh : 1; /* [7] */
+ __IO uint32_t pd15_uh : 1; /* [8] */
+ __IO uint32_t pf14_uh : 1; /* [9] */
+ __IO uint32_t pf15_uh : 1; /* [10] */
+ __IO uint32_t reserved2 : 21;/* [31:11] */
+ } uhdrv_bit;
+ };
+
+} scfg_type;
+
+/**
+ * @}
+ */
+
+#define SCFG ((scfg_type *) SCFG_BASE)
+
+/** @defgroup SCFG_exported_functions
+ * @{
+ */
+
+void scfg_reset(void);
+void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap);
+void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity);
+void scfg_mem_map_set(scfg_mem_map_type mem_map);
+void scfg_emac_interface_set(scfg_emac_interface_type mode);
+void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source);
+void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_sdio.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_sdio.h
new file mode 100644
index 0000000..babd040
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_sdio.h
@@ -0,0 +1,624 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_sdio.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 sdio header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_SDIO_H
+#define __AT32F435_437_SDIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup SDIO
+ * @{
+ */
+
+/** @defgroup SDIO_interrupts_definition
+ * @brief sdio interrupt
+ * @{
+ */
+
+#define SDIO_CMDFAIL_INT ((uint32_t)0x00000001) /*!< command response received check failed interrupt */
+#define SDIO_DTFAIL_INT ((uint32_t)0x00000002) /*!< data block sent/received check failed interrupt */
+#define SDIO_CMDTIMEOUT_INT ((uint32_t)0x00000004) /*!< command response timerout interrupt */
+#define SDIO_DTTIMEOUT_INT ((uint32_t)0x00000008) /*!< data timeout interrupt */
+#define SDIO_TXERRU_INT ((uint32_t)0x00000010) /*!< transmit underrun error interrupt */
+#define SDIO_RXERRO_INT ((uint32_t)0x00000020) /*!< received overrun error interrupt */
+#define SDIO_CMDRSPCMPL_INT ((uint32_t)0x00000040) /*!< command response received interrupt */
+#define SDIO_CMDCMPL_INT ((uint32_t)0x00000080) /*!< command sent interrupt */
+#define SDIO_DTCMP_INT ((uint32_t)0x00000100) /*!< data sent interrupt */
+#define SDIO_SBITERR_INT ((uint32_t)0x00000200) /*!< start bit not detected on data bus interrupt */
+#define SDIO_DTBLKCMPL_INT ((uint32_t)0x00000400) /*!< data block sent/received interrupt */
+#define SDIO_DOCMD_INT ((uint32_t)0x00000800) /*!< command transfer in progress interrupt */
+#define SDIO_DOTX_INT ((uint32_t)0x00001000) /*!< data transmit in progress interrupt */
+#define SDIO_DORX_INT ((uint32_t)0x00002000) /*!< data receive in progress interrupt */
+#define SDIO_TXBUFH_INT ((uint32_t)0x00004000) /*!< transmit buf half empty interrupt */
+#define SDIO_RXBUFH_INT ((uint32_t)0x00008000) /*!< receive buf half full interrupt */
+#define SDIO_TXBUFF_INT ((uint32_t)0x00010000) /*!< transmit buf full interrupt */
+#define SDIO_RXBUFF_INT ((uint32_t)0x00020000) /*!< receive buf full interrupt */
+#define SDIO_TXBUFE_INT ((uint32_t)0x00040000) /*!< transmit buf empty interrupt */
+#define SDIO_RXBUFE_INT ((uint32_t)0x00080000) /*!< receive buf empty interrupt */
+#define SDIO_TXBUF_INT ((uint32_t)0x00100000) /*!< data available in transmit interrupt */
+#define SDIO_RXBUF_INT ((uint32_t)0x00200000) /*!< data available in receive interrupt */
+#define SDIO_SDIOIF_INT ((uint32_t)0x00400000) /*!< sdio interface received interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_flags_definition
+ * @brief sdio flag
+ * @{
+ */
+
+#define SDIO_CMDFAIL_FLAG ((uint32_t)0x00000001) /*!< command response received check failed flag */
+#define SDIO_DTFAIL_FLAG ((uint32_t)0x00000002) /*!< data block sent/received check failed flag */
+#define SDIO_CMDTIMEOUT_FLAG ((uint32_t)0x00000004) /*!< command response timerout flag */
+#define SDIO_DTTIMEOUT_FLAG ((uint32_t)0x00000008) /*!< data timeout flag */
+#define SDIO_TXERRU_FLAG ((uint32_t)0x00000010) /*!< transmit underrun error flag */
+#define SDIO_RXERRO_FLAG ((uint32_t)0x00000020) /*!< received overrun error flag */
+#define SDIO_CMDRSPCMPL_FLAG ((uint32_t)0x00000040) /*!< command response received flag */
+#define SDIO_CMDCMPL_FLAG ((uint32_t)0x00000080) /*!< command sent flag */
+#define SDIO_DTCMPL_FLAG ((uint32_t)0x00000100) /*!< data sent flag */
+#define SDIO_SBITERR_FLAG ((uint32_t)0x00000200) /*!< start bit not detected on data bus flag */
+#define SDIO_DTBLKCMPL_FLAG ((uint32_t)0x00000400) /*!< data block sent/received flag */
+#define SDIO_DOCMD_FLAG ((uint32_t)0x00000800) /*!< command transfer in progress flag */
+#define SDIO_DOTX_FLAG ((uint32_t)0x00001000) /*!< data transmit in progress flag */
+#define SDIO_DORX_FLAG ((uint32_t)0x00002000) /*!< data receive in progress flag */
+#define SDIO_TXBUFH_FLAG ((uint32_t)0x00004000) /*!< transmit buf half empty flag */
+#define SDIO_RXBUFH_FLAG ((uint32_t)0x00008000) /*!< receive buf half full flag */
+#define SDIO_TXBUFF_FLAG ((uint32_t)0x00010000) /*!< transmit buf full flag */
+#define SDIO_RXBUFF_FLAG ((uint32_t)0x00020000) /*!< receive buf full flag */
+#define SDIO_TXBUFE_FLAG ((uint32_t)0x00040000) /*!< transmit buf empty flag */
+#define SDIO_RXBUFE_FLAG ((uint32_t)0x00080000) /*!< receive buf empty flag */
+#define SDIO_TXBUF_FLAG ((uint32_t)0x00100000) /*!< data available in transmit flag */
+#define SDIO_RXBUF_FLAG ((uint32_t)0x00200000) /*!< data available in receive flag */
+#define SDIO_SDIOIF_FLAG ((uint32_t)0x00400000) /*!< sdio interface received flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_exported_types
+ * @{
+ */
+
+/**
+ * @brief sdio power state
+ */
+typedef enum
+{
+ SDIO_POWER_OFF = 0x00, /*!< power-off, clock to card is stopped */
+ SDIO_POWER_ON = 0x03 /*!< power-on, the card is clocked */
+} sdio_power_state_type;
+
+/**
+ * @brief sdio edge phase
+ */
+typedef enum
+{
+ SDIO_CLOCK_EDGE_RISING = 0x00, /*!< sdio bus clock generated on the rising edge of the master clock */
+ SDIO_CLOCK_EDGE_FALLING = 0x01 /*!< sdio bus clock generated on the falling edge of the master clock */
+} sdio_edge_phase_type;
+
+/**
+ * @brief sdio bus width
+ */
+typedef enum
+{
+ SDIO_BUS_WIDTH_D1 = 0x00, /*!< sdio wide bus select 1-bit */
+ SDIO_BUS_WIDTH_D4 = 0x01, /*!< sdio wide bus select 4-bit */
+ SDIO_BUS_WIDTH_D8 = 0x02 /*!< sdio wide bus select 8-bit */
+} sdio_bus_width_type;
+
+/**
+ * @brief sdio response type
+ */
+typedef enum
+{
+ SDIO_RESPONSE_NO = 0x00, /*!< no response */
+ SDIO_RESPONSE_SHORT = 0x01, /*!< short response */
+ SDIO_RESPONSE_LONG = 0x03 /*!< long response */
+} sdio_reponse_type;
+
+/**
+ * @brief sdio wait type
+ */
+typedef enum
+{
+ SDIO_WAIT_FOR_NO = 0x00, /*!< no wait */
+ SDIO_WAIT_FOR_INT = 0x01, /*!< wait interrupt request */
+ SDIO_WAIT_FOR_PEND = 0x02 /*!< wait end of transfer */
+} sdio_wait_type;
+
+/**
+ * @brief sdio response register index
+ */
+typedef enum
+{
+ SDIO_RSP1_INDEX = 0x00, /*!< response index 1, corresponding to sdio_rsp register 1 */
+ SDIO_RSP2_INDEX = 0x01, /*!< response index 2, corresponding to sdio_rsp register 2 */
+ SDIO_RSP3_INDEX = 0x02, /*!< response index 3, corresponding to sdio_rsp register 3 */
+ SDIO_RSP4_INDEX = 0x03 /*!< response index 4, corresponding to sdio_rsp register 4 */
+} sdio_rsp_index_type;
+
+/**
+ * @brief sdio data block size
+ */
+typedef enum
+{
+ SDIO_DATA_BLOCK_SIZE_1B = 0x00, /*!< data block size 1 byte */
+ SDIO_DATA_BLOCK_SIZE_2B = 0x01, /*!< data block size 2 bytes */
+ SDIO_DATA_BLOCK_SIZE_4B = 0x02, /*!< data block size 4 bytes */
+ SDIO_DATA_BLOCK_SIZE_8B = 0x03, /*!< data block size 8 bytes */
+ SDIO_DATA_BLOCK_SIZE_16B = 0x04, /*!< data block size 16 bytes */
+ SDIO_DATA_BLOCK_SIZE_32B = 0x05, /*!< data block size 32 bytes */
+ SDIO_DATA_BLOCK_SIZE_64B = 0x06, /*!< data block size 64 bytes */
+ SDIO_DATA_BLOCK_SIZE_128B = 0x07, /*!< data block size 128 bytes */
+ SDIO_DATA_BLOCK_SIZE_256B = 0x08, /*!< data block size 256 bytes */
+ SDIO_DATA_BLOCK_SIZE_512B = 0x09, /*!< data block size 512 bytes */
+ SDIO_DATA_BLOCK_SIZE_1024B = 0x0A, /*!< data block size 1024 bytes */
+ SDIO_DATA_BLOCK_SIZE_2048B = 0x0B, /*!< data block size 2048 bytes */
+ SDIO_DATA_BLOCK_SIZE_4096B = 0x0C, /*!< data block size 4096 bytes */
+ SDIO_DATA_BLOCK_SIZE_8192B = 0x0D, /*!< data block size 8192 bytes */
+ SDIO_DATA_BLOCK_SIZE_16384B = 0x0E /*!< data block size 16384 bytes */
+} sdio_block_size_type;
+
+/**
+ * @brief sdio data transfer mode
+ */
+typedef enum
+{
+ SDIO_DATA_BLOCK_TRANSFER = 0x00, /*!< the sdio block transfer mode */
+ SDIO_DATA_STREAM_TRANSFER = 0x01 /*!< the sdio stream transfer mode */
+} sdio_transfer_mode_type;
+
+/**
+ * @brief sdio data transfer direction
+ */
+typedef enum
+{
+ SDIO_DATA_TRANSFER_TO_CARD = 0x00, /*!< the sdio controller write */
+ SDIO_DATA_TRANSFER_TO_CONTROLLER = 0x01 /*!< the sdio controller read */
+} sdio_transfer_direction_type;
+
+/**
+ * @brief sdio read wait mode
+ */
+typedef enum
+{
+ SDIO_READ_WAIT_CONTROLLED_BY_D2 = 0x00, /*!< the sdio read wait on data2 line */
+ SDIO_READ_WAIT_CONTROLLED_BY_CK = 0x01 /*!< the sdio read wait on clock line */
+} sdio_read_wait_mode_type;
+
+/**
+ * @brief sdio command structure
+ */
+typedef struct
+{
+ uint32_t argument; /*!< the sdio command argument is sent to a card as part of command message */
+ uint8_t cmd_index; /*!< the sdio command index */
+ sdio_reponse_type rsp_type; /*!< the sdio response type */
+ sdio_wait_type wait_type; /*!< the sdio wait for interrupt request is enabled or disable */
+} sdio_command_struct_type;
+
+/**
+ * @brief sdio data structure
+ */
+typedef struct
+{
+ uint32_t timeout; /*!< the sdio data timeout period in car bus clock periods */
+ uint32_t data_length; /*!< the sdio data length */
+ sdio_block_size_type block_size; /*!< the sdio data block size of block transfer mode */
+ sdio_transfer_mode_type transfer_mode; /*!< the sdio transfer mode, block or stream */
+ sdio_transfer_direction_type transfer_direction; /*!< the sdio data transfer direction */
+} sdio_data_struct_type;
+
+/**
+ * @brief type define sdio register all
+ */
+typedef struct
+{
+ /**
+ * @brief sdio pwrctrl register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t pwrctrl;
+ struct
+ {
+ __IO uint32_t ps : 2; /* [1:0] */
+ __IO uint32_t reserved1 : 30;/* [31:2] */
+ } pwrctrl_bit;
+ };
+
+ /**
+ * @brief sdio clkctrl register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t clkctrl;
+ struct
+ {
+ __IO uint32_t clkdiv_l : 8; /* [7:0] */
+ __IO uint32_t clkoen : 1; /* [8] */
+ __IO uint32_t pwrsven : 1; /* [9] */
+ __IO uint32_t bypsen : 1; /* [10] */
+ __IO uint32_t busws : 2; /* [12:11] */
+ __IO uint32_t clkegs : 1; /* [13] */
+ __IO uint32_t hfcen : 1; /* [14] */
+ __IO uint32_t clkdiv_h : 2; /* [16:15] */
+ __IO uint32_t reserved1 : 15;/* [31:17] */
+ } clkctrl_bit;
+ };
+
+ /**
+ * @brief sdio argu register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t argu;
+ struct
+ {
+ __IO uint32_t argu : 32;/* [31:0] */
+ } argu_bit;
+ };
+
+ /**
+ * @brief sdio cmdctrl register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t cmdctrl;
+ struct
+ {
+ __IO uint32_t cmdidx : 6; /* [5:0] */
+ __IO uint32_t rspwt : 2; /* [7:6] */
+ __IO uint32_t intwt : 1; /* [8] */
+ __IO uint32_t pndwt : 1; /* [9] */
+ __IO uint32_t ccsmen : 1; /* [10] */
+ __IO uint32_t iosusp : 1; /* [11] */
+ __IO uint32_t reserved1 : 20;/* [31:12] */
+ } cmdctrl_bit;
+ };
+
+ /**
+ * @brief sdio rspcmd register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t rspcmd;
+ struct
+ {
+ __IO uint32_t rspcmd : 6; /* [5:0] */
+ __IO uint32_t reserved1 : 26;/* [31:6] */
+ } rspcmd_bit;
+ };
+
+ /**
+ * @brief sdio rsp1 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t rsp1;
+ struct
+ {
+ __IO uint32_t cardsts1 : 32;/* [31:0] */
+ } rsp1_bit;
+ };
+
+ /**
+ * @brief sdio rsp2 register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t rsp2;
+ struct
+ {
+ __IO uint32_t cardsts2 : 32;/* [31:0] */
+ } rsp2_bit;
+ };
+
+ /**
+ * @brief sdio rsp3 register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t rsp3;
+ struct
+ {
+ __IO uint32_t cardsts3 : 32;/* [31:0] */
+ } rsp3_bit;
+ };
+
+ /**
+ * @brief sdio rsp4 register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t rsp4;
+ struct
+ {
+ __IO uint32_t cardsts4 : 32;/* [31:0] */
+ } rsp4_bit;
+ };
+
+ /**
+ * @brief sdio dttmr register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t dttmr;
+ struct
+ {
+ __IO uint32_t timeout : 32;/* [31:0] */
+ } dttmr_bit;
+ };
+
+ /**
+ * @brief sdio dtlen register, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t dtlen;
+ struct
+ {
+ __IO uint32_t dtlen : 25;/* [24:0] */
+ __IO uint32_t reserved1 : 7; /* [31:25] */
+ } dtlen_bit;
+ };
+
+ /**
+ * @brief sdio dtctrl register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t dtctrl;
+ struct
+ {
+ __IO uint32_t tfren : 1; /* [0] */
+ __IO uint32_t tfrdir : 1; /* [1] */
+ __IO uint32_t tfrmode : 1; /* [2] */
+ __IO uint32_t dmaen : 1; /* [3] */
+ __IO uint32_t blksize : 4; /* [7:4] */
+ __IO uint32_t rdwtstart : 1; /* [8] */
+ __IO uint32_t rdwtstop : 1; /* [9] */
+ __IO uint32_t rdwtmode : 1; /* [10] */
+ __IO uint32_t ioen : 1; /* [11] */
+ __IO uint32_t reserved1 : 20;/* [31:12] */
+ } dtctrl_bit;
+ };
+
+ /**
+ * @brief sdio dtcnt register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t dtcnt;
+ struct
+ {
+ __IO uint32_t cnt : 25;/* [24:0] */
+ __IO uint32_t reserved1 : 7; /* [31:25] */
+ } dtcnt_bit;
+ };
+
+ /**
+ * @brief sdio sts register, offset:0x34
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t cmdfail : 1; /* [0] */
+ __IO uint32_t dtfail : 1; /* [1] */
+ __IO uint32_t cmdtimeout : 1; /* [2] */
+ __IO uint32_t dttimeout : 1; /* [3] */
+ __IO uint32_t txerru : 1; /* [4] */
+ __IO uint32_t rxerro : 1; /* [5] */
+ __IO uint32_t cmdrspcmpl : 1; /* [6] */
+ __IO uint32_t cmdcmpl : 1; /* [7] */
+ __IO uint32_t dtcmpl : 1; /* [8] */
+ __IO uint32_t sbiterr : 1; /* [9] */
+ __IO uint32_t dtblkcmpl : 1; /* [10] */
+ __IO uint32_t docmd : 1; /* [11] */
+ __IO uint32_t dotx : 1; /* [12] */
+ __IO uint32_t dorx : 1; /* [13] */
+ __IO uint32_t txbufh : 1; /* [14] */
+ __IO uint32_t rxbufh : 1; /* [15] */
+ __IO uint32_t txbuff : 1; /* [16] */
+ __IO uint32_t rxbuff : 1; /* [17] */
+ __IO uint32_t txbufe : 1; /* [18] */
+ __IO uint32_t rxbufe : 1; /* [19] */
+ __IO uint32_t txbuf : 1; /* [20] */
+ __IO uint32_t rxbuf : 1; /* [21] */
+ __IO uint32_t ioif : 1; /* [22] */
+ __IO uint32_t reserved1 : 9; /* [31:23] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief sdio intclr register, offset:0x38
+ */
+ union
+ {
+ __IO uint32_t intclr;
+ struct
+ {
+ __IO uint32_t cmdfail : 1; /* [0] */
+ __IO uint32_t dtfail : 1; /* [1] */
+ __IO uint32_t cmdtimeout : 1; /* [2] */
+ __IO uint32_t dttimeout : 1; /* [3] */
+ __IO uint32_t txerru : 1; /* [4] */
+ __IO uint32_t rxerro : 1; /* [5] */
+ __IO uint32_t cmdrspcmpl : 1; /* [6] */
+ __IO uint32_t cmdcmpl : 1; /* [7] */
+ __IO uint32_t dtcmpl : 1; /* [8] */
+ __IO uint32_t sbiterr : 1; /* [9] */
+ __IO uint32_t dtblkcmpl : 1; /* [10] */
+ __IO uint32_t reserved1 : 11;/* [21:11] */
+ __IO uint32_t ioif : 1; /* [22] */
+ __IO uint32_t reserved2 : 9; /* [31:23] */
+ } intclr_bit;
+ };
+
+ /**
+ * @brief sdio inten register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t inten;
+ struct
+ {
+ __IO uint32_t cmdfailien : 1; /* [0] */
+ __IO uint32_t dtfailien : 1; /* [1] */
+ __IO uint32_t cmdtimeoutien : 1; /* [2] */
+ __IO uint32_t dttimeoutien : 1; /* [3] */
+ __IO uint32_t txerruien : 1; /* [4] */
+ __IO uint32_t rxerroien : 1; /* [5] */
+ __IO uint32_t cmdrspcmplien : 1; /* [6] */
+ __IO uint32_t cmdcmplien : 1; /* [7] */
+ __IO uint32_t dtcmplien : 1; /* [8] */
+ __IO uint32_t sbiterrien : 1; /* [9] */
+ __IO uint32_t dtblkcmplien : 1; /* [10] */
+ __IO uint32_t docmdien : 1; /* [11] */
+ __IO uint32_t dotxien : 1; /* [12] */
+ __IO uint32_t dorxien : 1; /* [13] */
+ __IO uint32_t txbufhien : 1; /* [14] */
+ __IO uint32_t rxbufhien : 1; /* [15] */
+ __IO uint32_t txbuffien : 1; /* [16] */
+ __IO uint32_t rxbuffien : 1; /* [17] */
+ __IO uint32_t txbufeien : 1; /* [18] */
+ __IO uint32_t rxbufeien : 1; /* [19] */
+ __IO uint32_t txbufien : 1; /* [20] */
+ __IO uint32_t rxbufien : 1; /* [21] */
+ __IO uint32_t ioifien : 1; /* [22] */
+ __IO uint32_t reserved1 : 9; /* [31:23] */
+ } inten_bit;
+ };
+
+ /**
+ * @brief sdio reserved1 register, offset:0x40~0x44
+ */
+ __IO uint32_t reserved1[2];
+
+ /**
+ * @brief sdio bufcnt register, offset:0x48
+ */
+ union
+ {
+ __IO uint32_t bufcnt;
+ struct
+ {
+ __IO uint32_t cnt : 24;/* [23:0] */
+ __IO uint32_t reserved1 : 8; /* [31:24] */
+ } bufcnt_bit;
+ };
+
+ /**
+ * @brief sdio reserved2 register, offset:0x4C~0x7C
+ */
+ __IO uint32_t reserved2[13];
+
+ /**
+ * @brief sdio buf register, offset:0x80
+ */
+ union
+ {
+ __IO uint32_t buf;
+ struct
+ {
+ __IO uint32_t dt : 32;/* [31:0] */
+ } buf_bit;
+ };
+
+} sdio_type;
+
+/**
+ * @}
+ */
+
+#define SDIO1 ((sdio_type *) SDIO1_BASE)
+#define SDIO2 ((sdio_type *) SDIO2_BASE)
+
+/** @defgroup SDIO_exported_functions
+ * @{
+ */
+
+void sdio_reset(sdio_type *sdio_x);
+void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state);
+flag_status sdio_power_status_get(sdio_type *sdio_x);
+void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg);
+void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width);
+void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state);
+void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state);
+flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag);
+void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag);
+void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct);
+void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
+uint8_t sdio_command_response_get(sdio_type *sdio_x);
+uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index);
+void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct);
+void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
+uint32_t sdio_data_counter_get(sdio_type *sdio_x);
+uint32_t sdio_data_read(sdio_type *sdio_x);
+uint32_t sdio_buffer_counter_get(sdio_type *sdio_x);
+void sdio_data_write(sdio_type *sdio_x, uint32_t data);
+void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode);
+void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state);
+void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state);
+void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_spi.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_spi.h
new file mode 100644
index 0000000..6c65846
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_spi.h
@@ -0,0 +1,505 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_spi.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 spi header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_SPI_H
+#define __AT32F435_437_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/**
+ * @defgroup SPI_I2S_flags_definition
+ * @brief spi i2s flag
+ * @{
+ */
+
+#define SPI_I2S_RDBF_FLAG 0x0001 /*!< spi or i2s receive data buffer full flag */
+#define SPI_I2S_TDBE_FLAG 0x0002 /*!< spi or i2s transmit data buffer empty flag */
+#define I2S_ACS_FLAG 0x0004 /*!< i2s audio channel state flag */
+#define I2S_TUERR_FLAG 0x0008 /*!< i2s transmitter underload error flag */
+#define SPI_CCERR_FLAG 0x0010 /*!< spi crc calculation error flag */
+#define SPI_MMERR_FLAG 0x0020 /*!< spi master mode error flag */
+#define SPI_I2S_ROERR_FLAG 0x0040 /*!< spi or i2s receiver overflow error flag */
+#define SPI_I2S_BF_FLAG 0x0080 /*!< spi or i2s busy flag */
+#define SPI_CSPAS_FLAG 0x0100 /*!< spi cs pulse abnormal setting fiag */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_I2S_interrupts_definition
+ * @brief spi i2s interrupt
+ * @{
+ */
+
+#define SPI_I2S_ERROR_INT 0x0020 /*!< error interrupt */
+#define SPI_I2S_RDBF_INT 0x0040 /*!< receive data buffer full interrupt */
+#define SPI_I2S_TDBE_INT 0x0080 /*!< transmit data buffer empty interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_exported_types
+ * @{
+ */
+
+/**
+ * @brief spi frame bit num type
+ */
+typedef enum
+{
+ SPI_FRAME_8BIT = 0x00, /*!< 8-bit data frame format */
+ SPI_FRAME_16BIT = 0x01 /*!< 16-bit data frame format */
+} spi_frame_bit_num_type;
+
+/**
+ * @brief spi master/slave mode type
+ */
+typedef enum
+{
+ SPI_MODE_SLAVE = 0x00, /*!< select as slave mode */
+ SPI_MODE_MASTER = 0x01 /*!< select as master mode */
+} spi_master_slave_mode_type;
+
+/**
+ * @brief spi clock polarity (clkpol) type
+ */
+typedef enum
+{
+ SPI_CLOCK_POLARITY_LOW = 0x00, /*!< sck keeps low at idle state */
+ SPI_CLOCK_POLARITY_HIGH = 0x01 /*!< sck keeps high at idle state */
+} spi_clock_polarity_type;
+
+/**
+ * @brief spi clock phase (clkpha) type
+ */
+typedef enum
+{
+ SPI_CLOCK_PHASE_1EDGE = 0x00, /*!< data capture start from the first clock edge */
+ SPI_CLOCK_PHASE_2EDGE = 0x01 /*!< data capture start from the second clock edge */
+} spi_clock_phase_type;
+
+/**
+ * @brief spi cs mode type
+ */
+typedef enum
+{
+ SPI_CS_HARDWARE_MODE = 0x00, /*!< cs is hardware mode */
+ SPI_CS_SOFTWARE_MODE = 0x01 /*!< cs is software mode */
+} spi_cs_mode_type;
+
+/**
+ * @brief spi master clock frequency division type
+ */
+typedef enum
+{
+ SPI_MCLK_DIV_2 = 0x00, /*!< master clock frequency division 2 */
+ SPI_MCLK_DIV_3 = 0x0A, /*!< master clock frequency division 3 */
+ SPI_MCLK_DIV_4 = 0x01, /*!< master clock frequency division 4 */
+ SPI_MCLK_DIV_8 = 0x02, /*!< master clock frequency division 8 */
+ SPI_MCLK_DIV_16 = 0x03, /*!< master clock frequency division 16 */
+ SPI_MCLK_DIV_32 = 0x04, /*!< master clock frequency division 32 */
+ SPI_MCLK_DIV_64 = 0x05, /*!< master clock frequency division 64 */
+ SPI_MCLK_DIV_128 = 0x06, /*!< master clock frequency division 128 */
+ SPI_MCLK_DIV_256 = 0x07, /*!< master clock frequency division 256 */
+ SPI_MCLK_DIV_512 = 0x08, /*!< master clock frequency division 512 */
+ SPI_MCLK_DIV_1024 = 0x09 /*!< master clock frequency division 1024 */
+} spi_mclk_freq_div_type;
+
+/**
+ * @brief spi transmit first bit (lsb/msb) type
+ */
+typedef enum
+{
+ SPI_FIRST_BIT_MSB = 0x00, /*!< the frame format is msb first */
+ SPI_FIRST_BIT_LSB = 0x01 /*!< the frame format is lsb first */
+} spi_first_bit_type;
+
+/**
+ * @brief spi transmission mode type
+ */
+typedef enum
+{
+ SPI_TRANSMIT_FULL_DUPLEX = 0x00, /*!< dual line unidirectional full-duplex mode(slben = 0 and ora = 0) */
+ SPI_TRANSMIT_SIMPLEX_RX = 0x01, /*!< dual line unidirectional simplex receive-only mode(slben = 0 and ora = 1) */
+ SPI_TRANSMIT_HALF_DUPLEX_RX = 0x02, /*!< single line bidirectional half duplex mode-receiving(slben = 1 and slbtd = 0) */
+ SPI_TRANSMIT_HALF_DUPLEX_TX = 0x03 /*!< single line bidirectional half duplex mode-transmitting(slben = 1 and slbtd = 1) */
+} spi_transmission_mode_type;
+
+/**
+ * @brief spi crc direction type
+ */
+typedef enum
+{
+ SPI_CRC_RX = 0x0014, /*!< crc direction is rx */
+ SPI_CRC_TX = 0x0018 /*!< crc direction is tx */
+} spi_crc_direction_type;
+
+/**
+ * @brief spi single line bidirectional direction type
+ */
+typedef enum
+{
+ SPI_HALF_DUPLEX_DIRECTION_RX = 0x00, /*!< single line bidirectional half duplex mode direction: receive(slbtd = 0) */
+ SPI_HALF_DUPLEX_DIRECTION_TX = 0x01 /*!< single line bidirectional half duplex mode direction: transmit(slbtd = 1) */
+} spi_half_duplex_direction_type;
+
+/**
+ * @brief spi software cs internal level type
+ */
+typedef enum
+{
+ SPI_SWCS_INTERNAL_LEVEL_LOW = 0x00, /*!< internal level low */
+ SPI_SWCS_INTERNAL_LEVEL_HIGHT = 0x01 /*!< internal level high */
+} spi_software_cs_level_type;
+
+/**
+ * @brief i2s audio protocol type
+ */
+typedef enum
+{
+ I2S_AUDIO_PROTOCOL_PHILLIPS = 0x00, /*!< i2s philip standard */
+ I2S_AUDIO_PROTOCOL_MSB = 0x01, /*!< msb-justified standard */
+ I2S_AUDIO_PROTOCOL_LSB = 0x02, /*!< lsb-justified standard */
+ I2S_AUDIO_PROTOCOL_PCM_SHORT = 0x03, /*!< pcm standard-short frame */
+ I2S_AUDIO_PROTOCOL_PCM_LONG = 0x04 /*!< pcm standard-long frame */
+} i2s_audio_protocol_type;
+
+/**
+ * @brief i2s audio frequency type
+ */
+typedef enum
+{
+ I2S_AUDIO_FREQUENCY_DEFAULT = 2, /*!< i2s audio sampling frequency default */
+ I2S_AUDIO_FREQUENCY_8K = 8000, /*!< i2s audio sampling frequency 8k */
+ I2S_AUDIO_FREQUENCY_11_025K = 11025, /*!< i2s audio sampling frequency 11.025k */
+ I2S_AUDIO_FREQUENCY_16K = 16000, /*!< i2s audio sampling frequency 16k */
+ I2S_AUDIO_FREQUENCY_22_05K = 22050, /*!< i2s audio sampling frequency 22.05k */
+ I2S_AUDIO_FREQUENCY_32K = 32000, /*!< i2s audio sampling frequency 32k */
+ I2S_AUDIO_FREQUENCY_44_1K = 44100, /*!< i2s audio sampling frequency 44.1k */
+ I2S_AUDIO_FREQUENCY_48K = 48000, /*!< i2s audio sampling frequency 48k */
+ I2S_AUDIO_FREQUENCY_96K = 96000, /*!< i2s audio sampling frequency 96k */
+ I2S_AUDIO_FREQUENCY_192K = 192000 /*!< i2s audio sampling frequency 192k */
+} i2s_audio_sampling_freq_type;
+
+/**
+ * @brief i2s data bit num and channel bit num type
+ */
+typedef enum
+{
+ I2S_DATA_16BIT_CHANNEL_16BIT = 0x01, /*!< 16-bit data packed in 16-bit channel frame */
+ I2S_DATA_16BIT_CHANNEL_32BIT = 0x02, /*!< 16-bit data packed in 32-bit channel frame */
+ I2S_DATA_24BIT_CHANNEL_32BIT = 0x03, /*!< 24-bit data packed in 32-bit channel frame */
+ I2S_DATA_32BIT_CHANNEL_32BIT = 0x04 /*!< 32-bit data packed in 32-bit channel frame */
+} i2s_data_channel_format_type;
+
+/**
+ * @brief i2s operation mode type
+ */
+typedef enum
+{
+ I2S_MODE_SLAVE_TX = 0x00, /*!< slave transmission mode */
+ I2S_MODE_SLAVE_RX = 0x01, /*!< slave reception mode */
+ I2S_MODE_MASTER_TX = 0x02, /*!< master transmission mode */
+ I2S_MODE_MASTER_RX = 0x03 /*!< master reception mode */
+} i2s_operation_mode_type;
+
+/**
+ * @brief i2s clock polarity type
+ */
+typedef enum
+{
+ I2S_CLOCK_POLARITY_LOW = 0x00, /*!< i2s clock steady state is low level */
+ I2S_CLOCK_POLARITY_HIGH = 0x01 /*!< i2s clock steady state is high level */
+} i2s_clock_polarity_type;
+
+/**
+ * @brief spi init type
+ */
+typedef struct
+{
+ spi_transmission_mode_type transmission_mode; /*!< transmission mode selection */
+ spi_master_slave_mode_type master_slave_mode; /*!< master or slave mode selection */
+ spi_mclk_freq_div_type mclk_freq_division; /*!< master clock frequency division selection */
+ spi_first_bit_type first_bit_transmission;/*!< transmit lsb or msb selection */
+ spi_frame_bit_num_type frame_bit_num; /*!< frame bit num 8 or 16 bit selection */
+ spi_clock_polarity_type clock_polarity; /*!< clock polarity selection */
+ spi_clock_phase_type clock_phase; /*!< clock phase selection */
+ spi_cs_mode_type cs_mode_selection; /*!< hardware or software cs mode selection */
+} spi_init_type;
+
+/**
+ * @brief i2s init type
+ */
+typedef struct
+{
+ i2s_operation_mode_type operation_mode; /*!< operation mode selection */
+ i2s_audio_protocol_type audio_protocol; /*!< audio protocol selection */
+ i2s_audio_sampling_freq_type audio_sampling_freq; /*!< audio frequency selection */
+ i2s_data_channel_format_type data_channel_format; /*!< data bit num and channel bit num selection */
+ i2s_clock_polarity_type clock_polarity; /*!< clock polarity selection */
+ confirm_state mclk_output_enable; /*!< mclk_output selection */
+} i2s_init_type;
+
+/**
+ * @brief type define spi register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief spi ctrl1 register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t clkpha : 1; /* [0] */
+ __IO uint32_t clkpol : 1; /* [1] */
+ __IO uint32_t msten : 1; /* [2] */
+ __IO uint32_t mdiv_l : 3; /* [5:3] */
+ __IO uint32_t spien : 1; /* [6] */
+ __IO uint32_t ltf : 1; /* [7] */
+ __IO uint32_t swcsil : 1; /* [8] */
+ __IO uint32_t swcsen : 1; /* [9] */
+ __IO uint32_t ora : 1; /* [10] */
+ __IO uint32_t fbn : 1; /* [11] */
+ __IO uint32_t ntc : 1; /* [12] */
+ __IO uint32_t ccen : 1; /* [13] */
+ __IO uint32_t slbtd : 1; /* [14] */
+ __IO uint32_t slben : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief spi ctrl2 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t dmaren : 1; /* [0] */
+ __IO uint32_t dmaten : 1; /* [1] */
+ __IO uint32_t hwcsoe : 1; /* [2] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t tien : 1; /* [4] */
+ __IO uint32_t errie : 1; /* [5] */
+ __IO uint32_t rdbfie : 1; /* [6] */
+ __IO uint32_t tdbeie : 1; /* [7] */
+ __IO uint32_t mdiv_h : 1; /* [8] */
+ __IO uint32_t mdiv3en : 1; /* [9] */
+ __IO uint32_t reserved2 : 22;/* [31:10] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief spi sts register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t rdbf : 1; /* [0] */
+ __IO uint32_t tdbe : 1; /* [1] */
+ __IO uint32_t acs : 1; /* [2] */
+ __IO uint32_t tuerr : 1; /* [3] */
+ __IO uint32_t ccerr : 1; /* [4] */
+ __IO uint32_t mmerr : 1; /* [5] */
+ __IO uint32_t roerr : 1; /* [6] */
+ __IO uint32_t bf : 1; /* [7] */
+ __IO uint32_t cspas : 1; /* [8] */
+ __IO uint32_t reserved1 : 23;/* [31:9] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief spi dt register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t dt;
+ struct
+ {
+ __IO uint32_t dt : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } dt_bit;
+ };
+
+ /**
+ * @brief spi cpoly register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t cpoly;
+ struct
+ {
+ __IO uint32_t cpoly : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cpoly_bit;
+ };
+
+ /**
+ * @brief spi rcrc register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t rcrc;
+ struct
+ {
+ __IO uint32_t rcrc : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } rcrc_bit;
+ };
+
+ /**
+ * @brief spi tcrc register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t tcrc;
+ struct
+ {
+ __IO uint32_t tcrc : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } tcrc_bit;
+ };
+
+ /**
+ * @brief spi i2sctrl register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t i2sctrl;
+ struct
+ {
+ __IO uint32_t i2scbn : 1; /* [0] */
+ __IO uint32_t i2sdbn : 2; /* [2:1] */
+ __IO uint32_t i2sclkpol : 1; /* [3] */
+ __IO uint32_t stdsel : 2; /* [5:4] */
+ __IO uint32_t reserved1 : 1; /* [6] */
+ __IO uint32_t pcmfssel : 1; /* [7] */
+ __IO uint32_t opersel : 2; /* [9:8] */
+ __IO uint32_t i2sen : 1; /* [10] */
+ __IO uint32_t i2smsel : 1; /* [11] */
+ __IO uint32_t reserved2 : 20;/* [31:12] */
+ } i2sctrl_bit;
+ };
+
+ /**
+ * @brief spi i2sclk register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t i2sclk;
+ struct
+ {
+ __IO uint32_t i2sdiv_l : 8; /* [7:0] */
+ __IO uint32_t i2sodd : 1; /* [8] */
+ __IO uint32_t i2smclkoe : 1; /* [9] */
+ __IO uint32_t i2sdiv_h : 2; /* [11:10] */
+ __IO uint32_t reserved1 : 20;/* [31:12] */
+ } i2sclk_bit;
+ };
+
+} spi_type;
+
+/**
+ * @}
+ */
+
+#define SPI1 ((spi_type *) SPI1_BASE)
+#define SPI2 ((spi_type *) SPI2_BASE)
+#define SPI3 ((spi_type *) SPI3_BASE)
+#define SPI4 ((spi_type *) SPI4_BASE)
+#define I2S2EXT ((spi_type *) I2S2EXT_BASE)
+#define I2S3EXT ((spi_type *) I2S3EXT_BASE)
+
+/** @defgroup SPI_exported_functions
+ * @{
+ */
+
+void spi_i2s_reset(spi_type *spi_x);
+void spi_default_para_init(spi_init_type* spi_init_struct);
+void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct);
+void spi_ti_mode_enable(spi_type* spi_x, confirm_state new_state);
+void spi_crc_next_transmit(spi_type* spi_x);
+void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly);
+uint16_t spi_crc_polynomial_get(spi_type* spi_x);
+void spi_crc_enable(spi_type* spi_x, confirm_state new_state);
+uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction);
+void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state);
+void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level);
+void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num);
+void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction);
+void spi_enable(spi_type* spi_x, confirm_state new_state);
+void i2s_default_para_init(i2s_init_type* i2s_init_struct);
+void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct);
+void i2s_enable(spi_type* spi_x, confirm_state new_state);
+void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state);
+void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state);
+void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state);
+void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data);
+uint16_t spi_i2s_data_receive(spi_type* spi_x);
+flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
+void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_tmr.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_tmr.h
new file mode 100644
index 0000000..4e5e86b
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_tmr.h
@@ -0,0 +1,1017 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_tmr.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 tmr header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_TMR_H
+#define __AT32F435_437_TMR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup TMR
+ * @{
+ */
+
+/** @defgroup TMR_flags_definition
+ * @brief tmr flag
+ * @{
+ */
+
+#define TMR_OVF_FLAG ((uint32_t)0x000001) /*!< tmr flag overflow */
+#define TMR_C1_FLAG ((uint32_t)0x000002) /*!< tmr flag channel 1 */
+#define TMR_C2_FLAG ((uint32_t)0x000004) /*!< tmr flag channel 2 */
+#define TMR_C3_FLAG ((uint32_t)0x000008) /*!< tmr flag channel 3 */
+#define TMR_C4_FLAG ((uint32_t)0x000010) /*!< tmr flag channel 4 */
+#define TMR_HALL_FLAG ((uint32_t)0x000020) /*!< tmr flag hall */
+#define TMR_TRIGGER_FLAG ((uint32_t)0x000040) /*!< tmr flag trigger */
+#define TMR_BRK_FLAG ((uint32_t)0x000080) /*!< tmr flag brake */
+#define TMR_C1_RECAPTURE_FLAG ((uint32_t)0x000200) /*!< tmr flag channel 1 recapture */
+#define TMR_C2_RECAPTURE_FLAG ((uint32_t)0x000400) /*!< tmr flag channel 2 recapture */
+#define TMR_C3_RECAPTURE_FLAG ((uint32_t)0x000800) /*!< tmr flag channel 3 recapture */
+#define TMR_C4_RECAPTURE_FLAG ((uint32_t)0x001000) /*!< tmr flag channel 4 recapture */
+
+/**
+ * @}
+ */
+
+/** @defgroup TMR_interrupt_select_type_definition
+ * @brief tmr interrupt select type
+ * @{
+ */
+
+#define TMR_OVF_INT ((uint32_t)0x000001) /*!< tmr interrupt overflow */
+#define TMR_C1_INT ((uint32_t)0x000002) /*!< tmr interrupt channel 1 */
+#define TMR_C2_INT ((uint32_t)0x000004) /*!< tmr interrupt channel 2 */
+#define TMR_C3_INT ((uint32_t)0x000008) /*!< tmr interrupt channel 3 */
+#define TMR_C4_INT ((uint32_t)0x000010) /*!< tmr interrupt channel 4 */
+#define TMR_HALL_INT ((uint32_t)0x000020) /*!< tmr interrupt hall */
+#define TMR_TRIGGER_INT ((uint32_t)0x000040) /*!< tmr interrupt trigger */
+#define TMR_BRK_INT ((uint32_t)0x000080) /*!< tmr interrupt brake */
+
+/**
+ * @}
+ */
+
+/** @defgroup TMR_exported_types
+ * @{
+ */
+
+/**
+ * @brief tmr clock division type
+ */
+typedef enum
+{
+ TMR_CLOCK_DIV1 = 0x00, /*!< tmr clock division 1 */
+ TMR_CLOCK_DIV2 = 0x01, /*!< tmr clock division 2 */
+ TMR_CLOCK_DIV4 = 0x02 /*!< tmr clock division 4 */
+} tmr_clock_division_type;
+
+/**
+ * @brief tmr counter mode type
+ */
+typedef enum
+{
+ TMR_COUNT_UP = 0x00, /*!< tmr counter mode up */
+ TMR_COUNT_DOWN = 0x01, /*!< tmr counter mode down */
+ TMR_COUNT_TWO_WAY_1 = 0x02, /*!< tmr counter mode two way 1 */
+ TMR_COUNT_TWO_WAY_2 = 0x04, /*!< tmr counter mode two way 2 */
+ TMR_COUNT_TWO_WAY_3 = 0x06 /*!< tmr counter mode two way 3 */
+} tmr_count_mode_type;
+
+/**
+ * @brief tmr primary mode select type
+ */
+typedef enum
+{
+ TMR_PRIMARY_SEL_RESET = 0x00, /*!< tmr primary mode select reset */
+ TMR_PRIMARY_SEL_ENABLE = 0x01, /*!< tmr primary mode select enable */
+ TMR_PRIMARY_SEL_OVERFLOW = 0x02, /*!< tmr primary mode select overflow */
+ TMR_PRIMARY_SEL_COMPARE = 0x03, /*!< tmr primary mode select compare */
+ TMR_PRIMARY_SEL_C1ORAW = 0x04, /*!< tmr primary mode select c1oraw */
+ TMR_PRIMARY_SEL_C2ORAW = 0x05, /*!< tmr primary mode select c2oraw */
+ TMR_PRIMARY_SEL_C3ORAW = 0x06, /*!< tmr primary mode select c3oraw */
+ TMR_PRIMARY_SEL_C4ORAW = 0x07 /*!< tmr primary mode select c4oraw */
+} tmr_primary_select_type;
+
+/**
+ * @brief tmr subordinate mode input select type
+ */
+typedef enum
+{
+ TMR_SUB_INPUT_SEL_IS0 = 0x00, /*!< subordinate mode input select is0 */
+ TMR_SUB_INPUT_SEL_IS1 = 0x01, /*!< subordinate mode input select is1 */
+ TMR_SUB_INPUT_SEL_IS2 = 0x02, /*!< subordinate mode input select is2 */
+ TMR_SUB_INPUT_SEL_IS3 = 0x03, /*!< subordinate mode input select is3 */
+ TMR_SUB_INPUT_SEL_C1INC = 0x04, /*!< subordinate mode input select c1inc */
+ TMR_SUB_INPUT_SEL_C1DF1 = 0x05, /*!< subordinate mode input select c1df1 */
+ TMR_SUB_INPUT_SEL_C2DF2 = 0x06, /*!< subordinate mode input select c2df2 */
+ TMR_SUB_INPUT_SEL_EXTIN = 0x07 /*!< subordinate mode input select extin */
+} sub_tmr_input_sel_type;
+
+/**
+ * @brief tmr subordinate mode select type
+ */
+typedef enum
+{
+ TMR_SUB_MODE_DIABLE = 0x00, /*!< subordinate mode disable */
+ TMR_SUB_ENCODER_MODE_A = 0x01, /*!< subordinate mode select encoder mode a */
+ TMR_SUB_ENCODER_MODE_B = 0x02, /*!< subordinate mode select encoder mode b */
+ TMR_SUB_ENCODER_MODE_C = 0x03, /*!< subordinate mode select encoder mode c */
+ TMR_SUB_RESET_MODE = 0x04, /*!< subordinate mode select reset */
+ TMR_SUB_HANG_MODE = 0x05, /*!< subordinate mode select hang */
+ TMR_SUB_TRIGGER_MODE = 0x06, /*!< subordinate mode select trigger */
+ TMR_SUB_EXTERNAL_CLOCK_MODE_A = 0x07 /*!< subordinate mode external clock mode a */
+} tmr_sub_mode_select_type;
+
+/**
+ * @brief tmr encoder mode type
+ */
+typedef enum
+{
+ TMR_ENCODER_MODE_A = TMR_SUB_ENCODER_MODE_A, /*!< tmr encoder mode a */
+ TMR_ENCODER_MODE_B = TMR_SUB_ENCODER_MODE_B, /*!< tmr encoder mode b */
+ TMR_ENCODER_MODE_C = TMR_SUB_ENCODER_MODE_C /*!< tmr encoder mode c */
+} tmr_encoder_mode_type;
+
+/**
+ * @brief tmr output control mode type
+ */
+typedef enum
+{
+ TMR_OUTPUT_CONTROL_OFF = 0x00, /*!< tmr output control mode off */
+ TMR_OUTPUT_CONTROL_HIGH = 0x01, /*!< tmr output control mode high */
+ TMR_OUTPUT_CONTROL_LOW = 0x02, /*!< tmr output control mode low */
+ TMR_OUTPUT_CONTROL_SWITCH = 0x03, /*!< tmr output control mode switch */
+ TMR_OUTPUT_CONTROL_FORCE_HIGH = 0x04, /*!< tmr output control mode force high */
+ TMR_OUTPUT_CONTROL_FORCE_LOW = 0x05, /*!< tmr output control mode force low */
+ TMR_OUTPUT_CONTROL_PWM_MODE_A = 0x06, /*!< tmr output control mode pwm a */
+ TMR_OUTPUT_CONTROL_PWM_MODE_B = 0x07 /*!< tmr output control mode pwm b */
+} tmr_output_control_mode_type;
+
+/**
+ * @brief tmr force output type
+ */
+typedef enum
+{
+ TMR_FORCE_OUTPUT_HIGH = TMR_OUTPUT_CONTROL_FORCE_HIGH, /*!< tmr force output high */
+ TMR_FORCE_OUTPUT_LOW = TMR_OUTPUT_CONTROL_FORCE_LOW /*!< tmr force output low */
+} tmr_force_output_type;
+
+/**
+ * @brief tmr output channel polarity type
+ */
+typedef enum
+{
+ TMR_OUTPUT_ACTIVE_HIGH = 0x00, /*!< tmr output channel polarity high */
+ TMR_OUTPUT_ACTIVE_LOW = 0x01 /*!< tmr output channel polarity low */
+} tmr_output_polarity_type;
+
+/**
+ * @brief tmr input channel polarity type
+ */
+typedef enum
+{
+ TMR_INPUT_RISING_EDGE = 0x00, /*!< tmr input channel polarity rising */
+ TMR_INPUT_FALLING_EDGE = 0x01, /*!< tmr input channel polarity falling */
+ TMR_INPUT_BOTH_EDGE = 0x03 /*!< tmr input channel polarity both edge */
+} tmr_input_polarity_type;
+
+/**
+ * @brief tmr channel select type
+ */
+typedef enum
+{
+ TMR_SELECT_CHANNEL_1 = 0x00, /*!< tmr channel select channel 1 */
+ TMR_SELECT_CHANNEL_1C = 0x01, /*!< tmr channel select channel 1 complementary */
+ TMR_SELECT_CHANNEL_2 = 0x02, /*!< tmr channel select channel 2 */
+ TMR_SELECT_CHANNEL_2C = 0x03, /*!< tmr channel select channel 2 complementary */
+ TMR_SELECT_CHANNEL_3 = 0x04, /*!< tmr channel select channel 3 */
+ TMR_SELECT_CHANNEL_3C = 0x05, /*!< tmr channel select channel 3 complementary */
+ TMR_SELECT_CHANNEL_4 = 0x06, /*!< tmr channel select channel 4 */
+ TMR_SELECT_CHANNEL_5 = 0x07 /*!< tmr channel select channel 5 */
+} tmr_channel_select_type;
+
+/**
+ * @brief tmr channel1 input connected type
+ */
+typedef enum
+{
+ TMR_CHANEL1_CONNECTED_C1IRAW = 0x00, /*!< channel1 pins is only connected to C1IRAW input */
+ TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR = 0x01 /*!< channel1/2/3 pins are connected to C1IRAW input after xored */
+} tmr_channel1_input_connected_type;
+
+/**
+ * @brief tmr input channel mapped type channel direction
+ */
+typedef enum
+{
+ TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */
+ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */
+ TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */
+} tmr_input_direction_mapped_type;
+
+/**
+ * @brief tmr input divider type
+ */
+typedef enum
+{
+ TMR_CHANNEL_INPUT_DIV_1 = 0x00, /*!< tmr channel input divider 1 */
+ TMR_CHANNEL_INPUT_DIV_2 = 0x01, /*!< tmr channel input divider 2 */
+ TMR_CHANNEL_INPUT_DIV_4 = 0x02, /*!< tmr channel input divider 4 */
+ TMR_CHANNEL_INPUT_DIV_8 = 0x03 /*!< tmr channel input divider 8 */
+} tmr_channel_input_divider_type;
+
+/**
+ * @brief tmr dma request source select type
+ */
+typedef enum
+{
+ TMR_DMA_REQUEST_BY_CHANNEL = 0x00, /*!< tmr dma request source select channel */
+ TMR_DMA_REQUEST_BY_OVERFLOW = 0x01 /*!< tmr dma request source select overflow */
+} tmr_dma_request_source_type;
+
+/**
+ * @brief tmr dma request type
+ */
+typedef enum
+{
+ TMR_OVERFLOW_DMA_REQUEST = 0x00000100, /*!< tmr dma request select overflow */
+ TMR_C1_DMA_REQUEST = 0x00000200, /*!< tmr dma request select channel 1 */
+ TMR_C2_DMA_REQUEST = 0x00000400, /*!< tmr dma request select channel 2 */
+ TMR_C3_DMA_REQUEST = 0x00000800, /*!< tmr dma request select channel 3 */
+ TMR_C4_DMA_REQUEST = 0x00001000, /*!< tmr dma request select channel 4 */
+ TMR_HALL_DMA_REQUEST = 0x00002000, /*!< tmr dma request select hall */
+ TMR_TRIGGER_DMA_REQUEST = 0x00004000 /*!< tmr dma request select trigger */
+} tmr_dma_request_type;
+
+/**
+ * @brief tmr event triggered by software type
+ */
+typedef enum
+{
+ TMR_OVERFLOW_SWTRIG = 0x00000001, /*!< tmr event triggered by software of overflow */
+ TMR_C1_SWTRIG = 0x00000002, /*!< tmr event triggered by software of channel 1 */
+ TMR_C2_SWTRIG = 0x00000004, /*!< tmr event triggered by software of channel 2 */
+ TMR_C3_SWTRIG = 0x00000008, /*!< tmr event triggered by software of channel 3 */
+ TMR_C4_SWTRIG = 0x00000010, /*!< tmr event triggered by software of channel 4 */
+ TMR_HALL_SWTRIG = 0x00000020, /*!< tmr event triggered by software of hall */
+ TMR_TRIGGER_SWTRIG = 0x00000040, /*!< tmr event triggered by software of trigger */
+ TMR_BRK_SWTRIG = 0x00000080 /*!< tmr event triggered by software of brake */
+}tmr_event_trigger_type;
+
+/**
+ * @brief tmr channel output fast type
+ */
+typedef enum
+{
+ TMR_CHANNEL1_OUTPUT_FAST = MAKE_VALUE(0x18, 2), /*!< tmr channel 1 output fast mode */
+ TMR_CHANNEL2_OUTPUT_FAST = MAKE_VALUE(0x18, 10), /*!< tmr channel 2 output fast mode */
+ TMR_CHANNEL3_OUTPUT_FAST = MAKE_VALUE(0x1c, 2), /*!< tmr channel 3 output fast mode */
+ TMR_CHANNEL4_OUTPUT_FAST = MAKE_VALUE(0x1c, 10) /*!< tmr channel 4 output fast mode */
+}tmr_channel_output_fast_type;
+
+/**
+ * @brief tmr polarity active type
+ */
+typedef enum
+{
+ TMR_POLARITY_ACTIVE_HIGH = 0x00, /*!< tmr polarity active high */
+ TMR_POLARITY_ACTIVE_LOW = 0x01, /*!< tmr polarity active low */
+ TMR_POLARITY_ACTIVE_BOTH = 0x02 /*!< tmr polarity active both high ande low */
+}tmr_polarity_active_type;
+
+/**
+ * @brief tmr external signal divider type
+ */
+typedef enum
+{
+ TMR_ES_FREQUENCY_DIV_1 = 0x00, /*!< tmr external signal frequency divider 1 */
+ TMR_ES_FREQUENCY_DIV_2 = 0x01, /*!< tmr external signal frequency divider 2 */
+ TMR_ES_FREQUENCY_DIV_4 = 0x02, /*!< tmr external signal frequency divider 4 */
+ TMR_ES_FREQUENCY_DIV_8 = 0x03 /*!< tmr external signal frequency divider 8 */
+}tmr_external_signal_divider_type;
+
+/**
+ * @brief tmr external signal polarity type
+ */
+typedef enum
+{
+ TMR_ES_POLARITY_NON_INVERTED = 0x00, /*!< tmr external signal polarity non-inerted */
+ TMR_ES_POLARITY_INVERTED = 0x01 /*!< tmr external signal polarity inerted */
+}tmr_external_signal_polarity_type;
+
+/**
+ * @brief tmr dma transfer length type
+ */
+typedef enum
+{
+ TMR_DMA_TRANSFER_1BYTE = 0x00, /*!< tmr dma transfer length 1 byte */
+ TMR_DMA_TRANSFER_2BYTES = 0x01, /*!< tmr dma transfer length 2 bytes */
+ TMR_DMA_TRANSFER_3BYTES = 0x02, /*!< tmr dma transfer length 3 bytes */
+ TMR_DMA_TRANSFER_4BYTES = 0x03, /*!< tmr dma transfer length 4 bytes */
+ TMR_DMA_TRANSFER_5BYTES = 0x04, /*!< tmr dma transfer length 5 bytes */
+ TMR_DMA_TRANSFER_6BYTES = 0x05, /*!< tmr dma transfer length 6 bytes */
+ TMR_DMA_TRANSFER_7BYTES = 0x06, /*!< tmr dma transfer length 7 bytes */
+ TMR_DMA_TRANSFER_8BYTES = 0x07, /*!< tmr dma transfer length 8 bytes */
+ TMR_DMA_TRANSFER_9BYTES = 0x08, /*!< tmr dma transfer length 9 bytes */
+ TMR_DMA_TRANSFER_10BYTES = 0x09, /*!< tmr dma transfer length 10 bytes */
+ TMR_DMA_TRANSFER_11BYTES = 0x0A, /*!< tmr dma transfer length 11 bytes */
+ TMR_DMA_TRANSFER_12BYTES = 0x0B, /*!< tmr dma transfer length 12 bytes */
+ TMR_DMA_TRANSFER_13BYTES = 0x0C, /*!< tmr dma transfer length 13 bytes */
+ TMR_DMA_TRANSFER_14BYTES = 0x0D, /*!< tmr dma transfer length 14 bytes */
+ TMR_DMA_TRANSFER_15BYTES = 0x0E, /*!< tmr dma transfer length 15 bytes */
+ TMR_DMA_TRANSFER_16BYTES = 0x0F, /*!< tmr dma transfer length 16 bytes */
+ TMR_DMA_TRANSFER_17BYTES = 0x10, /*!< tmr dma transfer length 17 bytes */
+ TMR_DMA_TRANSFER_18BYTES = 0x11 /*!< tmr dma transfer length 18 bytes */
+}tmr_dma_transfer_length_type;
+
+/**
+ * @brief tmr dma base address type
+ */
+typedef enum
+{
+ TMR_CTRL1_ADDRESS = 0x0000, /*!< tmr dma base address ctrl1 */
+ TMR_CTRL2_ADDRESS = 0x0001, /*!< tmr dma base address ctrl2 */
+ TMR_STCTRL_ADDRESS = 0x0002, /*!< tmr dma base address stctrl */
+ TMR_IDEN_ADDRESS = 0x0003, /*!< tmr dma base address iden */
+ TMR_ISTS_ADDRESS = 0x0004, /*!< tmr dma base address ists */
+ TMR_SWEVT_ADDRESS = 0x0005, /*!< tmr dma base address swevt */
+ TMR_CM1_ADDRESS = 0x0006, /*!< tmr dma base address cm1 */
+ TMR_CM2_ADDRESS = 0x0007, /*!< tmr dma base address cm2 */
+ TMR_CCTRL_ADDRESS = 0x0008, /*!< tmr dma base address cctrl */
+ TMR_CVAL_ADDRESS = 0x0009, /*!< tmr dma base address cval */
+ TMR_DIV_ADDRESS = 0x000A, /*!< tmr dma base address div */
+ TMR_PR_ADDRESS = 0x000B, /*!< tmr dma base address pr */
+ TMR_RPR_ADDRESS = 0x000C, /*!< tmr dma base address rpr */
+ TMR_C1DT_ADDRESS = 0x000D, /*!< tmr dma base address c1dt */
+ TMR_C2DT_ADDRESS = 0x000E, /*!< tmr dma base address c2dt */
+ TMR_C3DT_ADDRESS = 0x000F, /*!< tmr dma base address c3dt */
+ TMR_C4DT_ADDRESS = 0x0010, /*!< tmr dma base address c4dt */
+ TMR_BRK_ADDRESS = 0x0011, /*!< tmr dma base address brake */
+ TMR_DMACTRL_ADDRESS = 0x0012 /*!< tmr dma base address dmactrl */
+}tmr_dma_address_type;
+
+/**
+ * @brief tmr brk polarity type
+ */
+typedef enum
+{
+ TMR_BRK_INPUT_ACTIVE_LOW = 0x00, /*!< tmr brk input channel active low */
+ TMR_BRK_INPUT_ACTIVE_HIGH = 0x01 /*!< tmr brk input channel active high */
+}tmr_brk_polarity_type;
+
+/**
+ * @brief tmr write protect level type
+ */
+typedef enum
+{
+ TMR_WP_OFF = 0x00, /*!< tmr write protect off */
+ TMR_WP_LEVEL_3 = 0x01, /*!< tmr write protect level 3 */
+ TMR_WP_LEVEL_2 = 0x02, /*!< tmr write protect level 2 */
+ TMR_WP_LEVEL_1 = 0x03 /*!< tmr write protect level 1 */
+}tmr_wp_level_type;
+
+/**
+ * @brief tmr input remap type
+ */
+typedef enum
+{
+ TMR2_TMR8TRGOUT_TMR5_GPIO = 0x00, /*!< tmr2 input remap to tmr8_trgout or tmr5 remap to gpio */
+ TMR2_PTP_TMR5_LICK = 0x01, /*!< tmr2 input remap to ptp or tmr5 remap to lick */
+ TMR2_OTG1FS_TMR5_LEXT = 0x02, /*!< tmr2 input remap to otg1fs or tmr5 remap to lext */
+ TMR2_OTG2FS_TMR5_ERTC = 0x03 /*!< tmr2 input remap to otg2fs or tmr5 remap to ertc */
+}tmr_input_remap_type ;
+/**
+
+ * @brief tmr output config type
+ */
+typedef struct
+{
+ tmr_output_control_mode_type oc_mode; /*!< output channel mode */
+ confirm_state oc_idle_state; /*!< output channel idle state */
+ confirm_state occ_idle_state; /*!< output channel complementary idle state */
+ tmr_output_polarity_type oc_polarity; /*!< output channel polarity */
+ tmr_output_polarity_type occ_polarity; /*!< output channel complementary polarity */
+ confirm_state oc_output_state; /*!< output channel enable */
+ confirm_state occ_output_state; /*!< output channel complementary enable */
+} tmr_output_config_type;
+
+/**
+ * @brief tmr input capture config type
+ */
+typedef struct
+{
+ tmr_channel_select_type input_channel_select; /*!< tmr input channel select */
+ tmr_input_polarity_type input_polarity_select; /*!< tmr input polarity select */
+ tmr_input_direction_mapped_type input_mapped_select; /*!< tmr channel mapped direct or indirect */
+ uint8_t input_filter_value; /*!< tmr channel filter value */
+} tmr_input_config_type;
+
+/**
+ * @brief tmr brkdt config type
+ */
+typedef struct
+{
+ uint8_t deadtime; /*!< dead-time generator setup */
+ tmr_brk_polarity_type brk_polarity; /*!< tmr brake polarity */
+ tmr_wp_level_type wp_level; /*!< write protect configuration */
+ confirm_state auto_output_enable; /*!< automatic output enable */
+ confirm_state fcsoen_state; /*!< frozen channel status when output enable */
+ confirm_state fcsodis_state; /*!< frozen channel status when output disable */
+ confirm_state brk_enable; /*!< tmr brk enale */
+} tmr_brkdt_config_type;
+
+/**
+ * @brief type define tmr register all
+ */
+typedef struct
+{
+ /**
+ * @brief tmr ctrl1 register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t tmren : 1; /* [0] */
+ __IO uint32_t ovfen : 1; /* [1] */
+ __IO uint32_t ovfs : 1; /* [2] */
+ __IO uint32_t ocmen : 1; /* [3] */
+ __IO uint32_t cnt_dir : 3; /* [6:4] */
+ __IO uint32_t prben : 1; /* [7] */
+ __IO uint32_t clkdiv : 2; /* [9:8] */
+ __IO uint32_t pmen : 1; /* [10] */
+ __IO uint32_t reserved1 : 21;/* [31:11] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief tmr ctrl2 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t cbctrl : 1; /* [0] */
+ __IO uint32_t reserved1 : 1; /* [1] */
+ __IO uint32_t ccfs : 1; /* [2] */
+ __IO uint32_t drs : 1; /* [3] */
+ __IO uint32_t ptos : 3; /* [6:4] */
+ __IO uint32_t c1insel : 1; /* [7] */
+ __IO uint32_t c1ios : 1; /* [8] */
+ __IO uint32_t c1cios : 1; /* [9] */
+ __IO uint32_t c2ios : 1; /* [10] */
+ __IO uint32_t c2cios : 1; /* [11] */
+ __IO uint32_t c3ios : 1; /* [12] */
+ __IO uint32_t c3cios : 1; /* [13] */
+ __IO uint32_t c4ios : 1; /* [14] */
+ __IO uint32_t reserved2 : 16;/* [30:15] */
+ __IO uint32_t trgout2en : 1; /* [31] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief tmr smc register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t stctrl;
+ struct
+ {
+ __IO uint32_t smsel : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t stis : 3; /* [6:4] */
+ __IO uint32_t sts : 1; /* [7] */
+ __IO uint32_t esf : 4; /* [11:8] */
+ __IO uint32_t esdiv : 2; /* [13:12] */
+ __IO uint32_t ecmben : 1; /* [14] */
+ __IO uint32_t esp : 1; /* [15] */
+ __IO uint32_t reserved2 : 16;/* [31:16] */
+ } stctrl_bit;
+ };
+
+ /**
+ * @brief tmr die register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t iden;
+ struct
+ {
+ __IO uint32_t ovfien : 1; /* [0] */
+ __IO uint32_t c1ien : 1; /* [1] */
+ __IO uint32_t c2ien : 1; /* [2] */
+ __IO uint32_t c3ien : 1; /* [3] */
+ __IO uint32_t c4ien : 1; /* [4] */
+ __IO uint32_t hallien : 1; /* [5] */
+ __IO uint32_t tien : 1; /* [6] */
+ __IO uint32_t brkie : 1; /* [7] */
+ __IO uint32_t ovfden : 1; /* [8] */
+ __IO uint32_t c1den : 1; /* [9] */
+ __IO uint32_t c2den : 1; /* [10] */
+ __IO uint32_t c3den : 1; /* [11] */
+ __IO uint32_t c4den : 1; /* [12] */
+ __IO uint32_t hallde : 1; /* [13] */
+ __IO uint32_t tden : 1; /* [14] */
+ __IO uint32_t reserved1 : 17;/* [31:15] */
+ } iden_bit;
+ };
+
+ /**
+ * @brief tmr ists register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ists;
+ struct
+ {
+ __IO uint32_t ovfif : 1; /* [0] */
+ __IO uint32_t c1if : 1; /* [1] */
+ __IO uint32_t c2if : 1; /* [2] */
+ __IO uint32_t c3if : 1; /* [3] */
+ __IO uint32_t c4if : 1; /* [4] */
+ __IO uint32_t hallif : 1; /* [5] */
+ __IO uint32_t trgif : 1; /* [6] */
+ __IO uint32_t brkif : 1; /* [7] */
+ __IO uint32_t reserved1 : 1; /* [8] */
+ __IO uint32_t c1rf : 1; /* [9] */
+ __IO uint32_t c2rf : 1; /* [10] */
+ __IO uint32_t c3rf : 1; /* [11] */
+ __IO uint32_t c4rf : 1; /* [12] */
+ __IO uint32_t reserved2 : 19;/* [31:13] */
+ } ists_bit;
+ };
+
+ /**
+ * @brief tmr eveg register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t swevt;
+ struct
+ {
+ __IO uint32_t ovfswtr : 1; /* [0] */
+ __IO uint32_t c1swtr : 1; /* [1] */
+ __IO uint32_t c2swtr : 1; /* [2] */
+ __IO uint32_t c3swtr : 1; /* [3] */
+ __IO uint32_t c4swtr : 1; /* [4] */
+ __IO uint32_t hallswtr : 1; /* [5] */
+ __IO uint32_t trgswtr : 1; /* [6] */
+ __IO uint32_t brkswtr : 1; /* [7] */
+ __IO uint32_t reserved : 24;/* [31:8] */
+ } swevt_bit;
+ };
+
+ /**
+ * @brief tmr ccm1 register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t cm1;
+
+ /**
+ * @brief channel mode
+ */
+ struct
+ {
+ __IO uint32_t c1c : 2; /* [1:0] */
+ __IO uint32_t c1oien : 1; /* [2] */
+ __IO uint32_t c1oben : 1; /* [3] */
+ __IO uint32_t c1octrl : 3; /* [6:4] */
+ __IO uint32_t c1osen : 1; /* [7] */
+ __IO uint32_t c2c : 2; /* [9:8] */
+ __IO uint32_t c2oien : 1; /* [10] */
+ __IO uint32_t c2oben : 1; /* [11] */
+ __IO uint32_t c2octrl : 3; /* [14:12] */
+ __IO uint32_t c2osen : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cm1_output_bit;
+
+ /**
+ * @brief input capture mode
+ */
+ struct
+ {
+ __IO uint32_t c1c : 2; /* [1:0] */
+ __IO uint32_t c1idiv : 2; /* [3:2] */
+ __IO uint32_t c1df : 4; /* [7:4] */
+ __IO uint32_t c2c : 2; /* [9:8] */
+ __IO uint32_t c2idiv : 2; /* [11:10] */
+ __IO uint32_t c2df : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cm1_input_bit;
+ };
+
+ /**
+ * @brief tmr ccm2 register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t cm2;
+
+ /**
+ * @brief channel mode
+ */
+ struct
+ {
+ __IO uint32_t c3c : 2; /* [1:0] */
+ __IO uint32_t c3oien : 1; /* [2] */
+ __IO uint32_t c3oben : 1; /* [3] */
+ __IO uint32_t c3octrl : 3; /* [6:4] */
+ __IO uint32_t c3osen : 1; /* [7] */
+ __IO uint32_t c4c : 2; /* [9:8] */
+ __IO uint32_t c4oien : 1; /* [10] */
+ __IO uint32_t c4oben : 1; /* [11] */
+ __IO uint32_t c4octrl : 3; /* [14:12] */
+ __IO uint32_t c4osen : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cm2_output_bit;
+
+ /**
+ * @brief input capture mode
+ */
+ struct
+ {
+ __IO uint32_t c3c : 2; /* [1:0] */
+ __IO uint32_t c3idiv : 2; /* [3:2] */
+ __IO uint32_t c3df : 4; /* [7:4] */
+ __IO uint32_t c4c : 2; /* [9:8] */
+ __IO uint32_t c4idiv : 2; /* [11:10] */
+ __IO uint32_t c4df : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cm2_input_bit;
+ };
+
+ /**
+ * @brief tmr cce register, offset:0x20
+ */
+ union
+ {
+ uint32_t cctrl;
+ struct
+ {
+ __IO uint32_t c1en : 1; /* [0] */
+ __IO uint32_t c1p : 1; /* [1] */
+ __IO uint32_t c1cen : 1; /* [2] */
+ __IO uint32_t c1cp : 1; /* [3] */
+ __IO uint32_t c2en : 1; /* [4] */
+ __IO uint32_t c2p : 1; /* [5] */
+ __IO uint32_t c2cen : 1; /* [6] */
+ __IO uint32_t c2cp : 1; /* [7] */
+ __IO uint32_t c3en : 1; /* [8] */
+ __IO uint32_t c3p : 1; /* [9] */
+ __IO uint32_t c3cen : 1; /* [10] */
+ __IO uint32_t c3cp : 1; /* [11] */
+ __IO uint32_t c4en : 1; /* [12] */
+ __IO uint32_t c4p : 1; /* [13] */
+ __IO uint32_t reserved1 : 18;/* [31:14] */
+ } cctrl_bit;
+ };
+
+ /**
+ * @brief tmr cnt register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t cval;
+ struct
+ {
+ __IO uint32_t cval : 32;/* [31:0] */
+ } cval_bit;
+ };
+
+ /**
+ * @brief tmr div, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t div;
+ struct
+ {
+ __IO uint32_t div : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } div_bit;
+ };
+
+ /**
+ * @brief tmr pr register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t pr;
+ struct
+ {
+ __IO uint32_t pr : 32;/* [31:0] */
+ } pr_bit;
+ };
+
+ /**
+ * @brief tmr rpr register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t rpr;
+ struct
+ {
+ __IO uint32_t rpr : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } rpr_bit;
+ };
+
+ /**
+ * @brief tmr c1dt register, offset:0x34
+ */
+ union
+ {
+ uint32_t c1dt;
+ struct
+ {
+ __IO uint32_t c1dt : 32;/* [31:0] */
+ } c1dt_bit;
+ };
+
+ /**
+ * @brief tmr c2dt register, offset:0x38
+ */
+ union
+ {
+ uint32_t c2dt;
+ struct
+ {
+ __IO uint32_t c2dt : 32;/* [31:0] */
+ } c2dt_bit;
+ };
+
+ /**
+ * @brief tmr c3dt register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t c3dt;
+ struct
+ {
+ __IO uint32_t c3dt : 32;/* [31:0] */
+ } c3dt_bit;
+ };
+
+ /**
+ * @brief tmr c4dt register, offset:0x40
+ */
+ union
+ {
+ __IO uint32_t c4dt;
+ struct
+ {
+ __IO uint32_t c4dt : 32;/* [31:0] */
+ } c4dt_bit;
+ };
+
+ /**
+ * @brief tmr brk register, offset:0x44
+ */
+ union
+ {
+ __IO uint32_t brk;
+ struct
+ {
+ __IO uint32_t dtc : 8; /* [7:0] */
+ __IO uint32_t wpc : 2; /* [9:8] */
+ __IO uint32_t fcsodis : 1; /* [10] */
+ __IO uint32_t fcsoen : 1; /* [11] */
+ __IO uint32_t brken : 1; /* [12] */
+ __IO uint32_t brkv : 1; /* [13] */
+ __IO uint32_t aoen : 1; /* [14] */
+ __IO uint32_t oen : 1; /* [15] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } brk_bit;
+ };
+ /**
+ * @brief tmr dmactrl register, offset:0x48
+ */
+ union
+ {
+ __IO uint32_t dmactrl;
+ struct
+ {
+ __IO uint32_t addr : 5; /* [4:0] */
+ __IO uint32_t reserved1 : 3; /* [7:5] */
+ __IO uint32_t dtb : 5; /* [12:8] */
+ __IO uint32_t reserved2 : 19;/* [31:13] */
+ } dmactrl_bit;
+ };
+
+ /**
+ * @brief tmr dmadt register, offset:0x4C
+ */
+ union
+ {
+ __IO uint32_t dmadt;
+ struct
+ {
+ __IO uint32_t dmadt : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } dmadt_bit;
+ };
+
+ /**
+ * @brief tmr rmp register, offset:0x50
+ */
+ union
+ {
+ __IO uint32_t rmp;
+ struct
+ {
+ __IO uint32_t reserved1 : 6; /* [5:0] */
+ __IO uint32_t tmr5_ch4_irmp : 2; /* [7:6] */
+ __IO uint32_t reserved2 : 2; /* [9:8] */
+ __IO uint32_t tmr2_ch1_irmp : 2; /* [11:10] */
+ __IO uint32_t reserved3 : 20;/* [31:16] */
+ } rmp_bit;
+ };
+
+ /**
+ * @brief tmr reserved0 register, offset:0x54-0x6C
+ */
+ __IO uint32_t reserved1[7];
+
+ /**
+ * @brief tmr cm3 register, offset:0x70
+ */
+ union
+ {
+ __IO uint32_t cm3;
+ struct
+ {
+ __IO uint32_t reserved1 : 2; /* [1:0] */
+ __IO uint32_t c5oien : 1; /* [2] */
+ __IO uint32_t c5oben : 1; /* [3] */
+ __IO uint32_t c5octrl : 3; /* [6:4] */
+ __IO uint32_t c5osen : 1; /* [7] */
+ __IO uint32_t reserved2 : 24;/* [31:8] */
+ } cm3_output_bit;
+ };
+
+ /**
+ * @brief tmr c5dt register, offset:0x74
+ */
+ union
+ {
+ __IO uint32_t c5dt;
+ struct
+ {
+ __IO uint32_t c5dt : 32;/* [31:0] */
+ } c5dt_bit;
+ };
+} tmr_type;
+
+/**
+ * @}
+ */
+
+#define TMR1 ((tmr_type *) TMR1_BASE)
+#define TMR2 ((tmr_type *) TMR2_BASE)
+#define TMR3 ((tmr_type *) TMR3_BASE)
+#define TMR4 ((tmr_type *) TMR4_BASE)
+#define TMR5 ((tmr_type *) TMR5_BASE)
+#define TMR6 ((tmr_type *) TMR6_BASE)
+#define TMR7 ((tmr_type *) TMR7_BASE)
+#define TMR8 ((tmr_type *) TMR8_BASE)
+#define TMR9 ((tmr_type *) TMR9_BASE)
+#define TMR10 ((tmr_type *) TMR10_BASE)
+#define TMR11 ((tmr_type *) TMR11_BASE)
+#define TMR12 ((tmr_type *) TMR12_BASE)
+#define TMR13 ((tmr_type *) TMR13_BASE)
+#define TMR14 ((tmr_type *) TMR14_BASE)
+#define TMR20 ((tmr_type *) TMR20_BASE)
+
+/** @defgroup TMR_exported_functions
+ * @{
+ */
+
+void tmr_reset(tmr_type *tmr_x);
+void tmr_counter_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_output_default_para_init(tmr_output_config_type *tmr_output_struct);
+void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct);
+void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct);
+void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div);
+void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div);
+void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir);
+void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value);
+void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value);
+uint32_t tmr_counter_value_get(tmr_type *tmr_x);
+void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value);
+uint32_t tmr_div_value_get(tmr_type *tmr_x);
+void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_output_config_type *tmr_output_struct);
+void tmr_output_channel_mode_select(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_output_control_mode_type oc_mode);
+void tmr_period_value_set(tmr_type *tmr_x, uint32_t tmr_pr_value);
+uint32_t tmr_period_value_get(tmr_type *tmr_x);
+void tmr_channel_value_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ uint32_t tmr_channel_value);
+uint32_t tmr_channel_value_get(tmr_type *tmr_x, tmr_channel_select_type tmr_channel);
+void tmr_period_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ confirm_state new_state);
+void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ confirm_state new_state);
+void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ confirm_state new_state);
+void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_32_bit_function_enable (tmr_type *tmr_x, confirm_state new_state);
+void tmr_overflow_request_source_set(tmr_type *tmr_x, confirm_state new_state);
+void tmr_overflow_event_disable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
+ tmr_channel_input_divider_type divider_factor);
+void tmr_channel_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state);
+void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ uint16_t filter_value);
+void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
+ tmr_channel_input_divider_type divider_factor);
+void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect);
+void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_channel_input_divider_type divider_factor);
+void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode);
+void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode);
+void tmr_channel_dma_select(tmr_type *tmr_x, tmr_dma_request_source_type cc_dma_select);
+void tmr_hall_select(tmr_type *tmr_x, confirm_state new_state);
+void tmr_channel_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_trgout2_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_select);
+void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state);
+void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state);
+void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state);
+flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
+void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag);
+void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event);
+void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_internal_clock_set(tmr_type *tmr_x);
+void tmr_output_channel_fast_set(tmr_type *tmr_x, tmr_channel_output_fast_type oc_fast);
+void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_polarity_active_type oc_polarity);
+void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+ tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
+void tmr_external_clock_mode1_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+ tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
+void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+ tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
+void tmr_encoder_mode_config(tmr_type *tmr_x, tmr_encoder_mode_type encoder_mode, tmr_input_polarity_type \
+ ic1_polarity, tmr_input_polarity_type ic2_polarity);
+void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_force_output_type force_output);
+void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \
+ tmr_dma_address_type dma_base_address);
+void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct);
+void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_usart.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_usart.h
new file mode 100644
index 0000000..d7c6176
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_usart.h
@@ -0,0 +1,412 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_usart.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 usart header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_USART_H
+#define __AT32F435_437_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/** @defgroup USART_flags_definition
+ * @brief usart flag
+ * @{
+ */
+
+#define USART_PERR_FLAG ((uint32_t)0x00000001) /*!< usart parity error flag */
+#define USART_FERR_FLAG ((uint32_t)0x00000002) /*!< usart framing error flag */
+#define USART_NERR_FLAG ((uint32_t)0x00000004) /*!< usart noise error flag */
+#define USART_ROERR_FLAG ((uint32_t)0x00000008) /*!< usart receiver overflow error flag */
+#define USART_IDLEF_FLAG ((uint32_t)0x00000010) /*!< usart idle flag */
+#define USART_RDBF_FLAG ((uint32_t)0x00000020) /*!< usart receive data buffer full flag */
+#define USART_TDC_FLAG ((uint32_t)0x00000040) /*!< usart transmit data complete flag */
+#define USART_TDBE_FLAG ((uint32_t)0x00000080) /*!< usart transmit data buffer empty flag */
+#define USART_BFF_FLAG ((uint32_t)0x00000100) /*!< usart break frame flag */
+#define USART_CTSCF_FLAG ((uint32_t)0x00000200) /*!< usart cts change flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_interrupts_definition
+ * @brief usart interrupt
+ * @{
+ */
+
+#define USART_IDLE_INT MAKE_VALUE(0x0C,0x04) /*!< usart idle interrupt */
+#define USART_RDBF_INT MAKE_VALUE(0x0C,0x05) /*!< usart receive data buffer full interrupt */
+#define USART_TDC_INT MAKE_VALUE(0x0C,0x06) /*!< usart transmit data complete interrupt */
+#define USART_TDBE_INT MAKE_VALUE(0x0C,0x07) /*!< usart transmit data buffer empty interrupt */
+#define USART_PERR_INT MAKE_VALUE(0x0C,0x08) /*!< usart parity error interrupt */
+#define USART_BF_INT MAKE_VALUE(0x10,0x06) /*!< usart break frame interrupt */
+#define USART_ERR_INT MAKE_VALUE(0x14,0x00) /*!< usart error interrupt */
+#define USART_CTSCF_INT MAKE_VALUE(0x14,0x0A) /*!< usart cts change interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_exported_types
+ * @{
+ */
+
+/**
+ * @brief usart parity selection type
+ */
+typedef enum
+{
+ USART_PARITY_NONE = 0x00, /*!< usart no parity */
+ USART_PARITY_EVEN = 0x01, /*!< usart even parity */
+ USART_PARITY_ODD = 0x02 /*!< usart odd parity */
+} usart_parity_selection_type;
+
+/**
+ * @brief usart wakeup mode type
+ */
+typedef enum
+{
+ USART_WAKEUP_BY_IDLE_FRAME = 0x00, /*!< usart wakeup by idle frame */
+ USART_WAKEUP_BY_MATCHING_ID = 0x01 /*!< usart wakeup by matching id */
+} usart_wakeup_mode_type;
+
+/**
+ * @brief usart data bit num type
+ */
+typedef enum
+{
+ USART_DATA_7BITS = 0x00, /*!< usart data size is 7 bits */
+ USART_DATA_8BITS = 0x01, /*!< usart data size is 8 bits */
+ USART_DATA_9BITS = 0x02 /*!< usart data size is 9 bits */
+} usart_data_bit_num_type;
+
+/**
+ * @brief usart break frame bit num type
+ */
+typedef enum
+{
+ USART_BREAK_10BITS = 0x00, /*!< usart lin mode berak frame detection 10 bits */
+ USART_BREAK_11BITS = 0x01 /*!< usart lin mode berak frame detection 11 bits */
+} usart_break_bit_num_type;
+
+/**
+ * @brief usart phase of the clock type
+ */
+typedef enum
+{
+ USART_CLOCK_PHASE_1EDGE = 0x00, /*!< usart data capture is done on the clock leading edge */
+ USART_CLOCK_PHASE_2EDGE = 0x01 /*!< usart data capture is done on the clock trailing edge */
+} usart_clock_phase_type;
+
+/**
+ * @brief usart polarity of the clock type
+ */
+typedef enum
+{
+ USART_CLOCK_POLARITY_LOW = 0x00, /*!< usart clock stay low level outside transmission window */
+ USART_CLOCK_POLARITY_HIGH = 0x01 /*!< usart clock stay high level outside transmission window */
+} usart_clock_polarity_type;
+
+/**
+ * @brief usart last bit clock pulse type
+ */
+typedef enum
+{
+ USART_CLOCK_LAST_BIT_NONE = 0x00, /*!< usart clock pulse of the last data bit is not outputted */
+ USART_CLOCK_LAST_BIT_OUTPUT = 0x01 /*!< usart clock pulse of the last data bit is outputted */
+} usart_lbcp_type;
+
+/**
+ * @brief usart stop bit num type
+ */
+typedef enum
+{
+ USART_STOP_1_BIT = 0x00, /*!< usart stop bits num is 1 */
+ USART_STOP_0_5_BIT = 0x01, /*!< usart stop bits num is 0.5 */
+ USART_STOP_2_BIT = 0x02, /*!< usart stop bits num is 2 */
+ USART_STOP_1_5_BIT = 0x03 /*!< usart stop bits num is 1.5 */
+} usart_stop_bit_num_type;
+
+/**
+ * @brief usart hardware flow control type
+ */
+typedef enum
+{
+ USART_HARDWARE_FLOW_NONE = 0x00, /*!< usart without hardware flow */
+ USART_HARDWARE_FLOW_RTS = 0x01, /*!< usart hardware flow only rts */
+ USART_HARDWARE_FLOW_CTS = 0x02, /*!< usart hardware flow only cts */
+ USART_HARDWARE_FLOW_RTS_CTS = 0x03 /*!< usart hardware flow both rts and cts */
+} usart_hardware_flow_control_type;
+
+/**
+ * @brief usart identification bit num type
+ */
+typedef enum
+{
+ USART_ID_FIXED_4_BIT = 0x00, /*!< usart id bit num fixed 4 bits */
+ USART_ID_RELATED_DATA_BIT = 0x01 /*!< usart id bit num related data bits */
+} usart_identification_bit_num_type;
+
+/**
+ * @brief usart de polarity type
+ */
+typedef enum
+{
+ USART_DE_POLARITY_HIGH = 0x00, /*!< usart de polarity high */
+ USART_DE_POLARITY_LOW = 0x01 /*!< usart de polarity low */
+} usart_de_polarity_type;
+
+/**
+ * @brief type define usart register all
+ */
+typedef struct
+{
+ /**
+ * @brief usart sts register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t perr : 1; /* [0] */
+ __IO uint32_t ferr : 1; /* [1] */
+ __IO uint32_t nerr : 1; /* [2] */
+ __IO uint32_t roerr : 1; /* [3] */
+ __IO uint32_t idlef : 1; /* [4] */
+ __IO uint32_t rdbf : 1; /* [5] */
+ __IO uint32_t tdc : 1; /* [6] */
+ __IO uint32_t tdbe : 1; /* [7] */
+ __IO uint32_t bff : 1; /* [8] */
+ __IO uint32_t ctscf : 1; /* [9] */
+ __IO uint32_t reserved1 : 22;/* [31:10] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief usart dt register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t dt;
+ struct
+ {
+ __IO uint32_t dt : 9; /* [8:0] */
+ __IO uint32_t reserved1 : 23;/* [31:9] */
+ } dt_bit;
+ };
+
+ /**
+ * @brief usart baudr register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t baudr;
+ struct
+ {
+ __IO uint32_t div : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } baudr_bit;
+ };
+
+ /**
+ * @brief usart ctrl1 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t sbf : 1; /* [0] */
+ __IO uint32_t rm : 1; /* [1] */
+ __IO uint32_t ren : 1; /* [2] */
+ __IO uint32_t ten : 1; /* [3] */
+ __IO uint32_t idleien : 1; /* [4] */
+ __IO uint32_t rdbfien : 1; /* [5] */
+ __IO uint32_t tdcien : 1; /* [6] */
+ __IO uint32_t tdbeien : 1; /* [7] */
+ __IO uint32_t perrien : 1; /* [8] */
+ __IO uint32_t psel : 1; /* [9] */
+ __IO uint32_t pen : 1; /* [10] */
+ __IO uint32_t wum : 1; /* [11] */
+ __IO uint32_t dbn_l : 1; /* [12] */
+ __IO uint32_t uen : 1; /* [13] */
+ __IO uint32_t reserved1 : 2; /* [15:14] */
+ __IO uint32_t tcdt : 5; /* [20:16] */
+ __IO uint32_t tsdt : 5; /* [25:21] */
+ __IO uint32_t reserved2 : 2; /* [27:26] */
+ __IO uint32_t dbn_h : 1; /* [28] */
+ __IO uint32_t reserved3 : 3; /* [31:29] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief usart ctrl2 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t id_l : 4; /* [3:0] */
+ __IO uint32_t idbn : 1; /* [4] */
+ __IO uint32_t bfbn : 1; /* [5] */
+ __IO uint32_t bfien : 1; /* [6] */
+ __IO uint32_t reserved1 : 1; /* [7] */
+ __IO uint32_t lbcp : 1; /* [8] */
+ __IO uint32_t clkpha : 1; /* [9] */
+ __IO uint32_t clkpol : 1; /* [10] */
+ __IO uint32_t clken : 1; /* [11] */
+ __IO uint32_t stopbn : 2; /* [13:12] */
+ __IO uint32_t linen : 1; /* [14] */
+ __IO uint32_t trpswap : 1; /* [15] */
+ __IO uint32_t reserved2 : 12;/* [27:16] */
+ __IO uint32_t id_h : 4; /* [31:28] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief usart ctrl3 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t ctrl3;
+ struct
+ {
+ __IO uint32_t errien : 1; /* [0] */
+ __IO uint32_t irdaen : 1; /* [1] */
+ __IO uint32_t irdalp : 1; /* [2] */
+ __IO uint32_t slben : 1; /* [3] */
+ __IO uint32_t scnacken : 1; /* [4] */
+ __IO uint32_t scmen : 1; /* [5] */
+ __IO uint32_t dmaren : 1; /* [6] */
+ __IO uint32_t dmaten : 1; /* [7] */
+ __IO uint32_t rtsen : 1; /* [8] */
+ __IO uint32_t ctsen : 1; /* [9] */
+ __IO uint32_t ctscfien : 1; /* [10] */
+ __IO uint32_t reserved1 : 3; /* [13:11] */
+ __IO uint32_t rs485en : 1; /* [14] */
+ __IO uint32_t dep : 1; /* [15] */
+ __IO uint32_t reserved2 : 16;/* [31:16] */
+ } ctrl3_bit;
+ };
+
+ /**
+ * @brief usart gdiv register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t gdiv;
+ struct
+ {
+ __IO uint32_t isdiv : 8; /* [7:0] */
+ __IO uint32_t scgt : 8; /* [15:8] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } gdiv_bit;
+ };
+} usart_type;
+
+/**
+ * @}
+ */
+
+#define USART1 ((usart_type *) USART1_BASE)
+#define USART2 ((usart_type *) USART2_BASE)
+#define USART3 ((usart_type *) USART3_BASE)
+#define UART4 ((usart_type *) UART4_BASE)
+#define UART5 ((usart_type *) UART5_BASE)
+#define USART6 ((usart_type *) USART6_BASE)
+#define UART7 ((usart_type *) UART7_BASE)
+#define UART8 ((usart_type *) UART8_BASE)
+
+/** @defgroup USART_exported_functions
+ * @{
+ */
+
+void usart_reset(usart_type* usart_x);
+void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit);
+void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity);
+void usart_enable(usart_type* usart_x, confirm_state new_state);
+void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state);
+void usart_receiver_enable(usart_type* usart_x, confirm_state new_state);
+void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb);
+void usart_clock_enable(usart_type* usart_x, confirm_state new_state);
+void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state);
+void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state);
+void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state);
+void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id);
+void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode);
+void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state);
+void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit);
+void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state);
+void usart_data_transmit(usart_type* usart_x, uint16_t data);
+uint16_t usart_data_receive(usart_type* usart_x);
+void usart_break_send(usart_type* usart_x);
+void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val);
+void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val);
+void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state);
+void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state);
+void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state);
+void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state);
+void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state);
+void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state);
+flag_status usart_flag_get(usart_type* usart_x, uint32_t flag);
+void usart_flag_clear(usart_type* usart_x, uint32_t flag);
+void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time);
+void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state);
+void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type id_bit_num);
+void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity);
+void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_usb.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_usb.h
new file mode 100644
index 0000000..c5fb3fc
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_usb.h
@@ -0,0 +1,1422 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_usb.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 usb header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_USB_H
+#define __AT32F435_437_USB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup USB
+ * @{
+ */
+
+/** @defgroup USB_global_interrupts_definition
+ * @brief usb global interrupt mask
+ * @{
+ */
+
+#define USB_OTG_MODEMIS_INT ((uint32_t)0x00000002) /*!< usb otg mode mismatch interrupt */
+#define USB_OTG_OTGINT_INT ((uint32_t)0x00000004) /*!< usb otg interrupt */
+#define USB_OTG_SOF_INT ((uint32_t)0x00000008) /*!< usb otg sof interrupt */
+#define USB_OTG_RXFLVL_INT ((uint32_t)0x00000010) /*!< usb otg receive fifo non-empty interrupt */
+#define USB_OTG_NPTXFEMP_INT ((uint32_t)0x00000020) /*!< usb otg non-periodic tx fifo empty interrupt */
+#define USB_OTG_GINNAKEFF_INT ((uint32_t)0x00000040) /*!< usb otg global non-periodic in nak effective interrupt */
+#define USB_OTG_GOUTNAKEFF_INT ((uint32_t)0x00000080) /*!< usb otg global out nak effective interrupt */
+#define USB_OTG_ERLYSUSP_INT ((uint32_t)0x00000400) /*!< usb otg early suspend interrupt */
+#define USB_OTG_USBSUSP_INT ((uint32_t)0x00000800) /*!< usb otg suspend interrupt */
+#define USB_OTG_USBRST_INT ((uint32_t)0x00001000) /*!< usb otg reset interrupt */
+#define USB_OTG_ENUMDONE_INT ((uint32_t)0x00002000) /*!< usb otg enumeration done interrupt */
+#define USB_OTG_ISOOUTDROP_INT ((uint32_t)0x00004000) /*!< usb otg isochronous out packet dropped interrut */
+#define USB_OTG_EOPF_INT ((uint32_t)0x00008000) /*!< usb otg eop interrupt */
+#define USB_OTG_IEPT_INT ((uint32_t)0x00040000) /*!< usb otg in endpoint interrupt */
+#define USB_OTG_OEPT_INT ((uint32_t)0x00080000) /*!< usb otg out endpoint interrupt */
+#define USB_OTG_INCOMISOIN_INT ((uint32_t)0x00100000) /*!< usb otg incomplete isochronous in transfer interrupt */
+#define USB_OTG_INCOMPIP_INCOMPISOOUT_INT ((uint32_t)0x00200000) /*!< usb otg incomplete periodic transfer/isochronous out interrupt */
+#define USB_OTG_PRT_INT ((uint32_t)0x01000000) /*!< usb otg host port interrupt */
+#define USB_OTG_HCH_INT ((uint32_t)0x02000000) /*!< usb otg host channel interrupt */
+#define USB_OTG_PTXFEMP_INT ((uint32_t)0x04000000) /*!< usb otg periodic txfifo empty interrupt */
+#define USB_OTG_CONIDSCHG_INT ((uint32_t)0x10000000) /*!< usb otg connector id status change interrupt */
+#define USB_OTG_DISCON_INT ((uint32_t)0x20000000) /*!< usb otg disconnect detected interrupt */
+#define USB_OTG_WKUP_INT ((uint32_t)0x80000000) /*!< usb otg wakeup interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup USB_global_interrupt_flags_definition
+ * @brief usb global interrupt flag
+ * @{
+ */
+
+#define USB_OTG_CURMODE ((uint32_t)0x00000001) /*!< usb otg current mode */
+#define USB_OTG_MODEMIS_FLAG ((uint32_t)0x00000002) /*!< usb otg mode mismatch flag */
+#define USB_OTG_OTGINT_FLAG ((uint32_t)0x00000004) /*!< usb otg flag */
+#define USB_OTG_SOF_FLAG ((uint32_t)0x00000008) /*!< usb otg sof flag */
+#define USB_OTG_RXFLVL_FLAG ((uint32_t)0x00000010) /*!< usb otg receive fifo non-empty flag */
+#define USB_OTG_NPTXFEMP_FLAG ((uint32_t)0x00000020) /*!< usb otg non-periodic tx fifo empty flag */
+#define USB_OTG_GINNAKEFF_FLAG ((uint32_t)0x00000040) /*!< usb otg global non-periodic in nak effective flag */
+#define USB_OTG_GOUTNAKEFF_FLAG ((uint32_t)0x00000080) /*!< usb otg global out nak effective flag */
+#define USB_OTG_ERLYSUSP_FLAG ((uint32_t)0x00000400) /*!< usb otg early suspend flag */
+#define USB_OTG_USBSUSP_FLAG ((uint32_t)0x00000800) /*!< usb otg suspend flag */
+#define USB_OTG_USBRST_FLAG ((uint32_t)0x00001000) /*!< usb otg reset flag */
+#define USB_OTG_ENUMDONE_FLAG ((uint32_t)0x00002000) /*!< usb otg enumeration done flag */
+#define USB_OTG_ISOOUTDROP_FLAG ((uint32_t)0x00004000) /*!< usb otg isochronous out packet dropped flag */
+#define USB_OTG_EOPF_FLAG ((uint32_t)0x00008000) /*!< usb otg eop flag */
+#define USB_OTG_IEPT_FLAG ((uint32_t)0x00040000) /*!< usb otg in endpoint flag */
+#define USB_OTG_OEPT_FLAG ((uint32_t)0x00080000) /*!< usb otg out endpoint flag */
+#define USB_OTG_INCOMISOIN_FLAG ((uint32_t)0x00100000) /*!< usb otg incomplete isochronous in transfer flag */
+#define USB_OTG_INCOMPIP_INCOMPISOOUT_FLAG ((uint32_t)0x00200000) /*!< usb otg incomplete periodic transfer/isochronous out flag */
+#define USB_OTG_PRT_FLAG ((uint32_t)0x01000000) /*!< usb otg host port flag */
+#define USB_OTG_HCH_FLAG ((uint32_t)0x02000000) /*!< usb otg host channel flag */
+#define USB_OTG_PTXFEMP_FLAG ((uint32_t)0x04000000) /*!< usb otg periodic txfifo empty flag */
+#define USB_OTG_CONIDSCHG_FLAG ((uint32_t)0x10000000) /*!< usb otg connector id status change flag */
+#define USB_OTG_DISCON_FLAG ((uint32_t)0x20000000) /*!< usb otg disconnect detected flag */
+#define USB_OTG_WKUP_FLAG ((uint32_t)0x80000000) /*!< usb otg wakeup flag */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup USB_global_setting_definition
+ * @brief usb global setting
+ * @{
+ */
+
+/**
+ * @brief usb turnaround time
+ */
+#define USB_TRDTIM_8 0x9 /*!< usb turn around time 8 */
+#define USB_TRDTIM_16 0x5 /*!< usb turn around time 16 */
+
+/**
+ * @brief usb receive status
+ */
+#define USB_OTG_GRXSTSP_EPTNUM ((uint32_t)0x0000000F) /*!< usb device receive packet endpoint number*/
+#define USB_OTG_GRXSTSP_CHNUM ((uint32_t)0x0000000F) /*!< usb host receive packet channel number*/
+#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< usb receive packet byte count */
+#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< usb receive packet pid */
+#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< usb receive packet status */
+
+/**
+ * @brief usb host packet status
+ */
+#define PKTSTS_IN_DATA_PACKET_RECV 0x2 /*!< usb host in data packet received */
+#define PKTSTS_IN_TRANSFER_COMPLETE 0x3 /*!< usb host in transfer completed */
+#define PKTSTS_DATA_BIT_ERROR 0x5 /*!< usb host data toggle error */
+#define PKTSTS_CHANNEL_STOP 0x7 /*!< usb host channel halted */
+
+/**
+ * @brief usb device packet status
+ */
+#define USB_OUT_STS_NAK 0x1 /*!< usb device global out nak */
+#define USB_OUT_STS_DATA 0x2 /*!< usb device out data packet received */
+#define USB_OUT_STS_COMP 0x3 /*!< usb device out transfer completed */
+#define USB_SETUP_STS_COMP 0x4 /*!< usb device setup transcation completed */
+#define USB_SETUP_STS_DATA 0x6 /*!< usb device setup data packet received */
+
+/**
+ * @}
+ */
+
+/** @defgroup USB_host_config_definition
+ * @{
+ */
+
+/**
+ * @brief usb host phy clock
+ */
+#define USB_HCFG_CLK_60M 0 /*!< usb host phy clock 60mhz */
+#define USB_HCFG_CLK_48M 1 /*!< usb host phy clock 48mhz */
+#define USB_HCFG_CLK_6M 2 /*!< usb host phy clock 6mhz */
+
+/**
+ * @brief usb host port status
+ */
+#define USB_OTG_HPRT_PRTCONSTS ((uint32_t)0x00000001) /*!< usb host port connect status */
+#define USB_OTG_HPRT_PRTCONDET ((uint32_t)0x00000002) /*!< usb host port connect detected */
+#define USB_OTG_HPRT_PRTENA ((uint32_t)0x00000004) /*!< usb host port enable */
+#define USB_OTG_HPRT_PRTENCHNG ((uint32_t)0x00000008) /*!< usb host port enable/disable change */
+#define USB_OTG_HPRT_PRTOVRCACT ((uint32_t)0x00000010) /*!< usb host port overcurrent active */
+#define USB_OTG_HPRT_PRTOVRCCHNG ((uint32_t)0x00000020) /*!< usb host port overcurrent change */
+#define USB_OTG_HPRT_PRTRES ((uint32_t)0x00000040) /*!< usb host port resume */
+#define USB_OTG_HPRT_PRTSUSP ((uint32_t)0x00000080) /*!< usb host port suspend */
+#define USB_OTG_HPRT_PRTRST ((uint32_t)0x00000100) /*!< usb host port reset */
+#define USB_OTG_HPRT_PRTLNSTS ((uint32_t)0x00000C00) /*!< usb host port line status */
+#define USB_OTG_HPRT_PRTPWR ((uint32_t)0x00001000) /*!< usb host port power */
+#define USB_OTG_HPRT_PRTSPD ((uint32_t)0x00060000) /*!< usb host port speed */
+
+/**
+ * @brief usb port speed
+ */
+#define USB_PRTSPD_HIGH_SPEED 0 /*!< usb host port high speed */
+#define USB_PRTSPD_FULL_SPEED 1 /*!< usb host port full speed */
+#define USB_PRTSPD_LOW_SPEED 2 /*!< usb host port low speed */
+
+/**
+ * @brief usb host register hcchar bit define
+ */
+#define USB_OTG_HCCHAR_MPS ((uint32_t)0x000007FF) /*!< channel maximum packet size */
+#define USB_OTG_HCCHAR_EPTNUM ((uint32_t)0x00007800) /*!< endpoint number */
+#define USB_OTG_HCCHAR_EPTDIR ((uint32_t)0x00008000) /*!< endpoint direction */
+#define USB_OTG_HCCHAR_LSPDDEV ((uint32_t)0x00020000) /*!< low speed device */
+#define USB_OTG_HCCHAR_EPTYPE ((uint32_t)0x000C0000) /*!< endpoint type */
+#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< multi count */
+#define USB_OTG_HCCHAR_DEVADDR ((uint32_t)0x1FC00000) /*!< device address */
+#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< odd frame */
+#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< channel disable */
+#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< channel enable */
+
+/**
+ * @brief usb host register hctsiz bit define
+ */
+#define USB_OTG_HCTSIZ_XFERSIZE ((uint32_t)0x0007FFFF) /*!< channel transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< channel packet count */
+#define USB_OTG_HCTSIZ_PID ((uint32_t)0x60000000) /*!< channel pid */
+
+/**
+ * @brief usb host channel interrupt mask
+ */
+#define USB_OTG_HC_XFERCM_INT ((uint32_t)0x00000001) /*!< channel transfer complete interrupt */
+#define USB_OTG_HC_CHHLTDM_INT ((uint32_t)0x00000002) /*!< channel halted interrupt */
+#define USB_OTG_HC_STALLM_INT ((uint32_t)0x00000008) /*!< channel stall interrupt */
+#define USB_OTG_HC_NAKM_INT ((uint32_t)0x00000010) /*!< channel nak interrupt */
+#define USB_OTG_HC_ACKM_INT ((uint32_t)0x00000020) /*!< channel ack interrupt */
+#define USB_OTG_HC_NYETM_INT ((uint32_t)0x00000040) /*!< channel nyet interrupt */
+#define USB_OTG_HC_XACTERRM_INT ((uint32_t)0x00000080) /*!< channel transaction error interrupt */
+#define USB_OTG_HC_BBLERRM_INT ((uint32_t)0x00000100) /*!< channel babble error interrupt */
+#define USB_OTG_HC_FRMOVRRUN_INT ((uint32_t)0x00000200) /*!< channel frame overrun interrupt */
+#define USB_OTG_HC_DTGLERRM_INT ((uint32_t)0x00000400) /*!< channel data toggle interrupt */
+
+/**
+ * @brief usb host channel interrupt flag
+ */
+#define USB_OTG_HC_XFERC_FLAG ((uint32_t)0x00000001) /*!< channel transfer complete flag */
+#define USB_OTG_HC_CHHLTD_FLAG ((uint32_t)0x00000002) /*!< channel halted flag */
+#define USB_OTG_HC_STALL_FLAG ((uint32_t)0x00000008) /*!< channel stall flag */
+#define USB_OTG_HC_NAK_FLAG ((uint32_t)0x00000010) /*!< channel nak flag */
+#define USB_OTG_HC_ACK_FLAG ((uint32_t)0x00000020) /*!< channel ack flag */
+#define USB_OTG_HC_NYET_FLAG ((uint32_t)0x00000040) /*!< channel nyet flag */
+#define USB_OTG_HC_XACTERR_FLAG ((uint32_t)0x00000080) /*!< channel transaction error flag */
+#define USB_OTG_HC_BBLERR_FLAG ((uint32_t)0x00000100) /*!< channel babble error flag */
+#define USB_OTG_HC_FRMOVRRUN_FLAG ((uint32_t)0x00000200) /*!< channel frame overrun flag */
+#define USB_OTG_HC_DTGLERR_FLAG ((uint32_t)0x00000400) /*!< channel data toggle flag */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup USB_device_config_definition
+ * @{
+ */
+/**
+ * @brief usb device periodic frame interval
+ */
+typedef enum
+{
+ DCFG_PERFRINT_80 = 0x00, /*!< periodic frame interval 80% */
+ DCFG_PERFRINT_85 = 0x01, /*!< periodic frame interval 85% */
+ DCFG_PERFRINT_90 = 0x02, /*!< periodic frame interval 90% */
+ DCFG_PERFRINT_95 = 0x03 /*!< periodic frame interval 95% */
+} dcfg_perfrint_type;
+
+
+/**
+ * @brief usb device full speed
+ */
+#define USB_DCFG_FULL_SPEED 3 /*!< device full speed */
+
+/**
+ * @brief usb device ctrl define
+ */
+#define USB_OTG_DCTL_RWKUPSIG ((uint32_t)0x00000001) /*!< usb device remote wakeup signaling */
+#define USB_OTG_DCTL_SFTDISCON ((uint32_t)0x00000002) /*!< usb device soft disconnect */
+#define USB_OTG_DCTL_GNPINNAKSTS ((uint32_t)0x00000004) /*!< usb device global non-periodic in nak status */
+#define USB_OTG_DCTL_GOUTNAKSTS ((uint32_t)0x00000008) /*!< usb device global out nak status */
+#define USB_OTG_DCTL_SGNPINNAK ((uint32_t)0x00000080) /*!< usb device set global non-periodic in nak */
+#define USB_OTG_DCTL_CGNPINNAK ((uint32_t)0x00000100) /*!< usb device clear global non-periodic in nak */
+#define USB_OTG_DCTL_SGOUTNAK ((uint32_t)0x00000200) /*!< usb device set global out nak status */
+#define USB_OTG_DCTL_CGOUTNAK ((uint32_t)0x00000400) /*!< usb device clear global out nak status */
+#define USB_OTG_DCTL_PWROPRGDNE ((uint32_t)0x00000800) /*!< usb device power on programming done */
+
+/**
+ * @brief usb device in endpoint flag
+ */
+#define USB_OTG_DIEPINT_XFERC_FLAG ((uint32_t)0x00000001) /*!< usb device in transfer completed flag */
+#define USB_OTG_DIEPINT_EPTDISD_FLAG ((uint32_t)0x00000002) /*!< usb device endpoint disable flag */
+#define USB_OTG_DIEPINT_TIMEOUT_FLAG ((uint32_t)0x00000008) /*!< usb device in timeout */
+#define USB_OTG_DIEPINT_INTKNTXFEMP_FLAG ((uint32_t)0x00000010) /*!< usb device in token received when tx fifo is empty flag */
+#define USB_OTG_DIEPINT_INEPTNAK_FLAG ((uint32_t)0x00000040) /*!< usb device in endpoint nak effective flag */
+#define USB_OTG_DIEPINT_TXFEMP_FLAG ((uint32_t)0x00000080) /*!< usb device transmit fifo empty flag */
+
+/**
+ * @brief usb device out endpoint flag
+ */
+#define USB_OTG_DOEPINT_XFERC_FLAG ((uint32_t)0x00000001) /*!< usb device out transfer completed flag */
+#define USB_OTG_DOEPINT_EPTDISD_FLAG ((uint32_t)0x00000002) /*!< usb device endpoint disable flag */
+#define USB_OTG_DOEPINT_SETUP_FLAG ((uint32_t)0x00000008) /*!< usb device setup flag */
+#define USB_OTG_DOEPINT_OUTTEPD_FLAG ((uint32_t)0x00000010) /*!< usb device out token recevied when endpoint disable flag */
+#define USB_OTG_DOEPINT_B2BSTUP_FLAG ((uint32_t)0x00000040) /*!< back-to-back setup packets received */
+
+/**
+ * @brief usb device in endpoint fifo space mask
+ */
+#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< usb device in endpoint tx fifo space avail */
+
+/**
+ * @brief endpoint0 maximum packet size
+ */
+#define USB_EPT0_MPS_64 0 /*!< usb device endpoint 0 maximum packet size 64byte */
+#define USB_EPT0_MPS_32 1 /*!< usb device endpoint 0 maximum packet size 32byte */
+#define USB_EPT0_MPS_16 2 /*!< usb device endpoint 0 maximum packet size 16byte */
+#define USB_EPT0_MPS_8 3 /*!< usb device endpoint 0 maximum packet size 8byte */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief otg fifo size (word)
+ */
+#define OTG_FIFO_SIZE 320 /*!< otg usb total fifo size */
+
+/**
+ * @brief otg host max buffer length (byte)
+ */
+#define USB_MAX_DATA_LENGTH 0x200 /*!< usb host maximum buffer size */
+
+#define OTGFS_USB_GLOBAL
+#define OTGFS_USB_DEVICE
+#define OTGFS_USB_HOST
+
+/** @defgroup USB_exported_enum_types
+ * @{
+ */
+
+/**
+ * @brief usb mode define(device, host, drd)
+ */
+typedef enum
+{
+ OTG_DEVICE_MODE, /*!< usb device mode */
+ OTG_HOST_MODE, /*!< usb host mode */
+ OTG_DRD_MODE /*!< usb drd mode */
+} otg_mode_type;
+
+/**
+ * @brief endpoint type define
+ */
+typedef enum
+{
+ EPT_CONTROL_TYPE = 0x00, /*!< usb endpoint type control */
+ EPT_ISO_TYPE = 0x01, /*!< usb endpoint type iso */
+ EPT_BULK_TYPE = 0x02, /*!< usb endpoint type bulk */
+ EPT_INT_TYPE = 0x03 /*!< usb endpoint type interrupt */
+} endpoint_trans_type;
+
+/**
+ * @brief usb endpoint number define type
+ */
+typedef enum
+{
+ USB_EPT0 = 0x00, /*!< usb endpoint 0 */
+ USB_EPT1 = 0x01, /*!< usb endpoint 1 */
+ USB_EPT2 = 0x02, /*!< usb endpoint 2 */
+ USB_EPT3 = 0x03, /*!< usb endpoint 3 */
+ USB_EPT4 = 0x04, /*!< usb endpoint 4 */
+ USB_EPT5 = 0x05, /*!< usb endpoint 5 */
+ USB_EPT6 = 0x06, /*!< usb endpoint 6 */
+ USB_EPT7 = 0x07 /*!< usb endpoint 7 */
+} usb_endpoint_number_type;
+
+/**
+ * @brief usb endpoint max num define
+ */
+#ifndef USB_EPT_MAX_NUM
+#define USB_EPT_MAX_NUM 8 /*!< usb device support endpoint number */
+#endif
+/**
+ * @brief usb channel max num define
+ */
+#ifndef USB_HOST_CHANNEL_NUM
+#define USB_HOST_CHANNEL_NUM 16 /*!< usb host support channel number */
+#endif
+
+/**
+ * @brief endpoint trans dir type
+ */
+typedef enum
+{
+ EPT_DIR_IN = 0x00, /*!< usb transfer direction in */
+ EPT_DIR_OUT = 0x01 /*!< usb transfer direction out */
+} endpoint_dir_type;
+
+/**
+ * @brief otgfs1 and otgfs2 select type
+ */
+typedef enum
+{
+ USB_OTG1_ID, /*!< usb otg 1 id */
+ USB_OTG2_ID /*!< usb otg 2 id */
+} otg_id_type;
+
+/**
+ * @brief usb clock select
+ */
+typedef enum
+{
+ USB_CLK_HICK, /*!< usb clock use hick */
+ USB_CLK_HEXT /*!< usb clock use hext */
+}usb_clk48_s;
+
+/**
+ * @}
+ */
+
+
+
+/** @defgroup USB_exported_types
+ * @{
+ */
+
+/**
+ * @brief usb endpoint infomation structure definition
+ */
+typedef struct
+{
+ uint8_t eptn; /*!< endpoint register number (0~7) */
+ uint8_t ept_address; /*!< endpoint address */
+ uint8_t inout; /*!< endpoint dir EPT_DIR_IN or EPT_DIR_OUT */
+ uint8_t trans_type; /*!< endpoint type:
+ EPT_CONTROL_TYPE, EPT_BULK_TYPE, EPT_INT_TYPE, EPT_ISO_TYPE*/
+ uint16_t tx_addr; /*!< endpoint tx buffer offset address */
+ uint16_t rx_addr; /*!< endpoint rx buffer offset address */
+ uint32_t maxpacket; /*!< endpoint max packet*/
+ uint8_t is_double_buffer; /*!< endpoint double buffer flag */
+ uint8_t stall; /*!< endpoint is stall state */
+ uint32_t status;
+
+ /* transmission buffer and count */
+ uint8_t *trans_buf; /*!< endpoint transmission buffer */
+ uint32_t total_len; /*!< endpoint transmission lengtg */
+ uint32_t trans_len; /*!< endpoint transmission length*/
+
+ uint32_t last_len; /*!< last transfer length */
+ uint32_t ept0_slen; /*!< endpoint 0 transfer sum length */
+} usb_ept_info;
+
+
+/**
+ * @brief usb host channel infomation structure definition
+ */
+typedef struct
+{
+ uint8_t ch_num; /*!< host channel number */
+ uint8_t address; /*!< device address */
+ uint8_t dir; /*!< transmission direction */
+ uint8_t ept_num; /*!< device endpoint number */
+ uint8_t ept_type; /*!< channel transmission type */
+ uint32_t maxpacket; /*!< support max packet size */
+ uint8_t data_pid; /*!< data pid */
+ uint8_t speed; /*!< usb speed */
+ uint8_t stall; /*!< channel stall flag */
+ uint32_t status; /*!< channel status */
+ uint32_t state; /*!< channel state */
+ uint32_t urb_sts; /*!< usb channel request block state */
+
+ uint8_t toggle_in; /*!< channel in transfer toggle */
+ uint8_t toggle_out; /*!< channel out transfer toggle */
+
+ /* transmission buffer and count */
+ uint8_t *trans_buf; /* host channel buffer */
+ uint32_t trans_len; /* host channel transmission len */
+ uint32_t trans_count; /* host channel transmission count*/
+} usb_hch_type;
+
+
+typedef struct
+{
+ /**
+ * @brief otgfs control and status register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t gotgctrl;
+ struct
+ {
+ __IO uint32_t reserved1 : 16; /* [15:0] */
+ __IO uint32_t cidsts : 1; /* [16] */
+ __IO uint32_t reserved2 : 4; /* [20:17] */
+ __IO uint32_t curmod : 1; /* [21] */
+ __IO uint32_t reserved3 : 10; /* [31:22] */
+ } gotgctrl_bit;
+ };
+
+ /**
+ * @brief otgfs interrupt register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t gotgint;
+ struct
+ {
+ __IO uint32_t reserved1 : 2; /* [1:0] */
+ __IO uint32_t sesenddet : 1; /* [2] */
+ __IO uint32_t reserved2 : 29; /* [31:3] */
+
+ } gotgint_bit;
+ };
+
+ /**
+ * @brief otgfs gahbcfg configuration register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t gahbcfg;
+ struct
+ {
+ __IO uint32_t glbintmsk : 1; /* [0] */
+ __IO uint32_t reserved1 : 6; /* [6:1] */
+ __IO uint32_t nptxfemplvl : 1; /* [7] */
+ __IO uint32_t ptxfemplvl : 1; /* [8] */
+ __IO uint32_t reserved2 : 23; /* [31:9] */
+ } gahbcfg_bit;
+ };
+
+ /**
+ * @brief otgfs usb configuration register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t gusbcfg;
+ struct
+ {
+ __IO uint32_t toutcal : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 7; /* [9:3] */
+ __IO uint32_t usbtrdtim : 4; /* [13:10] */
+ __IO uint32_t reserved2 : 15; /* [28:14] */
+ __IO uint32_t fhstmode : 1; /* [29] */
+ __IO uint32_t fdevmode : 1; /* [30] */
+ __IO uint32_t cotxpkt : 1; /* [31] */
+ } gusbcfg_bit;
+ };
+
+ /**
+ * @brief otgfs reset register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t grstctl;
+ struct
+ {
+ __IO uint32_t csftrst : 1; /* [0] */
+ __IO uint32_t piusftrst : 1; /* [1] */
+ __IO uint32_t frmcntrst : 1; /* [2] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t rxfflsh : 1; /* [4] */
+ __IO uint32_t txfflsh : 1; /* [5] */
+ __IO uint32_t txfnum : 5; /* [10:6] */
+ __IO uint32_t reserved2 : 20; /* [30:11] */
+ __IO uint32_t ahbidle : 1; /* [31] */
+ } grstctl_bit;
+ };
+
+ /**
+ * @brief otgfs core interrupt register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t gintsts;
+ struct
+ {
+ __IO uint32_t curmode : 1; /* [0] */
+ __IO uint32_t modemis : 1; /* [1] */
+ __IO uint32_t otgint : 1; /* [2] */
+ __IO uint32_t sof : 1; /* [3] */
+ __IO uint32_t rxflvl : 1; /* [4] */
+ __IO uint32_t nptxfemp : 1; /* [5] */
+ __IO uint32_t ginnakeff : 1; /* [6] */
+ __IO uint32_t goutnakeff : 1; /* [7] */
+ __IO uint32_t reserved1 : 2; /* [9:8]] */
+ __IO uint32_t erlysusp : 1; /* [10] */
+ __IO uint32_t usbsusp : 1; /* [11] */
+ __IO uint32_t usbrst : 1; /* [12] */
+ __IO uint32_t enumdone : 1; /* [13] */
+ __IO uint32_t isooutdrop : 1; /* [14] */
+ __IO uint32_t eopf : 1; /* [15] */
+ __IO uint32_t reserved2 : 2; /* [17:16]] */
+ __IO uint32_t ieptint : 1; /* [18] */
+ __IO uint32_t oeptint : 1; /* [19] */
+ __IO uint32_t incompisoin : 1; /* [20] */
+ __IO uint32_t incompip_incompisoout : 1; /* [21] */
+ __IO uint32_t reserved3 : 2; /* [23:22] */
+ __IO uint32_t prtint : 1; /* [24] */
+ __IO uint32_t hchint : 1; /* [25] */
+ __IO uint32_t ptxfemp : 1; /* [26] */
+ __IO uint32_t reserved4 : 1; /* [27] */
+ __IO uint32_t conidschg : 1; /* [28] */
+ __IO uint32_t disconint : 1; /* [29] */
+ __IO uint32_t reserved5 : 1; /* [30] */
+ __IO uint32_t wkupint : 1; /* [31] */
+ } gintsts_bit;
+ };
+
+ /**
+ * @brief otgfs interrupt mask register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t gintmsk;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t modemismsk : 1; /* [1] */
+ __IO uint32_t otgintmsk : 1; /* [2] */
+ __IO uint32_t sofmsk : 1; /* [3] */
+ __IO uint32_t rxflvlmsk : 1; /* [4] */
+ __IO uint32_t nptxfempmsk : 1; /* [5] */
+ __IO uint32_t ginnakeffmsk : 1; /* [6] */
+ __IO uint32_t goutnakeffmsk : 1; /* [7] */
+ __IO uint32_t reserved2 : 2; /* [9:8]] */
+ __IO uint32_t erlysuspmsk : 1; /* [10] */
+ __IO uint32_t usbsuspmsk : 1; /* [11] */
+ __IO uint32_t usbrstmsk : 1; /* [12] */
+ __IO uint32_t enumdonemsk : 1; /* [13] */
+ __IO uint32_t isooutdropmsk : 1; /* [14] */
+ __IO uint32_t eopfmsk : 1; /* [15] */
+ __IO uint32_t reserved3 : 2; /* [17:16]] */
+ __IO uint32_t ieptintmsk : 1; /* [18] */
+ __IO uint32_t oeptintmsk : 1; /* [19] */
+ __IO uint32_t incompisoinmsk : 1; /* [20] */
+ __IO uint32_t incompip_incompisooutmsk : 1; /* [21] */
+ __IO uint32_t reserved4 : 2; /* [23:22] */
+ __IO uint32_t prtintmsk : 1; /* [24] */
+ __IO uint32_t hchintmsk : 1; /* [25] */
+ __IO uint32_t ptxfempmsk : 1; /* [26] */
+ __IO uint32_t reserved5 : 1; /* [27] */
+ __IO uint32_t conidschgmsk : 1; /* [28] */
+ __IO uint32_t disconintmsk : 1; /* [29] */
+ __IO uint32_t reserved6 : 1; /* [30] */
+ __IO uint32_t wkupintmsk : 1; /* [31] */
+ } gintmsk_bit;
+ };
+
+ /**
+ * @brief otgfs rx status debug read register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t grxstsr;
+ struct
+ {
+ __IO uint32_t eptnum : 4; /* [3:0] */
+ __IO uint32_t bcnt : 11; /* [14:4] */
+ __IO uint32_t dpid : 2; /* [16:15] */
+ __IO uint32_t pktsts : 4; /* [20:17] */
+ __IO uint32_t fn : 4; /* [24:21] */
+ __IO uint32_t reserved1 : 7; /* [31:25] */
+ } grxstsr_bit;
+ };
+
+ /**
+ * @brief otgfs rx status read and pop register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t grxstsp;
+ struct
+ {
+ __IO uint32_t chnum : 4; /* [3:0] */
+ __IO uint32_t bcnt : 11; /* [14:4] */
+ __IO uint32_t dpid : 2; /* [16:15] */
+ __IO uint32_t pktsts : 4; /* [20:17] */
+ __IO uint32_t reserved1 : 11; /* [31:21] */
+ } grxstsp_bit;
+ };
+
+ /**
+ * @brief otgfs rx fifo size register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t grxfsiz;
+ struct
+ {
+ __IO uint32_t rxfdep : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } grxfsiz_bit;
+ };
+
+ /**
+ * @brief otgfs non-periodic and ept0 tx fifo size register, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t gnptxfsiz_ept0tx;
+ struct
+ {
+ __IO uint32_t nptxfstaddr : 16; /* [15:0] */
+ __IO uint32_t nptxfdep : 16; /* [31:16] */
+ } gnptxfsiz_ept0tx_bit;
+ };
+
+ /**
+ * @brief otgfs non-periodic tx fifo request queue status register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t gnptxsts;
+ struct
+ {
+ __IO uint32_t nptxfspcavail : 16; /* [15:0] */
+ __IO uint32_t nptxqspcavail : 8; /* [23:16] */
+ __IO uint32_t nptxqtop : 7; /* [30:24] */
+ } gnptxsts_bit;
+ };
+
+ __IO uint32_t reserved2[2];
+
+ /**
+ * @brief otgfs general core configuration register, offset:0x38
+ */
+ union
+ {
+ __IO uint32_t gccfg;
+ struct
+ {
+ __IO uint32_t reserved1 : 16; /* [15:0] */
+ __IO uint32_t pwrdown : 1; /* [16] */
+ __IO uint32_t lp_mode : 1; /* [17] */
+ __IO uint32_t reserved2 : 2; /* [19:18] */
+ __IO uint32_t sofouten : 1; /* [20] */
+ __IO uint32_t vbusig : 1; /* [21] */
+ __IO uint32_t reserved3 : 10; /* [31:22] */
+ } gccfg_bit;
+ };
+
+ /**
+ * @brief otgfs core id register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t guid;
+ struct
+ {
+ __IO uint32_t userid : 32; /* [31:0] */
+ } guid_bit;
+ };
+
+ __IO uint32_t reserved3[48];
+
+ /**
+ * @brief otgfs host periodic tx fifo size register, offset:0x100
+ */
+ union
+ {
+ __IO uint32_t hptxfsiz;
+ struct
+ {
+ __IO uint32_t ptxfstaddr : 16; /* [15:0] */
+ __IO uint32_t ptxfsize : 16; /* [31:16] */
+ } hptxfsiz_bit;
+ };
+
+ /**
+ * @brief otgfs host periodic tx fifo size register, offset:0x100
+ */
+ union
+ {
+ __IO uint32_t dieptxfn[7];
+ struct
+ {
+ __IO uint32_t ineptxfstaddr : 16; /* [15:0] */
+ __IO uint32_t ineptxfdep : 16; /* [31:16] */
+ } dieptxfn_bit[7];
+ };
+} otg_global_type;
+
+
+typedef struct
+{
+ /**
+ * @brief otgfs host mode configuration register, offset:0x400
+ */
+ union
+ {
+ __IO uint32_t hcfg;
+ struct
+ {
+ __IO uint32_t fslspclksel : 2; /* [1:0] */
+ __IO uint32_t fslssupp : 1; /* [2] */
+ __IO uint32_t reserved1 : 29; /* [31:3] */
+ } hcfg_bit;
+ };
+
+ /**
+ * @brief otgfs host frame interval register, offset:0x404
+ */
+ union
+ {
+ __IO uint32_t hfir;
+ struct
+ {
+ __IO uint32_t frint : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:15] */
+ } hfir_bit;
+ };
+
+ /**
+ * @brief otgfs host frame number and time remaining register, offset:0x408
+ */
+ union
+ {
+ __IO uint32_t hfnum;
+ struct
+ {
+ __IO uint32_t frnum : 16; /* [15:0] */
+ __IO uint32_t ftrem : 16; /* [31:15] */
+ } hfnum_bit;
+ };
+
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief otgfs host periodic tx fifo request queue register, offset:0x410
+ */
+ union
+ {
+ __IO uint32_t hptxsts;
+ struct
+ {
+ __IO uint32_t ptxfspcavil : 16; /* [15:0] */
+ __IO uint32_t ptxqspcavil : 8; /* [23:16] */
+ __IO uint32_t ptxqtop : 8; /* [31:24] */
+ } hptxsts_bit;
+ };
+
+ /**
+ * @brief otgfs host all channel interrupt register, offset:0x414
+ */
+ union
+ {
+ __IO uint32_t haint;
+ struct
+ {
+ __IO uint32_t haint : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [32:16] */
+ } haint_bit;
+ };
+
+ /**
+ * @brief otgfs host all channel interrupt mask register, offset:0x418
+ */
+ union
+ {
+ __IO uint32_t haintmsk;
+ struct
+ {
+ __IO uint32_t haintmsk : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [32:16] */
+ } haintmsk_bit;
+ };
+
+ __IO uint32_t reserved2[9];
+
+ /**
+ * @brief otgfs host port control and status register, offset:0x440
+ */
+ union
+ {
+ __IO uint32_t hprt;
+ struct
+ {
+ __IO uint32_t prtconsts : 1; /* [0] */
+ __IO uint32_t prtcondet : 1; /* [1] */
+ __IO uint32_t prtena : 1; /* [2] */
+ __IO uint32_t prtenchng : 1; /* [3] */
+ __IO uint32_t prtovrcact : 1; /* [4] */
+ __IO uint32_t prtovrcchng : 1; /* [5] */
+ __IO uint32_t prtres : 1; /* [6] */
+ __IO uint32_t prtsusp : 1; /* [7] */
+ __IO uint32_t prtrst : 1; /* [8] */
+ __IO uint32_t reserved1 : 1; /* [9] */
+ __IO uint32_t prtlnsts : 2; /* [11:10] */
+ __IO uint32_t prtpwr : 1; /* [12] */
+ __IO uint32_t prttsctl : 4; /* [16:13] */
+ __IO uint32_t prtspd : 2; /* [18:17] */
+ __IO uint32_t reserved2 : 13; /* [31:19] */
+
+ } hprt_bit;
+ };
+} otg_host_type;
+
+typedef struct
+{
+ /**
+ * @brief otgfs host channel x characterisic register, offset:0x500
+ */
+ union
+ {
+ __IO uint32_t hcchar;
+ struct
+ {
+ __IO uint32_t mps : 11; /* [10:0] */
+ __IO uint32_t eptnum : 4; /* [14:11] */
+ __IO uint32_t eptdir : 1; /* [15] */
+ __IO uint32_t reserved1 : 1; /* [16] */
+ __IO uint32_t lspddev : 1; /* [17] */
+ __IO uint32_t eptype : 2; /* [19:18] */
+ __IO uint32_t mc : 2; /* [21:20] */
+ __IO uint32_t devaddr : 7; /* [28:22] */
+ __IO uint32_t oddfrm : 1; /* [29] */
+ __IO uint32_t chdis : 1; /* [30] */
+ __IO uint32_t chena : 1; /* [31] */
+ } hcchar_bit;
+ };
+
+ /**
+ * @brief otgfs host channel split control register, offset:0x504
+ */
+ union
+ {
+ __IO uint32_t hcsplt;
+ struct
+ {
+ __IO uint32_t prtaddr : 7; /* [6:0] */
+ __IO uint32_t hubaddr : 7; /* [13:7] */
+ __IO uint32_t xactpos : 2; /* [15:14] */
+ __IO uint32_t compsplt : 1; /* [16] */
+ __IO uint32_t reserved1 : 14; /* [30:17] */
+ __IO uint32_t spltena : 1; /* [31] */
+ } hcsplt_bit;
+ };
+
+ /**
+ * @brief otgfs host channel interrupt register, offset:0x508
+ */
+ union
+ {
+ __IO uint32_t hcint;
+ struct
+ {
+ __IO uint32_t xferc : 1; /* [0] */
+ __IO uint32_t chhltd : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t stall : 1; /* [3] */
+ __IO uint32_t nak : 1; /* [4] */
+ __IO uint32_t ack : 1; /* [5] */
+ __IO uint32_t reserved2 : 1; /* [6] */
+ __IO uint32_t xacterr : 1; /* [7] */
+ __IO uint32_t bblerr : 1; /* [8] */
+ __IO uint32_t frmovrun : 1; /* [9] */
+ __IO uint32_t dtglerr : 1; /* [10] */
+ __IO uint32_t reserved3 : 21; /* [31:11] */
+ } hcint_bit;
+ };
+
+ /**
+ * @brief otgfs host channel interrupt mask register, offset:0x50C
+ */
+ union
+ {
+ __IO uint32_t hcintmsk;
+ struct
+ {
+ __IO uint32_t xfercmsk : 1; /* [0] */
+ __IO uint32_t chhltdmsk : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t stallmsk : 1; /* [3] */
+ __IO uint32_t nakmsk : 1; /* [4] */
+ __IO uint32_t ackmsk : 1; /* [5] */
+ __IO uint32_t reserved2 : 1; /* [6] */
+ __IO uint32_t xacterrmsk : 1; /* [7] */
+ __IO uint32_t bblerrmsk : 1; /* [8] */
+ __IO uint32_t frmovrunmsk : 1; /* [9] */
+ __IO uint32_t dtglerrmsk : 1; /* [10] */
+ __IO uint32_t reserved3 : 21; /* [31:11] */
+ } hcintmsk_bit;
+ };
+
+ /**
+ * @brief otgfs host channel transfer size register, offset:0x510
+ */
+ union
+ {
+ __IO uint32_t hctsiz;
+ struct
+ {
+ __IO uint32_t xfersize : 19; /* [18:0] */
+ __IO uint32_t pktcnt : 10; /* [28:19] */
+ __IO uint32_t pid : 2; /* [30:29] */
+ __IO uint32_t reserved1 : 1; /* [31] */
+ } hctsiz_bit;
+ };
+ __IO uint32_t reserved3[3];
+
+}otg_hchannel_type;
+
+
+typedef struct
+{
+ /**
+ * @brief otgfs device configuration register, offset:0x800
+ */
+ union
+ {
+ __IO uint32_t dcfg;
+ struct
+ {
+ __IO uint32_t devspd : 2; /* [1:0] */
+ __IO uint32_t nzstsouthshk : 1; /* [2] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t devaddr : 7; /* [10:4] */
+ __IO uint32_t perfrint : 2; /* [12:11] */
+ __IO uint32_t reserved2 : 19; /* [31:13] */
+ } dcfg_bit;
+ };
+
+ /**
+ * @brief otgfs device controls register, offset:0x804
+ */
+ union
+ {
+ __IO uint32_t dctl;
+ struct
+ {
+ __IO uint32_t rwkupsig : 1; /* [0] */
+ __IO uint32_t sftdiscon : 1; /* [1] */
+ __IO uint32_t gnpinnaksts : 1; /* [2] */
+ __IO uint32_t goutnaksts : 1; /* [3] */
+ __IO uint32_t tstctl : 3; /* [6:4] */
+ __IO uint32_t sgnpinak : 1; /* [7] */
+ __IO uint32_t cgnpinak : 1; /* [8] */
+ __IO uint32_t sgoutnak : 1; /* [9] */
+ __IO uint32_t cgoutnak : 1; /* [10] */
+ __IO uint32_t pwroprgdne : 1; /* [11] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } dctl_bit;
+ };
+
+ /**
+ * @brief otgfs device status register, offset:0x80C
+ */
+ union
+ {
+ __IO uint32_t dsts;
+ struct
+ {
+ __IO uint32_t suspsts : 1; /* [0] */
+ __IO uint32_t enumspd : 2; /* [2:1] */
+ __IO uint32_t eticerr : 1; /* [3] */
+ __IO uint32_t reserved1 : 4; /* [7:4] */
+ __IO uint32_t soffn : 14; /* [21:8] */
+ __IO uint32_t reserved2 : 10; /* [31:22] */
+ } dsts_bit;
+ };
+
+ __IO uint32_t reserved1;
+ /**
+ * @brief otgfs device in endpoint general interrupt mask register, offset:0x810
+ */
+ union
+ {
+ __IO uint32_t diepmsk;
+ struct
+ {
+ __IO uint32_t xfercmsk : 1; /* [0] */
+ __IO uint32_t eptdismsk : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t timeoutmsk : 1; /* [3] */
+ __IO uint32_t intkntxfempmsk : 1; /* [4] */
+ __IO uint32_t intkneptmismsk : 1; /* [5] */
+ __IO uint32_t ineptnakmsk : 1; /* [6] */
+ __IO uint32_t reserved2 : 1; /* [7] */
+ __IO uint32_t txfifoudrmsk : 1; /* [8] */
+ __IO uint32_t bnainmsk : 1; /* [9] */
+ __IO uint32_t reserved3 : 22; /* [31:10] */
+ } diepmsk_bit;
+ };
+
+ /**
+ * @brief otgfs device out endpoint general interrupt mask register, offset:0x814
+ */
+ union
+ {
+ __IO uint32_t doepmsk;
+ struct
+ {
+ __IO uint32_t xfercmsk : 1; /* [0] */
+ __IO uint32_t eptdismsk : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t setupmsk : 1; /* [3] */
+ __IO uint32_t outtepdmsk : 1; /* [4] */
+ __IO uint32_t reserved2 : 1; /* [5] */
+ __IO uint32_t b2bsetupmsk : 1; /* [6] */
+ __IO uint32_t reserved3 : 1; /* [7] */
+ __IO uint32_t outperrmsk : 1; /* [8] */
+ __IO uint32_t bnaoutmsk : 1; /* [9] */
+ __IO uint32_t reserved4 : 22; /* [31:10] */
+ } doepmsk_bit;
+ };
+
+ /**
+ * @brief otgfs device all endpoint interrupt register, offset:0x818
+ */
+ union
+ {
+ __IO uint32_t daint;
+ struct
+ {
+ __IO uint32_t ineptint : 16; /* [15:0] */
+ __IO uint32_t outeptint : 16; /* [31:16] */
+ } daint_bit;
+ };
+
+ /**
+ * @brief otgfs device all endpoint interrupt mask register, offset:0x81C
+ */
+ union
+ {
+ __IO uint32_t daintmsk;
+ struct
+ {
+ __IO uint32_t ineptmsk : 16; /* [15:0] */
+ __IO uint32_t outeptmsk : 16; /* [31:16] */
+ } daintmsk_bit;
+ };
+
+ __IO uint32_t reserved2[5];
+
+ /**
+ * @brief otgfs device in endpoint fifo empty interrupt mask register, offset:0x834
+ */
+ union
+ {
+ __IO uint32_t diepempmsk;
+ struct
+ {
+ __IO uint32_t ineptxfemsk : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } diepempmsk_bit;
+ };
+
+} otg_device_type;
+
+typedef struct
+{
+ /**
+ * @brief otgfs device out endpoint control register, offset:0x900
+ */
+ union
+ {
+ __IO uint32_t diepctl;
+ struct
+ {
+ __IO uint32_t mps : 11; /* [10:0] */
+ __IO uint32_t reserved1 : 4; /* [14:11] */
+ __IO uint32_t usbacept : 1; /* [15] */
+ __IO uint32_t dpid : 1; /* [16] */
+ __IO uint32_t naksts : 1; /* [17] */
+ __IO uint32_t eptype : 2; /* [19:18] */
+ __IO uint32_t reserved2 : 1; /* [20] */
+ __IO uint32_t stall : 1; /* [21] */
+ __IO uint32_t txfnum : 4; /* [25:22] */
+ __IO uint32_t cnak : 1; /* [26] */
+ __IO uint32_t snak : 1; /* [27] */
+ __IO uint32_t setd0pid : 1; /* [28] */
+ __IO uint32_t setd1pid : 1; /* [29] */
+ __IO uint32_t eptdis : 1; /* [30] */
+ __IO uint32_t eptena : 1; /* [31] */
+ } diepctl_bit;
+ };
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief otgfs device in endpoint interrupt register, offset:0x908
+ */
+ union
+ {
+ __IO uint32_t diepint;
+ struct
+ {
+ __IO uint32_t xferc : 1; /* [0] */
+ __IO uint32_t epdisd : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t timeout : 1; /* [3] */
+ __IO uint32_t intkntxfemp : 1; /* [4] */
+ __IO uint32_t reserved2 : 1; /* [5] */
+ __IO uint32_t ineptnak : 1; /* [6] */
+ __IO uint32_t txfemp : 1; /* [7] */
+ __IO uint32_t reserved3 : 24; /* [31:8] */
+ } diepint_bit;
+ };
+ __IO uint32_t reserved2;
+
+ /**
+ * @brief otgfs device in endpoint transfer size register, offset:0x910 + endpoint number * 0x20
+ */
+ union
+ {
+ __IO uint32_t dieptsiz;
+ struct
+ {
+ __IO uint32_t xfersize : 19; /* [18:0] */
+ __IO uint32_t pktcnt : 10; /* [28:19] */
+ __IO uint32_t mc : 2; /* [30:29] */
+ __IO uint32_t reserved1 : 1; /* [31] */
+ } dieptsiz_bit;
+ };
+
+ __IO uint32_t reserved3;
+
+ /**
+ * @brief otgfs device in endpoint tx fifo status register, offset:0x918 + endpoint number * 0x20
+ */
+ union
+ {
+ __IO uint32_t dtxfsts;
+ struct
+ {
+ __IO uint32_t ineptxfsav : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } dtxfsts_bit;
+ };
+
+} otg_eptin_type;
+
+typedef struct
+{
+ /**
+ * @brief otgfs device out endpoint control register, offset:0xb00 + endpoint number * 0x20
+ */
+ union
+ {
+ __IO uint32_t doepctl;
+ struct
+ {
+ __IO uint32_t mps : 11; /* [10:0] */
+ __IO uint32_t reserved1 : 4; /* [14:11] */
+ __IO uint32_t usbacept : 1; /* [15] */
+ __IO uint32_t dpid : 1; /* [16] */
+ __IO uint32_t naksts : 1; /* [17] */
+ __IO uint32_t eptype : 2; /* [19:18] */
+ __IO uint32_t snpm : 1; /* [20] */
+ __IO uint32_t stall : 1; /* [21] */
+ __IO uint32_t reserved2 : 4; /* [25:22] */
+ __IO uint32_t cnak : 1; /* [26] */
+ __IO uint32_t snak : 1; /* [27] */
+ __IO uint32_t setd0pid : 1; /* [28] */
+ __IO uint32_t setd1pid : 1; /* [29] */
+ __IO uint32_t eptdis : 1; /* [30] */
+ __IO uint32_t eptena : 1; /* [31] */
+ } doepctl_bit;
+ };
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief otgfs device out endpoint interrupt register, offset:0xb08 + endpoint number * 0x20
+ */
+ union
+ {
+ __IO uint32_t doepint;
+ struct
+ {
+ __IO uint32_t xferc : 1; /* [0] */
+ __IO uint32_t epdisd : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t setup : 1; /* [3] */
+ __IO uint32_t outtepd : 1; /* [4] */
+ __IO uint32_t reserved2 : 1; /* [5] */
+ __IO uint32_t b2pstup : 1; /* [6] */
+ __IO uint32_t reserved3 : 25; /* [31:7] */
+ } doepint_bit;
+ };
+ __IO uint32_t reserved2;
+
+ /**
+ * @brief otgfs device out endpoint transfer size register, offset:0xb10 + endpoint number * 0x20
+ */
+ union
+ {
+ __IO uint32_t doeptsiz;
+ struct
+ {
+ __IO uint32_t xfersize : 19; /* [18:0] */
+ __IO uint32_t pktcnt : 10; /* [28:19] */
+ __IO uint32_t rxdpid_setupcnt : 2; /* [30:29] */
+ __IO uint32_t reserved1 : 1; /* [31] */
+ } doeptsiz_bit;
+ };
+} otg_eptout_type;
+
+typedef struct
+{
+ /**
+ * @brief otgfs power and clock gating control registers, offset:0xe00
+ */
+ union
+ {
+ __IO uint32_t pcgcctl;
+ struct
+ {
+ __IO uint32_t stoppclk : 1; /* [0] */
+ __IO uint32_t reserved1 : 3; /* [3:1] */
+ __IO uint32_t suspendm : 1; /* [4] */
+ __IO uint32_t reserved2 : 27; /* [31:5] */
+ } pcgcctl_bit;
+ };
+} otg_pcgcctl_type;
+
+/**
+ * @}
+ */
+
+/** @defgroup USB_exported_functions
+ * @{
+ */
+
+/**
+ * @brief usb host and device offset address
+ */
+#define OTG_HOST_ADDR_OFFSET 0x400 /*!< usb host register offset address */
+#define OTG_HOST_CHANNEL_ADDR_OFFSET 0x500 /*!< usb host channel register offset address */
+#define OTG_DEVICE_ADDR_OFFSET 0x800 /*!< usb device register offset address */
+#define OTG_DEVICE_EPTIN_ADDR_OFFSET 0x900 /*!< usb device endpoint in register offset address */
+#define OTG_DEVICE_EPTOUT_ADDR_OFFSET 0xB00 /*!< usb device endpoint out register offset address */
+#define OTG_PCGCCTL_ADDR_OFFSET 0xE00 /*!< usb power and clock control register offset address */
+#define OTG_FIFO_ADDR_OFFSET 0x1000 /*!< usb fifo offset address */
+
+/**
+ * @brief usb host and device register define
+ */
+#define OTG1_GLOBAL ((otg_global_type *)(OTGFS1_BASE)) /*!< usb otg1 global register */
+#define OTG2_GLOBAL ((otg_global_type *)(OTGFS2_BASE)) /*!< usb otg2 global register */
+#define OTG_PCGCCTL(usbx) ((otg_pcgcctl_type *)((uint32_t)usbx + OTG_PCGCCTL_ADDR_OFFSET)) /*!< usb power and clock control register */
+#define OTG_DEVICE(usbx) ((otg_device_type *)((uint32_t)usbx + OTG_DEVICE_ADDR_OFFSET)) /*!< usb device register */
+#define OTG_HOST(usbx) ((otg_host_type *)((uint32_t)usbx + OTG_HOST_ADDR_OFFSET)) /*!< usb host register */
+#define USB_CHL(usbx, n) ((otg_hchannel_type *)((uint32_t)usbx + OTG_HOST_CHANNEL_ADDR_OFFSET + n * 0x20)) /*!< usb channel n register */
+#define USB_INEPT(usbx, eptn) ((otg_eptin_type *)((uint32_t)usbx + OTG_DEVICE_EPTIN_ADDR_OFFSET + eptn * 0x20)) /*!< usb device endpoint in register */
+#define USB_OUTEPT(usbx, eptn) ((otg_eptout_type *)((uint32_t)usbx + OTG_DEVICE_EPTOUT_ADDR_OFFSET + eptn * 0x20)) /*!< usb device endpoint out register */
+#define USB_FIFO(usbx, eptn) *(__IO uint32_t *)((uint32_t)usbx + OTG_FIFO_ADDR_OFFSET + eptn * 0x1000) /*!< usb fifo address */
+
+
+
+typedef otg_global_type usb_reg_type;
+
+/** @defgroup USB_exported_functions
+ * @{
+ */
+
+#ifdef OTGFS_USB_GLOBAL
+error_status usb_global_reset(otg_global_type *usbx);
+void usb_global_init(otg_global_type *usbx);
+otg_global_type *usb_global_select_core(uint8_t usb_id);
+void usb_flush_tx_fifo(otg_global_type *usbx, uint32_t fifo_num);
+void usb_flush_rx_fifo(otg_global_type *usbx);
+void usb_global_interrupt_enable(otg_global_type *usbx, uint16_t interrupt, confirm_state new_state);
+uint32_t usb_global_get_all_interrupt(otg_global_type *usbx);
+void usb_global_clear_interrupt(otg_global_type *usbx, uint32_t flag);
+void usb_interrupt_enable(otg_global_type *usbx);
+void usb_interrupt_disable(otg_global_type *usbx);
+void usb_set_rx_fifo(otg_global_type *usbx, uint16_t size);
+void usb_set_tx_fifo(otg_global_type *usbx, uint8_t txfifo, uint16_t size);
+void usb_global_set_mode(otg_global_type *usbx, uint32_t mode);
+void usb_global_power_on(otg_global_type *usbx);
+void usb_write_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uint16_t nbytes);
+void usb_read_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uint16_t nbytes);
+void usb_stop_phy_clk(otg_global_type *usbx);
+void usb_open_phy_clk(otg_global_type *usbx);
+#endif
+
+#ifdef OTGFS_USB_DEVICE
+void usb_ept_open(otg_global_type *usbx, usb_ept_info *ept_info);
+void usb_ept_close(otg_global_type *usbx, usb_ept_info *ept_info);
+void usb_ept_stall(otg_global_type *usbx, usb_ept_info *ept_info);
+void usb_ept_clear_stall(otg_global_type *usbx, usb_ept_info *ept_info);
+uint32_t usb_get_all_out_interrupt(otg_global_type *usbx);
+uint32_t usb_get_all_in_interrupt(otg_global_type *usbx);
+uint32_t usb_ept_out_interrupt(otg_global_type *usbx, uint32_t eptn);
+uint32_t usb_ept_in_interrupt(otg_global_type *usbx, uint32_t eptn);
+void usb_ept_out_clear(otg_global_type *usbx, uint32_t eptn, uint32_t flag);
+void usb_ept_in_clear(otg_global_type *usbx, uint32_t eptn, uint32_t flag);
+void usb_set_address(otg_global_type *usbx, uint8_t address);
+void usb_ept0_start(otg_global_type *usbx);
+void usb_ept0_setup(otg_global_type *usbx);
+void usb_connect(otg_global_type *usbx);
+void usb_disconnect(otg_global_type *usbx);
+void usb_remote_wkup_set(otg_global_type *usbx);
+void usb_remote_wkup_clear(otg_global_type *usbx);
+uint8_t usb_suspend_status_get(otg_global_type *usbx);
+#endif
+
+#ifdef OTGFS_USB_HOST
+void usb_port_power_on(otg_global_type *usbx, confirm_state state);
+uint32_t usbh_get_frame(otg_global_type *usbx);
+void usb_hc_enable(otg_global_type *usbx,
+ uint8_t chn,
+ uint8_t ept_num,
+ uint8_t dev_address,
+ uint8_t type,
+ uint8_t maxpacket,
+ uint8_t speed);
+uint32_t usb_hch_read_interrupt(otg_global_type *usbx);
+void usb_host_disable(otg_global_type *usbx);
+void usb_hch_halt(otg_global_type *usbx, uint8_t chn);
+void usbh_fsls_clksel(otg_global_type *usbx, uint8_t clk);
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_wdt.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_wdt.h
new file mode 100644
index 0000000..e217c84
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_wdt.h
@@ -0,0 +1,197 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_wdt.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 wdt header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_WDT_H
+#define __AT32F435_437_WDT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup WDT
+ * @{
+ */
+
+
+/** @defgroup WDT_flags_definition
+ * @brief wdt flag
+ * @{
+ */
+
+#define WDT_DIVF_UPDATE_FLAG ((uint16_t)0x0001) /*!< wdt division value update complete flag */
+#define WDT_RLDF_UPDATE_FLAG ((uint16_t)0x0002) /*!< wdt reload value update complete flag */
+#define WDT_WINF_UPDATE_FLAG ((uint16_t)0x0004) /*!< wdt window value update complete flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup WDT_exported_types
+ * @{
+ */
+
+/**
+ * @brief wdt division value type
+ */
+typedef enum
+{
+ WDT_CLK_DIV_4 = 0x00, /*!< wdt clock divider value is 4 */
+ WDT_CLK_DIV_8 = 0x01, /*!< wdt clock divider value is 8 */
+ WDT_CLK_DIV_16 = 0x02, /*!< wdt clock divider value is 16 */
+ WDT_CLK_DIV_32 = 0x03, /*!< wdt clock divider value is 32 */
+ WDT_CLK_DIV_64 = 0x04, /*!< wdt clock divider value is 64 */
+ WDT_CLK_DIV_128 = 0x05, /*!< wdt clock divider value is 128 */
+ WDT_CLK_DIV_256 = 0x06 /*!< wdt clock divider value is 256 */
+} wdt_division_type;
+
+/**
+ * @brief wdt cmd value type
+ */
+typedef enum
+{
+ WDT_CMD_LOCK = 0x0000, /*!< disable write protection command */
+ WDT_CMD_UNLOCK = 0x5555, /*!< enable write protection command */
+ WDT_CMD_ENABLE = 0xCCCC, /*!< enable wdt command */
+ WDT_CMD_RELOAD = 0xAAAA /*!< reload command */
+} wdt_cmd_value_type;
+
+/**
+ * @brief type define wdt register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief wdt cmd register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t cmd;
+ struct
+ {
+ __IO uint32_t cmd : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cmd_bit;
+ };
+
+ /**
+ * @brief wdt div register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t div;
+ struct
+ {
+ __IO uint32_t div : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 29;/* [31:3] */
+ } div_bit;
+ };
+
+ /**
+ * @brief wdt rld register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t rld;
+ struct
+ {
+ __IO uint32_t rld : 12;/* [11:0] */
+ __IO uint32_t reserved1 : 20;/* [31:12] */
+ } rld_bit;
+ };
+
+ /**
+ * @brief wdt sts register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t divf : 1; /* [0] */
+ __IO uint32_t rldf : 1; /* [1] */
+ __IO uint32_t reserved1 : 30;/* [31:2] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief wdt win register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t win;
+ struct
+ {
+ __IO uint32_t win : 12;/* [11:0] */
+ __IO uint32_t reserved1 : 20;/* [31:12] */
+ } win_bit;
+ };
+} wdt_type;
+
+/**
+ * @}
+ */
+
+#define WDT ((wdt_type *) WDT_BASE)
+
+/** @defgroup WDT_exported_functions
+ * @{
+ */
+
+void wdt_enable(void);
+void wdt_counter_reload(void);
+void wdt_reload_value_set(uint16_t reload_value);
+void wdt_divider_set(wdt_division_type division);
+void wdt_register_write_enable( confirm_state new_state);
+flag_status wdt_flag_get(uint16_t wdt_flag);
+void wdt_window_counter_set(uint16_t window_cnt);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_wwdt.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_wwdt.h
new file mode 100644
index 0000000..01ab449
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_wwdt.h
@@ -0,0 +1,158 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_wwdt.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 wwdt header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_WWDT_H
+#define __AT32F435_437_WWDT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup WWDT
+ * @{
+ */
+
+/** @defgroup WWDT_enable_bit_definition
+ * @brief wwdt enable bit
+ * @{
+ */
+
+#define WWDT_EN_BIT ((uint32_t)0x00000080) /*!< wwdt enable bit */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDT_exported_types
+ * @{
+ */
+
+/**
+ * @brief wwdt division type
+ */
+typedef enum
+{
+ WWDT_PCLK1_DIV_4096 = 0x00, /*!< wwdt counter clock = (pclk1/4096)/1) */
+ WWDT_PCLK1_DIV_8192 = 0x01, /*!< wwdt counter clock = (pclk1/4096)/2) */
+ WWDT_PCLK1_DIV_16384 = 0x02, /*!< wwdt counter clock = (pclk1/4096)/4) */
+ WWDT_PCLK1_DIV_32768 = 0x03 /*!< wwdt counter clock = (pclk1/4096)/8) */
+} wwdt_division_type;
+
+/**
+ * @brief type define wwdt register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief wwdt ctrl register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t cnt : 7; /* [6:0] */
+ __IO uint32_t wwdten : 1; /* [7] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief wwdt cfg register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t cfg;
+ struct
+ {
+ __IO uint32_t win : 7; /* [6:0] */
+ __IO uint32_t div : 2; /* [8:7] */
+ __IO uint32_t rldien : 1; /* [9] */
+ __IO uint32_t reserved1 : 22;/* [31:10] */
+ } cfg_bit;
+ };
+
+ /**
+ * @brief wwdt cfg register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t rldf : 1; /* [0] */
+ __IO uint32_t reserved1 : 31;/* [31:1] */
+ } sts_bit;
+ };
+
+} wwdt_type;
+
+/**
+ * @}
+ */
+
+#define WWDT ((wwdt_type *) WWDT_BASE)
+
+/** @defgroup WWDT_exported_functions
+ * @{
+ */
+
+void wwdt_reset(void);
+void wwdt_divider_set(wwdt_division_type division);
+void wwdt_flag_clear(void);
+void wwdt_enable(uint8_t wwdt_cnt);
+void wwdt_interrupt_enable(void);
+flag_status wwdt_flag_get(void);
+void wwdt_counter_set(uint8_t wwdt_cnt);
+void wwdt_window_counter_set(uint8_t window_cnt);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_xmc.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_xmc.h
new file mode 100644
index 0000000..1c9bbca
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include/at32f435_437_xmc.h
@@ -0,0 +1,1075 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_xmc.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 xmc header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_XMC_H
+#define __AT32F435_437_XMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @addtogroup XMC
+ * @{
+ */
+
+/** @defgroup XMC_exported_types
+ * @{
+ */
+
+/**
+ * @brief xmc data address bus multiplexing type
+ */
+typedef enum
+{
+ XMC_DATA_ADDR_MUX_DISABLE = 0x00000000, /*!< xmc address/data multiplexing disable */
+ XMC_DATA_ADDR_MUX_ENABLE = 0x00000002 /*!< xmc address/data multiplexing enable */
+} xmc_data_addr_mux_type;
+
+/**
+ * @brief xmc burst access mode type
+ */
+typedef enum
+{
+ XMC_BURST_MODE_DISABLE = 0x00000000, /*!< xmc burst mode disable */
+ XMC_BURST_MODE_ENABLE = 0x00000100 /*!< xmc burst mode enable */
+} xmc_burst_access_mode_type;
+
+/**
+ * @brief xmc asynchronous wait type
+ */
+typedef enum
+{
+ XMC_ASYN_WAIT_DISABLE = 0x00000000, /*!< xmc wait signal during asynchronous transfers disbale */
+ XMC_ASYN_WAIT_ENABLE = 0x00008000 /*!< xmc wait signal during asynchronous transfers enable */
+} xmc_asyn_wait_type;
+
+/**
+ * @brief xmc wrapped mode type
+ */
+typedef enum
+{
+ XMC_WRAPPED_MODE_DISABLE = 0x00000000, /*!< xmc direct wrapped burst is disbale */
+ XMC_WRAPPED_MODE_ENABLE = 0x00000400 /*!< xmc direct wrapped burst is enable */
+} xmc_wrap_mode_type;
+
+/**
+ * @brief xmc write operation type
+ */
+typedef enum
+{
+ XMC_WRITE_OPERATION_DISABLE = 0x00000000, /*!< xmc write operations is disable */
+ XMC_WRITE_OPERATION_ENABLE = 0x00001000 /*!< xmc write operations is enable */
+} xmc_write_operation_type;
+
+/**
+ * @brief xmc wait signal type
+ */
+typedef enum
+{
+ XMC_WAIT_SIGNAL_DISABLE = 0x00000000, /*!< xmc nwait signal is disable */
+ XMC_WAIT_SIGNAL_ENABLE = 0x00002000 /*!< xmc nwait signal is enable */
+} xmc_wait_signal_type;
+
+/**
+ * @brief xmc write burst type
+ */
+typedef enum
+{
+ XMC_WRITE_BURST_SYN_DISABLE = 0x00000000, /*!< xmc write operations are always performed in asynchronous mode */
+ XMC_WRITE_BURST_SYN_ENABLE = 0x00080000 /*!< xmc write operations are performed in synchronous mode */
+} xmc_write_burst_type;
+
+/**
+ * @brief xmc extended mode type
+ */
+typedef enum
+{
+ XMC_WRITE_TIMING_DISABLE = 0x00000000, /*!< xmc write timing disable */
+ XMC_WRITE_TIMING_ENABLE = 0x00004000 /*!< xmc write timing enable */
+} xmc_extended_mode_type;
+
+/**
+ * @brief xmc pccard wait type
+ */
+typedef enum
+{
+ XMC_WAIT_OPERATION_DISABLE = 0x00000000, /*!< xmc wait operation for the pc card/nand flash memory bank disable */
+ XMC_WAIT_OPERATION_ENABLE = 0x00000002 /*!< xmc wait operation for the pc card/nand flash memory bank enable */
+} xmc_nand_pccard_wait_type;
+
+/**
+ * @brief xmc ecc enable type
+ */
+typedef enum
+{
+ XMC_ECC_OPERATION_DISABLE = 0x00000000, /*!< xmc ecc module disable */
+ XMC_ECC_OPERATION_ENABLE = 0x00000040 /*!< xmc ecc module enable */
+} xmc_ecc_enable_type;
+
+/**
+ * @brief xmc nor/sram subbank type
+ */
+typedef enum
+{
+ XMC_BANK1_NOR_SRAM1 = 0x00000000, /*!< xmc nor/sram subbank1 */
+ XMC_BANK1_NOR_SRAM2 = 0x00000001, /*!< xmc nor/sram subbank2 */
+ XMC_BANK1_NOR_SRAM3 = 0x00000002, /*!< xmc nor/sram subbank3 */
+ XMC_BANK1_NOR_SRAM4 = 0x00000003 /*!< xmc nor/sram subbank4 */
+} xmc_nor_sram_subbank_type;
+
+/**
+ * @brief xmc class bank type
+ */
+typedef enum
+{
+ XMC_BANK2_NAND = 0x00000000, /*!< xmc nand flash bank2 */
+ XMC_BANK3_NAND = 0x00000001, /*!< xmc nand flash bank3 */
+ XMC_BANK4_PCCARD = 0x00000002, /*!< xmc pc card bank4 */
+ XMC_BANK5_6_SDRAM = 0x00000003 /*!< xmc sdram bank5/6 */
+} xmc_class_bank_type;
+
+/**
+ * @brief xmc memory type
+ */
+typedef enum
+{
+ XMC_DEVICE_SRAM = 0x00000000, /*!< xmc device choice sram */
+ XMC_DEVICE_PSRAM = 0x00000004, /*!< xmc device choice psram */
+ XMC_DEVICE_NOR = 0x00000008 /*!< xmc device choice nor flash */
+} xmc_memory_type;
+
+/**
+ * @brief xmc data width type
+ */
+typedef enum
+{
+ XMC_BUSTYPE_8_BITS = 0x00000000, /*!< xmc databuss width 8bits */
+ XMC_BUSTYPE_16_BITS = 0x00000010 /*!< xmc databuss width 16bits */
+} xmc_data_width_type;
+
+/**
+ * @brief xmc wait signal polarity type
+ */
+typedef enum
+{
+ XMC_WAIT_SIGNAL_LEVEL_LOW = 0x00000000, /*!< xmc nwait active low */
+ XMC_WAIT_SIGNAL_LEVEL_HIGH = 0x00000200 /*!< xmc nwait active high */
+} xmc_wait_signal_polarity_type;
+
+/**
+ * @brief xmc wait timing type
+ */
+typedef enum
+{
+ XMC_WAIT_SIGNAL_SYN_BEFORE = 0x00000000, /*!< xmc nwait signal is active one data cycle before wait state */
+ XMC_WAIT_SIGNAL_SYN_DURING = 0x00000800 /*!< xmc nwait signal is active during wait state */
+} xmc_wait_timing_type;
+
+/**
+ * @brief xmc access mode type
+ */
+typedef enum
+{
+ XMC_ACCESS_MODE_A = 0x00000000, /*!< xmc access mode A */
+ XMC_ACCESS_MODE_B = 0x10000000, /*!< xmc access mode B */
+ XMC_ACCESS_MODE_C = 0x20000000, /*!< xmc access mode C */
+ XMC_ACCESS_MODE_D = 0x30000000 /*!< xmc access mode D */
+} xmc_access_mode_type;
+
+/**
+ * @brief xmc ecc page size type
+ */
+typedef enum
+{
+ XMC_ECC_PAGESIZE_256_BYTES = 0x00000000, /*!< xmc ecc page size 256 bytes */
+ XMC_ECC_PAGESIZE_512_BYTES = 0x00020000, /*!< xmc ecc page size 512 bytes */
+ XMC_ECC_PAGESIZE_1024_BYTES = 0x00040000, /*!< xmc ecc page size 1024 bytes */
+ XMC_ECC_PAGESIZE_2048_BYTES = 0x00060000, /*!< xmc ecc page size 2048 bytes */
+ XMC_ECC_PAGESIZE_4096_BYTES = 0x00080000, /*!< xmc ecc page size 4096 bytes */
+ XMC_ECC_PAGESIZE_8192_BYTES = 0x000A0000 /*!< xmc ecc page size 8192 bytes */
+} xmc_ecc_pagesize_type;
+
+/**
+ * @brief xmc interrupt sources type
+ */
+typedef enum
+{
+ XMC_INT_RISING_EDGE = 0x00000008, /*!< xmc rising edge detection interrupt enable */
+ XMC_INT_LEVEL = 0x00000010, /*!< xmc high-level edge detection interrupt enable */
+ XMC_INT_FALLING_EDGE = 0x00000020, /*!< xmc falling edge detection interrupt enable */
+ XMC_INT_ERR = 0x00004000 /*!< xmc sdram error interrupt enable */
+} xmc_interrupt_sources_type;
+
+/**
+ * @brief xmc interrupt flag type
+ */
+typedef enum
+{
+ XMC_RISINGEDGE_FLAG = 0x00000001, /*!< xmc interrupt rising edge detection flag */
+ XMC_LEVEL_FLAG = 0x00000002, /*!< xmc interrupt high-level edge detection flag */
+ XMC_FALLINGEDGE_FLAG = 0x00000004, /*!< xmc interrupt falling edge detection flag */
+ XMC_FEMPT_FLAG = 0x00000040, /*!< xmc fifo empty flag */
+ XMC_ERR_FLAG = 0x00000001, /*!< xmc sdram error flag */
+ XMC_BUSY_FLAG = 0x00000020 /*!< xmc sdram busy flag */
+} xmc_interrupt_flag_type;
+
+/**
+ * @brief xmc sdram number of column address type
+ */
+typedef enum
+{
+ XMC_COLUMN_8 = 0x00000000, /*!< xmc sdram column address 8bit */
+ XMC_COLUMN_9 = 0x00000001, /*!< xmc sdram column address 9bit */
+ XMC_COLUMN_10 = 0x00000002, /*!< xmc sdram column address 10bit */
+ XMC_COLUMN_11 = 0x00000003 /*!< xmc sdram column address 11bit */
+}xmc_sdram_column_type;
+
+/**
+ * @brief xmc sdram number of row address type
+ */
+typedef enum
+{
+ XMC_ROW_11 = 0x00000000, /*!< xmc sdram row address 11bit */
+ XMC_ROW_12 = 0x00000001, /*!< xmc sdram row address 12bit */
+ XMC_ROW_13 = 0x00000002 /*!< xmc sdram row address 13bit */
+}xmc_sdram_row_type;
+
+/**
+ * @brief xmc sdram memory data bus width type
+ */
+typedef enum
+{
+ XMC_MEM_WIDTH_8 = 0x00000000, /*!< xmc sdram data bus width 8 */
+ XMC_MEM_WIDTH_16 = 0x00000001 /*!< xmc sdram data bus width 16 */
+}xmc_sdram_width_type;
+
+/**
+ * @brief xmc sdram number of internal banks type
+ */
+typedef enum
+{
+ XMC_INBK_2 = 0x00000000, /*!< xmc sdram 2 internal banks */
+ XMC_INBK_4 = 0x00000001 /*!< xmc sdram 4 internal banks */
+}xmc_sdram_inbk_type;
+
+/**
+ * @brief xmc sdram cas latency type
+ */
+typedef enum
+{
+ XMC_CAS_1 = 0x00000001, /*!< xmc sdram cas 1 */
+ XMC_CAS_2 = 0x00000002, /*!< xmc sdram cas 2 */
+ XMC_CAS_3 = 0x00000003 /*!< xmc sdram cas 3 */
+}xmc_sdram_cas_type;
+
+/**
+ * @brief xmc sdram clock div type
+ */
+typedef enum
+{
+ XMC_NO_CLK = 0x00000000, /*!< xmc sdram disable clock */
+ XMC_CLKDIV_2 = 0x00000002, /*!< xmc sdram clock div 2 */
+ XMC_CLKDIV_3 = 0x00000003, /*!< xmc sdram clock div 3 */
+ XMC_CLKDIV_4 = 0x00000001 /*!< xmc sdram clock div 4 */
+}xmc_sdram_clkdiv_type;
+
+/**
+ * @brief xmc sdram read delay
+ */
+typedef enum
+{
+ XMC_READ_DELAY_0 = 0x00000000, /*!< xmc sdram no delay */
+ XMC_READ_DELAY_1 = 0x00000001, /*!< xmc sdram delay 1 clock*/
+ XMC_READ_DELAY_2 = 0x00000002, /*!< xmc sdram delay 2 clock */
+}xmc_sdram_rd_delay_type;
+
+/**
+ * @brief xmc sdram bank type
+ */
+typedef enum
+{
+ XMC_SDRAM_BANK1 = 0x00000000, /*!< xmc sdram bank 1 */
+ XMC_SDRAM_BANK2 = 0x00000001 /*!< xmc sdram bank 2 */
+}xmc_sdram_bank_type;
+
+
+/**
+ * @brief xmc sdram timing delay cycle type
+ */
+typedef enum
+{
+ XMC_DELAY_CYCLE_1 = 0x00000000, /*!< xmc sdram timming delay 1 cycle */
+ XMC_DELAY_CYCLE_2 = 0x00000001, /*!< xmc sdram timming delay 2 cycle */
+ XMC_DELAY_CYCLE_3 = 0x00000002, /*!< xmc sdram timming delay 3 cycle */
+ XMC_DELAY_CYCLE_4 = 0x00000003, /*!< xmc sdram timming delay 4 cycle */
+ XMC_DELAY_CYCLE_5 = 0x00000004, /*!< xmc sdram timming delay 5 cycle */
+ XMC_DELAY_CYCLE_6 = 0x00000005, /*!< xmc sdram timming delay 6 cycle */
+ XMC_DELAY_CYCLE_7 = 0x00000006, /*!< xmc sdram timming delay 7 cycle */
+ XMC_DELAY_CYCLE_8 = 0x00000007, /*!< xmc sdram timming delay 8 cycle */
+ XMC_DELAY_CYCLE_9 = 0x00000008, /*!< xmc sdram timming delay 9 cycle */
+ XMC_DELAY_CYCLE_10 = 0x00000009, /*!< xmc sdram timming delay 10 cycle */
+ XMC_DELAY_CYCLE_11 = 0x0000000A, /*!< xmc sdram timming delay 11 cycle */
+ XMC_DELAY_CYCLE_12 = 0x0000000B, /*!< xmc sdram timming delay 12 cycle */
+ XMC_DELAY_CYCLE_13 = 0x0000000C, /*!< xmc sdram timming delay 13 cycle */
+ XMC_DELAY_CYCLE_14 = 0x0000000D, /*!< xmc sdram timming delay 14 cycle */
+ XMC_DELAY_CYCLE_15 = 0x0000000E, /*!< xmc sdram timming delay 15 cycle */
+ XMC_DELAY_CYCLE_16 = 0x0000000F /*!< xmc sdram timming delay 16 cycle */
+}xmc_sdram_delay_type;
+
+
+/**
+ * @brief xmc sdram command type
+ */
+typedef enum
+{
+ XMC_CMD_NORMAL = 0x00000000, /*!< xmc sdram command normal */
+ XMC_CMD_CLK = 0x00000001, /*!< xmc sdram command clock enable */
+ XMC_CMD_PRECHARG_ALL = 0x00000002, /*!< xmc sdram command precharg all bank */
+ XMC_CMD_AUTO_REFRESH = 0x00000003, /*!< xmc sdram command auto refresh */
+ XMC_CMD_LOAD_MODE = 0x00000004, /*!< xmc sdram command load mode register */
+ XMC_CMD_SELF_REFRESH = 0x00000005, /*!< xmc sdram command self refresh */
+ XMC_CMD_POWER_DOWN = 0x00000006 /*!< xmc sdram command power down */
+}xmc_command_type;
+
+/**
+ * @brief xmc sdram command bank select type
+ */
+typedef enum
+{
+ XMC_CMD_BANK1 = 0x00000010, /*!< send xmc sdram command to bank1 */
+ XMC_CMD_BANK2 = 0x00000008, /*!< send xmc sdram command to bank2 */
+ XMC_CMD_BANK1_2 = 0x00000018 /*!< send xmc sdram command to bank1 and bank2 */
+}xmc_cmd_bank1_2_type;
+
+
+/**
+ * @brief xmc sdram bank status type
+ */
+typedef enum
+{
+ XMC_STATUS_NORMAL = 0x00000000, /*!< xmc sdram status normal */
+ XMC_STATUS_SELF_REFRESH = 0x00000001, /*!< xmc sdram status self refresh */
+ XMC_STATUS_POWER_DOWN = 0x00000002, /*!< xmc sdram power down */
+ XMC_STATUS_MASK = 0x00000003 /*!< xmc sdram mask */
+}xmc_bank_status_type;
+
+
+/**
+ * @brief nor/sram banks timing parameters
+ */
+typedef struct
+{
+ xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
+ xmc_extended_mode_type write_timing_enable; /*!< xmc nor/sram write timing enable */
+ uint32_t addr_setup_time; /*!< xmc nor/sram address setup time */
+ uint32_t addr_hold_time; /*!< xmc nor/sram address hold time */
+ uint32_t data_setup_time; /*!< xmc nor/sram data setup time */
+ uint32_t bus_latency_time; /*!< xmc nor/sram bus latency time */
+ uint32_t clk_psc; /*!< xmc nor/sram clock prescale */
+ uint32_t data_latency_time; /*!< xmc nor/sram data latency time */
+ xmc_access_mode_type mode; /*!< xmc nor/sram access mode */
+} xmc_norsram_timing_init_type;
+
+/**
+ * @brief xmc nor/sram init structure definition
+ */
+typedef struct
+{
+ xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
+ xmc_data_addr_mux_type data_addr_multiplex; /*!< xmc nor/sram address/data multiplexing enable */
+ xmc_memory_type device; /*!< xmc nor/sram memory device */
+ xmc_data_width_type bus_type; /*!< xmc nor/sram data bus width */
+ xmc_burst_access_mode_type burst_mode_enable; /*!< xmc nor/sram burst mode enable */
+ xmc_asyn_wait_type asynwait_enable; /*!< xmc nor/sram nwait in asynchronous transfer enable */
+ xmc_wait_signal_polarity_type wait_signal_lv; /*!< xmc nor/sram nwait polarity */
+ xmc_wrap_mode_type wrapped_mode_enable; /*!< xmc nor/sram wrapped enable */
+ xmc_wait_timing_type wait_signal_config; /*!< xmc nor/sram nwait timing configuration */
+ xmc_write_operation_type write_enable; /*!< xmc nor/sram write enable */
+ xmc_wait_signal_type wait_signal_enable; /*!< xmc nor/sram nwait in synchronous transfer enable */
+ xmc_extended_mode_type write_timing_enable; /*!< xmc nor/sram read-write timing different */
+ xmc_write_burst_type write_burst_syn; /*!< xmc nor/sram memory write mode control */
+} xmc_norsram_init_type;
+
+/**
+ * @brief nand and pccard timing parameters xmc
+ */
+
+typedef struct
+{
+ xmc_class_bank_type class_bank; /*!< xmc nand/pccard bank */
+ uint32_t mem_setup_time; /*!< xmc nand/pccard memory setup time */
+ uint32_t mem_waite_time; /*!< xmc nand/pccard memory wait time */
+ uint32_t mem_hold_time; /*!< xmc nand/pccard memory hold time */
+ uint32_t mem_hiz_time; /*!< xmc nand/pccard memory databus high resistance time */
+} xmc_nand_pccard_timinginit_type;
+
+/**
+ * @brief xmc nand init structure definition
+ */
+
+typedef struct
+{
+ xmc_class_bank_type nand_bank; /*!< xmc nand bank */
+ xmc_nand_pccard_wait_type wait_enable; /*!< xmc wait feature enable */
+ xmc_data_width_type bus_type; /*!< xmc nand bus width */
+ xmc_ecc_enable_type ecc_enable; /*!< xmc nand ecc enable */
+ xmc_ecc_pagesize_type ecc_pagesize; /*!< xmc nand ecc page size */
+ uint32_t delay_time_cycle; /*!< xmc nand cle to re delay */
+ uint32_t delay_time_ar; /*!< xmc nand ale to re delay */
+} xmc_nand_init_type;
+
+/**
+ * @brief xmc pccard init structure definition
+ */
+
+typedef struct
+{
+ xmc_nand_pccard_wait_type enable_wait; /*!< xmc pccard wait feature enable */
+ uint32_t delay_time_cr; /*!< xmc pccard cle to re delay */
+ uint32_t delay_time_ar; /*!< xmc pccard ale to re delay */
+} xmc_pccard_init_type;
+
+/**
+ * @brief xmc sdram init structure definition
+ */
+
+typedef struct
+{
+ xmc_sdram_bank_type sdram_bank; /*!< xmc sdram bank bype */
+ xmc_sdram_inbk_type internel_banks; /*!< xmc sdram internal banks */
+ xmc_sdram_clkdiv_type clkdiv; /*!< xmc sdram clock div */
+ uint8_t write_protection; /*!< xmc sdram write protection */
+ uint8_t burst_read; /*!< xmc sdram burst read */
+ uint8_t read_delay; /*!< xmc sdram read delay */
+ xmc_sdram_column_type column_address; /*!< xmc sdram column address */
+ xmc_sdram_row_type row_address; /*!< xmc sdram row address */
+ xmc_sdram_cas_type cas; /*!< xmc sdram cas */
+ xmc_sdram_width_type width; /*!< xmc sdram data width */
+} xmc_sdram_init_type;
+
+/**
+ * @brief xmc sdram timing structure definition
+ */
+
+typedef struct
+{
+ xmc_sdram_delay_type tmrd; /*!< mode register program to active delay */
+ xmc_sdram_delay_type txsr; /*!< exit self-refresh to active delay */
+ xmc_sdram_delay_type tras; /*!< self refresh */
+ xmc_sdram_delay_type trc; /*!< refresh to active delay */
+ xmc_sdram_delay_type twr; /*!< write recovery delay */
+ xmc_sdram_delay_type trp; /*!< precharge to active delay */
+ xmc_sdram_delay_type trcd; /*!< row active to read/write delay */
+} xmc_sdram_timing_type;
+
+/**
+ * @brief xmc sdram command structure definition
+ */
+
+typedef struct
+{
+ xmc_command_type cmd; /*!< sdram command */
+ xmc_cmd_bank1_2_type cmd_banks; /*!< which bank send command */
+ uint32_t auto_refresh; /*!< auto refresh times */
+ uint32_t data; /*!< mode register data */
+} xmc_sdram_cmd_type;
+
+typedef struct
+{
+ /**
+ * @brief xmc bank1 bk1ctrl register, offset:0x00+0x08*(x-1) x= 1...4
+ */
+ union
+ {
+ __IO uint32_t bk1ctrl;
+ struct
+ {
+ __IO uint32_t en : 1; /* [0] */
+ __IO uint32_t admuxen : 1; /* [1] */
+ __IO uint32_t dev : 2; /* [3:2] */
+ __IO uint32_t extmdbw : 2; /* [5:4] */
+ __IO uint32_t noren : 1; /* [6] */
+ __IO uint32_t reserved1 : 1; /* [7] */
+ __IO uint32_t syncben : 1; /* [8] */
+ __IO uint32_t nwpol : 1; /* [9] */
+ __IO uint32_t wrapen : 1; /* [10] */
+ __IO uint32_t nwtcfg : 1; /* [11] */
+ __IO uint32_t wen : 1; /* [12] */
+ __IO uint32_t nwsen : 1; /* [13] */
+ __IO uint32_t rwtd : 1; /* [14] */
+ __IO uint32_t nwasen : 1; /* [15] */
+ __IO uint32_t crpgs : 3; /* [18:16] */
+ __IO uint32_t mwmc : 1; /* [19] */
+ __IO uint32_t reserved2 : 12;/* [31:20] */
+ } bk1ctrl_bit;
+ };
+
+ /**
+ * @brief xmc bank1 bk1tmg register, offset:0x04+0x08*(x-1) x= 1...4
+ */
+ union
+ {
+ __IO uint32_t bk1tmg;
+ struct
+ {
+ __IO uint32_t addrst : 4; /* [3:0] */
+ __IO uint32_t addrht : 4; /* [7:4] */
+ __IO uint32_t dtst : 8; /* [15:8] */
+ __IO uint32_t buslat : 4; /* [19:16] */
+ __IO uint32_t clkpsc : 4; /* [23:20] */
+ __IO uint32_t dtlat : 4; /* [27:24] */
+ __IO uint32_t asyncm : 2; /* [29:28] */
+ __IO uint32_t reserved1 : 2; /* [31:30] */
+ } bk1tmg_bit;
+ };
+
+} xmc_bank1_ctrl_tmg_reg_type;
+
+typedef struct
+{
+ /**
+ * @brief xmc bank1 bk1tmgwr register, offset:0x104+0x08*(x-1) x= 1...4
+ */
+ union
+ {
+ __IO uint32_t bk1tmgwr;
+ struct
+ {
+ __IO uint32_t addrst : 4; /* [3:0] */
+ __IO uint32_t addrht : 4; /* [7:4] */
+ __IO uint32_t dtst : 8; /* [15:8] */
+ __IO uint32_t buslat : 4; /* [19:16] */
+ __IO uint32_t reserved1 : 8; /* [27:20] */
+ __IO uint32_t asyncm : 2; /* [29:28] */
+ __IO uint32_t reserved2 : 2; /* [31:30] */
+ } bk1tmgwr_bit;
+ };
+
+ /**
+ * @brief xmc bank1 reserved register
+ */
+ __IO uint32_t reserved1;
+
+} xmc_bank1_tmgwr_reg_type;
+
+/**
+ * @brief xmc bank1 registers
+ */
+typedef struct
+{
+ /**
+ * @brief xmc bank1 ctrl and tmg register, offset:0x00~0x1C
+ */
+ xmc_bank1_ctrl_tmg_reg_type ctrl_tmg_group[4];
+
+ /**
+ * @brief xmc bank1 reserved register, offset:0x20~0x100
+ */
+ __IO uint32_t reserved1[57];
+
+ /**
+ * @brief xmc bank1 tmgwr register, offset:0x104~0x11C
+ */
+ xmc_bank1_tmgwr_reg_type tmgwr_group[4];
+
+ /**
+ * @brief xmc bank1 reserved register, offset:0x120~0x21C
+ */
+ __IO uint32_t reserved2[64];
+
+ /**
+ * @brief xmc bank1 ext register, offset:0x220~0x22C
+ */
+ union
+ {
+ __IO uint32_t ext[4];
+ struct
+ {
+ __IO uint32_t buslatw2w : 8; /* [7:0] */
+ __IO uint32_t buslatr2r : 8; /* [15:8] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } ext_bit[4];
+ };
+
+} xmc_bank1_type;
+
+/**
+ * @brief xmc bank2 registers
+ */
+typedef struct
+{
+ /**
+ * @brief xmc bk2ctrl register, offset:0x60
+ */
+ union
+ {
+ __IO uint32_t bk2ctrl;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t nwen : 1; /* [1] */
+ __IO uint32_t en : 1; /* [2] */
+ __IO uint32_t dev : 1; /* [3] */
+ __IO uint32_t extmdbw : 2; /* [5:4] */
+ __IO uint32_t eccen : 1; /* [6] */
+ __IO uint32_t reserved2 : 2; /* [8:7] */
+ __IO uint32_t tcr : 4; /* [12:9] */
+ __IO uint32_t tar : 4; /* [16:13] */
+ __IO uint32_t eccpgs : 3; /* [19:17] */
+ __IO uint32_t reserved3 : 12;/* [31:20] */
+ } bk2ctrl_bit;
+ };
+
+ /**
+ * @brief xmc bk2is register, offset:0x64
+ */
+ union
+ {
+ __IO uint32_t bk2is;
+ struct
+ {
+ __IO uint32_t res : 1; /* [0] */
+ __IO uint32_t hls : 1; /* [1] */
+ __IO uint32_t fes : 1; /* [2] */
+ __IO uint32_t reien : 1; /* [3] */
+ __IO uint32_t hlien : 1; /* [4] */
+ __IO uint32_t feien : 1; /* [5] */
+ __IO uint32_t fifoe : 1; /* [6] */
+ __IO uint32_t reserved1 : 25;/* [31:7] */
+ } bk2is_bit;
+ };
+
+ /**
+ * @brief xmc bk2tmgmem register, offset:0x68
+ */
+ union
+ {
+ __IO uint32_t bk2tmgmem;
+ struct
+ {
+ __IO uint32_t cmst : 8; /* [7:0] */
+ __IO uint32_t cmwt : 8; /* [15:8] */
+ __IO uint32_t cmht : 8; /* [23:16] */
+ __IO uint32_t cmdhizt : 8; /* [31:24] */
+ } bk2tmgmem_bit;
+ };
+
+ /**
+ * @brief xmc bk2tmgatt register, offset:0x6C
+ */
+ union
+ {
+ __IO uint32_t bk2tmgatt;
+ struct
+ {
+ __IO uint32_t amst : 8; /* [7:0] */
+ __IO uint32_t amwt : 8; /* [15:8] */
+ __IO uint32_t amht : 8; /* [23:16] */
+ __IO uint32_t amdhizt : 8; /* [31:24] */
+ } bk2tmgatt_bit;
+ };
+
+ /**
+ * @brief xmc reserved register, offset:0x70
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief xmc bk2ecc register, offset:0x74
+ */
+ union
+ {
+ __IO uint32_t bk2ecc;
+ struct
+ {
+ __IO uint32_t ecc : 32; /* [31:0] */
+ } bk2ecc_bit;
+ };
+
+} xmc_bank2_type;
+
+/**
+ * @brief xmc bank3 registers
+ */
+typedef struct
+{
+ /**
+ * @brief xmc bk3ctrl register, offset:0x80
+ */
+ union
+ {
+ __IO uint32_t bk3ctrl;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t nwen : 1; /* [1] */
+ __IO uint32_t en : 1; /* [2] */
+ __IO uint32_t dev : 1; /* [3] */
+ __IO uint32_t extmdbw : 2; /* [5:4] */
+ __IO uint32_t eccen : 1; /* [6] */
+ __IO uint32_t reserved2 : 2; /* [8:7] */
+ __IO uint32_t tcr : 4; /* [12:9] */
+ __IO uint32_t tar : 4; /* [16:13] */
+ __IO uint32_t eccpgs : 3; /* [19:17] */
+ __IO uint32_t reserved3 : 12;/* [31:20] */
+ } bk3ctrl_bit;
+ };
+
+ /**
+ * @brief xmc bk3is register, offset:0x84
+ */
+ union
+ {
+ __IO uint32_t bk3is;
+ struct
+ {
+ __IO uint32_t res : 1; /* [0] */
+ __IO uint32_t hls : 1; /* [1] */
+ __IO uint32_t fes : 1; /* [2] */
+ __IO uint32_t reien : 1; /* [3] */
+ __IO uint32_t hlien : 1; /* [4] */
+ __IO uint32_t feien : 1; /* [5] */
+ __IO uint32_t fifoe : 1; /* [6] */
+ __IO uint32_t reserved1 : 25;/* [31:7] */
+ } bk3is_bit;
+ };
+
+ /**
+ * @brief xmc bk3tmgmem register, offset:0x88
+ */
+ union
+ {
+ __IO uint32_t bk3tmgmem;
+ struct
+ {
+ __IO uint32_t cmst : 8; /* [7:0] */
+ __IO uint32_t cmwt : 8; /* [15:8] */
+ __IO uint32_t cmht : 8; /* [23:16] */
+ __IO uint32_t cmdhizt : 8; /* [31:24] */
+ } bk3tmgmem_bit;
+ };
+
+ /**
+ * @brief xmc bk3tmgatt register, offset:0x8C
+ */
+ union
+ {
+ __IO uint32_t bk3tmgatt;
+ struct
+ {
+ __IO uint32_t amst : 8; /* [7:0] */
+ __IO uint32_t amwt : 8; /* [15:8] */
+ __IO uint32_t amht : 8; /* [23:16] */
+ __IO uint32_t amdhizt : 8; /* [31:24] */
+ } bk3tmgatt_bit;
+ };
+
+ /**
+ * @brief xmc reserved register, offset:0x90
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief xmc bk3ecc register, offset:0x94
+ */
+ union
+ {
+ __IO uint32_t bk3ecc;
+ struct
+ {
+ __IO uint32_t ecc : 32; /* [31:0] */
+ } bk3ecc_bit;
+ };
+} xmc_bank3_type;
+
+/**
+ * @brief xmc bank4 registers
+ */
+typedef struct
+{
+
+ /**
+ * @brief xmc bk4ctrl register, offset:0xA0
+ */
+ union
+ {
+ __IO uint32_t bk4ctrl;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t nwen : 1; /* [1] */
+ __IO uint32_t en : 1; /* [2] */
+ __IO uint32_t dev : 1; /* [3] */
+ __IO uint32_t extmdbw : 2; /* [5:4] */
+ __IO uint32_t eccen : 1; /* [6] */
+ __IO uint32_t reserved2 : 2; /* [8:7] */
+ __IO uint32_t tcr : 4; /* [12:9] */
+ __IO uint32_t tar : 4; /* [16:13] */
+ __IO uint32_t eccpgs : 3; /* [19:17] */
+ __IO uint32_t reserved3 : 12;/* [31:20] */
+ } bk4ctrl_bit;
+ };
+
+ /**
+ * @brief xmc bk4is register, offset:0xA4
+ */
+ union
+ {
+ __IO uint32_t bk4is;
+ struct
+ {
+ __IO uint32_t res : 1; /* [0] */
+ __IO uint32_t hls : 1; /* [1] */
+ __IO uint32_t fes : 1; /* [2] */
+ __IO uint32_t reien : 1; /* [3] */
+ __IO uint32_t hlien : 1; /* [4] */
+ __IO uint32_t feien : 1; /* [5] */
+ __IO uint32_t fifoe : 1; /* [6] */
+ __IO uint32_t reserved1 : 25;/* [31:7] */
+ } bk4is_bit;
+ };
+
+ /**
+ * @brief xmc bk4tmgmem register, offset:0xA8
+ */
+ union
+ {
+ __IO uint32_t bk4tmgmem;
+ struct
+ {
+ __IO uint32_t cmst : 8; /* [7:0] */
+ __IO uint32_t cmwt : 8; /* [15:8] */
+ __IO uint32_t cmht : 8; /* [23:16] */
+ __IO uint32_t cmdhizt : 8; /* [31:24] */
+ } bk4tmgmem_bit;
+ };
+
+ /**
+ * @brief xmc bk4tmgatt register, offset:0xAC
+ */
+ union
+ {
+ __IO uint32_t bk4tmgatt;
+ struct
+ {
+ __IO uint32_t amst : 8; /* [7:0] */
+ __IO uint32_t amwt : 8; /* [15:8] */
+ __IO uint32_t amht : 8; /* [23:16] */
+ __IO uint32_t amdhizt : 8; /* [31:24] */
+ } bk4tmgatt_bit;
+ };
+
+ /**
+ * @brief xmc bk4tmgio register, offset:0xB0
+ */
+ union
+ {
+ __IO uint32_t bk4tmgio;
+ struct
+ {
+ __IO uint32_t iost : 8; /* [7:0] */
+ __IO uint32_t iowt : 8; /* [15:8] */
+ __IO uint32_t ioht : 8; /* [23:16] */
+ __IO uint32_t iohizt : 8; /* [31:24] */
+ } bk4tmgio_bit;
+ };
+} xmc_bank4_type;
+
+/**
+ * @brief xmc sdram type
+ */
+typedef struct
+{
+ /**
+ * @brief xmc sdram ctrl register, offset:0x140~0x144
+ */
+ union
+ {
+ __IO uint32_t ctrl[2];
+ struct
+ {
+ __IO uint32_t ca : 2; /* [1:0] */
+ __IO uint32_t ra : 2; /* [3:2] */
+ __IO uint32_t db : 2; /* [5:4] */
+ __IO uint32_t inbk : 1; /* [6] */
+ __IO uint32_t cas : 2; /* [8:7] */
+ __IO uint32_t wrp : 1; /* [9] */
+ __IO uint32_t clkdiv : 2; /* [11:10] */
+ __IO uint32_t bstr : 1; /* [12] */
+ __IO uint32_t rd : 2; /* [14:13] */
+ __IO uint32_t reserved1 : 17;/* [31:15] */
+ } ctrl_bit[2];
+ };
+
+ /**
+ * @brief xmc sdram tm register, offset:0x148~0x14C
+ */
+ union
+ {
+ __IO uint32_t tm[2];
+ struct
+ {
+ __IO uint32_t tmrd : 4; /* [3:0] */
+ __IO uint32_t txsr : 4; /* [7:4] */
+ __IO uint32_t tras : 4; /* [11:8] */
+ __IO uint32_t trc : 4; /* [15:12] */
+ __IO uint32_t twr : 4; /* [19:16] */
+ __IO uint32_t trp : 4; /* [23:20] */
+ __IO uint32_t trcd : 4; /* [27:24] */
+ __IO uint32_t reserved1 : 4; /* [31:28] */
+ } tm_bit[2];
+
+ };
+
+/**
+ * @brief xmc sdram cmd register, offset:0x150
+ */
+ union
+ {
+ __IO uint32_t cmd;
+ struct
+ {
+ __IO uint32_t cmd : 3; /* [2:0] */
+ __IO uint32_t bk2 : 1; /* [3] */
+ __IO uint32_t bk1 : 1; /* [4] */
+ __IO uint32_t art : 4; /* [8:5] */
+ __IO uint32_t mrd : 13;/* [21:9] */
+ __IO uint32_t reserved1 : 10;/* [31:22] */
+ } cmd_bit;
+ };
+
+ /**
+ * @brief xmc sdram rcnt register, offset:0x154
+ */
+ union
+ {
+ __IO uint32_t rcnt;
+ struct
+ {
+ __IO uint32_t errc : 1; /* [0] */
+ __IO uint32_t rc : 13;/* [13:1] */
+ __IO uint32_t erien : 1; /* [14] */
+ __IO uint32_t reserved1 : 17;/* [31:15] */
+ } rcnt_bit;
+ };
+
+ /**
+ * @brief xmc sdram sts register, offset:0x158
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t err : 1; /* [0] */
+ __IO uint32_t bk1sts : 2; /* [2:1] */
+ __IO uint32_t bk2sts : 2; /* [4:3] */
+ __IO uint32_t busy : 1; /* [5] */
+ __IO uint32_t reserved1 : 26;/* [31:6] */
+ } sts_bit;
+ };
+}xmc_sdram_type;
+
+/**
+ * @}
+ */
+
+#define XMC_BANK1 ((xmc_bank1_type *) XMC_BANK1_REG_BASE)
+#define XMC_BANK2 ((xmc_bank2_type *) XMC_BANK2_REG_BASE)
+#define XMC_BANK3 ((xmc_bank3_type *) XMC_BANK3_REG_BASE)
+#define XMC_BANK4 ((xmc_bank4_type *) XMC_BANK4_REG_BASE)
+#define XMC_SDRAM ((xmc_sdram_type *) XMC_SDRAM_REG_BASE)
+
+/** @defgroup XMC_exported_functions
+ * @{
+ */
+
+void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank);
+void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct);
+void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
+ xmc_norsram_timing_init_type* xmc_w_timing_struct);
+void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct);
+void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
+ xmc_norsram_timing_init_type* xmc_w_timing_struct);
+void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state);
+void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing);
+void xmc_nand_reset(xmc_class_bank_type xmc_bank);
+void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct);
+void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct);
+void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct);
+void xmc_nand_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct);
+void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
+void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
+uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank);
+void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state);
+flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
+void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
+void xmc_pccard_reset(void);
+void xmc_pccard_init(xmc_pccard_init_type* xmc_pccard_init_struct);
+void xmc_pccard_timing_config(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct);
+void xmc_pccard_default_para_init(xmc_pccard_init_type* xmc_pccard_init_struct);
+void xmc_pccard_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct);
+void xmc_pccard_enable(confirm_state new_state);
+void xmc_sdram_reset(xmc_sdram_bank_type xmc_bank);
+void xmc_sdram_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct);
+void xmc_sdram_default_para_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct);
+void xmc_sdram_cmd(xmc_sdram_cmd_type *xmc_sdram_cmd_struct);
+uint32_t xmc_sdram_status_get(xmc_sdram_bank_type xmc_bank);
+void xmc_sdram_refresh_counter_set(uint32_t counter);
+void xmc_sdram_auto_refresh_set(uint32_t number);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/library.properties b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/library.properties
new file mode 100644
index 0000000..38817f9
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/library.properties
@@ -0,0 +1,9 @@
+name=AT32F43x_StdPeriph_Driver
+version=1.0.0
+author=AT
+maintainer=AT
+sentence=Source files wrapper (HAL, LL,...)
+paragraph=Allow to not archive source object files to core.a. This avoid the linker to select weak definitions instead of non-weak ones when 'whole-archive' option is not used.
+category=Other
+url=
+architectures=at32
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_acc.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_acc.c
new file mode 100644
index 0000000..539623c
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_acc.c
@@ -0,0 +1,231 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_acc.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the acc firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup ACC
+ * @brief ACC driver modules
+ * @{
+ */
+
+#ifdef ACC_MODULE_ENABLED
+
+/** @defgroup ACC_private_functions
+ * @{
+ */
+
+/**
+ * @brief enable or disable the acc calibration mode.
+ * @param acc_trim: specifies the acc calibration type.
+ * this parameter can be one of the following values:
+ * - ACC_CAL_HICKCAL
+ * - ACC_CAL_HICKTRIM
+ * @param new_state: specifies the acc calibration to be enabled or disabled.(TRUE or FALSE)
+ * @retval none
+ */
+void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state)
+{
+ if(acc_trim == ACC_CAL_HICKCAL)
+ {
+ ACC->ctrl1_bit.entrim = FALSE;
+ }
+ else
+ {
+ ACC->ctrl1_bit.entrim = TRUE;
+ }
+ ACC->ctrl1_bit.calon = new_state;
+}
+
+/**
+ * @brief store calibration step data in acc's ctrl1 register.
+ * @param step_value: value to be stored in the acc's ctrl1 register
+ * @retval none
+ */
+void acc_step_set(uint8_t step_value)
+{
+ ACC->ctrl1_bit.step = step_value;
+}
+
+/**
+ * @brief select sof sourse for acc in acc's ctrl1 register.
+ * @param sof_sel: value to be stored in the acc's ctrl1 register
+ * this parameter can be one of the following values:
+ * @arg ACC_SOF_OTG1
+ * @arg ACC_SOF_OTG2
+ * @retval none
+ */
+void acc_sof_select(uint16_t sof_sel)
+{
+ ACC->ctrl1 |= sof_sel;
+}
+
+/**
+ * @brief enable or disable the specified acc interrupts.
+ * @param acc_int: specifies the acc interrupt sources to be enabled or disabled.
+ * this parameter can be one of the following values:
+ * - ACC_CALRDYIEN_INT
+ * - ACC_EIEN_INT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state)
+{
+ if(acc_int == ACC_CALRDYIEN_INT)
+ {
+ ACC->ctrl1_bit.calrdyien = new_state;
+ }
+ else
+ {
+ ACC->ctrl1_bit.eien = new_state;
+ }
+}
+
+/**
+ * @brief return the current acc hicktrim value.
+ * @param none
+ * @retval 8-bit hicktrim value.
+ */
+uint8_t acc_hicktrim_get(void)
+{
+ return ((uint8_t)(ACC->ctrl2_bit.hicktrim));
+}
+
+/**
+ * @brief return the current acc hickcal value.
+ * @param none
+ * @retval 8-bit hicktrim value.
+ */
+uint8_t acc_hickcal_get(void)
+{
+ return ((uint8_t)(ACC->ctrl2_bit.hickcal));
+}
+
+/**
+ * @brief wtire the value to acc c1 register.
+ * @param acc_c1_value
+ * @retval none.
+ */
+void acc_write_c1(uint16_t acc_c1_value)
+{
+ ACC->c1 = acc_c1_value;
+}
+
+/**
+ * @brief wtire the value to acc c2 register.
+ * @param acc_c2_value
+ * @retval none.
+ */
+void acc_write_c2(uint16_t acc_c2_value)
+{
+ ACC->c2 = acc_c2_value;
+}
+
+/**
+ * @brief wtire the value to acc c3 register.
+ * @param acc_c3_value
+ * @retval none.
+ */
+void acc_write_c3(uint16_t acc_c3_value)
+{
+ ACC->c3 = acc_c3_value;
+}
+
+/**
+ * @brief return the current acc c1 value.
+ * @param none
+ * @retval 16-bit c1 value.
+ */
+uint16_t acc_read_c1(void)
+{
+ return ((uint16_t)(ACC->c1));
+}
+
+/**
+ * @brief return the current acc c2 value.
+ * @param none
+ * @retval 16-bit c2 value.
+ */
+uint16_t acc_read_c2(void)
+{
+ return ((uint16_t)(ACC->c2));
+}
+
+/**
+ * @brief return the current acc c3 value.
+ * @param none
+ * @retval 16-bit c3 value.
+ */
+uint16_t acc_read_c3(void)
+{
+ return ((uint16_t)(ACC->c3));
+}
+
+/**
+ * @brief check whether the specified acc flag is set or not.
+ * @param acc_flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - ACC_RSLOST_FLAG
+ * - ACC_CALRDY_FLAG
+ * @retval flag_status (SET or RESET)
+ */
+flag_status acc_flag_get(uint16_t acc_flag)
+{
+ if(acc_flag == ACC_CALRDY_FLAG)
+ return (flag_status)(ACC->sts_bit.calrdy);
+ else
+ return (flag_status)(ACC->sts_bit.rslost);
+}
+
+/**
+ * @brief clear the specified acc flag is set or not.
+ * @param acc_flag: specifies the flag to check.
+ * this parameter can be any combination of the following values:
+ * - ACC_RSLOST_FLAG
+ * - ACC_CALRDY_FLAG
+ * @retval none
+ */
+void acc_flag_clear(uint16_t acc_flag)
+{
+ ACC->sts = ~acc_flag;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_adc.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_adc.c
new file mode 100644
index 0000000..8755c2d
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_adc.c
@@ -0,0 +1,1215 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_adc.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the adc firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup ADC
+ * @brief ADC driver modules
+ * @{
+ */
+
+#ifdef ADC_MODULE_ENABLED
+
+/** @defgroup ADC_private_functions
+ * @{
+ */
+
+/**
+ * @brief deinitialize the adc peripheral registers to their default reset values.
+ * @param none
+ * @retval none
+ */
+void adc_reset(void)
+{
+ crm_periph_reset(CRM_ADC_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_ADC_PERIPH_RESET, FALSE);
+}
+
+/**
+ * @brief enable or disable the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param new_state: new state of a/d converter.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl2_bit.adcen = new_state;
+}
+
+/**
+ * @brief adc base default para init.
+ * @param sequence_mode: set the state of adc sequence mode.
+ * this parameter can be:TRUE or FALSE
+ * @param repeat_mode: set the state of adc repeat conversion mode.
+ * this parameter can be:TRUE or FALSE
+ * @param data_align: set the state of adc data alignment.
+ * this parameter can be one of the following values:
+ * - ADC_RIGHT_ALIGNMENT
+ * - ADC_LEFT_ALIGNMENT
+ * @param ordinary_channel_length: configure the adc ordinary channel sequence length.
+ * this parameter can be:
+ * - (0x1~0xf)
+ * @retval none
+ */
+void adc_base_default_para_init(adc_base_config_type *adc_base_struct)
+{
+ adc_base_struct->sequence_mode = FALSE;
+ adc_base_struct->repeat_mode = FALSE;
+ adc_base_struct->data_align = ADC_RIGHT_ALIGNMENT;
+ adc_base_struct->ordinary_channel_length = 1;
+}
+
+/**
+ * @brief initialize the adc peripheral according to the specified parameters.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param sequence_mode: set the state of adc sequence mode.
+ * this parameter can be:TRUE or FALSE
+ * @param repeat_mode: set the state of adc repeat conversion mode.
+ * this parameter can be:TRUE or FALSE
+ * @param data_align: set the state of adc data alignment.
+ * this parameter can be one of the following values:
+ * - ADC_RIGHT_ALIGNMENT
+ * - ADC_LEFT_ALIGNMENT
+ * @param ordinary_channel_length: configure the adc ordinary channel sequence length.
+ * this parameter can be:
+ * - (0x1~0xf)
+ * @retval none
+ */
+void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct)
+{
+ adc_x->ctrl1_bit.sqen = adc_base_struct->sequence_mode;
+ adc_x->ctrl2_bit.rpen = adc_base_struct->repeat_mode;
+ adc_x->ctrl2_bit.dtalign = adc_base_struct->data_align;
+ adc_x->osq1_bit.oclen = adc_base_struct->ordinary_channel_length - 1;
+}
+
+/**
+ * @brief adc common default para init.
+ * @param combine_mode: configure the adc combine_mode mode.
+ * this parameter can be one of the following values:
+ * - ADC_INDEPENDENT_MODE - ADC_ORDINARY_SMLT_PREEMPT_SMLT_ONESLAVE_MODE - ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_ONESLAVE_MODE
+ * - ADC_PREEMPT_SMLT_ONLY_ONESLAVE_MODE - ADC_ORDINARY_SMLT_ONLY_ONESLAVE_MODE - ADC_ORDINARY_SHIFT_ONLY_ONESLAVE_MODE
+ * - ADC_PREEMPT_INTERLTRIG_ONLY_ONESLAVE_MODE - ADC_ORDINARY_SMLT_PREEMPT_SMLT_TWOSLAVE_MODE - ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_TWOSLAVE_MODE
+ * - ADC_PREEMPT_SMLT_ONLY_TWOSLAVE_MODE - ADC_ORDINARY_SMLT_ONLY_TWOSLAVE_MODE - ADC_ORDINARY_SHIFT_ONLY_TWOSLAVE_MODE
+ * - ADC_PREEMPT_INTERLTRIG_ONLY_TWOSLAVE_MODE
+ * @param div: configure the adc division.
+ * this parameter can be one of the following values:
+ * - ADC_HCLK_DIV_2 - ADC_HCLK_DIV_3 - ADC_HCLK_DIV_4 - ADC_HCLK_DIV_5
+ * - ADC_HCLK_DIV_6 - ADC_HCLK_DIV_7 - ADC_HCLK_DIV_8 - ADC_HCLK_DIV_9
+ * - ADC_HCLK_DIV_10 - ADC_HCLK_DIV_11 - ADC_HCLK_DIV_12 - ADC_HCLK_DIV_13
+ * - ADC_HCLK_DIV_14 - ADC_HCLK_DIV_15 - ADC_HCLK_DIV_16 - ADC_HCLK_DIV_17
+ * @param common_dma_mode: configure the adc common dma mode.
+ * this parameter can be one of the following values:
+ * - ADC_COMMON_DMAMODE_DISABLE
+ * - ADC_COMMON_DMAMODE_1
+ * - ADC_COMMON_DMAMODE_2
+ * - ADC_COMMON_DMAMODE_3
+ * - ADC_COMMON_DMAMODE_4
+ * - ADC_COMMON_DMAMODE_5
+ * @param common_dma_request_repeat_state: set the adc common dma request repeat state.
+ * this parameter can be:TRUE or FALSE
+ * @param sampling_interval: configure the ordinary shifting mode adjacent adc sampling interval.
+ * this parameter can be one of the following values:
+ * - ADC_SAMPLING_INTERVAL_5CYCLES - ADC_SAMPLING_INTERVAL_6CYCLES - ADC_SAMPLING_INTERVAL_7CYCLES - ADC_SAMPLING_INTERVAL_8CYCLES
+ * - ADC_SAMPLING_INTERVAL_9CYCLES - ADC_SAMPLING_INTERVAL_10CYCLES - ADC_SAMPLING_INTERVAL_11CYCLES - ADC_SAMPLING_INTERVAL_12CYCLES
+ * - ADC_SAMPLING_INTERVAL_13CYCLES - ADC_SAMPLING_INTERVAL_14CYCLES - ADC_SAMPLING_INTERVAL_15CYCLES - ADC_SAMPLING_INTERVAL_16CYCLES
+ * - ADC_SAMPLING_INTERVAL_17CYCLES - ADC_SAMPLING_INTERVAL_18CYCLES - ADC_SAMPLING_INTERVAL_19CYCLES - ADC_SAMPLING_INTERVAL_20CYCLES
+ * @param tempervintrv_state: set the adc temperature sensor and vintrv state.
+ * this parameter can be:TRUE or FALSE
+ * @param vbat_state: set the adc voltage battery state.
+ * this parameter can be:TRUE or FALSE
+ * @retval none
+ */
+void adc_common_default_para_init(adc_common_config_type *adc_common_struct)
+{
+ adc_common_struct->combine_mode = ADC_INDEPENDENT_MODE;
+ adc_common_struct->div = ADC_HCLK_DIV_2;
+ adc_common_struct->common_dma_mode = ADC_COMMON_DMAMODE_DISABLE;
+ adc_common_struct->common_dma_request_repeat_state = FALSE;
+ adc_common_struct->sampling_interval = ADC_SAMPLING_INTERVAL_5CYCLES;
+ adc_common_struct->tempervintrv_state = FALSE;
+ adc_common_struct->vbat_state = FALSE;
+}
+
+/**
+ * @brief adc common default para init.
+ * @param combine_mode: configure the adc combine_mode mode.
+ * this parameter can be one of the following values:
+ * - ADC_INDEPENDENT_MODE - ADC_ORDINARY_SMLT_PREEMPT_SMLT_ONESLAVE_MODE - ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_ONESLAVE_MODE
+ * - ADC_PREEMPT_SMLT_ONLY_ONESLAVE_MODE - ADC_ORDINARY_SMLT_ONLY_ONESLAVE_MODE - ADC_ORDINARY_SHIFT_ONLY_ONESLAVE_MODE
+ * - ADC_PREEMPT_INTERLTRIG_ONLY_ONESLAVE_MODE - ADC_ORDINARY_SMLT_PREEMPT_SMLT_TWOSLAVE_MODE - ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_TWOSLAVE_MODE
+ * - ADC_PREEMPT_SMLT_ONLY_TWOSLAVE_MODE - ADC_ORDINARY_SMLT_ONLY_TWOSLAVE_MODE - ADC_ORDINARY_SHIFT_ONLY_TWOSLAVE_MODE
+ * - ADC_PREEMPT_INTERLTRIG_ONLY_TWOSLAVE_MODE
+ * @param div: configure the adc division.
+ * this parameter can be one of the following values:
+ * - ADC_HCLK_DIV_2 - ADC_HCLK_DIV_3 - ADC_HCLK_DIV_4 - ADC_HCLK_DIV_5
+ * - ADC_HCLK_DIV_6 - ADC_HCLK_DIV_7 - ADC_HCLK_DIV_8 - ADC_HCLK_DIV_9
+ * - ADC_HCLK_DIV_10 - ADC_HCLK_DIV_11 - ADC_HCLK_DIV_12 - ADC_HCLK_DIV_13
+ * - ADC_HCLK_DIV_14 - ADC_HCLK_DIV_15 - ADC_HCLK_DIV_16 - ADC_HCLK_DIV_17
+ * @param common_dma_mode: configure the adc common dma mode.
+ * this parameter can be one of the following values:
+ * - ADC_COMMON_DMAMODE_DISABLE
+ * - ADC_COMMON_DMAMODE_1
+ * - ADC_COMMON_DMAMODE_2
+ * - ADC_COMMON_DMAMODE_3
+ * - ADC_COMMON_DMAMODE_4
+ * - ADC_COMMON_DMAMODE_5
+ * @param common_dma_request_repeat_state: set the adc common dma request repeat state.
+ * this parameter can be:TRUE or FALSE
+ * @param sampling_interval: configure the ordinary shifting mode adjacent adc sampling interval.
+ * this parameter can be one of the following values:
+ * - ADC_SAMPLING_INTERVAL_5CYCLES - ADC_SAMPLING_INTERVAL_6CYCLES - ADC_SAMPLING_INTERVAL_7CYCLES - ADC_SAMPLING_INTERVAL_8CYCLES
+ * - ADC_SAMPLING_INTERVAL_9CYCLES - ADC_SAMPLING_INTERVAL_10CYCLES - ADC_SAMPLING_INTERVAL_11CYCLES - ADC_SAMPLING_INTERVAL_12CYCLES
+ * - ADC_SAMPLING_INTERVAL_13CYCLES - ADC_SAMPLING_INTERVAL_14CYCLES - ADC_SAMPLING_INTERVAL_15CYCLES - ADC_SAMPLING_INTERVAL_16CYCLES
+ * - ADC_SAMPLING_INTERVAL_17CYCLES - ADC_SAMPLING_INTERVAL_18CYCLES - ADC_SAMPLING_INTERVAL_19CYCLES - ADC_SAMPLING_INTERVAL_20CYCLES
+ * @param tempervintrv_state: set the adc temperature sensor and vintrv state.
+ * this parameter can be:TRUE or FALSE
+ * @param vbat_state: set the adc voltage battery state.
+ * this parameter can be:TRUE or FALSE
+ * @retval none
+ */
+void adc_common_config(adc_common_config_type *adc_common_struct)
+{
+ ADCCOM->cctrl_bit.mssel = adc_common_struct->combine_mode;
+ ADCCOM->cctrl_bit.adcdiv = adc_common_struct->div;
+ if(adc_common_struct->common_dma_mode & 0x04)
+ {
+ ADCCOM->cctrl_bit.msdmasel_h = TRUE;
+ }
+ else
+ {
+ ADCCOM->cctrl_bit.msdmasel_h = FALSE;
+ }
+ ADCCOM->cctrl_bit.msdmasel_l = adc_common_struct->common_dma_mode &0x03;
+ ADCCOM->cctrl_bit.msdrcen = adc_common_struct->common_dma_request_repeat_state;
+ ADCCOM->cctrl_bit.asisel = adc_common_struct->sampling_interval;
+ ADCCOM->cctrl_bit.itsrven = adc_common_struct->tempervintrv_state;
+ ADCCOM->cctrl_bit.vbaten = adc_common_struct->vbat_state;
+}
+
+/**
+ * @brief set resolution of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param resolution: set the conversion resolution.
+ * this parameter can be one of the following values:
+ * - ADC_RESOLUTION_12B
+ * - ADC_RESOLUTION_10B
+ * - ADC_RESOLUTION_8B
+ * - ADC_RESOLUTION_6B
+ * @retval none
+ */
+void adc_resolution_set(adc_type *adc_x, adc_resolution_type resolution)
+{
+ adc_x->ctrl1_bit.crsel = resolution;
+}
+
+/**
+ * @brief enable or disable the adc voltage battery.
+ * @param new_state: new state of the adc voltage battery.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_voltage_battery_enable(confirm_state new_state)
+{
+ ADCCOM->cctrl_bit.vbaten = new_state;
+}
+
+/**
+ * @brief enable or disable the adc dma transfer.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param new_state: new state of the adc dma transfer.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl2_bit.ocdmaen = new_state;
+}
+
+/**
+ * @brief enable or disable the adc dma request repeat.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param new_state: the adc dma request repeat state.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_dma_request_repeat_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl2_bit.ocdrcen = new_state;
+}
+
+/**
+ * @brief enable or disable the specified adc interrupts.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param adc_int: specifies the adc interrupt sources to be enabled or disabled.
+ * this parameter can be one of the following values:
+ * - ADC_OCCE_INT
+ * - ADC_VMOR_INT
+ * - ADC_PCCE_INT
+ * - ADC_OCCO_INT
+ * @param new_state: new state of the specified adc interrupts.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ {
+ adc_x->ctrl1 |= adc_int;
+ }
+ else if(new_state == FALSE)
+ {
+ adc_x->ctrl1 &= ~adc_int;
+ }
+}
+
+/**
+ * @brief set calibration value of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param adc_calibration_value: calibration value of adc.
+ * this parameter can be:
+ * - (0x00~0x7F)
+ * @retval none
+ */
+void adc_calibration_value_set(adc_type *adc_x, uint8_t adc_calibration_value)
+{
+ adc_x->calval = adc_calibration_value;
+}
+
+/**
+ * @brief initialize calibration register of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @retval none
+ */
+void adc_calibration_init(adc_type *adc_x)
+{
+ adc_x->ctrl2_bit.adcalinit = TRUE;
+}
+
+/**
+ * @brief get calibration register's initialize status of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @retval the new state of reset calibration register status(SET or RESET).
+ */
+flag_status adc_calibration_init_status_get(adc_type *adc_x)
+{
+ if(adc_x->ctrl2_bit.adcalinit)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief start calibration process of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @retval none
+ */
+void adc_calibration_start(adc_type *adc_x)
+{
+ adc_x->ctrl2_bit.adcal = TRUE;
+}
+
+/**
+ * @brief get calibration status of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @retval the new state of calibration status(SET or RESET).
+ */
+flag_status adc_calibration_status_get(adc_type *adc_x)
+{
+ if(adc_x->ctrl2_bit.adcal)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief enable or disable the voltage monitoring on single/all ordinary or preempt channels of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param adc_voltage_monitoring: choose the adc_voltage_monitoring config.
+ * this parameter can be one of the following values:
+ * - ADC_VMONITOR_SINGLE_ORDINARY
+ * - ADC_VMONITOR_SINGLE_PREEMPT
+ * - ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT
+ * - ADC_VMONITOR_ALL_ORDINARY
+ * - ADC_VMONITOR_ALL_PREEMPT
+ * - ADC_VMONITOR_ALL_ORDINARY_PREEMPT
+ * - ADC_VMONITOR_NONE
+ * @retval none
+ */
+void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring)
+{
+ adc_x->ctrl1_bit.ocvmen = FALSE;
+ adc_x->ctrl1_bit.pcvmen = FALSE;
+ adc_x->ctrl1_bit.vmsgen = FALSE;
+ adc_x->ctrl1 |= adc_voltage_monitoring;
+}
+
+/**
+ * @brief set voltage monitoring's high and low thresholds value of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param adc_high_threshold: voltage monitoring's high thresholds value.
+ * this parameter can be:
+ * - (0x000~0xFFF)
+ * @param adc_low_threshold: voltage monitoring's low thresholds value.
+ * this parameter can be:
+ * - (0x000~0xFFF)
+ * @retval none
+ */
+void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold)
+{
+ adc_x->vmhb_bit.vmhb = adc_high_threshold;
+ adc_x->vmlb_bit.vmlb = adc_low_threshold;
+}
+
+/**
+ * @brief select the voltage monitoring's channel of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param adc_channel: select the channel.
+ * this parameter can be one of the following values:
+ * - ADC_CHANNEL_0 - ADC_CHANNEL_1 - ADC_CHANNEL_2 - ADC_CHANNEL_3
+ * - ADC_CHANNEL_4 - ADC_CHANNEL_5 - ADC_CHANNEL_6 - ADC_CHANNEL_7
+ * - ADC_CHANNEL_8 - ADC_CHANNEL_9 - ADC_CHANNEL_10 - ADC_CHANNEL_11
+ * - ADC_CHANNEL_12 - ADC_CHANNEL_13 - ADC_CHANNEL_14 - ADC_CHANNEL_15
+ * - ADC_CHANNEL_16 - ADC_CHANNEL_17 - ADC_CHANNEL_18
+ * @retval none
+ */
+void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel)
+{
+ adc_x->ctrl1_bit.vmcsel = adc_channel;
+}
+
+/**
+ * @brief set ordinary channel's corresponding rank in the sequencer and sample time of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param adc_channel: select the channel.
+ * this parameter can be one of the following values:
+ * - ADC_CHANNEL_0 - ADC_CHANNEL_1 - ADC_CHANNEL_2 - ADC_CHANNEL_3
+ * - ADC_CHANNEL_4 - ADC_CHANNEL_5 - ADC_CHANNEL_6 - ADC_CHANNEL_7
+ * - ADC_CHANNEL_8 - ADC_CHANNEL_9 - ADC_CHANNEL_10 - ADC_CHANNEL_11
+ * - ADC_CHANNEL_12 - ADC_CHANNEL_13 - ADC_CHANNEL_14 - ADC_CHANNEL_15
+ * - ADC_CHANNEL_16 - ADC_CHANNEL_17 - ADC_CHANNEL_18
+ * @param adc_sequence: set rank in the ordinary group sequencer.
+ * this parameter must be:
+ * - between 1 to 16
+ * @param adc_sampletime: set the sampletime of adc channel.
+ * this parameter can be one of the following values:
+ * - ADC_SAMPLETIME_2_5
+ * - ADC_SAMPLETIME_6_5
+ * - ADC_SAMPLETIME_12_5
+ * - ADC_SAMPLETIME_24_5
+ * - ADC_SAMPLETIME_47_5
+ * - ADC_SAMPLETIME_92_5
+ * - ADC_SAMPLETIME_247_5
+ * - ADC_SAMPLETIME_640_5
+ * @retval none
+ */
+void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
+{
+ switch(adc_channel)
+ {
+ case ADC_CHANNEL_0:
+ adc_x->spt2_bit.cspt0 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_1:
+ adc_x->spt2_bit.cspt1 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_2:
+ adc_x->spt2_bit.cspt2 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_3:
+ adc_x->spt2_bit.cspt3 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_4:
+ adc_x->spt2_bit.cspt4 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_5:
+ adc_x->spt2_bit.cspt5 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_6:
+ adc_x->spt2_bit.cspt6 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_7:
+ adc_x->spt2_bit.cspt7 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_8:
+ adc_x->spt2_bit.cspt8 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_9:
+ adc_x->spt2_bit.cspt9 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_10:
+ adc_x->spt1_bit.cspt10 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_11:
+ adc_x->spt1_bit.cspt11 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_12:
+ adc_x->spt1_bit.cspt12 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_13:
+ adc_x->spt1_bit.cspt13 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_14:
+ adc_x->spt1_bit.cspt14 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_15:
+ adc_x->spt1_bit.cspt15 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_16:
+ adc_x->spt1_bit.cspt16 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_17:
+ adc_x->spt1_bit.cspt17 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_18:
+ adc_x->spt1_bit.cspt18 = adc_sampletime;
+ break;
+ default:
+ break;
+ }
+ switch(adc_sequence)
+ {
+ case 1:
+ adc_x->osq3_bit.osn1 = adc_channel;
+ break;
+ case 2:
+ adc_x->osq3_bit.osn2 = adc_channel;
+ break;
+ case 3:
+ adc_x->osq3_bit.osn3 = adc_channel;
+ break;
+ case 4:
+ adc_x->osq3_bit.osn4 = adc_channel;
+ break;
+ case 5:
+ adc_x->osq3_bit.osn5 = adc_channel;
+ break;
+ case 6:
+ adc_x->osq3_bit.osn6 = adc_channel;
+ break;
+ case 7:
+ adc_x->osq2_bit.osn7 = adc_channel;
+ break;
+ case 8:
+ adc_x->osq2_bit.osn8 = adc_channel;
+ break;
+ case 9:
+ adc_x->osq2_bit.osn9 = adc_channel;
+ break;
+ case 10:
+ adc_x->osq2_bit.osn10 = adc_channel;
+ break;
+ case 11:
+ adc_x->osq2_bit.osn11 = adc_channel;
+ break;
+ case 12:
+ adc_x->osq2_bit.osn12 = adc_channel;
+ break;
+ case 13:
+ adc_x->osq1_bit.osn13 = adc_channel;
+ break;
+ case 14:
+ adc_x->osq1_bit.osn14 = adc_channel;
+ break;
+ case 15:
+ adc_x->osq1_bit.osn15 = adc_channel;
+ break;
+ case 16:
+ adc_x->osq1_bit.osn16 = adc_channel;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief set preempt channel lenghth of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param adc_channel_lenght: set the adc preempt channel lenghth.
+ * this parameter can be:
+ * - (0x1~0x4)
+ * @retval none
+ */
+void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght)
+{
+ adc_x->psq_bit.pclen = adc_channel_lenght - 1;
+}
+
+/**
+ * @brief configure preempt channel's corresponding rank in the sequencer and sample time of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param adc_channel: select the channel.
+ * this parameter can be one of the following values:
+ * - ADC_CHANNEL_0 - ADC_CHANNEL_1 - ADC_CHANNEL_2 - ADC_CHANNEL_3
+ * - ADC_CHANNEL_4 - ADC_CHANNEL_5 - ADC_CHANNEL_6 - ADC_CHANNEL_7
+ * - ADC_CHANNEL_8 - ADC_CHANNEL_9 - ADC_CHANNEL_10 - ADC_CHANNEL_11
+ * - ADC_CHANNEL_12 - ADC_CHANNEL_13 - ADC_CHANNEL_14 - ADC_CHANNEL_15
+ * - ADC_CHANNEL_16 - ADC_CHANNEL_17 - ADC_CHANNEL_18
+ * @param adc_sequence: set rank in the preempt group sequencer.
+ * this parameter must be:
+ * - between 1 to 4
+ * @param adc_sampletime: config the sampletime of adc channel.
+ * this parameter can be one of the following values:
+ * - ADC_SAMPLETIME_2_5
+ * - ADC_SAMPLETIME_6_5
+ * - ADC_SAMPLETIME_12_5
+ * - ADC_SAMPLETIME_24_5
+ * - ADC_SAMPLETIME_47_5
+ * - ADC_SAMPLETIME_92_5
+ * - ADC_SAMPLETIME_247_5
+ * - ADC_SAMPLETIME_640_5
+ * @retval none
+ */
+void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
+{
+ uint16_t sequence_index=0;
+ switch(adc_channel)
+ {
+ case ADC_CHANNEL_0:
+ adc_x->spt2_bit.cspt0 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_1:
+ adc_x->spt2_bit.cspt1 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_2:
+ adc_x->spt2_bit.cspt2 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_3:
+ adc_x->spt2_bit.cspt3 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_4:
+ adc_x->spt2_bit.cspt4 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_5:
+ adc_x->spt2_bit.cspt5 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_6:
+ adc_x->spt2_bit.cspt6 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_7:
+ adc_x->spt2_bit.cspt7 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_8:
+ adc_x->spt2_bit.cspt8 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_9:
+ adc_x->spt2_bit.cspt9 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_10:
+ adc_x->spt1_bit.cspt10 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_11:
+ adc_x->spt1_bit.cspt11 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_12:
+ adc_x->spt1_bit.cspt12 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_13:
+ adc_x->spt1_bit.cspt13 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_14:
+ adc_x->spt1_bit.cspt14 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_15:
+ adc_x->spt1_bit.cspt15 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_16:
+ adc_x->spt1_bit.cspt16 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_17:
+ adc_x->spt1_bit.cspt17 = adc_sampletime;
+ break;
+ case ADC_CHANNEL_18:
+ adc_x->spt1_bit.cspt18 = adc_sampletime;
+ break;
+ default:
+ break;
+ }
+ sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen;
+ switch(sequence_index)
+ {
+ case 1:
+ adc_x->psq_bit.psn1 = adc_channel;
+ break;
+ case 2:
+ adc_x->psq_bit.psn2 = adc_channel;
+ break;
+ case 3:
+ adc_x->psq_bit.psn3 = adc_channel;
+ break;
+ case 4:
+ adc_x->psq_bit.psn4 = adc_channel;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief set the ordinary channel's external trigger edge and
+ * set external trigger event of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param adc_ordinary_trig: select the external trigger event.
+ * this parameter can be one of the following values:
+ * - ADC_ORDINARY_TRIG_TMR1CH1 - ADC_ORDINARY_TRIG_TMR1CH2 - ADC_ORDINARY_TRIG_TMR1CH3 - ADC_ORDINARY_TRIG_TMR2CH2
+ * - ADC_ORDINARY_TRIG_TMR2CH3 - ADC_ORDINARY_TRIG_TMR2CH4 - ADC_ORDINARY_TRIG_TMR2TRGOUT - ADC_ORDINARY_TRIG_TMR3CH1
+ * - ADC_ORDINARY_TRIG_TMR3TRGOUT - ADC_ORDINARY_TRIG_TMR4CH4 - ADC_ORDINARY_TRIG_TMR5CH1 - ADC_ORDINARY_TRIG_TMR5CH2
+ * - ADC_ORDINARY_TRIG_TMR5CH3 - ADC_ORDINARY_TRIG_TMR8CH1 - ADC_ORDINARY_TRIG_TMR8TRGOUT - ADC_ORDINARY_TRIG_EXINT11
+ * - ADC_ORDINARY_TRIG_TMR20TRGOUT - ADC_ORDINARY_TRIG_TMR20TRGOUT2 - ADC_ORDINARY_TRIG_TMR20CH1 - ADC_ORDINARY_TRIG_TMR20CH2
+ * - ADC_ORDINARY_TRIG_TMR20CH3 - ADC_ORDINARY_TRIG_TMR8TRGOUT2 - ADC_ORDINARY_TRIG_TMR1TRGOUT2 - ADC_ORDINARY_TRIG_TMR4TRGOUT
+ * - ADC_ORDINARY_TRIG_TMR6TRGOUT - ADC_ORDINARY_TRIG_TMR3CH4 - ADC_ORDINARY_TRIG_TMR4CH1 - ADC_ORDINARY_TRIG_TMR1TRGOUT
+ * - ADC_ORDINARY_TRIG_TMR2CH1 - ADC_ORDINARY_TRIG_TMR7TRGOUT
+ * @param adc_ordinary_trig_edge: ordinary channel conversion's external_trigger_edge.
+ * this parameter can be one of the following values:
+ * - ADC_ORDINARY_TRIG_EDGE_NONE
+ * - ADC_ORDINARY_TRIG_EDGE_RISING
+ * - ADC_ORDINARY_TRIG_EDGE_FALLING
+ * - ADC_ORDINARY_TRIG_EDGE_RISING_FALLING
+ * @retval none
+ */
+void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, adc_ordinary_trig_edge_type adc_ordinary_trig_edge)
+{
+ if(adc_ordinary_trig > ADC_ORDINARY_TRIG_EXINT11)
+ {
+ adc_x->ctrl2_bit.octesel_h = 1;
+ adc_x->ctrl2_bit.octesel_l = adc_ordinary_trig & 0x0F;
+ }
+ else
+ {
+ adc_x->ctrl2_bit.octesel_h = 0;
+ adc_x->ctrl2_bit.octesel_l = adc_ordinary_trig & 0x0F;
+ }
+ adc_x->ctrl2_bit.ocete = adc_ordinary_trig_edge;
+}
+
+/**
+ * @brief enable or disable the preempt channel's external trigger and
+ * set external trigger event of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param adc_preempt_trig: select the external trigger event.
+ * this parameter can be one of the following values:
+ * - ADC_PREEMPT_TRIG_TMR1CH4 - ADC_PREEMPT_TRIG_TMR1TRGOUT - ADC_PREEMPT_TRIG_TMR2CH1 - ADC_PREEMPT_TRIG_TMR2TRGOUT
+ * - ADC_PREEMPT_TRIG_TMR3CH2 - ADC_PREEMPT_TRIG_TMR3CH4 - ADC_PREEMPT_TRIG_TMR4CH1 - ADC_PREEMPT_TRIG_TMR4CH2
+ * - ADC_PREEMPT_TRIG_TMR4CH3 - ADC_PREEMPT_TRIG_TMR4TRGOUT - ADC_PREEMPT_TRIG_TMR5CH4 - ADC_PREEMPT_TRIG_TMR5TRGOUT
+ * - ADC_PREEMPT_TRIG_TMR8CH2 - ADC_PREEMPT_TRIG_TMR8CH3 - ADC_PREEMPT_TRIG_TMR8CH4 - ADC_PREEMPT_TRIG_EXINT15
+ * - ADC_PREEMPT_TRIG_TMR20TRGOUT - ADC_PREEMPT_TRIG_TMR20TRGOUT2 - ADC_PREEMPT_TRIG_TMR20CH4 - ADC_PREEMPT_TRIG_TMR1TRGOUT2
+ * - ADC_PREEMPT_TRIG_TMR8TRGOUT - ADC_PREEMPT_TRIG_TMR8TRGOUT2 - ADC_PREEMPT_TRIG_TMR3CH3 - ADC_PREEMPT_TRIG_TMR3TRGOUT
+ * - ADC_PREEMPT_TRIG_TMR3CH1 - ADC_PREEMPT_TRIG_TMR6TRGOUT - ADC_PREEMPT_TRIG_TMR4CH4 - ADC_PREEMPT_TRIG_TMR1CH3
+ * - ADC_PREEMPT_TRIG_TMR20CH2 - ADC_PREEMPT_TRIG_TMR7TRGOUT
+ * @param adc_preempt_trig_edge: preempt channel conversion's external_trigger_edge.
+ * this parameter can be one of the following values:
+ * - ADC_PREEMPT_TRIG_EDGE_NONE
+ * - ADC_PREEMPT_TRIG_EDGE_RISING
+ * - ADC_PREEMPT_TRIG_EDGE_FALLING
+ * - ADC_PREEMPT_TRIG_EDGE_RISING_FALLING
+ * @retval none
+ */
+void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, adc_preempt_trig_edge_type adc_preempt_trig_edge)
+{
+ if(adc_preempt_trig > ADC_PREEMPT_TRIG_EXINT15)
+ {
+ adc_x->ctrl2_bit.pctesel_h = 1;
+ adc_x->ctrl2_bit.pctesel_l = adc_preempt_trig & 0x0F;
+ }
+ else
+ {
+ adc_x->ctrl2_bit.pctesel_h = 0;
+ adc_x->ctrl2_bit.pctesel_l = adc_preempt_trig & 0x0F;
+ }
+ adc_x->ctrl2_bit.pcete = adc_preempt_trig_edge;
+}
+
+/**
+ * @brief set preempt channel's conversion value offset of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param adc_preempt_channel: select the preempt channel.
+ * this parameter can be one of the following values:
+ * - ADC_PREEMPT_CHANNEL_1
+ * - ADC_PREEMPT_CHANNEL_2
+ * - ADC_PREEMPT_CHANNEL_3
+ * - ADC_PREEMPT_CHANNEL_4
+ * @param adc_offset_value: set the adc preempt channel's conversion value offset.
+ * this parameter can be:
+ * - (0x000~0xFFF)
+ * @retval none
+ */
+void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value)
+{
+ switch(adc_preempt_channel)
+ {
+ case ADC_PREEMPT_CHANNEL_1:
+ adc_x->pcdto1_bit.pcdto1 = adc_offset_value;
+ break;
+ case ADC_PREEMPT_CHANNEL_2:
+ adc_x->pcdto2_bit.pcdto2 = adc_offset_value;
+ break;
+ case ADC_PREEMPT_CHANNEL_3:
+ adc_x->pcdto3_bit.pcdto3 = adc_offset_value;
+ break;
+ case ADC_PREEMPT_CHANNEL_4:
+ adc_x->pcdto4_bit.pcdto4 = adc_offset_value;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief set partitioned mode channel count of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param adc_channel_count: configure the adc partitioned mode channel count.
+ * this parameter can be:
+ * - (0x1~0x8)
+ * @retval none
+ */
+void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count)
+{
+
+ adc_x->ctrl1_bit.ocpcnt = adc_channel_count - 1;
+}
+
+/**
+ * @brief enable or disable the partitioned mode on ordinary channel of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param new_state: new state of ordinary channel's partitioned mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl1_bit.ocpen = new_state;
+}
+
+/**
+ * @brief enable or disable the partitioned mode on preempt channel of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param new_state: new state of preempt channel's partitioned mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl1_bit.pcpen = new_state;
+}
+
+/**
+ * @brief enable or disable automatic preempt group conversion of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param new_state: new state of automatic preempt group conversion.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl1_bit.pcautoen = new_state;
+}
+
+/**
+ * @brief stop the ongoing conversion of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @retval none
+ */
+void adc_conversion_stop(adc_type *adc_x)
+{
+ adc_x->ctrl2_bit.adabrt = TRUE;
+}
+
+/**
+ * @brief get stop conversion's status of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @retval the new state of stop conversion's status(SET or RESET).
+ */
+flag_status adc_conversion_stop_status_get(adc_type *adc_x)
+{
+ if(adc_x->ctrl2_bit.adabrt)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief enable or disable each ordinary channel conversion set occe flag of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param new_state: new state of each ordinary channel conversion set occe flag.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_occe_each_conversion_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl2_bit.eocsfen = new_state;
+}
+
+/**
+ * @brief enable or disable ordinary software start conversion of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param new_state: new state of ordinary software start conversion.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl2_bit.ocswtrg = new_state;
+}
+
+/**
+ * @brief get ordinary software start conversion status of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @retval the new state of ordinary software start conversion status(SET or RESET).
+ */
+flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x)
+{
+ if(adc_x->ctrl2_bit.ocswtrg)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief enable or disable preempt software start conversion of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param new_state: new state of preempt software start conversion.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl2_bit.pcswtrg = new_state;
+}
+
+/**
+ * @brief get preempt software start conversion status of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @retval the new state of preempt software start conversion status(SET or RESET).
+ */
+flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x)
+{
+ if(adc_x->ctrl2_bit.pcswtrg)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief return the last conversion data for ordinary channel of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @retval the last conversion data for ordinary channel.
+ */
+uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x)
+{
+ return (uint16_t)(adc_x->odt_bit.odt);
+}
+
+/**
+ * @brief return the last ordinary conversion data of combine adc.
+ * @retval the last conversion data for ordinary channel.
+ */
+uint32_t adc_combine_ordinary_conversion_data_get(void)
+{
+ return (uint32_t)(ADCCOM->codt);
+}
+
+/**
+ * @brief return the conversion data for selection preempt channel of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param adc_preempt_channel: select the preempt channel.
+ * this parameter can be one of the following values:
+ * - ADC_PREEMPT_CHANNEL_1
+ * - ADC_PREEMPT_CHANNEL_2
+ * - ADC_PREEMPT_CHANNEL_3
+ * - ADC_PREEMPT_CHANNEL_4
+ * @retval the conversion data for selection preempt channel.
+ */
+uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel)
+{
+ uint16_t preempt_conv_data_index = 0;
+ switch(adc_preempt_channel)
+ {
+ case ADC_PREEMPT_CHANNEL_1:
+ preempt_conv_data_index = (uint16_t)(adc_x->pdt1_bit.pdt1);
+ break;
+ case ADC_PREEMPT_CHANNEL_2:
+ preempt_conv_data_index = (uint16_t)(adc_x->pdt2_bit.pdt2);
+ break;
+ case ADC_PREEMPT_CHANNEL_3:
+ preempt_conv_data_index = (uint16_t)(adc_x->pdt3_bit.pdt3);
+ break;
+ case ADC_PREEMPT_CHANNEL_4:
+ preempt_conv_data_index = (uint16_t)(adc_x->pdt4_bit.pdt4);
+ break;
+ default:
+ break;
+ }
+ return preempt_conv_data_index;
+}
+
+/**
+ * @brief get flag of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param adc_flag: select the adc flag.
+ * this parameter can be one of the following values:
+ * - ADC_VMOR_FLAG
+ * - ADC_OCCE_FLAG
+ * - ADC_PCCE_FLAG
+ * - ADC_PCCS_FLAG(no interrupt associated)
+ * - ADC_OCCS_FLAG(no interrupt associated)
+ * - ADC_OCCO_FLAG
+ * - ADC_RDY_FLAG(no interrupt associated)
+ * @retval the new state of adc flag status(SET or RESET).
+ */
+flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag)
+{
+ flag_status status = RESET;
+
+ if((adc_x->sts & adc_flag) == RESET)
+ {
+ status = RESET;
+ }
+ else
+ {
+ status = SET;
+ }
+ return status;
+}
+
+/**
+ * @brief clear flag of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * ADC1, ADC2, ADC3.
+ * @param adc_flag: select the adc flag.
+ * this parameter can be any combination of the following values:
+ * - ADC_VMOR_FLAG
+ * - ADC_OCCE_FLAG(also can clear by reading the adc_x->odt)
+ * - ADC_PCCE_FLAG
+ * - ADC_PCCS_FLAG
+ * - ADC_OCCS_FLAG
+ * - ADC_OCCO_FLAG
+ * - note:"ADC_RDY_FLAG" cannot be choose!rdy bit is readonly bit,it means the adc is ready to accept conversion request
+ * @retval none
+ */
+void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag)
+{
+ adc_x->sts = ~adc_flag;
+}
+
+/**
+ * @brief enable or disable the ordinary oversampling of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param new_state: new state of ordinary oversampling.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ovsp_bit.oosen = new_state;
+}
+
+/**
+ * @brief enable or disable the preempt oversampling of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param new_state: new state of preempt oversampling.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ovsp_bit.posen = new_state;
+}
+
+/**
+ * @brief config the oversampling ratio and shift of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param adc_oversample_ratio: set the oversample ratio.
+ * this parameter can be one of the following values:
+ * - ADC_OVERSAMPLE_RATIO_2
+ * - ADC_OVERSAMPLE_RATIO_4
+ * - ADC_OVERSAMPLE_RATIO_8
+ * - ADC_OVERSAMPLE_RATIO_16
+ * - ADC_OVERSAMPLE_RATIO_32
+ * - ADC_OVERSAMPLE_RATIO_64
+ * - ADC_OVERSAMPLE_RATIO_128
+ * - ADC_OVERSAMPLE_RATIO_256
+ * @param adc_oversample_shift: set the oversample shift.
+ * this parameter can be one of the following values:
+ * - ADC_OVERSAMPLE_SHIFT_0
+ * - ADC_OVERSAMPLE_SHIFT_1
+ * - ADC_OVERSAMPLE_SHIFT_2
+ * - ADC_OVERSAMPLE_SHIFT_3
+ * - ADC_OVERSAMPLE_SHIFT_4
+ * - ADC_OVERSAMPLE_SHIFT_5
+ * - ADC_OVERSAMPLE_SHIFT_6
+ * - ADC_OVERSAMPLE_SHIFT_7
+ * - ADC_OVERSAMPLE_SHIFT_8
+ * @retval none
+ */
+void adc_oversample_ratio_shift_set(adc_type *adc_x, adc_oversample_ratio_type adc_oversample_ratio, adc_oversample_shift_type adc_oversample_shift)
+{
+ adc_x->ovsp_bit.osrsel = adc_oversample_ratio;
+ adc_x->ovsp_bit.osssel = adc_oversample_shift;
+}
+
+/**
+ * @brief enable or disable the ordinary oversampling trigger mode of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param new_state: new state of ordinary oversampling trigger mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_ordinary_oversample_trig_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ovsp_bit.oostren = new_state;
+}
+
+/**
+ * @brief set ordinary oversample restart mode of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2, ADC3.
+ * @param adc_or_oversample_restart: ordinary oversample restart mode.
+ * this parameter can be one of the following values:
+ * - ADC_OVERSAMPLE_CONTINUE
+ * - ADC_OVERSAMPLE_RESTART
+ * @retval none
+ */
+void adc_ordinary_oversample_restart_set(adc_type *adc_x, adc_ordinary_oversample_restart_type adc_ordinary_oversample_restart)
+{
+ adc_x->ovsp_bit.oosrsel = adc_ordinary_oversample_restart;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_can.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_can.c
new file mode 100644
index 0000000..bb6a26a
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_can.c
@@ -0,0 +1,1148 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_can.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the can firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+#ifdef CAN_MODULE_ENABLED
+
+/** @defgroup CAN_private_functions
+ * @{
+ */
+
+/**
+ * @brief deinitialize the can peripheral registers to their default reset values.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @retval none.
+ */
+void can_reset(can_type* can_x)
+{
+ if(can_x == CAN1)
+ {
+ crm_periph_reset(CRM_CAN1_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_CAN1_PERIPH_RESET, FALSE);
+ }
+ else if(can_x == CAN2)
+ {
+ crm_periph_reset(CRM_CAN2_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_CAN2_PERIPH_RESET, FALSE);
+ }
+}
+
+/**
+ * @brief fill each can_baudrate_struct member with its default value.
+ * @param can_baudrate_struct: pointer to a can_baudrate_type structure which will be initialized.
+ * @retval none.
+ */
+void can_baudrate_default_para_init(can_baudrate_type* can_baudrate_struct)
+{
+ /* reset can baudrate structure parameters values */
+
+ /* baud rate division */
+ can_baudrate_struct->baudrate_div = 1;
+
+ /* resynchronization adjust width */
+ can_baudrate_struct->rsaw_size = CAN_RSAW_2TQ;
+
+ /* bit time segment 1 */
+ can_baudrate_struct->bts1_size = CAN_BTS1_4TQ;
+
+ /* bit time segment 2 */
+ can_baudrate_struct->bts2_size = CAN_BTS2_3TQ;
+}
+
+/**
+ * @brief set the baudrate of the can peripheral
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @param can_baudrate_struct: pointer to a can_baudrate_type structure which will be set.
+ * @note baudrate calculate method is:
+ * baudrate = fpclk/(baudrate_div *(3 + bts1_size + bts2_size))
+ * @retval the result of baudrate set
+ * this parameter can be one of the following values:
+ * SUCCESS or ERROR
+ */
+error_status can_baudrate_set(can_type* can_x, can_baudrate_type* can_baudrate_struct)
+{
+ error_status status_index = ERROR;
+ uint32_t wait_ack_index = 0x00000000;
+ /* exit from doze mode */
+ can_x->mctrl_bit.dzen = FALSE;
+
+ /* request freeze mode */
+ can_x->mctrl_bit.fzen = TRUE;
+
+ /* wait the acknowledge */
+ while((!can_x->msts_bit.fzc) && (wait_ack_index != FZC_TIMEOUT))
+ {
+ wait_ack_index++;
+ }
+
+ /* check acknowledge */
+ if(can_x->msts_bit.fzc)
+ {
+ can_x->btmg_bit.brdiv = can_baudrate_struct->baudrate_div - 1;
+ can_x->btmg_bit.rsaw = can_baudrate_struct->rsaw_size;
+ can_x->btmg_bit.bts1 = can_baudrate_struct->bts1_size;
+ can_x->btmg_bit.bts2 = can_baudrate_struct->bts2_size;
+
+ /* request leave freeze mode */
+ can_x->mctrl_bit.fzen = FALSE;
+
+ /* wait the acknowledge */
+ wait_ack_index = 0;
+ while((can_x->msts_bit.fzc) && (wait_ack_index != FZC_TIMEOUT))
+ {
+ wait_ack_index++;
+ }
+
+ /* check acknowledged */
+ if(can_x->msts_bit.fzc)
+ {
+ status_index = ERROR;
+ }
+ else
+ {
+ status_index = SUCCESS ;
+ }
+ }
+ else
+ {
+ status_index = ERROR;
+ }
+
+ /* return the status of baudrate set */
+ return status_index;
+}
+
+/**
+ * @brief fill each can_init_struct member with its default value.
+ * @param can_base_struct: pointer to a can_base_type structure which will be initialized.
+ * @retval none.
+ */
+void can_default_para_init(can_base_type* can_base_struct)
+{
+ /* reset can init structure parameters values */
+
+ /* initialize the time triggered communication mode */
+ can_base_struct->ttc_enable = FALSE;
+
+ /* initialize the automatic exit bus-off management */
+ can_base_struct->aebo_enable = FALSE;
+
+ /* initialize the automatic exit doze mode */
+ can_base_struct->aed_enable = FALSE;
+
+ /* initialize the prohibit retransmission when sending fails */
+ can_base_struct->prsf_enable = FALSE;
+
+ /* initialize the message discarding rule select when overflow */
+ can_base_struct->mdrsel_selection = CAN_DISCARDING_FIRST_RECEIVED;
+
+ /* initialize the multiple message sending sequence rule */
+ can_base_struct->mmssr_selection = CAN_SENDING_BY_ID;
+
+ /* initialize the can_mode */
+ can_base_struct->mode_selection = CAN_MODE_COMMUNICATE;
+}
+
+/**
+ * @brief initialize the can peripheral according to the specified
+ * parameters in the can_init_struct.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @param can_base_struct: pointer to a can_base_struct structure that contains the configuration information for the can peripheral.
+ * @retval the status of initialization
+ * this parameter can be one of the following values:
+ * SUCCESS or ERROR
+ */
+error_status can_base_init(can_type* can_x, can_base_type* can_base_struct)
+{
+ error_status init_status_index = ERROR;
+ uint32_t wait_ack_index = 0x00000000;
+ /* exit from doze mode */
+ can_x->mctrl_bit.dzen = FALSE;
+
+ /* request freeze mode */
+ can_x->mctrl_bit.fzen = TRUE;
+
+ /* wait the acknowledge */
+ while((!can_x->msts_bit.fzc) && (wait_ack_index != FZC_TIMEOUT))
+ {
+ wait_ack_index++;
+ }
+
+ /* check acknowledge */
+ if(can_x->msts_bit.fzc)
+ {
+ /* set the time triggered communication mode */
+ can_x->mctrl_bit.ttcen = can_base_struct->ttc_enable;
+
+ /* set the automatic exit bus-off management */
+ can_x->mctrl_bit.aeboen = can_base_struct->aebo_enable;
+
+ /* set the automatic automatic exit doze mode */
+ can_x->mctrl_bit.aeden = can_base_struct->aed_enable;
+
+ /* set the prohibit retransmission when sending fails */
+ can_x->mctrl_bit.prsfen = can_base_struct->prsf_enable;
+
+ /* set the message discarding rule select when overflow */
+ can_x->mctrl_bit.mdrsel = can_base_struct->mdrsel_selection;
+
+ /* set the multiple message sending sequence rule */
+ can_x->mctrl_bit.mmssr = can_base_struct->mmssr_selection;
+
+ /* set the test mode */
+ can_x->btmg_bit.lben = can_base_struct->mode_selection & 0x01;
+ can_x->btmg_bit.loen = (can_base_struct->mode_selection >> 1) & 0x01;
+
+ /* request leave freeze mode */
+ can_x->mctrl_bit.fzen = FALSE;
+
+ /* wait the acknowledge */
+ wait_ack_index = 0;
+ while((can_x->msts_bit.fzc) && (wait_ack_index != FZC_TIMEOUT))
+ {
+ wait_ack_index++;
+ }
+
+ /* check acknowledged */
+ if(can_x->msts_bit.fzc)
+ {
+ init_status_index = ERROR;
+ }
+ else
+ {
+ init_status_index = SUCCESS ;
+ }
+ }
+ else
+ {
+ init_status_index = ERROR;
+ }
+
+ /* return the status of initialization */
+ return init_status_index;
+}
+
+/**
+ * @brief fill each can_filter_init_struct member with its default value.
+ * @param can_filter_init_struct: pointer to a can_filter_init_type structure which will be initialized.
+ * @retval none.
+ */
+void can_filter_default_para_init(can_filter_init_type* can_filter_init_struct)
+{
+ /* reset can filter init structure parameters values */
+
+ /* initialize the filter activate state */
+ can_filter_init_struct->filter_activate_enable = FALSE;
+
+ /* filter mode */
+ can_filter_init_struct->filter_mode = CAN_FILTER_MODE_ID_MASK;
+
+ /* filter relation fifo select */
+ can_filter_init_struct->filter_fifo = CAN_FILTER_FIFO0;
+
+ /* filter number select */
+ can_filter_init_struct->filter_number = 0;
+
+ /* initialize the filter bit width */
+ can_filter_init_struct->filter_bit = CAN_FILTER_16BIT;
+
+ /* initialize the filters filter data bit */
+ can_filter_init_struct->filter_id_high = 0;
+ can_filter_init_struct->filter_id_low = 0;
+ can_filter_init_struct->filter_mask_high = 0;
+ can_filter_init_struct->filter_mask_low = 0;
+}
+
+/**
+ * @brief initialize the can peripheral according to the specified
+ * parameters in the can_filter_init_struct.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @param can_filter_init_struct: pointer to a can_filter_init_type structure that contains the configuration information.
+ * @retval none.
+ */
+void can_filter_init(can_type* can_x, can_filter_init_type* can_filter_init_struct)
+{
+ uint32_t filter_number_bit_pos = 0;
+ filter_number_bit_pos = ((uint32_t)1) << can_filter_init_struct->filter_number;
+ /* set the filter turn into configuration condition */
+ can_x->fctrl_bit.fcs = TRUE;
+
+ /* filter activate disable */
+ can_x->facfg &= ~(uint32_t)filter_number_bit_pos;
+
+ /* filter bit width */
+ switch(can_filter_init_struct->filter_bit)
+ {
+ case CAN_FILTER_16BIT:
+ can_x->fbwcfg &= ~(uint32_t)filter_number_bit_pos;
+ /* first 16-bit identifier and first 16-bit mask or first 16-bit identifier and second 16-bit identifier */
+ can_x->ffb[can_filter_init_struct->filter_number].ffdb1 = ((0x0000FFFF & (uint32_t)can_filter_init_struct->filter_mask_low) << 16);
+ can_x->ffb[can_filter_init_struct->filter_number].ffdb1 |= (0x0000FFFF & (uint32_t)can_filter_init_struct->filter_id_low);
+
+ /* second 16-bit identifier and second 16-bit mask or third 16-bit identifier and fourth 16-bit identifier */
+ can_x->ffb[can_filter_init_struct->filter_number].ffdb2 = ((0x0000FFFF & (uint32_t)can_filter_init_struct->filter_mask_high) << 16);
+ can_x->ffb[can_filter_init_struct->filter_number].ffdb2 |= (0x0000FFFF & (uint32_t)can_filter_init_struct->filter_id_high);
+
+ break;
+ case CAN_FILTER_32BIT:
+ can_x->fbwcfg |= filter_number_bit_pos;
+ /* 32-bit identifier or first 32-bit identifier */
+ can_x->ffb[can_filter_init_struct->filter_number].ffdb1 = ((0x0000FFFF & (uint32_t)can_filter_init_struct->filter_id_high) << 16);
+ can_x->ffb[can_filter_init_struct->filter_number].ffdb1 |= (0x0000FFFF & (uint32_t)can_filter_init_struct->filter_id_low);
+
+ /* 32-bit mask or second 32-bit identifier */
+ can_x->ffb[can_filter_init_struct->filter_number].ffdb2 = ((0x0000FFFF & (uint32_t)can_filter_init_struct->filter_mask_high) << 16);
+ can_x->ffb[can_filter_init_struct->filter_number].ffdb2 |= (0x0000FFFF & (uint32_t)can_filter_init_struct->filter_mask_low);
+
+ break;
+ default:
+ break;
+ }
+
+ /* filter mode */
+ switch(can_filter_init_struct->filter_mode)
+ {
+ case CAN_FILTER_MODE_ID_MASK:
+ can_x->fmcfg &= ~(uint32_t)filter_number_bit_pos;
+ break;
+ case CAN_FILTER_MODE_ID_LIST:
+ can_x->fmcfg |= (uint32_t)filter_number_bit_pos;
+ break;
+ default:
+ break;
+ }
+
+ /* filter relation fifo select */
+ switch(can_filter_init_struct->filter_fifo)
+ {
+ case CAN_FILTER_FIFO0:
+ can_x->frf &= ~(uint32_t)filter_number_bit_pos;
+ break;
+ case CAN_FILTER_FIFO1:
+ can_x->frf |= (uint32_t)filter_number_bit_pos;
+ break;
+ default:
+ break;
+ }
+
+ /* filter activate enable */
+ switch(can_filter_init_struct->filter_activate_enable)
+ {
+ case TRUE:
+ can_x->facfg |= (uint32_t)filter_number_bit_pos;
+ break;
+ case FALSE:
+ can_x->facfg &= ~(uint32_t)filter_number_bit_pos;
+ break;
+ default:
+ break;
+ }
+
+ /* set the filter turn into working condition */
+ can_x->fctrl_bit.fcs = FALSE;
+}
+
+/**
+ * @brief enable or disable the debug transmission prohibit of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @param new_state: new state of debug transmission prohibit.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none.
+ */
+void can_debug_transmission_prohibit(can_type* can_x, confirm_state new_state)
+{
+ can_x->mctrl_bit.ptd = new_state;
+}
+
+/**
+ * @brief enable or disable time trigger operation communication mode of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1 or CAN2.
+ * @param new_state : new state of time trigger operation communication mode.
+ * this parameter can be: TRUE or FALSE.
+ * @note
+ * note1:
+ * when enabled, transmit mailbox time stamp(tmts[15:0]) value is sent in the last two data bytes of
+ * the 8-byte message: tmts[7:0] in data byte 6 and tmts[15:8] in data byte 7
+ * @note
+ * note2:
+ * tmdtbl must be programmed as 8 in order time stamp (2 bytes) to be sent over the can bus.
+ * @retval none
+ */
+void can_ttc_mode_enable(can_type* can_x, confirm_state new_state)
+{
+ /* config the ttc mode new_state */
+ can_x->mctrl_bit.ttcen = new_state;
+
+ /* config tmtsten bits new_state */
+ can_x->tx_mailbox[0].tmc_bit.tmtsten = new_state;
+ can_x->tx_mailbox[1].tmc_bit.tmtsten = new_state;
+ can_x->tx_mailbox[2].tmc_bit.tmtsten = new_state;
+}
+
+/**
+ * @brief fill the transmission message and transmit of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @param tx_message_struct: pointer to a structure which contains the message to be trans.
+ * @retval the number of the mailbox that is used for transmission:
+ * this parameter can be one of the following values:
+ * - CAN_TX_MAILBOX0
+ * - CAN_TX_MAILBOX1
+ * - CAN_TX_MAILBOX2
+ * - CAN_TX_STATUS_NO_EMPTY
+ */
+uint8_t can_message_transmit(can_type* can_x, can_tx_message_type* tx_message_struct)
+{
+ uint8_t transmit_mailbox = CAN_TX_STATUS_NO_EMPTY;
+
+ /* select one empty transmit mailbox */
+ if(can_x->tsts_bit.tm0ef)
+ {
+ transmit_mailbox = CAN_TX_MAILBOX0;
+ }
+ else if(can_x->tsts_bit.tm1ef)
+ {
+ transmit_mailbox = CAN_TX_MAILBOX1;
+ }
+ else if(can_x->tsts_bit.tm2ef)
+ {
+ transmit_mailbox = CAN_TX_MAILBOX2;
+ }
+ else
+ {
+ transmit_mailbox = CAN_TX_STATUS_NO_EMPTY;
+ }
+
+ if(transmit_mailbox != CAN_TX_STATUS_NO_EMPTY)
+ {
+ /* set up the id */
+ can_x->tx_mailbox[transmit_mailbox].tmi &= 0x00000001;
+ can_x->tx_mailbox[transmit_mailbox].tmi_bit.tmidsel = tx_message_struct->id_type;
+ switch(tx_message_struct->id_type)
+ {
+ case CAN_ID_STANDARD:
+ can_x->tx_mailbox[transmit_mailbox].tmi_bit.tmsid = tx_message_struct->standard_id;
+ break;
+ case CAN_ID_EXTENDED:
+ can_x->tx_mailbox[transmit_mailbox].tmi |= (tx_message_struct->extended_id << 3);
+ break;
+ default:
+ break;
+ }
+ can_x->tx_mailbox[transmit_mailbox].tmi_bit.tmfrsel = tx_message_struct->frame_type;
+ /* set up the dlc */
+ can_x->tx_mailbox[transmit_mailbox].tmc_bit.tmdtbl = (tx_message_struct->dlc & ((uint8_t)0x0F));
+
+ /* set up the data field */
+ can_x->tx_mailbox[transmit_mailbox].tmdtl = (((uint32_t)tx_message_struct->data[3] << 24) |
+ ((uint32_t)tx_message_struct->data[2] << 16) |
+ ((uint32_t)tx_message_struct->data[1] << 8) |
+ ((uint32_t)tx_message_struct->data[0]));
+ can_x->tx_mailbox[transmit_mailbox].tmdth = (((uint32_t)tx_message_struct->data[7] << 24) |
+ ((uint32_t)tx_message_struct->data[6] << 16) |
+ ((uint32_t)tx_message_struct->data[5] << 8) |
+ ((uint32_t)tx_message_struct->data[4]));
+
+ /* request transmission */
+ can_x->tx_mailbox[transmit_mailbox].tmi_bit.tmsr = TRUE;
+ }
+ return transmit_mailbox;
+}
+
+/**
+ * @brief check the transmission state of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1 or CAN2.
+ * @param transmit_mailbox: the number of the mailbox that is used for transmission.
+ * this parameter can be one of the following values:
+ * - CAN_TX_MAILBOX0
+ * - CAN_TX_MAILBOX1
+ * - CAN_TX_MAILBOX2
+ * @retval can transmit status
+ * this parameter can be one of the following values:
+ * - CAN_TX_STATUS_SUCCESSFUL
+ * - CAN_TX_STATUS_FAILED
+ * - CAN_TX_STATUS_PENDING
+ */
+can_transmit_status_type can_transmit_status_get(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox)
+{
+ can_transmit_status_type state_index = CAN_TX_STATUS_FAILED;
+ switch(transmit_mailbox)
+ {
+ case CAN_TX_MAILBOX0:
+ if(can_x->tsts_bit.tm0tcf != RESET)
+ {
+ if(can_x->tsts_bit.tm0tsf != RESET)
+ {
+ state_index = CAN_TX_STATUS_SUCCESSFUL;
+ }
+ else
+ {
+ state_index = CAN_TX_STATUS_FAILED;
+ }
+ }
+ else
+ {
+ state_index = CAN_TX_STATUS_PENDING;
+ }
+ break;
+ case CAN_TX_MAILBOX1:
+ if(can_x->tsts_bit.tm1tcf != RESET)
+ {
+ if(can_x->tsts_bit.tm1tsf != RESET)
+ {
+ state_index = CAN_TX_STATUS_SUCCESSFUL;
+ }
+ else
+ {
+ state_index = CAN_TX_STATUS_FAILED;
+ }
+ }
+ else
+ {
+ state_index = CAN_TX_STATUS_PENDING;
+ }
+ break;
+ case CAN_TX_MAILBOX2:
+ if(can_x->tsts_bit.tm2tcf != RESET)
+ {
+ if(can_x->tsts_bit.tm2tsf != RESET)
+ {
+ state_index = CAN_TX_STATUS_SUCCESSFUL;
+ }
+ else
+ {
+ state_index = CAN_TX_STATUS_FAILED;
+ }
+ }
+ else
+ {
+ state_index = CAN_TX_STATUS_PENDING;
+ }
+ break;
+ default:
+ state_index = CAN_TX_STATUS_FAILED;
+ break;
+ }
+ return state_index;
+}
+
+/**
+ * @brief cancel a transmit request of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1 or CAN2.
+ * @param mailbox: mailbox number.
+ * this parameter can be one of the following values:
+ * - CAN_TX_MAILBOX0
+ * - CAN_TX_MAILBOX1
+ * - CAN_TX_MAILBOX2
+ * @retval none.
+ */
+void can_transmit_cancel(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox)
+{
+ switch (transmit_mailbox)
+ {
+ case CAN_TX_MAILBOX0:
+ can_x->tsts = CAN_TSTS_TM0CT_VAL;
+ break;
+ case CAN_TX_MAILBOX1:
+ can_x->tsts = CAN_TSTS_TM1CT_VAL;
+ break;
+ case CAN_TX_MAILBOX2:
+ can_x->tsts = CAN_TSTS_TM2CT_VAL;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief receive message of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @param fifo_number: receive fifo number.
+ * this parameter can be one of the following values:
+ * - CAN_RX_FIFO0
+ * - CAN_RX_FIFO1
+ * @param rx_message_struct: pointer to a structure which store the receive message.
+ * @retval none.
+ */
+void can_message_receive(can_type* can_x, can_rx_fifo_num_type fifo_number, can_rx_message_type* rx_message_struct)
+{
+ /* get the id type */
+ rx_message_struct->id_type = (can_identifier_type)can_x->fifo_mailbox[fifo_number].rfi_bit.rfidi;
+ switch (rx_message_struct->id_type)
+ {
+ case CAN_ID_STANDARD:
+ rx_message_struct->standard_id = can_x->fifo_mailbox[fifo_number].rfi_bit.rfsid;
+ break;
+ case CAN_ID_EXTENDED:
+ rx_message_struct->extended_id = 0x1FFFFFFF & (can_x->fifo_mailbox[fifo_number].rfi >> 3);
+ break;
+ default:
+ break;
+ }
+ rx_message_struct->frame_type = (can_trans_frame_type)can_x->fifo_mailbox[fifo_number].rfi_bit.rffri;
+ /* get the dlc */
+ rx_message_struct->dlc = can_x->fifo_mailbox[fifo_number].rfc_bit.rfdtl;
+
+ /* get the filter match number */
+ rx_message_struct->filter_index = can_x->fifo_mailbox[fifo_number].rfc_bit.rffmn;
+
+ /* get the data field */
+ rx_message_struct->data[0] = can_x->fifo_mailbox[fifo_number].rfdtl_bit.rfdt0;
+ rx_message_struct->data[1] = can_x->fifo_mailbox[fifo_number].rfdtl_bit.rfdt1;
+ rx_message_struct->data[2] = can_x->fifo_mailbox[fifo_number].rfdtl_bit.rfdt2;
+ rx_message_struct->data[3] = can_x->fifo_mailbox[fifo_number].rfdtl_bit.rfdt3;
+ rx_message_struct->data[4] = can_x->fifo_mailbox[fifo_number].rfdth_bit.rfdt4;
+ rx_message_struct->data[5] = can_x->fifo_mailbox[fifo_number].rfdth_bit.rfdt5;
+ rx_message_struct->data[6] = can_x->fifo_mailbox[fifo_number].rfdth_bit.rfdt6;
+ rx_message_struct->data[7] = can_x->fifo_mailbox[fifo_number].rfdth_bit.rfdt7;
+
+ /* release the fifo */
+ can_receive_fifo_release(can_x, fifo_number);
+}
+
+/**
+ * @brief release the specified fifo of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @param fifo_number: fifo to be release.
+ * this parameter can be one of the following values:
+ * - CAN_RX_FIFO0
+ * - CAN_RX_FIFO1
+ * @retval none.
+ */
+void can_receive_fifo_release(can_type* can_x, can_rx_fifo_num_type fifo_number)
+{
+ switch (fifo_number)
+ {
+ case CAN_RX_FIFO0:
+ can_x->rf0 = CAN_RF0_RF0R_VAL;
+ break;
+ case CAN_RX_FIFO1:
+ can_x->rf1 = CAN_RF1_RF1R_VAL;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief return the number of pending messages of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @param fifo_number: receive fifo number.
+ * this parameter can be one of the following values:
+ * - CAN_RX_FIFO0
+ * - CAN_RX_FIFO1
+ * @retval the number of message pending in the receive fifo.
+ */
+uint8_t can_receive_message_pending_get(can_type* can_x, can_rx_fifo_num_type fifo_number)
+{
+ uint8_t message_pending = 0;
+ switch (fifo_number)
+ {
+ case CAN_RX_FIFO0:
+ message_pending = can_x->rf0_bit.rf0mn;
+ break;
+ case CAN_RX_FIFO1:
+ message_pending = can_x->rf1_bit.rf1mn;
+ break;
+ default:
+ break;
+ }
+ return message_pending;
+}
+
+/**
+ * @brief set the operation mode of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @param can_operating_mode: can operating mode.
+ * this parameter can be one of the following values:
+ * - CAN_OPERATINGMODE_FREEZE
+ * - CAN_OPERATINGMODE_DOZE
+ * - CAN_OPERATINGMODE_COMMUNICATE
+ * @retval status of operation mode set
+ * this parameter can be one of the following values:
+ * SUCCESS or ERROR
+ */
+error_status can_operating_mode_set(can_type* can_x, can_operating_mode_type can_operating_mode)
+{
+ error_status status = ERROR;
+ uint32_t time_out_index = FZC_TIMEOUT;
+
+ if (can_operating_mode == CAN_OPERATINGMODE_FREEZE)
+ {
+ /* request enter freeze mode */
+ can_x->mctrl_bit.dzen = FALSE;
+ can_x->mctrl_bit.fzen = TRUE;
+
+ while(((can_x->msts_bit.dzc) || (!can_x->msts_bit.fzc)) && (time_out_index != 0))
+ {
+ time_out_index--;
+ }
+ if((can_x->msts_bit.dzc) || (!can_x->msts_bit.fzc))
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else if(can_operating_mode == CAN_OPERATINGMODE_DOZE)
+ {
+ /* request enter doze mode */
+ can_x->mctrl_bit.dzen = TRUE;
+ can_x->mctrl_bit.fzen = FALSE;
+
+ while(((!can_x->msts_bit.dzc) || (can_x->msts_bit.fzc)) && (time_out_index != 0))
+ {
+ time_out_index--;
+ }
+ if((!can_x->msts_bit.dzc) || (can_x->msts_bit.fzc))
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else if(can_operating_mode == CAN_OPERATINGMODE_COMMUNICATE)
+ {
+ /* request enter normal mode */
+ can_x->mctrl_bit.dzen = FALSE;
+ can_x->mctrl_bit.fzen = FALSE;
+
+ while(((can_x->msts_bit.dzc) || (can_x->msts_bit.fzc)) && (time_out_index != 0))
+ {
+ time_out_index--;
+ }
+ if((can_x->msts_bit.dzc) || (can_x->msts_bit.fzc))
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief enter the low power mode of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @retval status of doze mode enter, the returned value can be:
+ * - CAN_ENTER_DOZE_SUCCESSFUL
+ * - CAN_ENTER_DOZE_FAILED
+ */
+can_enter_doze_status_type can_doze_mode_enter(can_type* can_x)
+{
+ can_enter_doze_status_type status = CAN_ENTER_DOZE_FAILED;
+ uint32_t time_out_index = FZC_TIMEOUT;
+ can_x->mctrl_bit.fzen = FALSE;
+ can_x->mctrl_bit.dzen = TRUE;
+ while(((!can_x->msts_bit.dzc) || (can_x->msts_bit.fzc)) && (time_out_index != 0))
+ {
+ time_out_index--;
+ }
+ if((!can_x->msts_bit.dzc) || (can_x->msts_bit.fzc))
+ {
+ status = CAN_ENTER_DOZE_FAILED;
+ }
+ else
+ {
+ status = CAN_ENTER_DOZE_SUCCESSFUL;
+ }
+ return status;
+}
+
+/**
+ * @brief exit the doze mode of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @retval status of doze mode enter, the returned value can be:
+ * - CAN_QUIT_DOZE_SUCCESSFUL
+ * - CAN_QUIT_DOZE_FAILED
+ */
+can_quit_doze_status_type can_doze_mode_exit(can_type* can_x)
+{
+ can_quit_doze_status_type status = CAN_QUIT_DOZE_FAILED;
+ uint32_t time_out_index = DZC_TIMEOUT;
+ can_x->mctrl_bit.dzen = FALSE;
+ while((can_x->msts_bit.dzc) && (time_out_index != 0))
+ {
+ time_out_index--;
+ }
+ if(!can_x->msts_bit.dzc)
+ {
+ status = CAN_QUIT_DOZE_SUCCESSFUL;
+ }
+ return status;
+}
+
+/**
+ * @brief return the error type record (etr) of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @retval the value of the error code
+ * the return can be one of the follow values:
+ * - CAN_ERRORRECORD_NOERR
+ * - CAN_ERRORRECORD_STUFFERR,
+ * - CAN_ERRORRECORD_FORMERR,
+ * - CAN_ERRORRECORD_ACKERR,
+ * - CAN_ERRORRECORD_BITRECESSIVEERR,
+ * - CAN_ERRORRECORD_BITDOMINANTERR,
+ * - CAN_ERRORRECORD_CRCERR,
+ * - CAN_ERRORRECORD_SOFTWARESETERR
+ */
+can_error_record_type can_error_type_record_get(can_type* can_x)
+{
+ can_error_record_type error_code = CAN_ERRORRECORD_NOERR;
+
+ error_code = (can_error_record_type)can_x->ests_bit.etr;
+ return error_code;
+}
+
+/**
+ * @brief return the receive error counter (rec) of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @retval the value of receive error counter.
+ */
+uint8_t can_receive_error_counter_get(can_type* can_x)
+{
+ uint8_t counter = 0;
+ counter = can_x->ests_bit.rec;
+ return counter;
+}
+
+/**
+ * @brief return the transmit error counter of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @retval the value of transmit error counter.
+ */
+uint8_t can_transmit_error_counter_get(can_type* can_x)
+{
+ uint8_t counter = 0;
+ counter = can_x->ests_bit.tec;
+ return counter;
+}
+
+/**
+ * @brief enable or disable the interrupt of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @param can_int: specifies the can interrupt sources to be enabled or disabled.
+ * this parameter can be one of the following values:
+ * - CAN_TCIEN_INT
+ * - CAN_RF0MIEN_INT
+ * - CAN_RF0FIEN_INT
+ * - CAN_RF0OIEN_INT
+ * - CAN_RF1MIEN_INT
+ * - CAN_RF1FIEN_INT
+ * - CAN_RF1OIEN_INT
+ * - CAN_EAIEN_INT
+ * - CAN_EPIEN_INT
+ * - CAN_BOIEN_INT
+ * - CAN_ETRIEN_INT
+ * - CAN_EOIEN_INT
+ * - CAN_QDZIEN_INT
+ * - CAN_EDZIEN_INT
+ * @param new_state: new state of the can interrupts.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none.
+ */
+void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state)
+{
+ if (new_state != FALSE)
+ {
+ can_x->inten |= can_int;
+ }
+ else
+ {
+ can_x->inten &= ~can_int;
+ }
+}
+
+/**
+ * @brief get flag of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @param can_flag: select the flag.
+ * this parameter can be one of the following flags:
+ * - CAN_EAF_FLAG
+ * - CAN_EPF_FLAG
+ * - CAN_BOF_FLAG
+ * - CAN_ETR_FLAG
+ * - CAN_EOIF_FLAG
+ * - CAN_TM0TCF_FLAG
+ * - CAN_TM1TCF_FLAG
+ * - CAN_TM2TCF_FLAG
+ * - CAN_RF0MN_FLAG
+ * - CAN_RF0FF_FLAG
+ * - CAN_RF0OF_FLAG
+ * - CAN_RF1MN_FLAG
+ * - CAN_RF1FF_FLAG
+ * - CAN_RF1OF_FLAG
+ * - CAN_QDZIF_FLAG
+ * - CAN_EDZC_FLAG
+ * - CAN_TMEF_FLAG
+ * note:the state of CAN_EDZC_FLAG need to check dzc and edzif bit
+ * note:the state of CAN_TMEF_FLAG need to check rqc0,rqc1 and rqc2 bit
+ * @retval status of can_flag, the returned value can be:SET or RESET.
+ */
+flag_status can_flag_get(can_type* can_x, uint32_t can_flag)
+{
+ flag_status bit_status = RESET;
+ switch(can_flag)
+ {
+ case CAN_EAF_FLAG:
+ bit_status = (flag_status)can_x->ests_bit.eaf;
+ break;
+ case CAN_EPF_FLAG:
+ bit_status = (flag_status)can_x->ests_bit.epf;
+ break;
+ case CAN_BOF_FLAG:
+ bit_status = (flag_status)can_x->ests_bit.bof;
+ break;
+ case CAN_ETR_FLAG:
+ if(can_x->ests_bit.etr != 0)
+ {
+ bit_status = SET;
+ }
+ else
+ {
+ bit_status = RESET;
+ }
+ break;
+ case CAN_EOIF_FLAG:
+ bit_status = (flag_status)can_x->msts_bit.eoif;
+ break;
+ case CAN_TM0TCF_FLAG:
+ bit_status = (flag_status)can_x->tsts_bit.tm0tcf;
+ break;
+ case CAN_TM1TCF_FLAG:
+ bit_status = (flag_status)can_x->tsts_bit.tm1tcf;
+ break;
+ case CAN_TM2TCF_FLAG:
+ bit_status = (flag_status)can_x->tsts_bit.tm2tcf;
+ break;
+ case CAN_RF0MN_FLAG:
+ if(can_x->rf0_bit.rf0mn != 0)
+ {
+ bit_status = SET;
+ }
+ else
+ {
+ bit_status = RESET;
+ }
+ break;
+ case CAN_RF0FF_FLAG:
+ bit_status = (flag_status)can_x->rf0_bit.rf0ff;
+ break;
+ case CAN_RF0OF_FLAG:
+ bit_status = (flag_status)can_x->rf0_bit.rf0of;
+ break;
+ case CAN_RF1MN_FLAG:
+ if(can_x->rf1_bit.rf1mn != 0)
+ {
+ bit_status = SET;
+ }
+ else
+ {
+ bit_status = RESET;
+ }
+ break;
+ case CAN_RF1FF_FLAG:
+ bit_status = (flag_status)can_x->rf1_bit.rf1ff;
+ break;
+ case CAN_RF1OF_FLAG:
+ bit_status = (flag_status)can_x->rf1_bit.rf1of;
+ break;
+ case CAN_QDZIF_FLAG:
+ bit_status = (flag_status)can_x->msts_bit.qdzif;
+ break;
+ case CAN_EDZC_FLAG:
+ if((can_x->msts_bit.dzc != RESET) ||(can_x->msts_bit.edzif != RESET))
+ {
+ bit_status = SET;
+ }
+ else
+ {
+ bit_status = RESET;
+ }
+ break;
+ case CAN_TMEF_FLAG:
+ if((can_x->tsts_bit.tm0ef != RESET) || (can_x->tsts_bit.tm1ef != RESET) || (can_x->tsts_bit.tm2ef != RESET))
+ {
+ bit_status = SET;
+ }
+ else
+ {
+ bit_status = RESET;
+ }
+ break;
+ default:
+ bit_status = RESET;
+ break;
+ }
+ return bit_status;
+}
+
+/**
+ * @brief clear flag of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1,CAN2.
+ * @param can_flag: select the flag.
+ * this parameter can be one of the following flags:
+ * - CAN_EAF_FLAG
+ * - CAN_EPF_FLAG
+ * - CAN_BOF_FLAG
+ * - CAN_ETR_FLAG
+ * - CAN_EOIF_FLAG
+ * - CAN_TM0TCF_FLAG
+ * - CAN_TM1TCF_FLAG
+ * - CAN_TM2TCF_FLAG
+ * - CAN_RF0FF_FLAG
+ * - CAN_RF0OF_FLAG
+ * - CAN_RF1FF_FLAG
+ * - CAN_RF1OF_FLAG
+ * - CAN_QDZIF_FLAG
+ * - CAN_EDZC_FLAG
+ * - CAN_TMEF_FLAG
+ * note:CAN_RF0MN_FLAG and CAN_RF1MN_FLAG can not clear by this function
+ * @retval none.
+ */
+void can_flag_clear(can_type* can_x, uint32_t can_flag)
+{
+ switch(can_flag)
+ {
+ case CAN_EAF_FLAG:
+ case CAN_EPF_FLAG:
+ case CAN_BOF_FLAG:
+ case CAN_EOIF_FLAG:
+ can_x->msts = CAN_MSTS_EOIF_VAL;
+ break;
+ case CAN_ETR_FLAG:
+ can_x->msts = CAN_MSTS_EOIF_VAL;
+ can_x->ests = 0;
+ break;
+ case CAN_TM0TCF_FLAG:
+ can_x->tsts = CAN_TSTS_TM0TCF_VAL;
+ break;
+ case CAN_TM1TCF_FLAG:
+ can_x->tsts = CAN_TSTS_TM1TCF_VAL;
+ break;
+ case CAN_TM2TCF_FLAG:
+ can_x->tsts = CAN_TSTS_TM2TCF_VAL;
+ break;
+ case CAN_RF0FF_FLAG:
+ can_x->rf0 = CAN_RF0_RF0FF_VAL;
+ break;
+ case CAN_RF0OF_FLAG:
+ can_x->rf0 = CAN_RF0_RF0OF_VAL;
+ break;
+ case CAN_RF1FF_FLAG:
+ can_x->rf1 = CAN_RF1_RF1FF_VAL;
+ break;
+ case CAN_RF1OF_FLAG:
+ can_x->rf1 = CAN_RF1_RF1OF_VAL;
+ break;
+ case CAN_QDZIF_FLAG:
+ can_x->msts = CAN_MSTS_QDZIF_VAL;
+ break;
+ case CAN_EDZC_FLAG:
+ can_x->msts = CAN_MSTS_EDZIF_VAL;
+ break;
+ case CAN_TMEF_FLAG:
+ can_x->tsts = CAN_TSTS_TM0TCF_VAL | CAN_TSTS_TM1TCF_VAL | CAN_TSTS_TM2TCF_VAL;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_crc.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_crc.c
new file mode 100644
index 0000000..7897043
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_crc.c
@@ -0,0 +1,164 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_crc.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the crc firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup CRC
+ * @brief CRC driver modules
+ * @{
+ */
+
+#ifdef CRC_MODULE_ENABLED
+
+/** @defgroup CRC_private_functions
+ * @{
+ */
+
+/**
+ * @brief reset the crc data register.
+ * @param none
+ * @retval none
+ */
+void crc_data_reset(void)
+{
+ /* reset crc generator */
+ CRC->ctrl_bit.rst = 0x1;
+}
+
+/**
+ * @brief compute the 32-bit crc of a given data word(32-bit).
+ * @param data: data word(32-bit) to compute its crc
+ * @retval 32-bit crc
+ */
+uint32_t crc_one_word_calculate(uint32_t data)
+{
+ CRC->dt = data;
+ return (CRC->dt);
+}
+
+/**
+ * @brief compute the 32-bit crc of a given buffer of data word(32-bit).
+ * @param pbuffer: pointer to the buffer containing the data to be computed
+ * @param length: length of the buffer to be computed
+ * @retval 32-bit crc
+ */
+uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length)
+{
+ uint32_t index = 0;
+
+ for(index = 0; index < length; index++)
+ {
+ CRC->dt = pbuffer[index];
+ }
+
+ return (CRC->dt);
+}
+
+/**
+ * @brief return the current crc value.
+ * @param none
+ * @retval 32-bit crc
+ */
+uint32_t crc_data_get(void)
+{
+ return (CRC->dt);
+}
+
+/**
+ * @brief store a 8-bit data in the common data register.
+ * @param cdt_value: 8-bit value to be stored in the common data register
+ * @retval none
+ */
+void crc_common_data_set(uint8_t cdt_value)
+{
+ CRC->cdt_bit.cdt = cdt_value;
+}
+
+/**
+ * @brief return the 8-bit data stored in the common data register
+ * @param none
+ * @retval 8-bit value of the common data register
+ */
+uint8_t crc_common_date_get(void)
+{
+ return (CRC->cdt_bit.cdt);
+}
+
+/**
+ * @brief set the 32-bit initial data of crc
+ * @param value: initial data
+ * @retval none
+ */
+void crc_init_data_set(uint32_t value)
+{
+ CRC->idt = value;
+}
+
+/**
+ * @brief control the reversal of the bit order in the input data
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRC_REVERSE_INPUT_NO_AFFECTE
+ * - CRC_REVERSE_INPUT_BY_BYTE
+ * - CRC_REVERSE_INPUT_BY_HALFWORD
+ * - CRC_REVERSE_INPUT_BY_WORD
+ * @retval none.
+ */
+void crc_reverse_input_data_set(crc_reverse_input_type value)
+{
+ CRC->ctrl_bit.revid = value;
+}
+
+/**
+ * @brief control the reversal of the bit order in the output data
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRC_REVERSE_OUTPUT_NO_AFFECTE
+ * - CRC_REVERSE_OUTPUT_DATA
+ * @retval none.
+ */
+void crc_reverse_output_data_set(crc_reverse_output_type value)
+{
+ CRC->ctrl_bit.revod = value;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_crm.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_crm.c
new file mode 100644
index 0000000..c12d71c
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_crm.c
@@ -0,0 +1,982 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_crm.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the crm firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup CRM
+ * @brief CRM driver modules
+ * @{
+ */
+
+#ifdef CRM_MODULE_ENABLED
+
+/** @defgroup CRM_private_functions
+ * @{
+ */
+
+/**
+ * @brief reset the crm register
+ * @param none
+ * @retval none
+ */
+void crm_reset(void)
+{
+ /* reset the crm clock configuration to the default reset state(for debug purpose) */
+ /* set hicken bit */
+ CRM->ctrl_bit.hicken = TRUE;
+
+ /* wait hick stable */
+ while(CRM->ctrl_bit.hickstbl != SET);
+
+ /* hick used as system clock */
+ CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
+
+ /* wait sclk switch status */
+ while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
+
+ /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */
+ CRM->cfg = 0;
+
+ /* reset hexten, hextbyps, cfden and pllen bits */
+ CRM->ctrl &= ~(0x010D0000U);
+
+ /* reset pllms pllns pllfr pllrcs bits */
+ CRM->pllcfg = 0x00033002U;
+
+ /* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
+ CRM->misc1 = 0;
+
+ /* disable all interrupts enable and clear pending bits */
+ CRM->clkint = 0x009F0000U;
+}
+
+/**
+ * @brief enable or disable crm low speed external crystal bypass
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_lext_bypass(confirm_state new_state)
+{
+ CRM->bpdc_bit.lextbyps = new_state;
+}
+
+/**
+ * @brief enable or disable crm high speed external crystal bypass
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_hext_bypass(confirm_state new_state)
+{
+ CRM->ctrl_bit.hextbyps = new_state;
+}
+
+/**
+ * @brief get crm flag status
+ * @param flag
+ * this parameter can be one of the following values:
+ * - CRM_HICK_STABLE_FLAG
+ * - CRM_HEXT_STABLE_FLAG
+ * - CRM_PLL_STABLE_FLAG
+ * - CRM_LEXT_STABLE_FLAG
+ * - CRM_LICK_STABLE_FLAG
+ * - CRM_PIN_RESET_FLAG
+ * - CRM_POR_RESET_FLAG
+ * - CRM_SW_RESET_FLAG
+ * - CRM_WDT_RESET_FLAG
+ * - CRM_WWDT_RESET_FLAG
+ * - CRM_LOWPOWER_RESET_FLAG
+ * interrupt flag:
+ * - CRM_LICK_READY_INT_FLAG
+ * - CRM_LEXT_READY_INT_FLAG
+ * - CRM_HICK_READY_INT_FLAG
+ * - CRM_HEXT_READY_INT_FLAG
+ * - CRM_PLL_READY_INT_FLAG
+ * - CRM_CLOCK_FAILURE_INT_FLAG
+ * @retval flag_status (SET or RESET)
+ */
+flag_status crm_flag_get(uint32_t flag)
+{
+ flag_status status = RESET;
+ if((CRM_REG(flag) & CRM_REG_BIT(flag)) != CRM_REG_BIT(flag))
+ {
+ status = RESET;
+ }
+ else
+ {
+ status = SET;
+ }
+ return status;
+}
+
+/**
+ * @brief wait for hext stable
+ * @param none
+ * @retval error_status (ERROR or SUCCESS)
+ */
+error_status crm_hext_stable_wait(void)
+{
+ uint32_t stable_cnt = 0;
+ error_status status = ERROR;
+
+ while((crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET) && (stable_cnt < HEXT_STARTUP_TIMEOUT))
+ {
+ stable_cnt ++;
+ }
+
+ if(crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+
+ return status;
+}
+
+/**
+ * @brief set the hick trimming value
+ * @param trim_value (0x00~0x3F)
+ * @retval none
+ */
+void crm_hick_clock_trimming_set(uint8_t trim_value)
+{
+ CRM->ctrl_bit.hicktrim = trim_value;
+}
+
+/**
+ * @brief set the crm calibration value
+ * @param cali_value (0x00~0xFF)
+ * @retval none
+ */
+void crm_hick_clock_calibration_set(uint8_t cali_value)
+{
+ /* enable write hick calibration */
+ CRM->misc1_bit.hickcal_key = 0x5A;
+
+ /* write hick calibration value */
+ CRM->ctrl_bit.hickcal = cali_value;
+
+ /* disable write hick calibration */
+ CRM->misc1_bit.hickcal_key = 0x0;
+}
+
+/**
+ * @brief enable or disable the peripheral clock
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_GPIOA_PERIPH_CLOCK - CRM_GPIOB_PERIPH_CLOCK - CRM_GPIOC_PERIPH_CLOCK - CRM_GPIOD_PERIPH_CLOCK
+ * - CRM_GPIOE_PERIPH_CLOCK - CRM_GPIOF_PERIPH_CLOCK - CRM_GPIOG_PERIPH_CLOCK - CRM_GPIOH_PERIPH_CLOCK
+ * - CRM_CRC_PERIPH_CLOCK - CRM_EDMA_PERIPH_CLOCK - CRM_DMA1_PERIPH_CLOCK - CRM_DMA2_PERIPH_CLOCK
+ * - CRM_EMAC_PERIPH_CLOCK - CRM_EMACTX_PERIPH_CLOCK - CRM_EMACRX_PERIPH_CLOCK - CRM_EMACPTP_PERIPH_CLOCK
+ * - CRM_OTGFS2_PERIPH_CLOCK - CRM_DVP_PERIPH_CLOCK - CRM_OTGFS1_PERIPH_CLOCK - CRM_SDIO1_PERIPH_CLOCK
+ * - CRM_XMC_PERIPH_CLOCK - CRM_QSPI1_PERIPH_CLOCK - CRM_QSPI2_PERIPH_CLOCK - CRM_SDIO2_PERIPH_CLOCK
+ * - CRM_TMR2_PERIPH_CLOCK - CRM_TMR3_PERIPH_CLOCK - CRM_TMR4_PERIPH_CLOCK - CRM_TMR5_PERIPH_CLOCK
+ * - CRM_TMR6_PERIPH_CLOCK - CRM_TMR7_PERIPH_CLOCK - CRM_TMR12_PERIPH_CLOCK - CRM_TMR13_PERIPH_CLOCK
+ * - CRM_TMR14_PERIPH_CLOCK - CRM_WWDT_PERIPH_CLOCK - CRM_SPI2_PERIPH_CLOCK - CRM_SPI3_PERIPH_CLOCK
+ * - CRM_USART2_PERIPH_CLOCK - CRM_USART3_PERIPH_CLOCK - CRM_UART4_PERIPH_CLOCK - CRM_UART5_PERIPH_CLOCK
+ * - CRM_I2C1_PERIPH_CLOCK - CRM_I2C2_PERIPH_CLOCK - CRM_I2C3_PERIPH_CLOCK - CRM_CAN1_PERIPH_CLOCK
+ * - CRM_CAN2_PERIPH_CLOCK - CRM_PWC_PERIPH_CLOCK - CRM_DAC_PERIPH_CLOCK - CRM_UART7_PERIPH_CLOCK
+ * - CRM_UART8_PERIPH_CLOCK - CRM_TMR1_PERIPH_CLOCK - CRM_TMR8_PERIPH_CLOCK - CRM_USART1_PERIPH_CLOCK
+ * - CRM_USART6_PERIPH_CLOCK - CRM_ADC1_PERIPH_CLOCK - CRM_ADC2_PERIPH_CLOCK - CRM_ADC3_PERIPH_CLOCK
+ * - CRM_SPI1_PERIPH_CLOCK - CRM_SPI4_PERIPH_CLOCK - CRM_SCFG_PERIPH_CLOCK - CRM_TMR9_PERIPH_CLOCK
+ * - CRM_TMR10_PERIPH_CLOCK - CRM_TMR11_PERIPH_CLOCK - CRM_TMR20_PERIPH_CLOCK - CRM_ACC_PERIPH_CLOCK
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state)
+{
+ /* enable periph clock */
+ if(TRUE == new_state)
+ {
+ CRM_REG(value) |= CRM_REG_BIT(value);
+ }
+ /* disable periph clock */
+ else
+ {
+ CRM_REG(value) &= ~(CRM_REG_BIT(value));
+ }
+}
+
+/**
+ * @brief enable or disable the peripheral reset
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_GPIOA_PERIPH_RESET - CRM_GPIOB_PERIPH_RESET - CRM_GPIOC_PERIPH_RESET - CRM_GPIOD_PERIPH_RESET
+ * - CRM_GPIOE_PERIPH_RESET - CRM_GPIOF_PERIPH_RESET - CRM_GPIOG_PERIPH_RESET - CRM_GPIOH_PERIPH_RESET
+ * - CRM_CRC_PERIPH_RESET - CRM_EDMA_PERIPH_RESET - CRM_DMA1_PERIPH_RESET - CRM_DMA2_PERIPH_RESET
+ * - CRM_EMAC_PERIPH_RESET - CRM_OTGFS2_PERIPH_RESET - CRM_DVP_PERIPH_RESET - CRM_OTGFS1_PERIPH_RESET
+ * - CRM_SDIO1_PERIPH_RESET - CRM_XMC_PERIPH_RESET - CRM_QSPI1_PERIPH_RESET - CRM_QSPI2_PERIPH_RESET
+ * - CRM_SDIO2_PERIPH_RESET - CRM_TMR2_PERIPH_RESET - CRM_TMR3_PERIPH_RESET - CRM_TMR4_PERIPH_RESET
+ * - CRM_TMR5_PERIPH_RESET - CRM_TMR6_PERIPH_RESET - CRM_TMR7_PERIPH_RESET - CRM_TMR12_PERIPH_RESET
+ * - CRM_TMR13_PERIPH_RESET - CRM_TMR14_PERIPH_RESET - CRM_WWDT_PERIPH_RESET - CRM_SPI2_PERIPH_RESET
+ * - CRM_SPI3_PERIPH_RESET - CRM_USART2_PERIPH_RESET - CRM_USART3_PERIPH_RESET - CRM_UART4_PERIPH_RESET
+ * - CRM_UART5_PERIPH_RESET - CRM_I2C1_PERIPH_RESET - CRM_I2C2_PERIPH_RESET - CRM_I2C3_PERIPH_RESET
+ * - CRM_CAN1_PERIPH_RESET - CRM_CAN2_PERIPH_RESET - CRM_PWC_PERIPH_RESET - CRM_DAC_PERIPH_RESET
+ * - CRM_UART7_PERIPH_RESET - CRM_UART8_PERIPH_RESET - CRM_TMR1_PERIPH_RESET - CRM_TMR8_PERIPH_RESET
+ * - CRM_USART1_PERIPH_RESET - CRM_USART6_PERIPH_RESET - CRM_ADC_PERIPH_RESET - CRM_SPI1_PERIPH_RESET
+ * - CRM_SPI4_PERIPH_RESET - CRM_SCFG_PERIPH_RESET - CRM_TMR9_PERIPH_RESET - CRM_TMR10_PERIPH_RESET
+ * - CRM_TMR11_PERIPH_RESET - CRM_TMR20_PERIPH_RESET - CRM_ACC_PERIPH_RESET
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state)
+{
+ /* enable periph reset */
+ if(new_state == TRUE)
+ {
+ CRM_REG(value) |= (CRM_REG_BIT(value));
+ }
+ /* disable periph reset */
+ else
+ {
+ CRM_REG(value) &= ~(CRM_REG_BIT(value));
+ }
+}
+
+/**
+ * @brief enable or disable the peripheral clock in lowpower mode
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_GPIOA_PERIPH_LOWPOWER - CRM_GPIOB_PERIPH_LOWPOWER - CRM_GPIOC_PERIPH_LOWPOWER - CRM_GPIOD_PERIPH_LOWPOWER
+ * - CRM_GPIOE_PERIPH_LOWPOWER - CRM_GPIOF_PERIPH_LOWPOWER - CRM_GPIOG_PERIPH_LOWPOWER - CRM_GPIOH_PERIPH_LOWPOWER
+ * - CRM_CRC_PERIPH_LOWPOWER - CRM_EDMA_PERIPH_LOWPOWER - CRM_DMA1_PERIPH_LOWPOWER - CRM_DMA2_PERIPH_LOWPOWER
+ * - CRM_EMAC_PERIPH_LOWPOWER - CRM_EMACTX_PERIPH_LOWPOWER - CRM_EMACRX_PERIPH_LOWPOWER - CRM_EMACPTP_PERIPH_LOWPOWER
+ * - CRM_OTGFS2_PERIPH_LOWPOWER - CRM_DVP_PERIPH_LOWPOWER - CRM_OTGFS1_PERIPH_LOWPOWER - CRM_SDIO1_PERIPH_LOWPOWER
+ * - CRM_XMC_PERIPH_LOWPOWER - CRM_QSPI1_PERIPH_LOWPOWER - CRM_QSPI2_PERIPH_LOWPOWER - CRM_SDIO2_PERIPH_LOWPOWER
+ * - CRM_TMR2_PERIPH_LOWPOWER - CRM_TMR3_PERIPH_LOWPOWER - CRM_TMR4_PERIPH_LOWPOWER - CRM_TMR5_PERIPH_LOWPOWER
+ * - CRM_TMR6_PERIPH_LOWPOWER - CRM_TMR7_PERIPH_LOWPOWER - CRM_TMR12_PERIPH_LOWPOWER - CRM_TMR13_PERIPH_LOWPOWER
+ * - CRM_TMR14_PERIPH_LOWPOWER - CRM_WWDT_PERIPH_LOWPOWER - CRM_SPI2_PERIPH_LOWPOWER - CRM_SPI3_PERIPH_LOWPOWER
+ * - CRM_USART2_PERIPH_LOWPOWER - CRM_USART3_PERIPH_LOWPOWER - CRM_UART4_PERIPH_LOWPOWER - CRM_UART5_PERIPH_LOWPOWER
+ * - CRM_I2C1_PERIPH_LOWPOWER - CRM_I2C2_PERIPH_LOWPOWER - CRM_I2C3_PERIPH_LOWPOWER - CRM_CAN1_PERIPH_LOWPOWER
+ * - CRM_CAN2_PERIPH_LOWPOWER - CRM_PWC_PERIPH_LOWPOWER - CRM_DAC_PERIPH_LOWPOWER - CRM_UART7_PERIPH_LOWPOWER
+ * - CRM_UART8_PERIPH_LOWPOWER - CRM_TMR1_PERIPH_LOWPOWER - CRM_TMR8_PERIPH_LOWPOWER - CRM_USART1_PERIPH_LOWPOWER
+ * - CRM_USART6_PERIPH_LOWPOWER - CRM_ADC1_PERIPH_LOWPOWER - CRM_ADC2_PERIPH_LOWPOWER - CRM_ADC3_PERIPH_LOWPOWER
+ * - CRM_SPI1_PERIPH_LOWPOWER - CRM_SPI4_PERIPH_LOWPOWER - CRM_SCFG_PERIPH_LOWPOWER - CRM_TMR9_PERIPH_LOWPOWER
+ * - CRM_TMR10_PERIPH_LOWPOWER - CRM_TMR11_PERIPH_LOWPOWER - CRM_TMR20_PERIPH_LOWPOWER - CRM_ACC_PERIPH_LOWPOWER
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_periph_lowpower_mode_enable(crm_periph_clock_lowpower_type value, confirm_state new_state)
+{
+ /* enable periph clock in lowpower mode */
+ if(new_state == TRUE)
+ {
+ CRM_REG(value) |= (CRM_REG_BIT(value));
+ }
+ /* disable periph clock in lowpower mode */
+ else
+ {
+ CRM_REG(value) &= ~(CRM_REG_BIT(value));
+ }
+}
+
+/**
+ * @brief enable or disable the crm clock source
+ * @param source
+ * this parameter can be one of the following values:
+ * - CRM_CLOCK_SOURCE_HICK
+ * - CRM_CLOCK_SOURCE_HEXT
+ * - CRM_CLOCK_SOURCE_PLL
+ * - CRM_CLOCK_SOURCE_LEXT
+ * - CRM_CLOCK_SOURCE_LICK
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state)
+{
+ switch(source)
+ {
+ case CRM_CLOCK_SOURCE_HICK:
+ CRM->ctrl_bit.hicken = new_state;
+ break;
+ case CRM_CLOCK_SOURCE_HEXT:
+ CRM->ctrl_bit.hexten = new_state;
+ break;
+ case CRM_CLOCK_SOURCE_PLL:
+ CRM->ctrl_bit.pllen = new_state;
+ break;
+ case CRM_CLOCK_SOURCE_LEXT:
+ CRM->bpdc_bit.lexten = new_state;
+ break;
+ case CRM_CLOCK_SOURCE_LICK:
+ CRM->ctrlsts_bit.licken = new_state;
+ break;
+ default: break;
+ }
+}
+
+/**
+ * @brief clear the crm reset flags
+ * @param flag
+ * this parameter can be one of the following values:
+ * reset flag:
+ * - CRM_PIN_RESET_FLAG
+ * - CRM_POR_RESET_FLAG
+ * - CRM_SW_RESET_FLAG
+ * - CRM_WDT_RESET_FLAG
+ * - CRM_WWDT_RESET_FLAG
+ * - CRM_LOWPOWER_RESET_FLAG
+ * interrupt flag:
+ * - CRM_LICK_READY_INT_FLAG
+ * - CRM_LEXT_READY_INT_FLAG
+ * - CRM_HICK_READY_INT_FLAG
+ * - CRM_HEXT_READY_INT_FLAG
+ * - CRM_PLL_READY_INT_FLAG
+ * - CRM_CLOCK_FAILURE_INT_FLAG
+ * @retval none
+ */
+void crm_flag_clear(uint32_t flag)
+{
+ switch(flag)
+ {
+ case CRM_NRST_RESET_FLAG:
+ case CRM_POR_RESET_FLAG:
+ case CRM_SW_RESET_FLAG:
+ case CRM_WDT_RESET_FLAG:
+ case CRM_WWDT_RESET_FLAG:
+ case CRM_LOWPOWER_RESET_FLAG:
+ CRM->ctrlsts_bit.rstfc = TRUE;
+ break;
+ case CRM_LICK_READY_INT_FLAG:
+ CRM->clkint_bit.lickstblfc = TRUE;
+ break;
+ case CRM_LEXT_READY_INT_FLAG:
+ CRM->clkint_bit.lextstblfc = TRUE;
+ break;
+ case CRM_HICK_READY_INT_FLAG:
+ CRM->clkint_bit.hickstblfc = TRUE;
+ break;
+ case CRM_HEXT_READY_INT_FLAG:
+ CRM->clkint_bit.hextstblfc = TRUE;
+ break;
+ case CRM_PLL_READY_INT_FLAG:
+ CRM->clkint_bit.pllstblfc = TRUE;
+ break;
+ case CRM_CLOCK_FAILURE_INT_FLAG:
+ CRM->clkint_bit.cfdfc = TRUE;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief select ertc clock
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_ERTC_CLOCK_NOCLK
+ * - CRM_ERTC_CLOCK_LEXT
+ * - CRM_ERTC_CLOCK_LICK
+ * - CRM_ERTC_CLOCK_HEXT_DIV_2
+ * - CRM_ERTC_CLOCK_HEXT_DIV_3
+ * - CRM_ERTC_CLOCK_HEXT_DIV_4
+ * - CRM_ERTC_CLOCK_HEXT_DIV_5
+ * - CRM_ERTC_CLOCK_HEXT_DIV_6
+ * - CRM_ERTC_CLOCK_HEXT_DIV_7
+ * - CRM_ERTC_CLOCK_HEXT_DIV_8
+ * - CRM_ERTC_CLOCK_HEXT_DIV_9
+ * - CRM_ERTC_CLOCK_HEXT_DIV_10
+ * - CRM_ERTC_CLOCK_HEXT_DIV_11
+ * - CRM_ERTC_CLOCK_HEXT_DIV_12
+ * - CRM_ERTC_CLOCK_HEXT_DIV_13
+ * - CRM_ERTC_CLOCK_HEXT_DIV_14
+ * - CRM_ERTC_CLOCK_HEXT_DIV_15
+ * - CRM_ERTC_CLOCK_HEXT_DIV_16
+ * - CRM_ERTC_CLOCK_HEXT_DIV_17
+ * - CRM_ERTC_CLOCK_HEXT_DIV_18
+ * - CRM_ERTC_CLOCK_HEXT_DIV_19
+ * - CRM_ERTC_CLOCK_HEXT_DIV_20
+ * - CRM_ERTC_CLOCK_HEXT_DIV_21
+ * - CRM_ERTC_CLOCK_HEXT_DIV_22
+ * - CRM_ERTC_CLOCK_HEXT_DIV_23
+ * - CRM_ERTC_CLOCK_HEXT_DIV_24
+ * - CRM_ERTC_CLOCK_HEXT_DIV_25
+ * - CRM_ERTC_CLOCK_HEXT_DIV_26
+ * - CRM_ERTC_CLOCK_HEXT_DIV_27
+ * - CRM_ERTC_CLOCK_HEXT_DIV_28
+ * - CRM_ERTC_CLOCK_HEXT_DIV_29
+ * - CRM_ERTC_CLOCK_HEXT_DIV_30
+ * - CRM_ERTC_CLOCK_HEXT_DIV_31
+ * @retval none
+ */
+void crm_ertc_clock_select(crm_ertc_clock_type value)
+{
+ CRM->cfg_bit.ertcdiv = ((value & 0x1F0) >> 4);
+ CRM->bpdc_bit.ertcsel = (value & 0xF);
+}
+
+/**
+ * @brief enable or disable ertc
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_ertc_clock_enable(confirm_state new_state)
+{
+ CRM->bpdc_bit.ertcen = new_state;
+}
+
+/**
+ * @brief set crm ahb division
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_AHB_DIV_1
+ * - CRM_AHB_DIV_2
+ * - CRM_AHB_DIV_4
+ * - CRM_AHB_DIV_8
+ * - CRM_AHB_DIV_16
+ * - CRM_AHB_DIV_64
+ * - CRM_AHB_DIV_128
+ * - CRM_AHB_DIV_256
+ * - CRM_AHB_DIV_512
+ * @retval none
+ */
+void crm_ahb_div_set(crm_ahb_div_type value)
+{
+ CRM->cfg_bit.ahbdiv = value;
+}
+
+/**
+ * @brief set crm apb1 division
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_APB1_DIV_1
+ * - CRM_APB1_DIV_2
+ * - CRM_APB1_DIV_4
+ * - CRM_APB1_DIV_8
+ * - CRM_APB1_DIV_16
+ * @retval none
+ */
+void crm_apb1_div_set(crm_apb1_div_type value)
+{
+ CRM->cfg_bit.apb1div = value;
+}
+
+/**
+ * @brief set crm apb2 division
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_APB2_DIV_1
+ * - CRM_APB2_DIV_2
+ * - CRM_APB2_DIV_4
+ * - CRM_APB2_DIV_8
+ * - CRM_APB2_DIV_16
+ * @retval none
+ */
+void crm_apb2_div_set(crm_apb2_div_type value)
+{
+ CRM->cfg_bit.apb2div = value;
+}
+
+/**
+ * @brief set usb division
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_USB_DIV_1_5
+ * - CRM_USB_DIV_1
+ * - CRM_USB_DIV_2_5
+ * - CRM_USB_DIV_2
+ * - CRM_USB_DIV_3_5
+ * - CRM_USB_DIV_3
+ * - CRM_USB_DIV_4_5
+ * - CRM_USB_DIV_4
+ * - CRM_USB_DIV_5_5
+ * - CRM_USB_DIV_5
+ * - CRM_USB_DIV_6_5
+ * - CRM_USB_DIV_6
+ * - CRM_USB_DIV_7
+ * @retval none
+ */
+void crm_usb_clock_div_set(crm_usb_div_type value)
+{
+ CRM->misc2_bit.usbdiv = value;
+}
+
+/**
+ * @brief enable or disable clock failure detection
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_clock_failure_detection_enable(confirm_state new_state)
+{
+ CRM->ctrl_bit.cfden = new_state;
+}
+
+/**
+ * @brief battery powered domain software reset
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_battery_powered_domain_reset(confirm_state new_state)
+{
+ CRM->bpdc_bit.bpdrst = new_state;
+}
+
+/**
+ * @brief auto step clock switch enable
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_auto_step_mode_enable(confirm_state new_state)
+{
+ if(new_state == TRUE)
+ CRM->misc2_bit.auto_step_en = CRM_AUTO_STEP_MODE_ENABLE;
+ else
+ CRM->misc2_bit.auto_step_en = CRM_AUTO_STEP_MODE_DISABLE;
+}
+
+/**
+ * @brief config hick divider select
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_HICK48_DIV6
+ * - CRM_HICK48_NODIV
+ * @retval none
+ */
+void crm_hick_divider_select(crm_hick_div_6_type value)
+{
+ CRM->misc1_bit.hickdiv = value;
+}
+
+/**
+ * @brief hick as system clock frequency select
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_HICK_SCLK_8MHZ
+ * - CRM_HICK_SCLK_48MHZ
+ * @retval none
+ */
+void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value)
+{
+ crm_hick_divider_select(CRM_HICK48_NODIV);
+ CRM->misc1_bit.hick_to_sclk = value;
+}
+
+/**
+ * @brief usb 48 mhz clock source select
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_USB_CLOCK_SOURCE_PLL
+ * - CRM_USB_CLOCK_SOURCE_HICK
+ * @retval none
+ */
+void crm_usb_clock_source_select(crm_usb_clock_source_type value)
+{
+ if(value == CRM_USB_CLOCK_SOURCE_HICK)
+ {
+ crm_hick_sclk_frequency_select(CRM_HICK_SCLK_48MHZ);
+ }
+ CRM->misc1_bit.hick_to_usb = value;
+}
+
+/**
+ * @brief enable or disable clkout direct to tmr10 channel 1
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_clkout_to_tmr10_enable(confirm_state new_state)
+{
+ CRM->misc2_bit.clk_to_tmr = new_state;
+}
+
+/**
+ * @brief config crm pll
+ * pll_rcs_freq * pll_ns
+ * pll clock = --------------------------------
+ * pll_ms * pll_fr_n
+ * attemtion:
+ * 31 <= pll_ns <= 500
+ * 1 <= pll_ms <= 15
+ *
+ * pll_rcs_freq
+ * 2mhz <= ---------------------- <= 16mhz
+ * pll_ms
+ *
+ * pll_rcs_freq * pll_ns
+ * 500mhz <= -------------------------------- <= 1000mhz
+ * pll_ms
+ * @param clock_source
+ * this parameter can be one of the following values:
+ * - CRM_PLL_SOURCE_HICK
+ * - CRM_PLL_SOURCE_HEXT
+ * @param pll_ns (31~500)
+ * @param pll_ms (1~15)
+ * @param pll_fr
+ * this parameter can be one of the following values:
+ * - CRM_PLL_FR_1
+ * - CRM_PLL_FR_2
+ * - CRM_PLL_FR_4
+ * - CRM_PLL_FR_8
+ * - CRM_PLL_FR_16
+ * - CRM_PLL_FR_32
+ * @retval none
+ */
+void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \
+ uint16_t pll_ms, crm_pll_fr_type pll_fr)
+{
+ /* config pll clock source */
+ CRM->pllcfg_bit.pllrcs = clock_source;
+
+ /* config pll multiplication factor */
+ CRM->pllcfg_bit.pllns = pll_ns;
+ CRM->pllcfg_bit.pllms = pll_ms;
+ CRM->pllcfg_bit.pllfr = pll_fr;
+}
+
+/**
+ * @brief select system clock source
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_SCLK_HICK
+ * - CRM_SCLK_HEXT
+ * - CRM_SCLK_PLL
+ * @retval none
+ */
+void crm_sysclk_switch(crm_sclk_type value)
+{
+ CRM->cfg_bit.sclksel = value;
+}
+
+/**
+ * @brief indicate which clock source is used as system clock
+ * @param none
+ * @retval crm_sclk
+ * this return can be one of the following values:
+ * - CRM_SCLK_HICK
+ * - CRM_SCLK_HEXT
+ * - CRM_SCLK_PLL
+ */
+crm_sclk_type crm_sysclk_switch_status_get(void)
+{
+ return (crm_sclk_type)CRM->cfg_bit.sclksts;
+}
+
+/**
+ * @brief get crm clocks freqency
+ * @param clocks_struct
+ * - pointer to the crm_clocks_freq_type structure
+ * @retval none
+ */
+void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct)
+{
+ uint32_t pll_ns = 0, pll_ms = 0, pll_fr = 0, pll_clock_source = 0, pllrcsfreq = 0;
+ uint32_t temp = 0, div_value = 0;
+ crm_sclk_type sclk_source;
+
+ static const uint8_t sclk_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+ static const uint8_t ahb_apb1_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+ static const uint8_t ahb_apb2_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+ static const uint8_t pll_fr_table[6] = {1, 2, 4, 8, 16, 32};
+
+ /* get sclk source */
+ sclk_source = crm_sysclk_switch_status_get();
+
+ switch(sclk_source)
+ {
+ case CRM_SCLK_HICK:
+ if(((CRM->misc1_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
+ clocks_struct->sclk_freq = HICK_VALUE * 6;
+ else
+ clocks_struct->sclk_freq = HICK_VALUE;
+ break;
+ case CRM_SCLK_HEXT:
+ clocks_struct->sclk_freq = HEXT_VALUE;
+ break;
+ case CRM_SCLK_PLL:
+ /* get pll clock source */
+ pll_clock_source = CRM->pllcfg_bit.pllrcs;
+
+ /* get multiplication factor */
+ pll_ns = CRM->pllcfg_bit.pllns;
+ pll_ms = CRM->pllcfg_bit.pllms;
+ pll_fr = pll_fr_table[CRM->pllcfg_bit.pllfr];
+
+ if (pll_clock_source == CRM_PLL_SOURCE_HICK)
+ {
+ /* hick selected as pll clock entry */
+ pllrcsfreq = HICK_VALUE;
+ }
+ else
+ {
+ /* hext selected as pll clock entry */
+ pllrcsfreq = HEXT_VALUE;
+ }
+
+ clocks_struct->sclk_freq = (pllrcsfreq * pll_ns) / (pll_ms * pll_fr);
+ break;
+ default:
+ clocks_struct->sclk_freq = HICK_VALUE;
+ break;
+ }
+
+ /* compute sclk, ahbclk, abp1clk and apb2clk frequencies */
+ /* get ahb division */
+ temp = CRM->cfg_bit.ahbdiv;
+ div_value = sclk_ahb_div_table[temp];
+ /* ahbclk frequency */
+ clocks_struct->ahb_freq = clocks_struct->sclk_freq >> div_value;
+
+ /* get apb1 division */
+ temp = CRM->cfg_bit.apb1div;
+ div_value = ahb_apb1_div_table[temp];
+ /* apb1clk frequency */
+ clocks_struct->apb1_freq = clocks_struct->ahb_freq >> div_value;
+
+ /* get apb2 division */
+ temp = CRM->cfg_bit.apb2div;
+ div_value = ahb_apb2_div_table[temp];
+ /* apb2clk frequency */
+ clocks_struct->apb2_freq = clocks_struct->ahb_freq >> div_value;
+}
+
+/**
+ * @brief set crm clkout1
+ * @param clkout
+ * this parameter can be one of the following values:
+ * - CRM_CLKOUT1_HICK
+ * - CRM_CLKOUT1_LEXT
+ * - CRM_CLKOUT1_HEXT
+ * - CRM_CLKOUT1_PLL
+ * @retval none
+ */
+void crm_clock_out1_set(crm_clkout1_select_type clkout)
+{
+ CRM->cfg_bit.clkout1_sel = clkout;
+}
+
+/**
+ * @brief set crm clkout2
+ * @param clkout
+ * this parameter can be one of the following values:
+ * - CRM_CLKOUT2_SCLK
+ * - CRM_CLKOUT2_HEXT
+ * - CRM_CLKOUT2_PLL
+ * - CRM_CLKOUT2_USB
+ * - CRM_CLKOUT2_ADC
+ * - CRM_CLKOUT2_HICK
+ * - CRM_CLKOUT2_LICK
+ * - CRM_CLKOUT2_LEXT
+ * @retval none
+ */
+void crm_clock_out2_set(crm_clkout2_select_type clkout)
+{
+ if(clkout < 0x10)
+ {
+ CRM->cfg_bit.clkout2_sel1 = (clkout & 0x3);
+ }
+ else
+ {
+ CRM->cfg_bit.clkout2_sel1 = 0x1;
+ CRM->misc1_bit.clkout2_sel2 = (clkout & 0xF);
+ }
+}
+
+/**
+ * @brief set crm clkout1 division1
+ * @param div1
+ * this parameter can be one of the following values:
+ * - CRM_CLKOUT_INDEX_1
+ * - CRM_CLKOUT_INDEX_2
+ * @param div1
+ * this parameter can be one of the following values:
+ * - CRM_CLKOUT_DIV1_1
+ * - CRM_CLKOUT_DIV1_2
+ * - CRM_CLKOUT_DIV1_3
+ * - CRM_CLKOUT_DIV1_4
+ * - CRM_CLKOUT_DIV1_5
+ * @param div2
+ * this parameter can be one of the following values:
+ * - CRM_CLKOUT_DIV2_1
+ * - CRM_CLKOUT_DIV2_2
+ * - CRM_CLKOUT_DIV2_4
+ * - CRM_CLKOUT_DIV2_8
+ * - CRM_CLKOUT_DIV2_16
+ * - CRM_CLKOUT_DIV2_64
+ * - CRM_CLKOUT_DIV2_128
+ * - CRM_CLKOUT_DIV2_256
+ * - CRM_CLKOUT_DIV2_512
+ * @retval none
+ */
+void crm_clkout_div_set(crm_clkout_index_type index, crm_clkout_div1_type div1, crm_clkout_div2_type div2)
+{
+ if(index == CRM_CLKOUT_INDEX_1)
+ {
+ CRM->cfg_bit.clkout1div1 = div1;
+ CRM->misc1_bit.clkout1div2 = div2;
+ }
+ else
+ {
+ CRM->cfg_bit.clkout2div1 = div1;
+ CRM->misc1_bit.clkout2div2 = div2;
+ }
+}
+
+/**
+ * @brief set emac output pulse width
+ * @param width
+ * this parameter can be one of the following values:
+ * - CRM_EMAC_PULSE_125MS
+ * - CRM_EMAC_PULSE_1SCLK
+ * @retval none
+ */
+void crm_emac_output_pulse_set(crm_emac_output_pulse_type width)
+{
+ CRM->misc2_bit.emac_pps_sel = width;
+}
+
+/**
+ * @brief config crm interrupt
+ * @param int
+ * this parameter can be any combination of the following values:
+ * - CRM_LICK_STABLE_INT
+ * - CRM_LEXT_STABLE_INT
+ * - CRM_HICK_STABLE_INT
+ * - CRM_HEXT_STABLE_INT
+ * - CRM_PLL_STABLE_INT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state)
+{
+ if(TRUE == new_state)
+ CRM->clkint |= crm_int;
+ else
+ CRM->clkint &= ~crm_int;
+}
+
+/**
+ * @brief calculate the pll parameters with pll reference clock and target pll output frequency.
+ * pll_rcs_freq * pll_ns
+ * pll clock = --------------------------------
+ * pll_ms * pll_fr_n
+ * attemtion:
+ * 31 <= pll_ns <= 500
+ * 1 <= pll_ms <= 15
+ *
+ * pll_rcs_freq
+ * 2mhz <= ---------------------- <= 16mhz
+ * pll_ms
+ *
+ * pll_rcs_freq * pll_ns
+ * 500mhz <= -------------------------------- <= 1000mhz
+ * pll_ms
+ * @param pll_rcs
+ * this parameter can be one of the following values:
+ * - CRM_PLL_SOURCE_HICK
+ * - CRM_PLL_SOURCE_HEXT
+ * @param target_sclk_freq: target pll output frequency, such as 200 mhz (target_sclk_freq: 200000000)
+ * @param ret_ms: pointer to ms value, return the pll_ms of pll parameters
+ * @param ret_ns: pointer to ns value, return the pll_ns of pll parameters
+ * @param ret_fr: pointer to fr value, return the pll_fr of pll parameters
+ * @retval error_status (SUCCESS or ERROR)
+ */
+error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint32_t target_sclk_freq, \
+ uint16_t *ret_ms, uint16_t *ret_ns, uint16_t *ret_fr)
+{
+ uint32_t pll_rcs_freq = 0, ns = 0, ms = 0, fr = 0;
+ uint32_t ms_min = 0, ms_max = 0, error_min = 0xFFFFFFFF;
+ uint32_t result = 0, absolute_value = 0;
+
+ /* reduce calculate accuracy, target_sclk_freq accuracy with khz */
+ target_sclk_freq = target_sclk_freq / 1000;
+
+ /* get pll reference clock frequency, accuracy with khz */
+ if(pll_rcs == CRM_PLL_SOURCE_HICK)
+ pll_rcs_freq = HICK_VALUE / 1000;
+ else
+ pll_rcs_freq = HEXT_VALUE / 1000;
+
+ /* polling ms range, accuracy with khz */
+ for(ms = 1; ms <= 15; ms ++)
+ {
+ result = pll_rcs_freq / ms;
+ if((result >= 2000U) && (result <= 16000U))
+ {
+ if(ms_min == 0)
+ ms_min = ms;
+
+ ms_max = ms;
+ }
+ }
+
+ /* polling pll parameters */
+ for(ms = ms_min; ms <= ms_max; ms ++)
+ {
+ for(fr = 0; fr <= 5; fr ++)
+ {
+ for(ns = 31; ns <= 500; ns ++)
+ {
+ result = (pll_rcs_freq * ns) / (ms);
+ /* check vco frequency range, accuracy with khz */
+ if((result < 500000U) || (result > 1000000U))
+ {
+ continue;
+ }
+ /* calculate pll output frequency */
+ result = result / (0x1 << fr);
+ /* check frequency */
+ if(target_sclk_freq == result)
+ {
+ *ret_ms = ms;
+ *ret_ns = ns;
+ *ret_fr = fr;
+ /* the pll parameters that is equal to target_sclk_freq */
+ return SUCCESS;
+ }
+ /* calculate error range, accuracy with khz */
+ absolute_value = (result > target_sclk_freq) ? (result - target_sclk_freq) : (target_sclk_freq - result);
+ if(absolute_value < error_min)
+ {
+ error_min = absolute_value;
+ *ret_ms = ms;
+ *ret_ns = ns;
+ *ret_fr = fr;
+ }
+ }
+ }
+ }
+ /* the pll parameters that is the closest approach to target_sclk_freq */
+ return ERROR;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_dac.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_dac.c
new file mode 100644
index 0000000..e116b50
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_dac.c
@@ -0,0 +1,454 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_dac.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the dac firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+#ifdef DAC_MODULE_ENABLED
+
+/** @defgroup DAC_private_functions
+ * @{
+ */
+
+/**
+ * @brief dac reset
+ * @param none
+ * @retval none
+ */
+void dac_reset(void)
+{
+ crm_periph_reset(CRM_DAC_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_DAC_PERIPH_RESET, FALSE);
+}
+
+/**
+ * @brief enable or disable dac
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dac_enable(dac_select_type dac_select, confirm_state new_state)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->ctrl_bit.d1en = new_state;
+ break;
+ case DAC2_SELECT:
+ DAC->ctrl_bit.d2en = new_state;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief enable or disable dac output buffer
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dac_output_buffer_enable(dac_select_type dac_select, confirm_state new_state)
+{
+ new_state = (confirm_state)!new_state;
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->ctrl_bit.d1obdis = new_state;
+ break;
+ case DAC2_SELECT:
+ DAC->ctrl_bit.d2obdis = new_state;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief enable or disable dac trigger
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dac_trigger_enable(dac_select_type dac_select, confirm_state new_state)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->ctrl_bit.d1trgen = new_state;
+ break;
+ case DAC2_SELECT:
+ DAC->ctrl_bit.d2trgen = new_state;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief select dac trigger
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @param dac_trigger_select
+ * this parameter can be one of the following values:
+ * - DAC_TMR6_TRGOUT_EVENT
+ * - DAC_TMR8_TRGOUT_EVENT
+ * - DAC_TMR7_TRGOUT_EVENT
+ * - DAC_TMR5_TRGOUT_EVENT
+ * - DAC_TMR2_TRGOUT_EVENT
+ * - DAC_TMR4_TRGOUT_EVENT
+ * - DAC_EXTERNAL_INTERRUPT_LINE_9
+ * - DAC_SOFTWARE_TRIGGER
+ * @retval none
+ */
+void dac_trigger_select(dac_select_type dac_select, dac_trigger_type dac_trigger_select)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->ctrl_bit.d1trgsel = dac_trigger_select;
+ break;
+ case DAC2_SELECT:
+ DAC->ctrl_bit.d2trgsel = dac_trigger_select;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief generate dac software trigger
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @retval none
+ */
+void dac_software_trigger_generate(dac_select_type dac_select)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->swtrg_bit.d1swtrg = TRUE;
+ break;
+ case DAC2_SELECT:
+ DAC->swtrg_bit.d2swtrg = TRUE;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief generate dac dual software trigger synchronously
+ * @param none
+ * @retval none
+ */
+void dac_dual_software_trigger_generate(void)
+{
+ DAC->swtrg |= 0x03;
+}
+
+/**
+ * @brief generate dac wave
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @param dac_wave
+ * this parameter can be one of the following values:
+ * - DAC_WAVE_GENERATE_NONE
+ * - DAC_WAVE_GENERATE_NOISE
+ * - DAC_WAVE_GENERATE_TRIANGLE
+ * @retval none
+ */
+void dac_wave_generate(dac_select_type dac_select, dac_wave_type dac_wave)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->ctrl_bit.d1nm = dac_wave;
+ break;
+ case DAC2_SELECT:
+ DAC->ctrl_bit.d2nm = dac_wave;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief select dac mask amplitude
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @param dac_mask_amplitude
+ * this parameter can be one of the following values:
+ * - DAC_LSFR_BIT0_AMPLITUDE_1
+ * - DAC_LSFR_BIT10_AMPLITUDE_3
+ * - DAC_LSFR_BIT20_AMPLITUDE_7
+ * - DAC_LSFR_BIT30_AMPLITUDE_15
+ * - DAC_LSFR_BIT40_AMPLITUDE_31
+ * - DAC_LSFR_BIT50_AMPLITUDE_63
+ * - DAC_LSFR_BIT60_AMPLITUDE_127
+ * - DAC_LSFR_BIT70_AMPLITUDE_255
+ * - DAC_LSFR_BIT80_AMPLITUDE_511
+ * - DAC_LSFR_BIT90_AMPLITUDE_1023
+ * - DAC_LSFR_BITA0_AMPLITUDE_2047
+ * - DAC_LSFR_BITB0_AMPLITUDE_4095
+ * @retval none
+ */
+void dac_mask_amplitude_select(dac_select_type dac_select, dac_mask_amplitude_type dac_mask_amplitude)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->ctrl_bit.d1nbsel = dac_mask_amplitude;
+ break;
+ case DAC2_SELECT:
+ DAC->ctrl_bit.d2nbsel = dac_mask_amplitude;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief enable or disable dac dma
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dac_dma_enable(dac_select_type dac_select, confirm_state new_state)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->ctrl_bit.d1dmaen = new_state;
+ break;
+ case DAC2_SELECT:
+ DAC->ctrl_bit.d2dmaen = new_state;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief get dac data output
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @retval dac channel data output
+ */
+uint16_t dac_data_output_get(dac_select_type dac_select)
+{
+ uint16_t data_output =0;
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ data_output = DAC->d1odt_bit.d1odt;
+ break;
+ case DAC2_SELECT:
+ data_output = DAC->d2odt_bit.d2odt;
+ break;
+ default:
+ break;
+ }
+ return data_output;
+}
+
+/**
+ * @brief set dac1 data
+ * @param dac1_aligned
+ * this parameter can be one of the following values:
+ * DAC1_12BIT_RIGHT
+ * DAC1_12BIT_LEFT
+ * DAC1_8BIT_RIGHT
+ * @param dac1_data :indecate from selected data holding register
+ * @retval none
+ */
+void dac_1_data_set(dac1_aligned_data_type dac1_aligned, uint16_t dac1_data)
+{
+ *(__IO uint32_t *) dac1_aligned = dac1_data;
+}
+
+/**
+ * @brief set dac2 data
+ * @param dac2_aligned
+ * this parameter can be one of the following values:
+ * DAC2_12BIT_RIGHT
+ * DAC2_12BIT_LEFT
+ * DAC2_8BIT_RIGHT
+ * @param dac2_data :indecate from selected data holding register
+ * @retval none
+ */
+void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data)
+{
+ *(__IO uint32_t *) dac2_aligned = dac2_data;
+}
+
+/**
+ * @brief set dac dual data
+ * @param dac_dual
+ * this parameter can be one of the following values:
+ * DAC_DUAL_12BIT_RIGHT
+ * DAC_DUAL_12BIT_LEFT
+ * DAC_DUAL_8BIT_RIGHT
+ * @param data1 :dac1 channel indecate from selected data holding register
+ * @param data2 :dac1 channel indecate from selected data holding register
+ * @retval none
+ */
+void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2)
+{
+ switch(dac_dual)
+ {
+ case DAC_DUAL_12BIT_RIGHT:
+ *(__IO uint32_t *) dac_dual = (uint32_t)(data1 | (data2 << 16));
+ break;
+ case DAC_DUAL_12BIT_LEFT:
+ *(__IO uint32_t *) dac_dual = (uint32_t)(data1 | (data2 << 16));
+ break;
+ case DAC_DUAL_8BIT_RIGHT:
+ *(__IO uint32_t *) dac_dual = (uint32_t)(data1 | (data2 << 8));
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief enable/disable dac dma udr interrupt
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dac_udr_enable(dac_select_type dac_select, confirm_state new_state)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->ctrl_bit.d1dmaudrien = new_state;
+ break;
+ case DAC2_SELECT:
+ DAC->ctrl_bit.d2dmaudrien = new_state;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief get flag of the dac udr flag.
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @retval the new state of dac udr flag status(SET or RESET).
+ */
+flag_status dac_udr_flag_get(dac_select_type dac_select)
+{
+ flag_status status = RESET;
+
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ if(DAC->sts_bit.d1dmaudrf != 0)
+ status = SET;
+ break;
+ case DAC2_SELECT:
+ if(DAC->sts_bit.d2dmaudrf != 0)
+ status = SET;
+ break;
+ default:
+ break;
+ }
+ return status;
+}
+
+/**
+ * @brief clear the dac udr flag.
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @retval none
+ */
+void dac_udr_flag_clear(dac_select_type dac_select)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->sts = DAC1_D1DMAUDRF;
+ break;
+ case DAC2_SELECT:
+ DAC->sts = DAC2_D2DMAUDRF;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_debug.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_debug.c
new file mode 100644
index 0000000..7426f48
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_debug.c
@@ -0,0 +1,135 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_mcudbg.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the mcudbg firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup DEBUG
+ * @brief DEBUG driver modules
+ * @{
+ */
+
+#ifdef DEBUG_MODULE_ENABLED
+
+/** @defgroup DEBUG_private_functions
+ * @{
+ */
+
+/**
+ * @brief get debug device id
+ * @param none
+ * @retval the debug device id
+ */
+uint32_t debug_device_id_get(void)
+{
+ return DEBUGMCU->pid;
+}
+/**
+ * @brief set periph debug mode
+ * @param periph_debug_mode
+ * this parameter can be one of the following values:
+ * - DEBUG_SLEEP
+ * - DEBUG_DEEPSLEEP
+ * - DEBUG_STANDBY
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void debug_low_power_mode_set(uint32_t low_power_mode, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ DEBUGMCU->ctrl |= low_power_mode;
+ }
+ else
+ {
+ DEBUGMCU->ctrl &= ~low_power_mode;
+ }
+}
+/**
+ * @brief set apb1 periph debug mode
+ * @param periph_debug_mode
+ * this parameter can be any combination of the following values:
+ * - DEBUG_TMR2_PAUSE - DEBUG_TMR3_PAUSE
+ * - DEBUG_TMR4_PAUSE - DEBUG_TMR5_PAUSE
+ * - DEBUG_TMR6_PAUSE - DEBUG_TMR7_PAUSE
+ * - DEBUG_TMR12_PAUSE - DEBUG_TMR13_PAUSE
+ * - DEBUG_TMR14_PAUSE - DEBUG_ERTC_PAUSE
+ * - DEBUG_WWDT_PAUSE - DEBUG_WDT_PAUSE
+ * - DEBUG_ERTC_512_PAUSE - DEBUG_I2C1_SMBUS_TIMEOUT
+ * - DEBUG_I2C2_SMBUS_TIMEOUT - DEBUG_I2C3_SMBUS_TIMEOUT
+ * - DEBUG_CAN1_PAUSE - DEBUG_CAN2_PAUSE
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void debug_apb1_periph_mode_set(uint32_t apb1_periph, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ DEBUGMCU->apb1_frz |= apb1_periph;
+ }
+ else
+ {
+ DEBUGMCU->apb1_frz &= ~apb1_periph;
+ }
+}
+/**
+ * @brief set apb2 periph debug mode
+ * @param periph_debug_mode
+ * this parameter can be any combination of the following values:
+ * - DEBUG_TMR1_PAUSE - DEBUG_TMR8_PAUSE
+ * - DEBUG_TMR20_PAUSE - DEBUG_TMR9_PAUSE
+ * - DEBUG_TMR10_PAUSE - DEBUG_TMR11_PAUSE
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void debug_apb2_periph_mode_set(uint32_t apb2_periph, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ DEBUGMCU->apb2_frz |= apb2_periph;
+ }
+ else
+ {
+ DEBUGMCU->apb2_frz &= ~apb2_periph;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_dma.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_dma.c
new file mode 100644
index 0000000..287c598
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_dma.c
@@ -0,0 +1,683 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_dma.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the dma firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup DMA
+ * @brief DMA driver modules
+ * @{
+ */
+
+#ifdef DMA_MODULE_ENABLED
+
+/** @defgroup DMA_private_functions
+ * @{
+ */
+
+/**
+ * @brief reset dmax channely register.
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
+ * - DMA2_CHANNEL1
+ * - DMA2_CHANNEL2
+ * - DMA2_CHANNEL3
+ * - DMA2_CHANNEL4
+ * - DMA2_CHANNEL5
+ * - DMA2_CHANNEL6
+ * - DMA2_CHANNEL7
+ * @retval none.
+ */
+void dma_reset(dma_channel_type *dmax_channely)
+{
+ uint32_t temp = 0;
+ dmax_channely->ctrl_bit.chen = FALSE;
+ dmax_channely->ctrl = 0;
+ dmax_channely->dtcnt = 0;
+ dmax_channely->paddr = 0;
+ dmax_channely->maddr = 0;
+
+ temp = (uint32_t)dmax_channely;
+
+ if((temp & 0x6FF) < 0x608)
+ {
+ /* dma1 channel */
+ DMA1->clr |= (uint32_t)(0x0F << ((((temp & 0xFF) - 0x08) / 0x14) * 4));
+ }
+ else if((temp & 0x6FF) < 0x688)
+ {
+ /* dma2 channel */
+ DMA2->clr |= (uint32_t)(0x0F << ((((temp & 0xFF) - 0x08) / 0x14) * 4));
+ }
+}
+
+/**
+ * @brief set the number of data to be transferred.
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
+ * - DMA2_CHANNEL1
+ * - DMA2_CHANNEL2
+ * - DMA2_CHANNEL3
+ * - DMA2_CHANNEL4
+ * - DMA2_CHANNEL5
+ * - DMA2_CHANNEL6
+ * - DMA2_CHANNEL7
+ * @param data_number: the number of data to be transferred (0x0000~0xFFFF).
+ * @retval none.
+ */
+void dma_data_number_set(dma_channel_type *dmax_channely, uint16_t data_number)
+{
+ dmax_channely->dtcnt = data_number;
+}
+
+/**
+ * @brief get the number of data to be transferred.
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
+ * - DMA2_CHANNEL1
+ * - DMA2_CHANNEL2
+ * - DMA2_CHANNEL3
+ * - DMA2_CHANNEL4
+ * - DMA2_CHANNEL5
+ * - DMA2_CHANNEL6
+ * - DMA2_CHANNEL7
+ * @retval the number value.
+ */
+uint16_t dma_data_number_get(dma_channel_type *dmax_channely)
+{
+ return (uint16_t)dmax_channely->dtcnt;
+}
+
+/**
+ * @brief enable or disable dma interrupt.
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
+ * - DMA2_CHANNEL1
+ * - DMA2_CHANNEL2
+ * - DMA2_CHANNEL3
+ * - DMA2_CHANNEL4
+ * - DMA2_CHANNEL5
+ * - DMA2_CHANNEL6
+ * - DMA2_CHANNEL7
+ * @param dma_int:
+ * this parameter can be any combination of the following values:
+ * - DMA_FDT_INT
+ * - DMA_HDT_INT
+ * - DMA_DTERR_INT
+ * @param new_state (TRUE or FALSE)
+ * @retval none.
+ */
+void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ dmax_channely->ctrl |= dma_int;
+ }
+ else
+ {
+ dmax_channely->ctrl &= ~dma_int;
+ }
+}
+
+/**
+ * @brief enable or disable dma channel.
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
+ * - DMA2_CHANNEL1
+ * - DMA2_CHANNEL2
+ * - DMA2_CHANNEL3
+ * - DMA2_CHANNEL4
+ * - DMA2_CHANNEL5
+ * - DMA2_CHANNEL6
+ * - DMA2_CHANNEL7
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state)
+{
+ dmax_channely->ctrl_bit.chen = new_state;
+}
+
+/**
+ * @brief dma flag get.
+ * @param dma_flag
+ * - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
+ * - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
+ * - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
+ * - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
+ * - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
+ * - DMA1_GL6_FLAG - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
+ * - DMA1_GL7_FLAG - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
+ * - DMA2_GL1_FLAG - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG
+ * - DMA2_GL2_FLAG - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG
+ * - DMA2_GL3_FLAG - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG
+ * - DMA2_GL4_FLAG - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG
+ * - DMA2_GL5_FLAG - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG
+ * - DMA2_GL6_FLAG - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG
+ * - DMA2_GL7_FLAG - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG
+ * @retval state of dma flag.
+ */
+flag_status dma_flag_get(uint32_t dmax_flag)
+{
+ uint32_t temp = 0;
+
+ if(dmax_flag > 0x10000000)
+ {
+ temp = DMA2->sts;
+ }
+ else
+ {
+ temp = DMA1->sts;
+ }
+
+ if((temp & dmax_flag) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief dma flag clear.
+ * @param dma_flag
+ * this parameter can be one of the following values:
+ * - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
+ * - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
+ * - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
+ * - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
+ * - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
+ * - DMA1_GL6_FLAG - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
+ * - DMA1_GL7_FLAG - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
+ * - DMA2_GL1_FLAG - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG
+ * - DMA2_GL2_FLAG - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG
+ * - DMA2_GL3_FLAG - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG
+ * - DMA2_GL4_FLAG - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG
+ * - DMA2_GL5_FLAG - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG
+ * - DMA2_GL6_FLAG - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG
+ * - DMA2_GL7_FLAG - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG
+ * @retval none.
+ */
+void dma_flag_clear(uint32_t dmax_flag)
+{
+ if(dmax_flag > ((uint32_t)0x10000000))
+ {
+ DMA2->clr = (uint32_t)(dmax_flag & 0x0FFFFFFF);
+ }
+ else
+ {
+ DMA1->clr = dmax_flag;
+ }
+}
+
+/**
+ * @brief dma init config with its default value.
+ * @param dma_init_struct: pointer to a dma_init_type structure which will be initialized.
+ * @retval none.
+ */
+void dma_default_para_init(dma_init_type *dma_init_struct)
+{
+ dma_init_struct->peripheral_base_addr = 0;
+ dma_init_struct->memory_base_addr = 0;
+ dma_init_struct->direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
+ dma_init_struct->buffer_size = 0;
+ dma_init_struct->peripheral_inc_enable = FALSE;
+ dma_init_struct->memory_inc_enable = FALSE;
+ dma_init_struct->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
+ dma_init_struct->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
+ dma_init_struct->loop_mode_enable = FALSE;
+ dma_init_struct->priority = DMA_PRIORITY_LOW;
+}
+
+/**
+ * @brief dma init.
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
+ * - DMA2_CHANNEL1
+ * - DMA2_CHANNEL2
+ * - DMA2_CHANNEL3
+ * - DMA2_CHANNEL4
+ * - DMA2_CHANNEL5
+ * - DMA2_CHANNEL6
+ * - DMA2_CHANNEL7
+ * @param dma_init_struct: pointer to a dma_init_type structure.
+ * @retval none.
+ */
+void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct)
+{
+ /* clear ctrl register dtd bit and m2m bit */
+ dmax_channely->ctrl &= 0xbfef;
+ dmax_channely->ctrl |= dma_init_struct->direction;
+
+ dmax_channely->ctrl_bit.chpl = dma_init_struct->priority;
+ dmax_channely->ctrl_bit.mwidth = dma_init_struct->memory_data_width;
+ dmax_channely->ctrl_bit.pwidth = dma_init_struct->peripheral_data_width;
+ dmax_channely->ctrl_bit.mincm = dma_init_struct->memory_inc_enable;
+ dmax_channely->ctrl_bit.pincm = dma_init_struct->peripheral_inc_enable;
+ dmax_channely->ctrl_bit.lm = dma_init_struct->loop_mode_enable;
+ dmax_channely->dtcnt_bit.cnt = dma_init_struct->buffer_size;
+ dmax_channely->paddr = dma_init_struct->peripheral_base_addr;
+ dmax_channely->maddr = dma_init_struct->memory_base_addr;
+}
+/**
+ * @brief dmamux init.
+ * @param dma_x: pointer to a dma_type structure, can be DMA1 or DMA2.
+ * @param dmamux_channelx:
+ * this parameter can be one of the following values:
+ * - DMA1MUX_CHANNEL1
+ * - DMA1MUX_CHANNEL2
+ * - DMA1MUX_CHANNEL3
+ * - DMA1MUX_CHANNEL4
+ * - DMA1MUX_CHANNEL5
+ * - DMA1MUX_CHANNEL6
+ * - DMA1MUX_CHANNEL7
+ * - DMA2MUX_CHANNEL1
+ * - DMA2MUX_CHANNEL2
+ * - DMA2MUX_CHANNEL3
+ * - DMA2MUX_CHANNEL4
+ * - DMA2MUX_CHANNEL5
+ * - DMA2MUX_CHANNEL6
+ * - DMA2MUX_CHANNEL7
+ * @param dmamux_req_sel:
+ * this parameter can be one of the following values:
+ * - DMAMUX_DMAREQ_ID_REQ_G1 - DMAMUX_DMAREQ_ID_REQ_G2 - DMAMUX_DMAREQ_ID_REQ_G3 - DMAMUX_DMAREQ_ID_REQ_G4
+ * - DMAMUX_DMAREQ_ID_ADC1 - DMAMUX_DMAREQ_ID_ADC2 - DMAMUX_DMAREQ_ID_ADC3 - DMAMUX_DMAREQ_ID_DAC1
+ * - DMAMUX_DMAREQ_ID_DAC2 - DMAMUX_DMAREQ_ID_TMR6_OVERFLOW- DMAMUX_DMAREQ_ID_TMR7_OVERFLOW- DMAMUX_DMAREQ_ID_SPI1_RX
+ * - DMAMUX_DMAREQ_ID_SPI1_TX - DMAMUX_DMAREQ_ID_SPI2_RX - DMAMUX_DMAREQ_ID_SPI2_TX - DMAMUX_DMAREQ_ID_SPI3_RX
+ * - DMAMUX_DMAREQ_ID_SPI3_TX - DMAMUX_DMAREQ_ID_SPI4_RX - DMAMUX_DMAREQ_ID_SPI4_TX - DMAMUX_DMAREQ_ID_I2S2_EXT_RX
+ * - DMAMUX_DMAREQ_ID_I2S2_EXT_TX - DMAMUX_DMAREQ_ID_I2S3_EXT_RX - DMAMUX_DMAREQ_ID_I2S3_EXT_TX - DMAMUX_DMAREQ_ID_I2C1_RX
+ * - DMAMUX_DMAREQ_ID_I2C1_TX - DMAMUX_DMAREQ_ID_I2C2_RX - DMAMUX_DMAREQ_ID_I2C2_TX - DMAMUX_DMAREQ_ID_I2C3_RX
+ * - DMAMUX_DMAREQ_ID_I2C3_TX - DMAMUX_DMAREQ_ID_USART1_RX - DMAMUX_DMAREQ_ID_USART1_TX - DMAMUX_DMAREQ_ID_USART2_RX
+ * - DMAMUX_DMAREQ_ID_USART2_TX - DMAMUX_DMAREQ_ID_USART3_RX - DMAMUX_DMAREQ_ID_USART3_TX - DMAMUX_DMAREQ_ID_UART4_RX
+ * - DMAMUX_DMAREQ_ID_UART4_TX - DMAMUX_DMAREQ_ID_UART5_RX - DMAMUX_DMAREQ_ID_UART5_TX - DMAMUX_DMAREQ_ID_USART6_RX
+ * - DMAMUX_DMAREQ_ID_USART6_TX - DMAMUX_DMAREQ_ID_UART7_RX - DMAMUX_DMAREQ_ID_UART7_TX - DMAMUX_DMAREQ_ID_UART8_RX
+ * - DMAMUX_DMAREQ_ID_UART8_TX - DMAMUX_DMAREQ_ID_SDIO1 - DMAMUX_DMAREQ_ID_SDIO2 - DMAMUX_DMAREQ_ID_QSPI1
+ * - DMAMUX_DMAREQ_ID_QSPI2 - DMAMUX_DMAREQ_ID_TMR1_CH1 - DMAMUX_DMAREQ_ID_TMR1_CH2 - DMAMUX_DMAREQ_ID_TMR1_CH3
+ * - DMAMUX_DMAREQ_ID_TMR1_CH4 - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW- DMAMUX_DMAREQ_ID_TMR1_TRIG - DMAMUX_DMAREQ_ID_TMR1_COM
+ * - DMAMUX_DMAREQ_ID_TMR8_CH1 - DMAMUX_DMAREQ_ID_TMR8_CH2 - DMAMUX_DMAREQ_ID_TMR8_CH3 - DMAMUX_DMAREQ_ID_TMR8_CH4
+ * - DMAMUX_DMAREQ_ID_TMR8_UP - DMAMUX_DMAREQ_ID_TMR8_TRIG - DMAMUX_DMAREQ_ID_TMR8_COM - DMAMUX_DMAREQ_ID_TMR2_CH1
+ * - DMAMUX_DMAREQ_ID_TMR2_CH2 - DMAMUX_DMAREQ_ID_TMR2_CH3 - DMAMUX_DMAREQ_ID_TMR2_CH4 - DMAMUX_DMAREQ_ID_TMR2_OVERFLOW
+ * - DMAMUX_DMAREQ_ID_TMR2_TRIG - DMAMUX_DMAREQ_ID_TMR3_CH1 - DMAMUX_DMAREQ_ID_TMR3_CH2 - DMAMUX_DMAREQ_ID_TMR3_CH3
+ * - DMAMUX_DMAREQ_ID_TMR3_CH4 - DMAMUX_DMAREQ_ID_TMR3_OVERFLOW- DMAMUX_DMAREQ_ID_TMR3_TRIG - DMAMUX_DMAREQ_ID_TMR4_CH1
+ * - DMAMUX_DMAREQ_ID_TMR4_CH2 - DMAMUX_DMAREQ_ID_TMR4_CH3 - DMAMUX_DMAREQ_ID_TMR4_CH4 - DMAMUX_DMAREQ_ID_TMR4_OVERFLOW
+ * - DMAMUX_DMAREQ_ID_TMR4_TRIG - DMAMUX_DMAREQ_ID_TMR5_CH1 - DMAMUX_DMAREQ_ID_TMR5_CH2 - DMAMUX_DMAREQ_ID_TMR5_CH3
+ * - DMAMUX_DMAREQ_ID_TMR5_CH4 - DMAMUX_DMAREQ_ID_TMR5_OVERFLOW- DMAMUX_DMAREQ_ID_TMR5_TRIG - DMAMUX_DMAREQ_ID_TMR20_CH1
+ * - DMAMUX_DMAREQ_ID_TMR20_CH2 - DMAMUX_DMAREQ_ID_TMR20_CH3 - DMAMUX_DMAREQ_ID_TMR20_CH4 - DMAMUX_DMAREQ_ID_TMR20_OVERFLOW
+ * - DMAMUX_DMAREQ_ID_TMR20_TRIG - DMAMUX_DMAREQ_ID_TMR20_HALL - DMAMUX_DMAREQ_ID_DVP
+ * @retval none.
+ */
+void dma_flexible_config(dma_type* dma_x, dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel)
+{
+ dma_x->muxsel_bit.tblsel = TRUE;
+ dmamux_channelx->muxctrl_bit.reqsel = dmamux_req_sel;
+}
+
+/**
+ * @brief enable or disable the dmamux.
+ * @param dma_x: pointer to a dma_type structure, can be DMA1 or DMA2.
+ * @param new_state (TRUE or FALSE) .
+ * @retval none.
+ */
+void dmamux_enable(dma_type *dma_x, confirm_state new_state)
+{
+ dma_x->muxsel_bit.tblsel = new_state;
+}
+
+/**
+ * @brief dmamux init.
+ * @param dmamux_channelx:
+ * this parameter can be one of the following values:
+ * - DMA1MUX_CHANNEL1
+ * - DMA1MUX_CHANNEL2
+ * - DMA1MUX_CHANNEL3
+ * - DMA1MUX_CHANNEL4
+ * - DMA1MUX_CHANNEL5
+ * - DMA1MUX_CHANNEL6
+ * - DMA1MUX_CHANNEL7
+ * - DMA2MUX_CHANNEL1
+ * - DMA2MUX_CHANNEL2
+ * - DMA2MUX_CHANNEL3
+ * - DMA2MUX_CHANNEL4
+ * - DMA2MUX_CHANNEL5
+ * - DMA2MUX_CHANNEL6
+ * - DMA2MUX_CHANNEL7
+ * @param dmamux_req_sel:
+ * this parameter can be one of the following values:
+ * - DMAMUX_DMAREQ_ID_REQ_G1 - DMAMUX_DMAREQ_ID_REQ_G2 - DMAMUX_DMAREQ_ID_REQ_G3 - DMAMUX_DMAREQ_ID_REQ_G4
+ * - DMAMUX_DMAREQ_ID_ADC1 - DMAMUX_DMAREQ_ID_ADC2 - DMAMUX_DMAREQ_ID_ADC3 - DMAMUX_DMAREQ_ID_DAC1
+ * - DMAMUX_DMAREQ_ID_DAC2 - DMAMUX_DMAREQ_ID_TMR6_OVERFLOW- DMAMUX_DMAREQ_ID_TMR7_OVERFLOW- DMAMUX_DMAREQ_ID_SPI1_RX
+ * - DMAMUX_DMAREQ_ID_SPI1_TX - DMAMUX_DMAREQ_ID_SPI2_RX - DMAMUX_DMAREQ_ID_SPI2_TX - DMAMUX_DMAREQ_ID_SPI3_RX
+ * - DMAMUX_DMAREQ_ID_SPI3_TX - DMAMUX_DMAREQ_ID_SPI4_RX - DMAMUX_DMAREQ_ID_SPI4_TX - DMAMUX_DMAREQ_ID_I2S2_EXT_RX
+ * - DMAMUX_DMAREQ_ID_I2S2_EXT_TX - DMAMUX_DMAREQ_ID_I2S3_EXT_RX - DMAMUX_DMAREQ_ID_I2S3_EXT_TX - DMAMUX_DMAREQ_ID_I2C1_RX
+ * - DMAMUX_DMAREQ_ID_I2C1_TX - DMAMUX_DMAREQ_ID_I2C2_RX - DMAMUX_DMAREQ_ID_I2C2_TX - DMAMUX_DMAREQ_ID_I2C3_RX
+ * - DMAMUX_DMAREQ_ID_I2C3_TX - DMAMUX_DMAREQ_ID_USART1_RX - DMAMUX_DMAREQ_ID_USART1_TX - DMAMUX_DMAREQ_ID_USART2_RX
+ * - DMAMUX_DMAREQ_ID_USART2_TX - DMAMUX_DMAREQ_ID_USART3_RX - DMAMUX_DMAREQ_ID_USART3_TX - DMAMUX_DMAREQ_ID_UART4_RX
+ * - DMAMUX_DMAREQ_ID_UART4_TX - DMAMUX_DMAREQ_ID_UART5_RX - DMAMUX_DMAREQ_ID_UART5_TX - DMAMUX_DMAREQ_ID_USART6_RX
+ * - DMAMUX_DMAREQ_ID_USART6_TX - DMAMUX_DMAREQ_ID_UART7_RX - DMAMUX_DMAREQ_ID_UART7_TX - DMAMUX_DMAREQ_ID_UART8_RX
+ * - DMAMUX_DMAREQ_ID_UART8_TX - DMAMUX_DMAREQ_ID_SDIO1 - DMAMUX_DMAREQ_ID_SDIO2 - DMAMUX_DMAREQ_ID_QSPI1
+ * - DMAMUX_DMAREQ_ID_QSPI2 - DMAMUX_DMAREQ_ID_TMR1_CH1 - DMAMUX_DMAREQ_ID_TMR1_CH2 - DMAMUX_DMAREQ_ID_TMR1_CH3
+ * - DMAMUX_DMAREQ_ID_TMR1_CH4 - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW- DMAMUX_DMAREQ_ID_TMR1_TRIG - DMAMUX_DMAREQ_ID_TMR1_COM
+ * - DMAMUX_DMAREQ_ID_TMR8_CH1 - DMAMUX_DMAREQ_ID_TMR8_CH2 - DMAMUX_DMAREQ_ID_TMR8_CH3 - DMAMUX_DMAREQ_ID_TMR8_CH4
+ * - DMAMUX_DMAREQ_ID_TMR8_UP - DMAMUX_DMAREQ_ID_TMR8_TRIG - DMAMUX_DMAREQ_ID_TMR8_COM - DMAMUX_DMAREQ_ID_TMR2_CH1
+ * - DMAMUX_DMAREQ_ID_TMR2_CH2 - DMAMUX_DMAREQ_ID_TMR2_CH3 - DMAMUX_DMAREQ_ID_TMR2_CH4 - DMAMUX_DMAREQ_ID_TMR2_OVERFLOW
+ * - DMAMUX_DMAREQ_ID_TMR2_TRIG - DMAMUX_DMAREQ_ID_TMR3_CH1 - DMAMUX_DMAREQ_ID_TMR3_CH2 - DMAMUX_DMAREQ_ID_TMR3_CH3
+ * - DMAMUX_DMAREQ_ID_TMR3_CH4 - DMAMUX_DMAREQ_ID_TMR3_OVERFLOW- DMAMUX_DMAREQ_ID_TMR3_TRIG - DMAMUX_DMAREQ_ID_TMR4_CH1
+ * - DMAMUX_DMAREQ_ID_TMR4_CH2 - DMAMUX_DMAREQ_ID_TMR4_CH3 - DMAMUX_DMAREQ_ID_TMR4_CH4 - DMAMUX_DMAREQ_ID_TMR4_OVERFLOW
+ * - DMAMUX_DMAREQ_ID_TMR4_TRIG - DMAMUX_DMAREQ_ID_TMR5_CH1 - DMAMUX_DMAREQ_ID_TMR5_CH2 - DMAMUX_DMAREQ_ID_TMR5_CH3
+ * - DMAMUX_DMAREQ_ID_TMR5_CH4 - DMAMUX_DMAREQ_ID_TMR5_OVERFLOW- DMAMUX_DMAREQ_ID_TMR5_TRIG - DMAMUX_DMAREQ_ID_TMR20_CH1
+ * - DMAMUX_DMAREQ_ID_TMR20_CH2 - DMAMUX_DMAREQ_ID_TMR20_CH3 - DMAMUX_DMAREQ_ID_TMR20_CH4 - DMAMUX_DMAREQ_ID_TMR20_OVERFLOW
+ * - DMAMUX_DMAREQ_ID_TMR20_TRIG - DMAMUX_DMAREQ_ID_TMR20_HALL - DMAMUX_DMAREQ_ID_DVP
+ * @retval none.
+ */
+void dmamux_init(dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel)
+{
+ dmamux_channelx->muxctrl_bit.reqsel = dmamux_req_sel;
+}
+
+/**
+ * @brief dmamux sync init struct config with its default value.
+ * @param dmamux_sync_init_struct: pointer to a dmamux_sync_init_type structure which will be initialized.
+ * @retval none.
+ */
+void dmamux_sync_default_para_init(dmamux_sync_init_type *dmamux_sync_init_struct)
+{
+ dmamux_sync_init_struct->sync_enable = FALSE;
+ dmamux_sync_init_struct->sync_event_enable = FALSE;
+ dmamux_sync_init_struct->sync_polarity = DMAMUX_SYNC_POLARITY_DISABLE;
+ dmamux_sync_init_struct->sync_request_number = 0x0;
+ dmamux_sync_init_struct->sync_signal_sel = (dmamux_sync_id_sel_type)0;
+}
+
+/**
+ * @brief dmamux synchronization config.
+ * @param dmamux_channelx:
+ * this parameter can be one of the following values:
+ * - DMA1MUX_CHANNEL1
+ * - DMA1MUX_CHANNEL2
+ * - DMA1MUX_CHANNEL3
+ * - DMA1MUX_CHANNEL4
+ * - DMA1MUX_CHANNEL5
+ * - DMA1MUX_CHANNEL6
+ * - DMA1MUX_CHANNEL7
+ * - DMA2MUX_CHANNEL1
+ * - DMA2MUX_CHANNEL2
+ * - DMA2MUX_CHANNEL3
+ * - DMA2MUX_CHANNEL4
+ * - DMA2MUX_CHANNEL5
+ * - DMA2MUX_CHANNEL6
+ * - DMA2MUX_CHANNEL7
+ * @param dmamux_sync_init_struct: ointer to a dmamux_sync_init_type structure.
+ * @retval none.
+ */
+void dmamux_sync_config(dmamux_channel_type *dmamux_channelx, dmamux_sync_init_type *dmamux_sync_init_struct)
+{
+ dmamux_channelx->muxctrl_bit.syncsel = dmamux_sync_init_struct->sync_signal_sel;
+ dmamux_channelx->muxctrl_bit.syncpol = dmamux_sync_init_struct->sync_polarity;
+ dmamux_channelx->muxctrl_bit.reqcnt = dmamux_sync_init_struct->sync_request_number;
+ dmamux_channelx->muxctrl_bit.evtgen = dmamux_sync_init_struct->sync_event_enable;
+ dmamux_channelx->muxctrl_bit.syncen = dmamux_sync_init_struct->sync_enable;
+}
+
+/**
+ * @brief dmamux request generator init struct config with its default value.
+ * @param dmamux_gen_init_struct: pointer to a dmamux_gen_init_type structure which will be initialized.
+ * @retval none.
+ */
+void dmamux_generator_default_para_init(dmamux_gen_init_type *dmamux_gen_init_struct)
+{
+ dmamux_gen_init_struct->gen_enable = FALSE;
+ dmamux_gen_init_struct->gen_polarity = DMAMUX_GEN_POLARITY_DISABLE;
+ dmamux_gen_init_struct->gen_request_number = 0x0;
+ dmamux_gen_init_struct->gen_signal_sel = (dmamux_gen_id_sel_type)0x0;
+}
+
+/**
+ * @brief dmamux request generator init.
+ * @param dmamux_gen_x :
+ * this parameter can be one of the following values:
+ * - DMA1MUX_GENERATOR1
+ * - DMA1MUX_GENERATOR2
+ * - DMA1MUX_GENERATOR3
+ * - DMA1MUX_GENERATOR4
+ * - DMA2MUX_GENERATOR1
+ * - DMA2MUX_GENERATOR2
+ * - DMA2MUX_GENERATOR3
+ * - DMA2MUX_GENERATOR4
+ * @param dmamux_gen_init_struct: pointer to a dmamux_gen_init_type structure which will be initialized.
+ * @retval none.
+ */
+void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_init_type *dmamux_gen_init_struct)
+{
+ dmamux_gen_x->gctrl_bit.sigsel = dmamux_gen_init_struct->gen_signal_sel;
+ dmamux_gen_x->gctrl_bit.gpol = dmamux_gen_init_struct->gen_polarity;
+ dmamux_gen_x->gctrl_bit.greqcnt = dmamux_gen_init_struct->gen_request_number;
+ dmamux_gen_x->gctrl_bit.gen = dmamux_gen_init_struct->gen_enable;
+}
+
+/**
+ * @brief enable or disable the dmamux sync interrupts.
+ * @param dmamux_channelx:
+ * this parameter can be one of the following values:
+ * - DMA1MUX_CHANNEL1
+ * - DMA1MUX_CHANNEL2
+ * - DMA1MUX_CHANNEL3
+ * - DMA1MUX_CHANNEL4
+ * - DMA1MUX_CHANNEL5
+ * - DMA1MUX_CHANNEL6
+ * - DMA1MUX_CHANNEL7
+ * - DMA2MUX_CHANNEL1
+ * - DMA2MUX_CHANNEL2
+ * - DMA2MUX_CHANNEL3
+ * - DMA2MUX_CHANNEL4
+ * - DMA2MUX_CHANNEL5
+ * - DMA2MUX_CHANNEL6
+ * - DMA2MUX_CHANNEL7
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ dmamux_channelx->muxctrl_bit.syncovien = TRUE;
+ }
+ else
+ {
+ dmamux_channelx->muxctrl_bit.syncovien = FALSE;
+ }
+}
+
+/**
+ * @brief enable or disable the dmamux request generator interrupts.
+ * @param dmamux_gen_x : pointer to a dmamux_generator_type structure.
+ * this parameter can be one of the following values:
+ * - DMA1MUX_GENERATOR1
+ * - DMA1MUX_GENERATOR2
+ * - DMA1MUX_GENERATOR3
+ * - DMA1MUX_GENERATOR4
+ * - DMA2MUX_GENERATOR1
+ * - DMA2MUX_GENERATOR2
+ * - DMA2MUX_GENERATOR3
+ * - DMA2MUX_GENERATOR4
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ dmamux_gen_x->gctrl_bit.trgovien = TRUE;
+ }
+ else
+ {
+ dmamux_gen_x->gctrl_bit.trgovien = FALSE;
+ }
+}
+
+/**
+ * @brief dmamux sync flag get.
+ * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
+ * @param flag
+ * this parameter can be any combination of the following values:
+ * - DMAMUX_SYNC_OV1_FLAG
+ * - DMAMUX_SYNC_OV2_FLAG
+ * - DMAMUX_SYNC_OV3_FLAG
+ * - DMAMUX_SYNC_OV4_FLAG
+ * - DMAMUX_SYNC_OV5_FLAG
+ * - DMAMUX_SYNC_OV6_FLAG
+ * - DMAMUX_SYNC_OV7_FLAG
+ * @retval state of dmamux sync flag.
+ */
+flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag)
+{
+ if((dma_x->muxsyncsts & flag) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief dmamux sync flag clear.
+ * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
+ * @param flag
+ * this parameter can be any combination of the following values:
+ * - DMAMUX_SYNC_OV1_FLAG
+ * - DMAMUX_SYNC_OV2_FLAG
+ * - DMAMUX_SYNC_OV3_FLAG
+ * - DMAMUX_SYNC_OV4_FLAG
+ * - DMAMUX_SYNC_OV5_FLAG
+ * - DMAMUX_SYNC_OV6_FLAG
+ * - DMAMUX_SYNC_OV7_FLAG
+ * @retval none.
+ */
+void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag)
+{
+ dma_x->muxsyncclr = flag;
+}
+
+/**
+ * @brief dmamux request generator flag get.
+ * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
+ * @param flag
+ * this parameter can be any combination of the following values:
+ * - DMAMUX_GEN_TRIG_OV1_FLAG
+ * - DMAMUX_GEN_TRIG_OV2_FLAG
+ * - DMAMUX_GEN_TRIG_OV3_FLAG
+ * - DMAMUX_GEN_TRIG_OV4_FLAG
+ * @retval state of dmamux sync flag.
+ */
+flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag)
+{
+ if((dma_x->muxgsts & flag) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief dmamux request generator flag clear.
+ * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
+ * @param flag
+ * this parameter can be any combination of the following values:
+ * - DMAMUX_GEN_TRIG_OV1_FLAG
+ * - DMAMUX_GEN_TRIG_OV2_FLAG
+ * - DMAMUX_GEN_TRIG_OV3_FLAG
+ * - DMAMUX_GEN_TRIG_OV4_FLAG
+ * @retval none.
+ */
+void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag)
+{
+ dma_x->muxgclr = flag;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_dvp.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_dvp.c
new file mode 100644
index 0000000..d9e80d1
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_dvp.c
@@ -0,0 +1,515 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_dvp.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the dvp firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup DVP
+ * @brief DVP driver modules
+ * @{
+ */
+
+#ifdef DVP_MODULE_ENABLED
+
+/** @defgroup DVP_private_functions
+ * @{
+ */
+
+/**
+ * @brief enable or disable dvp capture
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dvp_capture_enable(confirm_state new_state)
+{
+ DVP->ctrl_bit.cap = new_state;
+}
+
+/**
+ * @brief set dvp capture mode
+ * @param cap_mode
+ * this parameter can be one of the following values:
+ * - DVP_CAP_FUNC_MODE_CONTINUOUS
+ * - DVP_CAP_FUNC_MODE_SINGLE
+ * @retval none
+ */
+void dvp_capture_mode_set(dvp_cfm_type cap_mode)
+{
+ DVP->ctrl_bit.cfm = cap_mode;
+}
+
+/**
+ * @brief set dvp cropping window enable
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dvp_window_crop_enable(confirm_state new_state)
+{
+ DVP->ctrl_bit.crp = new_state;
+}
+
+/**
+ * @brief set dvp cropping window configuration
+ * @param crop_x(0x0000~0x3FFF): cropping window horizontal start pixel
+ * @param crop_y(0x0000~0x1FFF): cropping window vertical start pixel
+ * @param crop_w(0x0001~0x3FFF): cropping window horizontal pixel number
+ * @param crop_h(0x0001~0x3FFF): cropping window vertical pixel number
+ * @retval none
+ */
+void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h)
+{
+ DVP->cwst = ((crop_x * 2) | (crop_y << 16));
+ DVP->cwsz = ((crop_w * 2 - 1) | ((crop_h - 1) << 16));
+}
+
+/**
+ * @brief enable or disable dvp jpeg
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dvp_jpeg_enable(confirm_state new_state)
+{
+ DVP->ctrl_bit.jpeg = new_state;
+}
+
+/**
+ * @brief set dvp synchronization mode
+ * @param sync_mode
+ * this parameter can be one of the following values:
+ * - DVP_SYNC_MODE_HARDWARE
+ * - DVP_SYNC_MODE_EMBEDDED
+ * @retval none
+ */
+void dvp_sync_mode_set(dvp_sm_type sync_mode)
+{
+ DVP->ctrl_bit.sm = sync_mode;
+}
+
+/**
+ * @brief set dvp synchronization code configuration
+ * @param fmsc(0x00~0xFF): frame start code
+ * @param fmec(0x00~0xFF): frame end code
+ * @param lnsc(0x00~0xFF): line start code
+ * @param lnec(0x00~0xFF): line end code
+ * @retval none
+ */
+void dvp_sync_code_set(uint8_t fmsc, uint8_t fmec, uint8_t lnsc, uint8_t lnec)
+{
+ DVP->scr = (fmsc | (lnsc << 8) | (lnec << 16) | (fmec << 24));
+}
+
+/**
+ * @brief set dvp synchronization unmask configuration
+ * @param fmsu(0x00~0xFF): frame start unmask
+ * @param fmeu(0x00~0xFF): frame end unmask
+ * @param lnsu(0x00~0xFF): line start unmask
+ * @param lneu(0x00~0xFF): line end unmask
+ * @retval none
+ */
+void dvp_sync_unmask_set(uint8_t fmsu, uint8_t fmeu, uint8_t lnsu, uint8_t lneu)
+{
+ DVP->sur = (fmsu | (lnsu << 8) | (lneu << 16) | (fmeu << 24));
+}
+
+/**
+ * @brief set dvp pixel clock polarity
+ * @param edge
+ * this parameter can be one of the following values:
+ * - DVP_CLK_POLARITY_RISING
+ * - DVP_CLK_POLARITY_FALLING
+ * @retval none
+ */
+void dvp_pclk_polarity_set(dvp_ckp_type edge)
+{
+ DVP->ctrl_bit.ckp = edge;
+}
+
+/**
+ * @brief set dvp horizontal synchronization polarity
+ * @param hsync_pol
+ * this parameter can be one of the following values:
+ * - DVP_HSYNC_POLARITY_HIGH
+ * - DVP_HSYNC_POLARITY_LOW
+ * @retval none
+ */
+void dvp_hsync_polarity_set(dvp_hsp_type hsync_pol)
+{
+ DVP->ctrl_bit.hsp = hsync_pol;
+}
+
+/**
+ * @brief set dvp vertical synchronization polarity
+ * @param vsync_pol
+ * this parameter can be one of the following values:
+ * - DVP_VSYNC_POLARITY_LOW
+ * - DVP_VSYNC_POLARITY_HIGH
+ * @retval none
+ */
+void dvp_vsync_polarity_set(dvp_vsp_type vsync_pol)
+{
+ DVP->ctrl_bit.vsp = vsync_pol;
+}
+
+/**
+ * @brief config dvp basic frame rate control
+ * @note this function only work in continuous fire mode(ctrl_bit.cfm = 0)
+ * @param dvp_bfrc
+ * this parameter can be one of the following values:
+ * - DVP_BFRC_ALL
+ * - DVP_BFRC_HALF
+ * - DVP_BFRC_QUARTER
+ * @retval none
+ */
+void dvp_basic_frame_rate_control_set(dvp_bfrc_type dvp_bfrc)
+{
+ DVP->ctrl_bit.bfrc = dvp_bfrc;
+}
+
+/**
+ * @brief config dvp pixel data length
+ * @param dvp_pdl
+ * this parameter can be one of the following values:
+ * - DVP_PIXEL_DATA_LENGTH_8
+ * - DVP_PIXEL_DATA_LENGTH_10
+ * - DVP_PIXEL_DATA_LENGTH_12
+ * - DVP_PIXEL_DATA_LENGTH_14
+ * @retval none
+ */
+void dvp_pixel_data_length_set(dvp_pdl_type dvp_pdl)
+{
+ DVP->ctrl_bit.pdl = dvp_pdl;
+}
+
+/**
+ * @brief enable or disable dvp function
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dvp_enable(confirm_state new_state)
+{
+ DVP->ctrl_bit.ena = new_state;
+}
+
+/**
+ * @brief set dvp zoomout select
+ * @param dvp_pcdse: pixel capture/drop selection extension (Only work when pcdc = 2)
+ * this parameter can be one of the following values:
+ * - DVP_PCDSE_CAP_FIRST
+ * - DVP_PCDSE_DROP_FIRST
+ * @retval none
+ */
+void dvp_zoomout_select(dvp_pcdse_type dvp_pcdse)
+{
+ DVP->actrl_bit.pcdse = dvp_pcdse;
+}
+
+/**
+ * @brief set dvp zoomout configuration
+ * @param dvp_pcdc: basic pixel capture/drop control
+ * this parameter can be one of the following values:
+ * - DVP_PCDC_ALL
+ * - DVP_PCDC_ONE_IN_TWO
+ * - DVP_PCDC_ONE_IN_FOUR
+ * - DVP_PCDC_TWO_IN_FOUR
+ * @param dvp_pcds: pixel capture/drop selection
+ * this parameter can be one of the following values:
+ * - DVP_PCDS_CAP_FIRST
+ * - DVP_PCDS_DROP_FIRST
+ * @param dvp_lcdc: line capture/drop control
+ * this parameter can be one of the following values:
+ * - DVP_LCDC_ALL
+ * - DVP_LCDC_ONE_IN_TWO
+ * @param dvp_lcds: line capture/drop selection
+ * this parameter can be one of the following values:
+ * - DVP_LCDS_CAP_FIRST
+ * - DVP_LCDS_DROP_FIRST
+ * @retval none
+ */
+void dvp_zoomout_set(dvp_pcdc_type dvp_pcdc, dvp_pcds_type dvp_pcds, dvp_lcdc_type dvp_lcdc, dvp_lcds_type dvp_lcds)
+{
+ DVP->ctrl_bit.pcdc = dvp_pcdc;
+ DVP->ctrl_bit.pcds = dvp_pcds;
+ DVP->ctrl_bit.lcdc = dvp_lcdc;
+ DVP->ctrl_bit.lcds = dvp_lcds;
+}
+
+/**
+ * @brief get dvp basic status
+ * @param dvp_status_basic_type:
+ * this parameter can be one of the following values:
+ * - DVP_STATUS_HSYN
+ * - DVP_STATUS_VSYN
+ * - DVP_STATUS_OFS
+ * @retval flag_status (SET or RESET)
+ */
+flag_status dvp_basic_status_get(dvp_status_basic_type dvp_status_basic)
+{
+ flag_status status = RESET;
+
+ if ((DVP->sts & (0x1 << dvp_status_basic)) != (uint16_t)RESET)
+ {
+ status = SET;
+ }
+ else
+ {
+ status = RESET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief enable or disable dvp interrupt
+ * @param dvp_int:
+ * this parameter can be any combination of the following values:
+ * - DVP_CFD_INT
+ * - DVP_OVR_INT
+ * - DVP_ESE_INT
+ * - DVP_VS_INT
+ * - DVP_HS_INT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dvp_interrupt_enable(uint32_t dvp_int, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ {
+ DVP->ier |= dvp_int;
+ }
+ else
+ {
+ DVP->ier &= ~dvp_int;
+ }
+}
+
+/**
+ * @brief get dvp event/interrupt flag status
+ * @param flag
+ * this parameter can be one of the following values:
+ * event flag:
+ * - DVP_CFD_EVT_FLAG
+ * - DVP_OVR_EVT_FLAG
+ * - DVP_ESE_EVT_FLAG
+ * - DVP_VS_EVT_FLAG
+ * - DVP_HS_EVT_FLAG
+ * interrupt flag:
+ * - DVP_CFD_INT_FLAG
+ * - DVP_OVR_INT_FLAG
+ * - DVP_ESE_INT_FLAG
+ * - DVP_VS_INT_FLAG
+ * - DVP_HS_INT_FLAG
+ * @retval flag_status (SET or RESET)
+ */
+flag_status dvp_flag_get(uint32_t flag)
+{
+ flag_status status = RESET;
+ if(flag & 0x80000000)
+ {
+ if((DVP->ists & flag) != RESET)
+ {
+ status = SET;
+ }
+ else
+ {
+ status = RESET;
+ }
+ }
+ else
+ {
+ if((DVP->ests & flag) != RESET)
+ {
+ status = SET;
+ }
+ else
+ {
+ status = RESET;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief clear dvp's pending flags
+ * @param flag
+ * this parameter can be one of the following values:
+ * event flag:
+ * - DVP_CFD_EVT_FLAG
+ * - DVP_OVR_EVT_FLAG
+ * - DVP_ESE_EVT_FLAG
+ * - DVP_VS_EVT_FLAG
+ * - DVP_HS_EVT_FLAG
+ * interrupt flag:
+ * - DVP_CFD_INT_FLAG
+ * - DVP_OVR_INT_FLAG
+ * - DVP_ESE_INT_FLAG
+ * - DVP_VS_INT_FLAG
+ * - DVP_HS_INT_FLAG
+ * @retval none
+ */
+void dvp_flag_clear(uint32_t flag)
+{
+ flag &= ~0x80000000;
+ DVP->iclr = flag;
+}
+
+/**
+ * @brief set dvp enhanced image scaling resize enable
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dvp_enhanced_scaling_resize_enable(confirm_state new_state)
+{
+ DVP->actrl_bit.eisre = new_state;
+}
+/**
+ * @brief set dvp enhanced image scaling resize configuration
+ * @param src_w(0x0001~0x1FFF): horizontal scaling resize source size (source image width)
+ * @param des_w(0x0001~0x1FFF): horizontal scaling resize target size (target image width)
+ * @param src_h(0x0001~0x1FFF): vertical scaling resize source size (source image height)
+ * @param des_h(0x0001~0x1FFF): vertical scaling resize target size (target image height)
+ * @retval none
+ */
+void dvp_enhanced_scaling_resize_set(uint16_t src_w, uint16_t des_w, uint16_t src_h, uint16_t des_h)
+{
+ if((!DVP->ctrl_bit.pcdc) && (!DVP->ctrl_bit.lcdc) && DVP->actrl_bit.efdf)
+ {
+ DVP->hscf = (src_w | (des_w << 16));
+ DVP->vscf = (src_h | (des_h << 16));
+ }
+}
+
+/**
+ * @brief set enhanced frame rate control configuration
+ * @param efrcfm(0x00~0x1F): original frame rate contorl factor
+ * @param efrcfn(0x00~0x1F): enhanced frame rate contorl factor
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dvp_enhanced_framerate_set(uint16_t efrcfm, uint16_t efrcfn, confirm_state new_state)
+{
+ if((!DVP->ctrl_bit.cfm) && (!DVP->ctrl_bit.bfrc) && (efrcfn <= efrcfm))
+ {
+ DVP->frf = (efrcfm | (efrcfn << 8));
+ }
+
+ DVP->actrl_bit.efrce = new_state;
+}
+
+/**
+ * @brief set dvp monochrome image binarization configuration
+ * @param mibthd(0x00~0xFF): monochrome image binarization threshold
+ * @param new_state: (TRUE or FALSE)
+ * @retval none
+ */
+void dvp_monochrome_image_binarization_set(uint8_t mibthd, confirm_state new_state)
+{
+ DVP->bth_bit.mibthd = mibthd;
+ DVP->actrl_bit.mibe = new_state;
+}
+
+/**
+ * @brief set dvp enhanced function data format configuration
+ * @param dvp_efdf: enhanced function data format
+ * this parameter can be one of the following values:
+ * - DVP_EFDF_BYPASS
+ * - DVP_EFDF_YUV422_UYVY
+ * - DVP_EFDF_YUV422_YUYV
+ * - DVP_EFDF_YUV444
+ * - DVP_EFDF_Y8
+ * @retval none
+ */
+void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf)
+{
+ DVP->actrl_bit.efdf = dvp_efdf;
+}
+
+/**
+ * @brief set dvp input data un-used condition/number configuration
+ * @param dvp_iduc: input data un-used condition
+ * this parameter can be one of the following values:
+ * - DVP_IDUC_MSB
+ * - DVP_IDUC_LSB
+ * @param dvp_idun: input data un-used number
+ * this parameter can be one of the following values:
+ * - DVP_IDUN_0
+ * - DVP_IDUN_2
+ * - DVP_IDUN_4
+ * - DVP_IDUN_6
+ * @retval none
+ */
+void dvp_input_data_unused_set(dvp_iduc_type dvp_iduc, dvp_idun_type dvp_idun)
+{
+ DVP->actrl_bit.iduc = dvp_iduc;
+ DVP->actrl_bit.idun = dvp_idun;
+}
+
+/**
+ * @brief set dvp dma burst transfer configuration
+ * @param dvp_dmabt: dma burst transfer configuration
+ * this parameter can be one of the following values:
+ * - DVP_DMABT_SINGLE
+ * - DVP_DMABT_BURST
+ * @retval none
+ */
+void dvp_dma_burst_set(dvp_dmabt_type dvp_dmabt)
+{
+ DVP->actrl_bit.dmabt = dvp_dmabt;
+}
+
+/**
+ * @brief set dvp hsync/vsync event interrupt strategy configuration
+ * @param dvp_hseis: hsync event interrupt strategy
+ * this parameter can be one of the following values:
+ * - DVP_HSEIS_LINE_END
+ * - DVP_HSEIS_LINE_START
+ * @param dvp_vseis: vsync event interrupt strategy
+ * this parameter can be one of the following values:
+ * - DVP_VSEIS_FRAME_END
+ * - DVP_VSEIS_FRMAE_START
+ * @retval none
+ */
+void dvp_sync_event_interrupt_set(dvp_hseis_type dvp_hseis, dvp_vseis_type dvp_vseis)
+{
+ DVP->actrl_bit.hseis = dvp_hseis;
+ DVP->actrl_bit.vseis = dvp_vseis;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_edma.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_edma.c
new file mode 100644
index 0000000..ccd40b3
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_edma.c
@@ -0,0 +1,931 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_edma.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the edma firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup EDMA
+ * @brief EDMA driver modules
+ * @{
+ */
+
+#ifdef EDMA_MODULE_ENABLED
+
+/** @defgroup EDMA_private_functions
+ * @{
+ */
+
+/**
+ * @brief reset edma_streamx channely register.
+ * @param edma_streamx:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1
+ * - EDMA_STREAM2
+ * - EDMA_STREAM3
+ * - EDMA_STREAM4
+ * - EDMA_STREAM5
+ * - EDMA_STREAM6
+ * - EDMA_STREAM7
+ * - EDMA_STREAM8
+ * @retval none.
+ */
+void edma_reset(edma_stream_type *edma_streamx)
+{
+ /* reset registers for the selected stream */
+ edma_streamx->ctrl_bit.sen = FALSE;
+ edma_streamx->ctrl = 0x0;
+ edma_streamx->dtcnt = 0x0;
+ edma_streamx->paddr = 0x0;
+ edma_streamx->m0addr = 0x0;
+ edma_streamx->m1addr = 0x0;
+ edma_streamx->fctrl = (uint32_t)0x00000021;
+
+ /* reset interrupt pending bits for the selected stream */
+ switch((uint32_t)edma_streamx)
+ {
+ case EDMA_STREAM1_BASE:
+ EDMA->clr1 = EDMA_STREAM1_INT_MASK;
+ break;
+ case EDMA_STREAM2_BASE:
+ EDMA->clr1 = EDMA_STREAM2_INT_MASK;
+ break;
+ case EDMA_STREAM3_BASE:
+ EDMA->clr1 = EDMA_STREAM3_INT_MASK;
+ break;
+ case EDMA_STREAM4_BASE:
+ EDMA->clr1 = EDMA_STREAM4_INT_MASK;
+ break;
+ case EDMA_STREAM5_BASE:
+ EDMA->clr2 = EDMA_STREAM5_INT_MASK;
+ break;
+ case EDMA_STREAM6_BASE:
+ EDMA->clr2 = EDMA_STREAM6_INT_MASK;
+ break;
+ case EDMA_STREAM7_BASE:
+ EDMA->clr2 = EDMA_STREAM7_INT_MASK;
+ break;
+ case EDMA_STREAM8_BASE:
+ EDMA->clr2 = EDMA_STREAM8_INT_MASK;
+ break;
+ default: break;
+ }
+}
+
+/**
+ * @brief edma init.
+ * @param edma_streamx:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1
+ * - EDMA_STREAM2
+ * - EDMA_STREAM3
+ * - EDMA_STREAM4
+ * - EDMA_STREAM5
+ * - EDMA_STREAM6
+ * - EDMA_STREAM7
+ * - EDMA_STREAM8
+ * @param edma_init_struct: pointer to a edma_init_type structure.
+ * @retval none.
+ */
+void edma_init(edma_stream_type *edma_streamx, edma_init_type *edma_init_struct)
+{
+ /* config dtd bits */
+ edma_streamx->ctrl_bit.dtd = edma_init_struct->direction;
+
+ /* config pincm bit */
+ edma_streamx->ctrl_bit.pincm = edma_init_struct->peripheral_inc_enable;
+
+ /* config mincm bit*/
+ edma_streamx->ctrl_bit.mincm = edma_init_struct->memory_inc_enable;
+
+ /* config pwidth bits */
+ edma_streamx->ctrl_bit.pwidth = edma_init_struct->peripheral_data_width;
+
+ /* config mwidth bits */
+ edma_streamx->ctrl_bit.mwidth = edma_init_struct->memory_data_width;
+
+ /* config lm bit */
+ edma_streamx->ctrl_bit.lm = edma_init_struct->loop_mode_enable;
+
+ /* config spl bits */
+ edma_streamx->ctrl_bit.spl = edma_init_struct->priority;
+
+ /* config mct bits */
+ edma_streamx->ctrl_bit.mct = edma_init_struct->memory_burst_mode;
+
+ /* config pct bits */
+ edma_streamx->ctrl_bit.pct = edma_init_struct->peripheral_burst_mode;
+
+ /* config fen bits */
+ edma_streamx->fctrl_bit.fen = edma_init_struct->fifo_mode_enable;
+
+ /* config fthsel bits*/
+ edma_streamx->fctrl_bit.fthsel = edma_init_struct->fifo_threshold;
+
+ /* config dtcnt */
+ edma_streamx->dtcnt = edma_init_struct->buffer_size;
+
+ /* config paddr */
+ edma_streamx->paddr = edma_init_struct->peripheral_base_addr;
+
+ /* config m0addr */
+ edma_streamx->m0addr = edma_init_struct->memory0_base_addr;
+}
+
+/**
+ * @brief edma init struct config with its default value.
+ * @param edma_init_struct: pointer to a edma_init_type structure which will be initialized.
+ * @retval none.
+ */
+void edma_default_para_init(edma_init_type *edma_init_struct)
+{
+ edma_init_struct->buffer_size = 0;
+ edma_init_struct->loop_mode_enable = FALSE;
+ edma_init_struct->direction = EDMA_DIR_PERIPHERAL_TO_MEMORY;
+ edma_init_struct->fifo_threshold = EDMA_FIFO_THRESHOLD_1QUARTER;
+ edma_init_struct->fifo_mode_enable = FALSE;
+ edma_init_struct->memory0_base_addr = 0;
+ edma_init_struct->memory_burst_mode = EDMA_MEMORY_SINGLE;
+ edma_init_struct->memory_data_width = EDMA_MEMORY_DATA_WIDTH_BYTE;
+ edma_init_struct->memory_inc_enable = FALSE;
+ edma_init_struct->peripheral_base_addr = 0;
+ edma_init_struct->peripheral_burst_mode = EDMA_PERIPHERAL_SINGLE;
+ edma_init_struct->peripheral_data_width = EDMA_PERIPHERAL_DATA_WIDTH_BYTE;
+ edma_init_struct->peripheral_inc_enable = FALSE;
+ edma_init_struct->priority = EDMA_PRIORITY_LOW;
+}
+
+/**
+ * @brief enable or disable the edma streamx.
+ * @param edma_streamx:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1
+ * - EDMA_STREAM2
+ * - EDMA_STREAM3
+ * - EDMA_STREAM4
+ * - EDMA_STREAM5
+ * - EDMA_STREAM6
+ * - EDMA_STREAM7
+ * - EDMA_STREAM8
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void edma_stream_enable(edma_stream_type *edma_streamx, confirm_state new_state)
+{
+ edma_streamx->ctrl_bit.sen = new_state;
+}
+
+/**
+ * @brief enable or disable the edma streamx interrupts.
+ * @param edma_streamx:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1
+ * - EDMA_STREAM2
+ * - EDMA_STREAM3
+ * - EDMA_STREAM4
+ * - EDMA_STREAM5
+ * - EDMA_STREAM6
+ * - EDMA_STREAM7
+ * - EDMA_STREAM8
+ * @param edma_int:
+ * this parameter can be one of the following values:
+ * - EDMA_FDT_INT
+ * - EDMA_HDT_INT
+ * - EDMA_DTERR_INT
+ * - EDMA_DMERR_INT
+ * - EDMA_FERR_INT
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void edma_interrupt_enable(edma_stream_type *edma_streamx, uint32_t edma_int, confirm_state new_state)
+{
+ if((edma_int & EDMA_FERR_INT) != 0)
+ {
+ if(new_state != FALSE)
+ {
+ edma_streamx->fctrl |= (uint32_t)EDMA_FERR_INT;
+ }
+ else
+ {
+ edma_streamx->fctrl &= ~(uint32_t)EDMA_FERR_INT;
+ }
+ }
+
+ if(edma_int != EDMA_FERR_INT)
+ {
+ if(new_state != FALSE)
+ {
+ edma_streamx->ctrl |= (uint32_t)edma_int;
+ }
+ else
+ {
+ edma_streamx->ctrl &= ~(uint32_t)edma_int;
+ }
+ }
+}
+
+/**
+ * @brief config the edma peripheral increment offset size mode.
+ * @param edma_streamx:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1
+ * - EDMA_STREAM2
+ * - EDMA_STREAM3
+ * - EDMA_STREAM4
+ * - EDMA_STREAM5
+ * - EDMA_STREAM6
+ * - EDMA_STREAM7
+ * - EDMA_STREAM8
+ * @param offset: peripheral increment offset size.
+ * this parameter can be one of the following values:
+ * - EDMA_PERIPHERAL_INC_PSIZE
+ * - EDMA_PERIPHERAL_INC_4_BYTE
+ * @retval none.
+ */
+void edma_peripheral_inc_offset_set(edma_stream_type *edma_streamx, edma_peripheral_inc_offset_type offset)
+{
+ edma_streamx->ctrl_bit.pincos = offset;
+}
+
+/**
+ * @brief enable or disable the edma streamx flow controller.
+ * @param edma_streamx:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1
+ * - EDMA_STREAM2
+ * - EDMA_STREAM3
+ * - EDMA_STREAM4
+ * - EDMA_STREAM5
+ * - EDMA_STREAM6
+ * - EDMA_STREAM7
+ * - EDMA_STREAM8
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void edma_flow_controller_enable(edma_stream_type *edma_streamx, confirm_state new_state)
+{
+ edma_streamx->ctrl_bit.pfctrl = new_state;
+}
+
+/**
+ * @brief set the number of data to be transferred.
+ * @param edma_streamx:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1
+ * - EDMA_STREAM2
+ * - EDMA_STREAM3
+ * - EDMA_STREAM4
+ * - EDMA_STREAM5
+ * - EDMA_STREAM6
+ * - EDMA_STREAM7
+ * - EDMA_STREAM8
+ * @param data_number: the number of data to be transferred (0x0000~0xFFFF).
+ * @retval none.
+ */
+void edma_data_number_set(edma_stream_type *edma_streamx, uint16_t data_number)
+{
+ /* write the number of data units to be transferred */
+ edma_streamx->dtcnt = data_number;
+}
+
+/**
+ * @brief get the number of data to be transferred.
+ * @param edma_streamx:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1
+ * - EDMA_STREAM2
+ * - EDMA_STREAM3
+ * - EDMA_STREAM4
+ * - EDMA_STREAM5
+ * - EDMA_STREAM6
+ * - EDMA_STREAM7
+ * - EDMA_STREAM8
+ * @retval the number value.
+ */
+uint16_t edma_data_number_get(edma_stream_type *edma_streamx)
+{
+ return ((uint16_t)(edma_streamx->dtcnt));
+}
+
+/**
+ * @brief config the the double buffer mode.
+ * @param edma_streamx:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1
+ * - EDMA_STREAM2
+ * - EDMA_STREAM3
+ * - EDMA_STREAM4
+ * - EDMA_STREAM5
+ * - EDMA_STREAM6
+ * - EDMA_STREAM7
+ * - EDMA_STREAM8
+ * @param memory1_addr: the address of the second buffer.
+ * @param current_memory: specifies the target area of the first transfer.
+ * this parameter can be one of the following values:
+ * - EDMA_MEMORY_0
+ * - EDMA_MEMORY_1
+ * @retval none.
+ */
+void edma_double_buffer_mode_init(edma_stream_type *edma_streamx, uint32_t memory1_addr, edma_memory_type current_memory)
+{
+ if(current_memory != EDMA_MEMORY_0)
+ {
+ edma_streamx->ctrl_bit.cm = 1;
+ }
+ else
+ {
+ edma_streamx->ctrl_bit.cm = 0;
+ }
+
+ edma_streamx->m1addr = memory1_addr;
+}
+
+/**
+ * @brief enable or disable the double memory mode.
+ * @param edma_streamx:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1
+ * - EDMA_STREAM2
+ * - EDMA_STREAM3
+ * - EDMA_STREAM4
+ * - EDMA_STREAM5
+ * - EDMA_STREAM6
+ * - EDMA_STREAM7
+ * - EDMA_STREAM8
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void edma_double_buffer_mode_enable(edma_stream_type *edma_streamx, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ edma_streamx->ctrl_bit.dmm = 1;
+ }
+ else
+ {
+ edma_streamx->ctrl_bit.dmm = 0;
+ }
+}
+
+/**
+ * @brief config the memory address in double buffer mode.
+ * @param edma_streamx:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1
+ * - EDMA_STREAM2
+ * - EDMA_STREAM3
+ * - EDMA_STREAM4
+ * - EDMA_STREAM5
+ * - EDMA_STREAM6
+ * - EDMA_STREAM7
+ * - EDMA_STREAM8
+ * @param memory_addr: the address of the buffer.
+ * @param memory_target: indicates the which memory addr register will be config.
+ * this parameter can be one of the following values:
+ * - EDMA_MEMORY_0
+ * - EDMA_MEMORY_1
+ * @retval none.
+ */
+void edma_memory_addr_set(edma_stream_type *edma_streamx, uint32_t memory_addr, uint32_t memory_target)
+{
+ if(memory_target != EDMA_MEMORY_0)
+ {
+ edma_streamx->m1addr = memory_addr;
+ }
+ else
+ {
+ edma_streamx->m0addr = memory_addr;
+ }
+}
+
+/**
+ * @brief get the current memory target.
+ * @param edma_streamx:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1
+ * - EDMA_STREAM2
+ * - EDMA_STREAM3
+ * - EDMA_STREAM4
+ * - EDMA_STREAM5
+ * - EDMA_STREAM6
+ * - EDMA_STREAM7
+ * - EDMA_STREAM8
+ * @retval the memory target
+ * - EDMA_MEMORY_0
+ * - EDMA_MEMORY_1
+ */
+edma_memory_type edma_memory_target_get(edma_stream_type *edma_streamx)
+{
+ return (edma_memory_type)(edma_streamx->ctrl_bit.cm);
+}
+
+/**
+ * @brief get the enable status of edma streamx.
+ * @param edma_streamx:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1
+ * - EDMA_STREAM2
+ * - EDMA_STREAM3
+ * - EDMA_STREAM4
+ * - EDMA_STREAM5
+ * - EDMA_STREAM6
+ * - EDMA_STREAM7
+ * - EDMA_STREAM8
+ * @retval current state of the edma streamx (SET or RESET).
+ */
+flag_status edma_stream_status_get(edma_stream_type *edma_streamx)
+{
+ if((edma_streamx->ctrl_bit.sen) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief get the fifo level status.
+ * @param edma_streamx:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1
+ * - EDMA_STREAM2
+ * - EDMA_STREAM3
+ * - EDMA_STREAM4
+ * - EDMA_STREAM5
+ * - EDMA_STREAM6
+ * - EDMA_STREAM7
+ * - EDMA_STREAM8
+ * @retval the fifo filling state.
+ * - EDMA_FIFO_STATUS_LESS_1QUARTER: (0) < fifo level < (1/4).
+ * - EDMA_FIFO_STATUS_1QUARTER: (1/4) <= fifo level < (1/2) .
+ * - EDMA_FIFO_STATUS_HALF: (1/2) <= fifo level < (3/4).
+ * - EDMA_FIFO_STATUS_3QUARTER: (3/4) <= fifo level < (1).
+ * - EDMA_FIFO_STATUS_EMPTY: fifo is empty.
+ * - EDMA_FIFO_STATUS_FULL: fifo is full.
+ */
+uint8_t edma_fifo_status_get(edma_stream_type *edma_streamx)
+{
+ return (uint8_t)(edma_streamx->fctrl_bit.fsts);
+}
+
+/**
+ * @brief get the edma flag.
+ * @param edma_flag:
+ * this parameter can be one of the following values:
+ * - EDMA_FERR1_FLAG - EDMA_DMERR1_FLAG - EDMA_DTERR1_FLAG - EDMA_HDT1_FLAG - EDMA_FDT1_FLAG
+ * - EDMA_FERR2_FLAG - EDMA_DMERR2_FLAG - EDMA_DTERR2_FLAG - EDMA_HDT2_FLAG - EDMA_FDT2_FLAG
+ * - EDMA_FERR3_FLAG - EDMA_DMERR3_FLAG - EDMA_DTERR3_FLAG - EDMA_HDT3_FLAG - EDMA_FDT3_FLAG
+ * - EDMA_FERR4_FLAG - EDMA_DMERR4_FLAG - EDMA_DTERR4_FLAG - EDMA_HDT4_FLAG - EDMA_FDT4_FLAG
+ * - EDMA_FERR5_FLAG - EDMA_DMERR5_FLAG - EDMA_DTERR5_FLAG - EDMA_HDT5_FLAG - EDMA_FDT5_FLAG
+ * - EDMA_FERR6_FLAG - EDMA_DMERR6_FLAG - EDMA_DTERR6_FLAG - EDMA_HDT6_FLAG - EDMA_FDT6_FLAG
+ * - EDMA_FERR7_FLAG - EDMA_DMERR7_FLAG - EDMA_DTERR7_FLAG - EDMA_HDT7_FLAG - EDMA_FDT7_FLAG
+ * - EDMA_FERR8_FLAG - EDMA_DMERR8_FLAG - EDMA_DTERR8_FLAG - EDMA_HDT8_FLAG - EDMA_FDT8_FLAG
+ * @retval the new state of edma flag (SET or RESET).
+ */
+flag_status edma_flag_get(uint32_t edma_flag)
+{
+ uint32_t status;
+
+ if(edma_flag > ((uint32_t)0x20000000))
+ {
+ status = EDMA->sts2;
+ }
+ else
+ {
+ status = EDMA->sts1;
+ }
+
+ if((status & edma_flag) != ((uint32_t)RESET))
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief clear the edma flag.
+ * @param edma_flag:
+ * this parameter can be one of the following values:
+ * - EDMA_FERR1_FLAG - EDMA_DMERR1_FLAG - EDMA_DTERR1_FLAG - EDMA_HDT1_FLAG - EDMA_FDT1_FLAG
+ * - EDMA_FERR2_FLAG - EDMA_DMERR2_FLAG - EDMA_DTERR2_FLAG - EDMA_HDT2_FLAG - EDMA_FDT2_FLAG
+ * - EDMA_FERR3_FLAG - EDMA_DMERR3_FLAG - EDMA_DTERR3_FLAG - EDMA_HDT3_FLAG - EDMA_FDT3_FLAG
+ * - EDMA_FERR4_FLAG - EDMA_DMERR4_FLAG - EDMA_DTERR4_FLAG - EDMA_HDT4_FLAG - EDMA_FDT4_FLAG
+ * - EDMA_FERR5_FLAG - EDMA_DMERR5_FLAG - EDMA_DTERR5_FLAG - EDMA_HDT5_FLAG - EDMA_FDT5_FLAG
+ * - EDMA_FERR6_FLAG - EDMA_DMERR6_FLAG - EDMA_DTERR6_FLAG - EDMA_HDT6_FLAG - EDMA_FDT6_FLAG
+ * - EDMA_FERR7_FLAG - EDMA_DMERR7_FLAG - EDMA_DTERR7_FLAG - EDMA_HDT7_FLAG - EDMA_FDT7_FLAG
+ * - EDMA_FERR8_FLAG - EDMA_DMERR8_FLAG - EDMA_DTERR8_FLAG - EDMA_HDT8_FLAG - EDMA_FDT8_FLAG
+ * @retval none.
+ */
+void edma_flag_clear(uint32_t edma_flag)
+{
+ if(edma_flag > ((uint32_t)0x20000000))
+ {
+ EDMA->clr2 = (uint32_t)(edma_flag & 0x0FFFFFFF);
+ }
+ else
+ {
+ EDMA->clr1 = edma_flag;
+ }
+}
+
+/**
+ * @brief initialize the edma 2d mode.
+ * @param edma_streamx_2d:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1_2D
+ * - EDMA_STREAM2_2D
+ * - EDMA_STREAM3_2D
+ * - EDMA_STREAM4_2D
+ * - EDMA_STREAM5_2D
+ * - EDMA_STREAM6_2D
+ * - EDMA_STREAM7_2D
+ * - EDMA_STREAM8_2D
+ * @param src_stride: source stride(-32768 ~ 32767).
+ * @param dst_stride: destination stride(-32768 ~ 32767).
+ * @param xcnt: x dimension transfer count(0x0000~ 0xFFFF).
+ * @param ycnt: y dimension transfer count(0x0000~ 0xFFFF).
+ * @retval none.
+ */
+void edma_2d_init(edma_stream_2d_type *edma_streamx_2d, int16_t src_stride, int16_t dst_stride, uint16_t xcnt, uint16_t ycnt)
+{
+ edma_streamx_2d->s2dcnt = (uint32_t)((ycnt << 16) | (xcnt));
+
+ edma_streamx_2d->stride = (uint32_t)((dst_stride << 16) | (src_stride));
+}
+
+/**
+ * @brief enable or disable the edma 2d mode.
+ * @param edma_streamx_2d:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1_2D
+ * - EDMA_STREAM2_2D
+ * - EDMA_STREAM3_2D
+ * - EDMA_STREAM4_2D
+ * - EDMA_STREAM5_2D
+ * - EDMA_STREAM6_2D
+ * - EDMA_STREAM7_2D
+ * - EDMA_STREAM8_2D
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void edma_2d_enable(edma_stream_2d_type *edma_streamx_2d, confirm_state new_state)
+{
+ uint32_t offset;
+
+ offset = ((uint32_t)edma_streamx_2d - EDMA_STREAM1_2D_BASE) / 4;
+
+ if(new_state != FALSE)
+ {
+ EDMA->s2dctrl |= (uint16_t)0x0001 << offset;
+ }
+ else
+ {
+ EDMA->s2dctrl &= ~((uint16_t)0x0001 << offset);
+ }
+}
+
+/**
+ * @brief initialize the edma link list.
+ * @param edma_streamx_ll:
+ * this parameter can be one of the following values:
+ * - EDMA_STREAM1_LL
+ * - EDMA_STREAM2_LL
+ * - EDMA_STREAM3_LL
+ * - EDMA_STREAM4_LL
+ * - EDMA_STREAM5_LL
+ * - EDMA_STREAM6_LL
+ * - EDMA_STREAM7_LL
+ * - EDMA_STREAM8_LL
+ * @param pointer: link list pointer.
+ * @retval none.
+ */
+void edma_link_list_init(edma_stream_link_list_type *edma_streamx_ll, uint32_t pointer)
+{
+ edma_streamx_ll->llp = pointer;
+}
+
+/**
+ * @brief enable or disable the edma stream link list mode.
+ * @param edma_streamx_ll:
+ * this parameter can be any combination of the following values:
+ * - EDMA_STREAM1_LL
+ * - EDMA_STREAM2_LL
+ * - EDMA_STREAM3_LL
+ * - EDMA_STREAM4_LL
+ * - EDMA_STREAM5_LL
+ * - EDMA_STREAM6_LL
+ * - EDMA_STREAM7_LL
+ * - EDMA_STREAM8_LL
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void edma_link_list_enable(edma_stream_link_list_type *edma_streamx_ll, confirm_state new_state)
+{
+ uint32_t offset;
+
+ offset = ((uint32_t)edma_streamx_ll - EDMA_STREAM1_LL_BASE) / 4;
+
+ if(new_state != FALSE)
+ {
+ EDMA->llctrl |= (uint16_t)0x0001 << offset;
+ }
+ else
+ {
+ EDMA->llctrl &= ~((uint16_t)0x0001 << offset);
+ }
+}
+
+/**
+ * @brief enable or disable the edma edmamux.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void edmamux_enable(confirm_state new_state)
+{
+ EDMA->muxsel_bit.tblsel = new_state;
+}
+
+/**
+ * @brief edmamux init.
+ * @param edmamux_channelx:
+ * this parameter can be one of the following values:
+ * - EDMAMUX_CHANNEL1
+ * - EDMAMUX_CHANNEL2
+ * - EDMAMUX_CHANNEL3
+ * - EDMAMUX_CHANNEL4
+ * - EDMAMUX_CHANNEL5
+ * - EDMAMUX_CHANNEL6
+ * - EDMAMUX_CHANNEL7
+ * - EDMAMUX_CHANNEL8
+ * @param edmamux_req_id:
+ * this parameter can be one of the following values:
+ * - EDMAMUX_DMAREQ_ID_REQ_G1 - EDMAMUX_DMAREQ_ID_REQ_G2 - EDMAMUX_DMAREQ_ID_REQ_G3 - EDMAMUX_DMAREQ_ID_REQ_G4
+ * - EDMAMUX_DMAREQ_ID_ADC1 - EDMAMUX_DMAREQ_ID_ADC2 - EDMAMUX_DMAREQ_ID_ADC3 - EDMAMUX_DMAREQ_ID_DAC1
+ * - EDMAMUX_DMAREQ_ID_DAC2 - EDMAMUX_DMAREQ_ID_TMR6_OVERFLOW- EDMAMUX_DMAREQ_ID_TMR7_OVERFLOW- EDMAMUX_DMAREQ_ID_SPI1_RX
+ * - EDMAMUX_DMAREQ_ID_SPI1_TX - EDMAMUX_DMAREQ_ID_SPI2_RX - EDMAMUX_DMAREQ_ID_SPI2_TX - EDMAMUX_DMAREQ_ID_SPI3_RX
+ * - EDMAMUX_DMAREQ_ID_SPI3_TX - EDMAMUX_DMAREQ_ID_SPI4_RX - EDMAMUX_DMAREQ_ID_SPI4_TX - EDMAMUX_DMAREQ_ID_I2S2_EXT_RX
+ * - EDMAMUX_DMAREQ_ID_I2S2_EXT_TX - EDMAMUX_DMAREQ_ID_I2S3_EXT_RX - EDMAMUX_DMAREQ_ID_I2S3_EXT_TX - EDMAMUX_DMAREQ_ID_I2C1_RX
+ * - EDMAMUX_DMAREQ_ID_I2C1_TX - EDMAMUX_DMAREQ_ID_I2C2_RX - EDMAMUX_DMAREQ_ID_I2C2_TX - EDMAMUX_DMAREQ_ID_I2C3_RX
+ * - EDMAMUX_DMAREQ_ID_I2C3_TX - EDMAMUX_DMAREQ_ID_USART1_RX - EDMAMUX_DMAREQ_ID_USART1_TX - EDMAMUX_DMAREQ_ID_USART2_RX
+ * - EDMAMUX_DMAREQ_ID_USART2_TX - EDMAMUX_DMAREQ_ID_USART3_RX - EDMAMUX_DMAREQ_ID_USART3_TX - EDMAMUX_DMAREQ_ID_UART4_RX
+ * - EDMAMUX_DMAREQ_ID_UART4_TX - EDMAMUX_DMAREQ_ID_UART5_RX - EDMAMUX_DMAREQ_ID_UART5_TX - EDMAMUX_DMAREQ_ID_USART6_RX
+ * - EDMAMUX_DMAREQ_ID_USART6_TX - EDMAMUX_DMAREQ_ID_UART7_RX - EDMAMUX_DMAREQ_ID_UART7_TX - EDMAMUX_DMAREQ_ID_UART8_RX
+ * - EDMAMUX_DMAREQ_ID_UART8_TX - EDMAMUX_DMAREQ_ID_SDIO1 - EDMAMUX_DMAREQ_ID_SDIO2 - EDMAMUX_DMAREQ_ID_QSPI1
+ * - EDMAMUX_DMAREQ_ID_QSPI2 - EDMAMUX_DMAREQ_ID_TMR1_CH1 - EDMAMUX_DMAREQ_ID_TMR1_CH2 - EDMAMUX_DMAREQ_ID_TMR1_CH3
+ * - EDMAMUX_DMAREQ_ID_TMR1_CH4 - EDMAMUX_DMAREQ_ID_TMR1_OVERFLOW- EDMAMUX_DMAREQ_ID_TMR1_TRIG - EDMAMUX_DMAREQ_ID_TMR1_COM
+ * - EDMAMUX_DMAREQ_ID_TMR8_CH1 - EDMAMUX_DMAREQ_ID_TMR8_CH2 - EDMAMUX_DMAREQ_ID_TMR8_CH3 - EDMAMUX_DMAREQ_ID_TMR8_CH4
+ * - EDMAMUX_DMAREQ_ID_TMR8_UP - EDMAMUX_DMAREQ_ID_TMR8_TRIG - EDMAMUX_DMAREQ_ID_TMR8_COM - EDMAMUX_DMAREQ_ID_TMR2_CH1
+ * - EDMAMUX_DMAREQ_ID_TMR2_CH2 - EDMAMUX_DMAREQ_ID_TMR2_CH3 - EDMAMUX_DMAREQ_ID_TMR2_CH4 - EDMAMUX_DMAREQ_ID_TMR2_OVERFLOW
+ * - EDMAMUX_DMAREQ_ID_TMR2_TRIG - EDMAMUX_DMAREQ_ID_TMR3_CH1 - EDMAMUX_DMAREQ_ID_TMR3_CH2 - EDMAMUX_DMAREQ_ID_TMR3_CH3
+ * - EDMAMUX_DMAREQ_ID_TMR3_CH4 - EDMAMUX_DMAREQ_ID_TMR3_OVERFLOW- EDMAMUX_DMAREQ_ID_TMR3_TRIG - EDMAMUX_DMAREQ_ID_TMR4_CH1
+ * - EDMAMUX_DMAREQ_ID_TMR4_CH2 - EDMAMUX_DMAREQ_ID_TMR4_CH3 - EDMAMUX_DMAREQ_ID_TMR4_CH4 - EDMAMUX_DMAREQ_ID_TMR4_OVERFLOW
+ * - EDMAMUX_DMAREQ_ID_TMR4_TRIG - EDMAMUX_DMAREQ_ID_TMR5_CH1 - EDMAMUX_DMAREQ_ID_TMR5_CH2 - EDMAMUX_DMAREQ_ID_TMR5_CH3
+ * - EDMAMUX_DMAREQ_ID_TMR5_CH4 - EDMAMUX_DMAREQ_ID_TMR5_OVERFLOW- EDMAMUX_DMAREQ_ID_TMR5_TRIG - EDMAMUX_DMAREQ_ID_TMR20_CH1
+ * - EDMAMUX_DMAREQ_ID_TMR20_CH2 - EDMAMUX_DMAREQ_ID_TMR20_CH3 - EDMAMUX_DMAREQ_ID_TMR20_CH4 - EDMAMUX_DMAREQ_ID_TMR20_OVERFLOW
+ * - EDMAMUX_DMAREQ_ID_TMR20_TRIG - EDMAMUX_DMAREQ_ID_TMR20_HALL - EDMAMUX_DMAREQ_ID_DVP
+ * @retval none.
+ */
+void edmamux_init(edmamux_channel_type *edmamux_channelx, edmamux_requst_id_sel_type edmamux_req_id)
+{
+ edmamux_channelx->muxctrl_bit.reqsel = edmamux_req_id;
+}
+
+/**
+ * @brief edmamux sync init struct config with its default value.
+ * @param edmamux_sync_init_struct: pointer to a edmamux_sync_init_type structure which will be initialized.
+ * @retval none.
+ */
+void edmamux_sync_default_para_init(edmamux_sync_init_type *edmamux_sync_init_struct)
+{
+ edmamux_sync_init_struct->sync_enable = FALSE;
+ edmamux_sync_init_struct->sync_event_enable = FALSE;
+ edmamux_sync_init_struct->sync_polarity = EDMAMUX_SYNC_POLARITY_DISABLE;
+ edmamux_sync_init_struct->sync_request_number = 0x0;
+ edmamux_sync_init_struct->sync_signal_sel = EDMAMUX_SYNC_ID_EXINT0;
+}
+
+/**
+ * @brief edmamux synchronization config.
+ * @param edmamux_channelx:
+ * this parameter can be one of the following values:
+ * - EDMAMUX_CHANNEL1
+ * - EDMAMUX_CHANNEL2
+ * - EDMAMUX_CHANNEL3
+ * - EDMAMUX_CHANNEL4
+ * - EDMAMUX_CHANNEL5
+ * - EDMAMUX_CHANNEL6
+ * - EDMAMUX_CHANNEL7
+ * - EDMAMUX_CHANNEL8
+ * @param edmamux_sync_init_struct: ointer to a edmamux_sync_init_type structure.
+ * @retval none.
+ */
+void edmamux_sync_config(edmamux_channel_type *edmamux_channelx, edmamux_sync_init_type *edmamux_sync_init_struct)
+{
+ edmamux_channelx->muxctrl_bit.syncsel = edmamux_sync_init_struct->sync_signal_sel;
+ edmamux_channelx->muxctrl_bit.syncpol = edmamux_sync_init_struct->sync_polarity;
+ edmamux_channelx->muxctrl_bit.reqcnt = edmamux_sync_init_struct->sync_request_number;
+ edmamux_channelx->muxctrl_bit.evtgen = edmamux_sync_init_struct->sync_event_enable;
+ edmamux_channelx->muxctrl_bit.syncen = edmamux_sync_init_struct->sync_enable;
+}
+
+/**
+ * @brief edmamux request generator init struct config with its default value.
+ * @param edmamux_gen_init_struct: pointer to a edmamux_gen_init_type structure which will be initialized.
+ * @retval none.
+ */
+void edmamux_generator_default_para_init(edmamux_gen_init_type *edmamux_gen_init_struct)
+{
+ edmamux_gen_init_struct->gen_enable = FALSE;
+ edmamux_gen_init_struct->gen_polarity = EDMAMUX_GEN_POLARITY_DISABLE;
+ edmamux_gen_init_struct->gen_request_number = 0x0;
+ edmamux_gen_init_struct->gen_signal_sel = EDMAMUX_GEN_ID_EXINT0;
+}
+
+/**
+ * @brief edmamux request generator init.
+ * @param edmamux_gen_init_struct: pointer to a edmamux_gen_init_type structure which will be initialized.
+ * @retval none.
+ */
+void edmamux_generator_config(edmamux_generator_type *edmamux_gen_x, edmamux_gen_init_type *edmamux_gen_init_struct)
+{
+ edmamux_gen_x->gctrl_bit.sigsel = edmamux_gen_init_struct->gen_signal_sel;
+ edmamux_gen_x->gctrl_bit.gpol = edmamux_gen_init_struct->gen_polarity;
+ edmamux_gen_x->gctrl_bit.greqcnt = edmamux_gen_init_struct->gen_request_number;
+ edmamux_gen_x->gctrl_bit.gen = edmamux_gen_init_struct->gen_enable;
+}
+
+/**
+ * @brief enable or disable the edmamux sync interrupts.
+ * @param edmamux_channelx:
+ * this parameter can be one of the following values:
+ * - EDMAMUX_CHANNEL1
+ * - EDMAMUX_CHANNEL2
+ * - EDMAMUX_CHANNEL3
+ * - EDMAMUX_CHANNEL4
+ * - EDMAMUX_CHANNEL5
+ * - EDMAMUX_CHANNEL6
+ * - EDMAMUX_CHANNEL7
+ * - EDMAMUX_CHANNEL8
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void edmamux_sync_interrupt_enable(edmamux_channel_type *edmamux_channelx, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ edmamux_channelx->muxctrl_bit.syncovien = TRUE;
+ }
+ else
+ {
+ edmamux_channelx->muxctrl_bit.syncovien = FALSE;
+ }
+}
+
+/**
+ * @brief enable or disable the edmamux request generator interrupts.
+ * @param edmamux_gen_x: pointer to a edmamux_generator_type structure.
+ * this parameter can be one of the following values:
+ * - EDMAMUX_GENERATOR1
+ * - EDMAMUX_GENERATOR2
+ * - EDMAMUX_GENERATOR3
+ * - EDMAMUX_GENERATOR4
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void edmamux_generator_interrupt_enable(edmamux_generator_type *edmamux_gen_x, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ edmamux_gen_x->gctrl_bit.trgovien = TRUE;
+ }
+ else
+ {
+ edmamux_gen_x->gctrl_bit.trgovien = FALSE;
+ }
+}
+
+/**
+ * @brief edmamux sync flag get.
+ * @param flag
+ * this parameter can be any combination of the following values:
+ * - EDMAMUX_SYNC_OV1_FLAG
+ * - EDMAMUX_SYNC_OV2_FLAG
+ * - EDMAMUX_SYNC_OV3_FLAG
+ * - EDMAMUX_SYNC_OV4_FLAG
+ * - EDMAMUX_SYNC_OV5_FLAG
+ * - EDMAMUX_SYNC_OV6_FLAG
+ * - EDMAMUX_SYNC_OV7_FLAG
+ * - EDMAMUX_SYNC_OV8_FLAG
+ * @retval state of edmamux sync flag.
+ */
+flag_status edmamux_sync_flag_get(uint32_t flag)
+{
+ if((EDMA->muxsyncsts & flag) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief edmamux sync flag clear.
+ * @param flag
+ * this parameter can be any combination of the following values:
+ * - EDMAMUX_SYNC_OV1_FLAG
+ * - EDMAMUX_SYNC_OV2_FLAG
+ * - EDMAMUX_SYNC_OV3_FLAG
+ * - EDMAMUX_SYNC_OV4_FLAG
+ * - EDMAMUX_SYNC_OV5_FLAG
+ * - EDMAMUX_SYNC_OV6_FLAG
+ * - EDMAMUX_SYNC_OV7_FLAG
+ * - EDMAMUX_SYNC_OV8_FLAG
+ * @retval none.
+ */
+void edmamux_sync_flag_clear(uint32_t flag)
+{
+ EDMA->muxsyncclr = flag;
+}
+
+/**
+ * @brief edmamux request generator flag get.
+ * @param flag
+ * this parameter can be any combination of the following values:
+ * - EDMAMUX_GEN_TRIG_OV1_FLAG
+ * - EDMAMUX_GEN_TRIG_OV2_FLAG
+ * - EDMAMUX_GEN_TRIG_OV3_FLAG
+ * - EDMAMUX_GEN_TRIG_OV4_FLAG
+ * @retval state of edmamux sync flag.
+ */
+flag_status edmamux_generator_flag_get(uint32_t flag)
+{
+ if((EDMA->muxgsts & flag) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief edmamux request generator flag clear.
+ * @param flag
+ * this parameter can be any combination of the following values:
+ * - EDMAMUX_GEN_TRIG_OV1_FLAG
+ * - EDMAMUX_GEN_TRIG_OV2_FLAG
+ * - EDMAMUX_GEN_TRIG_OV3_FLAG
+ * - EDMAMUX_GEN_TRIG_OV4_FLAG
+ * @retval none.
+ */
+void edmamux_generator_flag_clear(uint32_t flag)
+{
+ EDMA->muxgclr = flag;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_emac.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_emac.c
new file mode 100644
index 0000000..1c8561b
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_emac.c
@@ -0,0 +1,2342 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_emac.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the emac firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup EMAC
+ * @brief EMAC driver modules
+ * @{
+ */
+
+#ifdef EMAC_MODULE_ENABLED
+
+/** @defgroup EMAC_private_functions
+ * @{
+ */
+
+#if defined (EMAC_BASE)
+/**
+ * @brief global pointers on tx and rx descriptor used to track transmit and receive descriptors
+ */
+emac_dma_desc_type *dma_tx_desc_to_set;
+emac_dma_desc_type *dma_rx_desc_to_get;
+
+/* emac private function */
+static void emac_delay(uint32_t delay);
+
+/**
+ * @brief deinitialize the emac peripheral registers to their default reset values.
+ * @param none
+ * @retval none
+ */
+void emac_reset(void)
+{
+ crm_periph_reset(CRM_EMAC_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_EMAC_PERIPH_RESET, FALSE);
+}
+
+/**
+ * @brief initialize emac control structure
+ * @param emac_control_config_type
+ * @retval none
+ */
+void emac_control_para_init(emac_control_config_type *control_para)
+{
+ control_para->auto_nego = EMAC_AUTO_NEGOTIATION_OFF;
+ control_para->auto_pad_crc_strip = FALSE;
+ control_para->back_off_limit = EMAC_BACKOFF_LIMIT_0;
+ control_para->carrier_sense_disable = FALSE;
+ control_para->deferral_check = FALSE;
+ control_para->duplex_mode = EMAC_HALF_DUPLEX;
+ control_para->fast_ethernet_speed = EMAC_SPEED_10MBPS;
+ control_para->interframe_gap = EMAC_INTERFRAME_GAP_96BIT;
+ control_para->ipv4_checksum_offload = FALSE;
+ control_para->jabber_disable = FALSE;
+ control_para->loopback_mode = FALSE;
+ control_para->receive_own_disable = FALSE;
+ control_para->retry_disable = FALSE;
+ control_para->watchdog_disable = FALSE;
+}
+
+/**
+ * @brief according to hclk to set mdc clock frequency.
+ * @param none
+ * @retval none
+ */
+void emac_clock_range_set(void)
+{
+ uint8_t bits_value = 0;
+ crm_clocks_freq_type clocks_freq = {0};
+
+ /* clear clock range bits */
+ EMAC->miiaddr_bit.cr = bits_value;
+
+ crm_clocks_freq_get(&clocks_freq);
+
+ if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_20MHZ) && (clocks_freq.ahb_freq < EMAC_HCLK_BORDER_35MHZ))
+ {
+ bits_value = EMAC_CLOCK_RANGE_20_TO_35;
+ }
+ else if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_35MHZ) && (clocks_freq.ahb_freq < EMAC_HCLK_BORDER_60MHZ))
+ {
+ bits_value = EMAC_CLOCK_RANGE_35_TO_60;
+ }
+ else if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_60MHZ) && (clocks_freq.ahb_freq < EMAC_HCLK_BORDER_100MHZ))
+ {
+ bits_value = EMAC_CLOCK_RANGE_60_TO_100;
+ }
+ else if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_100MHZ) && (clocks_freq.ahb_freq < EMAC_HCLK_BORDER_150MHZ))
+ {
+ bits_value = EMAC_CLOCK_RANGE_100_TO_150;
+ }
+ else if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_150MHZ) && (clocks_freq.ahb_freq < EMAC_HCLK_BORDER_250MHZ))
+ {
+ bits_value = EMAC_CLOCK_RANGE_150_TO_250;
+ }
+ else if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_250MHZ) && (clocks_freq.ahb_freq <= EMAC_HCLK_BORDER_288MHZ))
+ {
+ bits_value = EMAC_CLOCK_RANGE_250_TO_288;
+ }
+
+ EMAC->miiaddr_bit.cr = bits_value;
+}
+
+/**
+ * @brief configure emac control setting.
+ * @param control_struct: control setting of mac control register.
+ * @retval none
+ */
+void emac_control_config(emac_control_config_type *control_struct)
+{
+ emac_deferral_check_set(control_struct->deferral_check);
+ emac_backoff_limit_set(control_struct->back_off_limit);
+ emac_auto_pad_crc_stripping_set(control_struct->auto_pad_crc_strip);
+ emac_retry_disable(control_struct->retry_disable);
+ emac_ipv4_checksum_offload_set(control_struct->ipv4_checksum_offload);
+ emac_loopback_mode_enable(control_struct->loopback_mode);
+ emac_receive_own_disable(control_struct->receive_own_disable);
+ emac_carrier_sense_disable(control_struct->carrier_sense_disable);
+ emac_interframe_gap_set(control_struct->interframe_gap);
+ emac_jabber_disable(control_struct->jabber_disable);
+ emac_watchdog_disable(control_struct->watchdog_disable);
+}
+
+/**
+ * @brief reset emac dma
+ * @param none
+ * @retval none
+ */
+void emac_dma_software_reset_set(void)
+{
+ EMAC_DMA->bm_bit.swr = 1;
+}
+
+/**
+ * @brief get emac dma reset status
+ * @param none
+ * @retval TRUE of FALSE
+ */
+flag_status emac_dma_software_reset_get(void)
+{
+ if(EMAC_DMA->bm_bit.swr)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief enable emac and dma reception/transmission
+ * @param none
+ * @retval none
+ */
+void emac_start(void)
+{
+ /* enable transmit state machine of the mac for transmission on the mii */
+ emac_trasmitter_enable(TRUE);
+
+ /* flush transmit fifo */
+ emac_dma_operations_set(EMAC_DMA_OPS_FLUSH_TRANSMIT_FIFO, TRUE);
+
+ /* enable receive state machine of the mac for reception from the mii */
+ emac_receiver_enable(TRUE);
+
+ /* start dma transmission */
+ emac_dma_operations_set(EMAC_DMA_OPS_START_STOP_TRANSMIT, TRUE);
+
+ /* start dma reception */
+ emac_dma_operations_set(EMAC_DMA_OPS_START_STOP_RECEIVE, TRUE);
+}
+
+/**
+ * @brief stop emac and dma reception/transmission
+ * @param none
+ * @retval none
+ */
+void emac_stop(void)
+{
+ /* stop dma transmission */
+ emac_dma_operations_set(EMAC_DMA_OPS_START_STOP_TRANSMIT, FALSE);
+
+ /* stop dma reception */
+ emac_dma_operations_set(EMAC_DMA_OPS_START_STOP_RECEIVE, FALSE);
+
+ /* stop receive state machine of the mac for reception from the mii */
+ emac_receiver_enable(FALSE);
+
+ /* flush transmit fifo */
+ emac_dma_operations_set(EMAC_DMA_OPS_FLUSH_TRANSMIT_FIFO, TRUE);
+
+ /* stop transmit state machine of the mac for transmission on the mii */
+ emac_trasmitter_enable(FALSE);
+}
+
+
+/**
+ * @brief write phy data.
+ * @param address: phy address.
+ * @param reg: register of phy.
+ * @param data: value that wants to write to phy.
+ * @retval SUCCESS or ERROR
+ */
+error_status emac_phy_register_write(uint8_t address, uint8_t reg, uint16_t data)
+{
+ uint32_t timeout = 0;
+
+ EMAC->miidt_bit.md = data;
+
+ EMAC->miiaddr_bit.pa = address;
+ EMAC->miiaddr_bit.mii = reg;
+ EMAC->miiaddr_bit.mw = 1;
+ EMAC->miiaddr_bit.mb = 1;
+
+ do
+ {
+ timeout++;
+ } while((EMAC->miiaddr_bit.mb) && (timeout < PHY_TIMEOUT));
+
+ if(timeout == PHY_TIMEOUT)
+ {
+ return ERROR;
+ }
+ return SUCCESS;
+}
+
+/**
+ * @brief read phy data
+ * @param address: phy address.
+ * @param reg: register of phy.
+ * @param data: value that is read from phy.
+ * @retval SUCCESS or ERROR
+ */
+error_status emac_phy_register_read(uint8_t address, uint8_t reg, uint16_t *data)
+{
+ uint32_t timeout = 0;
+
+ EMAC->miiaddr_bit.pa = address;
+ EMAC->miiaddr_bit.mii = reg;
+ EMAC->miiaddr_bit.mw = 0;
+ EMAC->miiaddr_bit.mb = 1;
+
+ do
+ {
+ *data = EMAC->miidt_bit.md;
+ } while((EMAC->miiaddr_bit.mb) && (timeout < PHY_TIMEOUT));
+
+ if(timeout == PHY_TIMEOUT)
+ {
+ return ERROR;
+ }
+
+ *data = EMAC->miidt_bit.md;
+ return SUCCESS;
+}
+
+/**
+ * @brief emac receiver enable.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_receiver_enable(confirm_state new_state)
+{
+ __IO uint32_t temp = 0;
+
+ EMAC->ctrl_bit.re = new_state;
+
+ temp = EMAC->ctrl;
+ emac_delay(1);
+ EMAC->ctrl = temp;
+}
+
+/**
+ * @brief emac transmitter enable.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_trasmitter_enable(confirm_state new_state)
+{
+ __IO uint32_t temp = 0;
+
+ EMAC->ctrl_bit.te = new_state;
+
+ temp = EMAC->ctrl;
+ emac_delay(1);
+ EMAC->ctrl = temp;
+}
+
+/**
+ * @brief emac defferal check enable, only avalible in half-duplex mode.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_deferral_check_set(confirm_state new_state)
+{
+ EMAC->ctrl_bit.dc = new_state;
+}
+
+/**
+ * @brief emac back-off limit, only avalible in half-duplex mode.
+ * @param slot_time: waiting time of retransmission after collision
+ * this parameter can be one of the following values:
+ * - EMAC_BACKOFF_LIMIT_0
+ * - EMAC_BACKOFF_LIMIT_1
+ * - EMAC_BACKOFF_LIMIT_2
+ * - EMAC_BACKOFF_LIMIT_3
+ * @retval none
+ */
+void emac_backoff_limit_set(emac_bol_type slot_time)
+{
+ EMAC->ctrl_bit.bl = slot_time;
+}
+
+/**
+ * @brief set mac automatic pad/CRC stripping.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_auto_pad_crc_stripping_set(confirm_state new_state)
+{
+ EMAC->ctrl_bit.acs = new_state;
+}
+
+/**
+ * @brief transmittion retry disable.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_retry_disable(confirm_state new_state)
+{
+ EMAC->ctrl_bit.dr = new_state;
+}
+
+/**
+ * @brief set ipv4 checksum offload.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ipv4_checksum_offload_set(confirm_state new_state)
+{
+ EMAC->ctrl_bit.ipc = new_state;
+}
+
+/**
+ * @brief enable loopback mode.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_loopback_mode_enable(confirm_state new_state)
+{
+ EMAC->ctrl_bit.lm = new_state;
+}
+
+/**
+ * @brief receive own disable.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_receive_own_disable(confirm_state new_state)
+{
+ EMAC->ctrl_bit.dro = new_state;
+}
+
+/**
+ * @brief carrier sense disbale.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_carrier_sense_disable(confirm_state new_state)
+{
+ EMAC->ctrl_bit.dcs = new_state;
+}
+
+/**
+ * @brief set minimum interframe gap between frames during transmission.
+ * @param number: interframe gap number.
+ * this parameter can be one of the following values:
+ * - EMAC_FRAME_GAP_96BIT
+ * - EMAC_FRAME_GAP_88BIT
+ * - EMAC_FRAME_GAP_80BIT
+ * - EMAC_FRAME_GAP_72BIT
+ * - EMAC_FRAME_GAP_64BIT
+ * - EMAC_FRAME_GAP_56BIT
+ * - EMAC_FRAME_GAP_48BIT
+ * - EMAC_FRAME_GAP_40BIT
+ * @retval none
+ */
+void emac_interframe_gap_set(emac_intergrame_gap_type number)
+{
+ EMAC->ctrl_bit.ifg = number;
+}
+
+/**
+ * @brief jabber disable.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_jabber_disable(confirm_state new_state)
+{
+ EMAC->ctrl_bit.jd = new_state;
+}
+
+/**
+ * @brief watchdog disable.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_watchdog_disable(confirm_state new_state)
+{
+ EMAC->ctrl_bit.wd = new_state;
+}
+
+/**
+ * @brief set mac fast emac speed.
+ * @param speed: mac bandwidth
+ * this parameter can be one of the following values:
+ * - EMAC_SPEED_10MBPS
+ * - EMAC_SPEED_100MBPS
+ * @retval none
+ */
+void emac_fast_speed_set(emac_speed_type speed)
+{
+ EMAC->ctrl_bit.fes = speed;
+}
+
+/**
+ * @brief set duplex mode.
+ * @param duplex_mode: communication mode
+ * this parameter can be one of the following values:
+ * - EMAC_HALF_DUPLEX
+ * - EMAC_FULL_DUPLEX
+ * @retval none
+ */
+void emac_duplex_mode_set(emac_duplex_type duplex_mode)
+{
+ EMAC->ctrl_bit.dm = duplex_mode;
+}
+
+/**
+ * @brief set mac promiscuous mode.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_promiscuous_mode_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.pr = new_state;
+}
+
+/**
+ * @brief hash unicast.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_hash_unicast_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.huc = new_state;
+}
+
+/**
+ * @brief hash multicast.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_hash_multicast_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.hmc = new_state;
+}
+
+/**
+ * @brief destination address inverse filtering.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_dstaddr_inverse_filter_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.daif = new_state;
+}
+
+/**
+ * @brief pass all multicasting frames.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_pass_all_multicasting_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.pmc = new_state;
+}
+
+/**
+ * @brief broadcast frames disable.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_broadcast_frames_disable(confirm_state new_state)
+{
+ EMAC->frmf_bit.dbf = new_state;
+}
+
+/**
+ * @brief set mac how to pass control frames.
+ * @param condition: set what control frame can pass filter.
+ * this parameter can be one of the following values:
+ * - EMAC_CONTROL_FRAME_PASSING_NO
+ * - EMAC_CONTROL_FRAME_PASSING_ALL
+ * - EMAC_CONTROL_FRAME_PASSING_MATCH
+ * @retval none
+ */
+void emac_pass_control_frames_set(emac_control_frames_filter_type condition)
+{
+ EMAC->frmf_bit.pcf = condition;
+}
+
+/**
+ * @brief source address inverse filtering.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_srcaddr_inverse_filter_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.saif = new_state;
+}
+
+/**
+ * @brief source address filtering.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_srcaddr_filter_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.saf = new_state;
+}
+
+/**
+ * @brief mac uses hash or perfect filter.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_hash_perfect_filter_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.hpf = new_state;
+}
+
+/**
+ * @brief mac receives all frames.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_receive_all_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.ra = new_state;
+}
+
+/**
+ * @brief hash table high 32-bit.
+ * @param high32bits: the highest 32-bit of hash table.
+ * @retval none
+ */
+void emac_hash_table_high32bits_set(uint32_t high32bits)
+{
+ EMAC->hth_bit.hth = high32bits;
+}
+
+/**
+ * @brief hash table low 32-bit.
+ * @param low32bits: the lowest 32-bit of hash table.
+ * @retval none
+ */
+void emac_hash_table_low32bits_set(uint32_t low32bits)
+{
+ EMAC->htl_bit.htl = low32bits;
+}
+
+/**
+ * @brief mii busy status.
+ * @param none
+ * @retval SET or RESET
+ */
+flag_status emac_mii_busy_get(void)
+{
+ if(EMAC->miiaddr_bit.mb) {
+ return SET;
+ }
+ else {
+ return RESET;
+ }
+}
+
+/**
+ * @brief tell phy that will be written.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_mii_write(confirm_state new_state)
+{
+ EMAC->miiaddr_bit.mw = new_state;
+}
+
+/**
+ * @brief set flow control busy in full-duplex mode, back pressure activate in half-duplex mode.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_fcb_bpa_set(confirm_state new_state)
+{
+ EMAC->fctrl_bit.fcbbpa = new_state;
+}
+
+/**
+ * @brief set transmit flow control.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_transmit_flow_control_enable(confirm_state new_state)
+{
+ EMAC->fctrl_bit.etf = new_state;
+}
+
+/**
+ * @brief set receive flow control.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_receive_flow_control_enable(confirm_state new_state)
+{
+ EMAC->fctrl_bit.erf = new_state;
+}
+
+/**
+ * @brief set unicast pause frame detect.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_unicast_pause_frame_detect(confirm_state new_state)
+{
+ EMAC->fctrl_bit.dup = new_state;
+}
+
+/**
+ * @brief set pause low threshold.
+ * @param pasue_threshold: pause slot time.
+ * this parameter can be one of the following values:
+ * - EMAC_PAUSE_4_SLOT_TIME
+ * - EMAC_PAUSE_28_SLOT_TIME
+ * - EMAC_PAUSE_144_SLOT_TIME
+ * - EMAC_PAUSE_256_SLOT_TIME
+ * @retval none
+ */
+void emac_pause_low_threshold_set(emac_pause_slot_threshold_type pasue_threshold)
+{
+ EMAC->fctrl_bit.plt = pasue_threshold;
+}
+
+/**
+ * @brief set zero-quanta pause disable.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_zero_quanta_pause_disable(confirm_state new_state)
+{
+ EMAC->fctrl_bit.dzqp = new_state;
+}
+
+/**
+ * @brief set pause time.
+ * @param pause_time: time slots to pause transmit frame.
+ * @retval none
+ */
+void emac_pause_time_set(uint16_t pause_time)
+{
+ EMAC->fctrl_bit.pt = pause_time;
+}
+
+/**
+ * @brief identify coming vlan frame field with setting value.
+ * @param identifier: it will be compared with coming frame.
+ * @retval none
+ */
+void emac_vlan_tag_identifier_set(uint16_t identifier)
+{
+ EMAC->vlt_bit.vti = identifier;
+}
+
+/**
+ * @brief set 12-bit vlan identifier.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_vlan_tag_comparison_set(confirm_state new_state)
+{
+ EMAC->vlt_bit.etv = new_state;
+}
+
+/**
+ * @brief set wakeup frame.
+ * @param value: it will be written to eight non transparent registers.
+ * @retval none
+ */
+void emac_wakeup_frame_set(uint32_t value)
+{
+ EMAC->rwff = value;
+}
+
+/**
+ * @brief get wakeup frame.
+ * @param none
+ * @retval get value from eight non transparent registers.
+ */
+uint32_t emac_wakeup_frame_get(void)
+{
+ return (EMAC->rwff);
+}
+
+/**
+ * @brief all frame will be droppped except wakeup frame or magic packet.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_power_down_set(confirm_state new_state)
+{
+ EMAC->pmtctrlsts_bit.pd = new_state;
+}
+
+/**
+ * @brief magic packet enable
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_magic_packet_enable(confirm_state new_state)
+{
+ EMAC->pmtctrlsts_bit.emp = new_state;
+}
+
+/**
+ * @brief wakeup frame enable
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_wakeup_frame_enable(confirm_state new_state)
+{
+ EMAC->pmtctrlsts_bit.erwf = new_state;
+}
+
+/**
+ * @brief received magic packet
+ * @param none
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status emac_received_magic_packet_get(void)
+{
+ if(EMAC->pmtctrlsts_bit.rmp)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief received wakeup frame.
+ * @param none
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status emac_received_wakeup_frame_get(void)
+{
+ if(EMAC->pmtctrlsts_bit.rrwf)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief set unicast frame that passes DAF as wakeup frame.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_global_unicast_set(confirm_state new_state)
+{
+ EMAC->pmtctrlsts_bit.guc = new_state;
+}
+
+/**
+ * @brief reset wakeup frame filter resgister
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_wakeup_frame_filter_reset(confirm_state new_state)
+{
+ EMAC->pmtctrlsts_bit.rwffpr = new_state;
+}
+
+/**
+ * @brief read interrupt status
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - EMAC_PMT_FLAG
+ * - EMAC_MMC_FLAG
+ * - EMAC_MMCR_FLAG
+ * - EMAC_MMCT_FLAG
+ * - EMAC_TST_FLAG
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status emac_interrupt_status_read(uint32_t flag)
+{
+ if(EMAC->ists & flag)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief set interrupt mask
+ * @param mask_type: mask the interrupt signal
+ * this parameter can be one of the following values:
+ * - EMAC_INTERRUPT_PMT_MASK
+ * - EMAC_INTERRUPT_TST_MASK
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_interrupt_mask_set(emac_interrupt_mask_type mask_type, confirm_state new_state)
+{
+ switch(mask_type)
+ {
+ case EMAC_INTERRUPT_PMT_MASK:
+ {
+ EMAC->imr_bit.pim = new_state;
+ break;
+ }
+ case EMAC_INTERRUPT_TST_MASK:
+ {
+ EMAC->imr_bit.tim = new_state;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief set local mac address
+ * @param address: local address for mac0
+ * @retval none
+ */
+void emac_local_address_set(uint8_t *address)
+{
+ EMAC->a0h_bit.ma0h = (uint32_t)(address[5] << 8 | address[4]);
+ EMAC->a0l_bit.ma0l = (uint32_t)(address[3] << 24 | address[2] << 16 | address[1] << 8 | address[0]);
+}
+
+/**
+ * @brief set mac filter address
+ * @param mac: select which mac you want to set
+ * this parameter can be one of the following values:
+ * - EMAC_ADDRESS_FILTER_1
+ * - EMAC_ADDRESS_FILTER_2
+ * - EMAC_ADDRESS_FILTER_3
+ * @retval none
+ */
+void emac_address_filter_set(emac_address_type mac, emac_address_filter_type filter, emac_address_mask_type mask_bit, confirm_state new_state)
+{
+ switch(mac)
+ {
+ case EMAC_ADDRESS_FILTER_1:
+ {
+ EMAC->a1h_bit.sa = filter;
+ EMAC->a1h_bit.mbc = mask_bit;
+ EMAC->a1h_bit.ae = new_state;
+ break;
+ }
+ case EMAC_ADDRESS_FILTER_2:
+ {
+ EMAC->a2h_bit.sa = filter;
+ EMAC->a2h_bit.mbc = mask_bit;
+ EMAC->a2h_bit.ae = new_state;
+ break;
+ }
+ case EMAC_ADDRESS_FILTER_3:
+ {
+ EMAC->a3h_bit.sa = filter;
+ EMAC->a3h_bit.mbc = mask_bit;
+ EMAC->a3h_bit.ae = new_state;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief set transmit/receive descriptor list address
+ * @param transfer_type: it will be transmit or receive
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_TRANSMIT
+ * - EMAC_DMA_RECEIVE
+ * @param dma_desc_tab: pointer on the first tx desc list
+ * @param buff: pointer on the first tx/rx buffer list
+ * @param buffer_count: number of the used Tx desc in the list
+ * @retval none
+ */
+void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, uint8_t *buff, uint32_t buffer_count)
+{
+ uint32_t i = 0;
+ emac_dma_desc_type *dma_descriptor;
+
+ switch(transfer_type)
+ {
+ case EMAC_DMA_TRANSMIT:
+ {
+ dma_tx_desc_to_set = dma_desc_tab;
+ for(i = 0; i < buffer_count; i++)
+ {
+ dma_descriptor = dma_desc_tab + i;
+
+ dma_descriptor->status = EMAC_DMATXDESC_TCH;
+
+ dma_descriptor->buf1addr = (uint32_t)(&buff[i * EMAC_MAX_PACKET_LENGTH]);
+
+ if(i < (buffer_count - 1))
+ {
+ dma_descriptor->buf2nextdescaddr = (uint32_t)(dma_desc_tab + i + 1);
+ }
+ else
+ {
+ dma_descriptor->buf2nextdescaddr = (uint32_t) dma_desc_tab;
+ }
+ }
+ EMAC_DMA->tdladdr_bit.stl = (uint32_t) dma_desc_tab;
+ break;
+ }
+ case EMAC_DMA_RECEIVE:
+ {
+ dma_rx_desc_to_get = dma_desc_tab;
+ for(i = 0; i < buffer_count; i++)
+ {
+ dma_descriptor = dma_desc_tab + i;
+
+ dma_descriptor->status = EMAC_DMARXDESC_OWN;
+
+ dma_descriptor->controlsize = EMAC_DMARXDESC_RCH | (uint32_t)EMAC_MAX_PACKET_LENGTH;
+
+ dma_descriptor->buf1addr = (uint32_t)(&buff[i * EMAC_MAX_PACKET_LENGTH]);
+
+ if(i < (buffer_count - 1))
+ {
+ dma_descriptor->buf2nextdescaddr = (uint32_t)(dma_desc_tab + i + 1);
+ }
+ else
+ {
+ dma_descriptor->buf2nextdescaddr = (uint32_t) dma_desc_tab;
+ }
+ }
+ EMAC_DMA->rdladdr_bit.srl = (uint32_t) dma_desc_tab;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief enable or disable the specified dma rx descriptor receive interrupt
+ * @param dma_rx_desc: pointer on a rx desc.
+ * @param new_state: new state of the specified dma rx descriptor interrupt.
+ * this parameter can be one of the following values:
+ * - TRUE
+ * - FALSE.
+ * @retval none
+ */
+void emac_dma_rx_desc_interrupt_config(emac_dma_desc_type *dma_rx_desc, confirm_state new_state)
+{
+ if (new_state != FALSE)
+ {
+ /* enable the dma rx desc receive interrupt */
+ dma_rx_desc->controlsize &= (~(uint32_t)EMAC_DMARXDESC_DIC);
+ }
+ else
+ {
+ /* disable the dma rx desc receive interrupt */
+ dma_rx_desc->controlsize |= EMAC_DMARXDESC_DIC;
+ }
+}
+
+/**
+ * @brief get transmit/receive descriptor list address
+ * @param transfer_type: it will be transmit or receive
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_TRANSMIT
+ * - EMAC_DMA_RECEIVE
+ * @retval transmit/receive descriptor list address
+ */
+uint32_t emac_dma_descriptor_list_address_get(emac_dma_tx_rx_type transfer_type)
+{
+ switch(transfer_type)
+ {
+ case EMAC_DMA_TRANSMIT:
+ {
+ return (EMAC_DMA->tdladdr_bit.stl);
+ }
+ case EMAC_DMA_RECEIVE:
+ {
+ return (EMAC_DMA->rdladdr_bit.srl);
+ }
+ }
+ return 0;
+}
+
+/**
+ * @brief get the size of received the received packet.
+ * @param none
+ * @retval received packet size
+ */
+uint32_t emac_received_packet_size_get(void)
+{
+ uint32_t frame_length = 0;
+ if(((dma_rx_desc_to_get->status & EMAC_DMARXDESC_OWN) == (uint32_t)RESET) &&
+ ((dma_rx_desc_to_get->status & EMAC_DMATXDESC_ES) == (uint32_t)RESET) &&
+ ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_LS) != (uint32_t)RESET) &&
+ ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_FS) != (uint32_t)RESET))
+ {
+ frame_length = emac_dmarxdesc_frame_length_get(dma_rx_desc_to_get);
+ }
+
+ return frame_length;
+}
+
+/**
+ * @brief get the specified dma rx descsriptor frame length.
+ * @param dma_rx_desc: pointer on a dma rx descriptor
+ * @retval the rx descriptor received frame length.
+ */
+uint32_t emac_dmarxdesc_frame_length_get(emac_dma_desc_type *dma_rx_desc)
+{
+ return ((dma_rx_desc->status & EMAC_DMARXDESC_FL) >> EMAC_DMARXDESC_FRAME_LENGTHSHIFT);
+}
+
+/**
+ * @brief init emac dma parameters
+ * @param emac_dma_config_type
+ * @retval none
+ */
+void emac_dma_para_init(emac_dma_config_type *control_para)
+{
+ control_para->aab_enable = FALSE;
+ control_para->da_enable = FALSE;
+ control_para->desc_skip_length = 0;
+ control_para->dt_disable = FALSE;
+ control_para->fb_enable = FALSE;
+ control_para->fef_enable = FALSE;
+ control_para->flush_rx_disable = FALSE;
+ control_para->fugf_enable = FALSE;
+ control_para->osf_enable = FALSE;
+ control_para->priority_ratio = EMAC_DMA_1_RX_1_TX;
+ control_para->rsf_enable = FALSE;
+ control_para->rx_dma_pal = EMAC_DMA_PBL_1;
+ control_para->rx_threshold = EMAC_DMA_RX_THRESHOLD_64_BYTES;
+ control_para->tsf_enable = FALSE;
+ control_para->tx_dma_pal = EMAC_DMA_PBL_1;
+ control_para->tx_threshold = EMAC_DMA_TX_THRESHOLD_64_BYTES;
+ control_para->usp_enable = FALSE;
+}
+
+/**
+ * @brief configure emac dma
+ * @param emac_dma_config_type
+ * @retval none
+ */
+void emac_dma_config(emac_dma_config_type *control_para)
+{
+ EMAC_DMA->bm_bit.aab = control_para->aab_enable;
+ EMAC_DMA->bm_bit.dsl = control_para->desc_skip_length;
+ EMAC_DMA->bm_bit.rdp = control_para->rx_dma_pal;
+ EMAC_DMA->bm_bit.pbl = control_para->tx_dma_pal;
+ EMAC_DMA->bm_bit.fb = control_para->fb_enable;
+ EMAC_DMA->bm_bit.usp = control_para->usp_enable;
+ EMAC_DMA->bm_bit.da = control_para->da_enable;
+ EMAC_DMA->bm_bit.pr = control_para->priority_ratio;
+
+ EMAC_DMA->opm_bit.dt = control_para->dt_disable;
+ EMAC_DMA->opm_bit.rsf = control_para->rsf_enable;
+ EMAC_DMA->opm_bit.dfrf = control_para->flush_rx_disable;
+ EMAC_DMA->opm_bit.tsf = control_para->tsf_enable;
+ EMAC_DMA->opm_bit.ttc = control_para->tx_threshold;
+ EMAC_DMA->opm_bit.fef = control_para->fef_enable;
+ EMAC_DMA->opm_bit.fugf = control_para->fugf_enable;
+ EMAC_DMA->opm_bit.rtc = control_para->rx_threshold;
+ EMAC_DMA->opm_bit.osf = control_para->osf_enable;
+}
+
+/**
+ * @brief set rx tx priority
+ * @param ratio: rx tx priority ratio
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_1_RX_1_TX
+ * - EMAC_DMA_2_RX_1_TX
+ * - EMAC_DMA_3_RX_1_TX
+ * - EMAC_DMA_4_RX_1_TX
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void emac_dma_arbitation_set(emac_dma_rx_tx_ratio_type ratio, confirm_state new_state)
+{
+ EMAC_DMA->bm_bit.da = new_state;
+
+ if(new_state)
+ {
+ EMAC_DMA->bm_bit.pr = ratio;
+ }
+}
+
+/**
+ * @brief set descriptor skip mength
+ * @param length: descriptor skip length
+ * @retval none
+ */
+void emac_dma_descriptor_skip_length_set(uint8_t length)
+{
+ EMAC_DMA->bm_bit.dsl = length;
+}
+
+/**
+ * @brief set programmable burst length
+ * @param tx_length: tx programmable burst length
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_PBL_1
+ * - EMAC_DMA_PBL_2
+ * - EMAC_DMA_PBL_4
+ * - EMAC_DMA_PBL_8
+ * - EMAC_DMA_PBL_16
+ * - EMAC_DMA_PBL_32
+ * @param rx_length: rx programmable burst length
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_PBL_1
+ * - EMAC_DMA_PBL_2
+ * - EMAC_DMA_PBL_4
+ * - EMAC_DMA_PBL_8
+ * - EMAC_DMA_PBL_16
+ * - EMAC_DMA_PBL_32
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void emac_dma_separate_pbl_set(emac_dma_pbl_type tx_length, emac_dma_pbl_type rx_length, confirm_state new_state)
+{
+ EMAC_DMA->bm_bit.usp = new_state;
+ EMAC_DMA->bm_bit.pbl = tx_length;
+
+ if(new_state)
+ {
+ EMAC_DMA->bm_bit.pbl = rx_length;
+ }
+}
+
+/**
+ * @brief set 8 times programmable burst length
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void emac_dma_eight_pbl_mode_set(confirm_state new_state)
+{
+ EMAC_DMA->bm_bit.pblx8 = new_state;
+}
+
+/**
+ * @brief set address-aligned beats
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void emac_dma_address_aligned_beats_set(confirm_state new_state)
+{
+ EMAC_DMA->bm_bit.aab = new_state;
+}
+
+/**
+ * @brief set transmit/receive poll demand
+ * @param transfer_type: it will be transmit or receive
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_TRANSMIT
+ * - EMAC_DMA_RECEIVE
+ * @param value: it can be any number
+ * @retval none
+ */
+void emac_dma_poll_demand_set(emac_dma_tx_rx_type transfer_type, uint32_t value)
+{
+ switch(transfer_type)
+ {
+ case EMAC_DMA_TRANSMIT:
+ {
+ EMAC_DMA->tpd_bit.tpd = value;
+ break;
+ }
+ case EMAC_DMA_RECEIVE:
+ {
+ EMAC_DMA->rpd_bit.rpd = value;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief get transmit poll demand
+ * @param transfer_type: it will be transmit or receive
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_TRANSMIT
+ * - EMAC_DMA_RECEIVE
+ * @retval current transmit descriptor
+ */
+uint32_t emac_dma_poll_demand_get(emac_dma_tx_rx_type transfer_type)
+{
+ switch(transfer_type)
+ {
+ case EMAC_DMA_TRANSMIT:
+ {
+ return (EMAC_DMA->tpd_bit.tpd);
+ }
+ case EMAC_DMA_RECEIVE:
+ {
+ return (EMAC_DMA->rpd_bit.rpd);
+ }
+ }
+ return 0;
+}
+
+/**
+ * @brief get emac dma status
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - DMA_TX_DONE
+ * - DMA_TX_STOP
+ * - DMA_TX_UNAVAILABLE
+ * - DMA_TX_JABBER_TIMEOUT
+ * - DMA_RX_OVERFLOW
+ * - DMA_TX_UNDERFLOW
+ * - DMA_RX_DONE
+ * - DMA_RX_UNAVAILABLE
+ * - DMA_RX_STOP
+ * - DMA_RX_WDG_TIMEOUT
+ * - DMA_TX_EARLY
+ * - DMA_FATAL_BUS_ERROR
+ * - DMA_RX_EARLY
+ * - DMA_MMC_STATUS
+ * - DMA_PMT_STATUS
+ * - DMA_TST_STATUS
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status emac_dma_status_get(uint32_t flag)
+{
+ if(EMAC_DMA->sts & flag)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief get receive dma process status
+ * @param none
+ * @retval every situation it describe in RM
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_RX_RESET_STOP_COMMAND
+ * - EMAC_DMA_RX_FETCH_DESCRIPTOR
+ * - EMAC_DMA_RX_WAITING_PACKET
+ * - EMAC_DMA_RX_DESCRIPTOR_UNAVAILABLE
+ * - EMAC_DMA_RX_CLOSE_DESCRIPTOR
+ * - EMAC_DMA_RX_FIFO_TO_HOST
+ */
+emac_dma_receive_process_status_type emac_dma_receive_status_get(void)
+{
+ switch(EMAC_DMA->sts_bit.rs)
+ {
+ case EMAC_DMA_RX_RESET_STOP_COMMAND:
+ {
+ return EMAC_DMA_RX_RESET_STOP_COMMAND;
+ }
+
+ case EMAC_DMA_RX_FETCH_DESCRIPTOR:
+ {
+ return EMAC_DMA_RX_FETCH_DESCRIPTOR;
+ }
+
+ case EMAC_DMA_RX_WAITING_PACKET:
+ {
+ return EMAC_DMA_RX_WAITING_PACKET;
+ }
+
+ case EMAC_DMA_RX_DESCRIPTOR_UNAVAILABLE:
+ {
+ return EMAC_DMA_RX_DESCRIPTOR_UNAVAILABLE;
+ }
+
+ case EMAC_DMA_RX_CLOSE_DESCRIPTOR:
+ {
+ return EMAC_DMA_RX_CLOSE_DESCRIPTOR;
+ }
+
+ case EMAC_DMA_RX_FIFO_TO_HOST:
+ {
+ return EMAC_DMA_RX_FIFO_TO_HOST;
+ }
+ }
+
+ return EMAC_DMA_RX_RESET_STOP_COMMAND;
+}
+
+/**
+ * @brief get transmit dma process status
+ * @param none
+ * @retval every situation it describe in RM
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_TX_RESET_STOP_COMMAND
+ * - EMAC_DMA_TX_FETCH_DESCRIPTOR
+ * - EMAC_DMA_TX_WAITING_FOR_STATUS
+ * - EMAC_DMA_TX_HOST_TO_FIFO
+ * - EMAC_DMA_TX_DESCRIPTOR_UNAVAILABLE
+ * - EMAC_DMA_TX_CLOSE_DESCRIPTOR
+ */
+emac_dma_transmit_process_status_type emac_dma_transmit_status_get(void)
+{
+ switch(EMAC_DMA->sts_bit.ts)
+ {
+ case EMAC_DMA_TX_RESET_STOP_COMMAND:
+ {
+ return EMAC_DMA_TX_RESET_STOP_COMMAND;
+ }
+
+ case EMAC_DMA_TX_FETCH_DESCRIPTOR:
+ {
+ return EMAC_DMA_TX_FETCH_DESCRIPTOR;
+ }
+
+ case EMAC_DMA_TX_WAITING_FOR_STATUS:
+ {
+ return EMAC_DMA_TX_WAITING_FOR_STATUS;
+ }
+
+ case EMAC_DMA_TX_HOST_TO_FIFO:
+ {
+ return EMAC_DMA_TX_HOST_TO_FIFO;
+ }
+
+ case EMAC_DMA_TX_DESCRIPTOR_UNAVAILABLE:
+ {
+ return EMAC_DMA_TX_DESCRIPTOR_UNAVAILABLE;
+ }
+
+ case EMAC_DMA_TX_CLOSE_DESCRIPTOR:
+ {
+ return EMAC_DMA_TX_CLOSE_DESCRIPTOR;
+ }
+ }
+
+ return EMAC_DMA_TX_RESET_STOP_COMMAND;
+}
+
+/**
+ * @brief set dma operations
+ * @param ops: operations of dma
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_OPS_START_STOP_RECEIVE
+ * - EMAC_DMA_OPS_SECOND_FRAME
+ * - EMAC_DMA_OPS_FORWARD_UNDERSIZED
+ * - EMAC_DMA_OPS_FORWARD_ERROR
+ * - EMAC_DMA_OPS_START_STOP_TRANSMIT
+ * - EMAC_DMA_OPS_FLUSH_TRANSMIT_FIFO
+ * - EMAC_DMA_OPS_TRANSMIT_STORE_FORWARD
+ * - EMAC_DMA_OPS_RECEIVE_FLUSH_DISABLE
+ * - EMAC_DMA_OPS_RECEIVE_STORE_FORWARD
+ * - EMAC_DMA_OPS_DROP_ERROR_DISABLE
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void emac_dma_operations_set(emac_dma_operations_type ops, confirm_state new_state)
+{
+ __IO uint32_t temp = 0;
+ switch(ops)
+ {
+ case EMAC_DMA_OPS_START_STOP_RECEIVE:
+ {
+ EMAC_DMA->opm_bit.ssr = new_state;
+ break;
+ }
+
+ case EMAC_DMA_OPS_SECOND_FRAME:
+ {
+ EMAC_DMA->opm_bit.osf = new_state;
+ break;
+ }
+
+ case EMAC_DMA_OPS_FORWARD_UNDERSIZED:
+ {
+ EMAC_DMA->opm_bit.fugf = new_state;
+ break;
+ }
+
+ case EMAC_DMA_OPS_FORWARD_ERROR:
+ {
+ EMAC_DMA->opm_bit.fef = new_state;
+ break;
+ }
+
+ case EMAC_DMA_OPS_START_STOP_TRANSMIT:
+ {
+ EMAC_DMA->opm_bit.sstc = new_state;
+ break;
+ }
+
+ case EMAC_DMA_OPS_FLUSH_TRANSMIT_FIFO:
+ {
+ EMAC_DMA->opm_bit.ftf = new_state;
+ temp = EMAC_DMA->opm;
+ emac_delay(1);
+ EMAC_DMA->opm = temp;
+ break;
+ }
+
+ case EMAC_DMA_OPS_TRANSMIT_STORE_FORWARD:
+ {
+ EMAC_DMA->opm_bit.tsf = new_state;
+ break;
+ }
+
+ case EMAC_DMA_OPS_RECEIVE_FLUSH_DISABLE:
+ {
+ EMAC_DMA->opm_bit.dfrf = new_state;
+ break;
+ }
+
+ case EMAC_DMA_OPS_RECEIVE_STORE_FORWARD:
+ {
+ EMAC_DMA->opm_bit.rsf = new_state;
+ break;
+ }
+
+ case EMAC_DMA_OPS_DROP_ERROR_DISABLE:
+ {
+ EMAC_DMA->opm_bit.dt = new_state;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief set receive dma threshold
+ * @param value: receive threshold
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_RX_THRESHOLD_64_BYTES
+ * - EMAC_DMA_RX_THRESHOLD_32_BYTES
+ * - EMAC_DMA_RX_THRESHOLD_96_BYTES
+ * - EMAC_DMA_RX_THRESHOLD_128_BYTES
+ * @retval none
+ */
+void emac_dma_receive_threshold_set(emac_dma_receive_threshold_type value)
+{
+ EMAC_DMA->opm_bit.rtc = value;
+}
+
+/**
+ * @brief set transmit dma threshold
+ * @param value: transmit threshold
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_TX_THRESHOLD_64_BYTES
+ * - EMAC_DMA_TX_THRESHOLD_128_BYTES
+ * - EMAC_DMA_TX_THRESHOLD_192_BYTES
+ * - EMAC_DMA_TX_THRESHOLD_256_BYTES
+ * - EMAC_DMA_TX_THRESHOLD_40_BYTES
+ * - EMAC_DMA_TX_THRESHOLD_32_BYTES
+ * - EMAC_DMA_TX_THRESHOLD_24_BYTES
+ * - EMAC_DMA_TX_THRESHOLD_16_BYTES
+ * @retval none
+ */
+void emac_dma_transmit_threshold_set(emac_dma_transmit_threshold_type value)
+{
+ EMAC_DMA->opm_bit.ttc = value;
+}
+
+/**
+ * @brief enable dma interrupt
+ * @param it: interrupt type
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_INTERRUPT_TX
+ * - EMAC_DMA_INTERRUPT_TX_STOP
+ * - EMAC_DMA_INTERRUPT_TX_UNAVAILABLE
+ * - EMAC_DMA_INTERRUPT_TX_JABBER
+ * - EMAC_DMA_INTERRUPT_RX_OVERFLOW
+ * - EMAC_DMA_INTERRUPT_TX_UNDERFLOW
+ * - EMAC_DMA_INTERRUPT_RX
+ * - EMAC_DMA_INTERRUPT_RX_UNAVAILABLE
+ * - EMAC_DMA_INTERRUPT_RX_STOP
+ * - EMAC_DMA_INTERRUPT_RX_TIMEOUT
+ * - EMAC_DMA_INTERRUPT_TX_EARLY
+ * - EMAC_DMA_INTERRUPT_FATAL_BUS_ERROR
+ * - EMAC_DMA_INTERRUPT_RX_EARLY
+ * - EMAC_DMA_INTERRUPT_ABNORMAL_SUMMARY
+ * - EMAC_DMA_INTERRUPT_NORMAL_SUMMARY
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void emac_dma_interrupt_enable(emac_dma_interrupt_type it, confirm_state new_state)
+{
+ switch(it)
+ {
+ case EMAC_DMA_INTERRUPT_TX:
+ {
+ EMAC_DMA->ie_bit.tie = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_TX_STOP:
+ {
+ EMAC_DMA->ie_bit.tse = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_TX_UNAVAILABLE:
+ {
+ EMAC_DMA->ie_bit.tue = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_TX_JABBER:
+ {
+ EMAC_DMA->ie_bit.tje = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_RX_OVERFLOW:
+ {
+ EMAC_DMA->ie_bit.ove = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_TX_UNDERFLOW:
+ {
+ EMAC_DMA->ie_bit.une = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_RX:
+ {
+ EMAC_DMA->ie_bit.rie = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_RX_UNAVAILABLE:
+ {
+ EMAC_DMA->ie_bit.rbue = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_RX_STOP:
+ {
+ EMAC_DMA->ie_bit.rse = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_RX_TIMEOUT:
+ {
+ EMAC_DMA->ie_bit.rwte = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_TX_EARLY:
+ {
+ EMAC_DMA->ie_bit.eie = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_FATAL_BUS_ERROR:
+ {
+ EMAC_DMA->ie_bit.fbee = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_RX_EARLY:
+ {
+ EMAC_DMA->ie_bit.ere = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_ABNORMAL_SUMMARY:
+ {
+ EMAC_DMA->ie_bit.aie = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_NORMAL_SUMMARY:
+ {
+ EMAC_DMA->ie_bit.nie = new_state;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief get missed frames by the controller
+ * @param none
+ * @retval missed frames by the controller
+ */
+uint16_t emac_dma_controller_missing_frame_get(void)
+{
+ uint16_t number = EMAC_DMA->mfbocnt_bit.mfc;
+ return number;
+}
+
+/**
+ * @brief get overflow bit for missed frame counter
+ * @param none
+ * @retval overflow bit for missed frame counter
+ */
+uint8_t emac_dma_missing_overflow_bit_get(void)
+{
+ uint8_t number = EMAC_DMA->mfbocnt_bit.obmfc;
+ return number;
+}
+
+/**
+ * @brief get missed frames by the application
+ * @param none
+ * @retval missed frames by the application
+ */
+uint16_t emac_dma_application_missing_frame_get(void)
+{
+ uint16_t number = EMAC_DMA->mfbocnt_bit.ofc;
+ return number;
+}
+
+/**
+ * @brief get overflow bit for FIFO overflow counter
+ * @param none
+ * @retval overflow bit for FIFO overflow counter
+ */
+uint8_t emac_dma_fifo_overflow_bit_get(void)
+{
+ uint8_t number = EMAC_DMA->mfbocnt_bit.obfoc;
+ return number;
+}
+
+/**
+ * @brief get overflow bit for FIFO overflow counter
+ * @param transfer type: receive/transmit type
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_TX_DESCRIPTOR
+ * - EMAC_DMA_RX_DESCRIPTOR
+ * - EMAC_DMA_TX_BUFFER
+ * - EMAC_DMA_RX_BUFFER
+ * @retval memory address
+ */
+uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_type)
+{
+ uint32_t address = 0;
+
+ switch(transfer_type)
+ {
+ case EMAC_DMA_TX_DESCRIPTOR:
+ {
+ address = EMAC_DMA->ctd_bit.htdap;
+ break;
+ }
+ case EMAC_DMA_RX_DESCRIPTOR:
+ {
+ address = EMAC_DMA->crd_bit.hrdap;
+ break;
+ }
+ case EMAC_DMA_TX_BUFFER:
+ {
+ address = EMAC_DMA->ctbaddr_bit.htbap;
+ break;
+ }
+ case EMAC_DMA_RX_BUFFER:
+ {
+ address = EMAC_DMA->crbaddr_bit.hrbap;
+ break;
+ }
+ }
+ return address;
+}
+
+/**
+ * @brief reset all counter
+ * @param none
+ * @retval none
+ */
+void emac_mmc_counter_reset(void)
+{
+ EMAC_MMC->ctrl_bit.rc = TRUE;
+}
+
+/**
+ * @brief counter stop counting from zero when it reaches maximum
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_mmc_rollover_stop(confirm_state new_state)
+{
+ EMAC_MMC->ctrl_bit.scr = new_state;
+}
+
+/**
+ * @brief enable reset on read
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_mmc_reset_on_read_enable(confirm_state new_state)
+{
+ EMAC_MMC->ctrl_bit.rr = new_state;
+}
+
+/**
+ * @brief freeze mmc counter
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_mmc_counter_freeze(confirm_state new_state)
+{
+ EMAC_MMC->ctrl_bit.fmc = new_state;
+}
+
+/**
+ * @brief interupt status of received frames
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - MMC_RX_CRC_ERROR
+ * - MMC_RX_ALIGN_ERROR
+ * - MMC_RX_GOOD_UNICAST
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status emac_mmc_received_status_get(uint32_t flag)
+{
+ if(EMAC_MMC->ri & flag)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief interupt status of transmit frames
+ * @param transmit_type: transmit type.
+ * this parameter can be one of the following values:
+ * - MMC_TX_SINGLE_COL
+ * - MMC_TX_MULTIPLE_COL
+ * - MMC_TX_GOOD_FRAMES
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status emac_mmc_transmit_status_get(uint32_t flag)
+{
+ if(EMAC_MMC->ti & flag)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief mask received mmc interrupt
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - MMC_RX_CRC_ERROR
+ * - MMC_RX_ALIGN_ERROR
+ * - MMC_RX_GOOD_UNICAST
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_mmc_received_interrupt_mask_set(uint32_t flag, confirm_state new_state)
+{
+ switch(flag)
+ {
+ case MMC_RX_CRC_ERROR:
+ {
+ EMAC_MMC->rim_bit.rcefcim = new_state;
+ break;
+ }
+ case MMC_RX_ALIGN_ERROR:
+ {
+ EMAC_MMC->rim_bit.raefacim = new_state;
+ break;
+ }
+ case MMC_RX_GOOD_UNICAST:
+ {
+ EMAC_MMC->rim_bit.rugfcim = new_state;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief mask transmit mmc interrupt
+ * @param transmit_type: transmit type.
+ * this parameter can be one of the following values:
+ * - MMC_TX_SINGLE_COL
+ * - MMC_TX_MULTIPLE_COL
+ * - MMC_TX_GOOD_FRAMES
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_mmc_transmit_interrupt_mask_set(uint32_t flag, confirm_state new_state)
+{
+ switch(flag)
+ {
+ case MMC_TX_SINGLE_COL:
+ {
+ EMAC_MMC->tim_bit.tscgfcim = new_state;
+ break;
+ }
+ case MMC_TX_MULTIPLE_COL:
+ {
+ EMAC_MMC->tim_bit.tmcgfcim = new_state;
+ break;
+ }
+ case MMC_TX_GOOD_FRAMES:
+ {
+ EMAC_MMC->tim_bit.tgfcim = new_state;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief get good frame numbers as single collision occurs.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - MMC_TX_SINGLE_COL
+ * - MMC_TX_MULTIPLE_COL
+ * - MMC_TX_GOOD_FRAMES
+ * @retval good frames
+ */
+uint32_t emac_mmc_transmit_good_frames_get(uint32_t flag)
+{
+ uint32_t good_frames = MMC_TX_GOOD_FRAMES;
+
+ switch(flag)
+ {
+ case MMC_TX_SINGLE_COL:
+ {
+ good_frames = EMAC_MMC->tfscc_bit.tgfscc;
+ break;
+ }
+ case MMC_TX_MULTIPLE_COL:
+ {
+ good_frames = EMAC_MMC->tfmscc_bit.tgfmscc;
+ break;
+ }
+ case MMC_TX_GOOD_FRAMES:
+ {
+ good_frames = EMAC_MMC->tfcnt_bit.tgfc;
+ break;
+ }
+ }
+ return good_frames;
+}
+
+/**
+ * @brief get good frame numbers as single collision occurs.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - MMC_RX_CRC_ERROR
+ * - MMC_RX_ALIGN_ERROR
+ * - MMC_RX_GOOD_UNICAST
+ * @retval good frames
+ */
+uint32_t emac_mmc_received_error_frames_get(uint32_t flag)
+{
+ uint32_t error_frames = MMC_RX_GOOD_UNICAST;
+
+ switch(flag)
+ {
+ case MMC_RX_CRC_ERROR:
+ {
+ error_frames = EMAC_MMC->rfcecnt_bit.rfcec;
+ break;
+ }
+ case MMC_RX_ALIGN_ERROR:
+ {
+ error_frames = EMAC_MMC->rfaecnt_bit.rfaec;
+ break;
+ }
+ case MMC_RX_GOOD_UNICAST:
+ {
+ error_frames = EMAC_MMC->rgufcnt_bit.rgufc;
+ break;
+ }
+ }
+ return error_frames;
+}
+
+/**
+ * @brief enable timestamp.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_timestamp_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.te = new_state;
+}
+
+/**
+ * @brief enable timestamp fine update.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_timestamp_fine_update_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.tfcu = new_state;
+}
+
+/**
+ * @brief initialize timestamp time system.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_timestamp_system_time_init(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.ti = new_state;
+}
+
+/**
+ * @brief update timestamp time system.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_timestamp_system_time_update(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.tu = new_state;
+}
+
+/**
+ * @brief enable timestamp interrupt trigger.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_interrupt_trigger_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.tite = new_state;
+}
+
+/**
+ * @brief update timestamp addend register.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_addend_register_update(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.aru = new_state;
+}
+
+/**
+ * @brief enable timestamp snapshot for all received frames.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_snapshot_received_frames_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.etaf = new_state;
+}
+
+/**
+ * @brief enable digital rollover.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_subsecond_rollover_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.tdbrc = new_state;
+}
+
+/**
+ * @brief enable packet snooping for version 2.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_psv2_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.eppv2f = new_state;
+}
+
+/**
+ * @brief enable snapshot over emac.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_snapshot_emac_frames_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.eppef = new_state;
+}
+
+/**
+ * @brief enable snapshot for ipv6 frames.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_snapshot_ipv6_frames_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.eppfsip6u = new_state;
+}
+
+/**
+ * @brief enable snapshot for ipv4 frames.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_snapshot_ipv4_frames_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.eppfsip4u = new_state;
+}
+
+/**
+ * @brief enable snapshot for event message.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_snapshot_event_message_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.etsfem = new_state;
+}
+
+/**
+ * @brief enable snapshot for message relevant to master
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_snapshot_master_event_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.esfmrtm = new_state;
+}
+
+/**
+ * @brief set clock node type
+ * @param node: select ptp packets for taking snapshot
+ * this parameter can be one of the following values:
+ * - EMAC_PTP_NORMAL_CLOCK
+ * - EMAC_PTP_BOUNDARY_CLOCK
+ * - EMAC_PTP_END_TO_END_CLOCK
+ * - EMAC_PTP_PEER_TO_PEER_CLOCK
+ * @retval none
+ */
+void emac_ptp_clock_node_set(emac_ptp_clock_node_type node)
+{
+ EMAC_PTP->tsctrl_bit.sppfts = node;
+}
+
+/**
+ * @brief enable ptp frame filtering mac address
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_mac_address_filter_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.emafpff = new_state;
+}
+
+/**
+ * @brief set subsecond increment value
+ * @param value: add to subsecond value for every update
+ * @retval none
+ */
+void emac_ptp_subsecond_increment_set(uint8_t value)
+{
+ EMAC_PTP->ssinc_bit.ssiv = value;
+}
+
+/**
+ * @brief get system time second
+ * @param none
+ * @retval system time second
+ */
+uint32_t emac_ptp_system_second_get(void)
+{
+ uint32_t second = EMAC_PTP->tsh_bit.ts;
+ return second;
+}
+
+/**
+ * @brief get system time subsecond
+ * @param none
+ * @retval system time subsecond
+ */
+uint32_t emac_ptp_system_subsecond_get(void)
+{
+ uint32_t subsecond = EMAC_PTP->tsl_bit.tss;
+ return subsecond;
+}
+
+/**
+ * @brief get system time sign
+ * @param none
+ * @retval TRUE or FALSE
+ */
+confirm_state emac_ptp_system_time_sign_get(void)
+{
+ if(EMAC_PTP->tsl_bit.ast)
+ {
+ return TRUE;
+ }
+ else
+ {
+ return FALSE;
+ }
+}
+
+/**
+ * @brief set system time second
+ * @param second: system time second
+ * @retval none
+ */
+void emac_ptp_system_second_set(uint32_t second)
+{
+ EMAC_PTP->tshud_bit.ts = second;
+}
+
+/**
+ * @brief set system time subsecond
+ * @param subsecond: system time subsecond
+ * @retval none
+ */
+void emac_ptp_system_subsecond_set(uint32_t subsecond)
+{
+ EMAC_PTP->tslud_bit.tss = subsecond;
+}
+
+/**
+ * @brief set system time sign
+ * @param sign: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_system_time_sign_set(confirm_state sign)
+{
+ if(sign)
+ {
+ EMAC_PTP->tslud_bit.ast = 1;
+ }
+ else
+ {
+ EMAC_PTP->tslud_bit.ast = 0;
+ }
+}
+
+/**
+ * @brief set time stamp addend
+ * @param value: to achieve time synchronization
+ * @retval none
+ */
+void emac_ptp_timestamp_addend_set(uint32_t value)
+{
+ EMAC_PTP->tsad_bit.tar = value;
+}
+
+/**
+ * @brief set target time stamp high
+ * @param value: to set target time second
+ * @retval none
+ */
+void emac_ptp_target_second_set(uint32_t value)
+{
+ EMAC_PTP->tth_bit.ttsr = value;
+}
+
+/**
+ * @brief set target time stamp low
+ * @param value: to set target time nanosecond
+ * @retval none
+ */
+void emac_ptp_target_nanosecond_set(uint32_t value)
+{
+ EMAC_PTP->ttl_bit.ttlr = value;
+}
+
+/**
+ * @brief set target time stamp low
+ * @param status: type of status
+ * this parameter can be one of the following values:
+ * - EMAC_PTP_SECOND_OVERFLOW
+ * - EMAC_PTP_TARGET_TIME_REACH
+ * @retval TRUE or FALSE
+ */
+confirm_state emac_ptp_timestamp_status_get(emac_ptp_timestamp_status_type status)
+{
+ switch(status)
+ {
+ case EMAC_PTP_SECOND_OVERFLOW:
+ {
+ if(EMAC_PTP->tssr_bit.tso)
+ {
+ return TRUE;
+ }
+ else
+ {
+ return FALSE;
+ }
+ }
+ case EMAC_PTP_TARGET_TIME_REACH:
+ {
+ if(EMAC_PTP->tssr_bit.tttr)
+ {
+ return TRUE;
+ }
+ else
+ {
+ return FALSE;
+ }
+ }
+ }
+ return FALSE;
+}
+
+/**
+ * @brief set pps frequency
+ * @param freq: pps frequency
+ * this parameter can be one of the following values:
+ * - EMAC_PTP_PPS_1HZ
+ * - EMAC_PTP_PPS_2HZ
+ * - EMAC_PTP_PPS_4HZ
+ * - EMAC_PTP_PPS_8HZ
+ * - EMAC_PTP_PPS_16HZ
+ * - EMAC_PTP_PPS_32HZ
+ * - EMAC_PTP_PPS_64HZ
+ * - EMAC_PTP_PPS_128HZ
+ * - EMAC_PTP_PPS_256HZ
+ * - EMAC_PTP_PPS_512HZ
+ * - EMAC_PTP_PPS_1024HZ
+ * - EMAC_PTP_PPS_2048HZ
+ * - EMAC_PTP_PPS_4096HZ
+ * - EMAC_PTP_PPS_8192HZ
+ * - EMAC_PTP_PPS_16384HZ
+ * - EMAC_PTP_PPS_32768HZ
+ * @retval none
+ */
+void emac_ptp_pps_frequency_set(emac_ptp_pps_control_type freq)
+{
+ EMAC_PTP->ppscr_bit.pofc = freq;
+}
+
+/**
+ * @brief this is delay function base on system clock.
+ * @param delay: delay time
+ * @retval none
+ */
+static void emac_delay(uint32_t delay)
+{
+ __IO uint32_t delay_time = delay * (system_core_clock / 8 / 1000);
+ do
+ {
+ __NOP();
+ }
+ while(delay_time --);
+}
+
+/**
+ * @brief check whether the specified emac dma flag is set or not.
+ * @param dma_flag: specifies the emac dma flag to check.
+ * this parameter can be one of emac dma flag status:
+ * - EMAC_DMA_TI_FLAG
+ * - EMAC_DMA_TPS_FLAG
+ * - EMAC_DMA_TBU_FLAG
+ * - EMAC_DMA_TJT_FLAG
+ * - EMAC_DMA_OVF_FLAG
+ * - EMAC_DMA_UNF_FLAG
+ * - EMAC_DMA_RI_FLAG
+ * - EMAC_DMA_RBU_FLAG
+ * - EMAC_DMA_RPS_FLAG
+ * - EMAC_DMA_RWT_FLAG
+ * - EMAC_DMA_ETI_FLAG
+ * - EMAC_DMA_FBEI_FLAG
+ * - EMAC_DMA_ERI_FLAG
+ * - EMAC_DMA_AIS_FLAG
+ * - EMAC_DMA_NIS_FLAG
+ * @retval the new state of dma_flag (SET or RESET).
+ */
+flag_status emac_dma_flag_get(uint32_t dma_flag)
+{
+ flag_status status = RESET;
+
+ if(EMAC_DMA->sts & dma_flag)
+ status = SET;
+ /* return the new state (SET or RESET) */
+ return status;
+}
+
+/**
+ * @brief clear the emac dma flag.
+ * @param dma_flag: specifies the emac dma flags to clear.
+ * this parameter can be any combination of the following values:
+ * - EMAC_DMA_TI_FLAG
+ * - EMAC_DMA_TPS_FLAG
+ * - EMAC_DMA_TBU_FLAG
+ * - EMAC_DMA_TJT_FLAG
+ * - EMAC_DMA_OVF_FLAG
+ * - EMAC_DMA_UNF_FLAG
+ * - EMAC_DMA_RI_FLAG
+ * - EMAC_DMA_RBU_FLAG
+ * - EMAC_DMA_RPS_FLAG
+ * - EMAC_DMA_RWT_FLAG
+ * - EMAC_DMA_ETI_FLAG
+ * - EMAC_DMA_FBEI_FLAG
+ * - EMAC_DMA_ERI_FLAG
+ * - EMAC_DMA_AIS_FLAG
+ * - EMAC_DMA_NIS_FLAG
+ * @retval none
+ */
+void emac_dma_flag_clear(uint32_t dma_flag)
+{
+ EMAC_DMA->sts = dma_flag;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_ertc.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_ertc.c
new file mode 100644
index 0000000..f46ea60
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_ertc.c
@@ -0,0 +1,1577 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_ertc.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the ertc firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup ERTC
+ * @brief ERTC driver modules
+ * @{
+ */
+
+#ifdef ERTC_MODULE_ENABLED
+
+/** @defgroup ERTC_private_functions
+ * @{
+ */
+
+#define ERTC_TIMEOUT ((uint32_t) 0x00360000)
+
+/**
+ * @brief number conversion to bcd code.
+ * @param num: number(0~99)
+ * @retval bcd code.
+ */
+uint8_t ertc_num_to_bcd(uint8_t num)
+{
+ uint8_t bcd_h = 0, bcd_l = 0;
+
+ bcd_h = num / 10;
+ bcd_l = num % 10;
+
+ return ((uint8_t)(bcd_h << 4) | bcd_l);
+}
+
+/**
+ * @brief bcd code conversion to number.
+ * @param bcd: bcd code(0~99).
+ * @retval number.
+ */
+uint8_t ertc_bcd_to_num(uint8_t bcd)
+{
+ return ((((uint8_t)(bcd & (uint8_t)0xF0) >> 4) * 10) + (bcd & (uint8_t)0x0F));
+}
+
+/**
+ * @brief enable write protection.
+ * @param none.
+ * @retval none
+ */
+void ertc_write_protect_enable(void)
+{
+ ERTC->wp = 0xFF;
+}
+
+/**
+ * @brief disable write protection.
+ * @param none.
+ * @retval none
+ */
+void ertc_write_protect_disable(void)
+{
+ ERTC->wp = 0xCA;
+ ERTC->wp = 0x53;
+}
+
+/**
+ * @brief ertc wait register update finish.
+ * @param none.
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_wait_update(void)
+{
+ uint32_t timeout = ERTC_TIMEOUT * 2;
+
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ /* clear updf flag */
+ ERTC->sts = ~(ERTC_UPDF_FLAG | 0x00000080) | (ERTC->sts_bit.imen << 7);
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ while(ERTC->sts_bit.updf == 0)
+ {
+ if(timeout == 0)
+ {
+ return ERROR;
+ }
+
+ timeout--;
+ }
+
+ return SUCCESS;
+}
+
+/**
+ * @brief ertc wait flag status.
+ * @param flag: flag to wait.
+ * this parameter can be one of the following values:
+ * - ERTC_ALAWF_FLAG: alarm a register allows write flag.
+ * - ERTC_ALBWF_FLAG: alarm b register allows write flag.
+ * - ERTC_WATWF_FLAG: wakeup timer register allows write flag.
+ * - ERTC_TADJF_FLAG: time adjustment flag.
+ * - ERTC_CALUPDF_FLAG: calibration value update completed flag.
+ * @param status: status to wait.
+ * this parameter can be one of the following values:
+ * - SET.
+ * - RESET.
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_wait_flag(uint32_t flag, flag_status status)
+{
+ uint32_t timeout = ERTC_TIMEOUT;
+
+ while(ertc_flag_get(flag) == status)
+ {
+ if(timeout == 0)
+ {
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return ERROR;
+ }
+
+ timeout--;
+ }
+
+ return SUCCESS;
+}
+
+/**
+ * @brief ertc enter init mode.
+ * @param none.
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_init_mode_enter(void)
+{
+ uint32_t timeout = ERTC_TIMEOUT * 2;
+
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(ERTC->sts_bit.imf == 0)
+ {
+ /* enter init mode */
+ ERTC->sts = 0xFFFFFFFF;
+
+ while(ERTC->sts_bit.imf == 0)
+ {
+ if(timeout == 0)
+ {
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return ERROR;
+ }
+
+ timeout--;
+ }
+ }
+
+ return SUCCESS;
+}
+
+/**
+ * @brief ertc exit init mode.
+ * @param none.
+ * @retval none.
+ */
+void ertc_init_mode_exit(void)
+{
+ ERTC->sts = 0xFFFFFF7F;
+}
+
+/**
+ * @brief ertc reset all register.
+ * @param none.
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_reset(void)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl = (uint32_t)0x00000000;
+
+ /* enter init mode */
+ if(ertc_init_mode_enter() != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ /* reset register */
+ ERTC->time = (uint32_t)0x00000000;
+ ERTC->date = (uint32_t)0x00002101;
+ ERTC->ctrl = (uint32_t)0x00000000;
+ ERTC->div = (uint32_t)0x007F00FF;
+ ERTC->wat = (uint32_t)0x0000FFFF;
+ ERTC->ccal = (uint32_t)0x00000000;
+ ERTC->ala = (uint32_t)0x00000000;
+ ERTC->alb = (uint32_t)0x00000000;
+ ERTC->tadj = (uint32_t)0x00000000;
+ ERTC->scal = (uint32_t)0x00000000;
+ ERTC->tamp = (uint32_t)0x00000000;
+ ERTC->alasbs = (uint32_t)0x00000000;
+ ERTC->albsbs = (uint32_t)0x00000000;
+ ERTC->sts = (uint32_t)0x00000000;
+
+ /* wait calendar update */
+ ertc_wait_update();
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief ertc division set.
+ * @param div_a: division a (0~0x7F).
+ * @param div_b: division b (0~0x7FFF).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_divider_set(uint16_t div_a, uint16_t div_b)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ /* enter init mode */
+ if(ertc_init_mode_enter() != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ /* config the ertc divider */
+ ERTC->div_bit.diva = div_a;
+ ERTC->div_bit.divb = div_b;
+
+ /* exit init mode */
+ ertc_init_mode_exit();
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief ertc hour mode set.
+ * @param mode: hour mode.
+ * this parameter can be one of the following values:
+ * - ERTC_HOUR_MODE_24: 24-hour format.
+ * - ERTC_HOUR_MODE_12: 12-hour format.
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_hour_mode_set(ertc_hour_mode_set_type mode)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ /* enter init mode */
+ if(ertc_init_mode_enter() != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ /* write register */
+ ERTC->ctrl_bit.hm = mode;
+
+ /* exit init mode */
+ ertc_init_mode_exit();
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief set date.
+ * @param year: year (0~99).
+ * @param month: month (1~12).
+ * @param date: date (1~31).
+ * @param week: week (1~7).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t week)
+{
+ ertc_reg_date_type reg;
+
+ reg.date = 0;
+
+ reg.date_bit.y = ertc_num_to_bcd(year);
+ reg.date_bit.m = ertc_num_to_bcd(month);
+ reg.date_bit.d = ertc_num_to_bcd(date);
+ reg.date_bit.wk = week;
+
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ /* enter init mode */
+ if(ertc_init_mode_enter() != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ /* Set the ertc_DR register */
+ ERTC->date = reg.date;
+
+ /* exit init mode */
+ ertc_init_mode_exit();
+
+ if(ERTC->ctrl_bit.dren == 0)
+ {
+ ertc_wait_update();
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief set time.
+ * @param hour: hour (0~23).
+ * @param min: minute (0~59).
+ * @param sec: second (0~59).
+ * @param ampm: hour mode.
+ * this parameter can be one of the following values:
+ * - ERTC_24H: 24-hour format.
+ * - ERTC_AM: 12-hour format, ante meridiem.
+ * - ERTC_PM: 12-hour format, post meridiem.
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_time_set(uint8_t hour, uint8_t min, uint8_t sec, ertc_am_pm_type ampm)
+{
+ ertc_reg_time_type reg;
+
+ reg.time = 0;
+
+ reg.time_bit.h = ertc_num_to_bcd(hour);
+ reg.time_bit.m = ertc_num_to_bcd(min);
+ reg.time_bit.s = ertc_num_to_bcd(sec);
+ reg.time_bit.ampm = ampm;
+
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ /* enter init mode */
+ if(ertc_init_mode_enter() != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ ERTC->time = reg.time;
+
+ /* exit init mode */
+ ertc_init_mode_exit();
+
+ if(ERTC->ctrl_bit.dren == 0)
+ {
+ ertc_wait_update();
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief get calendar
+ * @param time: ertc time.
+ * @retval none.
+ */
+void ertc_calendar_get(ertc_time_type* time)
+{
+ ertc_reg_time_type reg_tm;
+ ertc_reg_date_type reg_dt;
+
+ (void) (ERTC->sts);
+
+ reg_tm.time = ERTC->time;
+ reg_dt.date = ERTC->date;
+
+ time->hour = ertc_bcd_to_num(reg_tm.time_bit.h);
+ time->min = ertc_bcd_to_num(reg_tm.time_bit.m);
+ time->sec = ertc_bcd_to_num(reg_tm.time_bit.s);
+ time->ampm = (ertc_am_pm_type)reg_tm.time_bit.ampm;
+
+ time->year = ertc_bcd_to_num(reg_dt.date_bit.y);
+ time->month = ertc_bcd_to_num(reg_dt.date_bit.m);
+ time->day = ertc_bcd_to_num(reg_dt.date_bit.d);
+ time->week = reg_dt.date_bit.wk;
+}
+
+/**
+ * @brief get current sub second.
+ * @param none.
+ * @retval sub second.
+ */
+uint32_t ertc_sub_second_get(void)
+{
+ uint32_t reg = 0;
+
+ reg = ERTC->sbs;
+
+ (void) (ERTC->date);
+
+ return (reg);
+}
+
+/**
+ * @brief set which bits are irrelevant to the alarm match.
+ * @param alarm_x: select the alarm.
+ * this parameter can be one of the following values:
+ * - ERTC_ALA: alarm a.
+ * - ERTC_ALB: alarm b.
+ * @param mask: select which bits are irrelevant to the alarm match.
+ * this parameter can be one of the following values:
+ * - ERTC_ALARM_MASK_NONE: match all.
+ * - ERTC_ALARM_MASK_SEC: don't match seconds.
+ * - ERTC_ALARM_MASK_MIN: don't match minute.
+ * - ERTC_ALARM_MASK_HOUR: don't match hour.
+ * - ERTC_ALARM_MASK_DATE_WEEK: don't match date or week.
+ * - ERTC_ALARM_MASK_ALL: don't match all.
+ * @param alarm: alarm para.
+ * @retval none.
+ */
+void ertc_alarm_mask_set(ertc_alarm_type alarm_x, uint32_t mask)
+{
+ uint32_t reg;
+
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(alarm_x == ERTC_ALA)
+ {
+ reg = ERTC->ala;
+
+ reg &= ~ERTC_ALARM_MASK_ALL;
+ reg |= mask;
+
+ ERTC->ala= reg;
+ }
+ else
+ {
+ reg = ERTC->alb;
+
+ reg &= ~ERTC_ALARM_MASK_ALL;
+ reg |= mask;
+
+ ERTC->alb= reg;
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief alarm week or date mode select.
+ * @param alarm_x: select the alarm.
+ * this parameter can be one of the following values:
+ * - ERTC_ALA: alarm a.
+ * - ERTC_ALB: alarm b.
+ * @param wk: week or date mode select.
+ * this parameter can be one of the following values:
+ * - ERTC_SLECT_DATE: slect date mode.
+ * - ERTC_SLECT_WEEK: slect week mode.
+ * @retval none.
+ */
+void ertc_alarm_week_date_select(ertc_alarm_type alarm_x, ertc_week_date_select_type wk)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(alarm_x == ERTC_ALA)
+ {
+ ERTC->ala_bit.wksel = wk;
+ }
+ else
+ {
+ ERTC->alb_bit.wksel = wk;
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set alarm.
+ * @param alarm_x: select the alarm.
+ * this parameter can be one of the following values:
+ * - ERTC_ALA: alarm a.
+ * - ERTC_ALB: alarm b.
+ * @param week_day: week or date.
+ * - week: 1~7.
+ * - date: 1~31.
+ * @param hour: hour (0~23).
+ * @param min: minute (0~59).
+ * @param sec: second (0~59).
+ * @param ampm: hour mode.
+ * this parameter can be one of the following values:
+ * - ERTC_24H: 24-hour format.
+ * - ERTC_AM: 12-hour format, ante meridiem.
+ * - ERTC_PM: 12-hour format, post meridiem.
+ * @param alarm: alarm para.
+ * @retval none.
+ */
+void ertc_alarm_set(ertc_alarm_type alarm_x, uint8_t week_date, uint8_t hour, uint8_t min, uint8_t sec, ertc_am_pm_type ampm)
+{
+ ertc_reg_alarm_type reg;
+
+ if(alarm_x == ERTC_ALA)
+ {
+ reg.ala = ERTC->ala;
+ }
+ else
+ {
+ reg.ala = ERTC->alb;
+ }
+
+ reg.ala_bit.d = ertc_num_to_bcd(week_date);
+ reg.ala_bit.h = ertc_num_to_bcd(hour);
+ reg.ala_bit.m = ertc_num_to_bcd(min);
+ reg.ala_bit.s = ertc_num_to_bcd(sec);
+ reg.ala_bit.ampm = ampm;
+
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(alarm_x == ERTC_ALA)
+ {
+ ERTC->ala= reg.ala;
+ }
+ else
+ {
+ ERTC->alb = reg.ala;
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set alarm sub second.
+ * @param alarm_x: select the alarm.
+ * this parameter can be one of the following values:
+ * - ERTC_ALA: alarm a.
+ * - ERTC_ALB: alarm b.
+ * @param value: sub second value.
+ * @param mask: sub second mask.
+ * this parameter can be one of the following values:
+ * - ERTC_ALARM_SBS_MASK_ALL: do not match the sub-second.
+ * - ERTC_ALARM_SBS_MASK_14_1: only compare bit [0].
+ * - ERTC_ALARM_SBS_MASK_14_2: only compare bit [1:0].
+ * - ERTC_ALARM_SBS_MASK_14_3: only compare bit [2:0].
+ * - ERTC_ALARM_SBS_MASK_14_4: only compare bit [3:0].
+ * - ERTC_ALARM_SBS_MASK_14_5: only compare bit [4:0].
+ * - ERTC_ALARM_SBS_MASK_14_6: only compare bit [5:0].
+ * - ERTC_ALARM_SBS_MASK_14_7: only compare bit [6:0].
+ * - ERTC_ALARM_SBS_MASK_14_8: only compare bit [7:0].
+ * - ERTC_ALARM_SBS_MASK_14_9: only compare bit [8:0].
+ * - ERTC_ALARM_SBS_MASK_14_10: only compare bit [9:0].
+ * - ERTC_ALARM_SBS_MASK_14_11: only compare bit [10:0].
+ * - ERTC_ALARM_SBS_MASK_14_12: only compare bit [11:0].
+ * - ERTC_ALARM_SBS_MASK_14_13: only compare bit [12:0].
+ * - ERTC_ALARM_SBS_MASK_14: only compare bit [13:0].
+ * - ERTC_ALARM_SBS_MASK_NONE: compare bit [14:0].
+ * @retval none.
+ */
+void ertc_alarm_sub_second_set(ertc_alarm_type alarm_x, uint32_t value, ertc_alarm_sbs_mask_type mask)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(alarm_x == ERTC_ALA)
+ {
+ ERTC->alasbs_bit.sbsmsk = mask;
+ ERTC->alasbs_bit.sbs = value;
+ }
+ else
+ {
+ ERTC->albsbs_bit.sbsmsk = mask;
+ ERTC->albsbs_bit.sbs = value;
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief enable or disable alarm clock.
+ * @param alarm_x: select the alarm.
+ * this parameter can be one of the following values:
+ * - ERTC_ALA: alarm a.
+ * - ERTC_ALB: alarm b.
+ * @param new_state (TRUE or FALSE).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_alarm_enable(ertc_alarm_type alarm_x, confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(alarm_x == ERTC_ALA)
+ {
+ ERTC->ctrl_bit.alaen = new_state;
+
+ if(new_state == FALSE)
+ {
+ if(ertc_wait_flag(ERTC_ALAWF_FLAG, RESET) != SUCCESS)
+ {
+ return ERROR;
+ }
+ }
+ }
+ else
+ {
+ ERTC->ctrl_bit.alben = new_state;
+
+ if(new_state == FALSE)
+ {
+ if(ertc_wait_flag(ERTC_ALBWF_FLAG, RESET) != SUCCESS)
+ {
+ return ERROR;
+ }
+ }
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief get alarm value.
+ * @param alarm_x: select the alarm.
+ * this parameter can be one of the following values:
+ * - ERTC_ALA: alarm a.
+ * - ERTC_ALB: alarm b.
+ * @param alarm: alarm para.
+ * @retval none.
+ */
+void ertc_alarm_get(ertc_alarm_type alarm_x, ertc_alarm_value_type* alarm)
+{
+ ertc_reg_alarm_type reg;
+
+ reg.ala = 0;
+
+ if(alarm_x == ERTC_ALA)
+ {
+ reg.ala = ERTC->ala;
+ }
+ else
+ {
+ reg.ala = ERTC->alb;
+ }
+
+ alarm->day = ertc_bcd_to_num(reg.ala_bit.d);
+ alarm->week = ertc_bcd_to_num(reg.ala_bit.d);
+ alarm->hour = ertc_bcd_to_num(reg.ala_bit.h);
+ alarm->min = ertc_bcd_to_num(reg.ala_bit.m);
+ alarm->sec = ertc_bcd_to_num(reg.ala_bit.s);
+ alarm->ampm = (ertc_am_pm_type)reg.ala_bit.ampm;
+ alarm->week_date_sel = reg.ala_bit.wksel;
+ alarm->mask = reg.ala & ERTC_ALARM_MASK_ALL;
+}
+
+/**
+ * @brief get alarm sub second.
+ * @param alarm_x: select the alarm.
+ * this parameter can be one of the following values:
+ * - ERTC_ALA: alarm a.
+ * - ERTC_ALB: alarm b.
+ * @retval sub second.
+ */
+uint32_t ertc_alarm_sub_second_get(ertc_alarm_type alarm_x)
+{
+ if(alarm_x == ERTC_ALA)
+ {
+ return (ERTC->alasbs_bit.sbs);
+ }
+ else
+ {
+ return (ERTC->albsbs_bit.sbs);
+ }
+}
+
+/**
+ * @brief set wakeup timer clock.
+ * @param clock: wakeup timer clock source.
+ * this parameter can be one of the following values:
+ * - ERTC_WAT_CLK_ERTCCLK_DIV16: ERTC_CLK / 16.
+ * - ERTC_WAT_CLK_ERTCCLK_DIV8: ERTC_CLK / 8.
+ * - ERTC_WAT_CLK_ERTCCLK_DIV4: ERTC_CLK / 4.
+ * - ERTC_WAT_CLK_ERTCCLK_DIV2: ERTC_CLK / 2.
+ * - ERTC_WAT_CLK_CK_A_16BITS: CK_A, wakeup counter = ERTC_WAT
+ * - ERTC_WAT_CLK_CK_A_17BITS: CK_A, wakeup counter = ERTC_WAT + 65535.
+ * @retval none.
+ */
+void ertc_wakeup_clock_set(ertc_wakeup_clock_type clock)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl_bit.watclk = clock;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set wakeup counter.
+ * @param counter: wakeup counter(0~65535).
+ * @retval none.
+ */
+void ertc_wakeup_counter_set(uint32_t counter)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->wat_bit.val = counter;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief get wakeup counter.
+ * @param none.
+ * @retval wakeup counter.
+ */
+uint16_t ertc_wakeup_counter_get(void)
+{
+ return ERTC->wat_bit.val;
+}
+
+/**
+ * @brief enable or disable wakeup timer.
+ * @param new_state (TRUE or FALSE).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_wakeup_enable(confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl_bit.waten = new_state;
+
+ if(new_state == FALSE)
+ {
+ if(ertc_wait_flag(ERTC_ALAWF_FLAG, RESET) != SUCCESS)
+ {
+ return ERROR;
+ }
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief config the smooth calibration.
+ * @param period: calibration period.
+ * this parameter can be one of the following values:
+ * - ERTC_SMOOTH_CAL_PERIOD_32: 32 second calibration period.
+ * - ERTC_SMOOTH_CAL_PERIOD_16: 16 second calibration period.
+ * - ERTC_SMOOTH_CAL_PERIOD_8: 8 second calibration period.
+ * @param clk_add: add clock.
+ * this parameter can be one of the following values:
+ * - ERTC_SMOOTH_CAL_CLK_ADD_0: do not increase clock.
+ * - ERTC_SMOOTH_CAL_CLK_ADD_512: add 512 clocks.
+ * @param clk_dec: decrease clock(0~511).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_smooth_calibration_config(ertc_smooth_cal_period_type period, ertc_smooth_cal_clk_add_type clk_add, uint32_t clk_dec)
+{
+ ertc_reg_scal_type reg;
+
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(ertc_wait_flag(ERTC_CALUPDF_FLAG, SET) != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ reg.scal = 0;
+
+ switch (period)
+ {
+ case ERTC_SMOOTH_CAL_PERIOD_32:
+ break;
+ case ERTC_SMOOTH_CAL_PERIOD_16:
+ reg.scal_bit.cal16 = 1;
+ break;
+ case ERTC_SMOOTH_CAL_PERIOD_8:
+ reg.scal_bit.cal8 = 1;
+ break;
+ default:
+ break;
+ }
+
+ reg.scal_bit.add = clk_add;
+ reg.scal_bit.dec = clk_dec;
+
+ ERTC->scal = reg.scal;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief set the coarse digital calibration.
+ * @param dir: calibration direction.
+ * this parameter can be one of the following values:
+ * - ERTC_CAL_DIR_POSITIVE: positive calibration.
+ * - ERTC_CAL_DIR_NEGATIVE: negative calibration.
+ * @param value: calibration value(0~31).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_coarse_calibration_set(ertc_cal_direction_type dir, uint32_t value)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ /* enter init mode */
+ if(ertc_init_mode_enter() == ERROR)
+ {
+ return ERROR;
+ }
+
+ ERTC->ccal_bit.caldir = dir;
+
+ ERTC->ccal_bit.calval = value;
+
+ /* exit init mode */
+ ertc_init_mode_exit();
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief enable or disable coarse calibration.
+ * @param new_state (TRUE or FALSE).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_coarse_calibration_enable(confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ /* enter init mode */
+ if(ertc_init_mode_enter() == ERROR)
+ {
+ return ERROR;
+ }
+
+ ERTC->ctrl_bit.ccalen = new_state;
+
+ /* exit init mode */
+ ertc_init_mode_exit();
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief calibration output source select.
+ * @param output: output source.
+ * this parameter can be one of the following values:
+ * - ERTC_CAL_OUTPUT_512HZ: output 512 hz.
+ * - ERTC_CAL_OUTPUT_1HZ: output 1 hz.
+ * @retval none.
+ */
+void ertc_cal_output_select(ertc_cal_output_select_type output)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl_bit.calosel = output;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief enable or disable calibration output.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void ertc_cal_output_enable(confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl_bit.caloen = new_state;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief adjust the time.
+ * @param add1s: second operation.
+ * this parameter can be one of the following values:
+ * - ERTC_TIME_ADD_NONE: none operation.
+ * - ERTC_TIME_ADD_1S: add 1 second.
+ * @param decsbs: decrease sub second(0~0x7FFF).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_time_adjust(ertc_time_adjust_type add1s, uint32_t decsbs)
+{
+ ertc_reg_tadj_type reg;
+
+ reg.tadj = 0;
+
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(ertc_wait_flag(ERTC_TADJF_FLAG, SET) != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ /* check if the reference clock detection is disabled */
+ if(ERTC->ctrl_bit.rcden == 0)
+ {
+ reg.tadj_bit.add1s = add1s;
+ reg.tadj_bit.decsbs = decsbs;
+
+ ERTC->tadj = reg.tadj;
+
+ if(ertc_wait_update() == ERROR)
+ {
+ return ERROR;
+ }
+ }
+ else
+ {
+ return ERROR;
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief config the daylight saving time.
+ * @param operation: time adjust.
+ * this parameter can be one of the following values:
+ * - ERTC_DST_ADD_1H: add 1 hour.
+ * - ERTC_DST_DEC_1H: dec 1 hour.
+ * @param save: operation save.
+ * this parameter can be one of the following values:
+ * - ERTC_DST_SAVE_0: set the bpr register value to 0.
+ * - ERTC_DST_SAVE_1: set the bpr register value to 1.
+ * @retval none.
+ */
+void ertc_daylight_set(ertc_dst_operation_type operation, ertc_dst_save_type save)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(operation == ERTC_DST_ADD_1H)
+ {
+ ERTC->ctrl_bit.add1h = 1;
+ }
+ else
+ {
+ ERTC->ctrl_bit.dec1h = 1;
+ }
+
+ ERTC->ctrl_bit.bpr = save;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief get the bpr value.
+ * @param none.
+ * @retval bpr value.
+ */
+uint8_t ertc_daylight_bpr_get(void)
+{
+ return ERTC->ctrl_bit.bpr;
+}
+
+/**
+ * @brief enable or disable refer clock detect.
+ * @param new_state (TRUE or FALSE).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_refer_clock_detect_enable(confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ /* enter init mode */
+ if(ertc_init_mode_enter() != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ /* write register */
+ ERTC->ctrl_bit.rcden = new_state;
+
+ /* exit init mode */
+ ertc_init_mode_exit();
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief enable or disable direct read mode.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void ertc_direct_read_enable(confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl_bit.dren = new_state;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set the output mode.
+ * @param source: output source.
+ * this parameter can be one of the following values:
+ * - ERTC_OUTPUT_DISABLE: diable output.
+ * - ERTC_OUTPUT_ALARM_A: output alarm a event.
+ * - ERTC_OUTPUT_ALARM_B: output alarm b event.
+ * - ERTC_OUTPUT_WAKEUP: output wakeup event.
+ * @param polarity: output polarity.
+ * this parameter can be one of the following values:
+ * - ERTC_OUTPUT_POLARITY_HIGH: when the event occurs, the output is high.
+ * - ERTC_OUTPUT_POLARITY_LOW: when the event occurs, the output is low.
+ * @param type: output type.
+ * this parameter can be one of the following values:
+ * - ERTC_OUTPUT_TYPE_OPEN_DRAIN: open drain output.
+ * - ERTC_OUTPUT_TYPE_PUSH_PULL: push pull output.
+ * @retval none.
+ */
+void ertc_output_set(ertc_output_source_type source, ertc_output_polarity_type polarity, ertc_output_type type)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl_bit.outp = polarity;
+
+ ERTC->tamp_bit.outtype = type;
+
+ ERTC->ctrl_bit.outsel = source;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief timestamp detection pin selection.
+ * @param pin: data register
+ * this parameter can be one of the following values:
+ * - ERTC_PIN_PC13: pc13 is used as timestamp detection pin.
+ * - ERTC_PIN_PA0: pa0 is used as timestamp detection pin.
+ * @retval data value.
+ */
+void ertc_timestamp_pin_select(ertc_pin_select_type pin)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->tamp_bit.tspin = pin;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set the timestamp valid edge.
+ * @param edge: calibration period.
+ * this parameter can be one of the following values:
+ * - ERTC_TIMESTAMP_EDGE_RISING : rising edge trigger.
+ * - ERTC_TIMESTAMP_EDGE_FALLING: falling edge trigger.
+ * @retval none.
+ */
+void ertc_timestamp_valid_edge_set(ertc_timestamp_valid_edge_type edge)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl_bit.tsedg = edge;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief enable or disable timestamp.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void ertc_timestamp_enable(confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl_bit.tsen = new_state;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief get the timestamp.
+ * @param time: time.
+ * @param date: date.
+ * @retval none.
+ */
+void ertc_timestamp_get(ertc_time_type* time)
+{
+ ertc_reg_tstm_type tmtime;
+ ertc_reg_tsdt_type tmdate;
+
+ tmtime.tstm = ERTC->tstm;
+ tmdate.tsdt = ERTC->tsdt;
+
+ time->year = 0;
+ time->month = ertc_bcd_to_num(tmdate.tsdt_bit.m);
+ time->day = ertc_bcd_to_num(tmdate.tsdt_bit.d);
+ time->week = ertc_bcd_to_num(tmdate.tsdt_bit.wk);
+ time->hour = ertc_bcd_to_num(tmtime.tstm_bit.h);
+ time->min = ertc_bcd_to_num(tmtime.tstm_bit.m);
+ time->sec = ertc_bcd_to_num(tmtime.tstm_bit.s);
+ time->ampm = (ertc_am_pm_type)tmtime.tstm_bit.ampm;
+}
+
+/**
+ * @brief get the timestamp sub second.
+ * @param none.
+ * @retval timestamp sub second.
+ */
+uint32_t ertc_timestamp_sub_second_get(void)
+{
+ return ERTC->tssbs_bit.sbs;
+}
+
+/**
+ * @brief tamper 1 detection pin selection.
+ * @param pin: data register
+ * this parameter can be one of the following values:
+ * - ERTC_PIN_PC13: pc13 is used as tamper 1 detection pin.
+ * - ERTC_PIN_PA0: pa0 is used as tamper 1 detection pin.
+ * @retval data value.
+ */
+void ertc_tamper_1_pin_select(ertc_pin_select_type pin)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->tamp_bit.tp1pin = pin;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief enable or disable tamper pin pull up.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void ertc_tamper_pull_up_enable(confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->tamp_bit.tppu = !new_state;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set the tamper pin pre-charge time.
+ * @param precharge: tamper detection pre-charge time
+ * this parameter can be one of the following values:
+ * - ERTC_TAMPER_PR_1_ERTCCLK: pre-charge time is 1 ERTC_CLK.
+ * - ERTC_TAMPER_PR_2_ERTCCLK: pre-charge time is 2 ERTC_CLK.
+ * - ERTC_TAMPER_PR_4_ERTCCLK: pre-charge time is 4 ERTC_CLK.
+ * - ERTC_TAMPER_PR_8_ERTCCLK: pre-charge time is 8 ERTC_CLK.
+ * @retval none.
+ */
+void ertc_tamper_precharge_set(ertc_tamper_precharge_type precharge)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->tamp_bit.tppr = precharge;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set the tamper filter time.
+ * @param filter: tamper filter.
+ * this parameter can be one of the following values:
+ * - ERTC_TAMPER_FILTER_DISABLE: disable filter function.
+ * - ERTC_TAMPER_FILTER_2: 2 consecutive samples arw valid, effective tamper event.
+ * - ERTC_TAMPER_FILTER_4: 4 consecutive samples arw valid, effective tamper event.
+ * - ERTC_TAMPER_FILTER_8: 8 consecutive samples arw valid, effective tamper event.
+ * @retval none.
+ */
+void ertc_tamper_filter_set(ertc_tamper_filter_type filter)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->tamp_bit.tpflt = filter;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set the tamper detection frequency.
+ * @param freq: tamper detection frequency.
+ * this parameter can be one of the following values:
+ * - ERTC_TAMPER_FREQ_DIV_32768: ERTC_CLK / 32768.
+ * - ERTC_TAMPER_FREQ_DIV_16384: ERTC_CLK / 16384.
+ * - ERTC_TAMPER_FREQ_DIV_8192: ERTC_CLK / 8192.
+ * - ERTC_TAMPER_FREQ_DIV_4096: ERTC_CLK / 4096.
+ * - ERTC_TAMPER_FREQ_DIV_2048: ERTC_CLK / 2048.
+ * - ERTC_TAMPER_FREQ_DIV_1024: ERTC_CLK / 1024.
+ * - ERTC_TAMPER_FREQ_DIV_512: ERTC_CLK / 512.
+ * - ERTC_TAMPER_FREQ_DIV_256: ERTC_CLK / 256.
+ * @retval none.
+ */
+void ertc_tamper_detect_freq_set(ertc_tamper_detect_freq_type freq)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->tamp_bit.tpfreq = freq;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set the tamper trigger.
+ * @param tamper_x: select the tamper.
+ * this parameter can be one of the following values:
+ * - ERTC_TAMPER_1: tamper 1.
+ * - ERTC_TAMPER_2: tamper 2.
+ * @param trigger: tamper valid edge.
+ * this parameter can be one of the following values:
+ * - ERTC_TAMPER_EDGE_RISING: rising gedge.
+ * - ERTC_TAMPER_EDGE_FALLING: falling gedge.
+ * - ERTC_TAMPER_EDGE_LOW: low level.
+ * - ERTC_TAMPER_EDGE_HIGH: high level.
+ * @param alarm: alarm para.
+ * @retval none.
+ */
+void ertc_tamper_valid_edge_set(ertc_tamper_select_type tamper_x, ertc_tamper_valid_edge_type trigger)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(tamper_x == ERTC_TAMPER_1)
+ {
+ ERTC->tamp_bit.tp1edg = trigger;
+ }
+ else
+ {
+ ERTC->tamp_bit.tp2edg = trigger;
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief enable or disable trigger timestamp when tamper event occurs.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void ertc_tamper_timestamp_enable(confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->tamp_bit.tptsen = new_state;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief enable or disable tamper.
+ * @param tamper_x: select the tamper.
+ * this parameter can be one of the following values:
+ * - ERTC_TAMPER_1: tamper 1.
+ * - ERTC_TAMPER_2: tamper 2.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(tamper_x == ERTC_TAMPER_1)
+ {
+ ERTC->tamp_bit.tp1en = new_state;
+ }
+ else
+ {
+ ERTC->tamp_bit.tp2en = new_state;
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief enable or disable interrupt.
+ * @param source: interrupts sources
+ * this parameter can be any combination of the following values:
+ * - ERTC_TP_INT: tamper interrupt.
+ * - ERTC_ALA_INT: alarm a interrupt.
+ * - ERTC_ALB_INT: alarm b interrupt.
+ * - ERTC_WAT_INT: wakeup timer interrupt.
+ * - ERTC_TS_INT: timestamp interrupt.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void ertc_interrupt_enable(uint32_t source, confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(source & ERTC_TP_INT)
+ {
+ if(new_state != FALSE)
+ {
+ ERTC->tamp |= ERTC_TP_INT;
+ }
+ else
+ {
+ ERTC->tamp &= ~ERTC_TP_INT;
+ }
+
+ source &= ~ERTC_TP_INT;
+ }
+
+ if(new_state != FALSE)
+ {
+ ERTC->ctrl |= source;
+ }
+ else
+ {
+ ERTC->ctrl &= ~source;
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief get interrupt status
+ * @param source
+ * this parameter can be one of the following values:
+ * - ERTC_TP_INT: tamper interrupt.
+ * - ERTC_ALA_INT: alarm a interrupt.
+ * - ERTC_ALB_INT: alarm b interrupt.
+ * - ERTC_WAT_INT: wakeup timer interrupt.
+ * - ERTC_TS_INT: timestamp interrupt.
+ * @retval flag_status (SET or RESET)
+ */
+flag_status ertc_interrupt_get(uint32_t source)
+{
+ if(source & ERTC_TP_INT)
+ {
+ if((ERTC->tamp & ERTC_TP_INT) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+ }
+
+ if((ERTC->ctrl & source) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief get flag status.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - ERTC_ALAWF_FLAG: alarm a register allows write flag.
+ * - ERTC_ALBWF_FLAG: alarm b register allows write flag.
+ * - ERTC_WATWF_FLAG: wakeup timer register allows write flag.
+ * - ERTC_TADJF_FLAG: time adjustment flag.
+ * - ERTC_INITF_FLAG: calendar initialization flag.
+ * - ERTC_UPDF_FLAG: calendar update flag.
+ * - ERTC_IMF_FLAG: enter initialization mode flag.
+ * - ERTC_ALAF_FLAG: alarm clock a flag.
+ * - ERTC_ALBF_FLAG: alarm clock b flag.
+ * - ERTC_WATF_FLAG: wakeup timer flag.
+ * - ERTC_TSF_FLAG: timestamp flag.
+ * - ERTC_TSOF_FLAG: timestamp overflow flag.
+ * - ERTC_TP1F_FLAG: tamper detection 1 flag.
+ * - ERTC_TP2F_FLAG: tamper detection 2 flag.
+ * - ERTC_CALUPDF_FLAG: calibration value update completed flag.
+ * @retval the new state of flag (SET or RESET).
+ */
+flag_status ertc_flag_get(uint32_t flag)
+{
+ if((ERTC->sts & flag) != (uint32_t)RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief clear flag status
+ * @param flag: specifies the flag to clear.
+ * this parameter can be any combination of the following values:
+ * - ERTC_ALAWF_FLAG: alarm a register allows write flag.
+ * - ERTC_ALBWF_FLAG: alarm b register allows write flag.
+ * - ERTC_WATWF_FLAG: wakeup timer register allows write flag.
+ * - ERTC_TADJF_FLAG: time adjustment flag.
+ * - ERTC_INITF_FLAG: calendar initialization flag.
+ * - ERTC_UPDF_FLAG: calendar update flag.
+ * - ERTC_IMF_FLAG: enter initialization mode flag.
+ * - ERTC_ALAF_FLAG: alarm clock a flag.
+ * - ERTC_ALBF_FLAG: alarm clock b flag.
+ * - ERTC_WATF_FLAG: wakeup timer flag.
+ * - ERTC_TSF_FLAG: timestamp flag.
+ * - ERTC_TSOF_FLAG: timestamp overflow flag.
+ * - ERTC_TP1F_FLAG: tamper detection 1 flag.
+ * - ERTC_TP2F_FLAG: tamper detection 2 flag.
+ * - ERTC_CALUPDF_FLAG: calibration value update completed flag.
+ * @retval none
+ */
+void ertc_flag_clear(uint32_t flag)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->sts = ~(flag | 0x00000080) | (ERTC->sts_bit.imen << 7);
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief write data to the bpr register.
+ * @param dt: data register
+ * this parameter can be one of the following values:
+ * - ERTC_DT1
+ * - ERTC_DT2
+ * - ...
+ * - ERTC_DT19
+ * - ERTC_DT20
+ * @param data: data to be write.
+ * @retval none.
+ */
+void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data)
+{
+ __IO uint32_t reg = 0;
+
+ reg = ERTC_BASE + 0x50 + (dt * 4);
+
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ *(__IO uint32_t *)reg = data;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief read data from bpr register.
+ * @param dt: data register
+ * this parameter can be one of the following values:
+ * - ERTC_DT1
+ * - ERTC_DT2
+ * - ...
+ * - ERTC_DT19
+ * - ERTC_DT20
+ * @retval data value.
+ */
+uint32_t ertc_bpr_data_read(ertc_dt_type dt)
+{
+ __IO uint32_t reg = 0;
+
+ reg = ERTC_BASE + 0x50 + (dt * 4);
+
+ return (*(__IO uint32_t *)reg);
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_exint.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_exint.c
new file mode 100644
index 0000000..600c871
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_exint.c
@@ -0,0 +1,236 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_exint.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the exint firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup EXINT
+ * @brief EXINT driver modules
+ * @{
+ */
+
+#ifdef EXINT_MODULE_ENABLED
+
+/** @defgroup EXINT_private_functions
+ * @{
+ */
+
+/**
+ * @brief exint reset
+ * @param none
+ * @retval none
+ */
+void exint_reset(void)
+{
+ EXINT->inten = 0x00000000;
+ EXINT->polcfg1 = 0x00000000;
+ EXINT->polcfg2 = 0x00000000;
+ EXINT->evten = 0x00000000;
+ EXINT->intsts = 0x007FFFFF;
+}
+
+/**
+ * @brief exint default para init
+ * @param exint_struct
+ * - to the structure of exint_init_type
+ * @retval none
+ */
+void exint_default_para_init(exint_init_type *exint_struct)
+{
+ exint_struct->line_enable = FALSE;
+ exint_struct->line_select = EXINT_LINE_NONE;
+ exint_struct->line_polarity = EXINT_TRIGGER_FALLING_EDGE;
+ exint_struct->line_mode = EXINT_LINE_EVENT;
+}
+
+/**
+ * @brief exint init
+ * @param exint_struct
+ * - to the structure of exint_init_type
+ * @retval none
+ */
+void exint_init(exint_init_type *exint_struct)
+{
+ uint32_t line_index = 0;
+ line_index = exint_struct->line_select;
+
+ EXINT->inten &= ~line_index;
+ EXINT->evten &= ~line_index;
+
+ if(exint_struct->line_enable != FALSE)
+ {
+ if(exint_struct->line_mode == EXINT_LINE_INTERRUPUT)
+ {
+ EXINT->inten |= line_index;
+ }
+ else
+ {
+ EXINT->evten |= line_index;
+ }
+
+ EXINT->polcfg1 &= ~line_index;
+ EXINT->polcfg2 &= ~line_index;
+ if(exint_struct->line_polarity == EXINT_TRIGGER_RISING_EDGE)
+ {
+ EXINT->polcfg1 |= line_index;
+ }
+ else if(exint_struct->line_polarity == EXINT_TRIGGER_FALLING_EDGE)
+ {
+ EXINT->polcfg2 |= line_index;
+ }
+ else
+ {
+ EXINT->polcfg1 |= line_index;
+ EXINT->polcfg2 |= line_index;
+ }
+ }
+}
+
+/**
+ * @brief clear exint flag
+ * @param exint_line
+ * this parameter can be any combination of the following values:
+ * - EXINT_LINE_0
+ * - EXINT_LINE_1
+ * ...
+ * - EXINT_LINE_21
+ * - EXINT_LINE_22
+ * @retval none
+ */
+void exint_flag_clear(uint32_t exint_line)
+{
+ EXINT->intsts = exint_line;
+}
+
+/**
+ * @brief get exint flag
+ * @param exint_line
+ * this parameter can be one of the following values:
+ * - EXINT_LINE_0
+ * - EXINT_LINE_1
+ * ...
+ * - EXINT_LINE_21
+ * - EXINT_LINE_22
+ * @retval the new state of exint flag(SET or RESET).
+ */
+flag_status exint_flag_get(uint32_t exint_line)
+{
+ flag_status status = RESET;
+ uint32_t exint_flag =0;
+ exint_flag = EXINT->intsts & exint_line;
+ if((exint_flag != (uint16_t)RESET))
+ {
+ status = SET;
+ }
+ else
+ {
+ status = RESET;
+ }
+ return status;
+}
+
+/**
+ * @brief generate exint software interrupt event
+ * @param exint_line
+ * this parameter can be one of the following values:
+ * - EXINT_LINE_0
+ * - EXINT_LINE_1
+ * ...
+ * - EXINT_LINE_21
+ * - EXINT_LINE_22
+ * @retval none
+ */
+void exint_software_interrupt_event_generate(uint32_t exint_line)
+{
+ EXINT->swtrg |= exint_line;
+}
+
+/**
+ * @brief enable or disable exint interrupt
+ * @param exint_line
+ * this parameter can be any combination of the following values:
+ * - EXINT_LINE_0
+ * - EXINT_LINE_1
+ * ...
+ * - EXINT_LINE_21
+ * - EXINT_LINE_22
+ * @param new_state: new state of exint interrupt.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ {
+ EXINT->inten |= exint_line;
+ }
+ else
+ {
+ EXINT->inten &= ~exint_line;
+ }
+}
+
+/**
+ * @brief enable or disable exint event
+ * @param exint_line
+ * this parameter can be any combination of the following values:
+ * - EXINT_LINE_0
+ * - EXINT_LINE_1
+ * ...
+ * - EXINT_LINE_21
+ * - EXINT_LINE_22
+ * @param new_state: new state of exint event.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void exint_event_enable(uint32_t exint_line, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ {
+ EXINT->evten |= exint_line;
+ }
+ else
+ {
+ EXINT->evten &= ~exint_line;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_flash.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_flash.c
new file mode 100644
index 0000000..ab23a50
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_flash.c
@@ -0,0 +1,1251 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_flash.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the flash firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup FLASH
+ * @brief FLASH driver modules
+ * @{
+ */
+
+#ifdef FLASH_MODULE_ENABLED
+
+/** @defgroup FLASH_private_functions
+ * @{
+ */
+
+/**
+ * @brief check whether the specified flash flag is set or not.
+ * @param flash_flag: specifies the flash flag to check.
+ * this parameter can be one of flash flag status:
+ * - FLASH_OBF_FLAG
+ * - FLASH_ODF_FLAG
+ * - FLASH_PRGMERR_FLAG
+ * - FLASH_EPPERR_FLAG
+ * - FLASH_BANK1_OBF_FLAG
+ * - FLASH_BANK1_ODF_FLAG
+ * - FLASH_BANK1_PRGMERR_FLAG
+ * - FLASH_BANK1_EPPERR_FLAG
+ * - FLASH_BANK2_OBF_FLAG
+ * - FLASH_BANK2_ODF_FLAG
+ * - FLASH_BANK2_PRGMERR_FLAG
+ * - FLASH_BANK2_EPPERR_FLAG
+ * - FLASH_USDERR_FLAG
+ * @retval the new state of flash_flag (SET or RESET).
+ */
+flag_status flash_flag_get(uint32_t flash_flag)
+{
+ flag_status status = RESET;
+ uint32_t flag_position;
+ flag_position = flash_flag & 0x70000000;
+ flash_flag &= 0x8FFFFFFF;
+ switch(flag_position)
+ {
+ case 0x00000000:
+ if(FLASH->sts & flash_flag)
+ status = SET;
+ break;
+ case 0x10000000:
+ if(FLASH->sts2 & flash_flag)
+ status = SET;
+ break;
+ case 0x40000000:
+ if(FLASH->usd & flash_flag)
+ status = SET;
+ break;
+ default:
+ break;
+ }
+ /* return the new state of flash_flag (SET or RESET) */
+ return status;
+}
+
+/**
+ * @brief clear the flash flag.
+ * @param flash_flag: specifies the flash flags to clear.
+ * this parameter can be any combination of the following values:
+ * - FLASH_ODF_FLAG
+ * - FLASH_PRGMERR_FLAG
+ * - FLASH_EPPERR_FLAG
+ * - FLASH_BANK1_ODF_FLAG
+ * - FLASH_BANK1_PRGMERR_FLAG
+ * - FLASH_BANK1_EPPERR_FLAG
+ * - FLASH_BANK2_ODF_FLAG
+ * - FLASH_BANK2_PRGMERR_FLAG
+ * - FLASH_BANK2_EPPERR_FLAG
+ * @retval none
+ */
+void flash_flag_clear(uint32_t flash_flag)
+{
+ uint32_t flag_position;
+ flag_position = flash_flag & 0x70000000;
+ flash_flag &= 0x8FFFFFFF;
+ switch(flag_position)
+ {
+ case 0x00000000:
+ FLASH->sts = flash_flag;
+ break;
+ case 0x10000000:
+ FLASH->sts2 = flash_flag;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief return the flash operation status.
+ * @param none
+ * @retval status: the returned value can be: FLASH_OPERATE_BUSY,
+ * FLASH_PROGRAM_ERROR, FLASH_EPP_ERROR or FLASH_OPERATE_DONE.
+ */
+flash_status_type flash_operation_status_get(void)
+{
+ flash_status_type flash_status = FLASH_OPERATE_DONE;
+ if(FLASH->sts_bit.obf != RESET)
+ {
+ flash_status = FLASH_OPERATE_BUSY;
+ }
+ else if(FLASH->sts_bit.prgmerr != RESET)
+ {
+ flash_status = FLASH_PROGRAM_ERROR;
+ }
+ else if(FLASH->sts_bit.epperr != RESET)
+ {
+ flash_status = FLASH_EPP_ERROR;
+ }
+ else
+ {
+ flash_status = FLASH_OPERATE_DONE;
+ }
+ /* return the flash status */
+ return flash_status;
+}
+
+/**
+ * @brief return the flash bank1 operation status.
+ * @param none
+ * @retval status: the returned value can be: FLASH_OPERATE_BUSY,
+ * FLASH_PROGRAM_ERROR, FLASH_EPP_ERROR or FLASH_OPERATE_DONE.
+ */
+flash_status_type flash_bank1_operation_status_get(void)
+{
+ flash_status_type flash_status = FLASH_OPERATE_DONE;
+ if(FLASH->sts_bit.obf != RESET)
+ {
+ flash_status = FLASH_OPERATE_BUSY;
+ }
+ else if(FLASH->sts_bit.prgmerr != RESET)
+ {
+ flash_status = FLASH_PROGRAM_ERROR;
+ }
+ else if(FLASH->sts_bit.epperr != RESET)
+ {
+ flash_status = FLASH_EPP_ERROR;
+ }
+ else
+ {
+ flash_status = FLASH_OPERATE_DONE;
+ }
+ /* return the flash status */
+ return flash_status;
+}
+
+/**
+ * @brief return the flash bank2 operation status.
+ * @param none
+ * @retval status: the returned value can be: FLASH_OPERATE_BUSY,
+ * FLASH_PROGRAM_ERROR, FLASH_EPP_ERROR or FLASH_OPERATE_DONE.
+ */
+flash_status_type flash_bank2_operation_status_get(void)
+{
+ flash_status_type flash_status = FLASH_OPERATE_DONE;
+ if(FLASH->sts2_bit.obf != RESET)
+ {
+ flash_status = FLASH_OPERATE_BUSY;
+ }
+ else if(FLASH->sts2_bit.prgmerr != RESET)
+ {
+ flash_status = FLASH_PROGRAM_ERROR;
+ }
+ else if(FLASH->sts2_bit.epperr != RESET)
+ {
+ flash_status = FLASH_EPP_ERROR;
+ }
+ else
+ {
+ flash_status = FLASH_OPERATE_DONE;
+ }
+ /* return the flash status */
+ return flash_status;
+}
+
+/**
+ * @brief wait for flash operation complete or timeout.
+ * @param time_out: flash operation timeout
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_operation_wait_for(uint32_t time_out)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ /* check for the flash status */
+ status = flash_operation_status_get();
+
+ while((status == FLASH_OPERATE_BUSY) && (time_out != 0x00))
+ {
+ status = flash_operation_status_get();
+ time_out--;
+ }
+ if(time_out == 0x00)
+ {
+ status = FLASH_OPERATE_TIMEOUT;
+ }
+ /* return the status */
+ return status;
+}
+
+/**
+ * @brief wait for flash bank1 operation complete or timeout.
+ * @param time_out: flash operation timeout
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_bank1_operation_wait_for(uint32_t time_out)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ /* check for the flash status */
+ status = flash_bank1_operation_status_get();
+
+ while((status == FLASH_OPERATE_BUSY) && (time_out != 0x00))
+ {
+ status = flash_bank1_operation_status_get();
+ time_out--;
+ }
+ if(time_out == 0x00)
+ {
+ status = FLASH_OPERATE_TIMEOUT;
+ }
+ /* return the operation status */
+ return status;
+}
+
+/**
+ * @brief wait for flash bank2 operation complete or timeout.
+ * @param time_out: flash operation timeout
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_bank2_operation_wait_for(uint32_t time_out)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ /* check for the flash status */
+ status = flash_bank2_operation_status_get();
+
+ while((status == FLASH_OPERATE_BUSY) && (time_out != 0x00))
+ {
+ status = flash_bank2_operation_status_get();
+ time_out--;
+ }
+ if(time_out == 0x00)
+ {
+ status = FLASH_OPERATE_TIMEOUT;
+ }
+ /* return the operation status */
+ return status;
+}
+
+/**
+ * @brief unlock the flash controller.
+ * @param none
+ * @retval none
+ */
+void flash_unlock(void)
+{
+ FLASH->unlock = FLASH_UNLOCK_KEY1;
+ FLASH->unlock = FLASH_UNLOCK_KEY2;
+ FLASH->unlock2 = FLASH_UNLOCK_KEY1;
+ FLASH->unlock2 = FLASH_UNLOCK_KEY2;
+}
+
+/**
+ * @brief unlock the flash bank1 controller.
+ * @param none
+ * @retval none
+ */
+void flash_bank1_unlock(void)
+{
+ FLASH->unlock = FLASH_UNLOCK_KEY1;
+ FLASH->unlock = FLASH_UNLOCK_KEY2;
+}
+
+/**
+ * @brief unlock the flash bank2 controller.
+ * @param none
+ * @retval none
+ */
+void flash_bank2_unlock(void)
+{
+ FLASH->unlock2 = FLASH_UNLOCK_KEY1;
+ FLASH->unlock2 = FLASH_UNLOCK_KEY2;
+}
+
+/**
+ * @brief lock the flash controller.
+ * @param none
+ * @retval none
+ */
+void flash_lock(void)
+{
+ FLASH->ctrl_bit.oplk = TRUE;
+ FLASH->ctrl2_bit.oplk = TRUE;
+}
+
+/**
+ * @brief lock the flash bank1 controller.
+ * @param none
+ * @retval none
+ */
+void flash_bank1_lock(void)
+{
+ FLASH->ctrl_bit.oplk = TRUE;
+}
+
+/**
+ * @brief lock the flash bank2 controller.
+ * @param none
+ * @retval none
+ */
+void flash_bank2_lock(void)
+{
+ FLASH->ctrl2_bit.oplk = TRUE;
+}
+
+/**
+ * @brief erase a specified flash sector.
+ * @param sector_address: the sector address to be erased.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_sector_erase(uint32_t sector_address)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ if((sector_address >= FLASH_BANK1_START_ADDR) && (sector_address <= FLASH_BANK1_END_ADDR))
+ {
+ /* wait for last operation to be completed */
+ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* if the previous operation is completed, continue to erase the sector */
+ FLASH->ctrl_bit.secers = TRUE;
+ FLASH->addr = sector_address;
+ FLASH->ctrl_bit.erstr = TRUE;
+
+ /* wait for operation to be completed */
+ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT);
+
+ /* disable the secers bit */
+ FLASH->ctrl_bit.secers = FALSE;
+ }
+ }
+ else if((sector_address >= FLASH_BANK2_START_ADDR) && (sector_address <= FLASH_BANK2_END_ADDR))
+ {
+ /* wait for last operation to be completed */
+ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* if the previous operation is completed, continue to erase the sector */
+ FLASH->ctrl2_bit.secers = TRUE;
+ FLASH->addr2 = sector_address;
+ FLASH->ctrl2_bit.erstr = TRUE;
+
+ /* wait for operation to be completed */
+ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT);
+
+ /* disable the secers bit */
+ FLASH->ctrl2_bit.secers = FALSE;
+ }
+ }
+
+ /* return the erase status */
+ return status;
+}
+
+/**
+ * @brief erase a specified flash block.
+ * @param block_address: the block address to be erased.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_block_erase(uint32_t block_address)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ if((block_address >= FLASH_BANK1_START_ADDR) && (block_address <= FLASH_BANK1_END_ADDR))
+ {
+ /* wait for last operation to be completed */
+ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* if the previous operation is completed, continue to erase the blkers */
+ FLASH->ctrl_bit.blkers = TRUE;
+ FLASH->addr = block_address;
+ FLASH->ctrl_bit.erstr = TRUE;
+
+ /* wait for operation to be completed */
+ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT);
+
+ /* disable the blkers bit */
+ FLASH->ctrl_bit.blkers = FALSE;
+ }
+ }
+ else if((block_address >= FLASH_BANK2_START_ADDR) && (block_address <= FLASH_BANK2_END_ADDR))
+ {
+ /* wait for last operation to be completed */
+ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* if the previous operation is completed, continue to erase the blkers */
+ FLASH->ctrl2_bit.blkers = TRUE;
+ FLASH->addr2 = block_address;
+ FLASH->ctrl2_bit.erstr = TRUE;
+
+ /* wait for operation to be completed */
+ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT);
+
+ /* disable the blkers bit */
+ FLASH->ctrl2_bit.blkers = FALSE;
+ }
+ }
+
+ /* return the erase status */
+ return status;
+}
+
+/**
+ * @brief erase flash all internal sectors.
+ * @param none
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_internal_all_erase(void)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ /* wait for last operation to be completed */
+ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* if the previous operation is completed, continue to erase bank1 */
+ FLASH->ctrl_bit.bankers = TRUE;
+ FLASH->ctrl_bit.erstr = TRUE;
+
+ /* wait for operation to be completed */
+ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT);
+
+ /* disable the bankers bit */
+ FLASH->ctrl_bit.bankers = FALSE;
+ }
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* if the previous operation is completed, continue to erase bank2 */
+ FLASH->ctrl2_bit.bankers = TRUE;
+ FLASH->ctrl2_bit.erstr = TRUE;
+
+ /* wait for operation to be completed */
+ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT);
+
+ /* disable the bankers bit */
+ FLASH->ctrl2_bit.bankers = FALSE;
+ }
+ /* return the erase status */
+ return status;
+}
+
+/**
+ * @brief erase flash bank1 sectors.
+ * @param none
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_bank1_erase(void)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ /* wait for last operation to be completed */
+ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* if the previous operation is completed, continue to erase bank1 */
+ FLASH->ctrl_bit.bankers = TRUE;
+ FLASH->ctrl_bit.erstr = TRUE;
+
+ /* wait for operation to be completed */
+ status = flash_bank1_operation_wait_for(ERASE_TIMEOUT);
+
+ /* disable the bankers bit */
+ FLASH->ctrl_bit.bankers = FALSE;
+ }
+ /* return the erase status */
+ return status;
+}
+
+/**
+ * @brief erase flash bank2 sectors.
+ * @param none
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_bank2_erase(void)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ /* wait for last operation to be completed */
+ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* if the previous operation is completed, continue to erase bank2 */
+ FLASH->ctrl2_bit.bankers = TRUE;
+ FLASH->ctrl2_bit.erstr = TRUE;
+
+ /* wait for operation to be completed */
+ status = flash_bank2_operation_wait_for(ERASE_TIMEOUT);
+
+ /* disable the bankers bit */
+ FLASH->ctrl2_bit.bankers = FALSE;
+ }
+ /* return the erase status */
+ return status;
+}
+
+/**
+ * @brief erase the flash user system data.
+ * @note this functions erase all user system data except the fap byte.
+ * the eopb0 byte value change to 0xFF, sram size maybe change too.
+ * @param none
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_user_system_data_erase(void)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ uint16_t fap_val = FAP_RELIEVE_KEY;
+ /* get the flash access protection status */
+ if(flash_fap_status_get() != RESET)
+ {
+ fap_val = 0x0000;
+ }
+
+ /* wait for last operation to be completed */
+ status = flash_operation_wait_for(ERASE_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* unlock the user system data */
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+ while(FLASH->ctrl_bit.usdulks==RESET);
+
+ /* erase the user system data */
+ FLASH->ctrl_bit.usders = TRUE;
+ FLASH->ctrl_bit.erstr = TRUE;
+
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(ERASE_TIMEOUT);
+
+ /* disable the usders bit */
+ FLASH->ctrl_bit.usders = FALSE;
+
+ if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY))
+ {
+ /* enable the user system data programming operation */
+ FLASH->ctrl_bit.usdprgm = TRUE;
+
+ /* restore the last flash access protection value */
+ USD->fap = (uint16_t)fap_val;
+
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /*disable the usdprgm bit */
+ FLASH->ctrl_bit.usdprgm = FALSE;
+ }
+ }
+ /* return the status */
+ return status;
+}
+
+/**
+ * @brief config the extend sram byte eopb0 in user system data.
+ * @note the 256kb and below capacity mcu only support FLASH_EOPB0_SRAM_384K,
+ * FLASH_EOPB0_SRAM_448K or FLASH_EOPB0_SRAM_512K.
+ * @param data: the eopb0 value.
+ * this parameter can be one of the following values:
+ * - FLASH_EOPB0_SRAM_512K
+ * - FLASH_EOPB0_SRAM_448K
+ * - FLASH_EOPB0_SRAM_384K
+ * - FLASH_EOPB0_SRAM_320K
+ * - FLASH_EOPB0_SRAM_256K
+ * - FLASH_EOPB0_SRAM_192K
+ * - FLASH_EOPB0_SRAM_128K
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_eopb0_config(flash_usd_eopb0_type data)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+
+ /* wait for last operation to be completed */
+ status = flash_operation_wait_for(ERASE_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* unlock the user system data */
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+ while(FLASH->ctrl_bit.usdulks==RESET);
+
+ /* enable the user system data programming operation */
+ FLASH->ctrl_bit.usdprgm = TRUE;
+
+ /* restore the default eopb0 value */
+ USD->eopb0 = (uint16_t)data;
+
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /*disable the usdprgm bit */
+ FLASH->ctrl_bit.usdprgm = FALSE;
+ }
+ /* return the status */
+ return status;
+}
+
+/**
+ * @brief program a word at a specified address.
+ * @param address: specifies the address to be programmed, word alignment is recommended.
+ * @param data: specifies the data to be programmed.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_word_program(uint32_t address, uint32_t data)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR))
+ {
+ /* wait for last operation to be completed */
+ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ FLASH->ctrl_bit.fprgm = TRUE;
+ *(__IO uint32_t*)address = data;
+ /* wait for operation to be completed */
+ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /* disable the fprgm bit */
+ FLASH->ctrl_bit.fprgm = FALSE;
+ }
+ }
+ else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR))
+ {
+ /* wait for last operation to be completed */
+ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ FLASH->ctrl2_bit.fprgm = TRUE;
+ *(__IO uint32_t*)address = data;
+ /* wait for operation to be completed */
+ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /* disable the fprgm bit */
+ FLASH->ctrl2_bit.fprgm = FALSE;
+ }
+ }
+
+ /* return the program status */
+ return status;
+}
+
+/**
+ * @brief program a halfword at a specified address.
+ * @param address: specifies the address to be programmed, halfword alignment is recommended.
+ * @param data: specifies the data to be programmed.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_halfword_program(uint32_t address, uint16_t data)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR))
+ {
+ /* wait for last operation to be completed */
+ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ FLASH->ctrl_bit.fprgm = TRUE;
+ *(__IO uint16_t*)address = data;
+ /* wait for operation to be completed */
+ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /* disable the fprgm bit */
+ FLASH->ctrl_bit.fprgm = FALSE;
+ }
+ }
+ else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR))
+ {
+ /* wait for last operation to be completed */
+ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ FLASH->ctrl2_bit.fprgm = TRUE;
+ *(__IO uint16_t*)address = data;
+ /* wait for operation to be completed */
+ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /* disable the fprgm bit */
+ FLASH->ctrl2_bit.fprgm = FALSE;
+ }
+ }
+
+ /* return the program status */
+ return status;
+}
+
+/**
+ * @brief program a byte at a specified address.
+ * @note this function cannot be used to program spim.
+ * @param address: specifies the address to be programmed.
+ * @param data: specifies the data to be programmed.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_byte_program(uint32_t address, uint8_t data)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ if((address >= FLASH_BANK1_START_ADDR) && (address <= FLASH_BANK1_END_ADDR))
+ {
+ /* wait for last operation to be completed */
+ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ FLASH->ctrl_bit.fprgm = TRUE;
+ *(__IO uint8_t*)address = data;
+ /* wait for operation to be completed */
+ status = flash_bank1_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /* disable the fprgm bit */
+ FLASH->ctrl_bit.fprgm = FALSE;
+ }
+ }
+ else if((address >= FLASH_BANK2_START_ADDR) && (address <= FLASH_BANK2_END_ADDR))
+ {
+ /* wait for last operation to be completed */
+ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ FLASH->ctrl2_bit.fprgm = TRUE;
+ *(__IO uint8_t*)address = data;
+ /* wait for operation to be completed */
+ status = flash_bank2_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /* disable the fprgm bit */
+ FLASH->ctrl2_bit.fprgm = FALSE;
+ }
+ }
+ /* return the program status */
+ return status;
+}
+
+/**
+ * @brief program a halfword at a specified user system data address.
+ * @param address: specifies the address to be programmed.
+ * @param data: specifies the data to be programmed.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* unlock the user system data */
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+ while(FLASH->ctrl_bit.usdulks==RESET);
+
+ /* enable the user system data programming operation */
+ FLASH->ctrl_bit.usdprgm = TRUE;
+ *(__IO uint16_t*)address = data;
+
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /* disable the usdprgm bit */
+ FLASH->ctrl_bit.usdprgm = FALSE;
+ }
+ /* return the user system data program status */
+ return status;
+}
+
+/**
+ * @brief config erase/program protection for the desired sectors.
+ * @param sector_bits:
+ * the pointer of the address of the sectors to be erase/program protected.
+ * general bit 0~31 every bit is used to protect the 4KB bytes, bit 62~32
+ * every bit is used to protect the 128KB bytes
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_epp_set(uint32_t *sector_bits)
+{
+ uint16_t epp_data[4] = {0xFFFF,0xFFFF,0xFFFF,0xFFFF};
+ flash_status_type status = FLASH_OPERATE_DONE;
+ sector_bits[0] = (uint32_t)(~sector_bits[0]);
+ epp_data[0] = (uint16_t)((sector_bits[0] >> 0) & 0xFF);
+ epp_data[1] = (uint16_t)((sector_bits[0] >> 8) & 0xFF);
+ epp_data[2] = (uint16_t)((sector_bits[0] >> 16) & 0xFF);
+ epp_data[3] = (uint16_t)((sector_bits[0] >> 24) & 0xFF);
+ /* wait for last operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* unlock the user system data */
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+ while(FLASH->ctrl_bit.usdulks==RESET);
+
+ FLASH->ctrl_bit.usdprgm = TRUE;
+ USD->epp0 = epp_data[0];
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ USD->epp1 = epp_data[1];
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ }
+ if(status == FLASH_OPERATE_DONE)
+ {
+ USD->epp2 = epp_data[2];
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ }
+ if(status == FLASH_OPERATE_DONE)
+ {
+ USD->epp3 = epp_data[3];
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ }
+
+ sector_bits[1] = (uint32_t)(~sector_bits[1]);
+ epp_data[0] = (uint16_t)((sector_bits[1] >> 0) & 0xFF);
+ epp_data[1] = (uint16_t)((sector_bits[1] >> 8) & 0xFF);
+ epp_data[2] = (uint16_t)((sector_bits[1] >> 16) & 0xFF);
+ epp_data[3] = (uint16_t)((sector_bits[1] >> 24) & 0xFF);
+ if(status == FLASH_OPERATE_DONE)
+ {
+ USD->epp4 = epp_data[0];
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ }
+ if(status == FLASH_OPERATE_DONE)
+ {
+ USD->epp5 = epp_data[1];
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ }
+ if(status == FLASH_OPERATE_DONE)
+ {
+ USD->epp6 = epp_data[2];
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ }
+ if(status == FLASH_OPERATE_DONE)
+ {
+ USD->epp7 = epp_data[3];
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ }
+
+ /* disable the usdprgm bit */
+ FLASH->ctrl_bit.usdprgm = FALSE;
+ }
+ /* return the erase/program protection operation status */
+ return status;
+}
+
+/**
+ * @brief return the flash erase/program protection status.
+ * @param sector_bits: pointer to get the epps register.
+ * @retval none
+ */
+void flash_epp_status_get(uint32_t *sector_bits)
+{
+ /* return the flash erase/program protection register value */
+ sector_bits[0] = (uint32_t)(FLASH->epps0);
+ sector_bits[1] = (uint32_t)(FLASH->epps1);
+}
+
+/**
+ * @brief enable or disable the flash access protection.
+ * @note if the user has already programmed the other user system data before calling
+ * this function, must re-program them since this function erase all user system data.
+ * @param new_state: new state of the flash access protection.
+ * this parameter can be: TRUE or FALSE.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_fap_enable(confirm_state new_state)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ status = flash_operation_wait_for(ERASE_TIMEOUT);
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* unlock the user system data */
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+ while(FLASH->ctrl_bit.usdulks==RESET);
+
+ FLASH->ctrl_bit.usders = TRUE;
+ FLASH->ctrl_bit.erstr = TRUE;
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(ERASE_TIMEOUT);
+
+ /* disable the usders bit */
+ FLASH->ctrl_bit.usders = FALSE;
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* enable the user system data programming operation */
+ FLASH->ctrl_bit.usdprgm = TRUE;
+
+ /* restore the default eopb0 value */
+ USD->eopb0 = (uint16_t)0x0002;
+
+ /* Wait for operation to be completed */
+ status = flash_operation_wait_for(ERASE_TIMEOUT);
+
+ if(new_state == FALSE)
+ {
+ USD->fap = FAP_RELIEVE_KEY;
+ /* Wait for operation to be completed */
+ status = flash_operation_wait_for(ERASE_TIMEOUT);
+ }
+ /* disable the usdprgm bit */
+ FLASH->ctrl_bit.usdprgm = FALSE;
+ }
+ }
+ /* return the flash access protection operation status */
+ return status;
+}
+
+/**
+ * @brief check the flash access protection status.
+ * @param none
+ * @retval flash access protection status(SET or RESET)
+ */
+flag_status flash_fap_status_get(void)
+{
+ return (flag_status)FLASH->usd_bit.fap;
+}
+
+/**
+ * @brief program the flash system setting byte in usd: wdt_ato_en / depslp_rst / stdby_rst / btopt.
+ * @param usd_ssb: the system setting byte
+ * @note this parameter usd_ssb must contain a combination of all the following 6 types of data
+ * type 1: wdt_ato_en, select the wdt auto start
+ * this data can be one of the following values:
+ * - USD_WDT_ATO_DISABLE: disable wdt auto start
+ * - USD_WDT_ATO_ENABLE: enable wdt auto start
+ * type 2: depslp_rst, reset event when entering deepsleep mode.
+ * this data can be one of the following values:
+ * - USD_DEPSLP_NO_RST: no reset generated when entering in deepsleep
+ * - USD_DEPSLP_RST: reset generated when entering in deepsleep
+ * type 3: stdby_rst, reset event when entering standby mode.
+ * this data can be one of the following values:
+ * - USD_STDBY_NO_RST: no reset generated when entering in standby
+ * - USD_STDBY_RST: reset generated when entering in standby
+ * type 4: btopt, at startup,if boot pins are set in boot from user flash position,selected the device boot from bank1/bank2.
+ * this data can be one of the following values:
+ * - FLASH_BOOT_FROM_BANK1:boot from bank1
+ * - FLASH_BOOT_FROM_BANK2:boot from bank 2 or bank 1
+ * type 5: wdt_depslp, wdt stop/continue count when entering in deepsleep.
+ * this data can be one of the following values:
+ * - USD_WDT_DEPSLP_CONTINUE: wdt continue count
+ * - USD_WDT_DEPSLP_STOP: wdt stop count
+ * type 6: wdt_stdby, wdt stop/continue count when entering in standby.
+ * this data can be one of the following values:
+ * - USD_WDT_STDBY_CONTINUE: wdt continue count
+ * - USD_WDT_STDBY_STOP: wdt stop count
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_ssb_set(uint8_t usd_ssb)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ /* wait for last operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* unlock the user system data */
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+ while(FLASH->ctrl_bit.usdulks==RESET);
+
+ /* enable the user system data programming operation */
+ FLASH->ctrl_bit.usdprgm = TRUE;
+
+ USD->ssb = usd_ssb;
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /* disable the usdprgm bit */
+ FLASH->ctrl_bit.usdprgm = FALSE;
+ }
+ /* return the user system data program status */
+ return status;
+}
+
+/**
+ * @brief return the flash system setting byte status.
+ * @param none
+ * @retval values from flash_usd register: wdt_ato_en(bit0), depslp_rst(bit1),
+ * stdby_rst(bit2) and btopt(bit3).
+ */
+uint8_t flash_ssb_status_get(void)
+{
+ /* return the system setting byte status */
+ return (uint8_t)(FLASH->usd >> 2);
+}
+
+/**
+ * @brief enable or disable the specified flash interrupts.
+ * @param flash_int: specifies the flash interrupt sources to be enabled or disabled.
+ * this parameter can be any combination of the following values:
+ * - FLASH_ERR_INT
+ * - FLASH_ODF_INT
+ * - FLASH_BANK1_ERR_INT
+ * - FLASH_BANK1_ODF_INT
+ * - FLASH_BANK2_ERR_INT
+ * - FLASH_BANK2_ODF_INT
+ * @param new_state: new state of the specified flash interrupts.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state)
+{
+ if(flash_int & FLASH_BANK1_ERR_INT)
+ FLASH->ctrl_bit.errie = new_state;
+ if(flash_int & FLASH_BANK1_ODF_INT)
+ FLASH->ctrl_bit.odfie = new_state;
+ if(flash_int & FLASH_BANK2_ERR_INT)
+ FLASH->ctrl2_bit.errie = new_state;
+ if(flash_int & FLASH_BANK2_ODF_INT)
+ FLASH->ctrl2_bit.odfie = new_state;
+}
+
+/**
+ * @brief enable security library function.
+ * @param pwd: slib password
+ * start_sector: security library start sector
+ * inst_start_sector: security library i-bus area start sector
+ * end_sector: security library end sector
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t inst_start_sector, uint16_t end_sector)
+{
+ uint32_t slib_range;
+ flash_status_type status = FLASH_OPERATE_DONE;
+ /* wait for last operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /*check range param limits*/
+ if((start_sector>=inst_start_sector) || ((inst_start_sector > end_sector) && \
+ (inst_start_sector != 0xFFFF)) || (start_sector > end_sector))
+ return FLASH_PROGRAM_ERROR;
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* unlock slib cfg register */
+ FLASH->slib_unlock = SLIB_UNLOCK_KEY;
+ while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET);
+
+ /* configure slib, set pwd and range */
+ FLASH->slib_set_pwd = pwd;
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ slib_range = ((uint32_t)(end_sector << 16) & FLASH_SLIB_END_SECTOR) | (start_sector & FLASH_SLIB_START_SECTOR);
+ FLASH->slib_set_range0 = slib_range;
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ slib_range = (inst_start_sector & FLASH_SLIB_INST_START_SECTOR) | 0x80000000;
+ FLASH->slib_set_range1 = slib_range;
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ }
+ return status;
+}
+
+/**
+ * @brief disable slib when slib enabled.
+ * @param pwd: slib password
+ * @retval success or error
+ */
+error_status flash_slib_disable(uint32_t pwd)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ /* write password to disable slib */
+ FLASH->slib_pwd_clr = pwd;
+
+ status = flash_operation_wait_for(ERASE_TIMEOUT);
+ if(status == FLASH_OPERATE_DONE)
+ {
+ if(FLASH->slib_misc_sts_bit.slib_pwd_ok)
+ return SUCCESS;
+ else
+ return ERROR;
+ }
+ return ERROR;
+}
+
+/**
+ * @brief get remaining count of slib(range: 256~0).
+ * @param none
+ * @retval uint32_t
+ */
+uint32_t flash_slib_remaining_count_get(void)
+{
+ return (uint32_t)FLASH->slib_misc_sts_bit.slib_rcnt;
+}
+
+/**
+ * @brief get the slib state.
+ * @param none
+ * @retval SET or RESET
+ */
+flag_status flash_slib_state_get(void)
+{
+ if(FLASH->slib_sts0_bit.slib_enf)
+ return SET;
+ else
+ return RESET;
+}
+
+/**
+ * @brief get the start sector of slib.
+ * @param none
+ * @retval uint16_t
+ */
+uint16_t flash_slib_start_sector_get(void)
+{
+ return (uint16_t)FLASH->slib_sts1_bit.slib_ss;
+}
+
+/**
+ * @brief get the instruction start sector of slib.
+ * @param none
+ * @retval uint16_t
+ */
+uint16_t flash_slib_inststart_sector_get(void)
+{
+ return (uint16_t)FLASH->slib_sts2_bit.slib_inst_ss;
+}
+
+/**
+ * @brief get the end sector of slib.
+ * @param none
+ * @retval uint16_t
+ */
+uint16_t flash_slib_end_sector_get(void)
+{
+ return (uint16_t)FLASH->slib_sts1_bit.slib_es;
+}
+
+/**
+ * @brief flash crc calibration in main block.
+ * @param start_sector: crc calibration start sector number
+ * sector_cnt: crc calibration sector count
+ * @retval uint32: crc calibration result
+ */
+uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt)
+{
+ FLASH->crc_ctrl_bit.crc_ss = start_sector;
+ FLASH->crc_ctrl_bit.crc_sn = sector_cnt;
+ FLASH->crc_ctrl_bit.crc_strt = TRUE;
+ flash_operation_wait_for(OPERATION_TIMEOUT);
+ return FLASH->crc_chkr;
+}
+
+/**
+ * @brief flash non-zero wait area boost enable.
+ * @param new_state: new state of the flash non-zero wait area boost operation.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void flash_nzw_boost_enable(confirm_state new_state)
+{
+ FLASH->psr_bit.nzw_bst = new_state;
+}
+
+/**
+ * @brief flash continue read enable.
+ * @param new_state: new state of the flash continue read enable operation.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void flash_continue_read_enable(confirm_state new_state)
+{
+ FLASH->contr_bit.fcontr_en = new_state;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_gpio.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_gpio.c
new file mode 100644
index 0000000..c5121b5
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_gpio.c
@@ -0,0 +1,523 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_gpio.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the gpio firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup GPIO
+ * @brief GPIO driver modules
+ * @{
+ */
+
+#ifdef GPIO_MODULE_ENABLED
+
+/** @defgroup GPIO_private_functions
+ * @{
+ */
+
+/**
+ * @brief reset the gpio register
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @retval none
+ */
+void gpio_reset(gpio_type *gpio_x)
+{
+ if(gpio_x == GPIOA)
+ {
+ crm_periph_reset(CRM_GPIOA_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_GPIOA_PERIPH_RESET, FALSE);
+ }
+ else if(gpio_x == GPIOB)
+ {
+ crm_periph_reset(CRM_GPIOB_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_GPIOB_PERIPH_RESET, FALSE);
+ }
+ else if(gpio_x == GPIOC)
+ {
+ crm_periph_reset(CRM_GPIOC_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_GPIOC_PERIPH_RESET, FALSE);
+ }
+ else if(gpio_x == GPIOD)
+ {
+ crm_periph_reset(CRM_GPIOD_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_GPIOD_PERIPH_RESET, FALSE);
+ }
+ else if(gpio_x == GPIOE)
+ {
+ crm_periph_reset(CRM_GPIOE_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_GPIOE_PERIPH_RESET, FALSE);
+ }
+ else if(gpio_x == GPIOF)
+ {
+ crm_periph_reset(CRM_GPIOF_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_GPIOF_PERIPH_RESET, FALSE);
+ }
+ else if(gpio_x == GPIOG)
+ {
+ crm_periph_reset(CRM_GPIOG_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_GPIOG_PERIPH_RESET, FALSE);
+ }
+ else if(gpio_x == GPIOH)
+ {
+ crm_periph_reset(CRM_GPIOH_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_GPIOH_PERIPH_RESET, FALSE);
+ }
+}
+
+/**
+ * @brief initialize the gpio peripheral.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param gpio_init_struct: pointer to gpio init structure.
+ * @retval none
+ */
+void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct)
+{
+ uint16_t pinx_value, pin_index = 0;
+
+ pinx_value = (uint16_t)gpio_init_struct->gpio_pins;
+
+ while(pinx_value > 0)
+ {
+ if(pinx_value & 0x01)
+ {
+ gpio_x->cfgr &= (uint32_t)~(0x03 << (pin_index * 2));
+ gpio_x->cfgr |= (uint32_t)(gpio_init_struct->gpio_mode << (pin_index * 2));
+
+ gpio_x->omode &= (uint32_t)~(0x01 << (pin_index));
+ gpio_x->omode |= (uint32_t)(gpio_init_struct->gpio_out_type << (pin_index));
+
+ gpio_x->odrvr &= (uint32_t)~(0x03 << (pin_index * 2));
+ gpio_x->odrvr |= (uint32_t)(gpio_init_struct->gpio_drive_strength << (pin_index * 2));
+
+ gpio_x->pull &= (uint32_t)~(0x03 << (pin_index * 2));
+ gpio_x->pull |= (uint32_t)(gpio_init_struct->gpio_pull << (pin_index * 2));
+ }
+ pinx_value >>= 1;
+ pin_index++;
+ }
+}
+
+/**
+ * @brief fill each gpio_init_type member with its default value.
+ * @param gpio_init_struct : pointer to a gpio_init_type structure which will be initialized.
+ * @retval none
+ */
+void gpio_default_para_init(gpio_init_type *gpio_init_struct)
+{
+ /* reset gpio init structure parameters values */
+ gpio_init_struct->gpio_pins = GPIO_PINS_ALL;
+ gpio_init_struct->gpio_mode = GPIO_MODE_INPUT;
+ gpio_init_struct->gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
+ gpio_init_struct->gpio_pull = GPIO_PULL_NONE;
+ gpio_init_struct->gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
+}
+
+/**
+ * @brief read the specified input port pin.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param pins: gpio pin number
+ * this parameter can be one of the following values:
+ * - GPIO_PINS_0
+ * - GPIO_PINS_1
+ * - GPIO_PINS_2
+ * - GPIO_PINS_3
+ * - GPIO_PINS_4
+ * - GPIO_PINS_5
+ * - GPIO_PINS_6
+ * - GPIO_PINS_7
+ * - GPIO_PINS_8
+ * - GPIO_PINS_9
+ * - GPIO_PINS_10
+ * - GPIO_PINS_11
+ * - GPIO_PINS_12
+ * - GPIO_PINS_13
+ * - GPIO_PINS_14
+ * - GPIO_PINS_15
+ * @retval flag_status (SET or RESET)
+ */
+flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins)
+{
+ flag_status status = RESET;
+
+ if(pins != (pins & gpio_x->idt))
+ {
+ status = RESET;
+ }
+ else
+ {
+ status = SET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief read the specified gpio input data port.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @retval gpio input data port value.
+ */
+uint16_t gpio_input_data_read(gpio_type *gpio_x)
+{
+ return ((uint16_t)(gpio_x->idt));
+}
+
+/**
+ * @brief read the specified output port pin.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param pins: gpio pin number
+ * this parameter can be one of the following values:
+ * - GPIO_PINS_0
+ * - GPIO_PINS_1
+ * - GPIO_PINS_2
+ * - GPIO_PINS_3
+ * - GPIO_PINS_4
+ * - GPIO_PINS_5
+ * - GPIO_PINS_6
+ * - GPIO_PINS_7
+ * - GPIO_PINS_8
+ * - GPIO_PINS_9
+ * - GPIO_PINS_10
+ * - GPIO_PINS_11
+ * - GPIO_PINS_12
+ * - GPIO_PINS_13
+ * - GPIO_PINS_14
+ * - GPIO_PINS_15
+ * @retval flag_status (SET or RESET)
+ */
+flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins)
+{
+ flag_status status = RESET;
+
+ if((gpio_x->odt & pins) != RESET)
+ {
+ status = SET;
+ }
+ else
+ {
+ status = RESET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief read the specified gpio ouput data port.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @retval gpio input data port value.
+ */
+uint16_t gpio_output_data_read(gpio_type *gpio_x)
+{
+ return ((uint16_t)(gpio_x->odt));
+}
+
+/**
+ * @brief set the selected data port bits.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param pins: gpio pin number
+ * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
+ * - GPIO_PINS_0
+ * - GPIO_PINS_1
+ * - GPIO_PINS_2
+ * - GPIO_PINS_3
+ * - GPIO_PINS_4
+ * - GPIO_PINS_5
+ * - GPIO_PINS_6
+ * - GPIO_PINS_7
+ * - GPIO_PINS_8
+ * - GPIO_PINS_9
+ * - GPIO_PINS_10
+ * - GPIO_PINS_11
+ * - GPIO_PINS_12
+ * - GPIO_PINS_13
+ * - GPIO_PINS_14
+ * - GPIO_PINS_15
+ * - GPIO_PINS_ALL
+ * @retval none
+ */
+void gpio_bits_set(gpio_type *gpio_x, uint16_t pins)
+{
+ gpio_x->scr = pins;
+}
+
+/**
+ * @brief clear the selected data port bits.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param pins: gpio pin number
+ * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
+ * - GPIO_PINS_0
+ * - GPIO_PINS_1
+ * - GPIO_PINS_2
+ * - GPIO_PINS_3
+ * - GPIO_PINS_4
+ * - GPIO_PINS_5
+ * - GPIO_PINS_6
+ * - GPIO_PINS_7
+ * - GPIO_PINS_8
+ * - GPIO_PINS_9
+ * - GPIO_PINS_10
+ * - GPIO_PINS_11
+ * - GPIO_PINS_12
+ * - GPIO_PINS_13
+ * - GPIO_PINS_14
+ * - GPIO_PINS_15
+ * - GPIO_PINS_ALL
+ * @retval none
+ */
+void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins)
+{
+ gpio_x->clr = pins;
+}
+
+/**
+ * @brief set or clear the selected data port bit.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param pins: gpio pin number
+ * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
+ * - GPIO_PINS_0
+ * - GPIO_PINS_1
+ * - GPIO_PINS_2
+ * - GPIO_PINS_3
+ * - GPIO_PINS_4
+ * - GPIO_PINS_5
+ * - GPIO_PINS_6
+ * - GPIO_PINS_7
+ * - GPIO_PINS_8
+ * - GPIO_PINS_9
+ * - GPIO_PINS_10
+ * - GPIO_PINS_11
+ * - GPIO_PINS_12
+ * - GPIO_PINS_13
+ * - GPIO_PINS_14
+ * - GPIO_PINS_15
+ * - GPIO_PINS_ALL
+ * @param bit_state: specifies the value to be written to the selected bit (TRUE or FALSE).
+ * @retval none
+ */
+void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state)
+{
+ if(bit_state != FALSE)
+ {
+ gpio_x->scr = pins;
+ }
+ else
+ {
+ gpio_x->clr = pins;
+ }
+}
+
+/**
+ * @brief write data to the specified gpio data port.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param port_value: specifies the value to be written to the port output data register.
+ * @retval none
+ */
+void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value)
+{
+ gpio_x->odt = port_value;
+}
+
+/**
+ * @brief write protect gpio pins configuration registers.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param pins: gpio pin number
+ * this parameter can be any combination of the following:
+ * - GPIO_PINS_0
+ * - GPIO_PINS_1
+ * - GPIO_PINS_2
+ * - GPIO_PINS_3
+ * - GPIO_PINS_4
+ * - GPIO_PINS_5
+ * - GPIO_PINS_6
+ * - GPIO_PINS_7
+ * - GPIO_PINS_8
+ * - GPIO_PINS_9
+ * - GPIO_PINS_10
+ * - GPIO_PINS_11
+ * - GPIO_PINS_12
+ * - GPIO_PINS_13
+ * - GPIO_PINS_14
+ * - GPIO_PINS_15
+ * - GPIO_PINS_ALL
+ * @retval none
+ */
+void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins)
+{
+ uint32_t temp = 0x00010000;
+
+ temp |= pins;
+ /* set wpen bit */
+ gpio_x->wpr = temp;
+ /* reset wpen bit */
+ gpio_x->wpr = pins;
+ /* set wpen bit */
+ gpio_x->wpr = temp;
+ /* read wpen bit*/
+ temp = gpio_x->wpr;
+ /* read wpen bit*/
+ temp = gpio_x->wpr;
+}
+
+/**
+ * @brief enable or disable gpio pins huge driven.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param pins: gpio pin number
+ * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
+ * - GPIO_PINS_0
+ * - GPIO_PINS_1
+ * - GPIO_PINS_2
+ * - GPIO_PINS_3
+ * - GPIO_PINS_4
+ * - GPIO_PINS_5
+ * - GPIO_PINS_6
+ * - GPIO_PINS_7
+ * - GPIO_PINS_8
+ * - GPIO_PINS_9
+ * - GPIO_PINS_10
+ * - GPIO_PINS_11
+ * - GPIO_PINS_12
+ * - GPIO_PINS_13
+ * - GPIO_PINS_14
+ * - GPIO_PINS_15
+ * - GPIO_PINS_ALL
+ * @param new_state: new state of the slew rate.
+ * this parameter can be: true or false.
+ * @retval none
+ */
+void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ gpio_x->hdrv |= pins;
+ }
+ else
+ {
+ gpio_x->hdrv &= ~pins;
+ }
+}
+
+/**
+ * @brief configure the pin's muxing function.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param gpio_pin_source: specifies the pin for the muxing function.
+ * this parameter can be one of the following values:
+ * - GPIO_PINS_SOURCE0
+ * - GPIO_PINS_SOURCE1
+ * - GPIO_PINS_SOURCE2
+ * - GPIO_PINS_SOURCE3
+ * - GPIO_PINS_SOURCE4
+ * - GPIO_PINS_SOURCE5
+ * - GPIO_PINS_SOURCE6
+ * - GPIO_PINS_SOURCE7
+ * - GPIO_PINS_SOURCE8
+ * - GPIO_PINS_SOURCE9
+ * - GPIO_PINS_SOURCE10
+ * - GPIO_PINS_SOURCE11
+ * - GPIO_PINS_SOURCE12
+ * - GPIO_PINS_SOURCE13
+ * - GPIO_PINS_SOURCE14
+ * - GPIO_PINS_SOURCE15
+ * @param gpio_mux: select the pin to used as muxing function.
+ * this parameter can be one of the following values:
+ * - GPIO_MUX_0
+ * - GPIO_MUX_1
+ * - GPIO_MUX_2
+ * - GPIO_MUX_3
+ * - GPIO_MUX_4
+ * - GPIO_MUX_5
+ * - GPIO_MUX_6
+ * - GPIO_MUX_7
+ * - GPIO_MUX_8
+ * - GPIO_MUX_9
+ * - GPIO_MUX_10
+ * - GPIO_MUX_11
+ * - GPIO_MUX_12
+ * - GPIO_MUX_13
+ * - GPIO_MUX_14
+ * - GPIO_MUX_15
+ * @retval none
+ */
+void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux)
+{
+ uint32_t temp = 0x00;
+ uint32_t temp_2 = 0x00;
+
+ temp = ((uint32_t)(gpio_mux) << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
+ if(gpio_pin_source >> 0x03)
+ {
+ gpio_x->muxh &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
+ temp_2 = gpio_x->muxh | temp;
+ gpio_x->muxh = temp_2;
+ }
+ else
+ {
+ gpio_x->muxl &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
+ temp_2 = gpio_x->muxl | temp;
+ gpio_x->muxl = temp_2;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_i2c.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_i2c.c
new file mode 100644
index 0000000..0b9e8b3
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_i2c.c
@@ -0,0 +1,767 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_i2c.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the i2c firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup I2C
+ * @brief I2C driver modules
+ * @{
+ */
+
+#ifdef I2C_MODULE_ENABLED
+
+/** @defgroup I2C_private_functions
+ * @{
+ */
+
+/**
+ * @brief reset the i2c register
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @retval none
+ */
+void i2c_reset(i2c_type *i2c_x)
+{
+ if(i2c_x == I2C1)
+ {
+ crm_periph_reset(CRM_I2C1_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_I2C1_PERIPH_RESET, FALSE);
+ }
+ else if(i2c_x == I2C2)
+ {
+ crm_periph_reset(CRM_I2C2_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_I2C2_PERIPH_RESET, FALSE);
+ }
+ else if(i2c_x == I2C3)
+ {
+ crm_periph_reset(CRM_I2C3_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_I2C3_PERIPH_RESET, FALSE);
+ }
+}
+
+/**
+ * @brief init i2c digit filters and clock control register.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param dfilters: number of digit filters (0x00~0x0F).
+ * @param clk: i2c clock control register (0x00000000~0xFFFFFFFF).
+ * @retval none
+ */
+void i2c_init(i2c_type *i2c_x, uint8_t dfilters, uint32_t clk)
+{
+ /* disable i2c peripheral */
+ i2c_x->ctrl1_bit.i2cen = FALSE;
+
+ /* write clkctrl register*/
+ i2c_x->clkctrl = clk;
+
+ /* write digital filter register*/
+ i2c_x->ctrl1_bit.dflt = dfilters;
+}
+
+/**
+ * @brief config i2c own address 1.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param mode: i2c address mode.
+ * this parameter can be one of the following values:
+ * - I2C_ADDRESS_MODE_7BIT: 7bit address.
+ * - I2C_ADDRESS_MODE_10BIT: 10bit address.
+ * @param address: own address 1, such as 0xB0.
+ * @retval none
+ */
+void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address)
+{
+ /* config address mode */
+ i2c_x->oaddr1_bit.addr1mode = mode;
+
+ /* config address */
+ i2c_x->oaddr1_bit.addr1 = address & 0x03FF;
+
+ /* enable address */
+ i2c_x->oaddr1_bit.addr1en = TRUE;
+}
+
+/**
+ * @brief config i2c own address 2 and mask.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param address: own address 1, such as 0xC0.
+ * @param mask: own address 2 mask.
+ * this parameter can be one of the following values:
+ * - I2C_ADDR2_NOMASK: compare bit [7:1].
+ * - I2C_ADDR2_MASK01: only compare bit [7:2].
+ * - I2C_ADDR2_MASK02: only compare bit [7:2].
+ * - I2C_ADDR2_MASK03: only compare bit [7:3].
+ * - I2C_ADDR2_MASK04: only compare bit [7:4].
+ * - I2C_ADDR2_MASK05: only compare bit [7:5].
+ * - I2C_ADDR2_MASK06: only compare bit [7:6].
+ * - I2C_ADDR2_MASK07: only compare bit [7].
+ * @retval none
+ */
+void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask)
+{
+ i2c_x->oaddr2_bit.addr2mask = mask;
+
+ i2c_x->oaddr2_bit.addr2 = (address >> 1) & 0x7F;
+}
+
+/**
+ * @brief enable or disable own address 2.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->oaddr2_bit.addr2en = new_state;
+}
+
+/**
+ * @brief enable or disable smbus mode.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param mode: smbus device mode.
+ * this parameter can be one of the following values:
+ * - I2C_SMBUS_MODE_DEVICE: smbus device.
+ * - I2C_SMBUS_MODE_HOST: smbus host.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_smbus_enable(i2c_type *i2c_x, i2c_smbus_mode_type mode, confirm_state new_state)
+{
+ switch (mode)
+ {
+ case I2C_SMBUS_MODE_DEVICE:
+ i2c_x->ctrl1_bit.devaddren = new_state;
+ break;
+ case I2C_SMBUS_MODE_HOST:
+ i2c_x->ctrl1_bit.haddren = new_state;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief enable or disable peripheral.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl1_bit.i2cen = new_state;
+}
+
+/**
+ * @brief enable or disable clock stretch.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl1_bit.stretch = (!new_state);
+}
+
+/**
+ * @brief enable or disable ack.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl2_bit.nacken = (!new_state);
+}
+
+/**
+ * @brief enable or disable 10-bit address mode (master transfer).
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_addr10_mode_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl2_bit.addr10 = new_state;
+}
+
+/**
+ * @brief config the slave address to be transmitted.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param address: slave address.
+ * @retval none
+ */
+void i2c_transfer_addr_set(i2c_type *i2c_x, uint16_t address)
+{
+ i2c_x->ctrl2_bit.saddr = address & 0x03FF;
+}
+
+/**
+ * @brief get the slave address to be transmitted.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @retval slave address
+ */
+uint16_t i2c_transfer_addr_get(i2c_type *i2c_x)
+{
+ return i2c_x->ctrl2_bit.saddr;
+}
+
+/**
+ * @brief config the master transfer direction.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param i2c_direction: transfer request direction.
+ * this parameter can be one of the following values:
+ * - I2C_DIR_TRANSMIT: master request a write transfer.
+ * - I2C_DIR_RECEIVE: master request a read transfer.
+ * @retval none
+ */
+void i2c_transfer_dir_set(i2c_type *i2c_x, i2c_transfer_dir_type i2c_direction)
+{
+ i2c_x->ctrl2_bit.dir = i2c_direction;
+}
+
+/**
+ * @brief get the i2c slave received direction.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @retval the value of the received direction.
+ */
+i2c_transfer_dir_type i2c_transfer_dir_get(i2c_type *i2c_x)
+{
+ if (i2c_x->sts_bit.sdir == 0)
+ {
+ return I2C_DIR_TRANSMIT;
+ }
+ else
+ {
+ return I2C_DIR_RECEIVE;
+ }
+}
+
+/**
+ * @brief get the i2c slave matched address.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @retval slave matched address.
+ */
+uint8_t i2c_matched_addr_get(i2c_type *i2c_x)
+{
+ return i2c_x->sts_bit.addr;
+}
+
+/**
+ * @brief enable or disable auto send stop mode.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_auto_stop_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl2_bit.astopen = new_state;
+}
+
+/**
+ * @brief enable or disable cnt reload mode.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_reload_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl2_bit.rlden = new_state;
+}
+
+/**
+ * @brief config the transfer cnt .
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param cnt: transfer cnt.
+ * @retval none
+ */
+void i2c_cnt_set(i2c_type *i2c_x, uint8_t cnt)
+{
+ i2c_x->ctrl2_bit.cnt = cnt;
+}
+
+/**
+ * @brief enable or disable read 10-bit header, this mode
+ * only used in 10-bit address mode read.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_addr10_header_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl2_bit.readh10 = new_state;
+}
+
+/**
+ * @brief enable or disable general call mode.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl1_bit.gcaen = new_state;
+}
+
+/**
+ * @brief drives the smbus alert pin high or low.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param level
+ * this parameter can be one of the following values:
+ * - I2C_SMBUS_ALERT_LOW: smbus alert set low.
+ * - I2C_SMBUS_ALERT_HIGH: smbus alert set high.
+ * @retval none
+ */
+void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level)
+{
+ i2c_x->ctrl1_bit.smbalert = level;
+}
+
+/**
+ * @brief enable or disable slave data control.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_slave_data_ctrl_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl1_bit.sctrl = new_state;
+}
+
+/**
+ * @brief enable or disable pec calculate.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl1_bit.pecen = new_state;
+}
+
+/**
+ * @brief enable or disable pec transfer.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl2_bit.pecten = new_state;
+}
+
+/**
+ * @brief get the i2c pec value.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @retval the value of the pec.
+ */
+uint8_t i2c_pec_value_get(i2c_type *i2c_x)
+{
+ return (uint8_t)(i2c_x->pec_bit.pecval);
+}
+
+/**
+ * @brief config the i2c bus timeout.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param timeout: timeout (0x0000~0x0FFF).
+ * @retval none
+ */
+void i2c_timeout_set(i2c_type *i2c_x, uint16_t timeout)
+{
+ i2c_x->timeout_bit.totime = timeout;
+}
+
+/**
+ * @brief config the bus timeout detcet level.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param level
+ * this parameter can be one of the following values:
+ * - I2C_TIMEOUT_DETCET_HIGH: detect high level timeout.
+ * - I2C_TIMEOUT_DETCET_LOW: detect low level timeout.
+ * @retval none
+ */
+void i2c_timeout_detcet_set(i2c_type *i2c_x, i2c_timeout_detcet_type mode)
+{
+ i2c_x->timeout_bit.tomode = mode;
+}
+
+/**
+ * @brief enable or disable bus timeout.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_timeout_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->timeout_bit.toen = new_state;
+}
+
+/**
+ * @brief config the i2c extend bus timeout.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param timeout: extend timeout (0x0000~0x0FFF).
+ * @retval none
+ */
+void i2c_ext_timeout_set(i2c_type *i2c_x, uint16_t timeout)
+{
+ i2c_x->timeout_bit.exttime = timeout;
+}
+
+/**
+ * @brief enable or disable extend bus timeout.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_ext_timeout_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->timeout_bit.exten = new_state;
+}
+
+/**
+ * @brief enable or disable interrupts.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param i2c_int: interrupts sources.
+ * this parameter can be one of the following values:
+ * - I2C_TD_INT: transmit data interrupt.
+ * - I2C_RD_INT: receive data interrupt.
+ * - I2C_ADDR_INT: address match interrupt.
+ * - I2C_ACKFIAL_INT: ack fail interrupt.
+ * - I2C_STOP_INT: stop detect interrupt.
+ * - I2C_TDC_INT: transmit data complete interrupt.
+ * - I2C_ERR_INT: bus error interrupt.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_interrupt_enable(i2c_type *i2c_x, uint32_t source, confirm_state new_state)
+{
+ if (new_state != FALSE)
+ {
+ i2c_x->ctrl1 |= source;
+ }
+ else
+ {
+ i2c_x->ctrl1 &= (uint32_t)~source;
+ }
+}
+
+/**
+ * @brief get interrupt status
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param source
+ * this parameter can be one of the following values:
+ * - I2C_TD_INT: transmit data interrupt.
+ * - I2C_RD_INT: receive data interrupt.
+ * - I2C_ADDR_INT: address match interrupt.
+ * - I2C_ACKFIAL_INT: ack fail interrupt.
+ * - I2C_STOP_INT: stop detect interrupt.
+ * - I2C_TDC_INT: transmit data complete interrupt.
+ * - I2C_ERR_INT: bus error interrupt.
+ * @retval flag_status (SET or RESET)
+ */
+flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source)
+{
+ if((i2c_x->ctrl1 & source) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief enable or disable dma requests.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param dma_req: dma transfer request.
+ * this parameter can be one of the following values:
+ * - I2C_DMA_REQUEST_TX: dma transmit request.
+ * - I2C_DMA_REQUEST_RX: dma receive request.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state new_state)
+{
+ if(dma_req == I2C_DMA_REQUEST_TX)
+ {
+ i2c_x->ctrl1_bit.dmaten = new_state;
+ }
+ else
+ {
+ i2c_x->ctrl1_bit.dmaren = new_state;
+ }
+}
+
+/**
+ * @brief config data transfer.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param address: slave address.
+ * @param cnt: transfer conuter(0~255)
+ * @param rld_stop: config reload and gen stop condition mode.
+ * this parameter can be one of the following values:
+ * - I2C_AUTO_STOP_MODE: auto generate stop mode.
+ * - I2C_SOFT_STOP_MODE: soft generate stop mode.
+ * - I2C_RELOAD_MODE: reload mode.
+ * @param start_stop: config gen start condition mode.
+ * this parameter can be one of the following values:
+ * - I2C_WITHOUT_START: transfer data without start condition.
+ * - I2C_GEN_START_READ: read data and generate start.
+ * - I2C_GEN_START_WRITE: send data and generate start.
+ * @retval none
+ */
+void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_stop_mode_type start_stop)
+{
+ /* clear ctrl2_bit specific bits */
+ i2c_x->ctrl2 &= ~0x03FF67FF;
+
+ /* config reload and stop mode */
+ switch (rld_stop)
+ {
+ case I2C_RELOAD_MODE:
+ i2c_x->ctrl2_bit.rlden = TRUE;
+ break;
+ case I2C_AUTO_STOP_MODE:
+ i2c_x->ctrl2_bit.astopen = TRUE;
+ break;
+ case I2C_SOFT_STOP_MODE:
+ break;
+ default:
+ break;
+ }
+
+ /* config saddr and cnt */
+ i2c_x->ctrl2_bit.saddr = address;
+ i2c_x->ctrl2_bit.cnt = cnt;
+
+ /* config generate start mode */
+ switch (start_stop)
+ {
+ case I2C_GEN_START_READ:
+ i2c_x->ctrl2_bit.dir = TRUE;
+ i2c_x->ctrl2_bit.genstart = TRUE;
+ break;
+ case I2C_GEN_START_WRITE:
+ i2c_x->ctrl2_bit.genstart = TRUE;
+ break;
+ case I2C_WITHOUT_START:
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief generate start condition.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @retval none
+ */
+void i2c_start_generate(i2c_type *i2c_x)
+{
+ i2c_x->ctrl2_bit.genstart = TRUE;
+}
+
+/**
+ * @brief generate stop condition.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @retval none
+ */
+void i2c_stop_generate(i2c_type *i2c_x)
+{
+ i2c_x->ctrl2_bit.genstop = TRUE;
+}
+
+/**
+ * @brief send a byte through the i2c periph.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param data: byte to be transmitted.
+ * @retval none
+ */
+void i2c_data_send(i2c_type *i2c_x, uint8_t data)
+{
+ i2c_x->txdt = data;
+}
+
+/**
+ * @brief receive a byte through the i2c periph.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @retval the value of the received data.
+ */
+uint8_t i2c_data_receive(i2c_type *i2c_x)
+{
+ return (uint8_t)i2c_x->rxdt;
+}
+
+/**
+ * @brief get flag status.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - I2C_TDBE_FLAG: transmit data buffer empty flag.
+ * - I2C_TDIS_FLAG: send interrupt status.
+ * - I2C_RDBF_FLAG: receive data buffer full flag.
+ * - I2C_ADDRF_FLAG: 0~7 bit address match flag.
+ * - I2C_ACKFAIL_FLAG: acknowledge failure flag.
+ * - I2C_STOPF_FLAG: stop condition generation complete flag.
+ * - I2C_TDC_FLAG: transmit data complete flag.
+ * - I2C_TCRLD_FLAG: transmission is complete, waiting to load data.
+ * - I2C_BUSERR_FLAG: bus error flag.
+ * - I2C_ARLOST_FLAG: arbitration lost flag.
+ * - I2C_OUF_FLAG: overflow or underflow flag.
+ * - I2C_PECERR_FLAG: pec receive error flag.
+ * - I2C_TMOUT_FLAG: smbus timeout flag.
+ * - I2C_ALERTF_FLAG: smbus alert flag.
+ * - I2C_BUSYF_FLAG: bus busy flag transmission mode.
+ * - I2C_SDIR_FLAG: slave data transmit direction.
+ * @retval the new state of flag (SET or RESET).
+ */
+flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag)
+{
+ if((i2c_x->sts & flag) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief clear flag status
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param flag: specifies the flag to clear.
+ * this parameter can be any combination of the following values:
+ * - I2C_ADDRF_FLAG: 0~7 bit address match flag.
+ * - I2C_ACKFAIL_FLAG: acknowledge failure flag.
+ * - I2C_STOPF_FLAG: stop condition generation complete flag.
+ * - I2C_BUSERR_FLAG: bus error flag.
+ * - I2C_ARLOST_FLAG: arbitration lost flag.
+ * - I2C_OUF_FLAG: overflow or underflow flag.
+ * - I2C_PECERR_FLAG: pec receive error flag.
+ * - I2C_TMOUT_FLAG: smbus timeout flag.
+ * - I2C_ALERTF_FLAG: smbus alert flag.
+ * @retval none
+ */
+void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag)
+{
+ i2c_x->clr = flag;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_misc.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_misc.c
new file mode 100644
index 0000000..b5d6ebc
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_misc.c
@@ -0,0 +1,173 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_misc.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the misc firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup MISC
+ * @brief MISC driver modules
+ * @{
+ */
+
+#ifdef MISC_MODULE_ENABLED
+
+/** @defgroup MISC_private_functions
+ * @{
+ */
+
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
+
+/**
+ * @brief system reset
+ * @param none
+ * @retval none
+ */
+void nvic_system_reset(void)
+{
+ NVIC_SystemReset();
+}
+
+/**
+ * @brief enable nvic irq
+ * @param irqn (IRQn_Type number)
+ * @param preempt_priority: preemptive priority value (starting from 0)
+ * @param sub_priority: subpriority value (starting from 0)
+ * @retval none
+ */
+void nvic_irq_enable(uint32_t irqn, uint32_t preempt_priority, uint32_t sub_priority)
+{
+ uint32_t temp_priority = 0;
+
+ /* encode priority */
+ temp_priority = NVIC_EncodePriority(NVIC_GetPriorityGrouping(), preempt_priority, sub_priority);
+ /* set priority */
+ NVIC_SetPriority((IRQn_Type)irqn, temp_priority);
+ /* enable irqn */
+ NVIC_EnableIRQ((IRQn_Type)irqn);
+}
+
+/**
+ * @brief disable nvic irq number
+ * @param irqn (IRQn_Type number)
+ * @retval none
+ */
+void nvic_irq_disable(uint32_t irqn)
+{
+ NVIC_DisableIRQ((IRQn_Type)irqn);
+}
+
+/**
+ * @brief config nvic priority group
+ * @param priority_group
+ * this parameter can be one of the following values:
+ * - NVIC_PRIORITY_GROUP_0
+ * - NVIC_PRIORITY_GROUP_1
+ * - NVIC_PRIORITY_GROUP_2
+ * - NVIC_PRIORITY_GROUP_3
+ * - NVIC_PRIORITY_GROUP_4
+ * @retval none
+ */
+void nvic_priority_group_config(nvic_priority_group_type priority_group)
+{
+ /* set the prigroup[10:8] bits according to nvic_prioritygroup value */
+ NVIC_SetPriorityGrouping(priority_group);
+}
+
+/**
+ * @brief set the vector table location and offset.
+ * @param base
+ * this parameter can be one of the following values:
+ * - NVIC_VECTTAB_RAM
+ * - NVIC_VECTTAB_FLASH
+ * @param offset (vector table base offset field. this value must be a multiple of 0x200)
+ * @retval none
+ */
+void nvic_vector_table_set(uint32_t base, uint32_t offset)
+{
+ SCB->VTOR = base | (offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+ * @brief config nvic lowpower mode
+ * @param lp_mode
+ * this parameter can be one of the following values:
+ * - NVIC_LP_SEVONPEND
+ * - NVIC_LP_SLEEPDEEP
+ * - NVIC_LP_SLEEPONEXIT
+ * @param new_state (new state of lp condition. ENABLE or DISABLE)
+ * @retval none
+ */
+void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ SCB->SCR |= lp_mode;
+ }
+ else
+ {
+ SCB->SCR &= (uint32_t)(~(uint32_t)lp_mode);
+ }
+}
+
+/**
+ * @brief config systick clock source
+ * @param source
+ * this parameter can be one of the following values:
+ * - SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8
+ * - SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV
+ * @retval none
+ */
+void systick_clock_source_config(systick_clock_source_type source)
+{
+ if(source == SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV)
+ {
+ SysTick->CTRL |= SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV;
+ }
+ else
+ {
+ SysTick->CTRL &= ~(uint32_t)SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_pwc.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_pwc.c
new file mode 100644
index 0000000..e62f6a4
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_pwc.c
@@ -0,0 +1,247 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_pwc.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the pwc firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup PWC
+ * @brief PWC driver modules
+ * @{
+ */
+
+#ifdef PWC_MODULE_ENABLED
+
+/** @defgroup PWC_private_functions
+ * @{
+ */
+
+/**
+ * @brief deinitialize the pwc peripheral registers to their default reset values.
+ * @param none
+ * @retval none
+ */
+void pwc_reset(void)
+{
+ crm_periph_reset(CRM_PWC_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_PWC_PERIPH_RESET, FALSE);
+}
+
+/**
+ * @brief enable or disable access to the battery powered domain.
+ * @param new_state: new state of battery powered domain access.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void pwc_battery_powered_domain_access(confirm_state new_state)
+{
+ PWC->ctrl_bit.bpwen= new_state;
+}
+
+/**
+ * @brief select the voltage threshold detected by the power voltage detector.
+ * @param pvm_voltage: select pwc pvm voltage
+ * this parameter can be one of the following values:
+ * - PWC_PVM_VOLTAGE_2V3
+ * - PWC_PVM_VOLTAGE_2V4
+ * - PWC_PVM_VOLTAGE_2V5
+ * - PWC_PVM_VOLTAGE_2V6
+ * - PWC_PVM_VOLTAGE_2V7
+ * - PWC_PVM_VOLTAGE_2V8
+ * - PWC_PVM_VOLTAGE_2V9
+ * @retval none
+ */
+void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage)
+{
+ PWC->ctrl_bit.pvmsel= pvm_voltage;
+}
+
+/**
+ * @brief enable or disable pwc power voltage monitor (pvm)
+ * @param new_state: new state of pvm.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void pwc_power_voltage_monitor_enable(confirm_state new_state)
+{
+ PWC->ctrl_bit.pvmen= new_state;
+}
+
+/**
+ * @brief enable or disable pwc standby wakeup pin
+ * @param pin_num: choose the wakeup pin.
+ * this parameter can be be any combination of the following values:
+ * - PWC_WAKEUP_PIN_1
+ * - PWC_WAKEUP_PIN_2
+ * @param new_state: new state of the standby wakeup pin.
+ * this parameter can be one of the following values:
+ * - TRUE
+ * - FALSE
+ * @retval none
+ */
+void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ {
+ PWC->ctrlsts |= pin_num;
+ }
+ else
+ {
+ PWC->ctrlsts &= ~pin_num;
+ }
+}
+
+/**
+ * @brief clear flag of pwc
+ * @param pwc_flag: select the pwc flag.
+ * this parameter can be any combination of the following values:
+ * - PWC_WAKEUP_FLAG
+ * - PWC_STANDBY_FLAG
+ * - note:"PWC_PVM_OUTPUT_FLAG" cannot be choose!this bit is readonly bit,it means the voltage monitoring output state
+ * @retval none
+ */
+void pwc_flag_clear(uint32_t pwc_flag)
+{
+ if(pwc_flag == PWC_STANDBY_FLAG)
+ PWC->ctrl_bit.clsef = TRUE;
+ if(pwc_flag == PWC_WAKEUP_FLAG)
+ PWC->ctrl_bit.clswef = TRUE;
+}
+
+/**
+ * @brief get flag of pwc
+ * @param pwc_flag: select the pwc flag.
+ * this parameter can be one of the following values:
+ * - PWC_WAKEUP_FLAG
+ * - PWC_STANDBY_FLAG
+ * - PWC_PVM_OUTPUT_FLAG
+ * @retval state of select flag(SET or RESET).
+ */
+flag_status pwc_flag_get(uint32_t pwc_flag)
+{
+ flag_status status = RESET;
+ if ((PWC->ctrlsts & pwc_flag) == RESET)
+ {
+ status = RESET;
+ }
+ else
+ {
+ status = SET;
+ }
+ return status;
+}
+
+/**
+ * @brief enter pwc sleep mode
+ * @param sleep_mode_enter: choose the instruction to enter sleep mode.
+ * this parameter can be one of the following values:
+ * - PWC_SLEEP_ENTER_WFI
+ * - PWC_SLEEP_ENTER_WFE
+ * @retval none
+ */
+void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter)
+{
+ SCB->SCR &= (uint32_t)~0x4;
+ if(pwc_sleep_enter == PWC_SLEEP_ENTER_WFE)
+ {
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+ else if(pwc_sleep_enter == PWC_SLEEP_ENTER_WFI)
+ {
+ __WFI();
+ }
+}
+
+/**
+ * @brief enter pwc deep-sleep mode
+ * @param pwc_deep_sleep_enter: choose the instruction to enter deep sleep mode.
+ * this parameter can be one of the following values:
+ * - PWC_DEEP_SLEEP_ENTER_WFI
+ * - PWC_DEEP_SLEEP_ENTER_WFE
+ * @retval none
+ */
+void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter)
+{
+ SCB->SCR |= 0x04;
+ if(pwc_deep_sleep_enter == PWC_DEEP_SLEEP_ENTER_WFE)
+ {
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+ else if(pwc_deep_sleep_enter == PWC_DEEP_SLEEP_ENTER_WFI)
+ {
+ __WFI();
+ }
+ SCB->SCR &= (uint32_t)~0x4;
+}
+
+/**
+ * @brief regulate low power consumption in the deep sleep mode
+ * @param pwc_regulator: set the regulator state.
+ * this parameter can be one of the following values:
+ * - PWC_REGULATOR_ON
+ * - PWC_REGULATOR_LOW_POWER
+ * @retval none
+ */
+void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator)
+{
+ PWC->ctrl_bit.vrsel = pwc_regulator;
+}
+
+/**
+ * @brief enter pwc standby mode
+ * @param none
+ * @retval none
+ */
+void pwc_standby_mode_enter(void)
+{
+ PWC->ctrl_bit.clswef = FALSE;
+ PWC->ctrl_bit.lpsel = TRUE;
+ SCB->SCR |= 0x04;
+#if defined (__CC_ARM)
+ __force_stores();
+#endif
+ __WFI();
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_qspi.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_qspi.c
new file mode 100644
index 0000000..aab25e0
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_qspi.c
@@ -0,0 +1,420 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_qspi.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contain all the functions for qspi firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup QSPI
+ * @brief QSPI driver modules
+ * @{
+ */
+
+#ifdef QSPI_MODULE_ENABLED
+
+/** @defgroup QSPI_private_functions
+ * @{
+ */
+
+/**
+ * @brief enable/disable encryption for qspi.
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1,QSPI2.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state)
+{
+ qspi_x->ctrl_bit.keyen = new_state;
+}
+
+/**
+ * @brief set qspi sck mode.
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1,QSPI2.
+ * @param new_mode: new state to be set
+ * this parameter can be one of the following values:
+ * - QSPI_SCK_MODE_0
+ * - QSPI_SCK_MODE_3
+ * @retval none
+ */
+void qspi_sck_mode_set( qspi_type* qspi_x, qspi_clk_mode_type new_mode)
+{
+ qspi_x->ctrl_bit.sckmode = new_mode;
+}
+
+/**
+ * @brief set qspi clock division
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1,QSPI2.
+ * @param new_clkdiv: new division value
+ * this parameter can be one of the following values:
+ * - QSPI_CLK_DIV_2
+ * - QSPI_CLK_DIV_4
+ * - QSPI_CLK_DIV_6
+ * - QSPI_CLK_DIV_8
+ * - QSPI_CLK_DIV_3
+ * - QSPI_CLK_DIV_5
+ * - QSPI_CLK_DIV_10
+ * - QSPI_CLK_DIV_12
+ * @retval none
+ */
+void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv)
+{
+ qspi_x->ctrl_bit.clkdiv = new_clkdiv;
+}
+
+/**
+ * @brief enable/disable cache in xip mode
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1,QSPI2.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state)
+{
+ qspi_x->xip_cmd_w3_bit.bypassc = new_state;
+}
+
+/**
+ * @brief enable/disable interrupt when command is completed
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1,QSPI2.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state)
+{
+ qspi_x->ctrl2_bit.cmdie = new_state;
+}
+
+/**
+ * @brief get status flags.
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1,QSPI2.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - QSPI_RXFIFORDY_FLAG
+ * - QSPI_TXFIFORDY_FLAG
+ * - QSPI_CMDSTS_FLAG
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag)
+{
+ flag_status bit_status = RESET;
+ switch(flag)
+ {
+ case QSPI_RXFIFORDY_FLAG:
+ bit_status = (flag_status)qspi_x->fifosts_bit.rxfifordy;
+ break;
+ case QSPI_TXFIFORDY_FLAG:
+ bit_status = (flag_status)qspi_x->fifosts_bit.txfifordy;
+ break;
+ case QSPI_CMDSTS_FLAG:
+ bit_status = (flag_status)qspi_x->cmdsts_bit.cmdsts;
+ break;
+ default:
+ break;
+ }
+ return bit_status;
+}
+
+/**
+ * @brief clear flags
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1,QSPI2.
+ * @param flag: flags to be clear
+ * this parameter can be one of the following values:
+ * - QSPI_CMDSTS_FLAG
+ * @retval none
+ */
+void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag)
+{
+ qspi_x->cmdsts = QSPI_CMDSTS_FLAG;
+}
+
+/**
+ * @brief set dma threshold for dma rx
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1,QSPI2.
+ * @param new_threshold: value to set
+ * this parameter can be one of the following values:
+ * - QSPI_DMA_FIFO_THOD_WORD08
+ * - QSPI_DMA_FIFO_THOD_WORD16
+ * - QSPI_DMA_FIFO_THOD_WORD32
+ * @retval none
+ */
+void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold)
+{
+ qspi_x->ctrl2_bit.rxfifo_thod = new_threshold;
+}
+
+/**
+ * @brief set dma threshold for dma tx
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1,QSPI2.
+ * @param new_threshold: value to set
+ * this parameter can be one of the following values:
+ * - QSPI_DMA_FIFO_THOD_WORD08
+ * - QSPI_DMA_FIFO_THOD_WORD16
+ * - QSPI_DMA_FIFO_THOD_WORD32
+ * @retval none
+ */
+void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold)
+{
+ qspi_x->ctrl2_bit.txfifo_thod = new_threshold;
+}
+
+/**
+ * @brief enable/disable dma transfer
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1,QSPI2.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state)
+{
+ qspi_x->ctrl2_bit.dmaen = new_state;
+}
+
+/**
+ * @brief set wip position in status register of flash
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1,QSPI2.
+ * @param busy_pos: value to set
+ * this parameter can be one of the following values:
+ * - QSPI_BUSY_OFFSET_0
+ * - QSPI_BUSY_OFFSET_1
+ * - QSPI_BUSY_OFFSET_2
+ * - QSPI_BUSY_OFFSET_3
+ * - QSPI_BUSY_OFFSET_4
+ * - QSPI_BUSY_OFFSET_5
+ * - QSPI_BUSY_OFFSET_6
+ * - QSPI_BUSY_OFFSET_7
+ * @retval none
+ */
+void qspi_busy_config(qspi_type* qspi_x, qspi_busy_pos_type busy_pos)
+{
+ qspi_x->ctrl_bit.busy = busy_pos;
+}
+
+/**
+ * @brief enable xip mode or command-port mode.
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1,QSPI2.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state)
+{
+ /* skip if state is no change */
+ if(new_state == (confirm_state)(qspi_x->ctrl_bit.xipsel))
+ {
+ return;
+ }
+
+ /* flush and reset qspi state */
+ qspi_x->ctrl_bit.xiprcmdf = 1;
+
+ /* wait until action is finished */
+ while(qspi_x->ctrl_bit.abort);
+
+ /* set xip mode to new state */
+ qspi_x->ctrl_bit.xipsel = new_state;
+
+ /* wait until abort is not set */
+ while(qspi_x->ctrl_bit.abort);
+}
+
+/**
+ * @brief set command-port and qspi_x will start to work
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1,QSPI2.
+ * @param qspi_cmd_struct: pointer to qspi cmd structure
+ * @retval none
+ */
+void qspi_cmd_operation_kick(qspi_type* qspi_x, qspi_cmd_type* qspi_cmd_struct)
+{
+ uint32_t w1_val = 0, w3_val = 0;
+
+ /* config analyse cmd_w0 register */
+ qspi_x->cmd_w0 = (uint32_t)qspi_cmd_struct->address_code;
+
+ /* config analyse cmd_w1 register */
+ w1_val = (uint32_t)qspi_cmd_struct->address_length;
+ w1_val |= (uint32_t)(qspi_cmd_struct->second_dummy_cycle_num << 16);
+ w1_val |= (uint32_t)(qspi_cmd_struct->instruction_length << 24);
+ w1_val |= (uint32_t)(qspi_cmd_struct->pe_mode_enable << 28);
+ qspi_x->cmd_w1 = w1_val;
+
+ /* config analyse cmd_w2 register */
+ qspi_x->cmd_w2 = (uint32_t)qspi_cmd_struct->data_counter;
+
+ /* config analyse cmd_w3 register */
+ w3_val = (uint32_t)(qspi_cmd_struct->write_data_enable << 1);
+ w3_val |= (uint32_t)(qspi_cmd_struct->read_status_enable << 2);
+ w3_val |= (uint32_t)(qspi_cmd_struct->read_status_config << 3);
+ w3_val |= (uint32_t)(qspi_cmd_struct->operation_mode << 5);
+ w3_val |= (uint32_t)(qspi_cmd_struct->pe_mode_operate_code << 16);
+ w3_val |= (uint32_t)(qspi_cmd_struct->instruction_code << 24);
+ qspi_x->cmd_w3 = w3_val;
+}
+
+/**
+ * @brief initial xip mode for qspi_x
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1,QSPI2.
+ * @param xip_init_struct: pointer to xip init structure.
+ * @retval none.
+ */
+void qspi_xip_init(qspi_type* qspi_x, qspi_xip_type* xip_init_struct)
+{
+ uint32_t xc0_val = 0, xc1_val = 0, xc2_val = 0;
+ /* config analyse xip_cmd_w0 register */
+ xc0_val = (uint32_t)xip_init_struct->read_second_dummy_cycle_num;
+ xc0_val |= (uint32_t)(xip_init_struct->read_operation_mode << 8);
+ xc0_val |= (uint32_t)(xip_init_struct->read_address_length << 11);
+ xc0_val |= (uint32_t)(xip_init_struct->read_instruction_code << 12);
+ qspi_x->xip_cmd_w0 = xc0_val;
+
+ /* config analyse xip_cmd_w1 register */
+ xc1_val = (uint32_t)xip_init_struct->write_second_dummy_cycle_num;
+ xc1_val |= (uint32_t)(xip_init_struct->write_operation_mode << 8);
+ xc1_val |= (uint32_t)(xip_init_struct->write_address_length << 11);
+ xc1_val |= (uint32_t)(xip_init_struct->write_instruction_code << 12);
+ qspi_x->xip_cmd_w1 = xc1_val;
+
+ /* config analyse xip_cmd_w2 register */
+ xc2_val = (uint32_t)xip_init_struct->read_data_counter;
+ xc2_val |= (uint32_t)(xip_init_struct->read_time_counter << 8);
+ xc2_val |= (uint32_t)(xip_init_struct->read_select_mode << 15);
+ xc2_val |= (uint32_t)(xip_init_struct->write_data_counter << 16);
+ xc2_val |= (uint32_t)(xip_init_struct->write_time_counter << 24);
+ xc2_val |= (uint32_t)(xip_init_struct->write_select_mode << 31);
+ qspi_x->xip_cmd_w2 = xc2_val;
+}
+
+/**
+ * @brief read one byte from qspi device in command mode
+ * @param qspi_x: select the qspi peripheral.
+ * @retval 8-bit data.
+ */
+uint8_t qspi_byte_read(qspi_type* qspi_x)
+{
+ return qspi_x->dt_u8;
+}
+
+/**
+ * @brief read one half-word from qspi device in command mode
+ * @param qspi_x: select the qspi peripheral.
+ * @retval 16-bit data.
+ */
+uint16_t qspi_half_word_read(qspi_type* qspi_x)
+{
+ return qspi_x->dt_u16;
+}
+
+/**
+ * @brief read one word from qspi device in command mode
+ * @param qspi_x: select the qspi peripheral.
+ * @retval 32-bit data.
+ */
+uint32_t qspi_word_read(qspi_type* qspi_x)
+{
+ return qspi_x->dt;
+}
+
+/**
+ * @brief write one byte to qspi device in command mode
+ * @param qspi_x: select the qspi peripheral.
+ * @param value: 8-bit data.
+ * @retval none.
+ */
+void qspi_byte_write(qspi_type* qspi_x, uint8_t value)
+{
+ qspi_x->dt_u8 = value;
+}
+
+/**
+ * @brief write one half-word to qspi device in command mode
+ * @param qspi_x: select the qspi peripheral.
+ * @param value: 16-bit data.
+ * @retval none.
+ */
+void qspi_half_word_write(qspi_type* qspi_x, uint16_t value)
+{
+ qspi_x->dt_u16 = value;
+}
+
+/**
+ * @brief write one word to qspi device in command mode
+ * @param qspi_x: select the qspi peripheral.
+ * @param value: 32-bit data.
+ * @retval none.
+ */
+void qspi_word_write(qspi_type* qspi_x, uint32_t value)
+{
+ qspi_x->dt = value;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_scfg.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_scfg.c
new file mode 100644
index 0000000..8075881
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_scfg.c
@@ -0,0 +1,220 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_scfg.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the system config firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup SCFG
+ * @brief SCFG driver modules
+ * @{
+ */
+
+#ifdef SCFG_MODULE_ENABLED
+
+/** @defgroup SCFG_private_functions
+ * @{
+ */
+
+/**
+ * @brief scfg reset
+ * @param none
+ * @retval none
+ */
+void scfg_reset(void)
+{
+ crm_periph_reset(CRM_SCFG_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_SCFG_PERIPH_RESET, FALSE);
+}
+
+/**
+ * @brief scfg xmc address mapping swap set
+ * @param xmc_swap
+ * this parameter can be one of the following values:
+ * - SCFG_XMC_SWAP_NONE
+ * - SCFG_XMC_SWAP_MODE1
+ * - SCFG_XMC_SWAP_MODE2
+ * - SCFG_XMC_SWAP_MODE3
+ * @retval none
+ */
+void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap)
+{
+ SCFG->cfg1_bit.swap_xmc = xmc_swap;
+}
+
+/**
+ * @brief scfg infrared config
+ * @param source
+ * this parameter can be one of the following values:
+ * - SCFG_IR_SOURCE_TMR10
+ * - SCFG_IR_SOURCE_USART1
+ * - SCFG_IR_SOURCE_USART2
+ * @param polarity
+ * this parameter can be one of the following values:
+ * - SCFG_IR_POLARITY_NO_AFFECTE
+ * - SCFG_IR_POLARITY_REVERSE
+ * @retval none
+ */
+void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity)
+{
+ SCFG->cfg1_bit.ir_src_sel = source;
+ SCFG->cfg1_bit.ir_pol = polarity;
+}
+
+/**
+ * @brief scfg memory address mapping set
+ * @param mem_map
+ * this parameter can be one of the following values:
+ * - SCFG_MEM_MAP_MAIN_MEMORY
+ * - SCFG_MEM_MAP_BOOT_MEMORY
+ * - SCFG_MEM_MAP_XMC_BANK1
+ * - SCFG_MEM_MAP_INTERNAL_SRAM
+ * - SCFG_MEM_MAP_XMC_SDRAM_BANK1
+ * @retval none
+ */
+void scfg_mem_map_set(scfg_mem_map_type mem_map)
+{
+ SCFG->cfg1_bit.mem_map_sel = mem_map;
+}
+
+/**
+ * @brief scfg emac interface set
+ * @param mode
+ * this parameter can be one of the following values:
+ * - SCFG_EMAC_SELECT_MII
+ * - SCFG_EMAC_SELECT_RMII
+ * @retval none
+ */
+void scfg_emac_interface_set(scfg_emac_interface_type mode)
+{
+ SCFG->cfg2_bit.mii_rmii_sel = mode;
+}
+
+/**
+ * @brief select the gpio pin used as exint line.
+ * @param port_source:
+ * select the gpio port to be used as source for exint lines.
+ * this parameter can be one of the following values:
+ * - SCFG_PORT_SOURCE_GPIOA
+ * - SCFG_PORT_SOURCE_GPIOB
+ * - SCFG_PORT_SOURCE_GPIOC
+ * - SCFG_PORT_SOURCE_GPIOD
+ * - SCFG_PORT_SOURCE_GPIOE
+ * - SCFG_PORT_SOURCE_GPIOF
+ * - SCFG_PORT_SOURCE_GPIOG
+ * - SCFG_PORT_SOURCE_GPIOH
+ * @param pin_source:
+ * specifies the exint line to be configured.
+ * this parameter can be one of the following values:
+ * - SCFG_PINS_SOURCE0
+ * - SCFG_PINS_SOURCE1
+ * - SCFG_PINS_SOURCE2
+ * - SCFG_PINS_SOURCE3
+ * - SCFG_PINS_SOURCE4
+ * - SCFG_PINS_SOURCE5
+ * - SCFG_PINS_SOURCE6
+ * - SCFG_PINS_SOURCE7
+ * - SCFG_PINS_SOURCE8
+ * - SCFG_PINS_SOURCE9
+ * - SCFG_PINS_SOURCE10
+ * - SCFG_PINS_SOURCE11
+ * - SCFG_PINS_SOURCE12
+ * - SCFG_PINS_SOURCE13
+ * - SCFG_PINS_SOURCE14
+ * - SCFG_PINS_SOURCE15
+ * @retval none
+ */
+void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source)
+{
+ uint32_t tmp = 0x00;
+ tmp = ((uint32_t)0x0F) << (0x04 * (pin_source & (uint8_t)0x03));
+
+ switch (pin_source >> 0x02)
+ {
+ case 0:
+ SCFG->exintc1 &= ~tmp;
+ SCFG->exintc1 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
+ break;
+ case 1:
+ SCFG->exintc2 &= ~tmp;
+ SCFG->exintc2 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
+ break;
+ case 2:
+ SCFG->exintc3 &= ~tmp;
+ SCFG->exintc3 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
+ break;
+ case 3:
+ SCFG->exintc4 &= ~tmp;
+ SCFG->exintc4 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief enable or disable gpio pins ultra driven.
+ * @param value:
+ * this parameter can be one of the following values:
+ * - SCFG_ULTRA_DRIVEN_PB3
+ * - SCFG_ULTRA_DRIVEN_PB9
+ * - SCFG_ULTRA_DRIVEN_PB10
+ * - SCFG_ULTRA_DRIVEN_PD12
+ * - SCFG_ULTRA_DRIVEN_PD13
+ * - SCFG_ULTRA_DRIVEN_PD14
+ * - SCFG_ULTRA_DRIVEN_PD15
+ * - SCFG_ULTRA_DRIVEN_PF14
+ * - SCFG_ULTRA_DRIVEN_PF15
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state)
+{
+ if(TRUE == new_state)
+ {
+ SCFG_REG(value) |= SCFG_REG_BIT(value);
+ }
+ else
+ {
+ SCFG_REG(value) &= ~(SCFG_REG_BIT(value));
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_sdio.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_sdio.c
new file mode 100644
index 0000000..c078d50
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_sdio.c
@@ -0,0 +1,586 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_sdio.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the sdio firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup SDIO
+ * @brief SDIO driver modules
+ * @{
+ */
+
+#ifdef SDIO_MODULE_ENABLED
+
+/** @defgroup SDIO_private_functions
+ * @{
+ */
+
+/**
+ * @brief reset the sdio register
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @retval none
+ */
+void sdio_reset(sdio_type *sdio_x)
+{
+ sdio_x->pwrctrl = 0x0;
+ sdio_x->clkctrl = 0x0;
+ sdio_x->argu = 0x0;
+ sdio_x->cmdctrl = 0x0;
+ sdio_x->dttmr = 0x0;
+ sdio_x->dtlen = 0x0;
+ sdio_x->dtctrl = 0x0;
+ sdio_x->inten = 0x0;
+ sdio_x->intclr = 0x004007FF;
+}
+
+/**
+ * @brief set the power status of the controller
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param power_state
+ * this parameter can be one of the following values:
+ * - SDIO_POWER_OFF
+ * - SDIO_POWER_ON
+ * @retval none
+ */
+void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state)
+{
+ sdio_x->pwrctrl_bit.ps = power_state;
+}
+
+/**
+ * @brief get power status.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @retval flag_status (SET or RESET)
+ */
+flag_status sdio_power_status_get(sdio_type *sdio_x)
+{
+ flag_status flag = RESET;
+
+ if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_ON)
+ {
+ flag = SET;
+ }
+ else if(sdio_x->pwrctrl_bit.ps == SDIO_POWER_OFF)
+ {
+ flag = RESET;
+ }
+
+ return flag;
+}
+
+/**
+ * @brief config sdio clock
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param clk_div: sdio clock divide factor(frequency = sdio_clk / [clk_psc + 2]).
+ * @param clk_edg
+ * this parameter can be one of the following values:
+ * - SDIO_CLOCK_EDGE_RISING
+ * - SDIO_CLOCK_EDGE_FALLING
+ * @retval none
+ */
+void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg)
+{
+ /* config clock edge */
+ sdio_x->clkctrl_bit.clkegs = clk_edg;
+
+ /* config clock divide [7:0] */
+ sdio_x->clkctrl_bit.clkdiv_l = (clk_div & 0xFF);
+
+ /* config clock divide [9:8] */
+ sdio_x->clkctrl_bit.clkdiv_h = ((clk_div & 0x300) >> 8);
+}
+
+/**
+ * @brief config sdio bus width
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param width
+ * this parameter can be one of the following values:
+ * - SDIO_BUS_WIDTH_D1
+ * - SDIO_BUS_WIDTH_D4
+ * - SDIO_BUS_WIDTH_D8
+ * @retval none
+ */
+void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width)
+{
+ sdio_x->clkctrl_bit.busws = width;
+}
+
+/**
+ * @brief enable or disable clock divider bypss
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->clkctrl_bit.bypsen = new_state;
+}
+
+/**
+ * @brief enable or disable power saving mode, config sdio_ck clock output
+ * when the bus is idle.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->clkctrl_bit.pwrsven = new_state;
+}
+
+/**
+ * @brief enable or disable hardware flow control.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->clkctrl_bit.hfcen = new_state;
+}
+
+/**
+ * @brief enable or disable sdio_ck output.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->clkctrl_bit.clkoen = new_state;
+}
+
+/**
+ * @brief enable or disable dma.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->dtctrl_bit.dmaen = new_state;
+}
+
+/**
+ * @brief config corresponding interrupt.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param int_opt
+ * this parameter can be one of the following values:
+ * - SDIO_CMDFAIL_INT
+ * - SDIO_DTFAIL_INT
+ * - SDIO_CMDTIMEOUT_INT
+ * - SDIO_DTTIMEOUT_INT
+ * - SDIO_TXERRU_INT
+ * - SDIO_RXERRO_INT
+ * - SDIO_CMDRSPCMPL_INT
+ * - SDIO_CMDCMPL_INT
+ * - SDIO_DTCMP_INT
+ * - SDIO_SBITERR_INT
+ * - SDIO_DTBLKCMPL_INT
+ * - SDIO_DOCMD_INT
+ * - SDIO_DOTX_INT
+ * - SDIO_DORX_INT
+ * - SDIO_TXBUFH_INT
+ * - SDIO_RXBUFH_INT
+ * - SDIO_TXBUFF_INT
+ * - SDIO_RXBUFF_INT
+ * - SDIO_TXBUFE_INT
+ * - SDIO_RXBUFE_INT
+ * - SDIO_TXBUF_INT
+ * - SDIO_RXBUF_INT
+ * - SDIO_SDIOIF_INT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state)
+{
+ /* enable interrupt */
+ if(TRUE == new_state)
+ {
+ sdio_x->inten |= int_opt;
+ }
+ /* disable interrupt */
+ else
+ {
+ sdio_x->inten &= ~(int_opt);
+ }
+}
+
+/**
+ * @brief get sdio flag.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param flag
+ * this parameter can be one of the following values:
+ * - SDIO_CMDFAIL_FLAG
+ * - SDIO_DTFAIL_FLAG
+ * - SDIO_CMDTIMEOUT_FLAG
+ * - SDIO_DTTIMEOUT_FLAG
+ * - SDIO_TXERRU_FLAG
+ * - SDIO_RXERRO_FLAG
+ * - SDIO_CMDRSPCMPL_FLAG
+ * - SDIO_CMDCMPL_FLAG
+ * - SDIO_DTCMPL_FLAG
+ * - SDIO_SBITERR_FLAG
+ * - SDIO_DTBLKCMPL_FLAG
+ * - SDIO_DOCMD_FLAG
+ * - SDIO_DOTX_FLAG
+ * - SDIO_DORX_FLAG
+ * - SDIO_TXBUFH_FLAG
+ * - SDIO_RXBUFH_FLAG
+ * - SDIO_TXBUFF_FLAG
+ * - SDIO_RXBUFF_FLAG
+ * - SDIO_TXBUFE_FLAG
+ * - SDIO_RXBUFE_FLAG
+ * - SDIO_TXBUF_FLAG
+ * - SDIO_RXBUF_FLAG
+ * - SDIO_SDIOIF_FLAG
+ * @retval flag_status (SET or RESET)
+ */
+flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag)
+{
+ flag_status status = RESET;
+
+ if((sdio_x->sts & flag) == flag)
+ {
+ status = SET;
+ }
+ else
+ {
+ status = RESET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief clear sdio flag.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param int_opt
+ * this parameter can be any combination of the following values:
+ * - SDIO_CMDFAIL_FLAG
+ * - SDIO_DTFAIL_FLAG
+ * - SDIO_CMDTIMEOUT_FLAG
+ * - SDIO_DTTIMEOUT_FLAG
+ * - SDIO_TXERRU_FLAG
+ * - SDIO_RXERRO_FLAG
+ * - SDIO_CMDRSPCMPL_FLAG
+ * - SDIO_CMDCMPL_FLAG
+ * - SDIO_DTCMPL_FLAG
+ * - SDIO_SBITERR_FLAG
+ * - SDIO_DTBLKCMPL_FLAG
+ * - SDIO_SDIOIF_FLAG
+ * @retval none
+ */
+void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag)
+{
+ sdio_x->intclr = flag;
+}
+
+/**
+ * @brief config sdio command.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param command_struct : pointer to a sdio_command_struct_type structure
+ * that contains the configuration information for the sdio command.
+ * @retval none
+ */
+void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct)
+{
+ /* disable command path state machine */
+ sdio_x->cmdctrl_bit.ccsmen = FALSE;
+
+ /* config command argument */
+ sdio_x->argu = command_struct->argument;
+
+ /* config command register */
+ sdio_x->cmdctrl_bit.cmdidx = command_struct->cmd_index;
+ sdio_x->cmdctrl_bit.rspwt = command_struct->rsp_type;
+ sdio_x->cmdctrl_bit.intwt = (command_struct->wait_type & 0x1); /* [1:0] -> [0] */
+ sdio_x->cmdctrl_bit.pndwt = (command_struct->wait_type & 0x2)>>1; /* [1:0] -> [1] */
+}
+
+/**
+ * @brief enable or disable command path state machine(CPSM).
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->cmdctrl_bit.ccsmen = new_state;
+}
+
+/**
+ * @brief get command index of last command for which response received.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param new_state (TRUE or FALSE)
+ * @retval uint8_t: command index
+ */
+uint8_t sdio_command_response_get(sdio_type *sdio_x)
+{
+ return sdio_x->rspcmd_bit.rspcmd;
+}
+
+/**
+ * @brief get response received from the card for the last command.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param reg_index
+ * this parameter can be one of the following values:
+ * - SDIO_RSP1_INDEX
+ * - SDIO_RSP2_INDEX
+ * - SDIO_RSP3_INDEX
+ * - SDIO_RSP4_INDEX
+ * @retval uint32_t: response register value
+ */
+uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index)
+{
+ uint32_t response_value = 0;
+
+ switch(reg_index)
+ {
+ case SDIO_RSP1_INDEX:
+ response_value = sdio_x->rsp1;
+ break;
+ case SDIO_RSP2_INDEX:
+ response_value = sdio_x->rsp2;
+ break;
+ case SDIO_RSP3_INDEX:
+ response_value = sdio_x->rsp3;
+ break;
+ case SDIO_RSP4_INDEX:
+ response_value = sdio_x->rsp4;
+ break;
+ default: break;
+ }
+
+ return response_value;
+}
+
+/**
+ * @brief config sdio data.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param data_struct : pointer to a sdio_data_struct_type structure
+ * that contains the configuration information for the sdio data.
+ * @retval none
+ */
+void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct)
+{
+ /* disable data path state machine */
+ sdio_x->dtctrl_bit.tfren = FALSE;
+
+ /* config data block, transfer mode and transfer direction */
+ sdio_x->dtctrl_bit.blksize = data_struct->block_size;
+ sdio_x->dtctrl_bit.tfrdir = data_struct->transfer_direction;
+ sdio_x->dtctrl_bit.tfrmode = data_struct->transfer_mode;
+
+ /* config data length */
+ sdio_x->dtlen_bit.dtlen = data_struct->data_length;
+
+ /* config data transfer timeout */
+ sdio_x->dttmr_bit.timeout = data_struct->timeout;
+}
+
+/**
+ * @brief enable or disable data path state machine(DPSM).
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->dtctrl_bit.tfren = new_state;
+}
+
+/**
+ * @brief get the number of remaining data bytes to be transferred.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @retval uint32_t: number of bytes
+ */
+uint32_t sdio_data_counter_get(sdio_type *sdio_x)
+{
+ return sdio_x->dtcnt;
+}
+
+/**
+ * @brief read a word data from sdio fifo.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @retval uint32_t: data received
+ */
+uint32_t sdio_data_read(sdio_type *sdio_x)
+{
+ return sdio_x->buf;
+}
+
+/**
+ * @brief get the number of words left to be written to or read from fifo..
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @retval uint32_t: number of words
+ */
+uint32_t sdio_buffer_counter_get(sdio_type *sdio_x)
+{
+ return sdio_x->bufcnt;
+}
+
+/**
+ * @brief write one word data to fifo.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param data: data to be transferred.
+ * @retval none
+ */
+void sdio_data_write(sdio_type *sdio_x, uint32_t data)
+{
+ sdio_x->buf = data;
+}
+
+/**
+ * @brief set the read wait mode.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param mode
+ * this parameter can be one of the following values:
+ * - SDIO_READ_WAIT_CONTROLLED_BY_D2
+ * - SDIO_READ_WAIT_CONTROLLED_BY_CK
+ * @retval none
+ */
+void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode)
+{
+ sdio_x->dtctrl_bit.rdwtmode = mode;
+}
+
+/**
+ * @brief enable or disable to start sd i/o read wait operation.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->dtctrl_bit.rdwtstart = new_state;
+}
+
+/**
+ * @brief enable or disable to stop sd i/o read wait operation.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->dtctrl_bit.rdwtstop = new_state;
+}
+
+/**
+ * @brief enable or disable the sd i/o function.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->dtctrl_bit.ioen = new_state;
+}
+
+/**
+ * @brief enable or disable sd i/o suspend command sending.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1, SDIO2.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->cmdctrl_bit.iosusp = new_state;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_spi.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_spi.c
new file mode 100644
index 0000000..ab87bf2
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_spi.c
@@ -0,0 +1,652 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_spi.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the spi firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup SPI
+ * @brief SPI driver modules
+ * @{
+ */
+
+#ifdef SPI_MODULE_ENABLED
+
+/** @defgroup SPI_private_functions
+ * @{
+ */
+
+/**
+ * @brief spi reset by crm reset register
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4
+ * @retval none
+ */
+void spi_i2s_reset(spi_type *spi_x)
+{
+ if(spi_x == SPI1)
+ {
+ crm_periph_reset(CRM_SPI1_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_SPI1_PERIPH_RESET, FALSE);
+ }
+ else if(spi_x == SPI2)
+ {
+ crm_periph_reset(CRM_SPI2_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_SPI2_PERIPH_RESET, FALSE);
+ }
+ else if(spi_x == SPI3)
+ {
+ crm_periph_reset(CRM_SPI3_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_SPI3_PERIPH_RESET, FALSE);
+ }
+ else if(spi_x == SPI4)
+ {
+ crm_periph_reset(CRM_SPI4_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_SPI4_PERIPH_RESET, FALSE);
+ }
+}
+
+/**
+ * @brief spi init config with its default value.
+ * @param spi_init_struct : pointer to a spi_init_type structure which will
+ * be initialized.
+ * @retval none
+ */
+void spi_default_para_init(spi_init_type* spi_init_struct)
+{
+ spi_init_struct->transmission_mode = SPI_TRANSMIT_FULL_DUPLEX;
+ spi_init_struct->master_slave_mode = SPI_MODE_SLAVE;
+ spi_init_struct->mclk_freq_division = SPI_MCLK_DIV_2;
+ spi_init_struct->first_bit_transmission = SPI_FIRST_BIT_MSB;
+ spi_init_struct->frame_bit_num = SPI_FRAME_8BIT;
+ spi_init_struct->clock_polarity = SPI_CLOCK_POLARITY_LOW;
+ spi_init_struct->clock_phase = SPI_CLOCK_PHASE_1EDGE;
+ spi_init_struct->cs_mode_selection = SPI_CS_SOFTWARE_MODE;
+}
+
+/**
+ * @brief spi init config with its setting value.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4
+ * @param spi_init_struct : pointer to a spi_init_type structure which will be initialized.
+ * @retval none
+ */
+void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct)
+{
+ spi_x->i2sctrl_bit.i2smsel = FALSE;
+ if(spi_init_struct->transmission_mode == SPI_TRANSMIT_FULL_DUPLEX)
+ {
+ spi_x->ctrl1_bit.slben = FALSE;
+ spi_x->ctrl1_bit.slbtd = FALSE;
+ spi_x->ctrl1_bit.ora = FALSE;
+ }
+ else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_SIMPLEX_RX)
+ {
+ spi_x->ctrl1_bit.slben = FALSE;
+ spi_x->ctrl1_bit.slbtd = FALSE;
+ spi_x->ctrl1_bit.ora = TRUE;
+ }
+ else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_HALF_DUPLEX_RX)
+ {
+ spi_x->ctrl1_bit.slben = TRUE;
+ spi_x->ctrl1_bit.slbtd = FALSE;
+ spi_x->ctrl1_bit.ora = FALSE;
+ }
+ else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_HALF_DUPLEX_TX)
+ {
+ spi_x->ctrl1_bit.slben = TRUE;
+ spi_x->ctrl1_bit.slbtd = TRUE;
+ spi_x->ctrl1_bit.ora = FALSE;
+ }
+
+ spi_x->ctrl1_bit.swcsen = spi_init_struct->cs_mode_selection;
+ if((spi_init_struct->master_slave_mode == SPI_MODE_MASTER) && (spi_init_struct->cs_mode_selection == SPI_CS_SOFTWARE_MODE))
+ {
+ spi_x->ctrl1_bit.swcsil = TRUE;
+ }
+ else
+ {
+ spi_x->ctrl1_bit.swcsil = FALSE;
+ }
+ spi_x->ctrl1_bit.msten = spi_init_struct->master_slave_mode;
+
+ if(spi_init_struct->mclk_freq_division <= SPI_MCLK_DIV_256)
+ {
+ spi_x->ctrl2_bit.mdiv3en = FALSE;
+ spi_x->ctrl2_bit.mdiv_h = FALSE;
+ spi_x->ctrl1_bit.mdiv_l = spi_init_struct->mclk_freq_division;
+ }
+ else if(spi_init_struct->mclk_freq_division == SPI_MCLK_DIV_3)
+ {
+ spi_x->ctrl2_bit.mdiv3en = TRUE;
+ spi_x->ctrl2_bit.mdiv_h = FALSE;
+ spi_x->ctrl1_bit.mdiv_l = 0;
+ }
+ else
+ {
+ spi_x->ctrl2_bit.mdiv3en = FALSE;
+ spi_x->ctrl2_bit.mdiv_h = TRUE;
+ spi_x->ctrl1_bit.mdiv_l = spi_init_struct->mclk_freq_division & 0x7;
+ }
+
+ spi_x->ctrl1_bit.ltf = spi_init_struct->first_bit_transmission;
+ spi_x->ctrl1_bit.fbn = spi_init_struct->frame_bit_num;
+ spi_x->ctrl1_bit.clkpol = spi_init_struct->clock_polarity;
+ spi_x->ctrl1_bit.clkpha = spi_init_struct->clock_phase;
+}
+
+/**
+ * @brief enable or disable the ti mode for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4
+ * @param new_state: new state of ti mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void spi_ti_mode_enable(spi_type* spi_x, confirm_state new_state)
+{
+ spi_x->ctrl2_bit.tien = new_state;
+}
+
+/**
+ * @brief spi next transmit crc for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4
+ * @retval none
+ */
+void spi_crc_next_transmit(spi_type* spi_x)
+{
+ spi_x->ctrl1_bit.ntc = TRUE;
+}
+
+/**
+ * @brief set the crc polynomial value for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4
+ * @param crc_poly: crc polynomial value.
+ * @retval none
+ */
+void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly)
+{
+ spi_x->cpoly_bit.cpoly = crc_poly;
+}
+
+/**
+ * @brief return the crc polynomial register value for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4
+ * @retval the select crc polynomial register value
+ */
+uint16_t spi_crc_polynomial_get(spi_type* spi_x)
+{
+ return spi_x->cpoly_bit.cpoly;
+}
+
+/**
+ * @brief enable or disable the hardware crc calculation for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4
+ * @param new_state: new state of crc calculation.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void spi_crc_enable(spi_type* spi_x, confirm_state new_state)
+{
+ spi_x->ctrl1_bit.ccen = new_state;
+}
+
+/**
+ * @brief return the transmit or the receive crc value for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4
+ * @param crc_direction: select transmit or receive crc value to be read
+ * - SPI_CRC_RX
+ * - SPI_CRC_TX
+ * @retval the select crc register value
+ */
+uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction)
+{
+ if(crc_direction == SPI_CRC_RX)
+ return spi_x->rcrc_bit.rcrc;
+ else
+ return spi_x->tcrc_bit.tcrc;
+}
+
+/**
+ * @brief enable or disable the hardware cs output for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4
+ * @param new_state: new state of spi master cs output.
+ * this parameter can be: TRUE or FALSE.
+ * note:the bit only use in spi master mode
+ * @retval none
+ */
+void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state)
+{
+ spi_x->ctrl2_bit.hwcsoe = new_state;
+}
+
+/**
+ * @brief set the software cs internal level for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4
+ * @param level: set the state of spi cs level.
+ * this parameter can be one of the following values:
+ * - SPI_SWCS_INTERNAL_LEVEL_LOW
+ * - SPI_SWCS_INTERNAL_LEVEL_HIGHT
+ * note:the bit only use when swcsen bit is set.
+ * note:when use this bit,io operation on the cs pin are invalid.
+ * @retval none
+ */
+void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level)
+{
+ spi_x->ctrl1_bit.swcsil = level;
+}
+
+/**
+ * @brief set the data frame bit num for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4
+ * @param bit_num: set the data frame size
+ * - SPI_FRAME_8BIT
+ * - SPI_FRAME_16BIT
+ * @retval none
+ */
+void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num)
+{
+ spi_x->ctrl1_bit.fbn = bit_num;
+}
+
+/**
+ * @brief set the data transmission direction in single line bidirectiona half duplex mode of the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4
+ * @param direction: data transfer direction
+ * this parameter can be one of the following values:
+ * - SPI_HALF_DUPLEX_DIRECTION_RX
+ * - SPI_HALF_DUPLEX_DIRECTION_TX
+ * @retval none
+ */
+void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction)
+{
+ spi_x->ctrl1_bit.slbtd = direction;
+}
+
+/**
+ * @brief enable or disable spi.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4
+ * @param new_state: new state of spi.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void spi_enable(spi_type* spi_x, confirm_state new_state)
+{
+ spi_x->ctrl1_bit.spien = new_state;
+}
+
+/**
+ * @brief i2s init config with its default value.
+ * @param i2s_init_struct : pointer to a i2s_init_type structure which will
+ * be initialized.
+ * @retval none
+ */
+void i2s_default_para_init(i2s_init_type* i2s_init_struct)
+{
+ i2s_init_struct->operation_mode = I2S_MODE_SLAVE_TX;
+ i2s_init_struct->audio_protocol = I2S_AUDIO_PROTOCOL_PHILLIPS;
+ i2s_init_struct->audio_sampling_freq = I2S_AUDIO_FREQUENCY_DEFAULT;
+ i2s_init_struct->data_channel_format = I2S_DATA_16BIT_CHANNEL_16BIT;
+ i2s_init_struct->clock_polarity = I2S_CLOCK_POLARITY_LOW;
+ i2s_init_struct->mclk_output_enable = FALSE;
+}
+
+/**
+ * @brief i2s init config with its setting value.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+ * @param i2s_init_struct : pointer to a i2s_init_type structure which will be initialized.
+ * @retval none
+ */
+void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct)
+{
+ crm_clocks_freq_type clocks_freq;
+ uint32_t i2s_sclk_index = 0;
+ uint32_t i2sdiv_index = 2, i2sodd_index = 0, frequency_index = 0;
+
+ /* i2s audio frequency config */
+ if(i2s_init_struct->audio_sampling_freq == I2S_AUDIO_FREQUENCY_DEFAULT)
+ {
+ i2sodd_index = 0;
+ i2sdiv_index = 2;
+ }
+ else
+ {
+ crm_clocks_freq_get(&clocks_freq);
+ i2s_sclk_index = clocks_freq.sclk_freq;
+ if((i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT) || (i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG))
+ {
+ if(i2s_init_struct->mclk_output_enable == TRUE)
+ {
+ frequency_index = (((i2s_sclk_index / 128) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ }
+ else
+ {
+ if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
+ frequency_index = (((i2s_sclk_index / 16) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ else
+ frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ }
+ }
+ else
+ {
+ if(i2s_init_struct->mclk_output_enable == TRUE)
+ {
+ frequency_index = (((i2s_sclk_index / 256) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ }
+ else
+ {
+ if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
+ frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ else
+ frequency_index = (((i2s_sclk_index / 64) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ }
+ }
+ }
+ frequency_index = frequency_index / 10;
+ i2sodd_index = frequency_index & (uint16_t)0x0001;
+ i2sdiv_index = (frequency_index - i2sodd_index) / 2;
+ if((i2sdiv_index < 2) || (i2sdiv_index > 0x03FF))
+ {
+ i2sodd_index = 0;
+ i2sdiv_index = 2;
+ }
+ spi_x->i2sclk_bit.i2sodd = i2sodd_index;
+ if(i2sdiv_index > 0x00FF)
+ {
+ spi_x->i2sclk_bit.i2sdiv_h = (i2sdiv_index >> 8) & 0x0003;
+ spi_x->i2sclk_bit.i2sdiv_l = i2sdiv_index & 0x00FF;
+ }
+ else
+ {
+ spi_x->i2sclk_bit.i2sdiv_h = 0;
+ spi_x->i2sclk_bit.i2sdiv_l = i2sdiv_index;
+ }
+
+ /* i2s audio_protocol set*/
+ if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG)
+ {
+ spi_x->i2sctrl_bit.pcmfssel = 1;
+ spi_x->i2sctrl_bit.stdsel = 3;
+ }
+ else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT)
+ {
+ spi_x->i2sctrl_bit.pcmfssel = 0;
+ spi_x->i2sctrl_bit.stdsel = 3;
+ }
+ else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_LSB)
+ {
+ spi_x->i2sctrl_bit.pcmfssel = 0;
+ spi_x->i2sctrl_bit.stdsel = 2;
+ }
+ else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_MSB)
+ {
+ spi_x->i2sctrl_bit.pcmfssel = 0;
+ spi_x->i2sctrl_bit.stdsel = 1;
+ }
+ else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PHILLIPS)
+ {
+ spi_x->i2sctrl_bit.pcmfssel = 0;
+ spi_x->i2sctrl_bit.stdsel = 0;
+ }
+
+ /* i2s data_channel_format set*/
+ if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
+ {
+ spi_x->i2sctrl_bit.i2scbn = 0;
+ spi_x->i2sctrl_bit.i2sdbn = 0;
+ }
+ else if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_32BIT)
+ {
+ spi_x->i2sctrl_bit.i2scbn = 1;
+ spi_x->i2sctrl_bit.i2sdbn = 0;
+ }
+ else if(i2s_init_struct->data_channel_format == I2S_DATA_24BIT_CHANNEL_32BIT)
+ {
+ spi_x->i2sctrl_bit.i2scbn = 1;
+ spi_x->i2sctrl_bit.i2sdbn = 1;
+ }
+ else if(i2s_init_struct->data_channel_format == I2S_DATA_32BIT_CHANNEL_32BIT)
+ {
+ spi_x->i2sctrl_bit.i2scbn = 1;
+ spi_x->i2sctrl_bit.i2sdbn = 2;
+ }
+
+ spi_x->i2sctrl_bit.i2sclkpol = i2s_init_struct->clock_polarity;
+ spi_x->i2sclk_bit.i2smclkoe = i2s_init_struct->mclk_output_enable;
+ spi_x->i2sctrl_bit.opersel = i2s_init_struct->operation_mode;
+ spi_x->i2sctrl_bit.i2smsel = TRUE;
+}
+
+/**
+ * @brief enable or disable i2s.
+ * @param spi_x: select the i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+ * @param new_state: new state of i2s.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void i2s_enable(spi_type* spi_x, confirm_state new_state)
+{
+ spi_x->i2sctrl_bit.i2sen = new_state;
+}
+
+/**
+ * @brief enable or disable the specified spi/i2s interrupts.
+ * @param spi_x: select the spi/i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+ * @param spi_i2s_int: specifies the spi/i2s interrupt sources to be enabled or disabled.
+ * this parameter can be one of the following values:
+ * - SPI_I2S_ERROR_INT
+ * - SPI_I2S_RDBF_INT
+ * - SPI_I2S_TDBE_INT
+ * @param new_state: new state of the specified spi/i2s interrupts.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ spi_x->ctrl2 |= spi_i2s_int;
+ }
+ else
+ {
+ spi_x->ctrl2 &= ~spi_i2s_int;
+ }
+}
+
+/**
+ * @brief enable or disable the spi/i2s dma transmitter mode.
+ * @param spi_x: select the spi/i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+ * @param new_state: new state of the dma request.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state)
+{
+ spi_x->ctrl2_bit.dmaten = new_state;
+}
+
+/**
+ * @brief enable or disable the spi/i2s dma receiver mode.
+ * @param spi_x: select the spi/i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+ * @param new_state: new state of the dma request.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state)
+{
+ spi_x->ctrl2_bit.dmaren = new_state;
+}
+
+/**
+ * @brief spi/i2s data transmit
+ * @param spi_x: select the spi/i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+ * @param tx_data: the data to be transmit.
+ * this parameter can be:
+ * - (0x0000~0xFFFF)
+ * @retval none
+ */
+void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data)
+{
+ spi_x->dt = tx_data;
+}
+
+/**
+ * @brief spi/i2s data receive
+ * @param spi_x: select the spi/i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+ * @retval the received data value
+ */
+uint16_t spi_i2s_data_receive(spi_type* spi_x)
+{
+ return (uint16_t)spi_x->dt;
+}
+
+/**
+ * @brief get flag of the specified spi/i2s peripheral.
+ * @param spi_x: select the spi/i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+ * @param spi_i2s_flag: select the spi/i2s flag
+ * this parameter can be one of the following values:
+ * - SPI_I2S_RDBF_FLAG
+ * - SPI_I2S_TDBE_FLAG
+ * - I2S_ACS_FLAG (this flag only use in i2s mode)
+ * - I2S_TUERR_FLAG (this flag only use in i2s mode)
+ * - SPI_CCERR_FLAG (this flag only use in spi mode)
+ * - SPI_MMERR_FLAG (this flag only use in spi mode)
+ * - SPI_I2S_ROERR_FLAG
+ * - SPI_I2S_BF_FLAG
+ * - SPI_CSPAS_FLAG
+ * @retval the new state of spi/i2s flag
+ */
+flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
+{
+ flag_status status = RESET;
+ if ((spi_x->sts & spi_i2s_flag) == RESET)
+ {
+ status = RESET;
+ }
+ else
+ {
+ status = SET;
+ }
+ return status;
+}
+
+/**
+ * @brief clear flag of the specified spi/i2s peripheral.
+ * @param spi_x: select the spi/i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3 ,SPI4 , I2S2EXT, I2S3EXT
+ * @param spi_i2s_flag: select the spi/i2s flag
+ * this parameter can be one of the following values:
+ * - SPI_CCERR_FLAG
+ * - SPI_I2S_RDBF_FLAG
+ * - I2S_TUERR_FLAG
+ * - SPI_MMERR_FLAG
+ * - SPI_I2S_ROERR_FLAG
+ * - SPI_CSPAS_FLAG
+ * @note
+ * SPI_I2S_TDBE_FLAG this flag is cleared when the tx buffer already contain data to be transmit.
+ * I2S_ACS_FLAG this flag cann't cleared by software,the flag indicate the channel side(not use in pcm standard mode).
+ * SPI_I2S_BF_FLAG this flag cann't cleared by software, it's set and cleared by hardware.
+ * @retval none
+ */
+void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag)
+{
+ volatile uint32_t temp = 0;
+ temp = temp;
+ if(spi_i2s_flag == SPI_CCERR_FLAG)
+ spi_x->sts = ~SPI_CCERR_FLAG;
+ else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG)
+ temp = REG32(&spi_x->dt);
+ else if(spi_i2s_flag == I2S_TUERR_FLAG)
+ temp = REG32(&spi_x->sts);
+ else if(spi_i2s_flag == SPI_CSPAS_FLAG)
+ temp = REG32(&spi_x->sts);
+ else if(spi_i2s_flag == SPI_MMERR_FLAG)
+ {
+ temp = REG32(&spi_x->sts);
+ spi_x->ctrl1 = spi_x->ctrl1;
+ }
+ else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG)
+ {
+ temp = REG32(&spi_x->dt);
+ temp = REG32(&spi_x->sts);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_tmr.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_tmr.c
new file mode 100644
index 0000000..8daf0e4
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_tmr.c
@@ -0,0 +1,1865 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_tmr.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the tmr firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup TMR
+ * @brief TMR driver modules
+ * @{
+ */
+
+#ifdef TMR_MODULE_ENABLED
+
+/** @defgroup TMR_private_functions
+ * @{
+ */
+
+/**
+ * @brief tmr reset by crm reset register
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @retval none
+ */
+void tmr_reset(tmr_type *tmr_x)
+{
+ if(tmr_x == TMR1)
+ {
+ crm_periph_reset(CRM_TMR1_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR1_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR2)
+ {
+ crm_periph_reset(CRM_TMR2_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR2_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR3)
+ {
+ crm_periph_reset(CRM_TMR3_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR3_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR4)
+ {
+ crm_periph_reset(CRM_TMR4_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR4_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR5)
+ {
+ crm_periph_reset(CRM_TMR5_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR5_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR6)
+ {
+ crm_periph_reset(CRM_TMR6_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR6_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR7)
+ {
+ crm_periph_reset(CRM_TMR7_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR7_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR8)
+ {
+ crm_periph_reset(CRM_TMR8_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR8_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR9)
+ {
+ crm_periph_reset(CRM_TMR9_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR9_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR10)
+ {
+ crm_periph_reset(CRM_TMR10_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR10_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR11)
+ {
+ crm_periph_reset(CRM_TMR11_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR11_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR12)
+ {
+ crm_periph_reset(CRM_TMR12_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR12_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR13)
+ {
+ crm_periph_reset(CRM_TMR13_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR13_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR14)
+ {
+ crm_periph_reset(CRM_TMR14_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR14_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR20)
+ {
+ crm_periph_reset(CRM_TMR20_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR20_PERIPH_RESET, FALSE);
+ }
+}
+
+/**
+ * @brief enable or disable tmr counter
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_counter_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+ /* tmr counter enable */
+ tmr_x->ctrl1_bit.tmren = new_state;
+}
+
+/**
+ * @brief init tmr output default para
+ * @param tmr_output_struct
+ * - to the structure of tmr_output_config_type
+ * @retval none
+ */
+void tmr_output_default_para_init(tmr_output_config_type *tmr_output_struct)
+{
+ tmr_output_struct->oc_mode = TMR_OUTPUT_CONTROL_OFF;
+ tmr_output_struct->oc_idle_state = FALSE;
+ tmr_output_struct->occ_idle_state = FALSE;
+ tmr_output_struct->oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
+ tmr_output_struct->occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
+ tmr_output_struct->oc_output_state = FALSE;
+ tmr_output_struct->occ_output_state = FALSE;
+}
+
+/**
+ * @brief init tmr input default para
+ * @param tmr_input_struct
+ * - to the structure of tmr_input_config_type
+ * @retval none
+ */
+void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct)
+{
+ tmr_input_struct->input_channel_select = TMR_SELECT_CHANNEL_1;
+ tmr_input_struct->input_polarity_select = TMR_INPUT_RISING_EDGE;
+ tmr_input_struct->input_mapped_select = TMR_CC_CHANNEL_MAPPED_DIRECT;
+ tmr_input_struct->input_filter_value = 0x0;
+}
+
+/**
+ * @brief init tmr brkdt default para
+ * @param tmr_brkdt_struct
+ * - to the structure of tmr_brkdt_config_type
+ * @retval none
+ */
+void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct)
+{
+ tmr_brkdt_struct->deadtime = 0x0;
+ tmr_brkdt_struct->brk_polarity = TMR_BRK_INPUT_ACTIVE_LOW;
+ tmr_brkdt_struct->wp_level = TMR_WP_OFF;
+ tmr_brkdt_struct->auto_output_enable = FALSE ;
+ tmr_brkdt_struct->fcsoen_state = FALSE ;
+ tmr_brkdt_struct->fcsodis_state = FALSE ;
+ tmr_brkdt_struct->brk_enable = FALSE ;
+}
+
+/**
+ * @brief init tmr base
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_pr (for 16 bit tmr 0x0000~0xFFFF,
+ * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
+ * @param tmr_div (timer div value:0x0000~0xFFFF)
+ * @retval none
+ */
+void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div)
+{
+ /* set the pr value */
+ tmr_x->pr = tmr_pr;
+
+ /* set the div value */
+ tmr_x->div = tmr_div;
+
+ /* trigger the overflow event to immediately reload pr value and div value */
+ tmr_x->swevt_bit.ovfswtr = TRUE;
+}
+
+/**
+ * @brief set tmr clock source division
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_clock_div
+ * this parameter can be one of the following values:
+ * - TMR_CLOCK_DIV1
+ * - TMR_CLOCK_DIV2
+ * - TMR_CLOCK_DIV4
+ * @retval none
+ */
+void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div)
+{
+ /* set tmr clock source division */
+ tmr_x->ctrl1_bit.clkdiv = tmr_clock_div;
+}
+
+/**
+ * @brief set tmr counter count direction
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_cnt_dir
+ * this parameter can be one of the following values:
+ * - TMR_COUNT_UP
+ * - TMR_COUNT_DOWN
+ * - TMR_COUNT_TWO_WAY_1
+ * - TMR_COUNT_TWO_WAY_2
+ * - TMR_COUNT_TWO_WAY_3
+ * @retval none
+ */
+void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir)
+{
+ /* set the cnt direct */
+ tmr_x->ctrl1_bit.cnt_dir = tmr_cnt_dir;
+}
+
+/**
+ * @brief set the repetition counter register(rpr) value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR8, TMR20
+ * @param tmr_rpr_value (0x0000~0xFFFF)
+ * @retval none
+ */
+void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value)
+{
+ /* set the repetition counter value */
+ if((tmr_x == TMR1) || (tmr_x == TMR8))
+
+ {
+ tmr_x->rpr_bit.rpr = tmr_rpr_value;
+ }
+}
+
+/**
+ * @brief set tmr counter value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_cnt_value (for 16 bit tmr 0x0000~0xFFFF,
+ * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
+ * @retval none
+ */
+void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value)
+{
+ /* set the tmr counter value */
+ tmr_x->cval = tmr_cnt_value;
+}
+
+/**
+ * @brief get tmr counter value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @retval tmr counter value
+ */
+uint32_t tmr_counter_value_get(tmr_type *tmr_x)
+{
+ return tmr_x->cval;
+}
+
+/**
+ * @brief set tmr div value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_div_value (for 16 bit tmr 0x0000~0xFFFF,
+ * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
+ * @retval none
+ */
+void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value)
+{
+ /* set the tmr div value */
+ tmr_x->div = tmr_div_value;
+}
+
+/**
+ * @brief get tmr div value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @retval tmr div value
+ */
+uint32_t tmr_div_value_get(tmr_type *tmr_x)
+{
+ return tmr_x->div;
+}
+
+/**
+ * @brief config tmr output channel
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_5
+ * @param tmr_output_struct
+ * - to the structure of tmr_output_config_type
+ * @retval none
+ */
+void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_output_config_type *tmr_output_struct)
+{
+ uint16_t channel_index = 0, channel_c_index = 0, channel = 0;
+
+ /* get channel idle state bit position in ctrl2 register */
+ channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << (8 + tmr_channel));
+
+ /* get channel complementary idle state bit position in ctrl2 register */
+ channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << (9 + tmr_channel));
+
+ if((tmr_x == TMR1) || (tmr_x == TMR8))
+ {
+ /* set output channel complementary idle state */
+ tmr_x->ctrl2 &= ~channel_c_index;
+ tmr_x->ctrl2 |= channel_c_index;
+ }
+
+ /* set output channel idle state */
+ tmr_x->ctrl2 &= ~channel_index;
+ tmr_x->ctrl2 |= channel_index;
+
+ /* set channel output mode */
+ channel = tmr_channel;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cm1_output_bit.c1octrl = tmr_output_struct->oc_mode;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cm1_output_bit.c2octrl = tmr_output_struct->oc_mode;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cm2_output_bit.c3octrl = tmr_output_struct->oc_mode;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cm2_output_bit.c4octrl = tmr_output_struct->oc_mode;
+ break;
+
+ case TMR_SELECT_CHANNEL_5:
+ tmr_x->cm3_output_bit.c5octrl = tmr_output_struct->oc_mode;
+ break;
+
+ default:
+ break;
+ }
+
+ /* get channel polarity bit position in cctrl register */
+ channel_index = (uint16_t)(tmr_output_struct->oc_polarity << ((tmr_channel * 2) + 1));
+
+ /* get channel complementary polarity bit position in cctrl register */
+ channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << ((tmr_channel * 2) + 3));
+
+ if((tmr_x == TMR1) || (tmr_x == TMR8))
+ {
+ /* set output channel complementary polarity */
+ tmr_x->cctrl &= ~channel_c_index;
+ tmr_x->cctrl |= channel_c_index;
+ }
+
+ /* set output channel polarity */
+ tmr_x->cctrl &= ~channel_index;
+ tmr_x->cctrl |= channel_index;
+
+ /* get channel enable bit position in cctrl register */
+ channel_index = (uint16_t)(tmr_output_struct->oc_output_state << (tmr_channel * 2));
+
+ /* get channel complementary enable bit position in cctrl register */
+ channel_c_index = (uint16_t)(tmr_output_struct->occ_output_state << ((tmr_channel * 2) + 2));
+
+ if((tmr_x == TMR1) || (tmr_x == TMR8))
+ {
+ /* set output channel complementary enable bit */
+ tmr_x->cctrl &= ~channel_c_index;
+ tmr_x->cctrl |= channel_c_index;
+ }
+
+ /* set output channel enable bit */
+ tmr_x->cctrl &= ~channel_index;
+ tmr_x->cctrl |= channel_index;
+}
+
+/**
+ * @brief select tmr output channel mode
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_5
+ * @param oc_mode
+ * this parameter can be one of the following values:
+ * - TMR_OUTPUT_CONTROL_OFF
+ * - TMR_OUTPUT_CONTROL_HIGH
+ * - TMR_OUTPUT_CONTROL_LOW
+ * - TMR_OUTPUT_CONTROL_SWITCH
+ * - TMR_OUTPUT_CONTROL_FORCE_HIGH
+ * - TMR_OUTPUT_CONTROL_FORCE_LOW
+ * - TMR_OUTPUT_CONTROL_PWM_MODE_A
+ * - TMR_OUTPUT_CONTROL_PWM_MODE_B
+ * @retval none
+ */
+void tmr_output_channel_mode_select(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_output_control_mode_type oc_mode)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cm1_output_bit.c1octrl = oc_mode;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cm1_output_bit.c2octrl = oc_mode;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cm2_output_bit.c3octrl = oc_mode;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cm2_output_bit.c4octrl = oc_mode;
+ break;
+
+ case TMR_SELECT_CHANNEL_5:
+ tmr_x->cm3_output_bit.c5octrl = oc_mode;
+ break;
+
+ default:
+ break;
+ }
+}
+/**
+ * @brief set tmr period value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_pr_value: timer period register value of counter
+ * (for 16 bit tmr 0x0000~0xFFFF,
+ * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
+ * @retval none
+ */
+void tmr_period_value_set(tmr_type *tmr_x, uint32_t tmr_pr_value)
+{
+ /* set tmr period value */
+ tmr_x->pr = tmr_pr_value;
+}
+
+/**
+ * @brief get tmr period value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @retval timer period register value of counter
+ * (for 16 bit tmr 0x0000~0xFFFF, for 32 bit tmr
+ * 0x0000_0000~0xFFFF_FFFF)
+ */
+uint32_t tmr_period_value_get(tmr_type *tmr_x)
+{
+ return tmr_x->pr;
+}
+
+/**
+ * @brief set tmr channel value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_5
+ * @param tmr_channel_value (for 16 bit tmr 0x0000~0xFFFF,
+ * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
+ * @retval none
+ */
+void tmr_channel_value_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ uint32_t tmr_channel_value)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ /* set tmr channel value */
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->c1dt = tmr_channel_value;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->c2dt = tmr_channel_value;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->c3dt = tmr_channel_value;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->c4dt = tmr_channel_value;
+ break;
+
+ case TMR_SELECT_CHANNEL_5:
+ tmr_x->c5dt = tmr_channel_value;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief get tmr channel value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_5
+ * @retval tmr channel value
+ */
+uint32_t tmr_channel_value_get(tmr_type *tmr_x, tmr_channel_select_type tmr_channel)
+{
+ uint32_t cc_value_get = 0;
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ /* get tmr channel value */
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ cc_value_get = tmr_x->c1dt;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ cc_value_get = tmr_x->c2dt;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ cc_value_get = tmr_x->c3dt;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ cc_value_get = tmr_x->c4dt;
+ break;
+
+ case TMR_SELECT_CHANNEL_5:
+ cc_value_get = tmr_x->c5dt;
+ break;
+
+ default:
+ break;
+ }
+
+ return cc_value_get;
+}
+/**
+ * @brief set tmr period buffer
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_period_buffer_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+ /* tmr period buffer set */
+ tmr_x->ctrl1_bit.prben = new_state;
+}
+
+/**
+ * @brief set tmr output channel buffer
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_5
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ confirm_state new_state)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ /* get tmr channel value */
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cm1_output_bit.c1oben = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cm1_output_bit.c2oben = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cm2_output_bit.c3oben = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cm2_output_bit.c4oben = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_5:
+ tmr_x->cm3_output_bit.c5oben = new_state;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief set tmr output channel immediately
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_5
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ confirm_state new_state)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ /* get tmr channel value */
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cm1_output_bit.c1oien = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cm1_output_bit.c2oien = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cm2_output_bit.c3oien = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cm2_output_bit.c4oien = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_5:
+ tmr_x->cm3_output_bit.c5oien = new_state;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief set tmr output channel switch
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_5
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ confirm_state new_state)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ /* get tmr channel value */
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cm1_output_bit.c1osen = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cm1_output_bit.c2osen = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cm2_output_bit.c3osen = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cm2_output_bit.c4osen = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_5:
+ tmr_x->cm3_output_bit.c5osen = new_state;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief enable or disable tmr one cycle mode
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TMR9, TMR12, TMR20
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+ /* tmr one cycle mode enable */
+ tmr_x->ctrl1_bit.ocmen = new_state;
+}
+
+/**
+ * @brief enable or disable tmr 32 bit function(plus mode)
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR2, TMR5
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_32_bit_function_enable (tmr_type *tmr_x, confirm_state new_state)
+{
+ /* tmr 32 bit function(plus mode) enable,only for TMR2/TMR5 */
+ if((tmr_x == TMR2) || (tmr_x == TMR5))
+ {
+ tmr_x->ctrl1_bit.pmen = new_state;
+ }
+}
+
+/**
+ * @brief select tmr the overflow event sources
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_overflow_request_source_set(tmr_type *tmr_x, confirm_state new_state)
+{
+ tmr_x->ctrl1_bit.ovfs = new_state;
+}
+
+/**
+ * @brief enable or disable tmr overflow event generation
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_overflow_event_disable(tmr_type *tmr_x, confirm_state new_state)
+{
+ tmr_x->ctrl1_bit.ovfen = new_state;
+}
+
+/**
+ * @brief init tmr input channel
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param input_struct
+ * - to the structure of tmr_input_config_type
+ * @param divider_factor
+ * this parameter can be one of the following values:
+ * - TMR_CHANNEL_INPUT_DIV_1
+ * - TMR_CHANNEL_INPUT_DIV_2
+ * - TMR_CHANNEL_INPUT_DIV_4
+ * - TMR_CHANNEL_INPUT_DIV_8
+ * @retval none
+ */
+void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
+ tmr_channel_input_divider_type divider_factor)
+{
+ uint16_t channel = 0;
+
+ /* get channel selected */
+ channel = input_struct->input_channel_select;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select;
+ tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1;
+ tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select;
+ tmr_x->cm1_input_bit.c1df = input_struct->input_filter_value;
+ tmr_x->cm1_input_bit.c1idiv = divider_factor;
+ tmr_x->cctrl_bit.c1en = TRUE;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select;
+ tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1;
+ tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select;
+ tmr_x->cm1_input_bit.c2df = input_struct->input_filter_value;
+ tmr_x->cm1_input_bit.c2idiv = divider_factor;
+ tmr_x->cctrl_bit.c2en = TRUE;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select;
+ tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1;
+ tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select;
+ tmr_x->cm2_input_bit.c3df = input_struct->input_filter_value;
+ tmr_x->cm2_input_bit.c3idiv = divider_factor;
+ tmr_x->cctrl_bit.c3en = TRUE;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select;
+ tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select;
+ tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value;
+ tmr_x->cm2_input_bit.c4idiv = divider_factor;
+ tmr_x->cctrl_bit.c4en = TRUE;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief tmr channel enable
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_1C
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_2C
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_3C
+ * - TMR_SELECT_CHANNEL_4
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_channel_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cctrl_bit.c1en = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_1C:
+ tmr_x->cctrl_bit.c1cen = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cctrl_bit.c2en = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_2C:
+ tmr_x->cctrl_bit.c2cen = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cctrl_bit.c3en = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_3C:
+ tmr_x->cctrl_bit.c3cen = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cctrl_bit.c4en = new_state;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief set tmr input channel filter
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * @param filter_value (0x0~0xf)
+ * @retval none
+ */
+void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ uint16_t filter_value)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cm1_input_bit.c1df = filter_value;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cm1_input_bit.c2df = filter_value;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cm2_input_bit.c3df = filter_value;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cm2_input_bit.c4df = filter_value;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief config tmr pwm input
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param input_struct
+ * - to the structure of tmr_input_config_type
+ * @param divider_factor
+ * this parameter can be one of the following values:
+ * - TMR_CHANNEL_INPUT_DIV_1
+ * - TMR_CHANNEL_INPUT_DIV_2
+ * - TMR_CHANNEL_INPUT_DIV_4
+ * - TMR_CHANNEL_INPUT_DIV_8
+ * @retval none
+ */
+void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
+ tmr_channel_input_divider_type divider_factor)
+{
+ uint16_t channel = 0;
+
+ /* get channel selected */
+ channel = input_struct->input_channel_select;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ if(input_struct->input_polarity_select == TMR_INPUT_RISING_EDGE)
+ {
+ /* set channel polarity */
+ tmr_x->cctrl_bit.c1p = TMR_INPUT_RISING_EDGE;
+ tmr_x->cctrl_bit.c2p = TMR_INPUT_FALLING_EDGE;
+ }
+ else if(input_struct->input_polarity_select == TMR_INPUT_FALLING_EDGE)
+ {
+ /* set channel polarity */
+ tmr_x->cctrl_bit.c1p = TMR_INPUT_FALLING_EDGE;
+ tmr_x->cctrl_bit.c2p = TMR_INPUT_RISING_EDGE;
+ }
+
+ if(input_struct->input_mapped_select == TMR_CC_CHANNEL_MAPPED_DIRECT)
+ {
+ /* ic1 is mapped on ti1 */
+ tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+
+ /* ic1 is mapped on ti2 */
+ tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_INDIRECT;
+ }
+ else if(input_struct->input_mapped_select == TMR_CC_CHANNEL_MAPPED_INDIRECT)
+ {
+ /* ic1 is mapped on ti1 */
+ tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_INDIRECT;
+
+ /* ic1 is mapped on ti2 */
+ tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+ }
+
+ /* set input ch1 and ch2 filter value*/
+ tmr_x->cm1_input_bit.c1df = input_struct->input_filter_value;
+ tmr_x->cm1_input_bit.c2df = input_struct->input_filter_value;
+
+ /*set input ch1 and ch2 divider value*/
+ tmr_x->cm1_input_bit.c1idiv = divider_factor;
+ tmr_x->cm1_input_bit.c2idiv = divider_factor;
+
+ tmr_x->cctrl_bit.c1en = TRUE;
+ tmr_x->cctrl_bit.c2en = TRUE;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ if(input_struct->input_polarity_select == TMR_INPUT_RISING_EDGE)
+ {
+ /* set channel polarity */
+ tmr_x->cctrl_bit.c2p = TMR_INPUT_RISING_EDGE;
+ tmr_x->cctrl_bit.c1p = TMR_INPUT_FALLING_EDGE;
+ }
+ else if(input_struct->input_polarity_select == TMR_INPUT_FALLING_EDGE)
+ {
+ /* set channel polarity */
+ tmr_x->cctrl_bit.c2p = TMR_INPUT_FALLING_EDGE;
+ tmr_x->cctrl_bit.c1p = TMR_INPUT_RISING_EDGE;
+ }
+
+ if(input_struct->input_mapped_select == TMR_CC_CHANNEL_MAPPED_DIRECT)
+ {
+ /* set mapped direct */
+ tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+ tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_INDIRECT;
+ }
+ else if(input_struct->input_mapped_select == TMR_CC_CHANNEL_MAPPED_INDIRECT)
+ {
+ /* set mapped direct */
+ tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_INDIRECT;
+ tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+ }
+
+ /* set input ch1 and ch2 filter value*/
+ tmr_x->cm1_input_bit.c1df = input_struct->input_filter_value;
+ tmr_x->cm1_input_bit.c2df = input_struct->input_filter_value;
+
+ /*set input ch1 and ch2 divider value*/
+ tmr_x->cm1_input_bit.c1idiv = divider_factor;
+ tmr_x->cm1_input_bit.c2idiv = divider_factor;
+
+ tmr_x->cctrl_bit.c1en = TRUE;
+ tmr_x->cctrl_bit.c2en = TRUE;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief select tmr channel1 input
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR20
+ * @param ti1_connect
+ * this parameter can be one of the following values:
+ * - TMR_CHANEL1_CONNECTED_C1IRAW
+ * - TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR
+ * @retval none
+ */
+void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ti1_connect)
+{
+ tmr_x->ctrl2_bit.c1insel = ti1_connect;
+}
+
+/**
+ * @brief set tmr input channel divider
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * @param divider_factor
+ * this parameter can be one of the following values:
+ * - TMR_CHANNEL_INPUT_DIV_1
+ * - TMR_CHANNEL_INPUT_DIV_2
+ * - TMR_CHANNEL_INPUT_DIV_4
+ * - TMR_CHANNEL_INPUT_DIV_8
+ * @retval none
+ */
+void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_channel_input_divider_type divider_factor)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cm1_input_bit.c1idiv = divider_factor;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cm1_input_bit.c2idiv = divider_factor;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cm2_input_bit.c3idiv = divider_factor;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cm2_input_bit.c4idiv = divider_factor;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief select tmr primary mode
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TMR20
+ * @param primary_mode
+ * this parameter can be one of the following values:
+ * - TMR_PRIMARY_SEL_RESET
+ * - TMR_PRIMARY_SEL_ENABLE
+ * - TMR_PRIMARY_SEL_OVERFLOW
+ * - TMR_PRIMARY_SEL_COMPARE
+ * - TMR_PRIMARY_SEL_C1ORAW
+ * - TMR_PRIMARY_SEL_C2ORAW
+ * - TMR_PRIMARY_SEL_C3ORAW
+ * - TMR_PRIMARY_SEL_C4ORAW
+ * @retval none
+ */
+void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode)
+{
+ tmr_x->ctrl2_bit.ptos = primary_mode;
+}
+
+/**
+ * @brief select tmr subordinate mode
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR12, TMR20
+ * @param sub_mode
+ * this parameter can be one of the following values:
+ * - TMR_SUB_MODE_DIABLE
+ * - TMR_SUB_ENCODER_MODE_A
+ * - TMR_SUB_ENCODER_MODE_B
+ * - TMR_SUB_ENCODER_MODE_C
+ * - TMR_SUB_RESET_MODE
+ * - TMR_SUB_HANG_MODE
+ * - TMR_SUB_TRIGGER_MODE
+ * - TMR_SUB_EXTERNAL_CLOCK_MODE_A
+
+ * @retval none
+ */
+void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode)
+{
+ tmr_x->stctrl_bit.smsel = sub_mode;
+}
+
+/**
+ * @brief select tmr channel dma
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR12, TMR20
+ * @param cc_dma_select
+ * this parameter can be one of the following values:
+ * - TMR_DMA_REQUEST_BY_CHANNEL
+ * - TMR_DMA_REQUEST_BY_OVERFLOW
+ * @retval none
+ */
+void tmr_channel_dma_select(tmr_type *tmr_x, tmr_dma_request_source_type cc_dma_select)
+{
+ tmr_x->ctrl2_bit.drs = cc_dma_select;
+}
+
+/**
+ * @brief select tmr hall
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR8, TMR20
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_hall_select(tmr_type *tmr_x, confirm_state new_state)
+{
+ tmr_x->ctrl2_bit.ccfs = new_state;
+}
+
+/**
+ * @brief select tmr channel buffer
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR8, TMR20
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_channel_buffer_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+ tmr_x->ctrl2_bit.cbctrl = new_state;
+}
+
+/**
+ * @brief select tmr trgout2
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR8, TMR20
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_trgout2_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+ tmr_x->ctrl2_bit.trgout2en = new_state;
+}
+
+/**
+ * @brief select tmr sub-trigger
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR12, TMR20
+ * @param trigger_select
+ * this parameter can be one of the following values:
+ * - TMR_SUB_INPUT_SEL_IS0
+ * - TMR_SUB_INPUT_SEL_IS1
+ * - TMR_SUB_INPUT_SEL_IS2
+ * - TMR_SUB_INPUT_SEL_IS3
+ * - TMR_SUB_INPUT_SEL_C1INC
+ * - TMR_SUB_INPUT_SEL_C1DF1
+ * - TMR_SUB_INPUT_SEL_C2DF2
+ * - TMR_SUB_INPUT_SEL_EXTIN
+ * @retval none
+ */
+void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_select)
+{
+ tmr_x->stctrl_bit.stis = trigger_select;
+}
+
+/**
+ * @brief set tmr subordinate synchronization mode
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR12, TMR20
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state)
+{
+ tmr_x->stctrl_bit.sts = new_state;
+}
+
+/**
+ * @brief enable or disable tmr dma request
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param dma_request
+ * this parameter can be one of the following values:
+ * - TMR_OVERFLOW_DMA_REQUEST
+ * - TMR_C1_DMA_REQUEST
+ * - TMR_C2_DMA_REQUEST
+ * - TMR_C3_DMA_REQUEST
+ * - TMR_C4_DMA_REQUEST
+ * - TMR_HALL_DMA_REQUEST
+ * - TMR_TRIGGER_DMA_REQUEST
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ {
+ tmr_x->iden |= dma_request;
+ }
+ else if(new_state == FALSE)
+ {
+ tmr_x->iden &= ~dma_request;
+ }
+}
+
+/**
+ * @brief enable or disable tmr interrupt
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_interrupt
+ * this parameter can be one of the following values:
+ * - TMR_OVF_INT
+ * - TMR_C1_INT
+ * - TMR_C2_INT
+ * - TMR_C3_INT
+ * - TMR_C4_INT
+ * - TMR_HALL_INT
+ * - TMR_TRIGGER_INT
+ * - TMR_BRK_INT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ {
+ tmr_x->iden |= tmr_interrupt;
+ }
+ else if(new_state == FALSE)
+ {
+ tmr_x->iden &= ~tmr_interrupt;
+ }
+}
+
+/**
+ * @brief get tmr flag
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_flag
+ * this parameter can be one of the following values:
+ * - TMR_OVF_FLAG
+ * - TMR_C1_FLAG
+ * - TMR_C2_FLAG
+ * - TMR_C3_FLAG
+ * - TMR_C4_FLAG
+ * - TMR_HALL_FLAG
+ * - TMR_TRIGGER_FLAG
+ * - TMR_BRK_FLAG
+ * - TMR_C1_RECAPTURE_FLAG
+ * - TMR_C2_RECAPTURE_FLAG
+ * - TMR_C3_RECAPTURE_FLAG
+ * - TMR_C4_RECAPTURE_FLAG
+ * @retval state of tmr flag
+ */
+flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag)
+{
+ flag_status status = RESET;
+
+ if((tmr_x->ists & tmr_flag) != RESET)
+ {
+ status = SET;
+ }
+ else
+ {
+ status = RESET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief clear tmr flag
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_flag
+ * this parameter can be any combination of the following values:
+ * - TMR_OVF_FLAG
+ * - TMR_C1_FLAG
+ * - TMR_C2_FLAG
+ * - TMR_C3_FLAG
+ * - TMR_C4_FLAG
+ * - TMR_HALL_FLAG
+ * - TMR_TRIGGER_FLAG
+ * - TMR_BRK_FLAG
+ * - TMR_C1_RECAPTURE_FLAG
+ * - TMR_C2_RECAPTURE_FLAG
+ * - TMR_C3_RECAPTURE_FLAG
+ * - TMR_C4_RECAPTURE_FLAG
+ * @retval none
+ */
+void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag)
+{
+ tmr_x->ists = ~tmr_flag;
+}
+
+/**
+ * @brief generate tmr event
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_event
+ * this parameter can be one of the following values:
+ * - TMR_OVERFLOW_SWTRIG
+ * - TMR_C1_SWTRIG
+ * - TMR_C2_SWTRIG
+ * - TMR_C3_SWTRIG
+ * - TMR_C4_SWTRIG
+ * - TMR_HALL_SWTRIG
+ * - TMR_TRIGGER_SWTRIG
+ * - TMR_BRK_SWTRIG
+ * @retval none
+ */
+void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event)
+{
+ tmr_x->swevt |= tmr_event;
+}
+
+/**
+ * @brief tmr output enable(oen),this function is important for advtm output enable
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR8, TMR20
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+ tmr_x->brk_bit.oen = new_state;
+}
+
+/**
+ * @brief set tmr select internal clock
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR12, TMR20
+ * @retval none
+ */
+void tmr_internal_clock_set(tmr_type *tmr_x)
+{
+ tmr_x->stctrl_bit.smsel = TMR_SUB_MODE_DIABLE;
+}
+
+/**
+ * @brief set tmr output channel fast
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param oc_fast
+ * this parameter can be one of the following values:
+ * - TMR_CHANNEL1_OUTPUT_FAST
+ * - TMR_CHANNEL2_OUTPUT_FAST
+ * - TMR_CHANNEL3_OUTPUT_FAST
+ * - TMR_CHANNEL4_OUTPUT_FAST
+ * @retval none
+ */
+void tmr_output_channel_fast_set(tmr_type *tmr_x, tmr_channel_output_fast_type oc_fast)
+{
+ PERIPH_REG((uint32_t)(tmr_x), oc_fast) |= PERIPH_REG_BIT(oc_fast);
+}
+
+/**
+ * @brief set tmr output channel polarity
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_1C
+ * - TMR_SELECT_CHANNEL_2C
+ * - TMR_SELECT_CHANNEL_3C
+ * @param oc_polarity
+ * this parameter can be one of the following values:
+ * - TMR_POLARITY_ACTIVE_HIGH
+ * - TMR_POLARITY_ACTIVE_LOW
+ * @retval none
+ */
+void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_polarity_active_type oc_polarity)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cctrl_bit.c1p = (uint32_t)oc_polarity;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cctrl_bit.c2p = (uint32_t)oc_polarity;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cctrl_bit.c3p = (uint32_t)oc_polarity;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cctrl_bit.c4p = (uint32_t)oc_polarity;
+ break;
+
+ case TMR_SELECT_CHANNEL_1C:
+ tmr_x->cctrl_bit.c1cp = (uint32_t)oc_polarity;
+ break;
+
+ case TMR_SELECT_CHANNEL_2C:
+ tmr_x->cctrl_bit.c2cp = (uint32_t)oc_polarity;
+ break;
+
+ case TMR_SELECT_CHANNEL_3C:
+ tmr_x->cctrl_bit.c3cp = (uint32_t)oc_polarity;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief config tmr external clock
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR20
+ * @param es_divide
+ * this parameter can be one of the following values:
+ * - TMR_ES_FREQUENCY_DIV_1
+ * - TMR_ES_FREQUENCY_DIV_2
+ * - TMR_ES_FREQUENCY_DIV_4
+ * - TMR_ES_FREQUENCY_DIV_8
+ * @param es_polarity
+ * this parameter can be one of the following values:
+ * - TMR_ES_POLARITY_NON_INVERTED
+ * - TMR_ES_POLARITY_INVERTED
+ * @param es_filter (0x0~0xf)
+ * @retval none
+ */
+void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+ tmr_external_signal_polarity_type es_polarity, uint16_t es_filter)
+{
+ tmr_x->stctrl_bit.esdiv = es_divide;
+ tmr_x->stctrl_bit.esp = es_polarity;
+ tmr_x->stctrl_bit.esf = es_filter;
+}
+
+/**
+ * @brief config tmr external clock mode1
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR12, TMR20
+ * @param es_divide
+ * this parameter can be one of the following values:
+ * - TMR_ES_FREQUENCY_DIV_1
+ * - TMR_ES_FREQUENCY_DIV_2
+ * - TMR_ES_FREQUENCY_DIV_4
+ * - TMR_ES_FREQUENCY_DIV_8
+ * @param es_polarity
+ * this parameter can be one of the following values:
+ * - TMR_ES_POLARITY_NON_INVERTED
+ * - TMR_ES_POLARITY_INVERTED
+ * @param es_filter (0x0~0xf)
+ * @retval none
+ */
+void tmr_external_clock_mode1_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+ tmr_external_signal_polarity_type es_polarity, uint16_t es_filter)
+{
+ tmr_external_clock_config(tmr_x, es_divide, es_polarity, es_filter);
+ tmr_x->stctrl_bit.smsel = TMR_SUB_EXTERNAL_CLOCK_MODE_A;
+ tmr_x->stctrl_bit.stis = TMR_SUB_INPUT_SEL_EXTIN;
+}
+
+/**
+ * @brief config tmr external clock mode2
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR20
+ * @param es_divide
+ * this parameter can be one of the following values:
+ * - TMR_ES_FREQUENCY_DIV_1
+ * - TMR_ES_FREQUENCY_DIV_2
+ * - TMR_ES_FREQUENCY_DIV_4
+ * - TMR_ES_FREQUENCY_DIV_8
+ * @param es_polarity
+ * this parameter can be one of the following values:
+ * - TMR_ES_POLARITY_NON_INVERTED
+ * - TMR_ES_POLARITY_INVERTED
+ * @param es_filter (0x0~0xf)
+ * @retval none
+ */
+void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+ tmr_external_signal_polarity_type es_polarity, uint16_t es_filter)
+{
+ tmr_external_clock_config(tmr_x, es_divide, es_polarity, es_filter);
+ tmr_x->stctrl_bit.ecmben = TRUE;
+}
+
+/**
+ * @brief config tmr encoder mode
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR20
+ * @param encoder_mode
+ * this parameter can be one of the following values:
+ * - TMR_ENCODER_MODE_A
+ * - TMR_ENCODER_MODE_B
+ * - TMR_ENCODER_MODE_C
+ * @param ic1_polarity
+ * this parameter can be one of the following values:
+ * - TMR_INPUT_RISING_EDGE
+ * - TMR_INPUT_FALLING_EDGE
+ * - TMR_INPUT_BOTH_EDGE
+ * @param ic2_polarity
+ * this parameter can be one of the following values:
+ * - TMR_INPUT_RISING_EDGE
+ * - TMR_INPUT_FALLING_EDGE
+ * - TMR_INPUT_BOTH_EDGE
+ * @retval none
+ */
+void tmr_encoder_mode_config(tmr_type *tmr_x, tmr_encoder_mode_type encoder_mode, tmr_input_polarity_type \
+ ic1_polarity, tmr_input_polarity_type ic2_polarity)
+{
+ tmr_x->stctrl_bit.smsel = encoder_mode;
+
+ /* set ic1 polarity */
+ tmr_x->cctrl_bit.c1p = (ic1_polarity & 0x1);
+ tmr_x->cctrl_bit.c1cp = (ic1_polarity >> 1);
+ /* set ic1 as input channel */
+ tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+
+ /* set ic2 polarity */
+ tmr_x->cctrl_bit.c2p = (ic2_polarity & 0x1);
+ tmr_x->cctrl_bit.c2cp = (ic2_polarity >> 1);
+ /* set ic2 as input channel */
+ tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+}
+
+/**
+ * @brief set tmr force output
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14, TMR20
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_5
+ * @param force_output
+ * this parameter can be one of the following values:
+ * - TMR_FORCE_OUTPUT_HIGH
+ * - TMR_FORCE_OUTPUT_LOW
+ * @retval none
+ */
+void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_force_output_type force_output)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cm1_output_bit.c1octrl = force_output;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cm1_output_bit.c2octrl = force_output;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cm2_output_bit.c3octrl = force_output;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cm2_output_bit.c4octrl = force_output;
+ break;
+
+ case TMR_SELECT_CHANNEL_5:
+ tmr_x->cm3_output_bit.c5octrl = force_output;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief config tmr dma control
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR20
+ * @param dma_length
+ * this parameter can be one of the following values:
+ * - TMR_DMA_TRANSFER_1BYTE
+ * - TMR_DMA_TRANSFER_2BYTES
+ * - TMR_DMA_TRANSFER_3BYTES
+ * ...
+ * - TMR_DMA_TRANSFER_17BYTES
+ * - TMR_DMA_TRANSFER_18BYTES
+ * @param dma_base_address
+ * this parameter can be one of the following values:
+ * - TMR_CTRL1_ADDRESS
+ * - TMR_CTRL2_ADDRESS
+ * - TMR_STCTRL_ADDRESS
+ * - TMR_IDEN_ADDRESS
+ * - TMR_ISTS_ADDRESS
+ * - TMR_SWEVT_ADDRESS
+ * - TMR_CM1_ADDRESS
+ * - TMR_CM2_ADDRESS
+ * - TMR_CCTRL_ADDRESS
+ * - TMR_CVAL_ADDRESS
+ * - TMR_DIV_ADDRESS
+ * - TMR_PR_ADDRESS
+ * - TMR_RPR_ADDRESS
+ * - TMR_C1DT_ADDRESS
+ * - TMR_C2DT_ADDRESS
+ * - TMR_C3DT_ADDRESS
+ * - TMR_C4DT_ADDRESS
+ * - TMR_BRK_ADDRESS
+ * - TMR_DMACTRL_ADDRESS
+ * @retval none
+ */
+void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \
+ tmr_dma_address_type dma_base_address)
+{
+ tmr_x->dmactrl_bit.dtb = dma_length;
+ tmr_x->dmactrl_bit.addr = dma_base_address;
+}
+
+/**
+ * @brief config tmr break mode and dead-time
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR8, TMR20
+ * @param brkdt_struct
+ * - to the structure of tmr_brkdt_config_type
+ * @retval none
+ */
+void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct)
+{
+ tmr_x->brk_bit.brken = brkdt_struct->brk_enable;
+ tmr_x->brk_bit.dtc = brkdt_struct->deadtime;
+ tmr_x->brk_bit.fcsodis = brkdt_struct->fcsodis_state;
+ tmr_x->brk_bit.fcsoen = brkdt_struct->fcsoen_state;
+ tmr_x->brk_bit.brkv = brkdt_struct->brk_polarity;
+ tmr_x->brk_bit.aoen = brkdt_struct->auto_output_enable;
+ tmr_x->brk_bit.wpc = brkdt_struct->wp_level;
+}
+
+/**
+ * @brief set tmr2/tmr5 input channel remap
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR2, TMR5
+ * @param input_remap
+ * - TMR2_TMR8TRGOUT_TMR5_GPIO
+ * - TMR2_PTP_TMR5_LICK
+ * - TMR2_OTG1FS_TMR5_LEXT
+ * - TMR2_OTG2FS_TMR5_ERTC
+ * @retval none
+ */
+void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap)
+{
+ if(tmr_x == TMR2)
+ {
+ tmr_x->rmp_bit.tmr2_ch1_irmp = input_remap;
+ }
+ else if(tmr_x == TMR5)
+ {
+ tmr_x->rmp_bit.tmr5_ch4_irmp = input_remap;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_usart.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_usart.c
new file mode 100644
index 0000000..c875e24
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_usart.c
@@ -0,0 +1,719 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_usart.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the usart firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup USART
+ * @brief USART driver modules
+ * @{
+ */
+
+#ifdef USART_MODULE_ENABLED
+
+/** @defgroup USART_private_functions
+ * @{
+ */
+
+/**
+ * @brief deinitialize the usart peripheral registers to their default reset values.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7,or UART8.
+ * @retval none
+ */
+void usart_reset(usart_type* usart_x)
+{
+ if(usart_x == USART1)
+ {
+ crm_periph_reset(CRM_USART1_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_USART1_PERIPH_RESET, FALSE);
+ }
+ else if(usart_x == USART2)
+ {
+ crm_periph_reset(CRM_USART2_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_USART2_PERIPH_RESET, FALSE);
+ }
+ else if(usart_x == USART3)
+ {
+ crm_periph_reset(CRM_USART3_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_USART3_PERIPH_RESET, FALSE);
+ }
+ else if(usart_x == UART4)
+ {
+ crm_periph_reset(CRM_UART4_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_UART4_PERIPH_RESET, FALSE);
+ }
+ else if(usart_x == UART5)
+ {
+ crm_periph_reset(CRM_UART5_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_UART5_PERIPH_RESET, FALSE);
+ }
+ else if(usart_x == USART6)
+ {
+ crm_periph_reset(CRM_USART6_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_USART6_PERIPH_RESET, FALSE);
+ }
+ else if(usart_x == UART7)
+ {
+ crm_periph_reset(CRM_UART7_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_UART7_PERIPH_RESET, FALSE);
+ }
+ else if(usart_x == UART8)
+ {
+ crm_periph_reset(CRM_UART8_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_UART8_PERIPH_RESET, FALSE);
+ }
+}
+
+/**
+ * @brief initialize the usart peripheral according to the specified parameters.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 ,UART5, USART6, UART7 or UART8.
+ * @param baud_rate: configure the usart communication baud rate.
+ * @param data_bit: data bits transmitted or received in a frame
+ * this parameter can be one of the following values:
+ * - USART_DATA_7BITS
+ * - USART_DATA_8BITS
+ * - USART_DATA_9BITS.
+ * @param stop_bit: stop bits transmitted
+ * this parameter can be one of the following values:
+ * - USART_STOP_1_BIT
+ * - USART_STOP_0_5_BIT.
+ * - USART_STOP_2_BIT
+ * - USART_STOP_1_5_BIT.
+ * @retval none
+ */
+void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit)
+{
+ crm_clocks_freq_type clocks_freq;
+ uint32_t apb_clock, temp_val;
+ crm_clocks_freq_get(&clocks_freq);
+ if((usart_x == USART1) || (usart_x == USART6) || (usart_x == UART7) || (usart_x == UART8))
+ {
+ apb_clock = clocks_freq.apb2_freq;
+ }
+ else
+ {
+ apb_clock = clocks_freq.apb1_freq;
+ }
+ temp_val = (apb_clock * 10 / baud_rate);
+ if((temp_val % 10) < 5)
+ {
+ temp_val = (temp_val / 10);
+ }
+ else
+ {
+ temp_val = (temp_val / 10) + 1;
+ }
+ usart_x->baudr_bit.div = temp_val;
+ if(data_bit == USART_DATA_7BITS)
+ {
+ usart_x->ctrl1_bit.dbn_h = 1;
+ usart_x->ctrl1_bit.dbn_l = 0;
+ }
+ else if(data_bit == USART_DATA_8BITS)
+ {
+ usart_x->ctrl1_bit.dbn_h = 0;
+ usart_x->ctrl1_bit.dbn_l = 0;
+ }
+ else
+ {
+ usart_x->ctrl1_bit.dbn_h = 0;
+ usart_x->ctrl1_bit.dbn_l = 1;
+ }
+ usart_x->ctrl2_bit.stopbn = stop_bit;
+}
+
+/**
+ * @brief usart parity selection config.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 ,UART5, USART6, UART7 or UART8.
+ * @param parity: select the none, odd or even parity.
+ * this parameter can be one of the following values:
+ * - USART_PARITY_NONE
+ * - USART_PARITY_EVEN.
+ * - USART_PARITY_ODD
+ * @retval none
+ */
+void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity)
+{
+ if(parity == USART_PARITY_NONE)
+ {
+ usart_x->ctrl1_bit.psel = FALSE;
+ usart_x->ctrl1_bit.pen = FALSE;
+ }
+ else if(parity == USART_PARITY_EVEN)
+ {
+ usart_x->ctrl1_bit.psel = FALSE;
+ usart_x->ctrl1_bit.pen = TRUE;
+ }
+ else if(parity == USART_PARITY_ODD)
+ {
+ usart_x->ctrl1_bit.psel = TRUE;
+ usart_x->ctrl1_bit.pen = TRUE;
+ }
+}
+
+/**
+ * @brief enable or disable the specified usart peripheral.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @param new_state: new state of the usart peripheral.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl1_bit.uen = new_state;
+}
+
+/**
+ * @brief usart transmitter enable.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 ,UART5, USART6, UART7 or UART8.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl1_bit.ten = new_state;
+}
+
+/**
+ * @brief usart receiver enable.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 ,UART5, USART6, UART7 or UART8.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void usart_receiver_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl1_bit.ren = new_state;
+}
+
+/**
+ * @brief usart clock config.
+ * @note clock config are not available for UART4, UART5, UART7 and UART8.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3 or USART6.
+ * @param clk_pol: polarity of the clock output on the ck pin.
+ * this parameter can be one of the following values:
+ * - USART_CLOCK_POLARITY_LOW
+ * - USART_CLOCK_POLARITY_HIGH
+ * @param clk_pha: phase of the clock output on the ck pin.
+ * this parameter can be one of the following values:
+ * - USART_CLOCK_PHASE_1EDGE
+ * - USART_CLOCK_PHASE_2EDGE
+ * @param clk_lb: whether the clock pulse of the last data bit transmitted (MSB) is outputted on the ck pin.
+ * this parameter can be one of the following values:
+ * - USART_CLOCK_LAST_BIT_NONE
+ * - USART_CLOCK_LAST_BIT_OUTPUT
+ * @retval none
+ */
+void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb)
+{
+ usart_x->ctrl2_bit.clkpol = clk_pol;
+ usart_x->ctrl2_bit.clkpha = clk_pha;
+ usart_x->ctrl2_bit.lbcp = clk_lb;
+}
+
+/**
+ * @brief usart enable the ck pin.
+ * @note clock enable are not available for UART4, UART5, UART7 and UART8.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3 or USART6.
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void usart_clock_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl2_bit.clken = new_state;
+}
+
+/**
+ * @brief enable or disable the specified usart interrupts.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @param usart_int: specifies the USART interrupt sources to be enabled or disabled.
+ * this parameter can be one of the following values:
+ * - USART_IDLE_INT: idle interrupt
+ * - USART_RDBF_INT: rdbf interrupt
+ * - USART_TDC_INT: tdc interrupt
+ * - USART_TDBE_INT: tdbe interrupt
+ * - USART_PERR_INT: perr interrupt
+ * - USART_BF_INT: break frame interrupt
+ * - USART_ERR_INT: err interrupt
+ * - USART_CTSCF_INT: ctscf interrupt
+ * @param new_state: new state of the specified usart interrupts.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ PERIPH_REG((uint32_t)usart_x, usart_int) |= PERIPH_REG_BIT(usart_int);
+ else
+ PERIPH_REG((uint32_t)usart_x, usart_int) &= ~PERIPH_REG_BIT(usart_int);
+}
+
+/**
+ * @brief enable or disable the usart's dma transmitter interface.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @param new_state: new state of the dma request sources.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl3_bit.dmaten = new_state;
+}
+
+/**
+ * @brief enable or disable the usart's dma receiver interface.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @param new_state: new state of the dma request sources.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl3_bit.dmaren = new_state;
+}
+
+/**
+ * @brief set the wakeup id of the usart.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @param usart_id: the matching id(0x0~0xFF).
+ * @retval none
+ */
+void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id)
+{
+ if(usart_x->ctrl2_bit.idbn == USART_ID_FIXED_4_BIT)
+ {
+ usart_x->ctrl2_bit.id_l = (usart_id & 0x0F);
+ usart_x->ctrl2_bit.id_h = 0;
+ }
+ else
+ {
+ usart_x->ctrl2_bit.id_l = (usart_id & 0x0F);
+ usart_x->ctrl2_bit.id_h = ((usart_id & 0xF0) >> 4);
+ }
+}
+
+/**
+ * @brief select the usart wakeup method in multi-processor communication.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @param wakeup_mode: determines the way to wake up usart method.
+ * this parameter can be one of the following values:
+ * - USART_WAKEUP_BY_IDLE_FRAME
+ * - USART_WAKEUP_BY_MATCHING_ID
+ * @retval none
+ */
+void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode)
+{
+ usart_x->ctrl1_bit.wum = wakeup_mode;
+}
+
+/**
+ * @brief config the usart in mute mode in multi-processor communication.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @param new_state: new state of the usart mute mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl1_bit.rm = new_state;
+}
+
+/**
+ * @brief set the usart break frame bit num.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @param break_bit: specifies the break bit num.
+ * this parameter can be one of the following values:
+ * - USART_BREAK_10BITS
+ * - USART_BREAK_11BITS
+ * @retval none
+ */
+void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit)
+{
+ usart_x->ctrl2_bit.bfbn = break_bit;
+}
+
+/**
+ * @brief enable or disable the usart lin mode.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @param new_state: new state of the usart lin mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl2_bit.linen = new_state;
+}
+
+/**
+ * @brief transmit single data through the usart peripheral.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @param data: the data to transmit.
+ * @retval none
+ */
+void usart_data_transmit(usart_type* usart_x, uint16_t data)
+{
+ usart_x->dt = (data & 0x01FF);
+}
+
+/**
+ * @brief return the most recent received data by the usart peripheral.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @retval the received data.
+ */
+uint16_t usart_data_receive(usart_type* usart_x)
+{
+ return (uint16_t)(usart_x->dt);
+}
+
+/**
+ * @brief transmit break characters.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @retval none
+ */
+void usart_break_send(usart_type* usart_x)
+{
+ usart_x->ctrl1_bit.sbf = TRUE;
+}
+
+/**
+ * @brief config the specified usart smartcard guard time.
+ * @note The guard time bits are not available for UART4, UART5, UART7 or UART8.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3 or USART6.
+ * @param guard_time_val: specifies the guard time (0x00~0xFF).
+ * @retval none
+ */
+void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val)
+{
+ usart_x->gdiv_bit.scgt = guard_time_val;
+}
+
+/**
+ * @brief config the irda/smartcard division.
+ * @note the division are not available for UART4, UART5, UART7 or UART8.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3 or USART6.
+ * @param div_val: specifies the division.
+ * @retval none
+ */
+void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val)
+{
+ usart_x->gdiv_bit.isdiv = div_val;
+}
+
+/**
+ * @brief enable or disable the usart smart card mode.
+ * @note the smart card mode are not available for UART4, UART5, UART7 or UART8.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3 or USART6.
+ * @param new_state: new state of the smart card mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl3_bit.scmen = new_state;
+}
+
+/**
+ * @brief enable or disable nack transmission in smartcard mode.
+ * @note the smart card nack are not available for UART4, UART5, UART7 or UART8.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3 or USART6.
+ * @param new_state: new state of the nack transmission.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl3_bit.scnacken = new_state;
+}
+
+/**
+ * @brief enable or disable the usart single line bidirectional half-duplex communication.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @param new_state: new state of the single line half-duplex select.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl3_bit.slben = new_state;
+}
+
+/**
+ * @brief enable or disable the usart's irda interface.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @param new_state: new state of the irda mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl3_bit.irdaen = new_state;
+}
+
+/**
+ * @brief configure the usart's irda low power.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @param new_state: new state of the irda mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl3_bit.irdalp = new_state;
+}
+
+/**
+ * @brief configure the usart's hardware flow control.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3
+ * @param flow_state: specifies the hardware flow control.
+ * this parameter can be one of the following values:
+ * - USART_HARDWARE_FLOW_NONE
+ * - USART_HARDWARE_FLOW_RTS,
+ * - USART_HARDWARE_FLOW_CTS,
+ * - USART_HARDWARE_FLOW_RTS_CTS
+ * @retval none
+ */
+void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state)
+{
+ if(flow_state == USART_HARDWARE_FLOW_NONE)
+ {
+ usart_x->ctrl3_bit.rtsen = FALSE;
+ usart_x->ctrl3_bit.ctsen = FALSE;
+ }
+ else if(flow_state == USART_HARDWARE_FLOW_RTS)
+ {
+ usart_x->ctrl3_bit.rtsen = TRUE;
+ usart_x->ctrl3_bit.ctsen = FALSE;
+ }
+ else if(flow_state == USART_HARDWARE_FLOW_CTS)
+ {
+ usart_x->ctrl3_bit.rtsen = FALSE;
+ usart_x->ctrl3_bit.ctsen = TRUE;
+ }
+ else if(flow_state == USART_HARDWARE_FLOW_RTS_CTS)
+ {
+ usart_x->ctrl3_bit.rtsen = TRUE;
+ usart_x->ctrl3_bit.ctsen = TRUE;
+ }
+}
+
+/**
+ * @brief check whether the specified usart flag is set or not.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - USART_CTSCF_FLAG: cts change flag (not available for UART4,UART5,USART6,UART7 and UART8)
+ * - USART_BFF_FLAG: break frame flag
+ * - USART_TDBE_FLAG: transmit data buffer empty flag
+ * - USART_TDC_FLAG: transmit data complete flag
+ * - USART_RDBF_FLAG: receive data buffer full flag
+ * - USART_IDLEF_FLAG: idle flag
+ * - USART_ROERR_FLAG: receiver overflow error flag
+ * - USART_NERR_FLAG: noise error flag
+ * - USART_FERR_FLAG: framing error flag
+ * - USART_PERR_FLAG: parity error flag
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status usart_flag_get(usart_type* usart_x, uint32_t flag)
+{
+ if(usart_x->sts & flag)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief clear the usart's pending flags.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7 or UART8.
+ * @param flag: specifies the flag to clear.
+ * this parameter can be any combination of the following values:
+ * - USART_CTSCF_FLAG: (not available for UART4,UART5,USART6,UART7 and UART8).
+ * - USART_BFF_FLAG:
+ * - USART_TDC_FLAG:
+ * - USART_RDBF_FLAG:
+ * @note
+ * - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software
+ * sequence: a read operation to usart sts register (usart_flag_get())
+ * followed by a read operation to usart dt register (usart_data_receive()).
+ * - USART_RDBF_FLAG can be also cleared by a read to the usart dt register(usart_data_receive()).
+ * - USART_TDC_FLAG can be also cleared by software sequence: a read operation to usart sts register (usart_flag_get())
+ * followed by a write operation to usart dt register (usart_data_transmit()).
+ * - USART_TDBE_FLAG is cleared only by a write to the usart dt register(usart_data_transmit()).
+ * @retval none
+ */
+void usart_flag_clear(usart_type* usart_x, uint32_t flag)
+{
+ usart_x->sts = ~flag;
+}
+
+/**
+ * @brief configure the usart's rs485 transmit delay time.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3
+ * @param start_delay_time: transmit start delay time.
+ * @param complete_delay_time: transmit complete delay time.
+ * @retval none
+ */
+void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time)
+{
+ usart_x->ctrl1_bit.tsdt = start_delay_time;
+ usart_x->ctrl1_bit.tcdt = complete_delay_time;
+}
+
+/**
+ * @brief swap the usart's transmit receive pin.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7,or UART8.
+ * @param new_state: new state of the usart peripheral.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl2_bit.trpswap = new_state;
+}
+
+/**
+ * @brief set the usart's identification bit num.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4, UART5, USART6, UART7,or UART8.
+ * @param id_bit_num: the usart wakeup identification bit num.
+ * this parameter can be: USART_ID_FIXED_4_BIT or USART_ID_RELATED_DATA_BIT.
+ * @retval none
+ */
+void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type id_bit_num)
+{
+ usart_x->ctrl2_bit.idbn = (uint8_t)id_bit_num;
+}
+
+/**
+ * @brief set the usart's de polarity.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3
+ * @param de_polarity: the usart de polarity selection.
+ * this parameter can be: USART_DE_POLARITY_HIGH or USART_DE_POLARITY_LOW.
+ * @retval none
+ */
+void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity)
+{
+ usart_x->ctrl3_bit.dep = (uint8_t)de_polarity;
+}
+
+/**
+ * @brief enable or disable the usart's rs485 mode.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3
+ * @param new_state: new state of the irda mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl3_bit.rs485en = new_state;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_usb.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_usb.c
new file mode 100644
index 0000000..199b716
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_usb.c
@@ -0,0 +1,1097 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_usb.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the usb firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup USB
+ * @brief USB driver modules
+ * @{
+ */
+
+#ifdef USB_MODULE_ENABLED
+
+/** @defgroup USB_private_functions
+ * @{
+ */
+
+#ifdef OTGFS_USB_GLOBAL
+/**
+ * @brief usb global core soft reset
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval error status
+ */
+error_status usb_global_reset(otg_global_type *usbx)
+{
+ uint32_t timeout = 0;
+ while(usbx->grstctl_bit.ahbidle == RESET)
+ {
+ if(timeout ++ > 200000)
+ {
+ break;
+ }
+ }
+ timeout = 0;
+ usbx->grstctl_bit.csftrst = TRUE;
+ while(usbx->grstctl_bit.csftrst == SET)
+ {
+ if(timeout ++ > 200000)
+ {
+ break;
+ }
+ }
+ return SUCCESS;
+}
+
+/**
+ * @brief usb global initialization
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval none
+ */
+void usb_global_init(otg_global_type *usbx)
+{
+ /* reset otg moudle */
+ usb_global_reset(usbx);
+
+ /* exit power down mode */
+ usbx->gccfg_bit.pwrdown = TRUE;
+}
+
+/**
+ * @brief usb global select usb core (otg1 or otg2).
+ * @param usb_id: select otg1 or otg2
+ * this parameter can be one of the following values:
+ * - USB_OTG1_ID
+ * - USB_OTG2_ID
+ * @retval usb global register type pointer
+ */
+otg_global_type *usb_global_select_core(uint8_t usb_id)
+{
+ if(usb_id == USB_OTG1_ID)
+ {
+ /* use otg1 */
+ return OTG1_GLOBAL;
+ }
+ else
+ {
+ /* use otg2 */
+ return OTG2_GLOBAL;
+ }
+}
+
+/**
+ * @brief flush tx fifo
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param fifo_num: tx fifo num,when fifo_num=16,flush all tx fifo
+ * parameter as following values: 0-16
+ * @retval none
+ */
+void usb_flush_tx_fifo(otg_global_type *usbx, uint32_t fifo_num)
+{
+ uint32_t timeout = 0;
+ /* set flush fifo number */
+ usbx->grstctl_bit.txfnum = fifo_num;
+
+ /* start flush fifo */
+ usbx->grstctl_bit.txfflsh = TRUE;
+
+ while(usbx->grstctl_bit.txfflsh == TRUE)
+ {
+ if(timeout ++ > 200000)
+ {
+ break;
+ }
+ }
+}
+
+/**
+ * @brief flush rx fifo
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval none
+ */
+void usb_flush_rx_fifo(otg_global_type *usbx)
+{
+ uint32_t timeout = 0;
+ usbx->grstctl_bit.rxfflsh = TRUE;
+ while(usbx->grstctl_bit.rxfflsh == TRUE)
+ {
+ if(timeout ++ > 200000)
+ {
+ break;
+ }
+ }
+}
+
+/**
+ * @brief usb interrupt mask enable
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param interrupt:
+ * this parameter can be any combination of the following values:
+ * - USB_OTG_MODEMIS_INT
+ * - USB_OTG_OTGINT_INT
+ * - USB_OTG_SOF_INT
+ * - USB_OTG_RXFLVL_INT
+ * - USB_OTG_NPTXFEMP_INT
+ * - USB_OTG_GINNAKEFF_INT
+ * - USB_OTG_GOUTNAKEFF_INT
+ * - USB_OTG_ERLYSUSP_INT
+ * - USB_OTG_USBSUSP_INT
+ * - USB_OTG_USBRST_INT
+ * - USB_OTG_ENUMDONE_INT
+ * - USB_OTG_ISOOUTDROP_INT
+ * - USB_OTG_IEPT_INT
+ * - USB_OTG_OEPT_INT
+ * - USB_OTG_INCOMISOIN_INT
+ * - USB_OTG_INCOMPIP_INCOMPISOOUT_INT
+ * - USB_OTG_PRT_INT
+ * - USB_OTG_HCH_INT
+ * - USB_OTG_PTXFEMP_INT
+ * - USB_OTG_CONIDSCHG_INT
+ * - USB_OTG_DISCON_INT
+ * - USB_OTG_WKUP_INT
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void usb_global_interrupt_enable(otg_global_type *usbx, uint16_t interrupt, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ {
+ usbx->gintmsk |= interrupt;
+ }
+ else
+ {
+ usbx->gintmsk &= ~interrupt;
+ }
+}
+
+/**
+ * @brief get all global core interrupt flag
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval intterupt flag
+ */
+uint32_t usb_global_get_all_interrupt(otg_global_type *usbx)
+{
+ uint32_t intsts = usbx->gintsts;
+ return intsts & usbx->gintmsk;
+}
+
+/**
+ * @brief clear the global interrupt flag
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param flag: interrupt flag
+ * this parameter can be any combination of the following values:
+ * - USB_OTG_MODEMIS_FLAG
+ * - USB_OTG_OTGINT_FLAG
+ * - USB_OTG_SOF_FLAG
+ * - USB_OTG_RXFLVL_FLAG
+ * - USB_OTG_NPTXFEMP_FLAG
+ * - USB_OTG_GINNAKEFF_FLAG
+ * - USB_OTG_GOUTNAKEFF_FLAG
+ * - USB_OTG_ERLYSUSP_FLAG
+ * - USB_OTG_USBSUSP_FLAG
+ * - USB_OTG_USBRST_FLAG
+ * - USB_OTG_ENUMDONE_FLAG
+ * - USB_OTG_ISOOUTDROP_FLAG
+ * - USB_OTG_EOPF_FLAG
+ * - USB_OTG_IEPT_FLAG
+ * - USB_OTG_OEPT_FLAG
+ * - USB_OTG_INCOMISOIN_FLAG
+ * - USB_OTG_INCOMPIP_INCOMPISOOUT_FLAG
+ * - USB_OTG_PRT_FLAG
+ * - USB_OTG_HCH_FLAG
+ * - USB_OTG_PTXFEMP_FLAG
+ * - USB_OTG_CONIDSCHG_FLAG
+ * - USB_OTG_DISCON_FLAG
+ * - USB_OTG_WKUP_FLAG
+ * @retval none
+ */
+void usb_global_clear_interrupt(otg_global_type *usbx, uint32_t flag)
+{
+ usbx->gintsts = flag;
+}
+
+/**
+ * @brief usb global interrupt enable
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * OTG1_GLOBAL , OTG2_GLOBAL
+ * @retval none
+ */
+void usb_interrupt_enable(otg_global_type *usbx)
+{
+ usbx->gahbcfg_bit.glbintmsk = TRUE;
+}
+
+/**
+ * @brief usb global interrupt disable
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval none
+ */
+void usb_interrupt_disable(otg_global_type *usbx)
+{
+ usbx->gahbcfg_bit.glbintmsk = FALSE;
+}
+
+/**
+ * @brief usb set rx fifo size
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param size: rx fifo size
+ * @retval none
+ */
+void usb_set_rx_fifo(otg_global_type *usbx, uint16_t size)
+{
+ usbx->grxfsiz = size;
+}
+
+/**
+ * @brief usb set tx fifo size
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param txfifo: the fifo number
+ * @param size: tx fifo size
+ * @retval none
+ */
+void usb_set_tx_fifo(otg_global_type *usbx, uint8_t txfifo, uint16_t size)
+{
+ uint8_t i_index = 0;
+ uint32_t offset = 0;
+
+ offset = usbx->grxfsiz;
+ if(txfifo == 0)
+ {
+ usbx->gnptxfsiz_ept0tx = offset | (size << 16);
+ }
+ else
+ {
+ offset += usbx->gnptxfsiz_ept0tx_bit.nptxfdep;
+ for(i_index = 0; i_index < (txfifo - 1); i_index ++)
+ {
+ offset += usbx->dieptxfn_bit[i_index].ineptxfdep;
+ }
+ usbx->dieptxfn[txfifo - 1] = offset | (size << 16);
+ }
+}
+
+
+/**
+ * @brief set otg mode(device or host mode)
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param mode:
+ this parameter can be one of the following values:
+ * - OTG_DEVICE_MODE
+ * - OTG_HOST_MODE
+ * - OTG_DRD_MODE
+ * @retval none
+ */
+void usb_global_set_mode(otg_global_type *usbx, uint32_t mode)
+{
+ /* set otg to device mode */
+ if(mode == OTG_DEVICE_MODE)
+ {
+ usbx->gusbcfg_bit.fhstmode = FALSE;
+ usbx->gusbcfg_bit.fdevmode = TRUE;
+ }
+
+ /* set otg to host mode */
+ if(mode == OTG_HOST_MODE)
+ {
+ usbx->gusbcfg_bit.fdevmode = FALSE;
+ usbx->gusbcfg_bit.fhstmode = TRUE;
+ }
+
+ /* set otg to default mode */
+ if(mode == OTG_DRD_MODE)
+ {
+ usbx->gusbcfg_bit.fdevmode = FALSE;
+ usbx->gusbcfg_bit.fhstmode = FALSE;
+ }
+}
+
+
+/**
+ * @brief disable the transceiver power down mode
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval none
+ */
+void usb_global_power_on(otg_global_type *usbx)
+{
+ /* core soft reset */
+ usbx->grstctl_bit.csftrst = TRUE;
+ while(usbx->grstctl_bit.csftrst);
+
+ /* disable power down mode */
+ usbx->gccfg_bit.pwrdown = TRUE;
+
+}
+
+/**
+ * @brief usb stop phy clock
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval none
+ */
+void usb_stop_phy_clk(otg_global_type *usbx)
+{
+ OTG_PCGCCTL(usbx)->pcgcctl_bit.stoppclk = TRUE;
+}
+
+/**
+ * @brief usb open phy clock
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval none
+ */
+void usb_open_phy_clk(otg_global_type *usbx)
+{
+ OTG_PCGCCTL(usbx)->pcgcctl_bit.stoppclk = FALSE;
+}
+
+
+/**
+ * @brief write data from user memory to usb buffer
+ * @param pusr_buf: point to user buffer
+ * @param offset_addr: endpoint tx offset address
+ * @param nbytes: number of bytes data write to usb buffer
+ * @retval none
+ */
+void usb_write_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uint16_t nbytes)
+{
+ uint32_t n_index;
+ uint32_t nhbytes = (nbytes + 3) / 4;
+ uint32_t *pbuf = (uint32_t *)pusr_buf;
+ for(n_index = 0; n_index < nhbytes; n_index ++)
+ {
+#if defined (__ICCARM__) && (__VER__ < 7000000)
+ USB_FIFO(usbx, num) = *(__packed uint32_t *)pbuf;
+#else
+ USB_FIFO(usbx, num) = __UNALIGNED_UINT32_READ(pbuf);
+#endif
+ pbuf ++;
+ }
+}
+
+/**
+ * @brief read data from usb buffer to user buffer
+ * @param pusr_buf: point to user buffer
+ * @param offset_addr: endpoint rx offset address
+ * @param nbytes: number of bytes data write to usb buffer
+ * @retval none
+ */
+void usb_read_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uint16_t nbytes)
+{
+ uint32_t n_index;
+ uint32_t nhbytes = (nbytes + 3) / 4;
+ uint32_t *pbuf = (uint32_t *)pusr_buf;
+ for(n_index = 0; n_index < nhbytes; n_index ++)
+ {
+#if defined (__ICCARM__) && (__VER__ < 7000000)
+ *(__packed uint32_t *)pbuf = USB_FIFO(usbx, 0);
+#else
+ __UNALIGNED_UINT32_WRITE(pbuf, (USB_FIFO(usbx, 0)));
+#endif
+ pbuf ++;
+ }
+}
+#endif
+
+
+#ifdef OTGFS_USB_DEVICE
+/**
+ * @brief open usb endpoint
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param ept_info: endpoint information structure
+ * @retval none
+ */
+void usb_ept_open(otg_global_type *usbx, usb_ept_info *ept_info)
+{
+ uint8_t mps = USB_EPT0_MPS_64;
+ if(ept_info->eptn == USB_EPT0)
+ {
+ if(ept_info->maxpacket == 0x40)
+ {
+ mps = USB_EPT0_MPS_64;
+ }
+ else if(ept_info->maxpacket == 0x20)
+ {
+ mps = USB_EPT0_MPS_32;
+ }
+ else if(ept_info->maxpacket == 0x10)
+ {
+ mps = USB_EPT0_MPS_16;
+ }
+ else if(ept_info->maxpacket == 0x08)
+ {
+ mps = USB_EPT0_MPS_8;
+ }
+ }
+ /* endpoint direction is in */
+ if(ept_info->inout == EPT_DIR_IN)
+ {
+ OTG_DEVICE(usbx)->daintmsk |= 1 << ept_info->eptn;
+ if(ept_info->eptn == USB_EPT0)
+ {
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.mps = mps;
+ }
+ else
+ {
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.mps = ept_info->maxpacket;
+ }
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.eptype = ept_info->trans_type;
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.txfnum = ept_info->eptn;
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.setd0pid = TRUE;
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.usbacept = TRUE;
+ }
+ /* endpoint direction is out */
+ else
+ {
+ OTG_DEVICE(usbx)->daintmsk |= (1 << ept_info->eptn) << 16;
+ if(ept_info->eptn == USB_EPT0)
+ {
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.mps = mps;
+ }
+ else
+ {
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.mps = ept_info->maxpacket;
+ }
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.eptype = ept_info->trans_type;
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.setd0pid = TRUE;
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.usbacept = TRUE;
+ }
+}
+
+/**
+ * @brief close usb endpoint
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param ept_info: endpoint information structure
+ * @retval none
+ */
+void usb_ept_close(otg_global_type *usbx, usb_ept_info *ept_info)
+{
+ if(ept_info->inout == EPT_DIR_IN)
+ {
+ OTG_DEVICE(usbx)->daintmsk &= ~(1 << ept_info->eptn);
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.usbacept = FALSE;
+ }
+ else
+ {
+ OTG_DEVICE(usbx)->daintmsk &= ~((1 << ept_info->eptn) << 16);
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.usbacept = FALSE;
+ }
+}
+
+
+/**
+ * @brief set endpoint tx or rx status to stall
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param ept_info: endpoint information structure
+ * @retval none
+ */
+void usb_ept_stall(otg_global_type *usbx, usb_ept_info *ept_info)
+{
+ if(ept_info->inout == EPT_DIR_IN)
+ {
+ if(USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.eptena == RESET)
+ {
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.eptdis = FALSE;
+ }
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.stall = SET;
+ }
+ else
+ {
+ if(USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.eptena == RESET)
+ {
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.eptdis = FALSE;
+ }
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.stall = TRUE;
+ }
+}
+
+/**
+ * @brief clear endpoint tx or rx status to stall
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param ept_info: endpoint information structure
+ * @retval none
+ */
+void usb_ept_clear_stall(otg_global_type *usbx, usb_ept_info *ept_info)
+{
+ if(ept_info->inout == EPT_DIR_IN)
+ {
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.stall = FALSE;
+ if(ept_info->trans_type == EPT_INT_TYPE || ept_info->trans_type == EPT_BULK_TYPE)
+ {
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.setd0pid = TRUE;
+ }
+ }
+ else
+ {
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.stall = FALSE;
+ if(ept_info->trans_type == EPT_INT_TYPE || ept_info->trans_type == EPT_BULK_TYPE)
+ {
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.setd0pid = TRUE;
+ }
+ }
+}
+
+/**
+ * @brief get all out endpoint interrupt bits
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval out endpoint interrupt bits
+ */
+uint32_t usb_get_all_out_interrupt(otg_global_type *usbx)
+{
+ uint32_t intsts = OTG_DEVICE(usbx)->daint;
+ return ((intsts & (OTG_DEVICE(usbx)->daintmsk)) >> 16);
+}
+
+/**
+ * @brief get all in endpoint interrupt bits
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval in endpoint interrupt bits
+ */
+uint32_t usb_get_all_in_interrupt(otg_global_type *usbx)
+{
+ uint32_t intsts = OTG_DEVICE(usbx)->daint;
+ return ((intsts & (OTG_DEVICE(usbx)->daintmsk)) & 0xFFFF);
+}
+
+
+/**
+ * @brief get out endpoint interrupt flag
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param eptn: endpoint number
+ * @retval out endpoint interrupt flags
+ */
+uint32_t usb_ept_out_interrupt(otg_global_type *usbx, uint32_t eptn)
+{
+ uint32_t intsts = USB_OUTEPT(usbx, eptn)->doepint;
+ return (intsts & (OTG_DEVICE(usbx)->doepmsk));
+}
+
+/**
+ * @brief get in endpoint interrupt flag
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param eptn: endpoint number
+ * @retval in endpoint intterupt flags
+ */
+uint32_t usb_ept_in_interrupt(otg_global_type *usbx, uint32_t eptn)
+{
+ uint32_t intsts, mask1, mask2;
+ mask1 = OTG_DEVICE(usbx)->diepmsk;
+ mask2 = OTG_DEVICE(usbx)->diepempmsk;
+ mask1 |= ((mask2 >> eptn) & 0x1) << 7;
+ intsts = USB_INEPT(usbx, eptn)->diepint & mask1;
+ return intsts;
+}
+
+/**
+ * @brief clear out endpoint interrupt flag
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param eptn: endpoint number
+ * @retval flag: interrupt flag
+ * this parameter can be any combination of the following values:
+ * - USB_OTG_DOEPINT_XFERC_FLAG
+ * - USB_OTG_DOEPINT_EPTDISD_FLAG
+ * - USB_OTG_DOEPINT_SETUP_FLAG
+ * - USB_OTG_DOEPINT_OTEPDIS_FLAG
+ * - USB_OTG_DOEPINT_B2BSTUP_FLAG
+ */
+void usb_ept_out_clear(otg_global_type *usbx, uint32_t eptn, uint32_t flag)
+{
+ USB_OUTEPT(usbx, eptn)->doepint = flag;
+}
+
+/**
+ * @brief clear in endpoint interrupt flag
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param eptn: endpoint number
+ * @retval flag: interrupt flag
+ * this parameter can be any combination of the following values:
+ * - USB_OTG_DIEPINT_XFERC_FLAG
+ * - USB_OTG_DIEPINT_EPTDISD_FLAG
+ * - USB_OTG_DIEPINT_TMROC_FLAG
+ * - USB_OTG_DIEPINT_INTTXFE_FLAG
+ * - USB_OTG_DIEPINT_INEPNE_FLAG
+ * - USB_OTG_DIEPINT_TXFE_FLAG
+ */
+void usb_ept_in_clear(otg_global_type *usbx, uint32_t eptn, uint32_t flag)
+{
+ USB_INEPT(usbx, eptn)->diepint = flag;
+}
+
+
+/**
+ * @brief set the host assignment address
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param address: host assignment address
+ * @retval none
+ */
+void usb_set_address(otg_global_type *usbx, uint8_t address)
+{
+ OTG_DEVICE(usbx)->dcfg_bit.devaddr = address;
+}
+
+/**
+ * @brief enable endpoint 0 out
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval none
+ */
+void usb_ept0_start(otg_global_type *usbx)
+{
+ otg_eptout_type *usb_outept = USB_OUTEPT(usbx, 0);
+ usb_outept->doeptsiz = 0;
+ usb_outept->doeptsiz_bit.pktcnt = 1;
+ usb_outept->doeptsiz_bit.xfersize = 24;
+ usb_outept->doeptsiz_bit.rxdpid_setupcnt = 3;
+}
+
+
+/**
+ * @brief endpoint 0 start setup
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval none
+ */
+void usb_ept0_setup(otg_global_type *usbx)
+{
+ USB_INEPT(usbx, 0)->diepctl_bit.mps = 0;
+ OTG_DEVICE(usbx)->dctl_bit.cgnpinak = FALSE;
+}
+
+/**
+ * @brief connect usb device by enable pull-up
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval none
+ */
+void usb_connect(otg_global_type *usbx)
+{
+ /* D+ 1.5k pull-up enable */
+ OTG_DEVICE(usbx)->dctl_bit.sftdiscon = FALSE;
+}
+
+/**
+ * @brief disconnect usb device by disable pull-up
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval none
+ */
+void usb_disconnect(otg_global_type *usbx)
+{
+ /* D+ 1.5k pull-up disable */
+ OTG_DEVICE(usbx)->dctl_bit.sftdiscon = TRUE;
+}
+
+
+/**
+ * @brief usb remote wakeup set
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval none
+ */
+void usb_remote_wkup_set(otg_global_type *usbx)
+{
+ OTG_DEVICE(usbx)->dctl_bit.rwkupsig = TRUE;
+}
+
+/**
+ * @brief usb remote wakeup clear
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval none
+ */
+void usb_remote_wkup_clear(otg_global_type *usbx)
+{
+ OTG_DEVICE(usbx)->dctl_bit.rwkupsig = FALSE;
+}
+
+/**
+ * @brief usb suspend status get
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval usb suspend status
+ */
+uint8_t usb_suspend_status_get(otg_global_type *usbx)
+{
+ return OTG_DEVICE(usbx)->dsts_bit.suspsts;
+}
+#endif
+
+#ifdef OTGFS_USB_HOST
+/**
+ * @brief usb port power on
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param state: state (TRUE or FALSE)
+ * @retval none
+ */
+void usb_port_power_on(otg_global_type *usbx, confirm_state state)
+{
+ otg_host_type *usb_host = OTG_HOST(usbx);
+ uint32_t hprt_val = usb_host->hprt;
+
+ hprt_val &= ~(USB_OTG_HPRT_PRTENA | USB_OTG_HPRT_PRTENCHNG |
+ USB_OTG_HPRT_PRTOVRCACT | USB_OTG_HPRT_PRTCONDET);
+
+ if(state == TRUE)
+ {
+ usb_host->hprt = hprt_val | USB_OTG_HPRT_PRTPWR;
+ }
+ else
+ {
+ usb_host->hprt = hprt_val & (~USB_OTG_HPRT_PRTPWR);
+ }
+}
+
+/**
+ * @brief get current frame number
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval none
+ */
+uint32_t usbh_get_frame(otg_global_type *usbx)
+{
+ otg_host_type *usb_host = OTG_HOST(usbx);
+ return usb_host->hfnum & 0xFFFF;
+}
+
+/**
+ * @brief enable one host channel
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param chn: host channel number
+ * @param ept_num: devvice endpoint number
+ * @param dev_address: device address
+ * @param type: channel transfer type
+ * this parameter can be one of the following values:
+ * - EPT_CONTROL_TYPE
+ * - EPT_BULK_TYPE
+ * - EPT_INT_TYPE
+ * - EPT_ISO_TYPE
+ * @param maxpacket: support max packe size for this channel
+ * @param speed: device speed
+ * this parameter can be one of the following values:
+ * - USB_PRTSPD_FULL_SPEED
+ * - USB_PRTSPD_LOW_SPEED
+ * @retval none
+ */
+void usb_hc_enable(otg_global_type *usbx,
+ uint8_t chn,
+ uint8_t ept_num,
+ uint8_t dev_address,
+ uint8_t type,
+ uint8_t maxpacket,
+ uint8_t speed)
+{
+ otg_hchannel_type *hch = USB_CHL(usbx, chn);
+ otg_host_type *usb_host = OTG_HOST(usbx);
+
+ switch(type)
+ {
+ case EPT_CONTROL_TYPE:
+ case EPT_BULK_TYPE:
+ hch->hcintmsk |= USB_OTG_HC_XFERCM_INT | USB_OTG_HC_STALLM_INT |
+ USB_OTG_HC_XACTERRM_INT | USB_OTG_HC_NAKM_INT |
+ USB_OTG_HC_DTGLERRM_INT;
+ if(ept_num & 0x80)
+ {
+ hch->hcintmsk_bit.bblerrmsk = TRUE;
+ }
+ break;
+ case EPT_INT_TYPE:
+ hch->hcintmsk |= USB_OTG_HC_XFERCM_INT | USB_OTG_HC_STALLM_INT |
+ USB_OTG_HC_XACTERRM_INT | USB_OTG_HC_NAKM_INT |
+ USB_OTG_HC_DTGLERRM_INT | USB_OTG_HC_FRMOVRRUN_INT;
+ break;
+ case EPT_ISO_TYPE:
+
+ hch->hcintmsk |= USB_OTG_HC_XFERCM_INT | USB_OTG_HC_ACKM_INT |
+ USB_OTG_HC_FRMOVRRUN_INT;
+ break;
+ }
+ usb_host->haintmsk |= 1 << chn;
+ usbx->gintmsk_bit.hchintmsk = TRUE;
+
+ hch->hcchar_bit.devaddr = dev_address;
+ hch->hcchar_bit.eptnum = ept_num & 0x7F;
+ hch->hcchar_bit.eptdir = (ept_num & 0x80)?1:0;
+ hch->hcchar_bit.lspddev = (speed == USB_PRTSPD_LOW_SPEED)?1:0;
+ hch->hcchar_bit.eptype = type;
+ hch->hcchar_bit.mps = maxpacket;
+
+ if(type == EPT_INT_TYPE)
+ {
+ hch->hcchar_bit.oddfrm = TRUE;
+ }
+}
+
+/**
+ * @brief host read channel interrupt
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval interrupt flag
+ */
+uint32_t usb_hch_read_interrupt(otg_global_type *usbx)
+{
+ otg_host_type *usb_host = OTG_HOST(usbx);
+ return usb_host->haint & 0xFFFF;
+}
+
+/**
+ * @brief disable host
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @retval none
+ */
+void usb_host_disable(otg_global_type *usbx)
+{
+ uint32_t i_index = 0, count = 0;
+ otg_hchannel_type *hch;
+ otg_host_type *usb_host = OTG_HOST(usbx);
+
+ usbx->gahbcfg_bit.glbintmsk = FALSE;
+ usb_flush_rx_fifo(usbx);
+ usb_flush_tx_fifo(usbx, 0x10);
+
+ for(i_index = 0; i_index < 16; i_index ++)
+ {
+ hch = USB_CHL(usbx, i_index);
+ hch->hcchar_bit.chdis = TRUE;
+ hch->hcchar_bit.chena = FALSE;
+ hch->hcchar_bit.eptdir = 0;
+ }
+
+ for(i_index = 0; i_index < 16; i_index ++)
+ {
+ hch = USB_CHL(usbx, i_index);
+ hch->hcchar_bit.chdis = TRUE;
+ hch->hcchar_bit.chena = TRUE;
+ hch->hcchar_bit.eptdir = 0;
+ do
+ {
+ if(count ++ > 1000)
+ break;
+ }while(hch->hcchar_bit.chena);
+ }
+ usb_host->haint = 0xFFFFFFFF;
+ usbx->gintsts = 0xFFFFFFFF;
+ usbx->gahbcfg_bit.glbintmsk = TRUE;
+}
+
+/**
+ * @brief halt channel
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param chn: channel number
+ * @retval none
+ */
+void usb_hch_halt(otg_global_type *usbx, uint8_t chn)
+{
+ uint32_t count = 0;
+ otg_hchannel_type *usb_chh = USB_CHL(usbx, chn);
+ otg_host_type *usb_host = OTG_HOST(usbx);
+
+ /* endpoint type is control or bulk */
+ if(usb_chh->hcchar_bit.eptype == EPT_CONTROL_TYPE ||
+ usb_chh->hcchar_bit.eptype == EPT_BULK_TYPE)
+ {
+ usb_chh->hcchar_bit.chdis = TRUE;
+ if((usbx->gnptxsts & 0xFFFF) == 0)
+ {
+ usb_chh->hcchar_bit.chena = FALSE;
+ usb_chh->hcchar_bit.chena = TRUE;
+ usb_chh->hcchar_bit.eptdir = 0;
+ do
+ {
+ if(count ++ > 1000)
+ break;
+ }while(usb_chh->hcchar_bit.chena == SET);
+ }
+ else
+ {
+ usb_chh->hcchar_bit.chena = TRUE;
+ }
+ }
+ else
+ {
+ usb_chh->hcchar_bit.chdis = TRUE;
+ if((usb_host->hptxsts & 0xFFFF) == 0)
+ {
+ usb_chh->hcchar_bit.chena = FALSE;
+ usb_chh->hcchar_bit.chena = TRUE;
+ usb_chh->hcchar_bit.eptdir = 0;
+ do
+ {
+ if(count ++ > 1000)
+ break;
+ }while(usb_chh->hcchar_bit.chena == SET);
+ }
+ else
+ {
+ usb_chh->hcchar_bit.chena = TRUE;
+ }
+ }
+}
+/**
+ * @brief select full or low speed clock
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param clk: clock frequency
+ * @retval none
+ */
+void usbh_fsls_clksel(otg_global_type *usbx, uint8_t clk)
+{
+ otg_host_type *usb_host = OTG_HOST(usbx);
+
+ usb_host->hcfg_bit.fslspclksel = clk;
+ if(clk == USB_HCFG_CLK_6M)
+ {
+ usb_host->hfir = 6000;
+ }
+ else
+ {
+ usb_host->hfir = 48000;
+ }
+}
+#endif
+
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_wdt.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_wdt.c
new file mode 100644
index 0000000..f5c3e86
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_wdt.c
@@ -0,0 +1,156 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_wdt.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the wdt firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup WDT
+ * @brief WDT driver modules
+ * @{
+ */
+
+#ifdef WDT_MODULE_ENABLED
+
+/** @defgroup WDT_private_functions
+ * @{
+ */
+
+/**
+ * @brief wdt enable ,the reload value will be sent to the counter
+ * @param none
+ * @retval none
+ */
+void wdt_enable(void)
+{
+ WDT->cmd = WDT_CMD_ENABLE;
+}
+
+/**
+ * @brief reload wdt counter
+ * @param none
+ * @retval none
+ */
+void wdt_counter_reload(void)
+{
+ WDT->cmd = WDT_CMD_RELOAD;
+}
+
+/**
+ * @brief set wdt counter reload value
+ * @param reload_value (0x0000~0x0FFF)
+ * @retval none
+ */
+void wdt_reload_value_set(uint16_t reload_value)
+{
+ WDT->rld = reload_value;
+}
+
+/**
+ * @brief set wdt division divider
+ * @param division
+ * this parameter can be one of the following values:
+ * - WDT_CLK_DIV_4
+ * - WDT_CLK_DIV_8
+ * - WDT_CLK_DIV_16
+ * - WDT_CLK_DIV_32
+ * - WDT_CLK_DIV_64
+ * - WDT_CLK_DIV_128
+ * - WDT_CLK_DIV_256
+ * @retval none
+ */
+void wdt_divider_set(wdt_division_type division)
+{
+ WDT->div_bit.div = division;
+}
+
+/**
+ * @brief enable or disable wdt cmd register write
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void wdt_register_write_enable( confirm_state new_state)
+{
+ if(new_state == FALSE)
+ {
+ WDT->cmd = WDT_CMD_LOCK;
+ }
+ else
+ {
+ WDT->cmd = WDT_CMD_UNLOCK;
+ }
+}
+
+/**
+ * @brief get wdt flag
+ * @param wdt_flag
+ * this parameter can be one of the following values:
+ * - WDT_DIVF_UPDATE_FLAG: division value update complete flag.
+ * - WDT_RLDF_UPDATE_FLAG: reload value update complete flag.
+ * - WDT_WINF_UPDATE_FLAG: window value update complete flag.
+ * @retval state of wdt flag
+ */
+flag_status wdt_flag_get(uint16_t wdt_flag)
+{
+ flag_status status = RESET;
+
+ if ((WDT->sts & wdt_flag) != (uint16_t)RESET)
+ {
+ status = SET;
+ }
+ else
+ {
+ status = RESET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief wdt window counter value set
+ * @param window_cnt (0x0000~0x0FFF)
+ * @retval none
+ */
+void wdt_window_counter_set(uint16_t window_cnt)
+{
+ WDT->win_bit.win = window_cnt;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_wwdt.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_wwdt.c
new file mode 100644
index 0000000..3f058d9
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_wwdt.c
@@ -0,0 +1,141 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_wwdt.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the wwdt firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup WWDT
+ * @brief WWDT driver modules
+ * @{
+ */
+
+#ifdef WWDT_MODULE_ENABLED
+
+/** @defgroup WWDT_private_functions
+ * @{
+ */
+
+/**
+ * @brief wwdt reset by crm reset register
+ * @retval none
+ */
+void wwdt_reset(void)
+{
+ crm_periph_reset(CRM_WWDT_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_WWDT_PERIPH_RESET, FALSE);
+}
+
+/**
+ * @brief wwdt division set
+ * @param division
+ * this parameter can be one of the following values:
+ * - WWDT_PCLK1_DIV_4096 (wwdt counter clock = (pclk1/4096)/1)
+ * - WWDT_PCLK1_DIV_8192 (wwdt counter clock = (pclk1/4096)/2)
+ * - WWDT_PCLK1_DIV_16384 (wwdt counter clock = (pclk1/4096)/4)
+ * - WWDT_PCLK1_DIV_32768 (wwdt counter clock = (pclk1/4096)/8)
+ * @retval none
+ */
+void wwdt_divider_set(wwdt_division_type division)
+{
+ WWDT->cfg_bit.div = division;
+}
+
+/**
+ * @brief wwdt reload counter interrupt flag clear
+ * @param none
+ * @retval none
+ */
+void wwdt_flag_clear(void)
+{
+ WWDT->sts = 0;
+}
+
+/**
+ * @brief wwdt enable and the counter value load
+ * @param wwdt_cnt (0x40~0x7f)
+ * @retval none
+ */
+void wwdt_enable(uint8_t wwdt_cnt)
+{
+ WWDT->ctrl = wwdt_cnt | WWDT_EN_BIT;
+}
+
+/**
+ * @brief wwdt reload counter interrupt enable
+ * @param none
+ * @retval none
+ */
+void wwdt_interrupt_enable(void)
+{
+ WWDT->cfg_bit.rldien = TRUE;
+}
+
+/**
+ * @brief wwdt reload counter interrupt flag get
+ * @param none
+ * @retval state of reload counter interrupt flag
+ */
+flag_status wwdt_flag_get(void)
+{
+ return (flag_status)WWDT->sts_bit.rldf;
+}
+
+/**
+ * @brief wwdt counter value set
+ * @param wwdt_cnt (0x40~0x7f)
+ * @retval none
+ */
+void wwdt_counter_set(uint8_t wwdt_cnt)
+{
+ WWDT->ctrl_bit.cnt = wwdt_cnt;
+}
+
+/**
+ * @brief wwdt window counter value set
+ * @param window_cnt (0x40~0x7f)
+ * @retval none
+ */
+void wwdt_window_counter_set(uint8_t window_cnt)
+{
+ WWDT->cfg_bit.win = window_cnt;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_xmc.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_xmc.c
new file mode 100644
index 0000000..e711cbe
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/at32f435_437_xmc.c
@@ -0,0 +1,909 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_xmc.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for the xmc firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f435_437_conf.h"
+
+/** @addtogroup AT32F435_437_periph_driver
+ * @{
+ */
+
+/** @defgroup XMC
+ * @brief XMC driver modules
+ * @{
+ */
+
+#ifdef XMC_MODULE_ENABLED
+
+/** @defgroup XMC_private_functions
+ * @{
+ */
+
+/**
+ * @brief xmc nor or sram registers reset
+ * @param xmc_subbank
+ * this parameter can be one of the following values:
+ * - XMC_BANK1_NOR_SRAM1
+ * - XMC_BANK1_NOR_SRAM2
+ * - XMC_BANK1_NOR_SRAM3
+ * - XMC_BANK1_NOR_SRAM4
+ * @retval none
+ */
+void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank)
+{
+ /* XMC_BANK1_NORSRAM1 */
+ if(xmc_subbank == XMC_BANK1_NOR_SRAM1)
+ {
+ XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030DB;
+ }
+ /* XMC_BANK1_NORSRAM2, XMC_BANK1_NORSRAM3 or XMC_BANK1_NORSRAM4 */
+ else
+ {
+ XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030D2;
+ }
+ XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1tmg = 0x0FFFFFFF;
+ XMC_BANK1->tmgwr_group[xmc_subbank].bk1tmgwr = 0x0FFFFFFF;
+}
+
+/**
+ * @brief initialize the xmc nor/sram banks according to the specified
+ * parameters in the xmc_norsraminitstruct.
+ * @param xmc_norsram_init_struct : pointer to a xmc_norsram_init_type
+ * structure that contains the configuration information for
+ * the xmc nor/sram specified banks.
+ * @retval none
+ */
+void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct)
+{
+ /* bank1 nor/sram control register configuration */
+ XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl =
+ (uint32_t)xmc_norsram_init_struct->data_addr_multiplex |
+ xmc_norsram_init_struct->device |
+ xmc_norsram_init_struct->bus_type |
+ xmc_norsram_init_struct->burst_mode_enable |
+ xmc_norsram_init_struct->asynwait_enable |
+ xmc_norsram_init_struct->wait_signal_lv |
+ xmc_norsram_init_struct->wrapped_mode_enable |
+ xmc_norsram_init_struct->wait_signal_config |
+ xmc_norsram_init_struct->write_enable |
+ xmc_norsram_init_struct->wait_signal_enable |
+ xmc_norsram_init_struct->write_timing_enable |
+ xmc_norsram_init_struct->write_burst_syn;
+
+ /* if nor flash device */
+ if(xmc_norsram_init_struct->device == XMC_DEVICE_NOR)
+ {
+ XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl_bit.noren = 0x1;
+ }
+}
+
+/**
+ * @brief initialize the xmc nor/sram banks according to the specified
+ * parameters in the xmc_rw_timing_struct and xmc_w_timing_struct.
+ * @param xmc_rw_timing_struct : pointer to a xmc_norsram_timing_init_type
+ * structure that contains the configuration information for
+ * the xmc nor/sram specified banks.
+ * @param xmc_w_timing_struct : pointer to a xmc_norsram_timing_init_type
+ * structure that contains the configuration information for
+ * the xmc nor/sram specified banks.
+ * @retval none
+ */
+void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
+ xmc_norsram_timing_init_type* xmc_w_timing_struct)
+{
+ /* bank1 nor/sram timing register configuration */
+ XMC_BANK1->ctrl_tmg_group[xmc_rw_timing_struct->subbank].bk1tmg =
+ (uint32_t)xmc_rw_timing_struct->addr_setup_time |
+ (xmc_rw_timing_struct->addr_hold_time << 4) |
+ (xmc_rw_timing_struct->data_setup_time << 8) |
+ (xmc_rw_timing_struct->bus_latency_time <<16) |
+ (xmc_rw_timing_struct->clk_psc << 20) |
+ (xmc_rw_timing_struct->data_latency_time << 24) |
+ xmc_rw_timing_struct->mode;
+
+ /* bank1 nor/sram timing register for write configuration, if extended mode is used */
+ if(xmc_rw_timing_struct->write_timing_enable == XMC_WRITE_TIMING_ENABLE)
+ {
+ XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr =
+ (uint32_t)xmc_w_timing_struct->addr_setup_time |
+ (xmc_w_timing_struct->addr_hold_time << 4) |
+ (xmc_w_timing_struct->data_setup_time << 8) |
+ (xmc_w_timing_struct->bus_latency_time << 16) |
+ (xmc_w_timing_struct->clk_psc << 20) |
+ (xmc_w_timing_struct->data_latency_time << 24) |
+ xmc_w_timing_struct->mode;
+ }
+ else
+ {
+ XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr = 0x0FFFFFFF;
+ }
+}
+
+/**
+ * @brief fill each xmc_nor_sram_init_struct member with its default value.
+ * @param xmc_nor_sram_init_struct: pointer to a xmc_norsram_init_type
+ * structure which will be initialized.
+ * @retval none
+ */
+void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct)
+{
+ /* reset nor/sram init structure parameters values */
+ xmc_nor_sram_init_struct->subbank = XMC_BANK1_NOR_SRAM1;
+ xmc_nor_sram_init_struct->data_addr_multiplex = XMC_DATA_ADDR_MUX_ENABLE;
+ xmc_nor_sram_init_struct->device = XMC_DEVICE_SRAM;
+ xmc_nor_sram_init_struct->bus_type = XMC_BUSTYPE_8_BITS;
+ xmc_nor_sram_init_struct->burst_mode_enable = XMC_BURST_MODE_DISABLE;
+ xmc_nor_sram_init_struct->asynwait_enable = XMC_ASYN_WAIT_DISABLE;
+ xmc_nor_sram_init_struct->wait_signal_lv = XMC_WAIT_SIGNAL_LEVEL_LOW;
+ xmc_nor_sram_init_struct->wrapped_mode_enable = XMC_WRAPPED_MODE_DISABLE;
+ xmc_nor_sram_init_struct->wait_signal_config = XMC_WAIT_SIGNAL_SYN_BEFORE;
+ xmc_nor_sram_init_struct->write_enable = XMC_WRITE_OPERATION_ENABLE;
+ xmc_nor_sram_init_struct->wait_signal_enable = XMC_WAIT_SIGNAL_ENABLE;
+ xmc_nor_sram_init_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
+ xmc_nor_sram_init_struct->write_burst_syn = XMC_WRITE_BURST_SYN_DISABLE;
+}
+
+/**
+ * @brief fill each xmc_rw_timing_struct and xmc_w_timing_struct member with its default value.
+ * @param xmc_rw_timing_struct: pointer to a xmc_norsram_timing_init_type
+ * structure which will be initialized.
+ * @param xmc_w_timing_struct: pointer to a xmc_norsram_timing_init_type
+ * structure which will be initialized.
+ * @retval none
+ */
+void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
+ xmc_norsram_timing_init_type* xmc_w_timing_struct)
+{
+ xmc_rw_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
+ xmc_rw_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
+ xmc_rw_timing_struct->addr_setup_time = 0xF;
+ xmc_rw_timing_struct->addr_hold_time = 0xF;
+ xmc_rw_timing_struct->data_setup_time = 0xFF;
+ xmc_rw_timing_struct->bus_latency_time = 0xF;
+ xmc_rw_timing_struct->clk_psc = 0xF;
+ xmc_rw_timing_struct->data_latency_time = 0xF;
+ xmc_rw_timing_struct->mode = XMC_ACCESS_MODE_A;
+ xmc_w_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
+ xmc_w_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
+ xmc_w_timing_struct->addr_setup_time = 0xF;
+ xmc_w_timing_struct->addr_hold_time = 0xF;
+ xmc_w_timing_struct->data_setup_time = 0xFF;
+ xmc_w_timing_struct->bus_latency_time = 0xF;
+ xmc_w_timing_struct->clk_psc = 0xF;
+ xmc_w_timing_struct->data_latency_time = 0xF;
+ xmc_w_timing_struct->mode = XMC_ACCESS_MODE_A;
+}
+
+/**
+ * @brief enable or disable the specified nor/sram memory bank.
+ * @param xmc_subbank
+ * this parameter can be one of the following values:
+ * - XMC_BANK1_NOR_SRAM1
+ * - XMC_BANK1_NOR_SRAM2
+ * - XMC_BANK1_NOR_SRAM3
+ * - XMC_BANK1_NOR_SRAM4
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state)
+{
+ XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl_bit.en = new_state;
+}
+
+/**
+ * @brief config the bus turnaround phase.
+ * @param xmc_sub_bank
+ * this parameter can be one of the following values:
+ * - XMC_BANK1_NOR_SRAM1
+ * - XMC_BANK1_NOR_SRAM2
+ * - XMC_BANK1_NOR_SRAM3
+ * - XMC_BANK1_NOR_SRAM4
+ * @param w2w_timing :write timing
+ * @param r2r_timing :read timing
+ * @retval none
+ */
+void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing)
+{
+ XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing<<8;
+ XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing;
+}
+
+/**
+ * @brief xmc nand flash registers reset
+ * @param xmc_bank
+ * this parameter can be one of the following values:
+ * - XMC_BANK2_NAND
+ * - XMC_BANK3_NAND
+ * @retval none
+ */
+void xmc_nand_reset(xmc_class_bank_type xmc_bank)
+{
+ /* set the xmc_bank2_nand registers to their reset values */
+ if(xmc_bank == XMC_BANK2_NAND)
+ {
+ XMC_BANK2->bk2ctrl = 0x00000018;
+ XMC_BANK2->bk2is = 0x00000040;
+ XMC_BANK2->bk2tmgatt = 0xFCFCFCFC;
+ XMC_BANK2->bk2tmgmem = 0xFCFCFCFC;
+ }
+ /* set the xmc_bank3_nand registers to their reset values */
+ else
+ {
+ XMC_BANK3->bk3ctrl = 0x00000018;
+ XMC_BANK3->bk3is = 0x00000040;
+ XMC_BANK3->bk3tmgatt = 0xFCFCFCFC;
+ XMC_BANK3->bk3tmgmem = 0xFCFCFCFC;
+ }
+}
+
+/**
+ * @brief initialize the xmc nand banks according to the specified
+ * parameters in the xmc_nandinitstruct.
+ * @param xmc_nand_init_struct : pointer to a xmc_nand_init_type
+ * structure that contains the configuration information for the xmc
+ * nand specified banks.
+ * @retval none
+ */
+void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct)
+{
+ uint32_t tempctrl = 0x0;
+
+ /* Set the tempctrl value according to xmc_nand_init_struct parameters */
+ tempctrl = (uint32_t)xmc_nand_init_struct->wait_enable |
+ xmc_nand_init_struct->bus_type |
+ xmc_nand_init_struct->ecc_enable |
+ xmc_nand_init_struct->ecc_pagesize |
+ (xmc_nand_init_struct->delay_time_cycle << 9) |
+ (xmc_nand_init_struct->delay_time_ar << 13) |
+ 0x00000008;
+
+ /* xmc_bank2_nand registers configuration */
+ if(xmc_nand_init_struct->nand_bank == XMC_BANK2_NAND)
+ {
+ XMC_BANK2->bk2ctrl = tempctrl;
+ }
+ /* xmc_bank3_nand registers configuration */
+ else
+ {
+ XMC_BANK3->bk3ctrl = tempctrl;
+ }
+}
+
+/**
+ * @brief initialize the xmc nand banks according to the specified
+ * parameters in the xmc_nandinitstruct.
+ * @param xmc_regular_spacetiming_struct : pointer to a xmc_nand_pccard_timinginit_type
+ * structure that contains the configuration information for the xmc
+ * nand specified banks.
+ * @param xmc_special_spacetiming_struct : pointer to a xmc_nand_pccard_timinginit_type
+ * structure that contains the configuration information for the xmc
+ * nand specified banks.
+ * @retval none
+ */
+void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct)
+{
+ uint32_t tempmem = 0x0, tempatt = 0x0;
+
+ /* set the tempmem value according to xmc_nand_init_struct parameters */
+ tempmem = (uint32_t)xmc_regular_spacetiming_struct->mem_setup_time |
+ (xmc_regular_spacetiming_struct->mem_waite_time << 8) |
+ (xmc_regular_spacetiming_struct->mem_hold_time << 16) |
+ (xmc_regular_spacetiming_struct->mem_hiz_time << 24);
+
+ /* set the tempatt value according to xmc_nand_init_struct parameters */
+ tempatt = (uint32_t)xmc_special_spacetiming_struct->mem_setup_time |
+ (xmc_special_spacetiming_struct->mem_waite_time << 8) |
+ (xmc_special_spacetiming_struct->mem_hold_time << 16) |
+ (xmc_special_spacetiming_struct->mem_hiz_time << 24);
+ /* xmc_bank2_nand registers configuration */
+ if(xmc_regular_spacetiming_struct->class_bank == XMC_BANK2_NAND)
+ {
+ XMC_BANK2->bk2tmgatt = tempatt;
+ XMC_BANK2->bk2tmgmem = tempmem;
+ }
+ else
+ {
+ XMC_BANK3->bk3tmgatt = tempatt;
+ XMC_BANK3->bk3tmgmem = tempmem;
+ }
+}
+
+/**
+ * @brief fill each xmc_nand_init_struct member with its default value.
+ * @param xmc_nand_init_struct: pointer to a xmc_nand_init_type
+ * structure which will be initialized.
+ * @retval none
+ */
+void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct)
+{
+ /* reset nand init structure parameters values */
+ xmc_nand_init_struct->nand_bank = XMC_BANK2_NAND;
+ xmc_nand_init_struct->wait_enable = XMC_WAIT_OPERATION_DISABLE;
+ xmc_nand_init_struct->bus_type = XMC_BUSTYPE_8_BITS;
+ xmc_nand_init_struct->ecc_enable = XMC_ECC_OPERATION_DISABLE;
+ xmc_nand_init_struct->ecc_pagesize = XMC_ECC_PAGESIZE_256_BYTES;
+ xmc_nand_init_struct->delay_time_cycle = 0x0;
+ xmc_nand_init_struct->delay_time_ar = 0x0;
+}
+
+/**
+ * @brief fill each xmc_common_spacetiming_struct and xmc_attribute_spacetiming_struct member with its default value.
+ * @param xmc_common_spacetiming_struct: pointer to a xmc_nand_pccard_timinginit_type
+ * structure which will be initialized.
+ * @param xmc_special_spacetiming_struct: pointer to a xmc_nand_pccard_timinginit_type
+ * structure which will be initialized.
+ * @retval none
+ */
+void xmc_nand_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct)
+{
+ xmc_regular_spacetiming_struct->class_bank = XMC_BANK2_NAND;
+ xmc_regular_spacetiming_struct->mem_hold_time = 0xFC;
+ xmc_regular_spacetiming_struct->mem_waite_time = 0xFC;
+ xmc_regular_spacetiming_struct->mem_setup_time = 0xFC;
+ xmc_regular_spacetiming_struct->mem_hiz_time = 0xFC;
+ xmc_special_spacetiming_struct->class_bank = XMC_BANK2_NAND;
+ xmc_special_spacetiming_struct->mem_hold_time = 0xFC;
+ xmc_special_spacetiming_struct->mem_waite_time = 0xFC;
+ xmc_special_spacetiming_struct->mem_setup_time = 0xFC;
+ xmc_special_spacetiming_struct->mem_hiz_time = 0xFC;
+}
+
+/**
+ * @brief enable or disable the specified nand memory bank.
+ * @param xmc_bank: specifies the xmc bank to be used
+ * this parameter can be one of the following values:
+ * - XMC_BANK2_NAND
+ * - XMC_BANK3_NAND
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
+{
+ /* enable or disable the nand bank2 by setting the en bit in the bk2ctrl register */
+ if(xmc_bank == XMC_BANK2_NAND)
+ {
+ XMC_BANK2->bk2ctrl_bit.en = new_state;
+ }
+ /* enable or disable the nand bank3 by setting the en bit in the bk3ctrl register */
+ else
+ {
+ XMC_BANK3->bk3ctrl_bit.en = new_state;
+ }
+}
+
+/**
+ * @brief enable or disable the xmc nand ecc feature.
+ * @param xmc_bank: specifies the xmc bank to be used
+ * this parameter can be one of the following values:
+ * - XMC_BANK2_NAND
+ * - XMC_BANK3_NAND
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state)
+{
+ /* enable the selected nand bank2 ecc function by setting the eccen bit in the bk2ctrl register */
+ if(xmc_bank == XMC_BANK2_NAND)
+ {
+ XMC_BANK2->bk2ctrl_bit.eccen = new_state;
+ }
+ /* enable the selected nand bank3 ecc function by setting the eccen bit in the bk3ctrl register */
+ else
+ {
+ XMC_BANK3->bk3ctrl_bit.eccen = new_state;
+ }
+}
+
+/**
+ * @brief return the error correction code register value.
+ * @param xmc_bank: specifies the xmc bank to be used
+ * this parameter can be one of the following values:
+ * - XMC_BANK2_NAND
+ * - XMC_BANK3_NAND
+ * @retval the error correction code (ecc) value.
+ */
+uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank)
+{
+ uint32_t eccvaule = 0x0;
+
+ /* get the bk2ecc register value */
+ if(xmc_bank == XMC_BANK2_NAND)
+ {
+ eccvaule = XMC_BANK2->bk2ecc;
+ }
+ /* get the bk3ecc register value */
+ else
+ {
+ eccvaule = XMC_BANK3->bk3ecc;
+ }
+ /* return the error correction code value */
+ return eccvaule;
+}
+
+/**
+ * @brief xmc sdram registers reset
+ * @param xmc_bank
+ * this parameter can be one of the following values:
+ * - XMC_SDRAM_BANK1
+ * - XMC_SDRAM_BANK2
+ * @retval none
+ */
+void xmc_sdram_reset(xmc_sdram_bank_type xmc_bank)
+{
+ XMC_SDRAM->ctrl[xmc_bank] = 0x000002D0;
+ XMC_SDRAM->tm[xmc_bank] = 0x0FFFFFFF;
+ XMC_SDRAM->cmd = 0x00000000;
+ XMC_SDRAM->rcnt = 0x00000000;
+ XMC_SDRAM->sts = 0x00000000;
+}
+
+/**
+ * @brief initialize the xmc sdram banks according to the specified
+ * parameters in the xmc_sdram_init_struct and xmc_sdram_timing_struct.
+ * @param xmc_sdram_init_struct : pointer to a xmc_sdram_init_type
+ * structure that contains the configuration information for the xmc
+ * sdram specified banks.
+ * @param xmc_sdram_timing_struct : pointer to a xmc_sdram_timing_type
+ * structure that contains the configuration information for the xmc
+ * sdram specified banks.
+ * @retval none
+ */
+void xmc_sdram_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct)
+{
+ if(xmc_sdram_init_struct->sdram_bank == XMC_SDRAM_BANK1)
+ {
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].ca = xmc_sdram_init_struct->column_address;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].ra = xmc_sdram_init_struct->row_address;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].db = xmc_sdram_init_struct->width;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].inbk = xmc_sdram_init_struct->internel_banks;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].cas = xmc_sdram_init_struct->cas;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].wrp = xmc_sdram_init_struct->write_protection;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].bstr = xmc_sdram_init_struct->burst_read;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].rd = xmc_sdram_init_struct->read_delay;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].clkdiv = xmc_sdram_init_struct->clkdiv;
+
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].tmrd = xmc_sdram_timing_struct->tmrd;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].txsr = xmc_sdram_timing_struct->txsr;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].tras = xmc_sdram_timing_struct->tras;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trc = xmc_sdram_timing_struct->trc;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].twr = xmc_sdram_timing_struct->twr;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trp = xmc_sdram_timing_struct->trp;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trcd = xmc_sdram_timing_struct->trcd;
+ }
+
+ if(xmc_sdram_init_struct->sdram_bank == XMC_SDRAM_BANK2)
+ {
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].ca = xmc_sdram_init_struct->column_address;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].ra = xmc_sdram_init_struct->row_address;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].db = xmc_sdram_init_struct->width;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].inbk = xmc_sdram_init_struct->internel_banks;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].cas = xmc_sdram_init_struct->cas;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].wrp = xmc_sdram_init_struct->write_protection;
+ /* sdctrl2 bstr is not care */
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].bstr = xmc_sdram_init_struct->burst_read;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].rd = xmc_sdram_init_struct->read_delay;
+ /* sdctrl2 clkdiv is not care */
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].clkdiv = xmc_sdram_init_struct->clkdiv;
+
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].tmrd = xmc_sdram_timing_struct->tmrd;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].txsr = xmc_sdram_timing_struct->txsr;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].tras = xmc_sdram_timing_struct->tras;
+ /* sdtm2 trc is not care */
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trc = xmc_sdram_timing_struct->trc;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].twr = xmc_sdram_timing_struct->twr;
+ /* sdtm2 trp is not care */
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trp = xmc_sdram_timing_struct->trp;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].trcd = xmc_sdram_timing_struct->trcd;
+ }
+}
+
+/**
+ * @brief fill each xmc_sdram_init_struct member with its default value.
+ * @param xmc_sdram_init_struct: pointer to a xmc_sdram_init_type
+ * structure which will be initialized.
+ * @param xmc_sdram_timing_struct: pointer to a xmc_sdram_timing_type
+ * structure which will be initialized.
+ * @retval none
+ */
+void xmc_sdram_default_para_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct)
+{
+ /* reset sdram init structure parameters values */
+ xmc_sdram_init_struct->sdram_bank = XMC_SDRAM_BANK1;
+ xmc_sdram_init_struct->internel_banks = XMC_INBK_4;
+ xmc_sdram_init_struct->clkdiv = XMC_NO_CLK;
+ xmc_sdram_init_struct->write_protection = FALSE;
+ xmc_sdram_init_struct->burst_read = FALSE;
+ xmc_sdram_init_struct->column_address = XMC_COLUMN_8;
+ xmc_sdram_init_struct->row_address = XMC_ROW_11;
+ xmc_sdram_init_struct->cas = XMC_CAS_1;
+ xmc_sdram_init_struct->width = XMC_MEM_WIDTH_8;
+ xmc_sdram_init_struct->read_delay = XMC_READ_DELAY_1;
+
+ xmc_sdram_timing_struct->tmrd = XMC_DELAY_CYCLE_16;
+ xmc_sdram_timing_struct->txsr = XMC_DELAY_CYCLE_16;
+ xmc_sdram_timing_struct->tras = XMC_DELAY_CYCLE_16;
+ xmc_sdram_timing_struct->trc = XMC_DELAY_CYCLE_16;
+ xmc_sdram_timing_struct->twr = XMC_DELAY_CYCLE_16;
+ xmc_sdram_timing_struct->trp = XMC_DELAY_CYCLE_16;
+ xmc_sdram_timing_struct->trcd = XMC_DELAY_CYCLE_16;
+}
+
+/**
+ * @brief sdram command confg
+ * @param xmc_sdram_cmd_struct: pointer to a xmc_sdram_cmd_type
+ * structure which will be initialized.
+ * @retval none
+ */
+void xmc_sdram_cmd(xmc_sdram_cmd_type *xmc_sdram_cmd_struct)
+{
+ XMC_SDRAM->cmd = (xmc_sdram_cmd_struct->auto_refresh << 5) |
+ (xmc_sdram_cmd_struct->data << 9) |
+ xmc_sdram_cmd_struct->cmd |
+ xmc_sdram_cmd_struct->cmd_banks;
+}
+
+
+/**
+ * @brief get sdram bank status
+ * @param xmc_bank: specifies the xmc bank to be used
+ * this parameter can be one of the following values:
+ * - XMC_SDRAM_BANK1
+ * - XMC_SDRAM_BANK1
+ * @retval the bank status
+ */
+uint32_t xmc_sdram_status_get(xmc_sdram_bank_type xmc_bank)
+{
+ if(xmc_bank == XMC_SDRAM_BANK1)
+ {
+ return ((XMC_SDRAM->sts >> 1) & XMC_STATUS_MASK);
+ }
+ else
+ {
+ return ((XMC_SDRAM->sts >> 3) & XMC_STATUS_MASK);
+ }
+}
+
+/**
+ * @brief set sdram refresh counter
+ * @param counter: xmc sdram refresh counter
+ * @retval none
+ */
+void xmc_sdram_refresh_counter_set(uint32_t counter)
+{
+ XMC_SDRAM->rcnt_bit.rc = counter;
+}
+
+/**
+ * @brief set sdram auto refresh number
+ * @param number: xmc sdram auto refresh number
+ * @retval none
+ */
+void xmc_sdram_auto_refresh_set(uint32_t number)
+{
+ XMC_SDRAM->cmd_bit.art = number;
+}
+
+/**
+ * @brief enable or disable the specified xmc interrupts.
+ * @param xmc_bank: specifies the xmc bank to be used
+ * this parameter can be one of the following values:
+ * - XMC_BANK2_NAND
+ * - XMC_BANK3_NAND
+ * - XMC_BANK4_PCCARD
+ * - XMC_BANK5_6_SDRAM
+ * @param xmc_int: specifies the xmc interrupt sources to be enabled or disabled.
+ * this parameter can be any combination of the following values:
+ * - XMC_INT_RISING_EDGE
+ * - XMC_INT_LEVEL
+ * - XMC_INT_FALLING_EDGE
+ * - XMC_INT_ERR
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ /* enable the selected xmc_bank2 interrupts */
+ if(xmc_bank == XMC_BANK2_NAND)
+ {
+ XMC_BANK2->bk2is |= xmc_int;
+ }
+ /* enable the selected xmc_bank3 interrupts */
+ else if(xmc_bank == XMC_BANK3_NAND)
+ {
+ XMC_BANK3->bk3is |= xmc_int;
+ }
+ /* enable the selected xmc_bank4 interrupts */
+ else if(xmc_bank == XMC_BANK4_PCCARD)
+ {
+ XMC_BANK4->bk4is |= xmc_int;
+ }
+ /* enable the selected xmc_sdram interrupts */
+ else
+ {
+ XMC_SDRAM->rcnt |= xmc_int;
+ }
+ }
+ else
+ {
+ /* disable the selected xmc_bank2 interrupts */
+ if(xmc_bank == XMC_BANK2_NAND)
+ {
+ XMC_BANK2->bk2is &= ~xmc_int;
+ }
+ /* disable the selected xmc_bank3 interrupts */
+ else if(xmc_bank == XMC_BANK3_NAND)
+ {
+ XMC_BANK3->bk3is &= ~xmc_int;
+ }
+ /* disable the selected xmc_bank4 interrupts */
+ else if(xmc_bank == XMC_BANK4_PCCARD)
+ {
+ XMC_BANK4->bk4is &= ~xmc_int;
+ }
+ /* disable the selected xmc_sdram interrupts */
+ else
+ {
+ XMC_SDRAM->rcnt &= ~xmc_int;
+ }
+ }
+}
+
+/**
+ * @brief check whether the specified xmc flag is set or not.
+ * @param xmc_bank: specifies the xmc bank to be used
+ * this parameter can be one of the following values:
+ * - XMC_BANK2_NAND
+ * - XMC_BANK3_NAND
+ * - XMC_BANK4_PCCARD
+ * - XMC_BANK5_6_SDRAM
+ * @param xmc_flag: specifies the flag to check.
+ * this parameter can be any combination of the following values:
+ * - XMC_RISINGEDGE_FLAG
+ * - XMC_LEVEL_FLAG
+ * - XMC_FALLINGEDGE_FLAG
+ * - XMC_FEMPT_FLAG
+ * - XMC_BUSY_FLAG
+ * - XMC_ERR_FLAG
+ * @retval none
+ */
+flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
+{
+ flag_status status = RESET;
+ uint32_t temp = 0;
+
+ if(xmc_bank == XMC_BANK2_NAND)
+ {
+ temp = XMC_BANK2->bk2is;
+ }
+ else if(xmc_bank == XMC_BANK3_NAND)
+ {
+ temp = XMC_BANK3->bk3is;
+ }
+ else if(xmc_bank == XMC_BANK4_PCCARD)
+ {
+ temp = XMC_BANK4->bk4is;
+ }
+ else
+ {
+ temp = XMC_SDRAM->sts;
+ }
+ /* get the flag status */
+ if((temp & xmc_flag) == RESET)
+ {
+ status = RESET;
+ }
+ else
+ {
+ status = SET;
+ }
+ /* return the flag status */
+ return status;
+}
+
+/**
+ * @brief clear the xmc's pending flags.
+ * @param xmc_bank: specifies the xmc bank to be used
+ * this parameter can be one of the following values:
+ * - XMC_BANK2_NAND
+ * - XMC_BANK3_NAND
+ * - XMC_BANK4_PCCARD
+ * - XMC_BANK5_6_SDRAM
+ * @param xmc_flag: specifies the flag to check.
+ * this parameter can be any combination of the following values:
+ * - XMC_RISINGEDGE_FLAG
+ * - XMC_LEVEL_FLAG
+ * - XMC_FALLINGEDGE_FLAG
+ * - XMC_ERR_FLAG
+ * @retval none
+ */
+void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
+{
+ __IO uint32_t int_state;
+ if(xmc_bank == XMC_BANK2_NAND)
+ {
+ int_state = XMC_BANK2->bk2is & 0x38; /* keep interrupt state */
+ XMC_BANK2->bk2is = (~(xmc_flag | 0x38) | int_state);
+ }
+ else if(xmc_bank == XMC_BANK3_NAND)
+ {
+ int_state = XMC_BANK3->bk3is & 0x38; /* keep interrupt state */
+ XMC_BANK3->bk3is = (~(xmc_flag | 0x38) | int_state);
+ }
+ else if(xmc_bank == XMC_BANK4_PCCARD)
+ {
+ int_state = XMC_BANK4->bk4is & 0x38; /* keep interrupt state */
+ XMC_BANK4->bk4is = (~(xmc_flag | 0x38) | int_state);
+ }
+ else
+ {
+ XMC_SDRAM->rcnt |= xmc_flag;
+ }
+}
+
+/**
+ * @brief xmc pc card registers reset
+ * @param none
+ * @retval none
+ */
+void xmc_pccard_reset(void)
+{
+ /* Set the XMC_Bank4 registers to their reset values */
+ XMC_BANK4->bk4ctrl = 0x00000018;
+ XMC_BANK4->bk4is = 0x00000000;
+ XMC_BANK4->bk4tmgatt = 0xFCFCFCFC;
+ XMC_BANK4->bk4tmgio = 0xFCFCFCFC;
+ XMC_BANK4->bk4tmgmem = 0xFCFCFCFC;
+}
+
+/**
+ * @brief initialize the xmc pccard bank according to the specified
+ * parameters in the xmc_pccard_init_struct.
+ * @param xmc_pccard_init_struct : pointer to a xmc_pccard_init_type
+ * structure that contains the configuration information for the xmc
+ * pccard bank.
+ * @retval none
+ */
+void xmc_pccard_init(xmc_pccard_init_type* xmc_pccard_init_struct)
+{
+ /* set the bk4ctrl register value according to xmc_pccard_init_struct parameters */
+ XMC_BANK4->bk4ctrl = (uint32_t)xmc_pccard_init_struct->enable_wait |
+ XMC_BUSTYPE_16_BITS |
+ (xmc_pccard_init_struct->delay_time_cr << 9) |
+ (xmc_pccard_init_struct->delay_time_ar << 13);
+}
+
+/**
+ * @brief initialize the xmc pccard bank according to the specified
+ * parameters in the xmc_common_spacetiming_struct/xmc_attribute_spacetiming_struct
+ * and xmc_iospace_timing_struct.
+ * @param xmc_regular_spacetiming_struct : pointer to a xmc_pccard_init_type
+ * structure that contains the configuration information for the xmc
+ * pccard bank.
+ * @param xmc_special_spacetiming_struct : pointer to a xmc_pccard_init_type
+ * structure that contains the configuration information for the xmc
+ * pccard bank.
+ * @param xmc_iospace_timing_struct : pointer to a xmc_pccard_init_type
+ * structure that contains the configuration information for the xmc
+ * pccard bank.
+ * @retval none
+ */
+void xmc_pccard_timing_config(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct)
+{
+ /* set bk4tmgmem register value according to xmc_regular_spacetiming_struct parameters */
+ XMC_BANK4->bk4tmgmem = (uint32_t)xmc_regular_spacetiming_struct->mem_setup_time |
+ (xmc_regular_spacetiming_struct->mem_waite_time << 8) |
+ (xmc_regular_spacetiming_struct->mem_hold_time << 16) |
+ (xmc_regular_spacetiming_struct->mem_hiz_time << 24);
+
+ /* Set bk4tmgatt register value according to xmc_special_spacetiming_struct parameters */
+ XMC_BANK4->bk4tmgatt = (uint32_t)xmc_special_spacetiming_struct->mem_setup_time |
+ (xmc_special_spacetiming_struct->mem_waite_time << 8) |
+ (xmc_special_spacetiming_struct->mem_hold_time << 16) |
+ (xmc_special_spacetiming_struct->mem_hiz_time << 24);
+
+ /* Set bk4tmgio register value according to xmc_iospace_timing_struct parameters */
+ XMC_BANK4->bk4tmgio = (uint32_t)xmc_iospace_timing_struct->mem_setup_time |
+ (xmc_iospace_timing_struct->mem_waite_time << 8) |
+ (xmc_iospace_timing_struct->mem_hold_time << 16) |
+ (xmc_iospace_timing_struct->mem_hiz_time << 24);
+}
+/**
+ * @brief fill each xmc_pccard_init_struct member with its default value.
+ * @param xmc_pccard_init_struct: pointer to a xmc_pccardinittype
+ * structure which will be initialized.
+ * @retval none
+ */
+void xmc_pccard_default_para_init(xmc_pccard_init_type* xmc_pccard_init_struct)
+{
+ /* reset pccard init structure parameters values */
+ xmc_pccard_init_struct->enable_wait = XMC_WAIT_OPERATION_DISABLE;
+ xmc_pccard_init_struct->delay_time_ar = 0x0;
+ xmc_pccard_init_struct->delay_time_cr = 0x0;
+
+}
+/**
+ * @brief fill each xmc_common_spacetiming_struct/xmc_attribute_spacetiming_struct
+ * and xmc_iospace_timing_struct member with its default value.
+ * @param xmc_regular_spacetiming_struct : pointer to a xmc_pccard_init_type
+ * structure that contains the configuration information for the xmc
+ * pccard bank.
+ * @param xmc_special_spacetiming_struct : pointer to a xmc_pccard_init_type
+ * structure that contains the configuration information for the xmc
+ * pccard bank.
+ * @param xmc_iospace_timing_struct : pointer to a xmc_pccard_init_type
+ * structure that contains the configuration information for the xmc
+ * pccard bank.
+ * @retval none
+ */
+void xmc_pccard_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_regular_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_special_spacetiming_struct,
+ xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct)
+{
+ xmc_regular_spacetiming_struct->class_bank = XMC_BANK4_PCCARD;
+ xmc_regular_spacetiming_struct->mem_hold_time = 0xFC;
+ xmc_regular_spacetiming_struct->mem_waite_time = 0xFC;
+ xmc_regular_spacetiming_struct->mem_setup_time = 0xFC;
+ xmc_regular_spacetiming_struct->mem_hiz_time = 0xFC;
+ xmc_special_spacetiming_struct->class_bank = XMC_BANK4_PCCARD;
+ xmc_special_spacetiming_struct->mem_hold_time = 0xFC;
+ xmc_special_spacetiming_struct->mem_waite_time = 0xFC;
+ xmc_special_spacetiming_struct->mem_setup_time = 0xFC;
+ xmc_special_spacetiming_struct->mem_hiz_time = 0xFC;
+ xmc_iospace_timing_struct->class_bank = XMC_BANK4_PCCARD;
+ xmc_iospace_timing_struct->mem_hold_time = 0xFC;
+ xmc_iospace_timing_struct->mem_waite_time = 0xFC;
+ xmc_iospace_timing_struct->mem_setup_time = 0xFC;
+ xmc_iospace_timing_struct->mem_hiz_time = 0xFC;
+}
+/**
+ * @brief enable or disable the pccard memory bank.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void xmc_pccard_enable(confirm_state new_state)
+{
+ /* enable the pccard bank4 by setting the en bit in the bk4ctrl register */
+ XMC_BANK4->bk4ctrl_bit.en = new_state;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/system_at32f435_437.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/system_at32f435_437.c
new file mode 100644
index 0000000..7abb0a1
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/src/system_at32f435_437.c
@@ -0,0 +1,182 @@
+/**
+ **************************************************************************
+ * @file system_at32f435_437.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief contains all the functions for cmsis cortex-m4 system source file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup AT32F435_437_system
+ * @{
+ */
+
+#include "at32f435_437.h"
+
+/** @addtogroup AT32F435_437_system_private_defines
+ * @{
+ */
+#define VECT_TAB_OFFSET 0x0 /*!< vector table base offset field. this value must be a multiple of 0x200. */
+/**
+ * @}
+ */
+
+/** @addtogroup AT32F435_437_system_private_variables
+ * @{
+ */
+unsigned int system_core_clock = HICK_VALUE; /*!< system clock frequency (core clock) */
+/**
+ * @}
+ */
+
+/** @addtogroup AT32F435_437_system_private_functions
+ * @{
+ */
+
+/**
+ * @brief setup the microcontroller system
+ * initialize the flash interface.
+ * @note this function should be used only after reset.
+ * @param none
+ * @retval none
+ */
+void SystemInit (void)
+{
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3U << 10U * 2U) | /* set cp10 full access */
+ (3U << 11U * 2U) ); /* set cp11 full access */
+#endif
+
+ /* reset the crm clock configuration to the default reset state(for debug purpose) */
+ /* set hicken bit */
+ CRM->ctrl_bit.hicken = TRUE;
+
+ /* wait hick stable */
+ while(CRM->ctrl_bit.hickstbl != SET);
+
+ /* hick used as system clock */
+ CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
+
+ /* wait sclk switch status */
+ while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
+
+ /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */
+ CRM->cfg = 0;
+
+ /* reset hexten, hextbyps, cfden and pllen bits */
+ CRM->ctrl &= ~(0x010D0000U);
+
+ /* reset pllms pllns pllfr pllrcs bits */
+ CRM->pllcfg = 0x00033002U;
+
+ /* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
+ CRM->misc1 = 0;
+
+ /* disable all interrupts enable and clear pending bits */
+ CRM->clkint = 0x009F0000U;
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* vector table relocation in internal sram. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* vector table relocation in internal flash. */
+#endif
+}
+
+/**
+ * @brief update system_core_clock variable according to clock register values.
+ * the system_core_clock variable contains the core clock (hclk), it can
+ * be used by the user application to setup the systick timer or configure
+ * other parameters.
+ * @param none
+ * @retval none
+ */
+void system_core_clock_update(void)
+{
+ uint32_t pll_ns = 0, pll_ms = 0, pll_fr = 0, pll_clock_source = 0, pllrcsfreq = 0;
+ uint32_t temp = 0, div_value = 0;
+ crm_sclk_type sclk_source;
+
+ static const uint8_t sys_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+ static const uint8_t pll_fr_table[6] = {1, 2, 4, 8, 16, 32};
+
+ /* get sclk source */
+ sclk_source = crm_sysclk_switch_status_get();
+
+ switch(sclk_source)
+ {
+ case CRM_SCLK_HICK:
+ if(((CRM->misc1_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
+ system_core_clock = HICK_VALUE * 6;
+ else
+ system_core_clock = HICK_VALUE;
+ break;
+ case CRM_SCLK_HEXT:
+ system_core_clock = HEXT_VALUE;
+ break;
+ case CRM_SCLK_PLL:
+ /* get pll clock source */
+ pll_clock_source = CRM->pllcfg_bit.pllrcs;
+
+ /* get multiplication factor */
+ pll_ns = CRM->pllcfg_bit.pllns;
+ pll_ms = CRM->pllcfg_bit.pllms;
+ pll_fr = pll_fr_table[CRM->pllcfg_bit.pllfr];
+
+ if (pll_clock_source == CRM_PLL_SOURCE_HICK)
+ {
+ /* hick selected as pll clock entry */
+ pllrcsfreq = HICK_VALUE;
+ }
+ else
+ {
+ /* hext selected as pll clock entry */
+ pllrcsfreq = HEXT_VALUE;
+ }
+
+ system_core_clock = (pllrcsfreq * pll_ns) / (pll_ms * pll_fr);
+ break;
+ default:
+ system_core_clock = HICK_VALUE;
+ break;
+ }
+
+ /* compute sclk, ahbclk frequency */
+ /* get ahb division */
+ temp = CRM->cfg_bit.ahbdiv;
+ div_value = sys_ahb_div_table[temp];
+ /* ahbclk frequency */
+ system_core_clock = system_core_clock >> div_value;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_core.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_core.h
new file mode 100644
index 0000000..630cf56
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_core.h
@@ -0,0 +1,241 @@
+/**
+ ******************************************************************************
+ * File : usb_core.h
+ * Version: V1.2.2
+ * Date : 2020-07-01
+ * Brief : Standard protocol processing functions prototypes
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_CORE_H
+#define __USB_CORE_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef enum _CONTROL_STATE
+{
+ WAIT_SETUP, /* 0 */
+ SETTING_UP, /* 1 */
+ IN_DATA, /* 2 */
+ OUT_DATA, /* 3 */
+ LAST_IN_DATA, /* 4 */
+ LAST_OUT_DATA, /* 5 */
+ WAIT_STATUS_IN, /* 7 */
+ WAIT_STATUS_OUT, /* 8 */
+ STALLED, /* 9 */
+ PAUSE /* 10 */
+} CONTROL_STATE; /* The state machine states of a control pipe */
+
+typedef struct OneDescriptor
+{
+ uint8_t *Descriptor;
+ uint16_t Descriptor_Size;
+}
+ONE_DESCRIPTOR, *PONE_DESCRIPTOR;
+/* All the request process routines return a value of this type
+ If the return value is not SUCCESS or NOT_READY,
+ the software will STALL the correspond endpoint */
+typedef enum _RESULT
+{
+ USB_SUCCESS = 0, /* Process successfully */
+ USB_ERROR,
+ USB_UNSUPPORT,
+ USB_NOT_READY /* The process has not been finished, endpoint will be
+ NAK to further request */
+} RESULT;
+
+
+/*-*-*-*-*-*-*-*-*-*-* Definitions for endpoint level -*-*-*-*-*-*-*-*-*-*-*-*/
+typedef struct _ENDPOINT_INFO
+{
+ /* When send data out of the device,
+ CopyData() is used to get data buffer 'Length' bytes data
+ if Length is 0,
+ CopyData() returns the total length of the data
+ if the request is not supported, returns 0
+ (NEW Feature )
+ if CopyData() returns -1, the calling routine should not proceed
+ further and will resume the SETUP process by the class device
+ if Length is not 0,
+ CopyData() returns a pointer to indicate the data location
+ Usb_wLength is the data remain to be sent,
+ Usb_wOffset is the Offset of original data
+ When receive data from the host,
+ CopyData() is used to get user data buffer which is capable
+ of Length bytes data to copy data from the endpoint buffer.
+ if Length is 0,
+ CopyData() returns the available data length,
+ if Length is not 0,
+ CopyData() returns user buffer address
+ Usb_rLength is the data remain to be received,
+ Usb_rPointer is the Offset of data buffer
+ */
+ uint16_t Usb_wLength;
+ uint16_t Usb_wOffset;
+ uint16_t PacketSize;
+ uint8_t *(*CopyData)(uint16_t Length);
+}ENDPOINT_INFO;
+
+/*-*-*-*-*-*-*-*-*-*-*-* Definitions for device level -*-*-*-*-*-*-*-*-*-*-*-*/
+
+typedef struct _DEVICE
+{
+ uint8_t Total_Endpoint; /* Number of endpoints that are used */
+ uint8_t Total_Configuration;/* Number of configuration available */
+}
+DEVICE;
+
+typedef union
+{
+ uint16_t w;
+ struct BW
+ {
+ uint8_t bb1;
+ uint8_t bb0;
+ }
+ bw;
+} uint16_t_uint8_t;
+
+typedef struct _DEVICE_INFO
+{
+ uint8_t USBbmRequestType; /* bmRequestType */
+ uint8_t USBbRequest; /* bRequest */
+ uint16_t_uint8_t USBwValues; /* wValue */
+ uint16_t_uint8_t USBwIndexs; /* wIndex */
+ uint16_t_uint8_t USBwLengths; /* wLength */
+
+ uint8_t ControlState; /* of type CONTROL_STATE */
+ uint8_t Current_Feature;
+ uint8_t Current_Configuration; /* Selected configuration */
+ uint8_t Current_Interface; /* Selected interface of current configuration */
+ uint8_t Current_AlternateSetting;/* Selected Alternate Setting of current
+ interface*/
+
+ ENDPOINT_INFO Ctrl_Info;
+}DEVICE_INFO;
+
+typedef struct _DEVICE_PROP
+{
+ void (*Init)(void); /* Initialize the device */
+ void (*Reset)(void); /* Reset routine of this device */
+
+ /* Device dependent process after the status stage */
+ void (*Process_Status_IN)(void);
+ void (*Process_Status_OUT)(void);
+
+ /* Procedure of process on setup stage of a class specified request with data stage */
+ /* All class specified requests with data stage are processed in Class_Data_Setup
+ Class_Data_Setup()
+ responses to check all special requests and fills ENDPOINT_INFO
+ according to the request
+ If IN tokens are expected, then wLength & wOffset will be filled
+ with the total transferring bytes and the starting position
+ If OUT tokens are expected, then rLength & rOffset will be filled
+ with the total expected bytes and the starting position in the buffer
+
+ If the request is valid, Class_Data_Setup returns SUCCESS, else UNSUPPORT
+
+ CAUTION:
+ Since GET_CONFIGURATION & GET_INTERFACE are highly related to
+ the individual classes, they will be checked and processed here.
+ */
+ RESULT (*Class_Data_Setup)(uint8_t RequestNo);
+
+ /* Procedure of process on setup stage of a class specified request without data stage */
+ /* All class specified requests without data stage are processed in Class_NoData_Setup
+ Class_NoData_Setup
+ responses to check all special requests and perform the request
+
+ CAUTION:
+ Since SET_CONFIGURATION & SET_INTERFACE are highly related to
+ the individual classes, they will be checked and processed here.
+ */
+ RESULT (*Class_NoData_Setup)(uint8_t RequestNo);
+
+ /*Class_Get_Interface_Setting
+ This function is used by the file usb_core.c to test if the selected Interface
+ and Alternate Setting (uint8_t Interface, uint8_t AlternateSetting) are supported by
+ the application.
+ This function is writing by user. It should return "SUCCESS" if the Interface
+ and Alternate Setting are supported by the application or "UNSUPPORT" if they
+ are not supported. */
+
+ RESULT (*Class_Get_Interface_Setting)(uint8_t Interface, uint8_t AlternateSetting);
+
+ uint8_t* (*GetDeviceDescriptor)(uint16_t Length);
+ uint8_t* (*GetConfigDescriptor)(uint16_t Length);
+ uint8_t* (*GetStringDescriptor)(uint16_t Length);
+
+ /* This field is not used in current library version. It is kept only for
+ compatibility with previous versions */
+ void* RxEP_buffer;
+
+ uint8_t MaxPacketSize;
+
+}DEVICE_PROP;
+
+typedef struct _USER_STANDARD_REQUESTS
+{
+ void (*User_GetConfiguration)(void); /* Get Configuration */
+ void (*User_SetConfiguration)(void); /* Set Configuration */
+ void (*User_GetInterface)(void); /* Get Interface */
+ void (*User_SetInterface)(void); /* Set Interface */
+ void (*User_GetStatus)(void); /* Get Status */
+ void (*User_ClearFeature)(void); /* Clear Feature */
+ void (*User_SetEndPointFeature)(void); /* Set Endpoint Feature */
+ void (*User_SetDeviceFeature)(void); /* Set Device Feature */
+ void (*User_SetDeviceAddress)(void); /* Set Device Address */
+}
+USER_STANDARD_REQUESTS;
+
+/* Exported constants --------------------------------------------------------*/
+#define Type_Recipient (pInformation->USBbmRequestType & (REQUEST_TYPE | RECIPIENT))
+
+#define Usb_rLength Usb_wLength
+#define Usb_rOffset Usb_wOffset
+
+#define USBwValue USBwValues.w
+#define USBwValue0 USBwValues.bw.bb0
+#define USBwValue1 USBwValues.bw.bb1
+#define USBwIndex USBwIndexs.w
+#define USBwIndex0 USBwIndexs.bw.bb0
+#define USBwIndex1 USBwIndexs.bw.bb1
+#define USBwLength USBwLengths.w
+#define USBwLength0 USBwLengths.bw.bb0
+#define USBwLength1 USBwLengths.bw.bb1
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+uint8_t Setup0_Process(void);
+uint8_t Post0_Process(void);
+uint8_t Out0_Process(void);
+uint8_t In0_Process(void);
+
+RESULT Standard_SetEndPointFeature(void);
+RESULT Standard_SetDeviceFeature(void);
+
+uint8_t *Standard_GetConfiguration(uint16_t Length);
+RESULT Standard_SetConfiguration(void);
+uint8_t *Standard_GetInterface(uint16_t Length);
+RESULT Standard_SetInterface(void);
+uint8_t *Standard_GetDescriptorData(uint16_t Length, PONE_DESCRIPTOR pDesc);
+
+uint8_t *Standard_GetStatus(uint16_t Length);
+RESULT Standard_ClearFeature(void);
+void SetDeviceAddress(uint8_t);
+void NOP_Process(void);
+
+extern DEVICE_PROP Device_Property;
+extern USER_STANDARD_REQUESTS User_Standard_Requests;
+extern DEVICE Device_Table;
+extern DEVICE_INFO Device_Info;
+
+/* cells saving status during interrupt servicing */
+extern __IO uint16_t SaveRState;
+extern __IO uint16_t SaveTState;
+
+#endif /* __USB_CORE_H */
+
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_def.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_def.h
new file mode 100644
index 0000000..045799d
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_def.h
@@ -0,0 +1,75 @@
+/**
+ ******************************************************************************
+ * File : usb_def.h
+ * Version: V1.2.2
+ * Date : 2020-07-01
+ * Brief : Definitions related to USB Core
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_DEF_H
+#define __USB_DEF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef enum _RECIPIENT_TYPE
+{
+ DEVICE_RECIPIENT, /* Recipient device */
+ INTERFACE_RECIPIENT, /* Recipient interface */
+ ENDPOINT_RECIPIENT, /* Recipient endpoint */
+ OTHER_RECIPIENT
+} RECIPIENT_TYPE;
+
+
+typedef enum _STANDARD_REQUESTS
+{
+ GET_STATUS = 0,
+ CLEAR_FEATURE,
+ RESERVED1,
+ SET_FEATURE,
+ RESERVED2,
+ SET_ADDRESS,
+ GET_DESCRIPTOR,
+ SET_DESCRIPTOR,
+ GET_CONFIGURATION,
+ SET_CONFIGURATION,
+ GET_INTERFACE,
+ SET_INTERFACE,
+ TOTAL_sREQUEST, /* Total number of Standard request */
+ SYNCH_FRAME = 12
+} STANDARD_REQUESTS;
+
+/* Definition of "USBwValue" */
+typedef enum _DESCRIPTOR_TYPE
+{
+ DEVICE_DESCRIPTOR = 1,
+ CONFIG_DESCRIPTOR,
+ STRING_DESCRIPTOR,
+ INTERFACE_DESCRIPTOR,
+ ENDPOINT_DESCRIPTOR
+} DESCRIPTOR_TYPE;
+
+/* Feature selector of a SET_FEATURE or CLEAR_FEATURE */
+typedef enum _FEATURE_SELECTOR
+{
+ ENDPOINT_STALL,
+ DEVICE_REMOTE_WAKEUP
+} FEATURE_SELECTOR;
+
+/* Exported constants --------------------------------------------------------*/
+/* Definition of "USBbmRequestType" */
+#define REQUEST_TYPE 0x60 /* Mask to get request type */
+#define STANDARD_REQUEST 0x00 /* Standard request */
+#define CLASS_REQUEST 0x20 /* Class request */
+#define VENDOR_REQUEST 0x40 /* Vendor request */
+
+#define RECIPIENT 0x1F /* Mask to get recipient */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __USB_DEF_H */
+
+
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_init.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_init.h
new file mode 100644
index 0000000..f1dc4d1
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_init.h
@@ -0,0 +1,51 @@
+/**
+ ******************************************************************************
+ * File : usb_init.h
+ * Version: V1.2.2
+ * Date : 2020-07-01
+ * Brief : Initialization routines & global variables
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_INIT_H
+#define __USB_INIT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void USB_Init(void);
+
+/* External variables --------------------------------------------------------*/
+/* The number of current endpoint, it will be used to specify an endpoint */
+extern uint8_t EPindex;
+/* The number of current device, it is an index to the Device_Table */
+/*extern uint8_t Device_no; */
+/* Points to the DEVICE_INFO structure of current device */
+/* The purpose of this register is to speed up the execution */
+extern DEVICE_INFO* pInformation;
+/* Points to the DEVICE_PROP structure of current device */
+/* The purpose of this register is to speed up the execution */
+extern DEVICE_PROP* pProperty;
+/* Temporary save the state of Rx & Tx status. */
+/* Whenever the Rx or Tx state is changed, its value is saved */
+/* in this variable first and will be set to the EPRB or EPRA */
+/* at the end of interrupt process */
+extern USER_STANDARD_REQUESTS *pUser_Standard_Requests;
+
+extern uint16_t SaveState ;
+extern uint16_t wInterrupt_Mask;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_INIT_H */
+
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_int.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_int.h
new file mode 100644
index 0000000..290303f
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_int.h
@@ -0,0 +1,28 @@
+/**
+ ******************************************************************************
+ * File : usb_int.h
+ * Version: V1.2.2
+ * Date : 2020-07-01
+ * Brief : Endpoint CTRF (Low and High) interrupt's service routines prototypes
+ ******************************************************************************
+ */
+
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_INT_H
+#define __USB_INT_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void CTR_LP(void);
+void CTR_HP(void);
+
+/* External variables --------------------------------------------------------*/
+
+#endif /* __USB_INT_H */
+
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_lib.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_lib.h
new file mode 100644
index 0000000..e09d8e1
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_lib.h
@@ -0,0 +1,35 @@
+/**
+ ******************************************************************************
+ * File : usb_lib.h
+ * Version: V1.2.2
+ * Date : 2020-07-01
+ * Brief : USB library include files
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_LIB_H
+#define __USB_LIB_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "hw_config.h"
+#include "usb_type.h"
+#include "usb_regs.h"
+#include "usb_def.h"
+#include "usb_core.h"
+#include "usb_init.h"
+#include "usb_sil.h"
+#include "usb_mem.h"
+#include "usb_int.h"
+
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* External variables --------------------------------------------------------*/
+
+#endif /* __USB_LIB_H */
+
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_mem.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_mem.h
new file mode 100644
index 0000000..08dbeb2
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_mem.h
@@ -0,0 +1,34 @@
+/**
+ ******************************************************************************
+ * File : usb_mem.h
+ * Version: V1.2.2
+ * Date : 2020-07-01
+ * Brief : Utility prototypes functions for memory/PMA transfers
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_MEM_H
+#define __USB_MEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void UserToPMABufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+void PMAToUserBufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+
+/* External variables --------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__USB_MEM_H*/
+
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_regs.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_regs.h
new file mode 100644
index 0000000..8d7850f
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_regs.h
@@ -0,0 +1,672 @@
+/**
+ ******************************************************************************
+ * File : usb_reg.h
+ * Version: V1.2.2
+ * Date : 2020-07-01
+ * Brief : Interface prototype functions to USB cell registers
+ ******************************************************************************
+ */
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __USB_REGS_H
+#define __USB_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef enum _EP_DBUF_DIR
+{
+ /* double buffered endpoint direction */
+ EP_DBUF_ERR,
+ EP_DBUF_OUT,
+ EP_DBUF_IN
+}EP_DBUF_DIR;
+
+/* endpoint buffer number */
+enum EP_BUF_NUM
+{
+ EP_NOBUF,
+ EP_BUF0,
+ EP_BUF1
+};
+
+/* Exported constants --------------------------------------------------------*/
+#define RegBase (0x40005C00L) /* USB_IP Peripheral Registers base address */
+extern int PMAAddr; /* USB_IP Packet Memory Area base address, default is 0x40006000*/
+
+/******************************************************************************/
+/* General registers */
+/******************************************************************************/
+
+/* Control register */
+#define CTRL ((__IO unsigned *)(RegBase + 0x40))
+/* Interrupt status register */
+#define INTSTS ((__IO unsigned *)(RegBase + 0x44))
+/* Frame number register */
+#define FRNUM ((__IO unsigned *)(RegBase + 0x48))
+/* Device address register */
+#define DEVADR ((__IO unsigned *)(RegBase + 0x4C))
+/* Buffer Table address register */
+#define BUFTBL ((__IO unsigned *)(RegBase + 0x50))
+/******************************************************************************/
+/* Endpoint registers */
+/******************************************************************************/
+#define EP0REG ((__IO unsigned *)(RegBase)) /* endpoint 0 register address */
+
+/* Endpoint Addresses (w/direction) */
+#define EP0_OUT ((uint8_t)0x00)
+#define EP0_IN ((uint8_t)0x80)
+#define EP1_OUT ((uint8_t)0x01)
+#define EP1_IN ((uint8_t)0x81)
+#define EP2_OUT ((uint8_t)0x02)
+#define EP2_IN ((uint8_t)0x82)
+#define EP3_OUT ((uint8_t)0x03)
+#define EP3_IN ((uint8_t)0x83)
+#define EP4_OUT ((uint8_t)0x04)
+#define EP4_IN ((uint8_t)0x84)
+#define EP5_OUT ((uint8_t)0x05)
+#define EP5_IN ((uint8_t)0x85)
+#define EP6_OUT ((uint8_t)0x06)
+#define EP6_IN ((uint8_t)0x86)
+#define EP7_OUT ((uint8_t)0x07)
+#define EP7_IN ((uint8_t)0x87)
+
+/* endpoints enumeration */
+#define ENDP0 ((uint8_t)0)
+#define ENDP1 ((uint8_t)1)
+#define ENDP2 ((uint8_t)2)
+#define ENDP3 ((uint8_t)3)
+#define ENDP4 ((uint8_t)4)
+#define ENDP5 ((uint8_t)5)
+#define ENDP6 ((uint8_t)6)
+#define ENDP7 ((uint8_t)7)
+
+/******************************************************************************/
+/* INTSTS interrupt events */
+/******************************************************************************/
+#define INTSTS_CTFR (0x8000) /* Correct TRansfer (clear-only bit) */
+#define INTSTS_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */
+#define INTSTS_ERRF (0x2000) /* ERRor (clear-only bit) */
+#define INTSTS_WKUPF (0x1000) /* WaKe UP (clear-only bit) */
+#define INTSTS_SUSPF (0x0800) /* SUSPend (clear-only bit) */
+#define INTSTS_RSTF (0x0400) /* RESET (clear-only bit) */
+#define INTSTS_SOFF (0x0200) /* Start Of Frame (clear-only bit) */
+#define INTSTS_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */
+
+
+#define INTSTS_DIR (0x0010) /* DIRection of transaction (read-only bit) */
+#define INTSTS_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */
+
+#define CLR_CTFR (~INTSTS_CTFR) /* clear Correct TRansfer bit */
+#define CLR_DOVR (~INTSTS_DOVR) /* clear DMA OVeR/underrun bit*/
+#define CLR_ERRF (~INTSTS_ERRF) /* clear ERRor bit */
+#define CLR_WKUPF (~INTSTS_WKUPF) /* clear WaKe UP bit */
+#define CLR_SUSPF (~INTSTS_SUSPF) /* clear SUSPend bit */
+#define CLR_RSTF (~INTSTS_RSTF) /* clear RESET bit */
+#define CLR_SOFF (~INTSTS_SOFF) /* clear Start Of Frame bit */
+#define CLR_ESOF (~INTSTS_ESOF) /* clear Expected Start Of Frame bit */
+
+/******************************************************************************/
+/* CTRL control register bits definitions */
+/******************************************************************************/
+#define CTRL_CTFR_IEN (0x8000) /* Correct TRansfer Mask */
+#define CTRL_DOVR_IEN (0x4000) /* DMA OVeR/underrun Mask */
+#define CTRL_ERR_IEN (0x2000) /* ERRor Mask */
+#define CTRL_WKUP_IEN (0x1000) /* WaKe UP Mask */
+#define CTRL_SUSP_IEN (0x0800) /* SUSPend Mask */
+#define CTRL_RST_IEN (0x0400) /* RESET Mask */
+#define CTRL_SOF_IEN (0x0200) /* Start Of Frame Mask */
+#define CTRL_ESOF_IEN (0x0100) /* Expected Start Of Frame Mask */
+
+
+#define CTRL_RESUME (0x0010) /* RESUME request */
+#define CTRL_FSUSP (0x0008) /* Force SUSPend */
+#define CTRL_LPWR (0x0004) /* Low-power MODE */
+#define CTRL_PDWN (0x0002) /* Power DoWN */
+#define CTRL_FRST (0x0001) /* Force USB RESet */
+
+/******************************************************************************/
+/* FRNUM Frame Number Register bit definitions */
+/******************************************************************************/
+#define FRNUM_RXDP (0x8000) /* status of D+ data line */
+#define FRNUM_RXDM (0x4000) /* status of D- data line */
+#define FRNUM_LCK (0x2000) /* LoCKed */
+#define FRNUM_LSOF (0x1800) /* Lost SOF */
+#define FRNUM_FN (0x07FF) /* Frame Number */
+/******************************************************************************/
+/* DEVADR Device ADDRess bit definitions */
+/******************************************************************************/
+#define DEVADR_EN (0x80)
+#define DEVADR_ADR (0x7F)
+/******************************************************************************/
+/* Endpoint register */
+/******************************************************************************/
+/* bit positions */
+#define EP_CTFR_RX (0x8000) /* EndPoint Correct TRansfer RX */
+#define EP_DTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */
+#define EP_STS_RX (0x3000) /* EndPoint RX STATus bit field */
+#define EP_SETUP (0x0800) /* EndPoint SETUP */
+#define EP_T_FIELD (0x0600) /* EndPoint TYPE */
+#define EP_SUBTYPE (0x0100) /* EndPoint KIND */
+#define EP_CTFR_TX (0x0080) /* EndPoint Correct TRansfer TX */
+#define EP_DTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */
+#define EP_STS_TX (0x0030) /* EndPoint TX STATus bit field */
+#define EPADR_FIELD (0x000F) /* EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define EPREG_MASK (EP_CTFR_RX|EP_SETUP|EP_T_FIELD|EP_SUBTYPE|EP_CTFR_TX|EPADR_FIELD)
+
+/* EP_TYPE[1:0] EndPoint TYPE */
+#define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */
+#define EP_BULK (0x0000) /* EndPoint BULK */
+#define EP_CONTROL (0x0200) /* EndPoint CONTROL */
+#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
+#define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */
+#define EP_T_MASK (~EP_T_FIELD & EPREG_MASK)
+
+
+/* EP_SUBTYPE EndPoint KIND */
+#define EPKIND_MASK (~EP_SUBTYPE & EPREG_MASK)
+
+/* STAT_TX[1:0] STATus for TX transfer */
+#define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */
+#define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */
+#define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */
+#define EP_TX_VALID (0x0030) /* EndPoint TX VALID */
+#define EPTX_DTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */
+#define EPTX_DTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */
+#define EPTX_DTOGMASK (EP_STS_TX|EPREG_MASK)
+
+/* STAT_RX[1:0] STATus for RX transfer */
+#define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */
+#define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */
+#define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */
+#define EP_RX_VALID (0x3000) /* EndPoint RX VALID */
+#define EPRX_DTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */
+#define EPRX_DTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */
+#define EPRX_DTOGMASK (EP_STS_RX|EPREG_MASK)
+/* Exported macro ------------------------------------------------------------*/
+/* SetCTRL */
+#define _SetCTRL(wRegValue) (*CTRL = (uint16_t)wRegValue)
+
+/* SetINTSTS */
+#define _SetINTSTS(wRegValue) (*INTSTS = (uint16_t)wRegValue)
+
+/* SetDEVADR */
+#define _SetDEVADR(wRegValue) (*DEVADR = (uint16_t)wRegValue)
+
+/* SetBUFTBL */
+#define _SetBUFTBL(wRegValue)(*BUFTBL = (uint16_t)(wRegValue & 0xFFF8))
+
+/* GetCTRL */
+#define _GetCTRL() ((uint16_t) *CTRL)
+
+/* GetINTSTS */
+#define _GetINTSTS() ((uint16_t) *INTSTS)
+
+/* GetFRNUM */
+#define _GetFRNUM() ((uint16_t) *FRNUM)
+
+/* GetDEVADR */
+#define _GetDEVADR() ((uint16_t) *DEVADR)
+
+/* GetBUFTBL */
+#define _GetBUFTBL() ((uint16_t) *BUFTBL)
+
+/* SetENDPOINT */
+#define _SetENDPOINT(bEpNum,wRegValue) (*(EP0REG + bEpNum)= \
+ (uint16_t)wRegValue)
+
+/* GetENDPOINT */
+#define _GetENDPOINT(bEpNum) ((uint16_t)(*(EP0REG + bEpNum)))
+
+/*******************************************************************************
+* Macro Name : SetEPType
+* Description : sets the type in the endpoint register(bits EP_TYPE[1:0])
+* Input : bEpNum: Endpoint Number.
+* wType
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\
+ ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType )))
+
+/*******************************************************************************
+* Macro Name : GetEPType
+* Description : gets the type in the endpoint register(bits EP_TYPE[1:0])
+* Input : bEpNum: Endpoint Number.
+* Output : None.
+* Return : Endpoint Type
+*******************************************************************************/
+#define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD)
+
+/*******************************************************************************
+* Macro Name : SetEPTxStatus
+* Description : sets the status for tx transfer (bits STAT_TX[1:0]).
+* Input : bEpNum: Endpoint Number.
+* wState: new state
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _SetEPTxStatus(bEpNum,wState) {\
+ register uint16_t _wRegVal; \
+ _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DTOGMASK;\
+ /* toggle first bit ? */ \
+ if((EPTX_DTOG1 & wState)!= 0) \
+ _wRegVal ^= EPTX_DTOG1; \
+ /* toggle second bit ? */ \
+ if((EPTX_DTOG2 & wState)!= 0) \
+ _wRegVal ^= EPTX_DTOG2; \
+ _SetENDPOINT(bEpNum, (_wRegVal | EP_CTFR_RX|EP_CTFR_TX)); \
+ } /* _SetEPTxStatus */
+
+/*******************************************************************************
+* Macro Name : SetEPRxStatus
+* Description : sets the status for rx transfer (bits STAT_TX[1:0])
+* Input : bEpNum: Endpoint Number.
+* wState: new state.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _SetEPRxStatus(bEpNum,wState) {\
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DTOGMASK;\
+ /* toggle first bit ? */ \
+ if((EPRX_DTOG1 & wState)!= 0) \
+ _wRegVal ^= EPRX_DTOG1; \
+ /* toggle second bit ? */ \
+ if((EPRX_DTOG2 & wState)!= 0) \
+ _wRegVal ^= EPRX_DTOG2; \
+ _SetENDPOINT(bEpNum, (_wRegVal | EP_CTFR_RX|EP_CTFR_TX)); \
+ } /* _SetEPRxStatus */
+
+/*******************************************************************************
+* Macro Name : SetEPRxTxStatus
+* Description : sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
+* Input : bEpNum: Endpoint Number.
+* wStaterx: new state.
+* wStatetx: new state.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _SetEPRxTxStatus(bEpNum,wStaterx,wStatetx) {\
+ register uint32_t _wRegVal; \
+ \
+ _wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DTOGMASK |EP_STS_TX) ;\
+ /* toggle first bit ? */ \
+ if((EPRX_DTOG1 & wStaterx)!= 0) \
+ _wRegVal ^= EPRX_DTOG1; \
+ /* toggle second bit ? */ \
+ if((EPRX_DTOG2 & wStaterx)!= 0) \
+ _wRegVal ^= EPRX_DTOG2; \
+ /* toggle first bit ? */ \
+ if((EPTX_DTOG1 & wStatetx)!= 0) \
+ _wRegVal ^= EPTX_DTOG1; \
+ /* toggle second bit ? */ \
+ if((EPTX_DTOG2 & wStatetx)!= 0) \
+ _wRegVal ^= EPTX_DTOG2; \
+ _SetENDPOINT(bEpNum, _wRegVal | EP_CTFR_RX|EP_CTFR_TX); \
+ } /* _SetEPRxTxStatus */
+/*******************************************************************************
+* Macro Name : GetEPTxStatus / GetEPRxStatus
+* Description : gets the status for tx/rx transfer (bits STAT_TX[1:0]
+* /STAT_RX[1:0])
+* Input : bEpNum: Endpoint Number.
+* Output : None.
+* Return : status .
+*******************************************************************************/
+#define _GetEPTxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EP_STS_TX)
+
+#define _GetEPRxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EP_STS_RX)
+
+/*******************************************************************************
+* Macro Name : SetEPTxValid / SetEPRxValid
+* Description : sets directly the VALID tx/rx-status into the enpoint register
+* Input : bEpNum: Endpoint Number.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID))
+
+#define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID))
+
+/*******************************************************************************
+* Macro Name : GetTxStallStatus / GetRxStallStatus.
+* Description : checks stall condition in an endpoint.
+* Input : bEpNum: Endpoint Number.
+* Output : None.
+* Return : TRUE = endpoint in stall condition.
+*******************************************************************************/
+#define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) \
+ == EP_TX_STALL)
+#define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) \
+ == EP_RX_STALL)
+
+/*******************************************************************************
+* Macro Name : SetEP_SUBTYPE / ClearEP_SUBTYPE.
+* Description : set & clear EP_SUBTYPE bit.
+* Input : bEpNum: Endpoint Number.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _SetEP_SUBTYPE(bEpNum) (_SetENDPOINT(bEpNum, \
+ (EP_CTFR_RX|EP_CTFR_TX|((_GetENDPOINT(bEpNum) | EP_SUBTYPE) & EPREG_MASK))))
+#define _ClearEP_SUBTYPE(bEpNum) (_SetENDPOINT(bEpNum, \
+ (EP_CTFR_RX|EP_CTFR_TX|(_GetENDPOINT(bEpNum) & EPKIND_MASK))))
+
+/*******************************************************************************
+* Macro Name : Set_Status_Out / Clear_Status_Out.
+* Description : Sets/clears directly STATUS_OUT bit in the endpoint register.
+* Input : bEpNum: Endpoint Number.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _Set_Status_Out(bEpNum) _SetEP_SUBTYPE(bEpNum)
+#define _Clear_Status_Out(bEpNum) _ClearEP_SUBTYPE(bEpNum)
+
+/*******************************************************************************
+* Macro Name : SetEPDoubleBuff / ClearEPDoubleBuff.
+* Description : Sets/clears directly EP_SUBTYPE bit in the endpoint register.
+* Input : bEpNum: Endpoint Number.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _SetEPDoubleBuff(bEpNum) _SetEP_SUBTYPE(bEpNum)
+#define _ClearEPDoubleBuff(bEpNum) _ClearEP_SUBTYPE(bEpNum)
+
+/*******************************************************************************
+* Macro Name : ClearEP_CTFR_RX / ClearEP_CTFR_TX.
+* Description : Clears bit CTR_RX / CTR_TX in the endpoint register.
+* Input : bEpNum: Endpoint Number.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _ClearEP_CTFR_RX(bEpNum) (_SetENDPOINT(bEpNum,\
+ _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK))
+#define _ClearEP_CTFR_TX(bEpNum) (_SetENDPOINT(bEpNum,\
+ _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK))
+
+/*******************************************************************************
+* Macro Name : ToggleDTOG_RX / ToggleDTOG_TX .
+* Description : Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
+* Input : bEpNum: Endpoint Number.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _ToggleDTOG_RX(bEpNum) (_SetENDPOINT(bEpNum, \
+ EP_CTFR_RX|EP_CTFR_TX|EP_DTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
+#define _ToggleDTOG_TX(bEpNum) (_SetENDPOINT(bEpNum, \
+ EP_CTFR_RX|EP_CTFR_TX|EP_DTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
+
+/*******************************************************************************
+* Macro Name : ClearDTOG_RX / ClearDTOG_TX.
+* Description : Clears DTOG_RX / DTOG_TX bit in the endpoint register.
+* Input : bEpNum: Endpoint Number.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _ClearDTOG_RX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_RX) != 0)\
+ _ToggleDTOG_RX(bEpNum)
+#define _ClearDTOG_TX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_TX) != 0)\
+ _ToggleDTOG_TX(bEpNum)
+/*******************************************************************************
+* Macro Name : SetEPAddress.
+* Description : Sets address in an endpoint register.
+* Input : bEpNum: Endpoint Number.
+* bAddr: Address.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\
+ EP_CTFR_RX|EP_CTFR_TX|(_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr)
+
+/*******************************************************************************
+* Macro Name : GetEPAddress.
+* Description : Gets address in an endpoint register.
+* Input : bEpNum: Endpoint Number.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _GetEPAddress(bEpNum) ((uint8_t)(_GetENDPOINT(bEpNum) & EPADR_FIELD))
+
+#define _pEPTxAddr(bEpNum) ((uint32_t *)((_GetBUFTBL()+bEpNum*8 )*2 + PMAAddr))
+#define _pEPTxCount(bEpNum) ((uint32_t *)((_GetBUFTBL()+bEpNum*8+2)*2 + PMAAddr))
+#define _pEPRxAddr(bEpNum) ((uint32_t *)((_GetBUFTBL()+bEpNum*8+4)*2 + PMAAddr))
+#define _pEPRxCount(bEpNum) ((uint32_t *)((_GetBUFTBL()+bEpNum*8+6)*2 + PMAAddr))
+
+/*******************************************************************************
+* Macro Name : SetEPTxAddr / SetEPRxAddr.
+* Description : sets address of the tx/rx buffer.
+* Input : bEpNum: Endpoint Number.
+* wAddr: address to be set (must be word aligned).
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _SetEPTxAddr(bEpNum,wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1))
+#define _SetEPRxAddr(bEpNum,wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1))
+
+/*******************************************************************************
+* Macro Name : GetEPTxAddr / GetEPRxAddr.
+* Description : Gets address of the tx/rx buffer.
+* Input : bEpNum: Endpoint Number.
+* Output : None.
+* Return : address of the buffer.
+*******************************************************************************/
+#define _GetEPTxAddr(bEpNum) ((uint16_t)*_pEPTxAddr(bEpNum))
+#define _GetEPRxAddr(bEpNum) ((uint16_t)*_pEPRxAddr(bEpNum))
+
+/*******************************************************************************
+* Macro Name : SetEPCountRxReg.
+* Description : Sets counter of rx buffer with no. of blocks.
+* Input : pdwReg: pointer to counter.
+* wCount: Counter.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _BlocksOf32(dwReg,wCount,wNBlocks) {\
+ wNBlocks = wCount >> 5;\
+ if((wCount & 0x1f) == 0)\
+ wNBlocks--;\
+ *pdwReg = (uint32_t)((wNBlocks << 10) | 0x8000);\
+ }/* _BlocksOf32 */
+
+#define _BlocksOf2(dwReg,wCount,wNBlocks) {\
+ wNBlocks = wCount >> 1;\
+ if((wCount & 0x1) != 0)\
+ wNBlocks++;\
+ *pdwReg = (uint32_t)(wNBlocks << 10);\
+ }/* _BlocksOf2 */
+
+#define _SetEPCountRxReg(dwReg,wCount) {\
+ uint16_t wNBlocks;\
+ if(wCount > 62){_BlocksOf32(dwReg,wCount,wNBlocks);}\
+ else {_BlocksOf2(dwReg,wCount,wNBlocks);}\
+ }/* _SetEPCountRxReg */
+
+
+
+#define _SetEPRxDblBuf0Count(bEpNum,wCount) {\
+ uint32_t *pdwReg = _pEPTxCount(bEpNum); \
+ _SetEPCountRxReg(pdwReg, wCount);\
+ }
+/*******************************************************************************
+* Macro Name : SetEPTxCount / SetEPRxCount.
+* Description : sets counter for the tx/rx buffer.
+* Input : bEpNum: endpoint number.
+* wCount: Counter value.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _SetEPTxCount(bEpNum,wCount) (*_pEPTxCount(bEpNum) = wCount)
+#define _SetEPRxCount(bEpNum,wCount) {\
+ uint32_t *pdwReg = _pEPRxCount(bEpNum); \
+ _SetEPCountRxReg(pdwReg, wCount);\
+ }
+/*******************************************************************************
+* Macro Name : GetEPTxCount / GetEPRxCount.
+* Description : gets counter of the tx buffer.
+* Input : bEpNum: endpoint number.
+* Output : None.
+* Return : Counter value.
+*******************************************************************************/
+#define _GetEPTxCount(bEpNum)((uint16_t)(*_pEPTxCount(bEpNum)) & 0x3ff)
+#define _GetEPRxCount(bEpNum)((uint16_t)(*_pEPRxCount(bEpNum)) & 0x3ff)
+
+/*******************************************************************************
+* Macro Name : SetEPDblBuf0Addr / SetEPDblBuf1Addr.
+* Description : Sets buffer 0/1 address in a double buffer endpoint.
+* Input : bEpNum: endpoint number.
+* : wBuf0Addr: buffer 0 address.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _SetEPDblBuf0Addr(bEpNum,wBuf0Addr) {_SetEPTxAddr(bEpNum, wBuf0Addr);}
+#define _SetEPDblBuf1Addr(bEpNum,wBuf1Addr) {_SetEPRxAddr(bEpNum, wBuf1Addr);}
+
+/*******************************************************************************
+* Macro Name : SetEPDblBuffAddr.
+* Description : Sets addresses in a double buffer endpoint.
+* Input : bEpNum: endpoint number.
+* : wBuf0Addr: buffer 0 address.
+* : wBuf1Addr = buffer 1 address.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _SetEPDblBuffAddr(bEpNum,wBuf0Addr,wBuf1Addr) { \
+ _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);\
+ _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);\
+ } /* _SetEPDblBuffAddr */
+
+/*******************************************************************************
+* Macro Name : GetEPDblBuf0Addr / GetEPDblBuf1Addr.
+* Description : Gets buffer 0/1 address of a double buffer endpoint.
+* Input : bEpNum: endpoint number.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum))
+#define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum))
+
+/*******************************************************************************
+* Macro Name : SetEPDblBuffCount / SetEPDblBuf0Count / SetEPDblBuf1Count.
+* Description : Gets buffer 0/1 address of a double buffer endpoint.
+* Input : bEpNum: endpoint number.
+* : bDir: endpoint dir EP_DBUF_OUT = OUT
+* EP_DBUF_IN = IN
+* : wCount: Counter value
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _SetEPDblBuf0Count(bEpNum, bDir, wCount) { \
+ if(bDir == EP_DBUF_OUT)\
+ /* OUT endpoint */ \
+ {_SetEPRxDblBuf0Count(bEpNum,wCount);} \
+ else if(bDir == EP_DBUF_IN)\
+ /* IN endpoint */ \
+ *_pEPTxCount(bEpNum) = (uint32_t)wCount; \
+ } /* SetEPDblBuf0Count*/
+
+#define _SetEPDblBuf1Count(bEpNum, bDir, wCount) { \
+ if(bDir == EP_DBUF_OUT)\
+ /* OUT endpoint */ \
+ {_SetEPRxCount(bEpNum,wCount);}\
+ else if(bDir == EP_DBUF_IN)\
+ /* IN endpoint */\
+ *_pEPRxCount(bEpNum) = (uint32_t)wCount; \
+ } /* SetEPDblBuf1Count */
+
+#define _SetEPDblBuffCount(bEpNum, bDir, wCount) {\
+ _SetEPDblBuf0Count(bEpNum, bDir, wCount); \
+ _SetEPDblBuf1Count(bEpNum, bDir, wCount); \
+ } /* _SetEPDblBuffCount */
+
+/*******************************************************************************
+* Macro Name : GetEPDblBuf0Count / GetEPDblBuf1Count.
+* Description : Gets buffer 0/1 rx/tx counter for double buffering.
+* Input : bEpNum: endpoint number.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+#define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum))
+#define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum))
+
+
+/* External variables --------------------------------------------------------*/
+extern __IO uint16_t wIstr; /* INTSTS register last read value */
+
+/* Exported functions ------------------------------------------------------- */
+void SetCTRL(uint16_t /*wRegValue*/);
+void SetINTSTS(uint16_t /*wRegValue*/);
+void SetDEVADR(uint16_t /*wRegValue*/);
+void SetBUFTBL(uint16_t /*wRegValue*/);
+void SetBUFTBL(uint16_t /*wRegValue*/);
+uint16_t GetCTRL(void);
+uint16_t GetINTSTS(void);
+uint16_t GetFRNUM(void);
+uint16_t GetDEVADR(void);
+uint16_t GetBUFTBL(void);
+void SetENDPOINT(uint8_t /*bEpNum*/, uint16_t /*wRegValue*/);
+uint16_t GetENDPOINT(uint8_t /*bEpNum*/);
+void SetEPType(uint8_t /*bEpNum*/, uint16_t /*wType*/);
+uint16_t GetEPType(uint8_t /*bEpNum*/);
+void SetEPTxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
+void SetEPRxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
+void SetDouBleBuffEPStall(uint8_t /*bEpNum*/, uint8_t bDir);
+uint16_t GetEPTxStatus(uint8_t /*bEpNum*/);
+uint16_t GetEPRxStatus(uint8_t /*bEpNum*/);
+void SetEPTxValid(uint8_t /*bEpNum*/);
+void SetEPRxValid(uint8_t /*bEpNum*/);
+uint16_t GetTxStallStatus(uint8_t /*bEpNum*/);
+uint16_t GetRxStallStatus(uint8_t /*bEpNum*/);
+void SetEP_SUBTYPE(uint8_t /*bEpNum*/);
+void ClearEP_SUBTYPE(uint8_t /*bEpNum*/);
+void Set_Status_Out(uint8_t /*bEpNum*/);
+void Clear_Status_Out(uint8_t /*bEpNum*/);
+void SetEPDoubleBuff(uint8_t /*bEpNum*/);
+void ClearEPDoubleBuff(uint8_t /*bEpNum*/);
+void ClearEP_CTFR_RX(uint8_t /*bEpNum*/);
+void ClearEP_CTFR_TX(uint8_t /*bEpNum*/);
+void ToggleDTOG_RX(uint8_t /*bEpNum*/);
+void ToggleDTOG_TX(uint8_t /*bEpNum*/);
+void ClearDTOG_RX(uint8_t /*bEpNum*/);
+void ClearDTOG_TX(uint8_t /*bEpNum*/);
+void SetEPAddress(uint8_t /*bEpNum*/, uint8_t /*bAddr*/);
+uint8_t GetEPAddress(uint8_t /*bEpNum*/);
+void SetEPTxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
+void SetEPRxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
+uint16_t GetEPTxAddr(uint8_t /*bEpNum*/);
+uint16_t GetEPRxAddr(uint8_t /*bEpNum*/);
+void SetEPCountRxReg(uint32_t * /*pdwReg*/, uint16_t /*wCount*/);
+void SetEPTxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
+void SetEPRxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
+uint16_t GetEPTxCount(uint8_t /*bEpNum*/);
+uint16_t GetEPRxCount(uint8_t /*bEpNum*/);
+void SetEPDblBuf0Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/);
+void SetEPDblBuf1Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf1Addr*/);
+void SetEPDblBuffAddr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/, uint16_t /*wBuf1Addr*/);
+uint16_t GetEPDblBuf0Addr(uint8_t /*bEpNum*/);
+uint16_t GetEPDblBuf1Addr(uint8_t /*bEpNum*/);
+void SetEPDblBuffCount(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+void SetEPDblBuf0Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+void SetEPDblBuf1Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
+uint16_t GetEPDblBuf0Count(uint8_t /*bEpNum*/);
+uint16_t GetEPDblBuf1Count(uint8_t /*bEpNum*/);
+EP_DBUF_DIR GetEPDblBufDir(uint8_t /*bEpNum*/);
+void FreeUserBuffer(uint8_t bEpNum/*bEpNum*/, uint8_t bDir);
+uint16_t ToWord(uint8_t, uint8_t);
+uint16_t ByteSwap(uint16_t);
+void Set_USB768ByteMode(void);
+void Clear_USB768ByteMode(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_REGS_H */
+
+
diff --git a/.platformio/packages/framework-cmsis-at32f40/Include/usb_sil.h b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_type.h
similarity index 70%
rename from .platformio/packages/framework-cmsis-at32f40/Include/usb_sil.h
rename to .platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_type.h
index 99d1218..1529319 100644
--- a/.platformio/packages/framework-cmsis-at32f40/Include/usb_sil.h
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/include/usb_type.h
@@ -1,30 +1,37 @@
/**
******************************************************************************
- * File : usb_sil.h
+ * File : usb_type.h
* Version: V1.2.2
* Date : 2020-07-01
- * Brief : Simplified Interface Layer function prototypes.
+ * Brief : Type definitions used by the USB Library
******************************************************************************
*/
-
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_SIL_H
-#define __USB_SIL_H
+#ifndef __USB_TYPE_H
+#define __USB_TYPE_H
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+#ifndef __cplusplus
+typedef enum
+{
+ FALSE = 0, TRUE = !FALSE
+}
+bool;
+#endif
+
+
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
-
-uint32_t USB_SIL_Init(void);
-uint32_t USB_SIL_Write(uint8_t bEpAddr, uint8_t* pBufferPointer, uint32_t wBufferSize);
-uint32_t USB_SIL_Read(uint8_t bEpAddr, uint8_t* pBufferPointer);
-
/* External variables --------------------------------------------------------*/
-#endif /* __USB_SIL_H */
+#endif /* __USB_TYPE_H */
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/library.properties b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/library.properties
new file mode 100644
index 0000000..8e4ec24
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/library.properties
@@ -0,0 +1,9 @@
+name=AT32_USB-FS-Device_Driver
+version=1.0.0
+author=AT
+maintainer=AT
+sentence=Source files wrapper (HAL, LL,...)
+paragraph=Allow to not archive source object files to core.a. This avoid the linker to select weak definitions instead of non-weak ones when 'whole-archive' option is not used.
+category=Other
+url=
+architectures=at32
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/src/usb_core.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/src/usb_core.c
new file mode 100644
index 0000000..6d683ce
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/src/usb_core.c
@@ -0,0 +1,973 @@
+/**
+ ******************************************************************************
+ * File : usb_core.c
+ * Version: V1.2.2
+ * Date : 2020-07-01
+ * Brief : Standard protocol processing (USB v2.0)
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define ValBit(VAR,Place) (VAR & (1 << Place))
+#define SetBit(VAR,Place) (VAR |= (1 << Place))
+#define ClrBit(VAR,Place) (VAR &= ((1 << Place) ^ 255))
+#define Send0LengthData() { _SetEPTxCount(ENDP0, 0); \
+ vSetEPTxStatus(EP_TX_VALID); \
+ }
+
+#define vSetEPRxStatus(st) (SaveRState = st)
+#define vSetEPTxStatus(st) (SaveTState = st)
+
+#define USB_StatusIn() Send0LengthData()
+#define USB_StatusOut() vSetEPRxStatus(EP_RX_VALID)
+
+#define StatusInfo0 StatusInfo.bw.bb1 /* Reverse bb0 & bb1 */
+#define StatusInfo1 StatusInfo.bw.bb0
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+uint16_t_uint8_t StatusInfo;
+
+bool Data_Mul_MaxPacketSize = FALSE;
+/* Private function prototypes -----------------------------------------------*/
+static void DataStageOut(void);
+static void DataStageIn(void);
+static void NoData_Setup0(void);
+static void Data_Setup0(void);
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief Return the current configuration variable address.
+ * @param Length: How many bytes are needed.
+ * @retval 0 if the request is invalid when Length is 0.
+ * Buffer address if the Length is not 0.
+ */
+uint8_t *Standard_GetConfiguration(uint16_t Length)
+{
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength =
+ sizeof(pInformation->Current_Configuration);
+ return 0;
+ }
+ pUser_Standard_Requests->User_GetConfiguration();
+ return (uint8_t *)&pInformation->Current_Configuration;
+}
+
+/**
+ * @brief This routine is called to set the configuration value
+ * Then each class should configure device itself.
+ * @param None.
+ * @retval USB_SUCCESS if the request is performed.
+ * USB_UNSUPPORT if the request is invalid.
+ */
+RESULT Standard_SetConfiguration(void)
+{
+
+ if ((pInformation->USBwValue0 <=
+ Device_Table.Total_Configuration) && (pInformation->USBwValue1 == 0)
+ && (pInformation->USBwIndex == 0)) /*call Back usb spec 2.0*/
+ {
+ pInformation->Current_Configuration = pInformation->USBwValue0;
+ pUser_Standard_Requests->User_SetConfiguration();
+ return USB_SUCCESS;
+ }
+ else
+ {
+ return USB_UNSUPPORT;
+ }
+}
+
+/**
+ * @brief Return the Alternate Setting of the current interface.
+ * @param Length: How many bytes are needed.
+ * @retval 0 if the request is invalid when Length is 0.
+ * Buffer address if the Length is not 0.
+ */
+uint8_t *Standard_GetInterface(uint16_t Length)
+{
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength =
+ sizeof(pInformation->Current_AlternateSetting);
+ return 0;
+ }
+ pUser_Standard_Requests->User_GetInterface();
+ return (uint8_t *)&pInformation->Current_AlternateSetting;
+}
+
+/**
+ * @brief This routine is called to set the interface.
+ * Then each class should configure the interface them self.
+ * @param None.
+ * @retval USB_SUCCESS if the request is performed.
+ * USB_UNSUPPORT if the request is invalid.
+ */
+RESULT Standard_SetInterface(void)
+{
+ RESULT Re;
+ /*Test if the specified Interface and Alternate Setting are supported by
+ the application Firmware*/
+ Re = (*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, pInformation->USBwValue0);
+
+ if (pInformation->Current_Configuration != 0)
+ {
+ if ((Re != USB_SUCCESS) || (pInformation->USBwIndex1 != 0)
+ || (pInformation->USBwValue1 != 0))
+ {
+ return USB_UNSUPPORT;
+ }
+ else if (Re == USB_SUCCESS)
+ {
+ pUser_Standard_Requests->User_SetInterface();
+ pInformation->Current_Interface = pInformation->USBwIndex0;
+ pInformation->Current_AlternateSetting = pInformation->USBwValue0;
+ return USB_SUCCESS;
+ }
+
+ }
+
+ return USB_UNSUPPORT;
+}
+
+/**
+ * @brief Copy the device request data to "StatusInfo buffer".
+ * @param Length: How many bytes are needed.
+ * @retval 0 if the Length is 0.
+ * status address if Length is valid.
+ */
+uint8_t *Standard_GetStatus(uint16_t Length)
+{
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = 2;
+ return 0;
+ }
+
+ /* Reset Status Information */
+ StatusInfo.w = 0;
+
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ /*Get Device Status */
+ uint8_t Feature = pInformation->Current_Feature;
+
+ /* Remote Wakeup enabled */
+ if (ValBit(Feature, 5))
+ {
+ SetBit(StatusInfo0, 1);
+ }
+ else
+ {
+ ClrBit(StatusInfo0, 1);
+ }
+
+ /* Bus-powered */
+ if (ValBit(Feature, 6))
+ {
+ SetBit(StatusInfo0, 0);
+ }
+ else /* Self-powered */
+ {
+ ClrBit(StatusInfo0, 0);
+ }
+ }
+ /*Interface Status*/
+ else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+ {
+ return (uint8_t *)&StatusInfo;
+ }
+ /*Get EndPoint Status*/
+ else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ {
+ uint8_t Related_Endpoint;
+ uint8_t wIndex0 = pInformation->USBwIndex0;
+
+ Related_Endpoint = (wIndex0 & 0x0f);
+ if (ValBit(wIndex0, 7))
+ {
+ /* IN endpoint */
+ if (_GetTxStallStatus(Related_Endpoint))
+ {
+ SetBit(StatusInfo0, 0); /* IN Endpoint stalled */
+ }
+ }
+ else
+ {
+ /* OUT endpoint */
+ if (_GetRxStallStatus(Related_Endpoint))
+ {
+ SetBit(StatusInfo0, 0); /* OUT Endpoint stalled */
+ }
+ }
+
+ }
+ else
+ {
+ return NULL;
+ }
+ pUser_Standard_Requests->User_GetStatus();
+ return (uint8_t *)&StatusInfo;
+}
+
+/**
+ * @brief Clear or disable a specific feature.
+ * @param None.
+ * @retval USB_SUCCESS if the request is performed.
+ * USB_UNSUPPORT if the request is invalid.
+ */
+RESULT Standard_ClearFeature(void)
+{
+ uint32_t Type_Rec = Type_Recipient;
+ uint32_t Status;
+
+
+ if (Type_Rec == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {/*Device Clear Feature*/
+ ClrBit(pInformation->Current_Feature, 5);
+ return USB_SUCCESS;
+ }
+ else if (Type_Rec == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ {/*EndPoint Clear Feature*/
+ DEVICE* pDev;
+ uint32_t Related_Endpoint;
+ uint32_t wIndex0;
+ uint32_t rEP;
+
+ if ((pInformation->USBwValue != ENDPOINT_STALL)
+ || (pInformation->USBwIndex1 != 0))
+ {
+ return USB_UNSUPPORT;
+ }
+
+ pDev = &Device_Table;
+ wIndex0 = pInformation->USBwIndex0;
+ rEP = wIndex0 & ~0x80;
+ Related_Endpoint = ENDP0 + rEP;
+
+ if (ValBit(pInformation->USBwIndex0, 7))
+ {
+ /*Get Status of endpoint & stall the request if the related_ENdpoint
+ is Disabled*/
+ Status = _GetEPTxStatus(Related_Endpoint);
+ }
+ else
+ {
+ Status = _GetEPRxStatus(Related_Endpoint);
+ }
+
+ if ((rEP >= pDev->Total_Endpoint) || (Status == 0)
+ || (pInformation->Current_Configuration == 0))
+ {
+ return USB_UNSUPPORT;
+ }
+
+
+ if (wIndex0 & 0x80)
+ {
+ /* IN endpoint */
+ if (_GetTxStallStatus(Related_Endpoint ))
+ {
+ ClearDTOG_TX(Related_Endpoint);
+ SetEPTxStatus(Related_Endpoint, EP_TX_VALID);
+ }
+ }
+ else
+ {
+ /* OUT endpoint */
+ if (_GetRxStallStatus(Related_Endpoint))
+ {
+ if (Related_Endpoint == ENDP0)
+ {
+ /* After clear the STALL, enable the default endpoint receiver */
+ SetEPRxCount(Related_Endpoint, Device_Property.MaxPacketSize);
+ _SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
+ }
+ else
+ {
+ ClearDTOG_RX(Related_Endpoint);
+ _SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
+ }
+ }
+ }
+ pUser_Standard_Requests->User_ClearFeature();
+ return USB_SUCCESS;
+ }
+
+ return USB_UNSUPPORT;
+}
+
+/**
+ * @brief Set or enable a specific feature of EndPoint.
+ * @param None.
+ * @retval USB_SUCCESS if the request is performed.
+ * USB_UNSUPPORT if the request is invalid.
+ */
+RESULT Standard_SetEndPointFeature(void)
+{
+ uint32_t wIndex0;
+ uint32_t Related_Endpoint;
+ uint32_t rEP;
+ uint32_t Status;
+
+ wIndex0 = pInformation->USBwIndex0;
+ rEP = wIndex0 & ~0x80;
+ Related_Endpoint = ENDP0 + rEP;
+
+ if (ValBit(pInformation->USBwIndex0, 7))
+ {
+ /* get Status of endpoint & stall the request if the related_ENdpoint
+ is Disabled*/
+ Status = _GetEPTxStatus(Related_Endpoint);
+ }
+ else
+ {
+ Status = _GetEPRxStatus(Related_Endpoint);
+ }
+
+ if (Related_Endpoint >= Device_Table.Total_Endpoint
+ || pInformation->USBwValue != 0 || Status == 0
+ || pInformation->Current_Configuration == 0)
+ {
+ return USB_UNSUPPORT;
+ }
+ else
+ {
+ if (wIndex0 & 0x80)
+ {
+ /* IN endpoint */
+ _SetEPTxStatus(Related_Endpoint, EP_TX_STALL);
+ }
+
+ else
+ {
+ /* OUT endpoint */
+ _SetEPRxStatus(Related_Endpoint, EP_RX_STALL);
+ }
+ }
+ pUser_Standard_Requests->User_SetEndPointFeature();
+ return USB_SUCCESS;
+}
+
+/**
+ * @brief Set or enable a specific feature of Device.
+ * @param None.
+ * @retval USB_SUCCESS if the request is performed.
+ * USB_UNSUPPORT if the request is invalid.
+ */
+RESULT Standard_SetDeviceFeature(void)
+{
+ SetBit(pInformation->Current_Feature, 5);
+ pUser_Standard_Requests->User_SetDeviceFeature();
+ return USB_SUCCESS;
+}
+
+/**
+ * @brief Standard_GetDescriptorData is used for descriptors transfer.
+ This routine is used for the descriptors resident in Flash
+ * or RAM
+ * pDesc can be in either Flash or RAM
+ * The purpose of this routine is to have a versatile way to
+ * response descriptors request. It allows user to generate
+ * certain descriptors with software or read descriptors from
+ * external storage part by part.
+ * @param Length: Length of the data in this transfer.
+ * @param pDesc: A pointer points to descriptor struct.
+ * The structure gives the initial address of the descriptor and its original size
+ * @retval Address of a part of the descriptor pointed by the Usb_wOffset the buffer pointed
+ * by this address contains at least Length bytes.
+ */
+uint8_t *Standard_GetDescriptorData(uint16_t Length, ONE_DESCRIPTOR *pDesc)
+{
+ uint32_t wOffset;
+
+ wOffset = pInformation->Ctrl_Info.Usb_wOffset;
+ if (Length == 0)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = pDesc->Descriptor_Size - wOffset;
+ return 0;
+ }
+
+ return pDesc->Descriptor + wOffset;
+}
+
+/**
+ * @brief Data stage of a Control Write Transfer.
+ * @param None.
+ * @retval None.
+ */
+void DataStageOut(void)
+{
+ ENDPOINT_INFO *pEPinfo = &pInformation->Ctrl_Info;
+ uint32_t save_rLength;
+
+ save_rLength = pEPinfo->Usb_rLength;
+
+ if (pEPinfo->CopyData && save_rLength)
+ {
+ uint8_t *Buffer;
+ uint32_t Length;
+
+ Length = pEPinfo->PacketSize;
+ if (Length > save_rLength)
+ {
+ Length = save_rLength;
+ }
+
+ Buffer = (*pEPinfo->CopyData)(Length);
+ pEPinfo->Usb_rLength -= Length;
+ pEPinfo->Usb_rOffset += Length;
+ PMAToUserBufferCopy(Buffer, GetEPRxAddr(ENDP0), Length);
+ }
+
+ if (pEPinfo->Usb_rLength != 0)
+ {
+ vSetEPRxStatus(EP_RX_VALID);/* re-enable for next data reception */
+// SetEPTxCount(ENDP0, 0);
+// vSetEPTxStatus(EP_TX_VALID);/* Expect the host to abort the data OUT stage */
+ }
+ /* Set the next State*/
+ if (pEPinfo->Usb_rLength >= pEPinfo->PacketSize)
+ {
+ pInformation->ControlState = OUT_DATA;
+ }
+ else
+ {
+ if (pEPinfo->Usb_rLength > 0)
+ {
+ pInformation->ControlState = LAST_OUT_DATA;
+ }
+ else if (pEPinfo->Usb_rLength == 0)
+ {
+ (*pEPinfo->CopyData)(0); //added to notify write to array finished
+ pInformation->ControlState = WAIT_STATUS_IN;
+ USB_StatusIn();
+ }
+ }
+}
+
+/**
+ * @brief Data stage of a Control Read Transfer.
+ * @param None.
+ * @retval None.
+ */
+void DataStageIn(void)
+{
+ ENDPOINT_INFO *pEPinfo = &pInformation->Ctrl_Info;
+ uint32_t save_wLength = pEPinfo->Usb_wLength;
+ uint32_t ControlState = pInformation->ControlState;
+
+ uint8_t *DataBuffer;
+ uint32_t Length;
+
+ if ((save_wLength == 0) && (ControlState == LAST_IN_DATA))
+ {
+ if(Data_Mul_MaxPacketSize == TRUE)
+ {
+ /* No more data to send and empty packet */
+ Send0LengthData();
+ ControlState = LAST_IN_DATA;
+ Data_Mul_MaxPacketSize = FALSE;
+ }
+ else
+ {
+ /* No more data to send so STALL the TX Status*/
+ ControlState = WAIT_STATUS_OUT;
+ vSetEPTxStatus(EP_TX_STALL);
+ }
+ goto Expect_Status_Out;
+ }
+
+ Length = pEPinfo->PacketSize;
+ ControlState = (save_wLength <= Length) ? LAST_IN_DATA : IN_DATA;
+
+ if (Length > save_wLength)
+ {
+ Length = save_wLength;
+ }
+
+ DataBuffer = (*pEPinfo->CopyData)(Length);
+
+ UserToPMABufferCopy(DataBuffer, GetEPTxAddr(ENDP0), Length);
+
+ SetEPTxCount(ENDP0, Length);
+
+ pEPinfo->Usb_wLength -= Length;
+ pEPinfo->Usb_wOffset += Length;
+ vSetEPTxStatus(EP_TX_VALID);
+
+ USB_StatusOut();/* Expect the host to abort the data IN stage */
+
+Expect_Status_Out:
+ pInformation->ControlState = ControlState;
+}
+
+/**
+ * @brief Proceed the processing of setup request without data stage.
+ * @param None.
+ * @retval None.
+ */
+void NoData_Setup0(void)
+{
+ RESULT Result = USB_UNSUPPORT;
+ uint32_t RequestNo = pInformation->USBbRequest;
+ uint32_t ControlState;
+
+ /* Device Request*/
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ /* Device Request*/
+ /* SET_CONFIGURATION*/
+ if (RequestNo == SET_CONFIGURATION)
+ {
+ Result = Standard_SetConfiguration();
+ }
+
+ /*SET ADDRESS*/
+ else if (RequestNo == SET_ADDRESS)
+ {
+ if ((pInformation->USBwValue0 > 127) || (pInformation->USBwValue1 != 0)
+ || (pInformation->USBwIndex != 0)
+ || (pInformation->Current_Configuration != 0))
+ /* Device Address should be 127 or less*/
+ {
+ ControlState = STALLED;
+ goto exit_NoData_Setup0;
+ }
+ else
+ {
+ Result = USB_SUCCESS;
+ }
+ }
+ /*SET FEATURE for Device*/
+ else if (RequestNo == SET_FEATURE)
+ {
+ if ((pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP) \
+ && (pInformation->USBwIndex == 0))
+ {
+ Result = Standard_SetDeviceFeature();
+ }
+ else
+ {
+ Result = USB_UNSUPPORT;
+ }
+ }
+ /*Clear FEATURE for Device */
+ else if (RequestNo == CLEAR_FEATURE)
+ {
+ if (pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP
+ && pInformation->USBwIndex == 0
+ && ValBit(pInformation->Current_Feature, 5))
+ {
+ Result = Standard_ClearFeature();
+ }
+ else
+ {
+ Result = USB_UNSUPPORT;
+ }
+ }
+
+ }
+
+ /* Interface Request*/
+ else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+ {
+ /*SET INTERFACE*/
+ if (RequestNo == SET_INTERFACE)
+ {
+ Result = Standard_SetInterface();
+ }
+ }
+
+ /* EndPoint Request*/
+ else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ {
+ /*CLEAR FEATURE for EndPoint*/
+ if (RequestNo == CLEAR_FEATURE)
+ {
+ Result = Standard_ClearFeature();
+ }
+ /* SET FEATURE for EndPoint*/
+ else if (RequestNo == SET_FEATURE)
+ {
+ Result = Standard_SetEndPointFeature();
+ }
+ }
+ else
+ {
+ Result = USB_UNSUPPORT;
+ }
+
+
+ if (Result != USB_SUCCESS)
+ {
+ Result = (*pProperty->Class_NoData_Setup)(RequestNo);
+ if (Result == USB_NOT_READY)
+ {
+ ControlState = PAUSE;
+ goto exit_NoData_Setup0;
+ }
+ }
+
+ if (Result != USB_SUCCESS)
+ {
+ ControlState = STALLED;
+ goto exit_NoData_Setup0;
+ }
+
+ ControlState = WAIT_STATUS_IN;/* After no data stage SETUP */
+
+ USB_StatusIn();
+
+exit_NoData_Setup0:
+ pInformation->ControlState = ControlState;
+ return;
+}
+
+/**
+ * @brief Proceed the processing of setup request with data stage.
+ * @param None.
+ * @retval None.
+ */
+void Data_Setup0(void)
+{
+ uint8_t *(*CopyRoutine)(uint16_t);
+ RESULT Result;
+ uint32_t Request_No = pInformation->USBbRequest;
+
+ uint32_t Related_Endpoint, Reserved;
+ uint32_t wOffset, Status;
+
+
+
+ CopyRoutine = NULL;
+ wOffset = 0;
+
+ /*GET DESCRIPTOR*/
+ if (Request_No == GET_DESCRIPTOR)
+ {
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ uint8_t wValue1 = pInformation->USBwValue1;
+ if (wValue1 == DEVICE_DESCRIPTOR)
+ {
+ CopyRoutine = pProperty->GetDeviceDescriptor;
+ }
+ else if (wValue1 == CONFIG_DESCRIPTOR)
+ {
+ CopyRoutine = pProperty->GetConfigDescriptor;
+ }
+ else if (wValue1 == STRING_DESCRIPTOR)
+ {
+ CopyRoutine = pProperty->GetStringDescriptor;
+ } /* End of GET_DESCRIPTOR */
+ }
+ }
+
+ /*GET STATUS*/
+ else if ((Request_No == GET_STATUS) && (pInformation->USBwValue == 0)
+ && (pInformation->USBwLength == 0x0002)
+ && (pInformation->USBwIndex1 == 0))
+ {
+ /* GET STATUS for Device*/
+ if ((Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ && (pInformation->USBwIndex == 0))
+ {
+ CopyRoutine = Standard_GetStatus;
+ }
+
+ /* GET STATUS for Interface*/
+ else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+ {
+ if (((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == USB_SUCCESS)
+ && (pInformation->Current_Configuration != 0))
+ {
+ CopyRoutine = Standard_GetStatus;
+ }
+ }
+
+ /* GET STATUS for EndPoint*/
+ else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
+ {
+ Related_Endpoint = (pInformation->USBwIndex0 & 0x0f);
+ Reserved = pInformation->USBwIndex0 & 0x70;
+
+ if (ValBit(pInformation->USBwIndex0, 7))
+ {
+ /*Get Status of endpoint & stall the request if the related_ENdpoint
+ is Disabled*/
+ Status = _GetEPTxStatus(Related_Endpoint);
+ }
+ else
+ {
+ Status = _GetEPRxStatus(Related_Endpoint);
+ }
+
+ if ((Related_Endpoint < Device_Table.Total_Endpoint) && (Reserved == 0)
+ && (Status != 0))
+ {
+ CopyRoutine = Standard_GetStatus;
+ }
+ }
+
+ }
+
+ /*GET CONFIGURATION*/
+ else if (Request_No == GET_CONFIGURATION)
+ {
+ if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
+ {
+ CopyRoutine = Standard_GetConfiguration;
+ }
+ }
+ /*GET INTERFACE*/
+ else if (Request_No == GET_INTERFACE)
+ {
+ if ((Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
+ && (pInformation->Current_Configuration != 0) && (pInformation->USBwValue == 0)
+ && (pInformation->USBwIndex1 == 0) && (pInformation->USBwLength == 0x0001)
+ && ((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == USB_SUCCESS))
+ {
+ CopyRoutine = Standard_GetInterface;
+ }
+
+ }
+
+ if (CopyRoutine)
+ {
+ pInformation->Ctrl_Info.Usb_wOffset = wOffset;
+ pInformation->Ctrl_Info.CopyData = CopyRoutine;
+ /* sb in the original the cast to word was directly */
+ /* now the cast is made step by step */
+ (*CopyRoutine)(0);
+ Result = USB_SUCCESS;
+ }
+ else
+ {
+ Result = (*pProperty->Class_Data_Setup)(pInformation->USBbRequest);
+ if (Result == USB_NOT_READY)
+ {
+ pInformation->ControlState = PAUSE;
+ return;
+ }
+ }
+
+ if (pInformation->Ctrl_Info.Usb_wLength == 0xFFFF)
+ {
+ /* Data is not ready, wait it */
+ pInformation->ControlState = PAUSE;
+ return;
+ }
+ if ((Result == USB_UNSUPPORT) || (pInformation->Ctrl_Info.Usb_wLength == 0))
+ {
+ /* Unsupported request */
+ pInformation->ControlState = STALLED;
+ return;
+ }
+
+
+ if (ValBit(pInformation->USBbmRequestType, 7))
+ {
+ /* Device ==> Host */
+ __IO uint32_t wLength = pInformation->USBwLength;
+
+ /* Restrict the data length to be the one host asks for */
+ if (pInformation->Ctrl_Info.Usb_wLength > wLength)
+ {
+ pInformation->Ctrl_Info.Usb_wLength = wLength;
+ }
+
+ else if (pInformation->Ctrl_Info.Usb_wLength < pInformation->USBwLength)
+ {
+ if (pInformation->Ctrl_Info.Usb_wLength < pProperty->MaxPacketSize)
+ {
+ Data_Mul_MaxPacketSize = FALSE;
+ }
+ else if ((pInformation->Ctrl_Info.Usb_wLength % pProperty->MaxPacketSize) == 0)
+ {
+ Data_Mul_MaxPacketSize = TRUE;
+ }
+ }
+
+ pInformation->Ctrl_Info.PacketSize = pProperty->MaxPacketSize;
+ DataStageIn();
+ }
+ else
+ {
+ pInformation->ControlState = OUT_DATA;
+ vSetEPRxStatus(EP_RX_VALID); /* enable for next data reception */
+ }
+
+ return;
+}
+
+/**
+ * @brief Get the device request data and dispatch to individual process.
+ * @param None.
+ * @retval None.
+ */
+uint8_t Setup0_Process(void)
+{
+
+ union
+ {
+ uint8_t* b;
+ uint16_t* w;
+ } pBuf;
+ uint16_t offset = 1;
+
+ pBuf.b = PMAAddr + (uint8_t *)(_GetEPRxAddr(ENDP0) * 2); /* *2 for 32 bits addr */
+
+ if (pInformation->ControlState != PAUSE)
+ {
+ pInformation->USBbmRequestType = *pBuf.b++; /* bmRequestType */
+ pInformation->USBbRequest = *pBuf.b++; /* bRequest */
+ pBuf.w += offset; /* word not accessed because of 32 bits addressing */
+ pInformation->USBwValue = ByteSwap(*pBuf.w++); /* wValue */
+ pBuf.w += offset; /* word not accessed because of 32 bits addressing */
+ pInformation->USBwIndex = ByteSwap(*pBuf.w++); /* wIndex */
+ pBuf.w += offset; /* word not accessed because of 32 bits addressing */
+ pInformation->USBwLength = *pBuf.w; /* wLength */
+ }
+
+ pInformation->ControlState = SETTING_UP;
+ if (pInformation->USBwLength == 0)
+ {
+ /* Setup with no data stage */
+ NoData_Setup0();
+ }
+ else
+ {
+ /* Setup with data stage */
+ Data_Setup0();
+ }
+ return Post0_Process();
+}
+
+/**
+ * @brief Process the IN token on all default endpoint.
+ * @param None.
+ * @retval None.
+ */
+uint8_t In0_Process(void)
+{
+ uint32_t ControlState = pInformation->ControlState;
+
+ if ((ControlState == IN_DATA) || (ControlState == LAST_IN_DATA))
+ {
+ DataStageIn();
+ /* ControlState may be changed outside the function */
+ ControlState = pInformation->ControlState;
+ }
+
+ else if (ControlState == WAIT_STATUS_IN)
+ {
+ if ((pInformation->USBbRequest == SET_ADDRESS) &&
+ (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)))
+ {
+ SetDeviceAddress(pInformation->USBwValue0);
+ pUser_Standard_Requests->User_SetDeviceAddress();
+ }
+ (*pProperty->Process_Status_IN)();
+ ControlState = STALLED;
+ }
+
+ else
+ {
+ ControlState = STALLED;
+ }
+
+ pInformation->ControlState = ControlState;
+
+ return Post0_Process();
+}
+
+/**
+ * @brief Process the OUT token on all default endpoint.
+ * @param None.
+ * @retval None.
+ */
+uint8_t Out0_Process(void)
+{
+ uint32_t ControlState = pInformation->ControlState;
+
+ if ((ControlState == IN_DATA) || (ControlState == LAST_IN_DATA))
+ {
+ /* host aborts the transfer before finish */
+ ControlState = STALLED;
+ }
+ else if ((ControlState == OUT_DATA) || (ControlState == LAST_OUT_DATA))
+ {
+ DataStageOut();
+ ControlState = pInformation->ControlState; /* may be changed outside the function */
+ }
+
+ else if (ControlState == WAIT_STATUS_OUT)
+ {
+ (*pProperty->Process_Status_OUT)();
+ ControlState = STALLED;
+ }
+
+
+ /* Unexpect state, STALL the endpoint */
+ else
+ {
+ ControlState = STALLED;
+ }
+
+ pInformation->ControlState = ControlState;
+
+ return Post0_Process();
+}
+
+/**
+ * @brief Stall the Endpoint 0 in case of error.
+ * @param None.
+ * @retval 0 if the control state is in PAUSE.
+ * 1 if not.
+ */
+uint8_t Post0_Process(void)
+{
+
+ SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
+ /*no need set to STALL*/
+ if (pInformation->ControlState == STALLED)
+ {
+ vSetEPRxStatus(EP_RX_STALL);
+ vSetEPTxStatus(EP_TX_STALL);
+ }
+
+ return (pInformation->ControlState == PAUSE);
+}
+
+/**
+ * @brief Set the device and all the used Endpoints addresses.
+ * @param Val: the device address
+ * @retval None.
+ */
+void SetDeviceAddress(uint8_t Val)
+{
+ uint32_t i;
+ uint32_t nEP = Device_Table.Total_Endpoint;
+
+ /* set address in every used endpoint */
+ for (i = 0; i < nEP; i++)
+ {
+ _SetEPAddress((uint8_t)i, (uint8_t)i);
+ } /* for */
+ _SetDEVADR(Val | DEVADR_EN); /* set device address and enable function */
+}
+/**
+ * @brief No operation function.
+ * @param None.
+ * @retval None.
+ */
+void NOP_Process(void)
+{
+}
+
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/src/usb_init.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/src/usb_init.c
new file mode 100644
index 0000000..673abe3
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/src/usb_init.c
@@ -0,0 +1,103 @@
+/**
+ ******************************************************************************
+ * File : usb_init.c
+ * Version: V1.2.2
+ * Date : 2020-07-01
+ * Brief : Initialization routines & global variables
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* The number of current endpoint, it will be used to specify an endpoint */
+ uint8_t EPindex;
+/* The number of current device, it is an index to the Device_Table */
+/* uint8_t Device_no; */
+/* Points to the DEVICE_INFO structure of current device */
+/* The purpose of this register is to speed up the execution */
+DEVICE_INFO *pInformation;
+/* Points to the DEVICE_PROP structure of current device */
+/* The purpose of this register is to speed up the execution */
+DEVICE_PROP *pProperty;
+/* Temporary save the state of Rx & Tx status. */
+/* Whenever the Rx or Tx state is changed, its value is saved */
+/* in this variable first and will be set to the EPRB or EPRA */
+/* at the end of interrupt process */
+uint16_t SaveState ;
+uint16_t wInterrupt_Mask;
+DEVICE_INFO Device_Info;
+USER_STANDARD_REQUESTS *pUser_Standard_Requests;
+
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : USB_Init
+* Description : USB system initialization
+* Input : None.
+* Output : None.
+* Return : None.
+*******************************************************************************/
+
+/* Re-enumerate the USB */
+void reenumerate() {
+ // pinMode(PA12, OUTPUT);
+ GPIO_InitType GPIO_InitStruct = {0};
+ GPIO_InitStruct.GPIO_Pins = GPIO_Pins_12;
+ GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_PU;
+ GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
+ GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ GPIO_WriteBit(GPIOA, GPIO_Pins_12, Bit_RESET); //Blue Pill
+ for(int i=0;i<1512;i++){};
+
+ GPIO_InitStruct.GPIO_Pins = GPIO_Pins_12;
+ GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
+ GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ for(int i=0;i<512;i++){};
+}
+
+void USB_BluePill_Reenumerate()
+{
+ //__HAL_RCC_GPIOA_CLK_ENABLE();
+
+ GPIO_InitType GPIO_InitStruct = {0};
+
+ GPIO_InitStruct.GPIO_Pins = GPIO_Pins_12;
+ GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT_OD;
+ GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
+ GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ GPIO_WriteBit(GPIOA, GPIO_Pins_12, Bit_RESET);
+ //HAL_Delay(1);
+}
+
+/**
+ * @brief USB system initialization.
+ * @param None.
+ * @retval None.
+ */
+void USB_Init(void)
+{
+ //reenumerate();
+ //USB_BluePill_Reenumerate();
+ pInformation = &Device_Info;
+ pInformation->ControlState = 2;
+ pProperty = &Device_Property;
+ pUser_Standard_Requests = &User_Standard_Requests;
+ /* Initialize devices one by one */
+ pProperty->Init();
+ //reenumerate();
+ //USB_BluePill_Reenumerate();
+}
+
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/src/usb_int.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/src/usb_int.c
new file mode 100644
index 0000000..1358e90
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/src/usb_int.c
@@ -0,0 +1,176 @@
+/**
+ ******************************************************************************
+ * File : usb_int.c
+ * Version: V1.2.2
+ * Date : 2020-07-01
+ * Brief : Endpoint CTRF (Low and High) interrupt's service routines
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint16_t SaveRState;
+__IO uint16_t SaveTState;
+
+/* Extern variables ----------------------------------------------------------*/
+extern void (*pEpInt_IN[7])(void); /* Handles IN interrupts */
+extern void (*pEpInt_OUT[7])(void); /* Handles OUT interrupts */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief Low priority Endpoint Correct Transfer interrupt's service.
+ * routine.
+ * @param None.
+ * @retval None.
+ */
+void CTR_LP(void)
+{
+ __IO uint16_t wEPVal = 0;
+ /* stay in loop while pending interrupts */
+ while (((wIstr = _GetINTSTS()) & INTSTS_CTFR) != 0)
+ {
+ /* extract highest priority endpoint number */
+ EPindex = (uint8_t)(wIstr & INTSTS_EP_ID);
+ if (EPindex != 0 )
+ {
+ /* Decode and service non control endpoints interrupt */
+
+ /* process related endpoint register */
+ wEPVal = _GetENDPOINT(EPindex);
+ if ((wEPVal & EP_CTFR_TX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTFR_TX(EPindex);
+
+ /* call IN service function */
+ (*pEpInt_IN[EPindex-1])();
+ continue;
+ } /* if((wEPVal & EP_CTFR_TX) != 0) */
+
+ if ((wEPVal & EP_CTFR_RX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTFR_RX(EPindex);
+
+ /* call OUT service function */
+ (*pEpInt_OUT[EPindex-1])();
+
+ } /* if((wEPVal & EP_CTFR_RX) */
+
+ }/* if(EPindex != 0) */
+ else
+ {
+ /* Decode and service control endpoint interrupt */
+ /* calling related service routine */
+ /* (Setup0_Process, In0_Process, Out0_Process) */
+
+ /* save RX & TX status */
+ /* and set both to NAK */
+
+ SaveRState = _GetENDPOINT(ENDP0);
+ SaveTState = SaveRState & EP_STS_TX;
+ SaveRState &= EP_STS_RX;
+
+ _SetEPRxTxStatus(ENDP0,EP_RX_NAK,EP_TX_NAK);
+
+ /* DIR bit = origin of the interrupt */
+
+ if ((wIstr & INTSTS_DIR) == 0)
+ {
+ /* DIR = 0 */
+
+ /* DIR = 0 => IN int */
+ /* DIR = 0 implies that (EP_CTFR_TX = 1) always */
+
+ _ClearEP_CTFR_TX(ENDP0);
+ In0_Process();
+
+ /* before terminate set Tx & Rx status */
+
+ _SetEPRxTxStatus(ENDP0,SaveRState,SaveTState);
+ return;
+ }
+ else
+ {
+ /* DIR = 1 */
+
+ /* DIR = 1 & CTR_RX => SETUP or OUT int */
+ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+
+ wEPVal = _GetENDPOINT(ENDP0);
+
+ if ((wEPVal &EP_SETUP) != 0)
+ {
+ _ClearEP_CTFR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */
+ Setup0_Process();
+ /* before terminate set Tx & Rx status */
+
+ _SetEPRxTxStatus(ENDP0,SaveRState,SaveTState);
+ return;
+ }
+
+ else if ((wEPVal & EP_CTFR_RX) != 0)
+ {
+ _ClearEP_CTFR_RX(ENDP0);
+ Out0_Process();
+ /* before terminate set Tx & Rx status */
+
+ _SetEPRxTxStatus(ENDP0,SaveRState,SaveTState);
+ return;
+ }
+ }
+ }/* if(EPindex != 0) else */
+
+ }/* while(...) */
+}
+
+/**
+ * @brief High Priority Endpoint Correct Transfer interrupt's service.
+ * routine.
+ * @param None.
+ * @retval None.
+ */
+void CTR_HP(void)
+{
+ uint32_t wEPVal = 0;
+
+ while (((wIstr = _GetINTSTS()) & INTSTS_CTFR) != 0)
+ {
+ _SetINTSTS((uint16_t)CLR_CTFR); /* clear CTR flag */
+ /* extract highest priority endpoint number */
+ EPindex = (uint8_t)(wIstr & INTSTS_EP_ID);
+ if ( EPindex == 0 )
+ return;
+ /* process related endpoint register */
+ wEPVal = _GetENDPOINT(EPindex);
+ if ((wEPVal & EP_CTFR_RX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTFR_RX(EPindex);
+
+ /* call OUT service function */
+ (*pEpInt_OUT[EPindex-1])();
+
+ } /* if((wEPVal & EP_CTFR_RX) */
+ else if ((wEPVal & EP_CTFR_TX) != 0)
+ {
+ /* clear int flag */
+ _ClearEP_CTFR_TX(EPindex);
+
+ /* call IN service function */
+ (*pEpInt_IN[EPindex-1])();
+
+
+ } /* if((wEPVal & EP_CTFR_TX) != 0) */
+
+ }/* while(...) */
+}
+
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/src/usb_mem.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/src/usb_mem.c
new file mode 100644
index 0000000..58724d8
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/src/usb_mem.c
@@ -0,0 +1,65 @@
+/**
+ ******************************************************************************
+ * File : usb_mem.c
+ * Version: V1.2.2
+ * Date : 2020-07-01
+ * Brief : Utility functions for memory transfers to/from PMA
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Extern variables ----------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA).
+ * @param pbUsrBuf: pointer to user memory area.
+ * @param wPMABufAddr: address into PMA.
+ * @param wNBytes: number of bytes to be copied.
+ * @retval None.
+ */
+void UserToPMABufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */
+ uint32_t i, temp1, temp2;
+ uint16_t *pdwVal;
+ pdwVal = (uint16_t *)(wPMABufAddr * 2 + PMAAddr);
+ for (i = n; i != 0; i--)
+ {
+ temp1 = (uint16_t) * pbUsrBuf;
+ pbUsrBuf++;
+ temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
+ *pdwVal++ = temp2;
+ pdwVal++;
+ pbUsrBuf++;
+ }
+}
+
+/**
+ * @brief Copy a buffer from packet memory area (PMA) to user memory area.
+ * @param pbUsrBuf: pointer to user memory area.
+ * @param wPMABufAddr: address into PMA.
+ * @param wNBytes: number of bytes to be copied.
+ * @retval None.
+ */
+void PMAToUserBufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (wNBytes + 1) >> 1;/* /2*/
+ uint32_t i;
+ uint32_t *pdwVal;
+ pdwVal = (uint32_t *)(wPMABufAddr * 2 + PMAAddr);
+ for (i = n; i != 0; i--)
+ {
+ *(uint16_t*)pbUsrBuf++ = *pdwVal++;
+ pbUsrBuf++;
+ }
+}
+
+
diff --git a/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/src/usb_regs.c b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/src/usb_regs.c
new file mode 100644
index 0000000..05cd858
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/libraries/AT32_USB-FS-Device_Driver/src/usb_regs.c
@@ -0,0 +1,692 @@
+/**
+ ******************************************************************************
+ * File : usb_reg.c
+ * Version: V1.2.2
+ * Date : 2020-07-01
+ * Brief : Interface functions to USB cell registers
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "usb_lib.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Extern variables ----------------------------------------------------------*/
+int PMAAddr = 0x40006000;
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief Set the CTRL register value.
+ * @param wRegValue: new register value.
+ * @retval None.
+ */
+void SetCTRL(uint16_t wRegValue)
+{
+ _SetCTRL(wRegValue);
+}
+
+/**
+ * @brief returns the CTRL register value.
+ * @param None.
+ * @retval CTRL register Value..
+ */
+uint16_t GetCTRL(void)
+{
+ return(_GetCTRL());
+}
+
+/**
+ * @brief Set the INTSTS register value.
+ * @param wRegValue: new register value.
+ * @retval None.
+ */
+void SetINTSTS(uint16_t wRegValue)
+{
+ _SetINTSTS(wRegValue);
+}
+
+/**
+ * @brief Returns the INTSTS register value.
+ * @param None.
+ * @retval INTSTS register Value.
+ */
+uint16_t GetINTSTS(void)
+{
+ return(_GetINTSTS());
+}
+
+/**
+ * @brief Returns the FRNUM register value.
+ * @param None.
+ * @retval FRNUM register Value.
+ */
+uint16_t GetFRNUM(void)
+{
+ return(_GetFRNUM());
+}
+
+/**
+ * @brief Set the DEVADR register value.
+ * @param wRegValue: new register value.
+ * @retval None.
+ */
+void SetDEVADR(uint16_t wRegValue)
+{
+ _SetDEVADR(wRegValue);
+}
+
+/**
+ * @brief Returns the DEVADR register value.
+ * @param None.
+ * @retval DEVADR register Value.
+ */
+uint16_t GetDEVADR(void)
+{
+ return(_GetDEVADR());
+}
+
+/**
+ * @brief Set the BUFTBL.
+ * @param wRegValue: New register value.
+ * @retval None.
+ */
+void SetBUFTBL(uint16_t wRegValue)
+{
+ _SetBUFTBL(wRegValue);
+}
+
+/**
+ * @brief Returns the BUFTBL register value.
+ * @param None
+ * @retval BUFTBL address.
+ */
+uint16_t GetBUFTBL(void)
+{
+ return(_GetBUFTBL());
+}
+
+/**
+ * @brief Set the Endpoint register value.
+ * @param bEpNum: Endpoint Number.
+ * @param wRegValue: New register value.
+ * @retval None.
+ */
+void SetENDPOINT(uint8_t bEpNum, uint16_t wRegValue)
+{
+ _SetENDPOINT(bEpNum, wRegValue);
+}
+
+/**
+ * @brief Return the Endpoint register value.
+ * @param bEpNum: Endpoint Number.
+ * @retval Endpoint register value.
+ */
+uint16_t GetENDPOINT(uint8_t bEpNum)
+{
+ return(_GetENDPOINT(bEpNum));
+}
+
+/**
+ * @brief sets the type in the endpoint register.
+ * @param bEpNum: Endpoint Number.
+ * @param wType: type definition.
+ * @retval None.
+ */
+void SetEPType(uint8_t bEpNum, uint16_t wType)
+{
+ _SetEPType(bEpNum, wType);
+}
+
+/**
+ * @brief Returns the endpoint type.
+ * @param bEpNum: Endpoint Number.
+ * @retval Endpoint Type.
+ */
+uint16_t GetEPType(uint8_t bEpNum)
+{
+ return(_GetEPType(bEpNum));
+}
+
+/**
+ * @brief Set the status of Tx endpoint.
+ * @param bEpNum: Endpoint Number.
+ * @param wState: new state.
+ * @retval None.
+ */
+void SetEPTxStatus(uint8_t bEpNum, uint16_t wState)
+{
+ _SetEPTxStatus(bEpNum, wState);
+}
+
+/**
+ * @brief Set the status of Rx endpoint.
+ * @param bEpNum: Endpoint Number.
+ * @param wState: new state.
+ * @retval None.
+ */
+void SetEPRxStatus(uint8_t bEpNum, uint16_t wState)
+{
+ _SetEPRxStatus(bEpNum, wState);
+}
+
+/**
+ * @brief sets the status for Double Buffer Endpoint to STALL
+ * @param bEpNum: Endpoint Number.
+ * @param bDir: Endpoint direction.
+ * @retval None.
+ */
+void SetDouBleBuffEPStall(uint8_t bEpNum, uint8_t bDir)
+{
+ uint16_t Endpoint_DTOG_Status;
+ Endpoint_DTOG_Status = GetENDPOINT(bEpNum);
+ if (bDir == EP_DBUF_OUT)
+ { /* OUT double buffered endpoint */
+ _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPRX_DTOG1);
+ }
+ else if (bDir == EP_DBUF_IN)
+ { /* IN double buffered endpoint */
+ _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPTX_DTOG1);
+ }
+}
+
+/**
+ * @brief Returns the endpoint Tx status.
+ * @param bEpNum: Endpoint Number.
+ * @retval Endpoint TX Status.
+ */
+uint16_t GetEPTxStatus(uint8_t bEpNum)
+{
+ return(_GetEPTxStatus(bEpNum));
+}
+
+/**
+ * @brief Returns the endpoint Rx status.
+ * @param bEpNum: Endpoint Number.
+ * @retval Endpoint RX Status.
+ */
+uint16_t GetEPRxStatus(uint8_t bEpNum)
+{
+ return(_GetEPRxStatus(bEpNum));
+}
+
+/**
+ * @brief Valid the endpoint Tx Status.
+ * @param bEpNum: Endpoint Number.
+ * @retval None.
+ */
+void SetEPTxValid(uint8_t bEpNum)
+{
+ _SetEPTxStatus(bEpNum, EP_TX_VALID);
+}
+
+/**
+ * @brief Valid the endpoint Rx Status.
+ * @param bEpNum: Endpoint Number.
+ * @retval None.
+ */
+void SetEPRxValid(uint8_t bEpNum)
+{
+ _SetEPRxStatus(bEpNum, EP_RX_VALID);
+}
+
+/**
+ * @brief Clear the EP_SUBTYPE bit.
+ * @param bEpNum: Endpoint Number.
+ * @retval None.
+ */
+void SetEP_SUBTYPE(uint8_t bEpNum)
+{
+ _SetEP_SUBTYPE(bEpNum);
+}
+
+/**
+ * @brief set the EP_SUBTYPE bit.
+ * @param bEpNum: Endpoint Number.
+ * @retval None.
+ */
+void ClearEP_SUBTYPE(uint8_t bEpNum)
+{
+ _ClearEP_SUBTYPE(bEpNum);
+}
+
+/**
+ * @brief Clear the Status Out of the related Endpoint
+ * @param bEpNum: Endpoint Number.
+ * @retval None.
+ */
+void Clear_Status_Out(uint8_t bEpNum)
+{
+ _ClearEP_SUBTYPE(bEpNum);
+}
+
+/**
+ * @brief Set the Status Out of the related Endpoint
+ * @param bEpNum: Endpoint Number.
+ * @retval None.
+ */
+void Set_Status_Out(uint8_t bEpNum)
+{
+ _SetEP_SUBTYPE(bEpNum);
+}
+
+/**
+ * @brief Enable the double buffer feature for the endpoint.
+ * @param bEpNum: Endpoint Number.
+ * @retval None.
+ */
+void SetEPDoubleBuff(uint8_t bEpNum)
+{
+ _SetEP_SUBTYPE(bEpNum);
+}
+
+/**
+ * @brief Disable the double buffer feature for the endpoint.
+ * @param bEpNum: Endpoint Number.
+ * @retval None.
+ */
+void ClearEPDoubleBuff(uint8_t bEpNum)
+{
+ _ClearEP_SUBTYPE(bEpNum);
+}
+
+/**
+ * @brief Returns the Stall status of the Tx endpoint.
+ * @param bEpNum: Endpoint Number.
+ * @retval Tx Stall status.
+ */
+uint16_t GetTxStallStatus(uint8_t bEpNum)
+{
+ return(_GetTxStallStatus(bEpNum));
+}
+
+/**
+ * @brief Returns the Stall status of the Rx endpoint.
+ * @param bEpNum: Endpoint Number.
+ * @retval Rx Stall status.
+ */
+uint16_t GetRxStallStatus(uint8_t bEpNum)
+{
+ return(_GetRxStallStatus(bEpNum));
+}
+
+/**
+ * @brief Clear the CTRF_RX bit.
+ * @param bEpNum: Endpoint Number.
+ * @retval None.
+ */
+void ClearEP_CTFR_RX(uint8_t bEpNum)
+{
+ _ClearEP_CTFR_RX(bEpNum);
+}
+
+/**
+ * @brief Clear the CTRF_TX bit.
+ * @param bEpNum: Endpoint Number.
+ * @retval None.
+ */
+void ClearEP_CTFR_TX(uint8_t bEpNum)
+{
+ _ClearEP_CTFR_TX(bEpNum);
+}
+
+/**
+ * @brief Toggle the DTOG_RX bit.
+ * @param bEpNum: Endpoint Number.
+ * @retval None.
+ */
+void ToggleDTOG_RX(uint8_t bEpNum)
+{
+ _ToggleDTOG_RX(bEpNum);
+}
+
+/**
+ * @brief Toggle the DTOG_TX bit.
+ * @param bEpNum: Endpoint Number.
+ * @retval None.
+ */
+void ToggleDTOG_TX(uint8_t bEpNum)
+{
+ _ToggleDTOG_TX(bEpNum);
+}
+
+/**
+ * @brief Clear the DTOG_RX bit.
+ * @param bEpNum: Endpoint Number.
+ * @retval None.
+ */
+void ClearDTOG_RX(uint8_t bEpNum)
+{
+ _ClearDTOG_RX(bEpNum);
+}
+
+/**
+ * @brief Clear the DTOG_TX bit.
+ * @param bEpNum: Endpoint Number.
+ * @retval None.
+ */
+void ClearDTOG_TX(uint8_t bEpNum)
+{
+ _ClearDTOG_TX(bEpNum);
+}
+
+/**
+ * @brief Set the endpoint address.
+ * @param bEpNum: Endpoint Number.
+ * @param bAddr: New endpoint address.
+ * @retval None.
+ */
+void SetEPAddress(uint8_t bEpNum, uint8_t bAddr)
+{
+ _SetEPAddress(bEpNum, bAddr);
+}
+
+/**
+ * @brief Get the endpoint address.
+ * @param bEpNum: Endpoint Number.
+ * @retval Endpoint address.
+ */
+uint8_t GetEPAddress(uint8_t bEpNum)
+{
+ return(_GetEPAddress(bEpNum));
+}
+
+/**
+ * @brief Set the endpoint Tx buffer address.
+ * @param bEpNum: Endpoint Number.
+ * @param wAddr: New address.
+ * @retval None.
+ */
+void SetEPTxAddr(uint8_t bEpNum, uint16_t wAddr)
+{
+ _SetEPTxAddr(bEpNum, wAddr);
+}
+
+/**
+ * @brief Set the endpoint Rx buffer address.
+ * @param bEpNum: Endpoint Number.
+ * @param wAddr: New address.
+ * @retval None.
+ */
+void SetEPRxAddr(uint8_t bEpNum, uint16_t wAddr)
+{
+ _SetEPRxAddr(bEpNum, wAddr);
+}
+
+/**
+ * @brief Returns the endpoint Tx buffer address.
+ * @param bEpNum: Endpoint Number.
+ * @retval Tx buffer address.
+ */
+uint16_t GetEPTxAddr(uint8_t bEpNum)
+{
+ return(_GetEPTxAddr(bEpNum));
+}
+
+/**
+ * @brief Returns the endpoint Rx buffer address.
+ * @param bEpNum: Endpoint Number.
+ * @retval Rx buffer address.
+ */
+uint16_t GetEPRxAddr(uint8_t bEpNum)
+{
+ return(_GetEPRxAddr(bEpNum));
+}
+
+/**
+ * @brief Set the Tx count.
+ * @param bEpNum: Endpoint Number.
+ * @param wCount: new count value.
+ * @retval None.
+ */
+void SetEPTxCount(uint8_t bEpNum, uint16_t wCount)
+{
+ _SetEPTxCount(bEpNum, wCount);
+}
+
+/**
+ * @brief Set the Count Rx Register value.
+ * @param *pdwReg: point to the register.
+ * @param wCount: the new register value.
+ * @retval None.
+ */
+void SetEPCountRxReg(uint32_t *pdwReg, uint16_t wCount)
+{
+ _SetEPCountRxReg(dwReg, wCount);
+}
+
+/**
+ * @brief Set the Rx count.
+ * @param bEpNum: Endpoint Number.
+ * @param wCount: the new count value.
+ * @retval None.
+ */
+void SetEPRxCount(uint8_t bEpNum, uint16_t wCount)
+{
+ _SetEPRxCount(bEpNum, wCount);
+}
+
+/**
+ * @brief Get the Tx count.
+ * @param bEpNum: Endpoint Number.
+ * @retval Tx count value.
+ */
+uint16_t GetEPTxCount(uint8_t bEpNum)
+{
+ return(_GetEPTxCount(bEpNum));
+}
+
+/**
+ * @brief Get the Rx count.
+ * @param bEpNum: Endpoint Number.
+ * @retval Rx count value.
+ */
+uint16_t GetEPRxCount(uint8_t bEpNum)
+{
+ return(_GetEPRxCount(bEpNum));
+}
+
+/**
+ * @brief Set the addresses of the buffer 0 and 1.
+ * @param bEpNum: Endpoint Number.
+ * @param wBuf0Addr: new address of buffer 0.
+ * @param wBuf1Addr: new address of buffer 1.
+ * @retval None.
+ */
+void SetEPDblBuffAddr(uint8_t bEpNum, uint16_t wBuf0Addr, uint16_t wBuf1Addr)
+{
+ _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr);
+}
+
+/**
+ * @brief Set the Buffer 0 address.
+ * @param bEpNum: Endpoint Number.
+ * @param wBuf0Addr: new address of buffer 0.
+ * @retval None.
+ */
+void SetEPDblBuf0Addr(uint8_t bEpNum, uint16_t wBuf0Addr)
+{
+ _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);
+}
+
+/**
+ * @brief Set the Buffer 1 address.
+ * @param bEpNum: Endpoint Number.
+ * @param wBuf1Addr: new address of buffer 1.
+ * @retval None.
+ */
+void SetEPDblBuf1Addr(uint8_t bEpNum, uint16_t wBuf1Addr)
+{
+ _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);
+}
+
+/**
+ * @brief Returns the address of the Buffer 0.
+ * @param bEpNum: Endpoint Number.
+ * @retval buffer 0 address.
+ */
+uint16_t GetEPDblBuf0Addr(uint8_t bEpNum)
+{
+ return(_GetEPDblBuf0Addr(bEpNum));
+}
+
+/**
+ * @brief Returns the address of the Buffer 1.
+ * @param bEpNum: Endpoint Number.
+ * @retval buffer 1 address.
+ */
+uint16_t GetEPDblBuf1Addr(uint8_t bEpNum)
+{
+ return(_GetEPDblBuf1Addr(bEpNum));
+}
+
+/**
+ * @brief Set the number of bytes for a double Buffer endpoint.
+ * @param bEpNum: Endpoint Number.
+ * @param bDin: Endpoint dir (IN/OUT).
+ * @param wCount: buffer count.
+ * @retval None.
+ */
+void SetEPDblBuffCount(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+ _SetEPDblBuffCount(bEpNum, bDir, wCount);
+}
+
+/**
+ * @brief Set the number of bytes for a double Buffer0 endpoint.
+ * @param bEpNum: Endpoint Number.
+ * @param bDin: Endpoint dir (IN/OUT).
+ * @param wCount: buffer count.
+ * @retval None.
+ */
+void SetEPDblBuf0Count(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+ _SetEPDblBuf0Count(bEpNum, bDir, wCount);
+}
+
+/**
+ * @brief Set the number of bytes for a double Buffer1 endpoint.
+ * @param bEpNum: Endpoint Number.
+ * @param bDin: Endpoint dir (IN/OUT).
+ * @param wCount: buffer count.
+ * @retval None.
+ */
+void SetEPDblBuf1Count(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
+{
+ _SetEPDblBuf1Count(bEpNum, bDir, wCount);
+}
+
+/**
+ * @brief Returns the number of byte received in the buffer 0
+ of a double Buffer endpoint.
+ * @param bEpNum: Endpoint Number.
+ * @retval Endpoint Buffer 0 count.
+ */
+uint16_t GetEPDblBuf0Count(uint8_t bEpNum)
+{
+ return(_GetEPDblBuf0Count(bEpNum));
+}
+
+/**
+ * @brief Returns the number of byte received in the buffer 1
+ of a double Buffer endpoint.
+ * @param bEpNum: Endpoint Number.
+ * @retval Endpoint Buffer 1 count.
+ */
+uint16_t GetEPDblBuf1Count(uint8_t bEpNum)
+{
+ return(_GetEPDblBuf1Count(bEpNum));
+}
+
+/**
+ * @brief gets direction of the double buffered endpoint.
+ * @param bEpNum: Endpoint Number.
+ * @retval EP_DBUF_OUT, EP_DBUF_IN,
+ * EP_DBUF_ERR if the endpoint counter not yet programmed.
+ */
+EP_DBUF_DIR GetEPDblBufDir(uint8_t bEpNum)
+{
+ if ((uint16_t)(*_pEPRxCount(bEpNum) & 0xFC00) != 0)
+ return(EP_DBUF_OUT);
+ else if (((uint16_t)(*_pEPTxCount(bEpNum)) & 0x03FF) != 0)
+ return(EP_DBUF_IN);
+ else
+ return(EP_DBUF_ERR);
+}
+
+/**
+ * @brief free buffer used from the application realizing it to the line
+ toggles bit SW_BUF in the double buffered endpoint register.
+ * @param bEpNum: Endpoint Number.
+ * @param bDir: Endpoint dir (IN/OUT).
+ * @retval None.
+ */
+void FreeUserBuffer(uint8_t bEpNum, uint8_t bDir)
+{
+ if (bDir == EP_DBUF_OUT)
+ { /* OUT double buffered endpoint */
+ _ToggleDTOG_TX(bEpNum);
+ }
+ else if (bDir == EP_DBUF_IN)
+ { /* IN double buffered endpoint */
+ _ToggleDTOG_RX(bEpNum);
+ }
+}
+
+/**
+ * @brief merge two byte in a word.
+ * @param bh: byte high.
+ * @param bl: bytes low.
+ * @retval resulted word..
+ */
+uint16_t ToWord(uint8_t bh, uint8_t bl)
+{
+ uint16_t wRet;
+ wRet = (uint16_t)bl | ((uint16_t)bh << 8);
+ return(wRet);
+}
+
+/**
+ * @brief Swap two byte in a word.
+ * @param wSwW: word to Swap.
+ * @retval resulted word..
+ */
+uint16_t ByteSwap(uint16_t wSwW)
+{
+ uint8_t bTemp;
+ uint16_t wRet;
+ bTemp = (uint8_t)(wSwW & 0xff);
+ wRet = (wSwW >> 8) | ((uint16_t)bTemp << 8);
+ return(wRet);
+}
+
+/**
+ * @brief Set USB SRAM size to 768 byte.
+ * @param None.
+ * @retval None..
+ */
+void Set_USB768ByteMode(void)
+{
+ /*Enable 768 Byte, Enable RCC->MISC*/
+ RCC->MISC |= 0x1 << 24;
+
+ /*USB SRAM Base address*/
+ PMAAddr = 0x40007800;
+}
+
+/**
+ * @brief Clear USB 768 byte mode, USB SRAM size is 512 byte.
+ * @param None.
+ * @retval None..
+ */
+void Clear_USB768ByteMode(void)
+{
+ /*Clear 768 byte mode*/
+ RCC->MISC &= ~(0x1 << 24);
+
+ /*USB SRAM Base address*/
+ PMAAddr = 0x40006000;
+}
diff --git a/.platformio/packages/framework-cmsis-at32f43/package.json b/.platformio/packages/framework-cmsis-at32f43/package.json
new file mode 100644
index 0000000..32ef3a8
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/package.json
@@ -0,0 +1,15 @@
+{
+ "name": "framework-cmsis-at32f43",
+ "version": "1.0.0",
+ "description": "CMSIS component for the Artery AT32F43x series",
+ "keywords": [
+ "framework",
+ "artery",
+ "at32"
+ ],
+ "license": "Apache-2.0",
+ "repository": {
+ "type": "git",
+ "url": "https://github.com/STMicroelectronics/cmsis_device_f1"
+ }
+}
\ No newline at end of file
diff --git a/.platformio/packages/framework-cmsis-at32f43/tools/.flake8 b/.platformio/packages/framework-cmsis-at32f43/tools/.flake8
new file mode 100644
index 0000000..9b7e20c
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/tools/.flake8
@@ -0,0 +1,2 @@
+[flake8]
+max-line-length = 95
diff --git a/.platformio/packages/framework-cmsis-at32f43/tools/platformio/platformio-build.py b/.platformio/packages/framework-cmsis-at32f43/tools/platformio/platformio-build.py
new file mode 100644
index 0000000..0b9a9e6
--- /dev/null
+++ b/.platformio/packages/framework-cmsis-at32f43/tools/platformio/platformio-build.py
@@ -0,0 +1,103 @@
+# Copyright 2014-present PlatformIO
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+No Comments
+"""
+
+import json
+from os.path import isfile, isdir, join
+
+from platformio.util import get_systype
+
+from SCons.Script import COMMAND_LINE_TARGETS, DefaultEnvironment
+
+env = DefaultEnvironment()
+platform = env.PioPlatform()
+board_config = env.BoardConfig()
+
+FRAMEWORK_DIR = platform.get_package_dir("framework-cmsis-at32f43")
+CMSIS_DIR = join(platform.get_package_dir("framework-cmsis"), "CMSIS")
+assert isdir(FRAMEWORK_DIR)
+assert isdir(CMSIS_DIR)
+
+
+mcu = board_config.get("build.mcu", "")
+mcu_type = mcu[:-2]
+series = mcu_type[:7].upper() + "xx"
+upload_protocol = env.subst("$UPLOAD_PROTOCOL")
+
+env.Append(
+ ASFLAGS=["-x", "assembler-with-cpp"],
+ CFLAGS=[
+ "-std=gnu11",
+ ],
+ CCFLAGS=[
+ "-O1", # optimize for speed Os
+ "-mcpu=%s" % board_config.get("build.cpu"),
+ "-mthumb",
+ "-ffunction-sections", # place each function in its own section
+ "-fdata-sections",
+ "-nostdlib",
+ "--param",
+ "max-inline-insns-single=500",
+ #"-print-multi-lib", #to check library versions
+ ],
+ CXXFLAGS=[
+ "-fno-rtti",
+ "-fno-exceptions",
+ ],
+ CPPPATH=[
+ ],
+ LIBS=[
+ "c",
+ "m",
+ "gcc",
+ "stdc++",
+ ],
+ LIBPATH=[join(CMSIS_DIR, "DSP", "Lib", "GCC")],
+)
+
+#Floating point unit: hard (hardware) | softfp (software)
+if (
+ any(cpu in board_config.get("build.cpu") for cpu in ("cortex-m4"))
+):
+ env.Append(
+ CFLAGS=["-mfpu=fpv4-sp-d16", "-mfloat-abi=hard"],
+ CCFLAGS=["-mfpu=fpv4-sp-d16", "-mfloat-abi=hard"],
+ LINKFLAGS=["-mcpu=%s" % board_config.get("build.cpu"), "-mfpu=fpv4-sp-d16", "-mfloat-abi=hard"],
+ )
+
+# copy CCFLAGS to ASFLAGS (-x assembler-with-cpp mode)
+env.Append(ASFLAGS=env.get("CCFLAGS", [])[:])
+
+#
+# Target: Build Core Library
+#
+
+libs = []
+
+libs.append(
+ env.BuildLibrary(
+ join("$BUILD_DIR", "AT32F43x_StdPeriph"), join(FRAMEWORK_DIR, "libraries", "AT32F43x_StdPeriph_Driver")
+ )
+)
+
+#libs.append(
+ #env.BuildLibrary(
+ #join("$BUILD_DIR", "AT32_USB-FS-Device"), join(FRAMEWORK_DIR, "libraries", "AT32_USB-FS-Device_Driver")
+ #)
+#)
+
+env.Prepend(LIBS=libs)
diff --git a/.platformio/packages/tool-ldscripts-at32/.piopm b/.platformio/packages/tool-ldscripts-at32/.piopm
index 8f4e095..e4cfeb7 100644
--- a/.platformio/packages/tool-ldscripts-at32/.piopm
+++ b/.platformio/packages/tool-ldscripts-at32/.piopm
@@ -1 +1 @@
-{"type": "tool", "name": "tool-ldscripts-at32", "version": "0.1.0", "spec": {"owner": "platformio", "id": 8167, "name": "tool-ldscripts-at32", "requirements": null, "url": null}}
\ No newline at end of file
+{"type": "tool", "name": "tool-ldscripts-at32", "version": "0.1.1", "spec": {"owner": "platformio", "id": 8167, "name": "tool-ldscripts-at32", "requirements": null, "url": null}}
\ No newline at end of file
diff --git a/.platformio/packages/tool-ldscripts-at32/at32f40/AT32F403AAG_DEFAULT.ld b/.platformio/packages/tool-ldscripts-at32/at32f40/AT32F403AAG_DEFAULT.ld
new file mode 100644
index 0000000..1fd0c47
--- /dev/null
+++ b/.platformio/packages/tool-ldscripts-at32/at32f40/AT32F403AAG_DEFAULT.ld
@@ -0,0 +1,175 @@
+/**
+ ******************************************************************************
+ * @file LinkerScript.ld
+ * @author Auto-generated by STM32CubeIDE
+ * @brief Linker script for STM32F030C6Tx Device from STM32F0 series
+ * 32Kbytes FLASH
+ * 4Kbytes RAM
+ *
+ * Set heap size, stack size and stack location according
+ * to application requirements.
+ *
+ * Set memory bank area and size if external memory is used
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 224K
+ FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
\ No newline at end of file
diff --git a/.platformio/packages/tool-ldscripts-at32/at32f40/AT32F403AxC_FLASH.ld b/.platformio/packages/tool-ldscripts-at32/at32f40/AT32F403AxC_FLASH.ld
index f409fe5..6c5f76d 100644
--- a/.platformio/packages/tool-ldscripts-at32/at32f40/AT32F403AxC_FLASH.ld
+++ b/.platformio/packages/tool-ldscripts-at32/at32f40/AT32F403AxC_FLASH.ld
@@ -32,7 +32,7 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
-RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 224K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
}
/* Define output sections */
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/linker/AT32F403AxC_FLASH.ld b/.platformio/packages/tool-ldscripts-at32/at32f43/AT32F435xC_FLASH.ld
similarity index 94%
rename from .platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/linker/AT32F403AxC_FLASH.ld
rename to .platformio/packages/tool-ldscripts-at32/at32f43/AT32F435xC_FLASH.ld
index f409fe5..d5c2b4b 100644
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/linker/AT32F403AxC_FLASH.ld
+++ b/.platformio/packages/tool-ldscripts-at32/at32f43/AT32F435xC_FLASH.ld
@@ -1,10 +1,10 @@
/*
*****************************************************************************
**
-** File : AT32F403AxC_FLASH.ld
+** File : AT32F435xC_FLASH.ld
**
-** Abstract : Linker script for AT32F403xC Device with
-** 256KByte FLASH, 96KByte RAM
+** Abstract : Linker script for AT32F435xC Device with
+** 256KByte FLASH, 384KByte RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
@@ -32,7 +32,7 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
-RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 224K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
}
/* Define output sections */
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/linker/AT32F403AxG_FLASH.ld b/.platformio/packages/tool-ldscripts-at32/at32f43/AT32F435xG_FLASH.ld
similarity index 94%
rename from .platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/linker/AT32F403AxG_FLASH.ld
rename to .platformio/packages/tool-ldscripts-at32/at32f43/AT32F435xG_FLASH.ld
index 9640684..1ecd8f0 100644
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/linker/AT32F403AxG_FLASH.ld
+++ b/.platformio/packages/tool-ldscripts-at32/at32f43/AT32F435xG_FLASH.ld
@@ -1,10 +1,10 @@
/*
*****************************************************************************
**
-** File : AT32F403AxG_FLASH.ld
+** File : AT32F435xG_FLASH.ld
**
-** Abstract : Linker script for AT32F403xG Device with
-** 1000KByte FLASH, 96KByte RAM
+** Abstract : Linker script for AT32F435xG Device with
+** 1000KByte FLASH, 384KByte RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
@@ -32,7 +32,7 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1000K
-RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 224K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
}
/* Define output sections */
diff --git a/.platformio/packages/tool-ldscripts-at32/at32f43/AT32F435xM_FLASH.ld b/.platformio/packages/tool-ldscripts-at32/at32f43/AT32F435xM_FLASH.ld
new file mode 100644
index 0000000..53bcdca
--- /dev/null
+++ b/.platformio/packages/tool-ldscripts-at32/at32f43/AT32F435xM_FLASH.ld
@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+** File : AT32F435xM_FLASH.ld
+**
+** Abstract : Linker script for AT32F435xM Device with
+** 4096KByte FLASH, 384KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : Artery Tek AT32
+**
+** Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF; /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 4032K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/linker/AT32F403AxE_FLASH.ld b/.platformio/packages/tool-ldscripts-at32/at32f43/AT32F437xC_FLASH.ld
similarity index 93%
rename from .platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/linker/AT32F403AxE_FLASH.ld
rename to .platformio/packages/tool-ldscripts-at32/at32f43/AT32F437xC_FLASH.ld
index c68b2bd..d9d0ecf 100644
--- a/.platformio/packages/framework-cmsis-at32f40/Source/Templates/gcc/linker/AT32F403AxE_FLASH.ld
+++ b/.platformio/packages/tool-ldscripts-at32/at32f43/AT32F437xC_FLASH.ld
@@ -1,10 +1,10 @@
/*
*****************************************************************************
**
-** File : AT32F403AxE_FLASH.ld
+** File : AT32F437xC_FLASH.ld
**
-** Abstract : Linker script for AT32F403AxE Device with
-** 512KByte FLASH, 96KByte RAM
+** Abstract : Linker script for AT32F437xC Device with
+** 256KByte FLASH, 384KByte RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
@@ -31,8 +31,8 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
-FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
-RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 224K
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
}
/* Define output sections */
diff --git a/.platformio/packages/tool-ldscripts-at32/at32f43/AT32F437xG_FLASH.ld b/.platformio/packages/tool-ldscripts-at32/at32f43/AT32F437xG_FLASH.ld
new file mode 100644
index 0000000..c0984f3
--- /dev/null
+++ b/.platformio/packages/tool-ldscripts-at32/at32f43/AT32F437xG_FLASH.ld
@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+** File : AT32F437xG_FLASH.ld
+**
+** Abstract : Linker script for AT32F437xG Device with
+** 1000KByte FLASH, 384KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : Artery Tek AT32
+**
+** Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF; /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1000K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/.platformio/packages/tool-ldscripts-at32/at32f43/AT32F437xM_FLASH.ld b/.platformio/packages/tool-ldscripts-at32/at32f43/AT32F437xM_FLASH.ld
new file mode 100644
index 0000000..850480c
--- /dev/null
+++ b/.platformio/packages/tool-ldscripts-at32/at32f43/AT32F437xM_FLASH.ld
@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+** File : AT32F437xM_FLASH.ld
+**
+** Abstract : Linker script for AT32F437xM Device with
+** 4096KByte FLASH, 384KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : Artery Tek AT32
+**
+** Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF; /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 4032K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/.platformio/packages/tool-ldscripts-at32/package.json b/.platformio/packages/tool-ldscripts-at32/package.json
index 6a90e83..e93ffc7 100644
--- a/.platformio/packages/tool-ldscripts-at32/package.json
+++ b/.platformio/packages/tool-ldscripts-at32/package.json
@@ -1,6 +1,6 @@
{
"name": "tool-ldscripts-at32",
- "version": "0.1.0",
+ "version": "0.1.1",
"description": "Linker scripts pack for Artery AT32 platform",
"keywords": [
"linker scripts",
diff --git a/.platformio/packages/tool-ldscripts-at32/piopm b/.platformio/packages/tool-ldscripts-at32/piopm
deleted file mode 100644
index 8f4e095..0000000
--- a/.platformio/packages/tool-ldscripts-at32/piopm
+++ /dev/null
@@ -1 +0,0 @@
-{"type": "tool", "name": "tool-ldscripts-at32", "version": "0.1.0", "spec": {"owner": "platformio", "id": 8167, "name": "tool-ldscripts-at32", "requirements": null, "url": null}}
\ No newline at end of file
diff --git a/.platformio/platforms/at32/boards/generic_f403a.json b/.platformio/platforms/at32/boards/generic_f403a.json
index 026c430..08c1123 100644
--- a/.platformio/platforms/at32/boards/generic_f403a.json
+++ b/.platformio/platforms/at32/boards/generic_f403a.json
@@ -10,7 +10,7 @@
"0xDF11"
]
],
- "mcu": "at32f403acgt7",
+ "mcu": "at32f403aAgx",
"product_line": "AT32F403ACGT7",
"variant": "AT32F4xx/F403A_F403A(T-U)"
},
@@ -18,7 +18,7 @@
"default_tools": [
"stlink"
],
- "jlink_device": "AT32F403ACG7",
+ "jlink_device": "AT32F403AxGx",
"openocd_extra_args": [
"-c",
"reset_config none"
diff --git a/.platformio/platforms/at32/boards/generic_f435.json b/.platformio/platforms/at32/boards/generic_f435.json
new file mode 100644
index 0000000..58eb2e2
--- /dev/null
+++ b/.platformio/platforms/at32/boards/generic_f435.json
@@ -0,0 +1,47 @@
+{
+ "build": {
+ "core": "at32",
+ "cpu": "cortex-m4",
+ "extra_flags": "-DAT32F435CGT7",
+ "f_cpu": "288000000L",
+ "hwids": [
+ [
+ "0x2E3C",
+ "0xDF11"
+ ]
+ ],
+ "mcu": "at32f435xg",
+ "product_line": "AT32F435_437",
+ "variant": "AT32F4xx/F435_F435(T-U)"
+ },
+ "debug": {
+ "default_tools": [
+ "stlink"
+ ],
+ "jlink_device": "AT32F435xGx",
+ "openocd_extra_args": [
+ "-c",
+ "reset_config none"
+ ],
+ "openocd_target": "stm32f4x",
+ "svd_path": "STM32F435xx.svd"
+ },
+ "frameworks": [
+ "cmsis"
+ ],
+ "name": "Generic_F435",
+ "upload": {
+ "maximum_ram_size": 524288,
+ "maximum_size": 262144,
+ "protocol": "serial",
+ "protocols": [
+ "jlink",
+ "cmsis-dap",
+ "stlink",
+ "serial",
+ "blackmagic"
+ ]
+ },
+ "url": "https://www.arterychip.com/en/product/AT32F435.jsp",
+ "vendor": "Artery"
+}
diff --git a/.platformio/platforms/at32/builder/frameworks/cmsis.py b/.platformio/platforms/at32/builder/frameworks/cmsis.py
index 5c22397..200a151 100644
--- a/.platformio/platforms/at32/builder/frameworks/cmsis.py
+++ b/.platformio/platforms/at32/builder/frameworks/cmsis.py
@@ -81,6 +81,7 @@ def generate_ldscript(default_ldscript_path):
def get_linker_script():
ldscript_match = glob.glob(os.path.join(
LDSCRIPTS_DIR, mcu[0:7], mcu[0:11].upper() + "*_FLASH.ld"))
+ #print(os.path.join(LDSCRIPTS_DIR, mcu[0:7], mcu[0:11].upper() + "*_FLASH.ld"))
if ldscript_match and os.path.isfile(ldscript_match[0]):
return ldscript_match[0]
@@ -99,6 +100,7 @@ def get_linker_script():
def prepare_startup_file(src_path):
startup_file = os.path.join(src_path, "gcc", "startup_%s.S" % product_line.lower())
+ print("Startup file: " + startup_file)
# Change file extension to uppercase:
if not os.path.isfile(startup_file) and os.path.isfile(startup_file[:-2] + ".s"):
os.rename(startup_file[:-2] + ".s", startup_file)
@@ -137,7 +139,7 @@ env.Append(
#
# Compile CMSIS sources
#
-sources_path = os.path.join(CMSIS_DEVICE_DIR, "Source", "Templates")
+sources_path = os.path.join(CMSIS_DEVICE_DIR, "Startup")
prepare_startup_file(sources_path)
env.BuildSources(
diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/gitignore b/.platformio/platforms/at32/examples/F435-cmsis-blink/.gitignore
similarity index 100%
rename from .platformio/platforms/at32/examples/cmsis-acd1_dma/gitignore
rename to .platformio/platforms/at32/examples/F435-cmsis-blink/.gitignore
diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/travis.yml b/.platformio/platforms/at32/examples/F435-cmsis-blink/.travis.yml
similarity index 100%
rename from .platformio/platforms/at32/examples/cmsis-acd1_dma/travis.yml
rename to .platformio/platforms/at32/examples/F435-cmsis-blink/.travis.yml
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/.vscode/c_cpp_properties.json b/.platformio/platforms/at32/examples/F435-cmsis-blink/.vscode/c_cpp_properties.json
new file mode 100644
index 0000000..c8df498
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/.vscode/c_cpp_properties.json
@@ -0,0 +1,48 @@
+//
+// !!! WARNING !!! AUTO-GENERATED FILE!
+// PLEASE DO NOT MODIFY IT AND USE "platformio.ini":
+// https://docs.platformio.org/page/projectconf/section_env_build.html#build-flags
+//
+{
+ "configurations": [
+ {
+ "name": "PlatformIO",
+ "includePath": [
+ "c:/Users/Xliloz/.platformio/platforms/at32/examples/F435-cmsis-blink/include",
+ "c:/Users/Xliloz/.platformio/platforms/at32/examples/F435-cmsis-blink/src",
+ "c:/Users/Xliloz/.platformio/platforms/at32/examples/F435-cmsis-blink/lib/Delay",
+ "C:/Users/Xliloz/.platformio/packages/framework-cmsis@2.50501.200527/CMSIS/Include",
+ "C:/Users/Xliloz/.platformio/packages/framework-cmsis-at32f43/Include",
+ ""
+ ],
+ "browse": {
+ "limitSymbolsToIncludedHeaders": true,
+ "path": [
+ "c:/Users/Xliloz/.platformio/platforms/at32/examples/F435-cmsis-blink/include",
+ "c:/Users/Xliloz/.platformio/platforms/at32/examples/F435-cmsis-blink/src",
+ "c:/Users/Xliloz/.platformio/platforms/at32/examples/F435-cmsis-blink/lib/Delay",
+ "C:/Users/Xliloz/.platformio/packages/framework-cmsis@2.50501.200527/CMSIS/Include",
+ "C:/Users/Xliloz/.platformio/packages/framework-cmsis-at32f43/Include",
+ ""
+ ]
+ },
+ "defines": [
+ "PLATFORMIO=50205",
+ "AT32F435CGT7",
+ ""
+ ],
+ "cStandard": "c11",
+ "compilerPath": "C:/Users/Xliloz/.platformio/packages/toolchain-gccarmnoneeabi@1.70201.0/bin/arm-none-eabi-gcc.exe",
+ "compilerArgs": [
+ "-mfpu=fpv4-sp-d16",
+ "-mfloat-abi=hard",
+ "-mcpu=cortex-m4",
+ "-mthumb",
+ "-mfpu=fpv4-sp-d16",
+ "-mfloat-abi=hard",
+ ""
+ ]
+ }
+ ],
+ "version": 4
+}
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/.vscode/extensions.json b/.platformio/platforms/at32/examples/F435-cmsis-blink/.vscode/extensions.json
new file mode 100644
index 0000000..080e70d
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/.vscode/extensions.json
@@ -0,0 +1,10 @@
+{
+ // See http://go.microsoft.com/fwlink/?LinkId=827846
+ // for the documentation about the extensions.json format
+ "recommendations": [
+ "platformio.platformio-ide"
+ ],
+ "unwantedRecommendations": [
+ "ms-vscode.cpptools-extension-pack"
+ ]
+}
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/.vscode/launch.json b/.platformio/platforms/at32/examples/F435-cmsis-blink/.vscode/launch.json
new file mode 100644
index 0000000..eb4ff76
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/.vscode/launch.json
@@ -0,0 +1,44 @@
+// AUTOMATICALLY GENERATED FILE. PLEASE DO NOT MODIFY IT MANUALLY
+//
+// PIO Unified Debugger
+//
+// Documentation: https://docs.platformio.org/page/plus/debugging.html
+// Configuration: https://docs.platformio.org/page/projectconf/section_env_debug.html
+
+{
+ "version": "0.2.0",
+ "configurations": [
+ {
+ "type": "platformio-debug",
+ "request": "launch",
+ "name": "PIO Debug",
+ "executable": "c:/Users/Xliloz/.platformio/platforms/at32/examples/F435-cmsis-blink/.pio/build/generic_f435/firmware.elf",
+ "projectEnvName": "generic_f435",
+ "toolchainBinDir": "C:/Users/Xliloz/.platformio/packages/toolchain-gccarmnoneeabi@1.70201.0/bin",
+ "internalConsoleOptions": "openOnSessionStart",
+ "preLaunchTask": {
+ "type": "PlatformIO",
+ "task": "Pre-Debug"
+ }
+ },
+ {
+ "type": "platformio-debug",
+ "request": "launch",
+ "name": "PIO Debug (skip Pre-Debug)",
+ "executable": "c:/Users/Xliloz/.platformio/platforms/at32/examples/F435-cmsis-blink/.pio/build/generic_f435/firmware.elf",
+ "projectEnvName": "generic_f435",
+ "toolchainBinDir": "C:/Users/Xliloz/.platformio/packages/toolchain-gccarmnoneeabi@1.70201.0/bin",
+ "internalConsoleOptions": "openOnSessionStart"
+ },
+ {
+ "type": "platformio-debug",
+ "request": "launch",
+ "name": "PIO Debug (without uploading)",
+ "executable": "c:/Users/Xliloz/.platformio/platforms/at32/examples/F435-cmsis-blink/.pio/build/generic_f435/firmware.elf",
+ "projectEnvName": "generic_f435",
+ "toolchainBinDir": "C:/Users/Xliloz/.platformio/packages/toolchain-gccarmnoneeabi@1.70201.0/bin",
+ "internalConsoleOptions": "openOnSessionStart",
+ "loadMode": "manual"
+ }
+ ]
+}
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/.vscode/settings.json b/.platformio/platforms/at32/examples/F435-cmsis-blink/.vscode/settings.json
new file mode 100644
index 0000000..9ae3c94
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/.vscode/settings.json
@@ -0,0 +1,5 @@
+{
+ "files.associations": {
+ "at32f4xx.h": "c"
+ }
+}
\ No newline at end of file
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/README.rst b/.platformio/platforms/at32/examples/F435-cmsis-blink/README.rst
new file mode 100644
index 0000000..1890ad5
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/README.rst
@@ -0,0 +1,38 @@
+.. Copyright 2014-present PlatformIO
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+ http://www.apache.org/licenses/LICENSE-2.0
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+How to build PlatformIO based project
+=====================================
+
+1. `Install PlatformIO Core `_
+2. Download `development platform with examples `_
+3. Extract ZIP archive
+4. Run these commands:
+
+.. code-block:: bash
+
+ # Change directory to example
+ > cd platform-at32/examples/cmsis-blink
+
+ # Build project
+ > platformio run
+
+ # Upload firmware
+ > platformio run --target upload
+
+ # Build specific environment
+ > platformio run -e disco_f407vg
+
+ # Upload firmware for the specific environment
+ > platformio run -e disco_f407vg --target upload
+
+ # Clean build files
+ > platformio run --target clean
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/include/README b/.platformio/platforms/at32/examples/F435-cmsis-blink/include/README
new file mode 100644
index 0000000..194dcd4
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/include/README
@@ -0,0 +1,39 @@
+
+This directory is intended for project header files.
+
+A header file is a file containing C declarations and macro definitions
+to be shared between several project source files. You request the use of a
+header file in your project source file (C, C++, etc) located in `src` folder
+by including it, with the C preprocessing directive `#include'.
+
+```src/main.c
+
+#include "header.h"
+
+int main (void)
+{
+ ...
+}
+```
+
+Including a header file produces the same results as copying the header file
+into each source file that needs it. Such copying would be time-consuming
+and error-prone. With a header file, the related declarations appear
+in only one place. If they need to be changed, they can be changed in one
+place, and programs that include the header file will automatically use the
+new version when next recompiled. The header file eliminates the labor of
+finding and changing all the copies as well as the risk that a failure to
+find one copy will result in inconsistencies within a program.
+
+In C, the usual convention is to give header files names that end with `.h'.
+It is most portable to use only letters, digits, dashes, and underscores in
+header file names, and at most one dot.
+
+Read more about using header files in official GCC documentation:
+
+* Include Syntax
+* Include Operation
+* Once-Only Headers
+* Computed Includes
+
+https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/include/at32f435_437_clock.h b/.platformio/platforms/at32/examples/F435-cmsis-blink/include/at32f435_437_clock.h
new file mode 100644
index 0000000..39da81e
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/include/at32f435_437_clock.h
@@ -0,0 +1,46 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_clock.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief header file of clock program
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_CLOCK_H
+#define __AT32F435_437_CLOCK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/* exported functions ------------------------------------------------------- */
+void system_clock_config(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/include/at32f435_437_conf.h b/.platformio/platforms/at32/examples/F435-cmsis-blink/include/at32f435_437_conf.h
new file mode 100644
index 0000000..4567d0d
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/include/at32f435_437_conf.h
@@ -0,0 +1,174 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_conf.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief at32f435_437 config header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_CONF_H
+#define __AT32F435_437_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief in the following line adjust the value of high speed exernal crystal (hext)
+ * used in your application
+ *
+ * tip: to avoid modifying this file each time you need to use different hext, you
+ * can define the hext value in your toolchain compiler preprocessor.
+ *
+ */
+#if !defined HEXT_VALUE
+#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed exernal crystal in hz */
+#endif
+
+/**
+ * @brief in the following line adjust the high speed exernal crystal (hext) startup
+ * timeout value
+ */
+#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
+#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
+
+/* module define -------------------------------------------------------------*/
+#define CRM_MODULE_ENABLED
+#define TMR_MODULE_ENABLED
+#define ERTC_MODULE_ENABLED
+#define GPIO_MODULE_ENABLED
+#define I2C_MODULE_ENABLED
+#define USART_MODULE_ENABLED
+#define PWC_MODULE_ENABLED
+#define CAN_MODULE_ENABLED
+#define ADC_MODULE_ENABLED
+#define DAC_MODULE_ENABLED
+#define SPI_MODULE_ENABLED
+#define EDMA_MODULE_ENABLED
+#define DMA_MODULE_ENABLED
+#define DEBUG_MODULE_ENABLED
+#define FLASH_MODULE_ENABLED
+#define CRC_MODULE_ENABLED
+#define WWDT_MODULE_ENABLED
+#define WDT_MODULE_ENABLED
+#define EXINT_MODULE_ENABLED
+#define SDIO_MODULE_ENABLED
+#define XMC_MODULE_ENABLED
+#define USB_MODULE_ENABLED
+#define ACC_MODULE_ENABLED
+#define MISC_MODULE_ENABLED
+#define QSPI_MODULE_ENABLED
+#define DVP_MODULE_ENABLED
+#define SCFG_MODULE_ENABLED
+#define EMAC_MODULE_ENABLED
+
+/* includes ------------------------------------------------------------------*/
+#ifdef CRM_MODULE_ENABLED
+#include "at32f435_437_crm.h"
+#endif
+#ifdef TMR_MODULE_ENABLED
+#include "at32f435_437_tmr.h"
+#endif
+#ifdef ERTC_MODULE_ENABLED
+#include "at32f435_437_ertc.h"
+#endif
+#ifdef GPIO_MODULE_ENABLED
+#include "at32f435_437_gpio.h"
+#endif
+#ifdef I2C_MODULE_ENABLED
+#include "at32f435_437_i2c.h"
+#endif
+#ifdef USART_MODULE_ENABLED
+#include "at32f435_437_usart.h"
+#endif
+#ifdef PWC_MODULE_ENABLED
+#include "at32f435_437_pwc.h"
+#endif
+#ifdef CAN_MODULE_ENABLED
+#include "at32f435_437_can.h"
+#endif
+#ifdef ADC_MODULE_ENABLED
+#include "at32f435_437_adc.h"
+#endif
+#ifdef DAC_MODULE_ENABLED
+#include "at32f435_437_dac.h"
+#endif
+#ifdef SPI_MODULE_ENABLED
+#include "at32f435_437_spi.h"
+#endif
+#ifdef DMA_MODULE_ENABLED
+#include "at32f435_437_dma.h"
+#endif
+#ifdef DEBUG_MODULE_ENABLED
+#include "at32f435_437_debug.h"
+#endif
+#ifdef FLASH_MODULE_ENABLED
+#include "at32f435_437_flash.h"
+#endif
+#ifdef CRC_MODULE_ENABLED
+#include "at32f435_437_crc.h"
+#endif
+#ifdef WWDT_MODULE_ENABLED
+#include "at32f435_437_wwdt.h"
+#endif
+#ifdef WDT_MODULE_ENABLED
+#include "at32f435_437_wdt.h"
+#endif
+#ifdef EXINT_MODULE_ENABLED
+#include "at32f435_437_exint.h"
+#endif
+#ifdef SDIO_MODULE_ENABLED
+#include "at32f435_437_sdio.h"
+#endif
+#ifdef XMC_MODULE_ENABLED
+#include "at32f435_437_xmc.h"
+#endif
+#ifdef ACC_MODULE_ENABLED
+#include "at32f435_437_acc.h"
+#endif
+#ifdef MISC_MODULE_ENABLED
+#include "at32f435_437_misc.h"
+#endif
+#ifdef EDMA_MODULE_ENABLED
+#include "at32f435_437_edma.h"
+#endif
+#ifdef QSPI_MODULE_ENABLED
+#include "at32f435_437_qspi.h"
+#endif
+#ifdef SCFG_MODULE_ENABLED
+#include "at32f435_437_scfg.h"
+#endif
+#ifdef EMAC_MODULE_ENABLED
+#include "at32f435_437_emac.h"
+#endif
+#ifdef DVP_MODULE_ENABLED
+#include "at32f435_437_dvp.h"
+#endif
+#ifdef USB_MODULE_ENABLED
+#include "at32f435_437_usb.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/include/at32f435_437_int.h b/.platformio/platforms/at32/examples/F435-cmsis-blink/include/at32f435_437_int.h
new file mode 100644
index 0000000..6671148
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/include/at32f435_437_int.h
@@ -0,0 +1,58 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_int.h
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief header file of main interrupt service routines.
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F435_437_INT_H
+#define __AT32F435_437_INT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437.h"
+
+/* exported types ------------------------------------------------------------*/
+/* exported constants --------------------------------------------------------*/
+/* exported macro ------------------------------------------------------------*/
+/* exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/lib/Delay/delay.c b/.platformio/platforms/at32/examples/F435-cmsis-blink/lib/Delay/delay.c
new file mode 100644
index 0000000..ef3f19c
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/lib/Delay/delay.c
@@ -0,0 +1,95 @@
+/*DO NOT USE - DON'T WORK*/
+
+#include "delay.h"
+#include "stdio.h"
+
+
+/*delay macros*/
+#define STEP_DELAY_MS 500
+
+/*delay variable*/
+static __IO float fac_us;
+static __IO float fac_ms;
+
+
+/**
+ * @brief initialize Delay function
+ * @param None
+ * @retval None
+ */
+void delay_init()
+{
+ /* configure systick */
+ systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8);
+ fac_us = system_core_clock / (1000000U);
+ fac_ms = fac_us * (1000U);
+}
+
+/**
+ * @brief inserts a delay time.
+ * @param nus: specifies the delay time length, in microsecond.
+ * @retval none
+ */
+void delay_us(uint32_t nus)
+{
+ uint32_t temp = 0;
+ SysTick->LOAD = (uint32_t)(nus * fac_us);
+ SysTick->VAL = 0x00;
+ SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk ;
+ do
+ {
+ temp = SysTick->CTRL;
+ }while((temp & 0x01) && !(temp & (1 << 16)));
+
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+ SysTick->VAL = 0x00;
+}
+
+/**
+ * @brief inserts a delay time.
+ * @param nms: specifies the delay time length, in milliseconds.
+ * @retval none
+ */
+void delay_ms(uint16_t nms)
+{
+ uint32_t temp = 0;
+ while(nms)
+ {
+ if(nms > STEP_DELAY_MS)
+ {
+ SysTick->LOAD = (uint32_t)(STEP_DELAY_MS * fac_ms);
+ nms -= STEP_DELAY_MS;
+ }
+ else
+ {
+ SysTick->LOAD = (uint32_t)(nms * fac_ms);
+ nms = 0;
+ }
+ SysTick->VAL = 0x00;
+ SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+ do
+ {
+ temp = SysTick->CTRL;
+ }while((temp & 0x01) && !(temp & (1 << 16)));
+
+ SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+ SysTick->VAL = 0x00;
+ }
+}
+
+/**
+ * @brief inserts a delay time.
+ * @param sec: specifies the delay time, in seconds.
+ * @retval none
+ */
+void delay_sec(uint16_t sec)
+{
+ uint16_t index;
+ for(index = 0; index < sec; index++)
+ {
+ delay_ms(500);
+ delay_ms(500);
+ }
+}
+
+
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/lib/Delay/delay.h b/.platformio/platforms/at32/examples/F435-cmsis-blink/lib/Delay/delay.h
new file mode 100644
index 0000000..9288794
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/lib/Delay/delay.h
@@ -0,0 +1,16 @@
+/**
+ **************************************************************************
+ * File : delay.h
+ */
+
+#ifndef __DELAY_H
+#define __DELAY_H
+#include "at32f435_437.h"
+
+/*Delay function*/
+void delay_init(void);
+void delay_us(u32 nus);
+void delay_ms(u16 nms);
+void delay_sec(u16 sec);
+
+#endif
\ No newline at end of file
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/lib/README b/.platformio/platforms/at32/examples/F435-cmsis-blink/lib/README
new file mode 100644
index 0000000..6debab1
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/lib/README
@@ -0,0 +1,46 @@
+
+This directory is intended for project specific (private) libraries.
+PlatformIO will compile them to static libraries and link into executable file.
+
+The source code of each library should be placed in a an own separate directory
+("lib/your_library_name/[here are source files]").
+
+For example, see a structure of the following two libraries `Foo` and `Bar`:
+
+|--lib
+| |
+| |--Bar
+| | |--docs
+| | |--examples
+| | |--src
+| | |- Bar.c
+| | |- Bar.h
+| | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html
+| |
+| |--Foo
+| | |- Foo.c
+| | |- Foo.h
+| |
+| |- README --> THIS FILE
+|
+|- platformio.ini
+|--src
+ |- main.c
+
+and a contents of `src/main.c`:
+```
+#include
+#include
+
+int main (void)
+{
+ ...
+}
+
+```
+
+PlatformIO Library Dependency Finder will find automatically dependent
+libraries scanning project source files.
+
+More information about PlatformIO Library Dependency Finder
+- https://docs.platformio.org/page/librarymanager/ldf.html
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/platformio.ini b/.platformio/platforms/at32/examples/F435-cmsis-blink/platformio.ini
new file mode 100644
index 0000000..50c145f
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/platformio.ini
@@ -0,0 +1,35 @@
+; PlatformIO Project Configuration File
+;
+; Build options: build flags, source filter, extra scripting
+; Upload options: custom port, speed and extra flags
+; Library options: dependencies, extra library storages
+;
+; Please visit documentation for the other options and examples
+; http://docs.platformio.org/page/projectconf.html
+
+[env:generic_f435]
+platform = at32
+framework = cmsis
+board = generic_f435
+monitor_speed = 115200 ;serial monitor baudrate
+
+;Use the following for jlink upload
+upload_protocol = jlink
+
+;Use the following for serial upload via bootloader (PA9, PA10)
+;upload_protocol = serial
+;upload_speed = 115200 ;default: 115200
+
+;Use the following for DFU upload via USB port
+;upload_protocol = dfu
+;build_flags =
+; -DDFU_MODE
+; -UVECT_TAB_OFFSET
+; -DUSER_VECT_TAB_ADDRESS
+; -DVECT_TAB_OFFSET=0x2000 ; override default vector tale to support ISR table for DFU mode
+
+;Use the following for custom uploader
+;upload_protocol = custom
+;upload_port = COM16
+;upload_speed = 115200
+;upload_command = ${platformio.packages_dir}/framework-cmsis-at32f40/tools/stm32flash/stm32flash -b $UPLOAD_SPEED -w $SOURCE -g 0x8000000 $UPLOAD_PORT
\ No newline at end of file
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/src/at32f435_437_clock.c b/.platformio/platforms/at32/examples/F435-cmsis-blink/src/at32f435_437_clock.c
new file mode 100644
index 0000000..2c29ee4
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/src/at32f435_437_clock.c
@@ -0,0 +1,109 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_clock.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief system clock config program
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437_clock.h"
+
+/**
+ * @brief system clock config program
+ * @note the system clock is configured as follow:
+ * - system clock = (hext * pll_ns)/(pll_ms * pll_fr)
+ * - system clock source = pll (hext)
+ * - hext = 8000000
+ * - sclk = 288000000
+ * - ahbdiv = 1
+ * - ahbclk = 288000000
+ * - apb2div = 2
+ * - apb2clk = 144000000
+ * - apb1div = 2
+ * - apb1clk = 144000000
+ * - pll_ns = 72
+ * - pll_ms = 1
+ * - pll_fr = 2
+ * @param none
+ * @retval none
+ */
+void system_clock_config(void)
+{
+ /* enable pwc periph clock */
+ crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
+
+ /* config ldo voltage */
+ pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3);
+
+ /* set the flash clock divider */
+ flash_clock_divider_set(FLASH_CLOCK_DIV_3);
+
+ /* reset crm */
+ crm_reset();
+
+ //crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
+ crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE);
+
+ /* wait till hext is ready */
+ //while(crm_hext_stable_wait() == ERROR)
+ while(crm_flag_get(CRM_HICK_STABLE_FLAG) != SET)
+ {
+ }
+
+ /* config pll clock resource */
+ //crm_pll_config(CRM_PLL_SOURCE_HEXT, 72, 1, CRM_PLL_FR_2);
+ crm_pll_config(CRM_PLL_SOURCE_HICK, 72, 1, CRM_PLL_FR_2);
+
+ /* enable pll */
+ crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
+
+ /* wait till pll is ready */
+ while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
+ {
+ }
+
+ /* config ahbclk */
+ crm_ahb_div_set(CRM_AHB_DIV_1);
+
+ /* config apb2clk */
+ crm_apb2_div_set(CRM_APB2_DIV_2);
+
+ /* config apb1clk */
+ crm_apb1_div_set(CRM_APB1_DIV_2);
+
+ /* enable auto step mode */
+ crm_auto_step_mode_enable(TRUE);
+
+ /* select pll as system clock source */
+ crm_sysclk_switch(CRM_SCLK_PLL);
+
+ /* wait till pll is used as system clock source */
+ while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
+ {
+ }
+
+ /* disable auto step mode */
+ crm_auto_step_mode_enable(FALSE);
+
+ /* update system_core_clock global variable */
+ system_core_clock_update();
+}
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/src/at32f435_437_int.c b/.platformio/platforms/at32/examples/F435-cmsis-blink/src/at32f435_437_int.c
new file mode 100644
index 0000000..22db16a
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/src/at32f435_437_int.c
@@ -0,0 +1,141 @@
+/**
+ **************************************************************************
+ * @file at32f435_437_int.c
+ * @version v2.0.4
+ * @date 2021-12-31
+ * @brief main interrupt service routines.
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f435_437_int.h"
+
+/** @addtogroup AT32F435_periph_examples
+ * @{
+ */
+
+/** @addtogroup 435_GPIO_led_toggle
+ * @{
+ */
+
+/**
+ * @brief this function handles nmi exception.
+ * @param none
+ * @retval none
+ */
+void NMI_Handler(void)
+{
+}
+
+/**
+ * @brief this function handles hard fault exception.
+ * @param none
+ * @retval none
+ */
+void HardFault_Handler(void)
+{
+ /* go to infinite loop when hard fault exception occurs */
+ while(1)
+ {
+ }
+}
+
+/**
+ * @brief this function handles memory manage exception.
+ * @param none
+ * @retval none
+ */
+void MemManage_Handler(void)
+{
+ /* go to infinite loop when memory manage exception occurs */
+ while(1)
+ {
+ }
+}
+
+/**
+ * @brief this function handles bus fault exception.
+ * @param none
+ * @retval none
+ */
+void BusFault_Handler(void)
+{
+ /* go to infinite loop when bus fault exception occurs */
+ while(1)
+ {
+ }
+}
+
+/**
+ * @brief this function handles usage fault exception.
+ * @param none
+ * @retval none
+ */
+void UsageFault_Handler(void)
+{
+ /* go to infinite loop when usage fault exception occurs */
+ while(1)
+ {
+ }
+}
+
+/**
+ * @brief this function handles svcall exception.
+ * @param none
+ * @retval none
+ */
+void SVC_Handler(void)
+{
+}
+
+/**
+ * @brief this function handles debug monitor exception.
+ * @param none
+ * @retval none
+ */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+ * @brief this function handles pendsv_handler exception.
+ * @param none
+ * @retval none
+ */
+void PendSV_Handler(void)
+{
+}
+
+/**
+ * @brief this function handles systick handler.
+ * @param none
+ * @retval none
+ */
+void SysTick_Handler(void)
+{
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/src/main.c b/.platformio/platforms/at32/examples/F435-cmsis-blink/src/main.c
new file mode 100644
index 0000000..d1494c5
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/src/main.c
@@ -0,0 +1,47 @@
+/** Light on/off pin PB12, 1Hz frequency */
+#include "at32f435_437_clock.h"
+#include "delay.h"
+
+#define LEDPERIPH CRM_GPIOB_PERIPH_CLOCK
+#define LEDPORT (GPIOB)
+#define LEDPIN (GPIO_PINS_12)
+
+
+/**
+ * @brief gpio configuration.
+ * @param none
+ * @retval none
+ */
+static void gpio_config(void)
+{
+ gpio_init_type gpio_init_struct;
+ crm_periph_clock_enable(LEDPERIPH, TRUE);
+
+ gpio_default_para_init(&gpio_init_struct);
+
+ //configure the led gpio
+ gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
+ gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
+ gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
+ gpio_init_struct.gpio_pins = LEDPIN;
+ gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
+ gpio_init(LEDPORT, &gpio_init_struct);
+}
+
+//Flash LEDs quickly
+int main(void)
+{
+ system_clock_config();
+ delay_init();
+
+ gpio_config();
+
+ gpio_bits_reset(LEDPORT, LEDPIN);
+
+ for (;;) {
+ delay_ms(500);
+ LEDPORT->odt ^= LEDPIN; // toggle pin
+ }
+
+ return 0;
+}
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/src/main.h b/.platformio/platforms/at32/examples/F435-cmsis-blink/src/main.h
new file mode 100644
index 0000000..bf5a107
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/src/main.h
@@ -0,0 +1,8 @@
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+
+#endif /* __MAIN_H */
+
+
diff --git a/.platformio/platforms/at32/examples/F435-cmsis-blink/test/README b/.platformio/platforms/at32/examples/F435-cmsis-blink/test/README
new file mode 100644
index 0000000..df5066e
--- /dev/null
+++ b/.platformio/platforms/at32/examples/F435-cmsis-blink/test/README
@@ -0,0 +1,11 @@
+
+This directory is intended for PIO Unit Testing and project tests.
+
+Unit Testing is a software testing method by which individual units of
+source code, sets of one or more MCU program modules together with associated
+control data, usage procedures, and operating procedures, are tested to
+determine whether they are fit for use. Unit testing finds problems early
+in the development cycle.
+
+More information about PIO Unit Testing:
+- https://docs.platformio.org/page/plus/unit-testing.html
diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/.gitignore b/.platformio/platforms/at32/examples/cmsis-acd1_dma/.gitignore
index 661538a..03f4a3c 100644
--- a/.platformio/platforms/at32/examples/cmsis-acd1_dma/.gitignore
+++ b/.platformio/platforms/at32/examples/cmsis-acd1_dma/.gitignore
@@ -1,3 +1 @@
.pio
-.vscode
-build
diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/.vscode/c_cpp_properties.json b/.platformio/platforms/at32/examples/cmsis-acd1_dma/.vscode/c_cpp_properties.json
new file mode 100644
index 0000000..cea2fd0
--- /dev/null
+++ b/.platformio/platforms/at32/examples/cmsis-acd1_dma/.vscode/c_cpp_properties.json
@@ -0,0 +1,46 @@
+//
+// !!! WARNING !!! AUTO-GENERATED FILE!
+// PLEASE DO NOT MODIFY IT AND USE "platformio.ini":
+// https://docs.platformio.org/page/projectconf/section_env_build.html#build-flags
+//
+{
+ "configurations": [
+ {
+ "name": "PlatformIO",
+ "includePath": [
+ "C:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-acd1_dma/include",
+ "C:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-acd1_dma/src",
+ "C:/Users/Xliloz/.platformio/packages/framework-cmsis@2.50501.200527/CMSIS/Include",
+ "C:/Users/Xliloz/.platformio/packages/framework-cmsis-at32f40/Include",
+ "C:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-acd1_dma/lib/Delay",
+ ""
+ ],
+ "browse": {
+ "limitSymbolsToIncludedHeaders": true,
+ "path": [
+ "C:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-acd1_dma/include",
+ "C:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-acd1_dma/src",
+ "C:/Users/Xliloz/.platformio/packages/framework-cmsis@2.50501.200527/CMSIS/Include",
+ "C:/Users/Xliloz/.platformio/packages/framework-cmsis-at32f40/Include",
+ "C:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-acd1_dma/lib/Delay",
+ ""
+ ]
+ },
+ "defines": [
+ "PLATFORMIO=50200",
+ "AT32F403ACGT7",
+ ""
+ ],
+ "cStandard": "c11",
+ "compilerPath": "C:/Users/Xliloz/.platformio/packages/toolchain-gccarmnoneeabi@1.70201.0/bin/arm-none-eabi-gcc.exe",
+ "compilerArgs": [
+ "-mcpu=cortex-m4",
+ "-mthumb",
+ "-mcpu=cortex-m4",
+ "-mthumb",
+ ""
+ ]
+ }
+ ],
+ "version": 4
+}
diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/.vscode/extensions.json b/.platformio/platforms/at32/examples/cmsis-acd1_dma/.vscode/extensions.json
new file mode 100644
index 0000000..e80666b
--- /dev/null
+++ b/.platformio/platforms/at32/examples/cmsis-acd1_dma/.vscode/extensions.json
@@ -0,0 +1,7 @@
+{
+ // See http://go.microsoft.com/fwlink/?LinkId=827846
+ // for the documentation about the extensions.json format
+ "recommendations": [
+ "platformio.platformio-ide"
+ ]
+}
diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/.vscode/launch.json b/.platformio/platforms/at32/examples/cmsis-acd1_dma/.vscode/launch.json
new file mode 100644
index 0000000..550195f
--- /dev/null
+++ b/.platformio/platforms/at32/examples/cmsis-acd1_dma/.vscode/launch.json
@@ -0,0 +1,34 @@
+// AUTOMATICALLY GENERATED FILE. PLEASE DO NOT MODIFY IT MANUALLY
+//
+// PIO Unified Debugger
+//
+// Documentation: https://docs.platformio.org/page/plus/debugging.html
+// Configuration: https://docs.platformio.org/page/projectconf/section_env_debug.html
+
+{
+ "version": "0.2.0",
+ "configurations": [
+ {
+ "type": "platformio-debug",
+ "request": "launch",
+ "name": "PIO Debug",
+ "executable": "C:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-acd1_dma/.pio/build/generic f403a/firmware.elf",
+ "projectEnvName": "generic f403a",
+ "toolchainBinDir": "C:/Users/Xliloz/.platformio/packages/toolchain-gccarmnoneeabi@1.70201.0/bin",
+ "internalConsoleOptions": "openOnSessionStart",
+ "preLaunchTask": {
+ "type": "PlatformIO",
+ "task": "Pre-Debug"
+ }
+ },
+ {
+ "type": "platformio-debug",
+ "request": "launch",
+ "name": "PIO Debug (skip Pre-Debug)",
+ "executable": "C:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-acd1_dma/.pio/build/generic f403a/firmware.elf",
+ "projectEnvName": "generic f403a",
+ "toolchainBinDir": "C:/Users/Xliloz/.platformio/packages/toolchain-gccarmnoneeabi@1.70201.0/bin",
+ "internalConsoleOptions": "openOnSessionStart"
+ }
+ ]
+}
diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/.vscode/settings.json b/.platformio/platforms/at32/examples/cmsis-acd1_dma/.vscode/settings.json
new file mode 100644
index 0000000..9ae3c94
--- /dev/null
+++ b/.platformio/platforms/at32/examples/cmsis-acd1_dma/.vscode/settings.json
@@ -0,0 +1,5 @@
+{
+ "files.associations": {
+ "at32f4xx.h": "c"
+ }
+}
\ No newline at end of file
diff --git a/.platformio/platforms/at32/examples/cmsis-blink/.gitignore b/.platformio/platforms/at32/examples/cmsis-blink/.gitignore
index 661538a..03f4a3c 100644
--- a/.platformio/platforms/at32/examples/cmsis-blink/.gitignore
+++ b/.platformio/platforms/at32/examples/cmsis-blink/.gitignore
@@ -1,3 +1 @@
.pio
-.vscode
-build
diff --git a/.platformio/platforms/at32/examples/cmsis-blink/.vscode/c_cpp_properties.json b/.platformio/platforms/at32/examples/cmsis-blink/.vscode/c_cpp_properties.json
new file mode 100644
index 0000000..f2dba01
--- /dev/null
+++ b/.platformio/platforms/at32/examples/cmsis-blink/.vscode/c_cpp_properties.json
@@ -0,0 +1,48 @@
+//
+// !!! WARNING !!! AUTO-GENERATED FILE!
+// PLEASE DO NOT MODIFY IT AND USE "platformio.ini":
+// https://docs.platformio.org/page/projectconf/section_env_build.html#build-flags
+//
+{
+ "configurations": [
+ {
+ "name": "PlatformIO",
+ "includePath": [
+ "c:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-blink/include",
+ "c:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-blink/src",
+ "c:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-blink/lib/Delay",
+ "C:/Users/Xliloz/.platformio/packages/framework-cmsis@2.50501.200527/CMSIS/Include",
+ "C:/Users/Xliloz/.platformio/packages/framework-cmsis-at32f40/Include",
+ ""
+ ],
+ "browse": {
+ "limitSymbolsToIncludedHeaders": true,
+ "path": [
+ "c:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-blink/include",
+ "c:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-blink/src",
+ "c:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-blink/lib/Delay",
+ "C:/Users/Xliloz/.platformio/packages/framework-cmsis@2.50501.200527/CMSIS/Include",
+ "C:/Users/Xliloz/.platformio/packages/framework-cmsis-at32f40/Include",
+ ""
+ ]
+ },
+ "defines": [
+ "PLATFORMIO=50205",
+ "AT32F403ACGT7",
+ ""
+ ],
+ "cStandard": "c11",
+ "compilerPath": "C:/Users/Xliloz/.platformio/packages/toolchain-gccarmnoneeabi@1.70201.0/bin/arm-none-eabi-gcc.exe",
+ "compilerArgs": [
+ "-mfpu=fpv4-sp-d16",
+ "-mfloat-abi=hard",
+ "-mcpu=cortex-m4",
+ "-mthumb",
+ "-mfpu=fpv4-sp-d16",
+ "-mfloat-abi=hard",
+ ""
+ ]
+ }
+ ],
+ "version": 4
+}
diff --git a/.platformio/platforms/at32/examples/cmsis-blink/.vscode/extensions.json b/.platformio/platforms/at32/examples/cmsis-blink/.vscode/extensions.json
new file mode 100644
index 0000000..080e70d
--- /dev/null
+++ b/.platformio/platforms/at32/examples/cmsis-blink/.vscode/extensions.json
@@ -0,0 +1,10 @@
+{
+ // See http://go.microsoft.com/fwlink/?LinkId=827846
+ // for the documentation about the extensions.json format
+ "recommendations": [
+ "platformio.platformio-ide"
+ ],
+ "unwantedRecommendations": [
+ "ms-vscode.cpptools-extension-pack"
+ ]
+}
diff --git a/.platformio/platforms/at32/examples/cmsis-blink/.vscode/launch.json b/.platformio/platforms/at32/examples/cmsis-blink/.vscode/launch.json
new file mode 100644
index 0000000..2bbedcb
--- /dev/null
+++ b/.platformio/platforms/at32/examples/cmsis-blink/.vscode/launch.json
@@ -0,0 +1,44 @@
+// AUTOMATICALLY GENERATED FILE. PLEASE DO NOT MODIFY IT MANUALLY
+//
+// PIO Unified Debugger
+//
+// Documentation: https://docs.platformio.org/page/plus/debugging.html
+// Configuration: https://docs.platformio.org/page/projectconf/section_env_debug.html
+
+{
+ "version": "0.2.0",
+ "configurations": [
+ {
+ "type": "platformio-debug",
+ "request": "launch",
+ "name": "PIO Debug",
+ "executable": "c:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-blink/.pio/build/generic_f403a/firmware.elf",
+ "projectEnvName": "generic_f403a",
+ "toolchainBinDir": "C:/Users/Xliloz/.platformio/packages/toolchain-gccarmnoneeabi@1.70201.0/bin",
+ "internalConsoleOptions": "openOnSessionStart",
+ "preLaunchTask": {
+ "type": "PlatformIO",
+ "task": "Pre-Debug"
+ }
+ },
+ {
+ "type": "platformio-debug",
+ "request": "launch",
+ "name": "PIO Debug (skip Pre-Debug)",
+ "executable": "c:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-blink/.pio/build/generic_f403a/firmware.elf",
+ "projectEnvName": "generic_f403a",
+ "toolchainBinDir": "C:/Users/Xliloz/.platformio/packages/toolchain-gccarmnoneeabi@1.70201.0/bin",
+ "internalConsoleOptions": "openOnSessionStart"
+ },
+ {
+ "type": "platformio-debug",
+ "request": "launch",
+ "name": "PIO Debug (without uploading)",
+ "executable": "c:/Users/Xliloz/.platformio/platforms/at32/examples/cmsis-blink/.pio/build/generic_f403a/firmware.elf",
+ "projectEnvName": "generic_f403a",
+ "toolchainBinDir": "C:/Users/Xliloz/.platformio/packages/toolchain-gccarmnoneeabi@1.70201.0/bin",
+ "internalConsoleOptions": "openOnSessionStart",
+ "loadMode": "manual"
+ }
+ ]
+}
diff --git a/.platformio/platforms/at32/examples/cmsis-blink/.vscode/settings.json b/.platformio/platforms/at32/examples/cmsis-blink/.vscode/settings.json
new file mode 100644
index 0000000..9ae3c94
--- /dev/null
+++ b/.platformio/platforms/at32/examples/cmsis-blink/.vscode/settings.json
@@ -0,0 +1,5 @@
+{
+ "files.associations": {
+ "at32f4xx.h": "c"
+ }
+}
\ No newline at end of file
diff --git a/.platformio/platforms/at32/examples/cmsis-blink/gitignore b/.platformio/platforms/at32/examples/cmsis-blink/gitignore
deleted file mode 100644
index 03f4a3c..0000000
--- a/.platformio/platforms/at32/examples/cmsis-blink/gitignore
+++ /dev/null
@@ -1 +0,0 @@
-.pio
diff --git a/.platformio/platforms/at32/examples/cmsis-blink/lib/Delay/delay.c b/.platformio/platforms/at32/examples/cmsis-blink/lib/Delay/delay.c
index f7da62c..d4f80b9 100644
--- a/.platformio/platforms/at32/examples/cmsis-blink/lib/Delay/delay.c
+++ b/.platformio/platforms/at32/examples/cmsis-blink/lib/Delay/delay.c
@@ -20,7 +20,7 @@ void Delay_init()
{
/*Config Systick*/
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
- fac_us=(float)SystemCoreClock/(8 * 1000000);
+ fac_us=(float)SystemCoreClock/(240 * 1000000);
fac_ms=fac_us*1000;
}
diff --git a/.platformio/platforms/at32/examples/cmsis-blink/platformio.ini b/.platformio/platforms/at32/examples/cmsis-blink/platformio.ini
index 6000e54..315b4c0 100644
--- a/.platformio/platforms/at32/examples/cmsis-blink/platformio.ini
+++ b/.platformio/platforms/at32/examples/cmsis-blink/platformio.ini
@@ -14,19 +14,19 @@ board = generic_f403a
monitor_speed = 115200 ;serial monitor baudrate
;Use the following for jlink upload
-;upload_protocol = jlink
+upload_protocol = jlink
;Use the following for serial upload via bootloader (PA9, PA10)
;upload_protocol = serial
;upload_speed = 115200 ;default: 115200
;Use the following for DFU upload via USB port
-upload_protocol = dfu
-build_flags =
- -DDFU_MODE
- -UVECT_TAB_OFFSET
- -DUSER_VECT_TAB_ADDRESS
- -DVECT_TAB_OFFSET=0x2000 ; override default vector tale to support ISR table for DFU mode
+;upload_protocol = dfu
+;build_flags =
+; -DDFU_MODE
+; -UVECT_TAB_OFFSET
+; -DUSER_VECT_TAB_ADDRESS
+; -DVECT_TAB_OFFSET=0x2000 ; override default vector tale to support ISR table for DFU mode
;Use the following for custom uploader
;upload_protocol = custom
diff --git a/.platformio/platforms/at32/examples/cmsis-blink/src/main.c b/.platformio/platforms/at32/examples/cmsis-blink/src/main.c
index 167368a..2c41212 100644
--- a/.platformio/platforms/at32/examples/cmsis-blink/src/main.c
+++ b/.platformio/platforms/at32/examples/cmsis-blink/src/main.c
@@ -19,7 +19,7 @@ int main(void)
LEDPORT->_MODER |= GPIOMODER; // set pins to be general purpose output
for (;;) {
- Delay_ms(200);
+ Delay_ms(1000);
LEDPORT->OPTDT ^= (1<
-#
-# Documentation:
-#
-# * Travis CI Embedded Builds with PlatformIO
-# < https://docs.travis-ci.com/user/integration/platformio/ >
-#
-# * PlatformIO integration with Travis CI
-# < https://docs.platformio.org/page/ci/travis.html >
-#
-# * User Guide for `platformio ci` command
-# < https://docs.platformio.org/page/userguide/cmd_ci.html >
-#
-#
-# Please choose one of the following templates (proposed below) and uncomment
-# it (remove "# " before each line) or use own configuration according to the
-# Travis CI documentation (see above).
-#
-
-
-#
-# Template #1: General project. Test it using existing `platformio.ini`.
-#
-
-# language: python
-# python:
-# - "2.7"
-#
-# sudo: false
-# cache:
-# directories:
-# - "~/.platformio"
-#
-# install:
-# - pip install -U platformio
-# - platformio update
-#
-# script:
-# - platformio run
-
-
-#
-# Template #2: The project is intended to be used as a library with examples.
-#
-
-# language: python
-# python:
-# - "2.7"
-#
-# sudo: false
-# cache:
-# directories:
-# - "~/.platformio"
-#
-# env:
-# - PLATFORMIO_CI_SRC=path/to/test/file.c
-# - PLATFORMIO_CI_SRC=examples/file.ino
-# - PLATFORMIO_CI_SRC=path/to/test/directory
-#
-# install:
-# - pip install -U platformio
-# - platformio update
-#
-# script:
-# - platformio ci --lib="." --board=ID_1 --board=ID_2 --board=ID_N
diff --git a/.platformio/platforms/at32/gitmodules b/.platformio/platforms/at32/gitmodules
deleted file mode 100644
index e5cbf91..0000000
--- a/.platformio/platforms/at32/gitmodules
+++ /dev/null
@@ -1,6 +0,0 @@
-[submodule "builder/frameworks/libopencm3"]
- path = builder/frameworks/libopencm3
- url = https://github.com/platformio/builder-framework-libopencm3.git
-[submodule "builder/frameworks/arduino/mbed-core"]
- path = builder/frameworks/arduino/mbed-core
- url = https://github.com/platformio/builder-framework-arduino-core-mbed.git
diff --git a/.platformio/platforms/at32/ldscripts/AT32F435xC_FLASH.ld b/.platformio/platforms/at32/ldscripts/AT32F435xC_FLASH.ld
new file mode 100644
index 0000000..d5c2b4b
--- /dev/null
+++ b/.platformio/platforms/at32/ldscripts/AT32F435xC_FLASH.ld
@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+** File : AT32F435xC_FLASH.ld
+**
+** Abstract : Linker script for AT32F435xC Device with
+** 256KByte FLASH, 384KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : Artery Tek AT32
+**
+** Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF; /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/.platformio/platforms/at32/ldscripts/AT32F435xG_FLASH.ld b/.platformio/platforms/at32/ldscripts/AT32F435xG_FLASH.ld
new file mode 100644
index 0000000..1ecd8f0
--- /dev/null
+++ b/.platformio/platforms/at32/ldscripts/AT32F435xG_FLASH.ld
@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+** File : AT32F435xG_FLASH.ld
+**
+** Abstract : Linker script for AT32F435xG Device with
+** 1000KByte FLASH, 384KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : Artery Tek AT32
+**
+** Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF; /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1000K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/.platformio/platforms/at32/ldscripts/AT32F435xM_FLASH.ld b/.platformio/platforms/at32/ldscripts/AT32F435xM_FLASH.ld
new file mode 100644
index 0000000..53bcdca
--- /dev/null
+++ b/.platformio/platforms/at32/ldscripts/AT32F435xM_FLASH.ld
@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+** File : AT32F435xM_FLASH.ld
+**
+** Abstract : Linker script for AT32F435xM Device with
+** 4096KByte FLASH, 384KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : Artery Tek AT32
+**
+** Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF; /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 4032K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/.platformio/platforms/at32/ldscripts/AT32F437xC_FLASH.ld b/.platformio/platforms/at32/ldscripts/AT32F437xC_FLASH.ld
new file mode 100644
index 0000000..d9d0ecf
--- /dev/null
+++ b/.platformio/platforms/at32/ldscripts/AT32F437xC_FLASH.ld
@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+** File : AT32F437xC_FLASH.ld
+**
+** Abstract : Linker script for AT32F437xC Device with
+** 256KByte FLASH, 384KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : Artery Tek AT32
+**
+** Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF; /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/.platformio/platforms/at32/ldscripts/AT32F437xG_FLASH.ld b/.platformio/platforms/at32/ldscripts/AT32F437xG_FLASH.ld
new file mode 100644
index 0000000..c0984f3
--- /dev/null
+++ b/.platformio/platforms/at32/ldscripts/AT32F437xG_FLASH.ld
@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+** File : AT32F437xG_FLASH.ld
+**
+** Abstract : Linker script for AT32F437xG Device with
+** 1000KByte FLASH, 384KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : Artery Tek AT32
+**
+** Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF; /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1000K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/.platformio/platforms/at32/ldscripts/AT32F437xM_FLASH.ld b/.platformio/platforms/at32/ldscripts/AT32F437xM_FLASH.ld
new file mode 100644
index 0000000..850480c
--- /dev/null
+++ b/.platformio/platforms/at32/ldscripts/AT32F437xM_FLASH.ld
@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+** File : AT32F437xM_FLASH.ld
+**
+** Abstract : Linker script for AT32F437xM Device with
+** 4096KByte FLASH, 384KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : Artery Tek AT32
+**
+** Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20017FFF; /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 4032K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/.platformio/platforms/at32/piopm_ b/.platformio/platforms/at32/piopm_
deleted file mode 100644
index d7062fa..0000000
--- a/.platformio/platforms/at32/piopm_
+++ /dev/null
@@ -1 +0,0 @@
-{"type": "platform", "name": "at32", "version": "1.0.0", "spec": {"owner": "platformio", "id": 8020, "name": "at32", "requirements": null, "url": null}}
\ No newline at end of file
diff --git a/.platformio/platforms/at32/platform.json b/.platformio/platforms/at32/platform.json
index fdbad5e..60feae3 100644
--- a/.platformio/platforms/at32/platform.json
+++ b/.platformio/platforms/at32/platform.json
@@ -54,6 +54,12 @@
"owner": "platformio",
"version": "~1.0.0"
},
+ "framework-cmsis-at32f43": {
+ "type": "framework",
+ "optional": true,
+ "owner": "platformio",
+ "version": "~1.0.0"
+ },
"tool-openocd": {
"type": "uploader",
"optional": true,
@@ -95,7 +101,7 @@
"tool-ldscripts-at32": {
"optional": true,
"owner": "platformio",
- "version": "~0.1.0"
+ "version": "~0.1.1"
}
}
}