From df1d35353c0e28041f7ecee2be2ee2ada1f4af3e Mon Sep 17 00:00:00 2001 From: Martin Loren Date: Thu, 5 Dec 2024 15:16:35 +0800 Subject: [PATCH] Update 2024-12 --- .../platforms/at32/boards/generic_f435.json | 2 +- .../platforms/at32/boards/generic_f437.json | 47 + .../at32/builder/frameworks/cmsis.py | 17 +- .../AT32F435/cmsis-blink/include/usb_conf.h | 205 + .../AT32F435/cmsis-blink/platformio.ini | 2 +- .../cmsis-blink/src/at32f435_437_clock.c | 2 +- .../led_toggle}/.gitignore | 0 .../led_toggle/include/at32f435_437_clock.h | 44 + .../led_toggle/include/at32f435_437_conf.h | 173 + .../led_toggle/include/at32f435_437_int.h | 56 + .../AT32F437/led_toggle/include/usb_conf.h | 205 + .../AT32F437/led_toggle/lib/Delay/delay.c | 95 + .../led_toggle}/lib/Delay/delay.h | 10 +- .../led_toggle}/lib/README | 0 .../led_toggle/mdk_v5/led_toggle.uvoptx | 344 ++ .../led_toggle/mdk_v5/led_toggle.uvprojx | 487 +++ .../led_toggle}/platformio.ini | 13 +- .../examples/AT32F437/led_toggle/readme.txt | 9 + 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old-jlink/JLINK.md | 1 + 180 files changed, 2080 insertions(+), 8012 deletions(-) create mode 100644 .platformio/platforms/at32/boards/generic_f437.json create mode 100644 .platformio/platforms/at32/examples/AT32F435/cmsis-blink/include/usb_conf.h rename .platformio/platforms/at32/examples/{cmsis-acd1_dma => AT32F437/led_toggle}/.gitignore (100%) create mode 100644 .platformio/platforms/at32/examples/AT32F437/led_toggle/include/at32f435_437_clock.h create mode 100644 .platformio/platforms/at32/examples/AT32F437/led_toggle/include/at32f435_437_conf.h create mode 100644 .platformio/platforms/at32/examples/AT32F437/led_toggle/include/at32f435_437_int.h create mode 100644 .platformio/platforms/at32/examples/AT32F437/led_toggle/include/usb_conf.h create mode 100644 .platformio/platforms/at32/examples/AT32F437/led_toggle/lib/Delay/delay.c rename .platformio/platforms/at32/examples/{cmsis-acd1_dma => AT32F437/led_toggle}/lib/Delay/delay.h (58%) rename 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old-jlink/.platformio}/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F437_960.FLM (100%) rename {.platformio => old-jlink/.platformio}/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F4xx.JLinkScript (100%) rename JLINK.md => old-jlink/JLINK.md (98%) diff --git a/.platformio/platforms/at32/boards/generic_f435.json b/.platformio/platforms/at32/boards/generic_f435.json index d8bb88e..4f6dab8 100644 --- a/.platformio/platforms/at32/boards/generic_f435.json +++ b/.platformio/platforms/at32/boards/generic_f435.json @@ -32,7 +32,7 @@ "name": "Generic_F435", "upload": { "maximum_ram_size": 524288, - "maximum_size": 262144, + "maximum_size": 1048576, "protocol": "serial", "protocols": [ "jlink", diff --git a/.platformio/platforms/at32/boards/generic_f437.json b/.platformio/platforms/at32/boards/generic_f437.json new file mode 100644 index 0000000..e0c42a6 --- /dev/null +++ b/.platformio/platforms/at32/boards/generic_f437.json @@ -0,0 +1,47 @@ +{ + "build": { + "core": "at32", + "cpu": "cortex-m4", + "extra_flags": "-DAT32F437RGT7 -DAT_START_F437_V1", + "f_cpu": "288000000L", + "hwids": [ + [ + "0x2E3C", + "0xDF11" + ] + ], + "mcu": "at32f437xg", + "product_line": "AT32F435_437", + "variant": "AT32F4xx/F437_F437(T-U)" + }, + "debug": { + "default_tools": [ + "stlink" + ], + "jlink_device": "AT32F437xGx", + "openocd_extra_args": [ + "-c", + "reset_config none" + ], + "openocd_target": "stm32f4x", + "svd_path": "STM32F437xx.svd" + }, + "frameworks": [ + "cmsis" + ], + "name": "Generic_F437", + "upload": { + "maximum_ram_size": 524288, + "maximum_size": 1048576, + "protocol": "serial", + "protocols": [ + "jlink", + "cmsis-dap", + "stlink", + "serial", + "blackmagic" + ] + }, + "url": "https://www.arterychip.com/en/product/AT32F437.jsp", + "vendor": "Artery" +} diff --git a/.platformio/platforms/at32/builder/frameworks/cmsis.py b/.platformio/platforms/at32/builder/frameworks/cmsis.py index bcb5102..280f24e 100644 --- a/.platformio/platforms/at32/builder/frameworks/cmsis.py +++ b/.platformio/platforms/at32/builder/frameworks/cmsis.py @@ -42,7 +42,10 @@ mcu = board.get("build.mcu", "") product_line = board.get("build.product_line", "") assert product_line, "Missing MCU or Product Line field" - +print("-------------------------------------------------------------------------------"); +print("AT32 PlatformIO porting by MartinLoren®"); +print("-------------------------------------------------------------------------------"); +print("Version: 2024-12"); #env.SConscript("_bare.py") #build_script = "_bare.py" @@ -58,7 +61,11 @@ SConscript(build_script) CMSIS_DIR = platform.get_package_dir("framework-cmsis") CMSIS_DEVICE_DIR = platform.get_package_dir("framework-cmsis-" + mcu[0:7]) -LDSCRIPTS_DIR = join('%s' % platform.get_dir() or "", "ldscripts") +LDSCRIPTS_DIR = platform.get_package_dir("tool-ldscripts-at32") +print("Environment:"); +print(" CMSIS_DIR: "+CMSIS_DIR); +print(" CMSIS_DEVICE_DIR: "+CMSIS_DEVICE_DIR); +print(" LDSCRIPTS_DIR: "+LDSCRIPTS_DIR); assert all(os.path.isdir(d) for d in (CMSIS_DIR, CMSIS_DEVICE_DIR, LDSCRIPTS_DIR)) @@ -81,9 +88,9 @@ def generate_ldscript(default_ldscript_path): def get_linker_script(): ldscript_match = glob.glob(os.path.join( LDSCRIPTS_DIR, mcu[0:7], mcu[0:11].upper() + "*_FLASH.ld")) - + #print(os.path.join(LDSCRIPTS_DIR, mcu[0:7], mcu[0:11].upper() + "*_FLASH.ld")) + if ldscript_match and os.path.isfile(ldscript_match[0]): - print("LD Script file: " +ldscript_match[0]) return ldscript_match[0] default_ldscript = os.path.join( @@ -99,7 +106,7 @@ def get_linker_script(): def prepare_startup_file(src_path): - startup_file = os.path.join(src_path, "gcc", "startup_%s.s" % product_line.lower()) + startup_file = os.path.join(src_path, "gcc", "startup_%s.S" % product_line.lower()) print("Startup file: " + startup_file) # Change file extension to uppercase: if not os.path.isfile(startup_file) and os.path.isfile(startup_file[:-2] + ".s"): diff --git a/.platformio/platforms/at32/examples/AT32F435/cmsis-blink/include/usb_conf.h b/.platformio/platforms/at32/examples/AT32F435/cmsis-blink/include/usb_conf.h new file mode 100644 index 0000000..c245708 --- /dev/null +++ b/.platformio/platforms/at32/examples/AT32F435/cmsis-blink/include/usb_conf.h @@ -0,0 +1,205 @@ +/** + ****************************************************************************** + * File : USB_Device/VirtualComPort_loopback/inc/usb_conf.h + * Version: V1.2.2 + * Date : 2020-07-01 + * Brief : USB Endpoint config header. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_CONF_F435_H +#define __USB_CONF_F435_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "at32f435_437_usb.h" +#include "at32f435_437.h" +#include "stdio.h" + +/** @addtogroup AT32F435_periph_examples + * @{ + */ + +/** @addtogroup 435_USB_device_vcp_loopback + * @{ + */ + +/** + * @brief enable usb device mode + */ +#define USE_OTG_DEVICE_MODE + +/** + * @brief enable usb host mode + */ +/* #define USE_OTG_HOST_MODE */ + +/** + * @brief select otgfs1 or otgfs2 define + */ + +/* use otgfs1 */ +#define OTG_USB_ID 1 + +/* use otgfs2 */ +//#define OTG_USB_ID 2 + +#if (OTG_USB_ID == 1) +#define USB_ID 0 +#define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK +#define OTG_IRQ OTGFS1_IRQn +#define OTG_IRQ_HANDLER OTGFS1_IRQHandler +#define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn +#define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler +#define OTG_WKUP_EXINT_LINE EXINT_LINE_18 + +#define OTG_PIN_GPIO GPIOA +#define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + +#define OTG_PIN_DP GPIO_PINS_12 +#define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE12 + +#define OTG_PIN_DM GPIO_PINS_11 +#define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE11 + +#define OTG_PIN_VBUS GPIO_PINS_9 +#define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 + +#define OTG_PIN_ID GPIO_PINS_10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 + +//#define OTG_PIN_SOF_GPIO GPIOA +//#define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +//#define OTG_PIN_SOF GPIO_PINS_8 +//#define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 + +#define OTG_PIN_MUX GPIO_MUX_10 +#endif + +#if (OTG_USB_ID == 2) +#define USB_ID 1 +#define OTG_CLOCK CRM_OTGFS2_PERIPH_CLOCK +#define OTG_IRQ OTGFS2_IRQn +#define OTG_IRQ_HANDLER OTGFS2_IRQHandler +#define OTG_WKUP_IRQ OTGFS2_WKUP_IRQn +#define OTG_WKUP_HANDLER OTGFS2_WKUP_IRQHandler +#define OTG_WKUP_EXINT_LINE EXINT_LINE_20 + +#define OTG_PIN_GPIO GPIOB +#define OTG_PIN_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK + +#define OTG_PIN_DP GPIO_PINS_15 +#define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE15 + +#define OTG_PIN_DM GPIO_PINS_14 +#define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE14 + +#define OTG_PIN_VBUS GPIO_PINS_13 +#define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 + +#define OTG_PIN_ID GPIO_PINS_12 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 + +#define OTG_PIN_SOF_GPIO GPIOA +#define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_SOF GPIO_PINS_4 +#define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE4 + +#define OTG_PIN_MUX GPIO_MUX_12 +#endif + +/** + * @brief usb device mode config + */ +#ifdef USE_OTG_DEVICE_MODE +/** + * @brief usb device mode fifo + */ +/* otg1 device fifo */ +#define USBD_RX_SIZE 128 +#define USBD_EP0_TX_SIZE 64//24 +#define USBD_EP1_TX_SIZE 64//20 +#define USBD_EP2_TX_SIZE 20 +#define USBD_EP3_TX_SIZE 20 +#define USBD_EP4_TX_SIZE 20 +#define USBD_EP5_TX_SIZE 20 +#define USBD_EP6_TX_SIZE 20 +#define USBD_EP7_TX_SIZE 20 + +/* otg2 device fifo */ +#define USBD2_RX_SIZE 128 +#define USBD2_EP0_TX_SIZE 24//24 +#define USBD2_EP1_TX_SIZE 20//20 +#define USBD2_EP2_TX_SIZE 20 +#define USBD2_EP3_TX_SIZE 20 +#define USBD2_EP4_TX_SIZE 20 +#define USBD2_EP5_TX_SIZE 20 +#define USBD2_EP6_TX_SIZE 20 +#define USBD2_EP7_TX_SIZE 20 + +/** + * @brief usb endpoint max num define + */ +#ifndef USB_EPT_MAX_NUM +#define USB_EPT_MAX_NUM 8 +#endif +#endif + +/** + * @brief usb host mode config + */ +#ifdef USE_OTG_HOST_MODE +#ifndef USB_HOST_CHANNEL_NUM +#define USB_HOST_CHANNEL_NUM 16 +#endif + +/** + * @brief usb host mode fifo + */ +/* otg1 host fifo */ +#define USBH_RX_FIFO_SIZE 128 +#define USBH_NP_TX_FIFO_SIZE 96 +#define USBH_P_TX_FIFO_SIZE 96 + +/* otg2 host fifo */ +#define USBH2_RX_FIFO_SIZE 128 +#define USBH2_NP_TX_FIFO_SIZE 96 +#define USBH2_P_TX_FIFO_SIZE 96 +#endif + +/** + * @brief usb sof output enable + */ +/* #define USB_SOF_OUTPUT_ENABLE */ + +/** + * @brief usb vubs ignor, not use vbus pin + */ +#define USB_VBUS_IGNORE + +/** + * @brief usb low power wakeup handler enable + */ +/* #define USB_LOW_POWER_WAKUP */ + +void usb_delay_ms(uint32_t ms); +void usb_delay_us(uint32_t us); + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /*__USB_CONF_F435_H*/ + + + diff --git a/.platformio/platforms/at32/examples/AT32F435/cmsis-blink/platformio.ini b/.platformio/platforms/at32/examples/AT32F435/cmsis-blink/platformio.ini index 50c145f..a44562d 100644 --- a/.platformio/platforms/at32/examples/AT32F435/cmsis-blink/platformio.ini +++ b/.platformio/platforms/at32/examples/AT32F435/cmsis-blink/platformio.ini @@ -12,7 +12,7 @@ platform = at32 framework = cmsis board = generic_f435 monitor_speed = 115200 ;serial monitor baudrate - +build_flags = -I include ;Use the following for jlink upload upload_protocol = jlink diff --git a/.platformio/platforms/at32/examples/AT32F435/cmsis-blink/src/at32f435_437_clock.c b/.platformio/platforms/at32/examples/AT32F435/cmsis-blink/src/at32f435_437_clock.c index 2c29ee4..885675e 100644 --- a/.platformio/platforms/at32/examples/AT32F435/cmsis-blink/src/at32f435_437_clock.c +++ b/.platformio/platforms/at32/examples/AT32F435/cmsis-blink/src/at32f435_437_clock.c @@ -58,7 +58,7 @@ void system_clock_config(void) flash_clock_divider_set(FLASH_CLOCK_DIV_3); /* reset crm */ - crm_reset(); + //crm_reset(); //crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE); diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/.gitignore b/.platformio/platforms/at32/examples/AT32F437/led_toggle/.gitignore similarity index 100% rename from .platformio/platforms/at32/examples/cmsis-acd1_dma/.gitignore rename to .platformio/platforms/at32/examples/AT32F437/led_toggle/.gitignore diff --git a/.platformio/platforms/at32/examples/AT32F437/led_toggle/include/at32f435_437_clock.h b/.platformio/platforms/at32/examples/AT32F437/led_toggle/include/at32f435_437_clock.h new file mode 100644 index 0000000..221f67b --- /dev/null +++ b/.platformio/platforms/at32/examples/AT32F437/led_toggle/include/at32f435_437_clock.h @@ -0,0 +1,44 @@ +/** + ************************************************************************** + * @file at32f435_437_clock.h + * @brief header file of clock program + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* define to prevent recursive inclusion -------------------------------------*/ +#ifndef __AT32F435_437_CLOCK_H +#define __AT32F435_437_CLOCK_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* includes ------------------------------------------------------------------*/ +#include "at32f435_437.h" + +/* exported functions ------------------------------------------------------- */ +void system_clock_config(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/.platformio/platforms/at32/examples/AT32F437/led_toggle/include/at32f435_437_conf.h b/.platformio/platforms/at32/examples/AT32F437/led_toggle/include/at32f435_437_conf.h new file mode 100644 index 0000000..54ab75b --- /dev/null +++ b/.platformio/platforms/at32/examples/AT32F437/led_toggle/include/at32f435_437_conf.h @@ -0,0 +1,173 @@ +/** + ************************************************************************** + * @file at32f435_437_conf.h + * @brief at32f435_437 config header file + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* define to prevent recursive inclusion -------------------------------------*/ +#ifndef __AT32F435_437_CONF_H +#define __AT32F435_437_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief in the following line adjust the value of high speed external crystal (hext) + * used in your application + * + * tip: to avoid modifying this file each time you need to use different hext, you + * can define the hext value in your toolchain compiler preprocessor. + * + */ +#if !defined HEXT_VALUE +#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed external crystal in hz */ +#endif + +/** + * @brief in the following line adjust the high speed external crystal (hext) startup + * timeout value + */ +#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ +#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */ +#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed external clock in hz */ + +/* module define -------------------------------------------------------------*/ +#define CRM_MODULE_ENABLED +#define TMR_MODULE_ENABLED +#define ERTC_MODULE_ENABLED +#define GPIO_MODULE_ENABLED +#define I2C_MODULE_ENABLED +#define USART_MODULE_ENABLED +#define PWC_MODULE_ENABLED +#define CAN_MODULE_ENABLED +#define ADC_MODULE_ENABLED +#define DAC_MODULE_ENABLED +#define SPI_MODULE_ENABLED +#define EDMA_MODULE_ENABLED +#define DMA_MODULE_ENABLED +#define DEBUG_MODULE_ENABLED +#define FLASH_MODULE_ENABLED +#define CRC_MODULE_ENABLED +#define WWDT_MODULE_ENABLED +#define WDT_MODULE_ENABLED +#define EXINT_MODULE_ENABLED +#define SDIO_MODULE_ENABLED +#define XMC_MODULE_ENABLED +#define USB_MODULE_ENABLED +#define ACC_MODULE_ENABLED +#define MISC_MODULE_ENABLED +#define QSPI_MODULE_ENABLED +#define DVP_MODULE_ENABLED +#define SCFG_MODULE_ENABLED +#define EMAC_MODULE_ENABLED + +/* includes ------------------------------------------------------------------*/ +#ifdef CRM_MODULE_ENABLED +#include "at32f435_437_crm.h" +#endif +#ifdef TMR_MODULE_ENABLED +#include "at32f435_437_tmr.h" +#endif +#ifdef ERTC_MODULE_ENABLED +#include "at32f435_437_ertc.h" +#endif +#ifdef GPIO_MODULE_ENABLED +#include "at32f435_437_gpio.h" +#endif +#ifdef I2C_MODULE_ENABLED +#include "at32f435_437_i2c.h" +#endif +#ifdef USART_MODULE_ENABLED +#include "at32f435_437_usart.h" +#endif +#ifdef PWC_MODULE_ENABLED +#include "at32f435_437_pwc.h" +#endif +#ifdef CAN_MODULE_ENABLED +#include "at32f435_437_can.h" +#endif +#ifdef ADC_MODULE_ENABLED +#include "at32f435_437_adc.h" +#endif +#ifdef DAC_MODULE_ENABLED +#include "at32f435_437_dac.h" +#endif +#ifdef SPI_MODULE_ENABLED +#include "at32f435_437_spi.h" +#endif +#ifdef DMA_MODULE_ENABLED +#include "at32f435_437_dma.h" +#endif +#ifdef DEBUG_MODULE_ENABLED +#include "at32f435_437_debug.h" +#endif +#ifdef FLASH_MODULE_ENABLED +#include "at32f435_437_flash.h" +#endif +#ifdef CRC_MODULE_ENABLED +#include "at32f435_437_crc.h" +#endif +#ifdef WWDT_MODULE_ENABLED +#include "at32f435_437_wwdt.h" +#endif +#ifdef WDT_MODULE_ENABLED +#include "at32f435_437_wdt.h" +#endif +#ifdef EXINT_MODULE_ENABLED +#include "at32f435_437_exint.h" +#endif +#ifdef SDIO_MODULE_ENABLED +#include "at32f435_437_sdio.h" +#endif +#ifdef XMC_MODULE_ENABLED +#include "at32f435_437_xmc.h" +#endif +#ifdef ACC_MODULE_ENABLED +#include "at32f435_437_acc.h" +#endif +#ifdef MISC_MODULE_ENABLED +#include "at32f435_437_misc.h" +#endif +#ifdef EDMA_MODULE_ENABLED +#include "at32f435_437_edma.h" +#endif +#ifdef QSPI_MODULE_ENABLED +#include "at32f435_437_qspi.h" +#endif +#ifdef SCFG_MODULE_ENABLED +#include "at32f435_437_scfg.h" +#endif +#ifdef EMAC_MODULE_ENABLED +#include "at32f435_437_emac.h" +#endif +#ifdef DVP_MODULE_ENABLED +#include "at32f435_437_dvp.h" +#endif +#ifdef USB_MODULE_ENABLED +#include "at32f435_437_usb.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/.platformio/platforms/at32/examples/AT32F437/led_toggle/include/at32f435_437_int.h b/.platformio/platforms/at32/examples/AT32F437/led_toggle/include/at32f435_437_int.h new file mode 100644 index 0000000..afd2ad1 --- /dev/null +++ b/.platformio/platforms/at32/examples/AT32F437/led_toggle/include/at32f435_437_int.h @@ -0,0 +1,56 @@ +/** + ************************************************************************** + * @file at32f435_437_int.h + * @brief header file of main interrupt service routines. + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* define to prevent recursive inclusion -------------------------------------*/ +#ifndef __AT32F435_437_INT_H +#define __AT32F435_437_INT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* includes ------------------------------------------------------------------*/ +#include "at32f435_437.h" + +/* exported types ------------------------------------------------------------*/ +/* exported constants --------------------------------------------------------*/ +/* exported macro ------------------------------------------------------------*/ +/* exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/.platformio/platforms/at32/examples/AT32F437/led_toggle/include/usb_conf.h b/.platformio/platforms/at32/examples/AT32F437/led_toggle/include/usb_conf.h new file mode 100644 index 0000000..c245708 --- /dev/null +++ b/.platformio/platforms/at32/examples/AT32F437/led_toggle/include/usb_conf.h @@ -0,0 +1,205 @@ +/** + ****************************************************************************** + * File : USB_Device/VirtualComPort_loopback/inc/usb_conf.h + * Version: V1.2.2 + * Date : 2020-07-01 + * Brief : USB Endpoint config header. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_CONF_F435_H +#define __USB_CONF_F435_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "at32f435_437_usb.h" +#include "at32f435_437.h" +#include "stdio.h" + +/** @addtogroup AT32F435_periph_examples + * @{ + */ + +/** @addtogroup 435_USB_device_vcp_loopback + * @{ + */ + +/** + * @brief enable usb device mode + */ +#define USE_OTG_DEVICE_MODE + +/** + * @brief enable usb host mode + */ +/* #define USE_OTG_HOST_MODE */ + +/** + * @brief select otgfs1 or otgfs2 define + */ + +/* use otgfs1 */ +#define OTG_USB_ID 1 + +/* use otgfs2 */ +//#define OTG_USB_ID 2 + +#if (OTG_USB_ID == 1) +#define USB_ID 0 +#define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK +#define OTG_IRQ OTGFS1_IRQn +#define OTG_IRQ_HANDLER OTGFS1_IRQHandler +#define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn +#define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler +#define OTG_WKUP_EXINT_LINE EXINT_LINE_18 + +#define OTG_PIN_GPIO GPIOA +#define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + +#define OTG_PIN_DP GPIO_PINS_12 +#define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE12 + +#define OTG_PIN_DM GPIO_PINS_11 +#define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE11 + +#define OTG_PIN_VBUS GPIO_PINS_9 +#define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 + +#define OTG_PIN_ID GPIO_PINS_10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 + +//#define OTG_PIN_SOF_GPIO GPIOA +//#define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +//#define OTG_PIN_SOF GPIO_PINS_8 +//#define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 + +#define OTG_PIN_MUX GPIO_MUX_10 +#endif + +#if (OTG_USB_ID == 2) +#define USB_ID 1 +#define OTG_CLOCK CRM_OTGFS2_PERIPH_CLOCK +#define OTG_IRQ OTGFS2_IRQn +#define OTG_IRQ_HANDLER OTGFS2_IRQHandler +#define OTG_WKUP_IRQ OTGFS2_WKUP_IRQn +#define OTG_WKUP_HANDLER OTGFS2_WKUP_IRQHandler +#define OTG_WKUP_EXINT_LINE EXINT_LINE_20 + +#define OTG_PIN_GPIO GPIOB +#define OTG_PIN_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK + +#define OTG_PIN_DP GPIO_PINS_15 +#define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE15 + +#define OTG_PIN_DM GPIO_PINS_14 +#define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE14 + +#define OTG_PIN_VBUS GPIO_PINS_13 +#define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 + +#define OTG_PIN_ID GPIO_PINS_12 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 + +#define OTG_PIN_SOF_GPIO GPIOA +#define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_SOF GPIO_PINS_4 +#define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE4 + +#define OTG_PIN_MUX GPIO_MUX_12 +#endif + +/** + * @brief usb device mode config + */ +#ifdef USE_OTG_DEVICE_MODE +/** + * @brief usb device mode fifo + */ +/* otg1 device fifo */ +#define USBD_RX_SIZE 128 +#define USBD_EP0_TX_SIZE 64//24 +#define USBD_EP1_TX_SIZE 64//20 +#define USBD_EP2_TX_SIZE 20 +#define USBD_EP3_TX_SIZE 20 +#define USBD_EP4_TX_SIZE 20 +#define USBD_EP5_TX_SIZE 20 +#define USBD_EP6_TX_SIZE 20 +#define USBD_EP7_TX_SIZE 20 + +/* otg2 device fifo */ +#define USBD2_RX_SIZE 128 +#define USBD2_EP0_TX_SIZE 24//24 +#define USBD2_EP1_TX_SIZE 20//20 +#define USBD2_EP2_TX_SIZE 20 +#define USBD2_EP3_TX_SIZE 20 +#define USBD2_EP4_TX_SIZE 20 +#define USBD2_EP5_TX_SIZE 20 +#define USBD2_EP6_TX_SIZE 20 +#define USBD2_EP7_TX_SIZE 20 + +/** + * @brief usb endpoint max num define + */ +#ifndef USB_EPT_MAX_NUM +#define USB_EPT_MAX_NUM 8 +#endif +#endif + +/** + * @brief usb host mode config + */ +#ifdef USE_OTG_HOST_MODE +#ifndef USB_HOST_CHANNEL_NUM +#define USB_HOST_CHANNEL_NUM 16 +#endif + +/** + * @brief usb host mode fifo + */ +/* otg1 host fifo */ +#define USBH_RX_FIFO_SIZE 128 +#define USBH_NP_TX_FIFO_SIZE 96 +#define USBH_P_TX_FIFO_SIZE 96 + +/* otg2 host fifo */ +#define USBH2_RX_FIFO_SIZE 128 +#define USBH2_NP_TX_FIFO_SIZE 96 +#define USBH2_P_TX_FIFO_SIZE 96 +#endif + +/** + * @brief usb sof output enable + */ +/* #define USB_SOF_OUTPUT_ENABLE */ + +/** + * @brief usb vubs ignor, not use vbus pin + */ +#define USB_VBUS_IGNORE + +/** + * @brief usb low power wakeup handler enable + */ +/* #define USB_LOW_POWER_WAKUP */ + +void usb_delay_ms(uint32_t ms); +void usb_delay_us(uint32_t us); + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /*__USB_CONF_F435_H*/ + + + diff --git a/.platformio/platforms/at32/examples/AT32F437/led_toggle/lib/Delay/delay.c b/.platformio/platforms/at32/examples/AT32F437/led_toggle/lib/Delay/delay.c new file mode 100644 index 0000000..ef3f19c --- /dev/null +++ b/.platformio/platforms/at32/examples/AT32F437/led_toggle/lib/Delay/delay.c @@ -0,0 +1,95 @@ +/*DO NOT USE - DON'T WORK*/ + +#include "delay.h" +#include "stdio.h" + + +/*delay macros*/ +#define STEP_DELAY_MS 500 + +/*delay variable*/ +static __IO float fac_us; +static __IO float fac_ms; + + +/** + * @brief initialize Delay function + * @param None + * @retval None + */ +void delay_init() +{ + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8); + fac_us = system_core_clock / (1000000U); + fac_ms = fac_us * (1000U); +} + +/** + * @brief inserts a delay time. + * @param nus: specifies the delay time length, in microsecond. + * @retval none + */ +void delay_us(uint32_t nus) +{ + uint32_t temp = 0; + SysTick->LOAD = (uint32_t)(nus * fac_us); + SysTick->VAL = 0x00; + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk ; + do + { + temp = SysTick->CTRL; + }while((temp & 0x01) && !(temp & (1 << 16))); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SysTick->VAL = 0x00; +} + +/** + * @brief inserts a delay time. + * @param nms: specifies the delay time length, in milliseconds. + * @retval none + */ +void delay_ms(uint16_t nms) +{ + uint32_t temp = 0; + while(nms) + { + if(nms > STEP_DELAY_MS) + { + SysTick->LOAD = (uint32_t)(STEP_DELAY_MS * fac_ms); + nms -= STEP_DELAY_MS; + } + else + { + SysTick->LOAD = (uint32_t)(nms * fac_ms); + nms = 0; + } + SysTick->VAL = 0x00; + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + do + { + temp = SysTick->CTRL; + }while((temp & 0x01) && !(temp & (1 << 16))); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SysTick->VAL = 0x00; + } +} + +/** + * @brief inserts a delay time. + * @param sec: specifies the delay time, in seconds. + * @retval none + */ +void delay_sec(uint16_t sec) +{ + uint16_t index; + for(index = 0; index < sec; index++) + { + delay_ms(500); + delay_ms(500); + } +} + + diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/lib/Delay/delay.h b/.platformio/platforms/at32/examples/AT32F437/led_toggle/lib/Delay/delay.h similarity index 58% rename from .platformio/platforms/at32/examples/cmsis-acd1_dma/lib/Delay/delay.h rename to .platformio/platforms/at32/examples/AT32F437/led_toggle/lib/Delay/delay.h index 58cc121..9288794 100644 --- a/.platformio/platforms/at32/examples/cmsis-acd1_dma/lib/Delay/delay.h +++ b/.platformio/platforms/at32/examples/AT32F437/led_toggle/lib/Delay/delay.h @@ -5,12 +5,12 @@ #ifndef __DELAY_H #define __DELAY_H -#include +#include "at32f435_437.h" /*Delay function*/ -void Delay_init(void); -void Delay_us(u32 nus); -void Delay_ms(u16 nms); -void Delay_sec(u16 sec); +void delay_init(void); +void delay_us(u32 nus); +void delay_ms(u16 nms); +void delay_sec(u16 sec); #endif \ No newline at end of file diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/lib/README b/.platformio/platforms/at32/examples/AT32F437/led_toggle/lib/README similarity index 100% rename from .platformio/platforms/at32/examples/cmsis-acd1_dma/lib/README rename to .platformio/platforms/at32/examples/AT32F437/led_toggle/lib/README diff --git a/.platformio/platforms/at32/examples/AT32F437/led_toggle/mdk_v5/led_toggle.uvoptx b/.platformio/platforms/at32/examples/AT32F437/led_toggle/mdk_v5/led_toggle.uvoptx new file mode 100644 index 0000000..f2ca0a6 --- /dev/null +++ b/.platformio/platforms/at32/examples/AT32F437/led_toggle/mdk_v5/led_toggle.uvoptx @@ -0,0 +1,344 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + led_toggle + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0AT32F437_4032 -FS08000000 -FL03F0000 -FP0($$Device:-AT32F437ZMT7$Flash\AT32F437_4032.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + user + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\src\at32f435_437_clock.c + at32f435_437_clock.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\src\at32f435_437_int.c + at32f435_437_int.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\src\main.c + main.c + 0 + 0 + + + + + bsp + 0 + 0 + 0 + 0 + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\at32f435_437_board\at32f435_437_board.c + at32f435_437_board.c + 0 + 0 + + + + + firmware + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_gpio.c + at32f435_437_gpio.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_crm.c + at32f435_437_crm.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_usart.c + at32f435_437_usart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_misc.c + at32f435_437_misc.c + 0 + 0 + + + + + cmsis + 0 + 0 + 0 + 0 + + 4 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\cmsis\cm4\device_support\system_at32f435_437.c + system_at32f435_437.c + 0 + 0 + + + 4 + 10 + 2 + 0 + 0 + 0 + ..\..\..\..\..\..\libraries\cmsis\cm4\device_support\startup\mdk\startup_at32f435_437.s + startup_at32f435_437.s + 0 + 0 + + + + + readme + 0 + 0 + 0 + 0 + + 5 + 11 + 5 + 0 + 0 + 0 + ..\readme.txt + readme.txt + 0 + 0 + + + + diff --git a/.platformio/platforms/at32/examples/AT32F437/led_toggle/mdk_v5/led_toggle.uvprojx b/.platformio/platforms/at32/examples/AT32F437/led_toggle/mdk_v5/led_toggle.uvprojx new file mode 100644 index 0000000..8aba61e --- /dev/null +++ b/.platformio/platforms/at32/examples/AT32F437/led_toggle/mdk_v5/led_toggle.uvprojx @@ -0,0 +1,487 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + led_toggle + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + -AT32F437ZMT7 + ArteryTek + ArteryTek.AT32F435_437_DFP.2.0.1 + IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0AT32F437_4032 -FS08000000 -FL03F0000 -FP0($$Device:-AT32F437ZMT7$Flash\AT32F437_4032.FLM)) + 0 + $$Device:- + + + + + + + + + + $$Device:-AT32F437ZMT7$SVD\AT32F437xx_v2.svd + 0 + 0 + + + + AT32F437ZMT7$Device\Include\at32f435_437.h\ + AT32F437ZMT7$Device\Include\at32f435_437.h\ + + 0 + 0 + 0 + 0 + 1 + + .\objects\ + led_toggle + 1 + 0 + 1 + 1 + 1 + .\listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 1 + 0x8000000 + 0x3f0000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x3f0000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + AT32F437ZMT7,USE_STDPERIPH_DRIVER,AT_START_F437_V1 + + ..\..\..\..\..\..\libraries\drivers\inc;..\..\..\..\..\..\libraries\cmsis\cm4\core_support;..\..\..\..\..\..\libraries\cmsis\cm4\device_support;..\..\..\..\templates\inc;..\..\..\..\..\at32f435_437_board + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + user + + + at32f435_437_clock.c + 1 + ..\src\at32f435_437_clock.c + + + at32f435_437_int.c + 1 + ..\src\at32f435_437_int.c + + + main.c + 1 + ..\src\main.c + + + + + bsp + + + at32f435_437_board.c + 1 + ..\..\..\..\..\at32f435_437_board\at32f435_437_board.c + + + + + firmware + + + at32f435_437_gpio.c + 1 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_gpio.c + + + at32f435_437_crm.c + 1 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_crm.c + + + at32f435_437_usart.c + 1 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_usart.c + + + at32f435_437_misc.c + 1 + ..\..\..\..\..\..\libraries\drivers\src\at32f435_437_misc.c + + + + + cmsis + + + system_at32f435_437.c + 1 + ..\..\..\..\..\..\libraries\cmsis\cm4\device_support\system_at32f435_437.c + + + startup_at32f435_437.s + 2 + ..\..\..\..\..\..\libraries\cmsis\cm4\device_support\startup\mdk\startup_at32f435_437.s + + + + + readme + + + readme.txt + 5 + ..\readme.txt + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/platformio.ini b/.platformio/platforms/at32/examples/AT32F437/led_toggle/platformio.ini similarity index 54% rename from .platformio/platforms/at32/examples/cmsis-acd1_dma/platformio.ini rename to .platformio/platforms/at32/examples/AT32F437/led_toggle/platformio.ini index a8ac39c..70ab93e 100644 --- a/.platformio/platforms/at32/examples/cmsis-acd1_dma/platformio.ini +++ b/.platformio/platforms/at32/examples/AT32F437/led_toggle/platformio.ini @@ -7,12 +7,11 @@ ; Please visit documentation for the other options and examples ; http://docs.platformio.org/page/projectconf.html -[env:generic_f403a] +[env:led_togle] platform = at32 framework = cmsis -board = generic_f403a -monitor_speed = 115200 -upload_protocol = custom -upload_port = COM12 -upload_speed = 921600 ;115200 460800 921600 -upload_command = ${platformio.packages_dir}/framework-cmsis-at32f40/tools/stm32flash/stm32flash -g 0x8000000 -b $UPLOAD_SPEED -w $SOURCE $UPLOAD_PORT +board = generic_f437 +build_flags = -I include +monitor_speed = 921600 +;upload_protocol = serial +upload_protocol = jlink diff --git a/.platformio/platforms/at32/examples/AT32F437/led_toggle/readme.txt b/.platformio/platforms/at32/examples/AT32F437/led_toggle/readme.txt new file mode 100644 index 0000000..e494181 --- /dev/null +++ b/.platformio/platforms/at32/examples/AT32F437/led_toggle/readme.txt @@ -0,0 +1,9 @@ +/** + ************************************************************************** + * @file readme.txt + * @brief readme + ************************************************************************** + */ + + Light on/off pin PB12, 1Hz frequency for complete cycle. + diff --git a/.platformio/platforms/at32/examples/AT32F437/led_toggle/src/at32f435_437_clock.c b/.platformio/platforms/at32/examples/AT32F437/led_toggle/src/at32f435_437_clock.c new file mode 100644 index 0000000..de1c563 --- /dev/null +++ b/.platformio/platforms/at32/examples/AT32F437/led_toggle/src/at32f435_437_clock.c @@ -0,0 +1,119 @@ +/** + ************************************************************************** + * @file at32f435_437_clock.c + * @brief system clock config program + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* includes ------------------------------------------------------------------*/ +#include "at32f435_437_clock.h" + +/** + * @brief system clock config program + * @note the system clock is configured as follow: + * system clock (sclk) = (hext * pll_ns)/(pll_ms * pll_fr) + * system clock source = pll (hext) + * - hext = HEXT_VALUE + * - sclk = 288000000 + * - ahbdiv = 1 + * - ahbclk = 288000000 + * - apb2div = 2 + * - apb2clk = 144000000 + * - apb1div = 2 + * - apb1clk = 144000000 + * - pll_ns = 144 + * - pll_ms = 1 + * - pll_fr = 4 + * @param none + * @retval none + */ +void system_clock_config(void) +{ + /* reset crm */ + //crm_reset(); + + /* enable pwc periph clock */ + crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); + + /* config ldo voltage */ + pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3); + + /* set the flash clock divider */ + flash_clock_divider_set(FLASH_CLOCK_DIV_3); + + crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE); + + /* wait till hext is ready */ + while(crm_hext_stable_wait() == ERROR) + { + } + + /* config pll clock resource + common frequency config list: pll source selected hick or hext(8mhz) + _________________________________________________________________________________________________ + | | | | | | | | | | | + |pll(mhz)| 288 | 252 | 216 | 192 | 180 | 144 | 108 | 72 | 36 | + |________|_________|_________|_________|_________|_________|_________|_________|_________________| + | | | | | | | | | | | + |pll_ns | 144 | 126 | 108 | 96 | 90 | 72 | 108 | 72 | 72 | + | | | | | | | | | | | + |pll_ms | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | + | | | | | | | | | | | + |pll_fr | FR_4 | FR_4 | FR_4 | FR_4 | FR_4 | FR_4 | FR_8 | FR_8 | FR_16| + |________|_________|_________|_________|_________|_________|_________|_________|________|________| + + if pll clock source selects hext with other frequency values, or configure pll to other + frequency values, please use the at32 new clock configuration tool for configuration. */ + crm_pll_config(CRM_PLL_SOURCE_HEXT, 144, 1, CRM_PLL_FR_4); + + /* enable pll */ + crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE); + + /* wait till pll is ready */ + while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET) + { + } + + /* config ahbclk */ + crm_ahb_div_set(CRM_AHB_DIV_1); + + /* config apb2clk, the maximum frequency of APB1/APB2 clock is 144 MHz */ + crm_apb2_div_set(CRM_APB2_DIV_2); + + /* config apb1clk, the maximum frequency of APB1/APB2 clock is 144 MHz */ + crm_apb1_div_set(CRM_APB1_DIV_2); + + /* enable auto step mode */ + crm_auto_step_mode_enable(TRUE); + + /* select pll as system clock source */ + crm_sysclk_switch(CRM_SCLK_PLL); + + /* wait till pll is used as system clock source */ + while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL) + { + } + + /* disable auto step mode */ + crm_auto_step_mode_enable(FALSE); + + /* update system_core_clock global variable */ + system_core_clock_update(); +} diff --git a/.platformio/platforms/at32/examples/AT32F437/led_toggle/src/at32f435_437_int.c b/.platformio/platforms/at32/examples/AT32F437/led_toggle/src/at32f435_437_int.c new file mode 100644 index 0000000..dd10c37 --- /dev/null +++ b/.platformio/platforms/at32/examples/AT32F437/led_toggle/src/at32f435_437_int.c @@ -0,0 +1,139 @@ +/** + ************************************************************************** + * @file at32f435_437_int.c + * @brief main interrupt service routines. + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* includes ------------------------------------------------------------------*/ +#include "at32f435_437_int.h" + +/** @addtogroup AT32F437_periph_examples + * @{ + */ + +/** @addtogroup 437_GPIO_led_toggle + * @{ + */ + +/** + * @brief this function handles nmi exception. + * @param none + * @retval none + */ +void NMI_Handler(void) +{ +} + +/** + * @brief this function handles hard fault exception. + * @param none + * @retval none + */ +void HardFault_Handler(void) +{ + /* go to infinite loop when hard fault exception occurs */ + while(1) + { + } +} + +/** + * @brief this function handles memory manage exception. + * @param none + * @retval none + */ +void MemManage_Handler(void) +{ + /* go to infinite loop when memory manage exception occurs */ + while(1) + { + } +} + +/** + * @brief this function handles bus fault exception. + * @param none + * @retval none + */ +void BusFault_Handler(void) +{ + /* go to infinite loop when bus fault exception occurs */ + while(1) + { + } +} + +/** + * @brief this function handles usage fault exception. + * @param none + * @retval none + */ +void UsageFault_Handler(void) +{ + /* go to infinite loop when usage fault exception occurs */ + while(1) + { + } +} + +/** + * @brief this function handles svcall exception. + * @param none + * @retval none + */ +void SVC_Handler(void) +{ +} + +/** + * @brief this function handles debug monitor exception. + * @param none + * @retval none + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief this function handles pendsv_handler exception. + * @param none + * @retval none + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief this function handles systick handler. + * @param none + * @retval none + */ +void SysTick_Handler(void) +{ +} + +/** + * @} + */ + +/** + * @} + */ diff --git a/.platformio/platforms/at32/examples/AT32F437/led_toggle/src/main.c b/.platformio/platforms/at32/examples/AT32F437/led_toggle/src/main.c new file mode 100644 index 0000000..3c1826a --- /dev/null +++ b/.platformio/platforms/at32/examples/AT32F437/led_toggle/src/main.c @@ -0,0 +1,90 @@ +/** + ************************************************************************** + * @file main.c + * @brief main program + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/* includes */ +#include "at32f435_437_clock.h" +#include "delay.h" + +#define LEDPERIPH CRM_GPIOB_PERIPH_CLOCK +#define LEDPORT (GPIOB) +#define LEDPIN (GPIO_PINS_12) + +/** @addtogroup AT32F437_periph_examples + * @{ + */ + +/** @addtogroup 437_GPIO_led_toggle GPIO_led_toggle + * @{ + */ + +/** + * @brief gpio configuration. + * @param none + * @retval none + */ +static void gpio_config(void) +{ + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(LEDPERIPH, TRUE); + + gpio_default_para_init(&gpio_init_struct); + + //configure the led gpio + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_init_struct.gpio_pins = LEDPIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LEDPORT, &gpio_init_struct); +} + +/** + * @brief main function. + * @param none + * @retval none + */ +int main(void) +{ + system_clock_config(); + delay_init(); + + gpio_config(); + + gpio_bits_reset(LEDPORT, LEDPIN); + + for (;;) { + delay_ms(500); + LEDPORT->odt ^= LEDPIN; // toggle pin + } + + return 0; +} + +/** + * @} + */ + +/** + * @} + */ diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/.travis.yml b/.platformio/platforms/at32/examples/cmsis-acd1_dma/.travis.yml deleted file mode 100644 index 7c486f1..0000000 --- a/.platformio/platforms/at32/examples/cmsis-acd1_dma/.travis.yml +++ /dev/null @@ -1,67 +0,0 @@ -# Continuous Integration (CI) is the practice, in software -# engineering, of merging all developer working copies with a shared mainline -# several times a day < https://docs.platformio.org/page/ci/index.html > -# -# Documentation: -# -# * Travis CI Embedded Builds with PlatformIO -# < https://docs.travis-ci.com/user/integration/platformio/ > -# -# * PlatformIO integration with Travis CI -# < https://docs.platformio.org/page/ci/travis.html > -# -# * User Guide for `platformio ci` command -# < https://docs.platformio.org/page/userguide/cmd_ci.html > -# -# -# Please choose one of the following templates (proposed below) and uncomment -# it (remove "# " before each line) or use own configuration according to the -# Travis CI documentation (see above). -# - - -# -# Template #1: General project. Test it using existing `platformio.ini`. -# - -# language: python -# python: -# - "2.7" -# -# sudo: false -# cache: -# directories: -# - "~/.platformio" -# -# install: -# - pip install -U platformio -# - platformio update -# -# script: -# - platformio run - - -# -# Template #2: The project is intended to be used as a library with examples. -# - -# language: python -# python: -# - "2.7" -# -# sudo: false -# cache: -# directories: -# - "~/.platformio" -# -# env: -# - PLATFORMIO_CI_SRC=path/to/test/file.c -# - PLATFORMIO_CI_SRC=examples/file.ino -# - PLATFORMIO_CI_SRC=path/to/test/directory -# -# install: -# - pip install -U platformio -# - platformio update -# -# script: -# - platformio ci --lib="." --board=ID_1 --board=ID_2 --board=ID_N diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/README.rst b/.platformio/platforms/at32/examples/cmsis-acd1_dma/README.rst deleted file mode 100644 index 1890ad5..0000000 --- a/.platformio/platforms/at32/examples/cmsis-acd1_dma/README.rst +++ /dev/null @@ -1,38 +0,0 @@ -.. Copyright 2014-present PlatformIO - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - http://www.apache.org/licenses/LICENSE-2.0 - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. - -How to build PlatformIO based project -===================================== - -1. `Install PlatformIO Core `_ -2. Download `development platform with examples `_ -3. Extract ZIP archive -4. Run these commands: - -.. code-block:: bash - - # Change directory to example - > cd platform-at32/examples/cmsis-blink - - # Build project - > platformio run - - # Upload firmware - > platformio run --target upload - - # Build specific environment - > platformio run -e disco_f407vg - - # Upload firmware for the specific environment - > platformio run -e disco_f407vg --target upload - - # Clean build files - > platformio run --target clean diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/include/README b/.platformio/platforms/at32/examples/cmsis-acd1_dma/include/README deleted file mode 100644 index 194dcd4..0000000 --- a/.platformio/platforms/at32/examples/cmsis-acd1_dma/include/README +++ /dev/null @@ -1,39 +0,0 @@ - -This directory is intended for project header files. - -A header file is a file containing C declarations and macro definitions -to be shared between several project source files. You request the use of a -header file in your project source file (C, C++, etc) located in `src` folder -by including it, with the C preprocessing directive `#include'. - -```src/main.c - -#include "header.h" - -int main (void) -{ - ... -} -``` - -Including a header file produces the same results as copying the header file -into each source file that needs it. Such copying would be time-consuming -and error-prone. With a header file, the related declarations appear -in only one place. If they need to be changed, they can be changed in one -place, and programs that include the header file will automatically use the -new version when next recompiled. The header file eliminates the labor of -finding and changing all the copies as well as the risk that a failure to -find one copy will result in inconsistencies within a program. - -In C, the usual convention is to give header files names that end with `.h'. -It is most portable to use only letters, digits, dashes, and underscores in -header file names, and at most one dot. - -Read more about using header files in official GCC documentation: - -* Include Syntax -* Include Operation -* Once-Only Headers -* Computed Includes - -https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/lib/Delay/delay.c b/.platformio/platforms/at32/examples/cmsis-acd1_dma/lib/Delay/delay.c deleted file mode 100644 index 2324b69..0000000 --- a/.platformio/platforms/at32/examples/cmsis-acd1_dma/lib/Delay/delay.c +++ /dev/null @@ -1,92 +0,0 @@ -#include "delay.h" -#include "stdio.h" - -/*delay macros*/ -#define STEP_DELAY_MS 500 - -/*delay variable*/ -static __IO float fac_us; -static __IO float fac_ms; - - -/** - * @brief initialize Delay function - * @param None - * @retval None - */ -void Delay_init() -{ - /*Config Systick*/ - SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8); - fac_us=(float)SystemCoreClock/(8 * 1000000); - fac_ms=fac_us*1000; -} - -/** - * @brief Inserts a delay time. - * @param nus: specifies the delay time length, in microsecond. - * @retval None - */ -void Delay_us(u32 nus) -{ - u32 temp; - SysTick->LOAD = (u32)(nus*fac_us); - SysTick->VAL = 0x00; - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk ; - do - { - temp = SysTick->CTRL; - }while((temp & 0x01) &&! (temp & (1<<16))); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - SysTick->VAL = 0X00; -} - -/** - * @brief Inserts a delay time. - * @param nms: specifies the delay time length, in milliseconds. - * @retval None - */ -void Delay_ms(u16 nms) -{ - u32 temp; - while(nms) - { - if(nms > STEP_DELAY_MS) - { - SysTick->LOAD = (u32)(STEP_DELAY_MS * fac_ms); - nms -= STEP_DELAY_MS; - } - else - { - SysTick->LOAD = (u32)(nms * fac_ms); - nms = 0; - } - SysTick->VAL = 0x00; - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; - do - { - temp = SysTick->CTRL; - }while( (temp & 0x01) && !(temp & (1<<16)) ); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - SysTick->VAL = 0X00; - } -} - -/** - * @brief Inserts a delay time. - * @param sec: specifies the delay time length, in seconds. - * @retval None - */ -void Delay_sec(u16 sec) -{ - u16 i; - for(i=0; i 0U) - { - len--; - while ( USART_GetFlagStatus(AT32_PRINT_UART, USART_FLAG_TRAC) == RESET ); - AT32_PRINT_UART->DT = (buff[i++] & (uint16_t)0x01FF); - } - while ( USART_GetFlagStatus(AT32_PRINT_UART, USART_FLAG_TRAC) == RESET ); -} - -/** - * @brief initialize UART1 - * @param bound: UART BaudRate - * @retval None - */ -void UART_Print_Init(uint32_t bound) -{ - GPIO_InitType GPIO_InitStructure; - USART_InitType USART_InitStructure; - - /*Enable the UART Clock*/ - RCC_APB2PeriphClockCmd(AT32_PRINT_UARTTX_GPIO_RCC | AT32_PRINT_UARTRX_GPIO_RCC, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_USART1, ENABLE); - - /* Configure the UART1 TX pin */ - GPIO_StructInit(&GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pins = AT32_PRINT_UARTTX_PIN; - GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; - GPIO_Init(AT32_PRINT_UARTTX_GPIO, &GPIO_InitStructure); - - /* Configure the UART1 RX pin */ - GPIO_InitStructure.GPIO_Pins = AT32_PRINT_UARTRX_PIN;//PA10 - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(AT32_PRINT_UARTRX_GPIO, &GPIO_InitStructure); - - /*Configure UART param*/ - USART_StructInit(&USART_InitStructure); - USART_InitStructure.USART_BaudRate = bound; - USART_InitStructure.USART_WordLength = USART_WordLength_8b; - USART_InitStructure.USART_StopBits = USART_StopBits_1; - USART_InitStructure.USART_Parity = USART_Parity_No; - USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - - USART_Init(AT32_PRINT_UART, &USART_InitStructure); - USART_INTConfig(AT32_PRINT_UART, USART_INT_RDNE, ENABLE); - USART_Cmd(AT32_PRINT_UART, ENABLE); -} - -/** - * @brief Main program - * @param None - * @retval None - */ -int main(void) -{ - /* System clocks configuration */ - RCC_Configuration(); - - /* GPIO configuration ------------------------------------------------------*/ - GPIO_Configuration(); - - /* UART configuration ------------------------------------------------------*/ - UART_Print_Init(115200); - UART_Print_sendData("ADC Test", 8); - - /* DMA1 channel1 configuration ----------------------------------------------*/ - DMA_Reset(DMA1_Channel1); - DMA_DefaultInitParaConfig(&DMA_InitStructure); - DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&ADC1->RDOR; - DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&ADCConvertedValue; - DMA_InitStructure.DMA_Direction = DMA_DIR_PERIPHERALSRC; - DMA_InitStructure.DMA_BufferSize = 1; - DMA_InitStructure.DMA_PeripheralInc = DMA_PERIPHERALINC_DISABLE; - DMA_InitStructure.DMA_MemoryInc = DMA_MEMORYINC_DISABLE; - DMA_InitStructure.DMA_PeripheralDataWidth = DMA_PERIPHERALDATAWIDTH_HALFWORD; - DMA_InitStructure.DMA_MemoryDataWidth = DMA_MEMORYDATAWIDTH_HALFWORD; - DMA_InitStructure.DMA_Mode = DMA_MODE_CIRCULAR; - DMA_InitStructure.DMA_Priority = DMA_PRIORITY_HIGH; - DMA_InitStructure.DMA_MTOM = DMA_MEMTOMEM_DISABLE; - DMA_Init(DMA1_Channel1, &DMA_InitStructure); - /* Enable DMA1 channel1 */ - DMA_ChannelEnable(DMA1_Channel1, ENABLE); - - /* ADC1 configuration ------------------------------------------------------*/ - ADC_StructInit(&ADC_InitStructure); - ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; - ADC_InitStructure.ADC_ScanMode = DISABLE; - ADC_InitStructure.ADC_ContinuousMode = ENABLE; - ADC_InitStructure.ADC_ExternalTrig = ADC_ExternalTrig_None; - ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; - ADC_InitStructure.ADC_NumOfChannel = 1; - ADC_Init(ADC1, &ADC_InitStructure); - - /* ADC1 regular channels configuration */ - ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_28_5); - - /* Enable ADC1 DMA */ - ADC_DMACtrl(ADC1, ENABLE); - - /* Enable ADC1 */ - ADC_Ctrl(ADC1, ENABLE); - - /* Enable ADC1 reset calibration register */ - ADC_RstCalibration(ADC1); - /* Check the end of ADC1 reset calibration register */ - while(ADC_GetResetCalibrationStatus(ADC1)); - - /* Start ADC1 calibration */ - ADC_StartCalibration(ADC1); - /* Check the end of ADC1 calibration */ - while(ADC_GetCalibrationStatus(ADC1)); - - /* Start ADC1 Software Conversion */ - ADC_SoftwareStartConvCtrl(ADC1, ENABLE); - - while (1) - { - - } -} - -/** - * @brief Configures the different system clocks. - * @param None - * @retval None - */ -void RCC_Configuration(void) -{ - /* ADCCLK = PCLK2/6 */ - RCC_ADCCLKConfig(RCC_APB2CLK_Div6); - - /* Enable peripheral clocks ------------------------------------------------*/ - /* Enable DMA1 clocks */ - RCC_AHBPeriphClockCmd(RCC_AHBPERIPH_DMA1, ENABLE); - - /* Enable ADC1 and GPIOC clocks */ - RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC1 | RCC_APB2PERIPH_GPIOC, ENABLE); -} - -/** - * @brief Configures the different GPIO ports. - * @param None - * @retval None - */ -void GPIO_Configuration(void) -{ - GPIO_InitType GPIO_InitStructure; - - /* Configure PC.04 (ADC Channel14) as analog input -------------------------*/ - GPIO_StructInit(&GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_ANALOG; - GPIO_Init(GPIOC, &GPIO_InitStructure); -} - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/ diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/src/main.h b/.platformio/platforms/at32/examples/cmsis-acd1_dma/src/main.h deleted file mode 100644 index 5a3e9ac..0000000 --- a/.platformio/platforms/at32/examples/cmsis-acd1_dma/src/main.h +++ /dev/null @@ -1,28 +0,0 @@ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MAIN_H -#define __MAIN_H - - -/**************** UART printf ****************/ -#define AT32_PRINT_UART USART1 -#define USARTx_IRQn USART1_IRQn -#define USARTx_IRQ_Handler USART1_IRQHandler -#define AT32_PRINT_UART_RCC RCC_APB2PERIPH_USART1 - -/*Tx*/ -#define AT32_PRINT_UARTTX_PIN GPIO_Pins_9 -#define AT32_PRINT_UARTTX_GPIO GPIOA -#define AT32_PRINT_UARTTX_GPIO_RCC RCC_APB2PERIPH_GPIOA - -/*Rx*/ -#define AT32_PRINT_UARTRX_PIN GPIO_Pins_10 -#define AT32_PRINT_UARTRX_GPIO GPIOA -#define AT32_PRINT_UARTRX_GPIO_RCC RCC_APB2PERIPH_GPIOA -/**************** End UART printf ****************/ - -void AT32_Board_Init(void); -void AT32_USB_GPIO_init(void); - -#endif /* __MAIN_H */ - - diff --git a/.platformio/platforms/at32/examples/cmsis-acd1_dma/src/system_at32f4xx.c b/.platformio/platforms/at32/examples/cmsis-acd1_dma/src/system_at32f4xx.c deleted file mode 100644 index b73ff8c..0000000 --- a/.platformio/platforms/at32/examples/cmsis-acd1_dma/src/system_at32f4xx.c +++ /dev/null @@ -1,3473 +0,0 @@ -/** - ****************************************************************************** - * File : system_at32f4xx.c - * Version: V1.2.2 - * Date : 2020-07-01 - * Brief : CMSIS Cortex-M4 system source file - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup at32f4xx_system - * @{ - */ - -/** @addtogroup at32f4xx_System_Private_Includes - * @{ - */ - -#include "at32f4xx.h" - -/** - * @} - */ - -/** @addtogroup at32f4xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup at32f4xx_System_Private_Defines - * @{ - */ - -/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) - frequency (after reset the HSI is used as SYSCLK source) - - IMPORTANT NOTE: - ============== - 1. After each device reset the HSI is used as System clock source. - - 2. Please make sure that the selected System clock doesn't exceed your device's - maximum frequency. - - 3. If none of the define below is enabled, the HSI is used as System clock - source. - - 4. The System clock configuration functions provided within this file assume that: - - For at32f4xx devices, an external 8MHz crystal is used to drive the System clock. - If you are using different crystal you have to adapt those functions accordingly. - - Clock (MHz) - PLL from HSE or HSI - SYSCLK HCLK PCLK2 PCLK1 - 24 24 24 24 - 36 36 36 36 - 48 48 48 24 - 56 56 56 28 - 72 72 72 36 - 96 96 48 48 - 108 108 54 54 - 120 120 60 60 - 144 144 72 72 - 150 150 75 75 - 168 168 84 84 - 176 176 88 88 - 192 192 96 96 - 200 200 100 100 - 224 224 112 112 - 240 240 120 120 - */ - -#if defined (AT32F403xx) || defined (AT32F413xx) || \ - defined (AT32F415xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) -/* #define SYSCLK_FREQ_HSE HSE_VALUE */ -/* #define SYSCLK_FREQ_24MHz 24000000 */ -/* #define SYSCLK_FREQ_36MHz 36000000 */ -/* #define SYSCLK_FREQ_48MHz 48000000 */ -/* #define SYSCLK_FREQ_56MHz 56000000 */ -#define SYSCLK_FREQ_72MHz 72000000 -/* #define SYSCLK_FREQ_96MHz 96000000 */ -/* #define SYSCLK_FREQ_108MHz 108000000 */ -/* #define SYSCLK_FREQ_120MHz 120000000 */ -/* #define SYSCLK_FREQ_144MHz 144000000 */ -/* #define SYSCLK_FREQ_24MHz_HSI 24000000 */ -/* #define SYSCLK_FREQ_36MHz_HSI 36000000 */ -/* #define SYSCLK_FREQ_48MHz_HSI 48000000 */ -/* #define SYSCLK_FREQ_56MHz_HSI 56000000 */ -/* #define SYSCLK_FREQ_72MHz_HSI 72000000 */ -/* #define SYSCLK_FREQ_96MHz_HSI 96000000 */ -/* #define SYSCLK_FREQ_108MHz_HSI 108000000 */ -/* #define SYSCLK_FREQ_120MHz_HSI 120000000 */ -/* #define SYSCLK_FREQ_144MHz_HSI 144000000 */ -#endif - -#if defined (AT32F415xx) -/* #define SYSCLK_FREQ_150MHz 150000000 */ -/* #define SYSCLK_FREQ_150MHz_HSI 150000000 */ -#endif - -#if defined (AT32F403xx) || defined (AT32F413xx) || \ - defined (AT32F403Axx)|| defined (AT32F407xx) -/* #define SYSCLK_FREQ_168MHz 168000000 */ -/* #define SYSCLK_FREQ_176MHz 176000000 */ -/* #define SYSCLK_FREQ_192MHz 192000000 */ -/* #define SYSCLK_FREQ_200MHz 200000000 */ -/* #define SYSCLK_FREQ_168MHz_HSI 168000000 */ -/* #define SYSCLK_FREQ_176MHz_HSI 176000000 */ -/* #define SYSCLK_FREQ_192MHz_HSI 192000000 */ -/* #define SYSCLK_FREQ_200MHz_HSI 200000000 */ -#endif - -#if defined (AT32F403Axx)|| defined (AT32F407xx) -/* #define SYSCLK_FREQ_224MHz 224000000 */ -/* #define SYSCLK_FREQ_240MHz 240000000 */ -/* #define SYSCLK_FREQ_224MHz_HSI 224000000 */ -/* #define SYSCLK_FREQ_240MHz_HSI 240000000 */ -#endif - -/*!< Uncomment the following line if you need to use external SRAM mounted - (AT32 High density and XL-density devices) as data memory */ - -/* #define DATA_IN_ExtSRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. -This value must be a multiple of 0x200. */ - - -/** - * @} - */ - -/** @addtogroup at32f4xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup at32f4xx_System_Private_Variables - * @{ - */ - -/******************************************************************************* -* Clock Definitions -*******************************************************************************/ -#ifdef SYSCLK_FREQ_HSE -uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz -uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_36MHz -uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz -uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz -uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz -uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_96MHz -uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_108MHz -uint32_t SystemCoreClock = SYSCLK_FREQ_108MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_120MHz -uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_144MHz -uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_150MHz -uint32_t SystemCoreClock = SYSCLK_FREQ_150MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_168MHz -uint32_t SystemCoreClock = SYSCLK_FREQ_168MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_176MHz -uint32_t SystemCoreClock = SYSCLK_FREQ_176MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_192MHz -uint32_t SystemCoreClock = SYSCLK_FREQ_192MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_200MHz -uint32_t SystemCoreClock = SYSCLK_FREQ_200MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_224MHz -uint32_t SystemCoreClock = SYSCLK_FREQ_224MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_240MHz -uint32_t SystemCoreClock = SYSCLK_FREQ_240MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSI; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_36MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz_HSI; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_96MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_108MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_108MHz_HSI; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_120MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_144MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_150MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_150MHz_HSI; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_168MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_168MHz_HSI; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_176MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_176MHz_HSI; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_192MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_192MHz_HSI; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_200MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_200MHz_HSI; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_224MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_224MHz_HSI; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_240MHz_HSI -uint32_t SystemCoreClock = SYSCLK_FREQ_240MHz_HSI; /*!< System Clock Frequency (Core Clock) */ -#else /*!< HSI Selected as System Clock source */ -#define SYSCLK_FREQ_HSI HSI_VALUE -uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ -#endif - -__I uint8_t AHBPscTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -/** - * @} - */ - -/** @addtogroup at32f4xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); - -#ifdef SYSCLK_FREQ_HSE -static void SetSysClockToHSE(void); -#elif defined SYSCLK_FREQ_24MHz -static void SetSysClockTo24M(void); -#elif defined SYSCLK_FREQ_36MHz -static void SetSysClockTo36M(void); -#elif defined SYSCLK_FREQ_48MHz -static void SetSysClockTo48M(void); -#elif defined SYSCLK_FREQ_56MHz -static void SetSysClockTo56M(void); -#elif defined SYSCLK_FREQ_72MHz -static void SetSysClockTo72M(void); -#elif defined SYSCLK_FREQ_96MHz -static void SetSysClockTo96M(void); -#elif defined SYSCLK_FREQ_108MHz -static void SetSysClockTo108M(void); -#elif defined SYSCLK_FREQ_120MHz -static void SetSysClockTo120M(void); -#elif defined SYSCLK_FREQ_144MHz -static void SetSysClockTo144M(void); -#elif defined SYSCLK_FREQ_150MHz -static void SetSysClockTo150M(void); -#elif defined SYSCLK_FREQ_168MHz -static void SetSysClockTo168M(void); -#elif defined SYSCLK_FREQ_176MHz -static void SetSysClockTo176M(void); -#elif defined SYSCLK_FREQ_192MHz -static void SetSysClockTo192M(void); -#elif defined SYSCLK_FREQ_200MHz -static void SetSysClockTo200M(void); -#elif defined SYSCLK_FREQ_224MHz -static void SetSysClockTo224M(void); -#elif defined SYSCLK_FREQ_240MHz -static void SetSysClockTo240M(void); -#elif defined SYSCLK_FREQ_24MHz_HSI -static void SetSysClockTo24MHSI(void); -#elif defined SYSCLK_FREQ_36MHz_HSI -static void SetSysClockTo36MHSI(void); -#elif defined SYSCLK_FREQ_48MHz_HSI -static void SetSysClockTo48MHSI(void); -#elif defined SYSCLK_FREQ_56MHz_HSI -static void SetSysClockTo56MHSI(void); -#elif defined SYSCLK_FREQ_72MHz_HSI -static void SetSysClockTo72MHSI(void); -#elif defined SYSCLK_FREQ_96MHz_HSI -static void SetSysClockTo96MHSI(void); -#elif defined SYSCLK_FREQ_108MHz_HSI -static void SetSysClockTo108MHSI(void); -#elif defined SYSCLK_FREQ_120MHz_HSI -static void SetSysClockTo120MHSI(void); -#elif defined SYSCLK_FREQ_144MHz_HSI -static void SetSysClockTo144MHSI(void); -#elif defined SYSCLK_FREQ_150MHz_HSI -static void SetSysClockTo150MHSI(void); -#elif defined SYSCLK_FREQ_168MHz_HSI -static void SetSysClockTo168MHSI(void); -#elif defined SYSCLK_FREQ_176MHz_HSI -static void SetSysClockTo176MHSI(void); -#elif defined SYSCLK_FREQ_192MHz_HSI -static void SetSysClockTo192MHSI(void); -#elif defined SYSCLK_FREQ_200MHz_HSI -static void SetSysClockTo200MHSI(void); -#elif defined SYSCLK_FREQ_224MHz_HSI -static void SetSysClockTo224MHSI(void); -#elif defined SYSCLK_FREQ_240MHz_HSI -static void SetSysClockTo240MHSI(void); -#endif - -#ifdef DATA_IN_ExtSRAM -static void SystemInit_ExtMemCtrl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup at32f4xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -void SystemInit (void) -{ -#if defined (AT32F415xx) - /* Enable low power mode, 0x40007050[bit2] */ - RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_PWR, ENABLE); - *(volatile uint8_t *)(0x40007050) |= (uint8_t)(0x1 << 2); - RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_PWR, DISABLE); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U * 2U) | /* set CP10 Full Access */ - (3U << 11U * 2U) ); /* set CP11 Full Access */ -#endif - - /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ - /* Set HSIEN bit */ - BIT_SET(RCC->CTRL, RCC_CTRL_HSIEN); - - /* Reset SW, AHBPSC, APB1PSC, APB2PSC, ADCPSC and CLKOUT bits */ - BIT_CLEAR(RCC->CFG, RCC_CFG_SYSCLKSEL | RCC_CFG_AHBPSC | \ - RCC_CFG_APB1PSC | RCC_CFG_APB2PSC | \ - RCC_CFG_ADCPSC | RCC_CFG_CLKOUT); - - /* Reset HSEEN, HSECFDEN and PLLEN bits */ - BIT_CLEAR(RCC->CTRL, RCC_CTRL_HSEEN | RCC_CTRL_HSECFDEN | \ - RCC_CTRL_PLLEN); - - /* Reset HSEBYPS bit */ - BIT_CLEAR(RCC->CTRL, RCC_CTRL_HSEBYPS); - - /* Reset PLLRC, PLLHSEPSC, PLLMUL, USBPSC and PLLRANGE bits */ - BIT_CLEAR(RCC->CFG, RCC_CFG_PLLRC | RCC_CFG_PLLHSEPSC | \ - RCC_CFG_PLLMULT | RCC_CFG_USBPSC | RCC_CFG_PLLRANGE); - - /* Reset USB768B, CLKOUT[3], HSICAL_KEY[7:0] */ - BIT_CLEAR(RCC->MISC, 0x010100FF); - - /* Disable all interrupts and clear pending bits */ - RCC->CLKINT = RCC_CLKINT_LSISTBLFC | RCC_CLKINT_LSESTBLFC | \ - RCC_CLKINT_HSISTBLFC | RCC_CLKINT_HSESTBLFC | \ - RCC_CLKINT_PLLSTBLFC | RCC_CLKINT_HSECFDFC; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtrl(); -#endif /* DATA_IN_ExtSRAM */ - - /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ - /* Configure the Flash Latency cycles and enable prefetch buffer */ - SetSysClock(); - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in at32f4xx.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in at32f4xx.h file (default value - * 8 MHz or 25 MHz, depedning on the product used), user has to ensure - * that HSE_VALUE is same as the real frequency of the crystal used. - * Otherwise, this function may have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmult = 0, pllrefclk = 0, tempcfg = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFG & RCC_CFG_SYSCLKSTS; - - switch (tmp) - { - case RCC_CFG_SYSCLKSTS_HSI: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - - case RCC_CFG_SYSCLKSTS_HSE: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - - case RCC_CFG_SYSCLKSTS_PLL: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllrefclk = RCC->CFG & RCC_CFG_PLLRC; - tempcfg = RCC->CFG; - pllmult = RCC_GET_PLLMULT(tempcfg); - - if (pllrefclk == RCC_PLLRefClk_HSI_Div2) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmult; - } - else - { - /* HSE selected as PLL clock entry */ - if ((RCC->CFG & RCC_CFG_PLLHSEPSC) != (uint32_t)RESET) - { - /* HSE oscillator clock divided by 2 */ - SystemCoreClock = (HSE_VALUE >> 1) * pllmult; - } - else - { - SystemCoreClock = HSE_VALUE * pllmult; - } - } - - break; - - default: - SystemCoreClock = HSI_VALUE; - break; - } - - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPscTable[((RCC->CFG & RCC_CFG_AHBPSC) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -#ifdef SYSCLK_FREQ_HSE - SetSysClockToHSE(); -#elif defined SYSCLK_FREQ_24MHz - SetSysClockTo24M(); -#elif defined SYSCLK_FREQ_36MHz - SetSysClockTo36M(); -#elif defined SYSCLK_FREQ_48MHz - SetSysClockTo48M(); -#elif defined SYSCLK_FREQ_56MHz - SetSysClockTo56M(); -#elif defined SYSCLK_FREQ_72MHz - SetSysClockTo72M(); -#elif defined SYSCLK_FREQ_96MHz - SetSysClockTo96M(); -#elif defined SYSCLK_FREQ_108MHz - SetSysClockTo108M(); -#elif defined SYSCLK_FREQ_120MHz - SetSysClockTo120M(); -#elif defined SYSCLK_FREQ_144MHz - SetSysClockTo144M(); -#elif defined SYSCLK_FREQ_150MHz - SetSysClockTo150M(); -#elif defined SYSCLK_FREQ_168MHz - SetSysClockTo168M(); -#elif defined SYSCLK_FREQ_176MHz - SetSysClockTo176M(); -#elif defined SYSCLK_FREQ_192MHz - SetSysClockTo192M(); -#elif defined SYSCLK_FREQ_200MHz - SetSysClockTo200M(); -#elif defined SYSCLK_FREQ_224MHz - SetSysClockTo224M(); -#elif defined SYSCLK_FREQ_240MHz - SetSysClockTo240M(); -#elif defined SYSCLK_FREQ_24MHz_HSI - SetSysClockTo24MHSI(); -#elif defined SYSCLK_FREQ_36MHz_HSI - SetSysClockTo36MHSI(); -#elif defined SYSCLK_FREQ_48MHz_HSI - SetSysClockTo48MHSI(); -#elif defined SYSCLK_FREQ_56MHz_HSI - SetSysClockTo56MHSI(); -#elif defined SYSCLK_FREQ_72MHz_HSI - SetSysClockTo72MHSI(); -#elif defined SYSCLK_FREQ_96MHz_HSI - SetSysClockTo96MHSI(); -#elif defined SYSCLK_FREQ_108MHz_HSI - SetSysClockTo108MHSI(); -#elif defined SYSCLK_FREQ_120MHz_HSI - SetSysClockTo120MHSI(); -#elif defined SYSCLK_FREQ_144MHz_HSI - SetSysClockTo144MHSI(); -#elif defined SYSCLK_FREQ_150MHz_HSI - SetSysClockTo150MHSI(); -#elif defined SYSCLK_FREQ_168MHz_HSI - SetSysClockTo168MHSI(); -#elif defined SYSCLK_FREQ_176MHz_HSI - SetSysClockTo176MHSI(); -#elif defined SYSCLK_FREQ_192MHz_HSI - SetSysClockTo192MHSI(); -#elif defined SYSCLK_FREQ_200MHz_HSI - SetSysClockTo200MHSI(); -#elif defined SYSCLK_FREQ_224MHz_HSI - SetSysClockTo224MHSI(); -#elif defined SYSCLK_FREQ_240MHz_HSI - SetSysClockTo240MHSI(); -#endif - - /* If none of the define above is enabled, the HSI is used as System clock - source (default after reset) */ -} - -/** - * @brief Setup the external memory controller. Called in startup_at32f4xx.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_at32f4xx_xx.s/.c before jump to main. - * This function configures the external SRAM mounted - * (AT32 High density devices). This SRAM will be used as program - * data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtrl(void) -{ - /* Enable XMC clock */ - RCC->AHBEN = RCC_AHBEN_SRAMEN | RCC_AHBEN_FLASHEN | RCC_AHBEN_XMCEN; - - /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ - RCC->APB2EN = RCC_APB2EN_GPIODEN | RCC_APB2EN_GPIOEEN | RCC_APB2EN_GPIOFEN | RCC_APB2EN_GPIOGEN; - - /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ - /*---------------- SRAM Address lines configuration -------------------------*/ - /*---------------- NOE and NWE configuration --------------------------------*/ - /*---------------- NE3 configuration ----------------------------------------*/ - /*---------------- NBL0, NBL1 configuration ---------------------------------*/ - - GPIOD->CTRLL = 0x44BB44BB; - GPIOD->CTRLH = 0xBBBBBBBB; - - GPIOE->CTRLL = 0xB44444BB; - GPIOE->CTRLH = 0xBBBBBBBB; - - GPIOF->CTRLL = 0x44BBBBBB; - GPIOF->CTRLH = 0xBBBB4444; - - GPIOG->CTRLL = 0x44BBBBBB; - GPIOG->CTRLH = 0x44444B44; - - /*---------------- XMC Configuration ---------------------------------------*/ - /*---------------- Enable XMC Bank1_SRAM Bank ------------------------------*/ - - XMC_Bank1->BK1CTRLR[4] = 0x00001011; - XMC_Bank1->BK1CTRLR[5] = 0x00000200; -} -#endif /* DATA_IN_ExtSRAM */ - -#ifndef SYSCLK_FREQ_HSI -#ifdef AT32F403xx -/** - * @brief Delay to wait for HSE stable. - * @note This function should be used before reading the HSESTBL flag. - * @param None - * @retval None - */ -static void WaitHseStbl(uint32_t delay) -{ - uint32_t i; - - for(i = 0; i < delay; i++) - ; -} -#endif -#endif /* SYSCLK_FREQ_HSI */ - -#ifdef SYSCLK_FREQ_HSE -/** - * @brief Selects HSE as System clock source and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockToHSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1; - - /* Select HSE as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_HSE; - - /* Wait till HSE is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != (uint32_t)0x04) - { - } - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_24MHz -/** - * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo24M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1; - - /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT6); -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_36MHz -/** - * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo36M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1; - - /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT9); -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_48MHz -/** - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo48M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT6); -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_56MHz -/** - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo56M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT7); -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_72MHz -/** - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo72M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT9); -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_96MHz -/** - * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo96M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; -#if defined (AT32F415xx) - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT12); -#else - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT12 | RCC_CFG_PLLRANGE_GT72MHZ); -#endif -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_108MHz -/** - * @brief Sets System clock frequency to 108MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo108M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSE/2) * 27 = 108 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - -#if defined (AT32F415xx) - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT27); -#else - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT27 \ - | RCC_CFG_PLLRANGE_GT72MHZ); -#endif -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_120MHz -/** - * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo120M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - -#if defined (AT32F415xx) - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT15); -#else - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT15 | RCC_CFG_PLLRANGE_GT72MHZ); -#endif -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_144MHz -/** - * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo144M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - -#if defined (AT32F415xx) - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18); -#else - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18 | RCC_CFG_PLLRANGE_GT72MHZ); -#endif -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_150MHz -/** - * @brief Sets System clock frequency to 150MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo150M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSE * 75) / (1 * 4) = 150 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE); - RCC_PLLconfig2(PLL_FREF_8M, 75, 1, PLL_FR_4); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_168MHz -/** - * @brief Sets System clock frequency to 168MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo168M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 21 = 168 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT21 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_176MHz -/** - * @brief Sets System clock frequency to 176MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo176M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 22 = 176 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT22 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_192MHz -/** - * @brief Sets System clock frequency to 192MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo192M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 24 = 192 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT24 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_200MHz -/** - * @brief Sets System clock frequency to 200MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo200M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 25 = 200 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT25 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_224MHz -/** - * @brief Sets System clock frequency to 224MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo224M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 28 = 224 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT28 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_240MHz -/** - * @brief Sets System clock frequency to 240MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo240M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 30 = 240 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT30 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_24MHz_HSI -/** - * @brief Sets System clock frequency to 24MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo24MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1; - - /* PLL configuration: PLLCLK = (HSI/2) * 6 = 24 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT6); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } -} - -#elif defined SYSCLK_FREQ_36MHz_HSI -/** - * @brief Sets System clock frequency to 36MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo36MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1; - - /* PLL configuration: PLLCLK = (HSI/2) * 9 = 36 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT9); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } -} - -#elif defined SYSCLK_FREQ_48MHz_HSI -/** - * @brief Sets System clock frequency to 48MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo48MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 12 = 48 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT12); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } -} - -#elif defined SYSCLK_FREQ_56MHz_HSI -/** - * @brief Sets System clock frequency to 56MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo56MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 14 = 56 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT14); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } -} - -#elif defined SYSCLK_FREQ_72MHz_HSI -/** - * @brief Sets System clock frequency to 72MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo72MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 18 = 72 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT18); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } -} - -#elif defined SYSCLK_FREQ_96MHz_HSI -/** - * @brief Sets System clock frequency to 96MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo96MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 24 = 96 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - -#if defined (AT32F415xx) - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT24); -#else - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT24 | RCC_CFG_PLLRANGE_GT72MHZ); -#endif - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } -} - -#elif defined SYSCLK_FREQ_108MHz_HSI -/** - * @brief Sets System clock frequency to 108MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo108MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 27 = 108 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - -#if defined (AT32F415xx) - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT27); -#else - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT27 | RCC_CFG_PLLRANGE_GT72MHZ); -#endif - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } -} - -#elif defined SYSCLK_FREQ_120MHz_HSI -/** - * @brief Sets System clock frequency to 120MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo120MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 30 = 120 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - -#if defined (AT32F415xx) - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT30); -#else - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT30 | RCC_CFG_PLLRANGE_GT72MHZ); -#endif - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} - -#elif defined SYSCLK_FREQ_144MHz_HSI -/** - * @brief Sets System clock frequency to 144MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo144MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 36 = 144 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - -#if defined (AT32F415xx) - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT36); -#else - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT36 | RCC_CFG_PLLRANGE_GT72MHZ); -#endif - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} - -#elif defined SYSCLK_FREQ_150MHz_HSI -/** - * @brief Sets System clock frequency to 150MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo150MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = ((HSI/2) * 150) / (1 * 4) = 150 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2); - RCC_PLLconfig2(PLL_FREF_4M, 150, 1, PLL_FR_4); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} - -#elif defined SYSCLK_FREQ_168MHz_HSI -/** - * @brief Sets System clock frequency to 168MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo168MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 42 = 168 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT42 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} -#elif defined SYSCLK_FREQ_176MHz_HSI -/** - * @brief Sets System clock frequency to 176MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo176MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 44 = 176 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT44 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} -#elif defined SYSCLK_FREQ_192MHz_HSI -/** - * @brief Sets System clock frequency to 192MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo192MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 48 = 192 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT48 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} -#elif defined SYSCLK_FREQ_200MHz_HSI -/** - * @brief Sets System clock frequency to 200MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo200MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 50 = 200 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT50 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} - -#elif defined SYSCLK_FREQ_224MHz_HSI -/** - * @brief Sets System clock frequency to 224MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo224MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 56 = 224 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT56 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} - -#elif defined SYSCLK_FREQ_240MHz_HSI -/** - * @brief Sets System clock frequency to 240MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo240MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 60 = 240 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT60 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} - -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/ diff --git a/.platformio/platforms/at32/examples/cmsis-blink/.gitignore b/.platformio/platforms/at32/examples/cmsis-blink/.gitignore deleted file mode 100644 index 3b8da3a..0000000 --- a/.platformio/platforms/at32/examples/cmsis-blink/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -.pio -.vscode \ No newline at end of file diff --git a/.platformio/platforms/at32/examples/cmsis-blink/.travis.yml b/.platformio/platforms/at32/examples/cmsis-blink/.travis.yml deleted file mode 100644 index 7c486f1..0000000 --- a/.platformio/platforms/at32/examples/cmsis-blink/.travis.yml +++ /dev/null @@ -1,67 +0,0 @@ -# Continuous Integration (CI) is the practice, in software -# engineering, of merging all developer working copies with a shared mainline -# several times a day < https://docs.platformio.org/page/ci/index.html > -# -# Documentation: -# -# * Travis CI Embedded Builds with PlatformIO -# < https://docs.travis-ci.com/user/integration/platformio/ > -# -# * PlatformIO integration with Travis CI -# < https://docs.platformio.org/page/ci/travis.html > -# -# * User Guide for `platformio ci` command -# < https://docs.platformio.org/page/userguide/cmd_ci.html > -# -# -# Please choose one of the following templates (proposed below) and uncomment -# it (remove "# " before each line) or use own configuration according to the -# Travis CI documentation (see above). -# - - -# -# Template #1: General project. Test it using existing `platformio.ini`. -# - -# language: python -# python: -# - "2.7" -# -# sudo: false -# cache: -# directories: -# - "~/.platformio" -# -# install: -# - pip install -U platformio -# - platformio update -# -# script: -# - platformio run - - -# -# Template #2: The project is intended to be used as a library with examples. -# - -# language: python -# python: -# - "2.7" -# -# sudo: false -# cache: -# directories: -# - "~/.platformio" -# -# env: -# - PLATFORMIO_CI_SRC=path/to/test/file.c -# - PLATFORMIO_CI_SRC=examples/file.ino -# - PLATFORMIO_CI_SRC=path/to/test/directory -# -# install: -# - pip install -U platformio -# - platformio update -# -# script: -# - platformio ci --lib="." --board=ID_1 --board=ID_2 --board=ID_N diff --git a/.platformio/platforms/at32/examples/cmsis-blink/README.rst b/.platformio/platforms/at32/examples/cmsis-blink/README.rst deleted file mode 100644 index 1890ad5..0000000 --- a/.platformio/platforms/at32/examples/cmsis-blink/README.rst +++ /dev/null @@ -1,38 +0,0 @@ -.. Copyright 2014-present PlatformIO - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - http://www.apache.org/licenses/LICENSE-2.0 - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. - -How to build PlatformIO based project -===================================== - -1. `Install PlatformIO Core `_ -2. Download `development platform with examples `_ -3. Extract ZIP archive -4. Run these commands: - -.. code-block:: bash - - # Change directory to example - > cd platform-at32/examples/cmsis-blink - - # Build project - > platformio run - - # Upload firmware - > platformio run --target upload - - # Build specific environment - > platformio run -e disco_f407vg - - # Upload firmware for the specific environment - > platformio run -e disco_f407vg --target upload - - # Clean build files - > platformio run --target clean diff --git a/.platformio/platforms/at32/examples/cmsis-blink/include/README b/.platformio/platforms/at32/examples/cmsis-blink/include/README deleted file mode 100644 index 194dcd4..0000000 --- a/.platformio/platforms/at32/examples/cmsis-blink/include/README +++ /dev/null @@ -1,39 +0,0 @@ - -This directory is intended for project header files. - -A header file is a file containing C declarations and macro definitions -to be shared between several project source files. You request the use of a -header file in your project source file (C, C++, etc) located in `src` folder -by including it, with the C preprocessing directive `#include'. - -```src/main.c - -#include "header.h" - -int main (void) -{ - ... -} -``` - -Including a header file produces the same results as copying the header file -into each source file that needs it. Such copying would be time-consuming -and error-prone. With a header file, the related declarations appear -in only one place. If they need to be changed, they can be changed in one -place, and programs that include the header file will automatically use the -new version when next recompiled. The header file eliminates the labor of -finding and changing all the copies as well as the risk that a failure to -find one copy will result in inconsistencies within a program. - -In C, the usual convention is to give header files names that end with `.h'. -It is most portable to use only letters, digits, dashes, and underscores in -header file names, and at most one dot. - -Read more about using header files in official GCC documentation: - -* Include Syntax -* Include Operation -* Once-Only Headers -* Computed Includes - -https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html diff --git a/.platformio/platforms/at32/examples/cmsis-blink/lib/Delay/delay.c b/.platformio/platforms/at32/examples/cmsis-blink/lib/Delay/delay.c deleted file mode 100644 index f7da62c..0000000 --- a/.platformio/platforms/at32/examples/cmsis-blink/lib/Delay/delay.c +++ /dev/null @@ -1,94 +0,0 @@ -/*DO NOT USE - DON'T WORK*/ - -#include "delay.h" -#include "stdio.h" - -/*delay macros*/ -#define STEP_DELAY_MS 500 - -/*delay variable*/ -static __IO float fac_us; -static __IO float fac_ms; - - -/** - * @brief initialize Delay function - * @param None - * @retval None - */ -void Delay_init() -{ - /*Config Systick*/ - SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8); - fac_us=(float)SystemCoreClock/(8 * 1000000); - fac_ms=fac_us*1000; -} - -/** - * @brief Inserts a delay time. - * @param nus: specifies the delay time length, in microsecond. - * @retval None - */ -void Delay_us(u32 nus) -{ - u32 temp; - SysTick->LOAD = (u32)(nus*fac_us); - SysTick->VAL = 0x00; - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk ; - do - { - temp = SysTick->CTRL; - }while((temp & 0x01) &&! (temp & (1<<16))); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - SysTick->VAL = 0X00; -} - -/** - * @brief Inserts a delay time. - * @param nms: specifies the delay time length, in milliseconds. - * @retval None - */ -void Delay_ms(u16 nms) -{ - u32 temp; - while(nms) - { - if(nms > STEP_DELAY_MS) - { - SysTick->LOAD = (u32)(STEP_DELAY_MS * fac_ms); - nms -= STEP_DELAY_MS; - } - else - { - SysTick->LOAD = (u32)(nms * fac_ms); - nms = 0; - } - SysTick->VAL = 0x00; - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; - do - { - temp = SysTick->CTRL; - }while( (temp & 0x01) && !(temp & (1<<16)) ); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - SysTick->VAL = 0X00; - } -} - -/** - * @brief Inserts a delay time. - * @param sec: specifies the delay time length, in seconds. - * @retval None - */ -void Delay_sec(u16 sec) -{ - u16 i; - for(i=0; i - -/*Delay function*/ -void Delay_init(void); -void Delay_us(u32 nus); -void Delay_ms(u16 nms); -void Delay_sec(u16 sec); - -#endif \ No newline at end of file diff --git a/.platformio/platforms/at32/examples/cmsis-blink/lib/README b/.platformio/platforms/at32/examples/cmsis-blink/lib/README deleted file mode 100644 index 6debab1..0000000 --- a/.platformio/platforms/at32/examples/cmsis-blink/lib/README +++ /dev/null @@ -1,46 +0,0 @@ - -This directory is intended for project specific (private) libraries. -PlatformIO will compile them to static libraries and link into executable file. - -The source code of each library should be placed in a an own separate directory -("lib/your_library_name/[here are source files]"). - -For example, see a structure of the following two libraries `Foo` and `Bar`: - -|--lib -| | -| |--Bar -| | |--docs -| | |--examples -| | |--src -| | |- Bar.c -| | |- Bar.h -| | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html -| | -| |--Foo -| | |- Foo.c -| | |- Foo.h -| | -| |- README --> THIS FILE -| -|- platformio.ini -|--src - |- main.c - -and a contents of `src/main.c`: -``` -#include -#include - -int main (void) -{ - ... -} - -``` - -PlatformIO Library Dependency Finder will find automatically dependent -libraries scanning project source files. - -More information about PlatformIO Library Dependency Finder -- https://docs.platformio.org/page/librarymanager/ldf.html diff --git a/.platformio/platforms/at32/examples/cmsis-blink/platformio.ini b/.platformio/platforms/at32/examples/cmsis-blink/platformio.ini deleted file mode 100644 index 315b4c0..0000000 --- a/.platformio/platforms/at32/examples/cmsis-blink/platformio.ini +++ /dev/null @@ -1,35 +0,0 @@ -; PlatformIO Project Configuration File -; -; Build options: build flags, source filter, extra scripting -; Upload options: custom port, speed and extra flags -; Library options: dependencies, extra library storages -; -; Please visit documentation for the other options and examples -; http://docs.platformio.org/page/projectconf.html - -[env:generic_f403a] -platform = at32 -framework = cmsis -board = generic_f403a -monitor_speed = 115200 ;serial monitor baudrate - -;Use the following for jlink upload -upload_protocol = jlink - -;Use the following for serial upload via bootloader (PA9, PA10) -;upload_protocol = serial -;upload_speed = 115200 ;default: 115200 - -;Use the following for DFU upload via USB port -;upload_protocol = dfu -;build_flags = -; -DDFU_MODE -; -UVECT_TAB_OFFSET -; -DUSER_VECT_TAB_ADDRESS -; -DVECT_TAB_OFFSET=0x2000 ; override default vector tale to support ISR table for DFU mode - -;Use the following for custom uploader -;upload_protocol = custom -;upload_port = COM16 -;upload_speed = 115200 -;upload_command = ${platformio.packages_dir}/framework-cmsis-at32f40/tools/stm32flash/stm32flash -b $UPLOAD_SPEED -w $SOURCE -g 0x8000000 $UPLOAD_PORT \ No newline at end of file diff --git a/.platformio/platforms/at32/examples/cmsis-blink/src/main.c b/.platformio/platforms/at32/examples/cmsis-blink/src/main.c deleted file mode 100644 index 5f6f00d..0000000 --- a/.platformio/platforms/at32/examples/cmsis-blink/src/main.c +++ /dev/null @@ -1,49 +0,0 @@ -/** Light on/off pin PC13, 100Hz frequency */ - -#include "at32f4xx.h" -#include "delay.h" - - -#define BLUEPILL // BLUEPILL BLACKPILL QFP48_FLASHER - -#ifdef BLUEPILL - #define LEDPORT (GPIOC) - #define LED1 (13) - #define ENABLE_GPIO_CLOCK (RCC->APB2EN |= RCC_APB2EN_GPIOCEN) //RCC_APB2ENR_IOPCEN) - #define _MODER CTRLH - #define GPIOMODER (GPIO_CTRLH_MDE13_0) -#endif -#ifdef BLACKPILL - #define LEDPORT (GPIOB) - #define LED1 (12) - #define ENABLE_GPIO_CLOCK (RCC->APB2EN |= RCC_APB2EN_GPIOBEN) //RCC_APB2ENR_IOPCEN) - #define _MODER CTRLH - #define GPIOMODER (GPIO_CTRLH_MDE12_0) -#endif -#ifdef QFP48_FLASHER - #define LEDPORT (GPIOB) - #define LED1 (15) - #define ENABLE_GPIO_CLOCK (RCC->APB2EN |= RCC_APB2EN_GPIOBEN) //RCC_APB2ENR_IOPCEN) - #define _MODER CTRLH - #define GPIOMODER (GPIO_CTRLH_MDE15_0) -#endif - - - - - -//Alternates blue and green LEDs quickly -int main(void) -{ - Delay_init(); - - ENABLE_GPIO_CLOCK; // enable the clock to GPIO - LEDPORT->_MODER |= GPIOMODER; // set pins to be general purpose output - - for (;;) { - Delay_ms(1000); - LEDPORT->OPTDT ^= (1<CPACR |= ((3U << 10U * 2U) | /* set CP10 Full Access */ - (3U << 11U * 2U) ); /* set CP11 Full Access */ -#endif - - /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ - /* Set HSIEN bit */ - BIT_SET(RCC->CTRL, RCC_CTRL_HSIEN); - - /* Reset SW, AHBPSC, APB1PSC, APB2PSC, ADCPSC and CLKOUT bits */ - BIT_CLEAR(RCC->CFG, RCC_CFG_SYSCLKSEL | RCC_CFG_AHBPSC | \ - RCC_CFG_APB1PSC | RCC_CFG_APB2PSC | \ - RCC_CFG_ADCPSC | RCC_CFG_CLKOUT); - - /* Reset HSEEN, HSECFDEN and PLLEN bits */ - BIT_CLEAR(RCC->CTRL, RCC_CTRL_HSEEN | RCC_CTRL_HSECFDEN | \ - RCC_CTRL_PLLEN); - - /* Reset HSEBYPS bit */ - BIT_CLEAR(RCC->CTRL, RCC_CTRL_HSEBYPS); - - /* Reset PLLRC, PLLHSEPSC, PLLMUL, USBPSC and PLLRANGE bits */ - BIT_CLEAR(RCC->CFG, RCC_CFG_PLLRC | RCC_CFG_PLLHSEPSC | \ - RCC_CFG_PLLMULT | RCC_CFG_USBPSC | RCC_CFG_PLLRANGE); - - /* Reset USB768B, CLKOUT[3], HSICAL_KEY[7:0] */ - BIT_CLEAR(RCC->MISC, 0x010100FF); - - /* Disable all interrupts and clear pending bits */ - RCC->CLKINT = RCC_CLKINT_LSISTBLFC | RCC_CLKINT_LSESTBLFC | \ - RCC_CLKINT_HSISTBLFC | RCC_CLKINT_HSESTBLFC | \ - RCC_CLKINT_PLLSTBLFC | RCC_CLKINT_HSECFDFC; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtrl(); -#endif /* DATA_IN_ExtSRAM */ - - /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ - /* Configure the Flash Latency cycles and enable prefetch buffer */ - SetSysClock(); - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in at32f4xx.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in at32f4xx.h file (default value - * 8 MHz or 25 MHz, depedning on the product used), user has to ensure - * that HSE_VALUE is same as the real frequency of the crystal used. - * Otherwise, this function may have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmult = 0, pllrefclk = 0, tempcfg = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFG & RCC_CFG_SYSCLKSTS; - - switch (tmp) - { - case RCC_CFG_SYSCLKSTS_HSI: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - - case RCC_CFG_SYSCLKSTS_HSE: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - - case RCC_CFG_SYSCLKSTS_PLL: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllrefclk = RCC->CFG & RCC_CFG_PLLRC; - tempcfg = RCC->CFG; - pllmult = RCC_GET_PLLMULT(tempcfg); - - if (pllrefclk == RCC_PLLRefClk_HSI_Div2) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmult; - } - else - { - /* HSE selected as PLL clock entry */ - if ((RCC->CFG & RCC_CFG_PLLHSEPSC) != (uint32_t)RESET) - { - /* HSE oscillator clock divided by 2 */ - SystemCoreClock = (HSE_VALUE >> 1) * pllmult; - } - else - { - SystemCoreClock = HSE_VALUE * pllmult; - } - } - - break; - - default: - SystemCoreClock = HSI_VALUE; - break; - } - - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPscTable[((RCC->CFG & RCC_CFG_AHBPSC) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -#ifdef SYSCLK_FREQ_HSE - SetSysClockToHSE(); -#elif defined SYSCLK_FREQ_24MHz - SetSysClockTo24M(); -#elif defined SYSCLK_FREQ_36MHz - SetSysClockTo36M(); -#elif defined SYSCLK_FREQ_48MHz - SetSysClockTo48M(); -#elif defined SYSCLK_FREQ_56MHz - SetSysClockTo56M(); -#elif defined SYSCLK_FREQ_72MHz - SetSysClockTo72M(); -#elif defined SYSCLK_FREQ_96MHz - SetSysClockTo96M(); -#elif defined SYSCLK_FREQ_108MHz - SetSysClockTo108M(); -#elif defined SYSCLK_FREQ_120MHz - SetSysClockTo120M(); -#elif defined SYSCLK_FREQ_144MHz - SetSysClockTo144M(); -#elif defined SYSCLK_FREQ_150MHz - SetSysClockTo150M(); -#elif defined SYSCLK_FREQ_168MHz - SetSysClockTo168M(); -#elif defined SYSCLK_FREQ_176MHz - SetSysClockTo176M(); -#elif defined SYSCLK_FREQ_192MHz - SetSysClockTo192M(); -#elif defined SYSCLK_FREQ_200MHz - SetSysClockTo200M(); -#elif defined SYSCLK_FREQ_224MHz - SetSysClockTo224M(); -#elif defined SYSCLK_FREQ_240MHz - SetSysClockTo240M(); -#elif defined SYSCLK_FREQ_24MHz_HSI - SetSysClockTo24MHSI(); -#elif defined SYSCLK_FREQ_36MHz_HSI - SetSysClockTo36MHSI(); -#elif defined SYSCLK_FREQ_48MHz_HSI - SetSysClockTo48MHSI(); -#elif defined SYSCLK_FREQ_56MHz_HSI - SetSysClockTo56MHSI(); -#elif defined SYSCLK_FREQ_72MHz_HSI - SetSysClockTo72MHSI(); -#elif defined SYSCLK_FREQ_96MHz_HSI - SetSysClockTo96MHSI(); -#elif defined SYSCLK_FREQ_108MHz_HSI - SetSysClockTo108MHSI(); -#elif defined SYSCLK_FREQ_120MHz_HSI - SetSysClockTo120MHSI(); -#elif defined SYSCLK_FREQ_144MHz_HSI - SetSysClockTo144MHSI(); -#elif defined SYSCLK_FREQ_150MHz_HSI - SetSysClockTo150MHSI(); -#elif defined SYSCLK_FREQ_168MHz_HSI - SetSysClockTo168MHSI(); -#elif defined SYSCLK_FREQ_176MHz_HSI - SetSysClockTo176MHSI(); -#elif defined SYSCLK_FREQ_192MHz_HSI - SetSysClockTo192MHSI(); -#elif defined SYSCLK_FREQ_200MHz_HSI - SetSysClockTo200MHSI(); -#elif defined SYSCLK_FREQ_224MHz_HSI - SetSysClockTo224MHSI(); -#elif defined SYSCLK_FREQ_240MHz_HSI - SetSysClockTo240MHSI(); -#endif - - /* If none of the define above is enabled, the HSI is used as System clock - source (default after reset) */ -} - -/** - * @brief Setup the external memory controller. Called in startup_at32f4xx.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_at32f4xx_xx.s/.c before jump to main. - * This function configures the external SRAM mounted - * (AT32 High density devices). This SRAM will be used as program - * data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtrl(void) -{ - /* Enable XMC clock */ - RCC->AHBEN = RCC_AHBEN_SRAMEN | RCC_AHBEN_FLASHEN | RCC_AHBEN_XMCEN; - - /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ - RCC->APB2EN = RCC_APB2EN_GPIODEN | RCC_APB2EN_GPIOEEN | RCC_APB2EN_GPIOFEN | RCC_APB2EN_GPIOGEN; - - /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ - /*---------------- SRAM Address lines configuration -------------------------*/ - /*---------------- NOE and NWE configuration --------------------------------*/ - /*---------------- NE3 configuration ----------------------------------------*/ - /*---------------- NBL0, NBL1 configuration ---------------------------------*/ - - GPIOD->CTRLL = 0x44BB44BB; - GPIOD->CTRLH = 0xBBBBBBBB; - - GPIOE->CTRLL = 0xB44444BB; - GPIOE->CTRLH = 0xBBBBBBBB; - - GPIOF->CTRLL = 0x44BBBBBB; - GPIOF->CTRLH = 0xBBBB4444; - - GPIOG->CTRLL = 0x44BBBBBB; - GPIOG->CTRLH = 0x44444B44; - - /*---------------- XMC Configuration ---------------------------------------*/ - /*---------------- Enable XMC Bank1_SRAM Bank ------------------------------*/ - - XMC_Bank1->BK1CTRLR[4] = 0x00001011; - XMC_Bank1->BK1CTRLR[5] = 0x00000200; -} -#endif /* DATA_IN_ExtSRAM */ - -#ifndef SYSCLK_FREQ_HSI -#ifdef AT32F403xx -/** - * @brief Delay to wait for HSE stable. - * @note This function should be used before reading the HSESTBL flag. - * @param None - * @retval None - */ -static void WaitHseStbl(uint32_t delay) -{ - uint32_t i; - - for(i = 0; i < delay; i++) - ; -} -#endif -#endif /* SYSCLK_FREQ_HSI */ - -#ifdef SYSCLK_FREQ_HSE -/** - * @brief Selects HSE as System clock source and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockToHSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1; - - /* Select HSE as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_HSE; - - /* Wait till HSE is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != (uint32_t)0x04) - { - } - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_24MHz -/** - * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo24M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1; - - /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT6); -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_36MHz -/** - * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo36M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1; - - /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT9); -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_48MHz -/** - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo48M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT6); -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_56MHz -/** - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo56M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT7); -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_72MHz -/** - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo72M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT9); -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_96MHz -/** - * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo96M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; -#if defined (AT32F415xx) - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT12); -#else - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT12 | RCC_CFG_PLLRANGE_GT72MHZ); -#endif -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_108MHz -/** - * @brief Sets System clock frequency to 108MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo108M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSE/2) * 27 = 108 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - -#if defined (AT32F415xx) - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT27); -#else - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLHSEPSC_HSE_DIV2 | RCC_CFG_PLLMULT27 \ - | RCC_CFG_PLLRANGE_GT72MHZ); -#endif -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_120MHz -/** - * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo120M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - -#if defined (AT32F415xx) - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT15); -#else - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT15 | RCC_CFG_PLLRANGE_GT72MHZ); -#endif -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_144MHz -/** - * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo144M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - -#if defined (AT32F415xx) - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18); -#else - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18 | RCC_CFG_PLLRANGE_GT72MHZ); -#endif -#if defined (AT32F415xx) - /* Config PLL clock resource Table */ - RCC_PLLFrefTableConfig(HSE_VALUE); -#endif - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_150MHz -/** - * @brief Sets System clock frequency to 150MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo150M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSE * 75) / (1 * 4) = 150 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE); - RCC_PLLconfig2(PLL_FREF_8M, 75, 1, PLL_FR_4); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_168MHz -/** - * @brief Sets System clock frequency to 168MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo168M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 21 = 168 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT21 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_176MHz -/** - * @brief Sets System clock frequency to 176MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo176M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 22 = 176 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT22 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_192MHz -/** - * @brief Sets System clock frequency to 192MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo192M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 24 = 192 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT24 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_200MHz -/** - * @brief Sets System clock frequency to 200MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo200M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 25 = 200 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT25 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_224MHz -/** - * @brief Sets System clock frequency to 224MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo224M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 28 = 224 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT28 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_240MHz -/** - * @brief Sets System clock frequency to 240MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo240M(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CTRL & RCC_CTRL_HSESTBL; - StartUpCounter++; - } - while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx - WaitHseStbl(HSE_STABLE_DELAY); -#endif - if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = HSE * 30 = 240 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT30 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_24MHz_HSI -/** - * @brief Sets System clock frequency to 24MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo24MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1; - - /* PLL configuration: PLLCLK = (HSI/2) * 6 = 24 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT6); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } -} - -#elif defined SYSCLK_FREQ_36MHz_HSI -/** - * @brief Sets System clock frequency to 36MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo36MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV1; - - /* PLL configuration: PLLCLK = (HSI/2) * 9 = 36 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT9); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } -} - -#elif defined SYSCLK_FREQ_48MHz_HSI -/** - * @brief Sets System clock frequency to 48MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo48MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 12 = 48 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT12); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } -} - -#elif defined SYSCLK_FREQ_56MHz_HSI -/** - * @brief Sets System clock frequency to 56MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo56MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 14 = 56 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT14); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } -} - -#elif defined SYSCLK_FREQ_72MHz_HSI -/** - * @brief Sets System clock frequency to 72MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo72MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV1; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 18 = 72 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT18); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } -} - -#elif defined SYSCLK_FREQ_96MHz_HSI -/** - * @brief Sets System clock frequency to 96MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo96MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 24 = 96 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - -#if defined (AT32F415xx) - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT24); -#else - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT24 | RCC_CFG_PLLRANGE_GT72MHZ); -#endif - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } -} - -#elif defined SYSCLK_FREQ_108MHz_HSI -/** - * @brief Sets System clock frequency to 108MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo108MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 27 = 108 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - -#if defined (AT32F415xx) - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT27); -#else - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT27 | RCC_CFG_PLLRANGE_GT72MHZ); -#endif - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif - } -} - -#elif defined SYSCLK_FREQ_120MHz_HSI -/** - * @brief Sets System clock frequency to 120MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo120MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 30 = 120 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - -#if defined (AT32F415xx) - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT30); -#else - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT30 | RCC_CFG_PLLRANGE_GT72MHZ); -#endif - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} - -#elif defined SYSCLK_FREQ_144MHz_HSI -/** - * @brief Sets System clock frequency to 144MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo144MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 36 = 144 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - -#if defined (AT32F415xx) - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT36); -#else - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT36 | RCC_CFG_PLLRANGE_GT72MHZ); -#endif - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} - -#elif defined SYSCLK_FREQ_150MHz_HSI -/** - * @brief Sets System clock frequency to 150MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo150MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { -#if defined (AT32F415xx) - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; -#endif - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = ((HSI/2) * 150) / (1 * 4) = 150 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2); - RCC_PLLconfig2(PLL_FREF_4M, 150, 1, PLL_FR_4); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) || defined (AT32F415xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} - -#elif defined SYSCLK_FREQ_168MHz_HSI -/** - * @brief Sets System clock frequency to 168MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo168MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 42 = 168 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT42 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} -#elif defined SYSCLK_FREQ_176MHz_HSI -/** - * @brief Sets System clock frequency to 176MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo176MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 44 = 176 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT44 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} -#elif defined SYSCLK_FREQ_192MHz_HSI -/** - * @brief Sets System clock frequency to 192MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo192MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 48 = 192 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT48 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} -#elif defined SYSCLK_FREQ_200MHz_HSI -/** - * @brief Sets System clock frequency to 200MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo200MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 50 = 200 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT50 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} - -#elif defined SYSCLK_FREQ_224MHz_HSI -/** - * @brief Sets System clock frequency to 224MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo224MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 56 = 224 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT56 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} - -#elif defined SYSCLK_FREQ_240MHz_HSI -/** - * @brief Sets System clock frequency to 240MHz from HSI and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo240MHSI(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CTRL |= ((uint32_t)RCC_CTRL_HSIEN); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CTRL & RCC_CTRL_HSISTBL; - StartUpCounter++; - } - while((HSIStatus == 0) && (StartUpCounter != 0xFFFF)); - - if ((RCC->CTRL & RCC_CTRL_HSISTBL) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK */ - RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; - - /* PCLK2 = HCLK/2 */ - RCC->CFG &= 0xFFFFC7FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB2PSC_DIV2; - - /* PCLK1 = HCLK/2 */ - RCC->CFG &= 0xFFFFF8FF; - RCC->CFG |= (uint32_t)RCC_CFG_APB1PSC_DIV2; - - /* PLL configuration: PLLCLK = (HSI/2) * 60 = 240 MHz */ - RCC->CFG &= RCC_CFG_PLLCFG_MASK; - RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSI_DIV2 | RCC_CFG_PLLMULT60 | RCC_CFG_PLLRANGE_GT72MHZ); - - /* Enable PLL */ - RCC->CTRL |= RCC_CTRL_PLLEN; - - /* Wait till PLL is ready */ - while((RCC->CTRL & RCC_CTRL_PLLSTBL) == 0) - { - } -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(ENABLE); -#endif - /* Select PLL as system clock source */ - RCC->CFG &= (uint32_t)((uint32_t)~(RCC_CFG_SYSCLKSEL)); - RCC->CFG |= (uint32_t)RCC_CFG_SYSCLKSEL_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFG & (uint32_t)RCC_CFG_SYSCLKSTS) != RCC_CFG_SYSCLKSTS_PLL) - { - } -#ifdef AT32F403xx - WaitHseStbl(PLL_STABLE_DELAY); -#endif -#if defined (AT32F413xx) || defined (AT32F403Axx)|| \ - defined (AT32F407xx) - RCC_StepModeCmd(DISABLE); -#endif - } -} - -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/ diff --git a/.platformio/platforms/at32/platform.json b/.platformio/platforms/at32/platform.json index d15bad1..319b797 100644 --- a/.platformio/platforms/at32/platform.json +++ b/.platformio/platforms/at32/platform.json @@ -1,6 +1,6 @@ { "name": "at32", - "title": "AT32", + "title": "Artery AT32", "description": "The AT32 family of 32-bit Flash MCUs based on the ARM Cortex-M processor is designed to offer new degrees of freedom to MCU users. It offers a 32-bit product range that combines very high performance, real-time capabilities, digital signal processing, and low-power, low-voltage operation, while maintaining full integration and ease of development.", "homepage": "https://www.arterychip.com/en/index.jsp", "license": "Apache-2.0", @@ -18,7 +18,7 @@ "type": "git", "url": "https://github.com/platformio/platform-at32.git" }, - "version": "1.0.0", + "version": "1.0.1", "frameworks": { "cmsis": { "package": "framework-cmsis", @@ -51,21 +51,15 @@ "framework-cmsis-at32f40": { "type": "framework", "optional": true, - "owner": "platformio", - "version": "~1.0.0" + "owner": "martinloren", + "version": "https://github.com/martinloren/framework-cmsis-at32f40.git" }, - "framework-cmsis-at32f42": { - "type": "framework", - "optional": true, - "owner": "platformio", - "version": "~1.0.0" - }, "framework-cmsis-at32f43": { "type": "framework", "optional": true, - "owner": "platformio", - "version": "~1.0.0" - }, + "owner": "martinloren", + "version": "https://github.com/martinloren/framework-cmsis-at32f43.git" + }, "tool-openocd": { "type": "uploader", "optional": true, diff --git a/JLinkDevices/AT/AT32F435xGx/AT32F435_1024.FLM b/JLinkDevices/AT/AT32F435xGx/AT32F435_1024.FLM new file mode 100644 index 0000000000000000000000000000000000000000..5bb5d7d6c8f63642a2388c243bab99a3c9282033 GIT binary patch literal 12428 zcmeHOZETy@bv~CbNl}(;QD2S{+wyChapXm!DT$J0#fn8qlt`PBXi>7Ag$YHGl*E`K zIeyr3);ewz6i$~FL7Ju?X&V11iZp4^7HPWyMdo3^+M;NIIPC^>Sc{-P>K52Ar3*R_ z7@$4pzV8(&#T~Z%NPbM$xxD8*=i{Dx?ib%z%oG05xDbL=u}}vo?k8PD^=?QkWb=}a zrh}Z+KtB)sL(nnr*iXyDYghBN`yKOizMcdelGlV;C4MQ zKm3RF{Iz+~oo~{2E#oi4UWffl(*B$4F9qs7a;)@XupZW541`Sn^T7~!q~^`%O`S1% zPU_H&X9Ess(HgReaXusE`kIwKE#=otA7k_>!^e%M0)Z<1t5VMTSIj>06Jq?^?@~PSy7~=bih+JkQ7Q+AuliwRc!M3+)S4F}-(l z$&ATDDZ@(6U<+M)qeXAp@0=I_UXZF$vvKl7nd3T z@QOSg5Q~$@YV^8}=C=sjc^?QFCDFQBKD@ZLd)m&xb_TXHu$_VJ3~Xm$I|JJp*v`Oq z2DUS>oq_EPY-ixZ%78dPM;q|Q@Blj0@M5twxEt>YTvS*0V4a3{1GYw?Iqr2d+x9pb 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Studio Code with PlatformIO installed （tested with PlatformIO v.2.4.0). -1) Copy the folders under .platformio into your .platformio folder (ie: C:\Users\(username)\.platformio)
-将 .platformio 下的文件夹复制到您的 .platformio 文件夹中（即：C:\Users\(用户名)\.platformio） + +## Installation 安装 +You need to have Visual Studio Code with PlatformIO installed （tested with PlatformIO Core v.6.1.16). +1) Copy the folders under `.platformio` into your .platformio folder (ie: `C:\Users\\.platformio`) +将 .platformio 下的文件夹复制到您的 .platformio 文件夹中（即：`C:\Users\<用户名>\.platformio`） + +#### Install AT32 Configurations for J-Link (last update from ArteryICPProgrammer V3.0.19) +In order to make the J-Link software aware of the new device, copy the folder `JLinkDevices` in the the central JLinkDevices folder (Windows): `C:\Users\\AppData\Roaming\SEGGER\` + +Currently available: +- AT32F435xGx +- AT32F437xGx + +More details about custom device configuration for J-Link are available [here](https://wiki.segger.com/J-Link_Device_Support_Kit). + + +## Usage Instructions 使用说明 3) Open Visual Studio Code, you should see AT32 Platform among the available platforms
打开 Visual Studio Code，在可用平台中应该可以看到 AT32 平台 4) Open one of the example folder and try to compile / upload
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a/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F435_256.FLM b/old-jlink/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F435_256.FLM similarity index 100% rename from .platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F435_256.FLM rename to old-jlink/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F435_256.FLM diff --git a/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F435_4032.FLM b/old-jlink/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F435_4032.FLM similarity index 100% rename from .platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F435_4032.FLM rename to old-jlink/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F435_4032.FLM diff --git a/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F435_960.FLM b/old-jlink/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F435_960.FLM similarity index 100% rename from .platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F435_960.FLM rename to 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.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F437_256.FLM rename to old-jlink/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F437_256.FLM diff --git a/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F437_4032.FLM b/old-jlink/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F437_4032.FLM similarity index 100% rename from .platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F437_4032.FLM rename to old-jlink/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F437_4032.FLM diff --git a/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F437_960.FLM b/old-jlink/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F437_960.FLM similarity index 100% rename from .platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F437_960.FLM rename to old-jlink/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F437_960.FLM diff --git a/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F4xx.JLinkScript b/old-jlink/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F4xx.JLinkScript similarity index 100% rename from .platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F4xx.JLinkScript rename to old-jlink/.platformio/packages/tool-jlink/Devices/AT/AT32F4xx/AT32F4xx.JLinkScript diff --git a/JLINK.md b/old-jlink/JLINK.md similarity index 98% rename from JLINK.md rename to old-jlink/JLINK.md index c80cdf4..633c269 100644 --- a/JLINK.md +++ b/old-jlink/JLINK.md @@ -1,4 +1,5 @@ # Instructions for JLINK Configuration +(Dismissed, not valid with latest version of tool-jlink package) ## 1. Add AT .FLM Files Copy the `.platformio\packages\tool-jlink\Devices\AT\AT32F4xx` folder from Github here to your .platformio folder.