mirror of
https://github.com/martinloren/Artery-AT32-PlatformIO.git
synced 2026-05-21 01:12:07 +00:00
updated
This commit is contained in:
Martin Loren
@@ -1,4 +1,4 @@
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name=AT32_USB-FS-Device_Driver
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name=AT32F435_427_USB-FS-Device_Driver
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version=1.0.0
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author=AT
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maintainer=AT
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@@ -1,205 +0,0 @@
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/**
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**************************************************************************
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* @file at32f435_437_acc.h
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* @version v2.0.4
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* @date 2021-12-31
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* @brief at32f435_437 acc header file
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**************************************************************************
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* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32F435_437_ACC_H
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#define __AT32F435_437_ACC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "at32f435_437.h"
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/** @addtogroup AT32F435_437_periph_driver
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* @{
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*/
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/** @addtogroup ACC
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* @{
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*/
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/** @defgroup ACC_exported_constants
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* @{
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*/
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#define ACC_CAL_HICKCAL ((uint16_t)0x0000) /*!< acc hick calibration */
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#define ACC_CAL_HICKTRIM ((uint16_t)0x0002) /*!< acc hick trim */
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#define ACC_RSLOST_FLAG ((uint16_t)0x0002) /*!< acc reference signal lost error flag */
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#define ACC_CALRDY_FLAG ((uint16_t)0x0001) /*!< acc internal high-speed clock calibration ready error flag */
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#define ACC_CALRDYIEN_INT ((uint16_t)0x0020) /*!< acc internal high-speed clock calibration ready interrupt enable */
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#define ACC_EIEN_INT ((uint16_t)0x0010) /*!< acc reference signal lost interrupt enable */
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#define ACC_SOF_OTG1 ((uint16_t)0x0000) /*!< acc sof signal select: otg1 */
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#define ACC_SOF_OTG2 ((uint16_t)0x0004) /*!< acc sof signal select: otg2 */
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/**
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* @}
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*/
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/** @defgroup ACC_exported_types
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* @{
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*/
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/**
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* @brief type define acc register all
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*/
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typedef struct
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{
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/**
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* @brief acc sts register, offset:0x00
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*/
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union
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{
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__IO uint32_t sts;
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struct
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{
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__IO uint32_t calrdy : 1; /* [0] */
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__IO uint32_t rslost : 1; /* [1] */
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__IO uint32_t reserved1 : 30;/* [31:2] */
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} sts_bit;
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};
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/**
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* @brief acc ctrl1 register, offset:0x04
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*/
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union
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{
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__IO uint32_t ctrl1;
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struct
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{
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__IO uint32_t calon : 1; /* [0] */
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__IO uint32_t entrim : 1; /* [1] */
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__IO uint32_t reserved1 : 2; /* [3:2] */
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__IO uint32_t eien : 1; /* [4] */
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__IO uint32_t calrdyien : 1; /* [5] */
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__IO uint32_t reserved2 : 2; /* [7:6] */
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__IO uint32_t step : 4; /* [11:8] */
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__IO uint32_t reserved3 : 20;/* [31:12] */
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} ctrl1_bit;
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};
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/**
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* @brief acc ctrl2 register, offset:0x08
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*/
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union
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{
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__IO uint32_t ctrl2;
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struct
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{
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__IO uint32_t hickcal : 8; /* [7:0] */
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__IO uint32_t hicktrim : 6; /* [13:8] */
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__IO uint32_t reserved1 : 18;/* [31:14] */
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} ctrl2_bit;
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};
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/**
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* @brief acc acc_c1 register, offset:0x0C
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*/
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union
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{
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__IO uint32_t c1;
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struct
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{
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__IO uint32_t c1 : 16;/* [15:0] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} c1_bit;
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};
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/**
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* @brief acc acc_c2 register, offset:0x10
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*/
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union
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{
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__IO uint32_t c2;
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struct
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{
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__IO uint32_t c2 : 16;/* [15:0] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} c2_bit;
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};
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/**
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* @brief acc acc_c3 register, offset:0x14
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*/
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union
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{
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__IO uint32_t c3;
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struct
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{
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__IO uint32_t c3 : 16;/* [15:0] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} c3_bit;
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};
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} acc_type;
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/**
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* @}
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*/
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#define ACC ((acc_type *) ACC_BASE)
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/** @defgroup ACC_exported_functions
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* @{
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*/
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void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state);
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void acc_step_set(uint8_t step_value);
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void acc_sof_select(uint16_t sof_sel);
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void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state);
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uint8_t acc_hicktrim_get(void);
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uint8_t acc_hickcal_get(void);
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void acc_write_c1(uint16_t acc_c1_value);
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void acc_write_c2(uint16_t acc_c2_value);
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void acc_write_c3(uint16_t acc_c3_value);
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uint16_t acc_read_c1(void);
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uint16_t acc_read_c2(void);
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uint16_t acc_read_c3(void);
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flag_status acc_flag_get(uint16_t acc_flag);
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void acc_flag_clear(uint16_t acc_flag);
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/**
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* @}
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*/
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||||
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/**
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* @}
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||||
*/
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||||
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||||
/**
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||||
* @}
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||||
*/
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||||
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#ifdef __cplusplus
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}
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#endif
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#endif
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@@ -1,938 +0,0 @@
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/**
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**************************************************************************
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* @file at32f435_437_adc.h
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* @version v2.0.4
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* @date 2021-12-31
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||||
* @brief at32f435_437 adc header file
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||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
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||||
*/
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||||
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32F435_437_ADC_H
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#define __AT32F435_437_ADC_H
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#ifdef __cplusplus
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||||
extern "C" {
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||||
#endif
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||||
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||||
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/* Includes ------------------------------------------------------------------*/
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||||
#include "at32f435_437.h"
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/** @addtogroup AT32F435_437_periph_driver
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* @{
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*/
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/** @addtogroup ADC
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* @{
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*/
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/** @defgroup ADC_interrupts_definition
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* @brief adc interrupt
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* @{
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*/
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#define ADC_OCCE_INT ((uint32_t)0x00000020) /*!< ordinary channels conversion end interrupt */
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#define ADC_VMOR_INT ((uint32_t)0x00000040) /*!< voltage monitoring out of range interrupt */
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#define ADC_PCCE_INT ((uint32_t)0x00000080) /*!< preempt channels conversion end interrupt */
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#define ADC_OCCO_INT ((uint32_t)0x04000000) /*!< ordinary channel conversion overflow interrupt */
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/**
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* @}
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*/
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/** @defgroup ADC_flags_definition
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* @brief adc flag
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* @{
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*/
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#define ADC_VMOR_FLAG ((uint8_t)0x01) /*!< voltage monitoring out of range flag */
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#define ADC_OCCE_FLAG ((uint8_t)0x02) /*!< ordinary channels conversion end flag */
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#define ADC_PCCE_FLAG ((uint8_t)0x04) /*!< preempt channels conversion end flag */
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#define ADC_PCCS_FLAG ((uint8_t)0x08) /*!< preempt channel conversion start flag */
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#define ADC_OCCS_FLAG ((uint8_t)0x10) /*!< ordinary channel conversion start flag */
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#define ADC_OCCO_FLAG ((uint8_t)0x20) /*!< ordinary channel conversion overflow flag */
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#define ADC_RDY_FLAG ((uint8_t)0x40) /*!< adc ready to conversion flag */
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/**
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* @}
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*/
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/** @defgroup ADC_exported_types
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* @{
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||||
*/
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||||
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/**
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* @brief adc division type
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*/
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typedef enum
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{
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ADC_HCLK_DIV_2 = 0x00, /*!< adcclk is hclk/2 */
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ADC_HCLK_DIV_3 = 0x01, /*!< adcclk is hclk/3 */
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ADC_HCLK_DIV_4 = 0x02, /*!< adcclk is hclk/4 */
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ADC_HCLK_DIV_5 = 0x03, /*!< adcclk is hclk/5 */
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ADC_HCLK_DIV_6 = 0x04, /*!< adcclk is hclk/6 */
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ADC_HCLK_DIV_7 = 0x05, /*!< adcclk is hclk/7 */
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ADC_HCLK_DIV_8 = 0x06, /*!< adcclk is hclk/8 */
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ADC_HCLK_DIV_9 = 0x07, /*!< adcclk is hclk/9 */
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ADC_HCLK_DIV_10 = 0x08, /*!< adcclk is hclk/10 */
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ADC_HCLK_DIV_11 = 0x09, /*!< adcclk is hclk/11 */
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ADC_HCLK_DIV_12 = 0x0A, /*!< adcclk is hclk/12 */
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ADC_HCLK_DIV_13 = 0x0B, /*!< adcclk is hclk/13 */
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ADC_HCLK_DIV_14 = 0x0C, /*!< adcclk is hclk/14 */
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ADC_HCLK_DIV_15 = 0x0D, /*!< adcclk is hclk/15 */
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ADC_HCLK_DIV_16 = 0x0E, /*!< adcclk is hclk/16 */
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ADC_HCLK_DIV_17 = 0x0F /*!< adcclk is hclk/17 */
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} adc_div_type;
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|
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/**
|
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* @brief adc combine mode type
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*/
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typedef enum
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{
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ADC_INDEPENDENT_MODE = 0x00, /*!< independent mode */
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ADC_ORDINARY_SMLT_PREEMPT_SMLT_ONESLAVE_MODE = 0x01, /*!< single slaver combined ordinary simultaneous + preempt simultaneous mode */
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ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_ONESLAVE_MODE = 0x02, /*!< single slaver combined ordinary simultaneous + preempt interleaved trigger mode */
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ADC_PREEMPT_SMLT_ONLY_ONESLAVE_MODE = 0x05, /*!< single slaver preempt simultaneous mode only */
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ADC_ORDINARY_SMLT_ONLY_ONESLAVE_MODE = 0x06, /*!< single slaver ordinary simultaneous mode only */
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ADC_ORDINARY_SHIFT_ONLY_ONESLAVE_MODE = 0x07, /*!< single slaver ordinary shifting mode only */
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ADC_PREEMPT_INTERLTRIG_ONLY_ONESLAVE_MODE = 0x09, /*!< single slaver preempt interleaved trigger mode only */
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ADC_ORDINARY_SMLT_PREEMPT_SMLT_TWOSLAVE_MODE = 0x11, /*!< double slaver combined ordinary simultaneous + preempt simultaneous mode */
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ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_TWOSLAVE_MODE = 0x12, /*!< double slaver combined ordinary simultaneous + preempt interleaved trigger mode */
|
||||
ADC_PREEMPT_SMLT_ONLY_TWOSLAVE_MODE = 0x15, /*!< double slaver preempt simultaneous mode only */
|
||||
ADC_ORDINARY_SMLT_ONLY_TWOSLAVE_MODE = 0x16, /*!< double slaver ordinary simultaneous mode only */
|
||||
ADC_ORDINARY_SHIFT_ONLY_TWOSLAVE_MODE = 0x17, /*!< double slaver ordinary shifting mode only */
|
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ADC_PREEMPT_INTERLTRIG_ONLY_TWOSLAVE_MODE = 0x19 /*!< double slaver preempt interleaved trigger mode only */
|
||||
} adc_combine_mode_type;
|
||||
|
||||
/**
|
||||
* @brief adc common dma mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_COMMON_DMAMODE_DISABLE = 0x00, /*!< dma mode disabled */
|
||||
ADC_COMMON_DMAMODE_1 = 0x01, /*!< dma mode1: each dma request trans a half-word data(reference manual account the rule of data package) */
|
||||
ADC_COMMON_DMAMODE_2 = 0x02, /*!< dma mode2: each dma request trans two half-word data(reference manual account the rule of data package) */
|
||||
ADC_COMMON_DMAMODE_3 = 0x03, /*!< dma mode3: each dma request trans two bytes data(reference manual account the rule of data package) */
|
||||
ADC_COMMON_DMAMODE_4 = 0x04, /*!< dma mode4: each dma request trans three bytes data(reference manual account the rule of data package) */
|
||||
ADC_COMMON_DMAMODE_5 = 0x05 /*!< dma mode5: odd dma request trans two half-word data,even dma request trans a half-word data(reference manual account the rule of data package) */
|
||||
} adc_common_dma_mode_type;
|
||||
|
||||
/**
|
||||
* @brief adc common sampling interval type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_SAMPLING_INTERVAL_5CYCLES = 0x00, /*!< ordinary shifting mode adjacent adc sampling interval 5 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_6CYCLES = 0x01, /*!< ordinary shifting mode adjacent adc sampling interval 6 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_7CYCLES = 0x02, /*!< ordinary shifting mode adjacent adc sampling interval 7 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_8CYCLES = 0x03, /*!< ordinary shifting mode adjacent adc sampling interval 8 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_9CYCLES = 0x04, /*!< ordinary shifting mode adjacent adc sampling interval 9 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_10CYCLES = 0x05, /*!< ordinary shifting mode adjacent adc sampling interval 10 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_11CYCLES = 0x06, /*!< ordinary shifting mode adjacent adc sampling interval 11 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_12CYCLES = 0x07, /*!< ordinary shifting mode adjacent adc sampling interval 12 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_13CYCLES = 0x08, /*!< ordinary shifting mode adjacent adc sampling interval 13 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_14CYCLES = 0x09, /*!< ordinary shifting mode adjacent adc sampling interval 14 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_15CYCLES = 0x0A, /*!< ordinary shifting mode adjacent adc sampling interval 15 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_16CYCLES = 0x0B, /*!< ordinary shifting mode adjacent adc sampling interval 16 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_17CYCLES = 0x0C, /*!< ordinary shifting mode adjacent adc sampling interval 17 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_18CYCLES = 0x0D, /*!< ordinary shifting mode adjacent adc sampling interval 18 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_19CYCLES = 0x0E, /*!< ordinary shifting mode adjacent adc sampling interval 19 adcclk */
|
||||
ADC_SAMPLING_INTERVAL_20CYCLES = 0x0F /*!< ordinary shifting mode adjacent adc sampling interval 20 adcclk */
|
||||
} adc_sampling_interval_type;
|
||||
|
||||
/**
|
||||
* @brief adc conversion resolution type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_RESOLUTION_12B = 0x00, /*!< conversion resolution 12 bit */
|
||||
ADC_RESOLUTION_10B = 0x01, /*!< conversion resolution 10 bit */
|
||||
ADC_RESOLUTION_8B = 0x02, /*!< conversion resolution 8 bit */
|
||||
ADC_RESOLUTION_6B = 0x03 /*!< conversion resolution 6 bit */
|
||||
} adc_resolution_type;
|
||||
|
||||
/**
|
||||
* @brief adc data align type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_RIGHT_ALIGNMENT = 0x00, /*!< data right alignment */
|
||||
ADC_LEFT_ALIGNMENT = 0x01 /*!< data left alignment */
|
||||
} adc_data_align_type;
|
||||
|
||||
/**
|
||||
* @brief adc channel select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_CHANNEL_0 = 0x00, /*!< adc channel 0 */
|
||||
ADC_CHANNEL_1 = 0x01, /*!< adc channel 1 */
|
||||
ADC_CHANNEL_2 = 0x02, /*!< adc channel 2 */
|
||||
ADC_CHANNEL_3 = 0x03, /*!< adc channel 3 */
|
||||
ADC_CHANNEL_4 = 0x04, /*!< adc channel 4 */
|
||||
ADC_CHANNEL_5 = 0x05, /*!< adc channel 5 */
|
||||
ADC_CHANNEL_6 = 0x06, /*!< adc channel 6 */
|
||||
ADC_CHANNEL_7 = 0x07, /*!< adc channel 7 */
|
||||
ADC_CHANNEL_8 = 0x08, /*!< adc channel 8 */
|
||||
ADC_CHANNEL_9 = 0x09, /*!< adc channel 9 */
|
||||
ADC_CHANNEL_10 = 0x0A, /*!< adc channel 10 */
|
||||
ADC_CHANNEL_11 = 0x0B, /*!< adc channel 11 */
|
||||
ADC_CHANNEL_12 = 0x0C, /*!< adc channel 12 */
|
||||
ADC_CHANNEL_13 = 0x0D, /*!< adc channel 13 */
|
||||
ADC_CHANNEL_14 = 0x0E, /*!< adc channel 14 */
|
||||
ADC_CHANNEL_15 = 0x0F, /*!< adc channel 15 */
|
||||
ADC_CHANNEL_16 = 0x10, /*!< adc channel 16 */
|
||||
ADC_CHANNEL_17 = 0x11, /*!< adc channel 17 */
|
||||
ADC_CHANNEL_18 = 0x12 /*!< adc channel 18 */
|
||||
} adc_channel_select_type;
|
||||
|
||||
/**
|
||||
* @brief adc sampletime select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_SAMPLETIME_2_5 = 0x00, /*!< adc sample time 2.5 cycle */
|
||||
ADC_SAMPLETIME_6_5 = 0x01, /*!< adc sample time 6.5 cycle */
|
||||
ADC_SAMPLETIME_12_5 = 0x02, /*!< adc sample time 12.5 cycle */
|
||||
ADC_SAMPLETIME_24_5 = 0x03, /*!< adc sample time 24.5 cycle */
|
||||
ADC_SAMPLETIME_47_5 = 0x04, /*!< adc sample time 47.5 cycle */
|
||||
ADC_SAMPLETIME_92_5 = 0x05, /*!< adc sample time 92.5 cycle */
|
||||
ADC_SAMPLETIME_247_5 = 0x06, /*!< adc sample time 247.5 cycle */
|
||||
ADC_SAMPLETIME_640_5 = 0x07 /*!< adc sample time 640.5 cycle */
|
||||
} adc_sampletime_select_type;
|
||||
|
||||
/**
|
||||
* @brief adc ordinary group trigger event select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_ORDINARY_TRIG_TMR1CH1 = 0x00, /*!< timer1 ch1 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR1CH2 = 0x01, /*!< timer1 ch2 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR1CH3 = 0x02, /*!< timer1 ch3 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR2CH2 = 0x03, /*!< timer2 ch2 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR2CH3 = 0x04, /*!< timer2 ch3 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR2CH4 = 0x05, /*!< timer2 ch4 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR2TRGOUT = 0x06, /*!< timer2 trgout event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR3CH1 = 0x07, /*!< timer3 ch1 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR3TRGOUT = 0x08, /*!< timer3 trgout event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR4CH4 = 0x09, /*!< timer4 ch4 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR5CH1 = 0x0A, /*!< timer5 ch1 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR5CH2 = 0x0B, /*!< timer5 ch2 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR5CH3 = 0x0C, /*!< timer5 ch3 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR8CH1 = 0x0D, /*!< timer8 ch1 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR8TRGOUT = 0x0E, /*!< timer8 trgout event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_EXINT11 = 0x0F, /*!< exint line11 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR20TRGOUT = 0x10, /*!< timer20 trgout event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR20TRGOUT2 = 0x11, /*!< timer20 trgout2 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR20CH1 = 0x12, /*!< timer20 ch1 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR20CH2 = 0x13, /*!< timer20 ch2 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR20CH3 = 0x14, /*!< timer20 ch3 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR8TRGOUT2 = 0x15, /*!< timer8 trgout2 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR1TRGOUT2 = 0x16, /*!< timer1 trgout2 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR4TRGOUT = 0x17, /*!< timer4 trgout event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR6TRGOUT = 0x18, /*!< timer6 trgout event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR3CH4 = 0x19, /*!< timer3 ch4 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR4CH1 = 0x1A, /*!< timer4 ch1 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR1TRGOUT = 0x1B, /*!< timer1 trgout event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR2CH1 = 0x1C, /*!< timer2 ch1 event as trigger source of ordinary sequence */
|
||||
ADC_ORDINARY_TRIG_TMR7TRGOUT = 0x1E /*!< timer7 trgout event as trigger source of ordinary sequence */
|
||||
} adc_ordinary_trig_select_type;
|
||||
|
||||
/**
|
||||
* @brief adc ordinary channel conversion's external_trigger_edge type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_ORDINARY_TRIG_EDGE_NONE = 0x00, /*!< ordinary channels trigger detection disabled */
|
||||
ADC_ORDINARY_TRIG_EDGE_RISING = 0x01, /*!< ordinary channels trigger detection on the rising edge */
|
||||
ADC_ORDINARY_TRIG_EDGE_FALLING = 0x02, /*!< ordinary channels trigger detection on the falling edge */
|
||||
ADC_ORDINARY_TRIG_EDGE_RISING_FALLING = 0x03 /*!< ordinary channels trigger detection on both the rising and falling edges */
|
||||
} adc_ordinary_trig_edge_type;
|
||||
|
||||
/**
|
||||
* @brief adc preempt group external trigger event select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_PREEMPT_TRIG_TMR1CH4 = 0x00, /*!< timer1 ch4 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR1TRGOUT = 0x01, /*!< timer1 trgout event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR2CH1 = 0x02, /*!< timer2 ch1 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR2TRGOUT = 0x03, /*!< timer2 trgout event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR3CH2 = 0x04, /*!< timer3 ch2 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR3CH4 = 0x05, /*!< timer3 ch4 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR4CH1 = 0x06, /*!< timer4 ch1 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR4CH2 = 0x07, /*!< timer4 ch2 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR4CH3 = 0x08, /*!< timer4 ch3 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR4TRGOUT = 0x09, /*!< timer4 trgout event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR5CH4 = 0x0A, /*!< timer5 ch4 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR5TRGOUT = 0x0B, /*!< timer5 trgout event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR8CH2 = 0x0C, /*!< timer8 ch2 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR8CH3 = 0x0D, /*!< timer8 ch3 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR8CH4 = 0x0E, /*!< timer8 ch4 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_EXINT15 = 0x0F, /*!< exint line15 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR20TRGOUT = 0x10, /*!< timer20 trgout event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR20TRGOUT2 = 0x11, /*!< timer20 trgout2 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR20CH4 = 0x12, /*!< timer20 ch4 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR1TRGOUT2 = 0x13, /*!< timer1 trgout2 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR8TRGOUT = 0x14, /*!< timer8 trgout event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR8TRGOUT2 = 0x15, /*!< timer8 trgout2 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR3CH3 = 0x16, /*!< timer3 ch3 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR3TRGOUT = 0x17, /*!< timer3 trgout event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR3CH1 = 0x18, /*!< timer3 ch1 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR6TRGOUT = 0x19, /*!< timer6 trgout event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR4CH4 = 0x1A, /*!< timer4 ch4 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR1CH3 = 0x1B, /*!< timer1 ch3 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR20CH2 = 0x1C, /*!< timer20 ch2 event as trigger source of preempt sequence */
|
||||
ADC_PREEMPT_TRIG_TMR7TRGOUT = 0x1E /*!< timer7 trgout event as trigger source of preempt sequence */
|
||||
} adc_preempt_trig_select_type;
|
||||
|
||||
/**
|
||||
* @brief adc preempt channel conversion's external_trigger_edge type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_PREEMPT_TRIG_EDGE_NONE = 0x00, /*!< preempt channels trigger detection disabled */
|
||||
ADC_PREEMPT_TRIG_EDGE_RISING = 0x01, /*!< preempt channels trigger detection on the rising edge */
|
||||
ADC_PREEMPT_TRIG_EDGE_FALLING = 0x02, /*!< preempt channels trigger detection on the falling edge */
|
||||
ADC_PREEMPT_TRIG_EDGE_RISING_FALLING = 0x03 /*!< preempt channels trigger detection on both the rising and falling edges */
|
||||
} adc_preempt_trig_edge_type;
|
||||
|
||||
/**
|
||||
* @brief adc preempt channel type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_PREEMPT_CHANNEL_1 = 0x00, /*!< adc preempt channel 1 */
|
||||
ADC_PREEMPT_CHANNEL_2 = 0x01, /*!< adc preempt channel 2 */
|
||||
ADC_PREEMPT_CHANNEL_3 = 0x02, /*!< adc preempt channel 3 */
|
||||
ADC_PREEMPT_CHANNEL_4 = 0x03 /*!< adc preempt channel 4 */
|
||||
} adc_preempt_channel_type;
|
||||
|
||||
/**
|
||||
* @brief adc voltage_monitoring type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_VMONITOR_SINGLE_ORDINARY = 0x00800200, /*!< voltage_monitoring on a single ordinary channel */
|
||||
ADC_VMONITOR_SINGLE_PREEMPT = 0x00400200, /*!< voltage_monitoring on a single preempt channel */
|
||||
ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT = 0x00C00200, /*!< voltage_monitoring on a single ordinary or preempt channel */
|
||||
ADC_VMONITOR_ALL_ORDINARY = 0x00800000, /*!< voltage_monitoring on all ordinary channel */
|
||||
ADC_VMONITOR_ALL_PREEMPT = 0x00400000, /*!< voltage_monitoring on all preempt channel */
|
||||
ADC_VMONITOR_ALL_ORDINARY_PREEMPT = 0x00C00000, /*!< voltage_monitoring on all ordinary and preempt channel */
|
||||
ADC_VMONITOR_NONE = 0x00000000 /*!< no channel guarded by the voltage_monitoring */
|
||||
} adc_voltage_monitoring_type;
|
||||
|
||||
/**
|
||||
* @brief adc oversample ratio type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_OVERSAMPLE_RATIO_2 = 0x00, /*!< adc oversample ratio 2 */
|
||||
ADC_OVERSAMPLE_RATIO_4 = 0x01, /*!< adc oversample ratio 4 */
|
||||
ADC_OVERSAMPLE_RATIO_8 = 0x02, /*!< adc oversample ratio 8 */
|
||||
ADC_OVERSAMPLE_RATIO_16 = 0x03, /*!< adc oversample ratio 16 */
|
||||
ADC_OVERSAMPLE_RATIO_32 = 0x04, /*!< adc oversample ratio 32 */
|
||||
ADC_OVERSAMPLE_RATIO_64 = 0x05, /*!< adc oversample ratio 64 */
|
||||
ADC_OVERSAMPLE_RATIO_128 = 0x06, /*!< adc oversample ratio 128 */
|
||||
ADC_OVERSAMPLE_RATIO_256 = 0x07 /*!< adc oversample ratio 256 */
|
||||
} adc_oversample_ratio_type;
|
||||
|
||||
/**
|
||||
* @brief adc oversample shift type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_OVERSAMPLE_SHIFT_0 = 0x00, /*!< adc oversample shift 0 */
|
||||
ADC_OVERSAMPLE_SHIFT_1 = 0x01, /*!< adc oversample shift 1 */
|
||||
ADC_OVERSAMPLE_SHIFT_2 = 0x02, /*!< adc oversample shift 2 */
|
||||
ADC_OVERSAMPLE_SHIFT_3 = 0x03, /*!< adc oversample shift 3 */
|
||||
ADC_OVERSAMPLE_SHIFT_4 = 0x04, /*!< adc oversample shift 4 */
|
||||
ADC_OVERSAMPLE_SHIFT_5 = 0x05, /*!< adc oversample shift 5 */
|
||||
ADC_OVERSAMPLE_SHIFT_6 = 0x06, /*!< adc oversample shift 6 */
|
||||
ADC_OVERSAMPLE_SHIFT_7 = 0x07, /*!< adc oversample shift 7 */
|
||||
ADC_OVERSAMPLE_SHIFT_8 = 0x08 /*!< adc oversample shift 8 */
|
||||
} adc_oversample_shift_type;
|
||||
|
||||
/**
|
||||
* @brief adc ordinary oversample recover type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_OVERSAMPLE_CONTINUE = 0x00, /*!< continue mode:when preempt triggered,oversampling is temporary stopped and continued after preempt sequence */
|
||||
ADC_OVERSAMPLE_RESTART = 0x01 /*!< restart mode:when preempt triggered,oversampling is aborted and resumed from start after preempt sequence */
|
||||
} adc_ordinary_oversample_restart_type;
|
||||
|
||||
/**
|
||||
* @brief adc common config type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
adc_combine_mode_type combine_mode; /*!< adc combine mode select */
|
||||
adc_div_type div; /*!< adc division select */
|
||||
adc_common_dma_mode_type common_dma_mode; /*!< adc common dma mode select */
|
||||
confirm_state common_dma_request_repeat_state; /*!< adc common dma repeat state */
|
||||
adc_sampling_interval_type sampling_interval; /*!< ordinary shifting mode adjacent adc sampling interval select */
|
||||
confirm_state tempervintrv_state; /*!< adc temperature sensor and vintrv state */
|
||||
confirm_state vbat_state; /*!< adc voltage battery state */
|
||||
} adc_common_config_type;
|
||||
|
||||
/**
|
||||
* @brief adc base config type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
confirm_state sequence_mode; /*!< adc sequence mode */
|
||||
confirm_state repeat_mode; /*!< adc repeat mode */
|
||||
adc_data_align_type data_align; /*!< adc data alignment */
|
||||
uint8_t ordinary_channel_length; /*!< adc ordinary channel sequence length*/
|
||||
} adc_base_config_type;
|
||||
|
||||
/**
|
||||
* @brief type define adc register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief adc sts register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vmor : 1; /* [0] */
|
||||
__IO uint32_t occe : 1; /* [1] */
|
||||
__IO uint32_t pcce : 1; /* [2] */
|
||||
__IO uint32_t pccs : 1; /* [3] */
|
||||
__IO uint32_t occs : 1; /* [4] */
|
||||
__IO uint32_t occo : 1; /* [5] */
|
||||
__IO uint32_t rdy : 1; /* [6] */
|
||||
__IO uint32_t reserved1 : 25;/* [31:7] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc ctrl1 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vmcsel : 5; /* [4:0] */
|
||||
__IO uint32_t occeien : 1; /* [5] */
|
||||
__IO uint32_t vmorien : 1; /* [6] */
|
||||
__IO uint32_t pcceien : 1; /* [7] */
|
||||
__IO uint32_t sqen : 1; /* [8] */
|
||||
__IO uint32_t vmsgen : 1; /* [9] */
|
||||
__IO uint32_t pcautoen : 1; /* [10] */
|
||||
__IO uint32_t ocpen : 1; /* [11] */
|
||||
__IO uint32_t pcpen : 1; /* [12] */
|
||||
__IO uint32_t ocpcnt : 3; /* [15:13] */
|
||||
__IO uint32_t reserved1 : 6; /* [21:16] */
|
||||
__IO uint32_t pcvmen : 1; /* [22] */
|
||||
__IO uint32_t ocvmen : 1; /* [23] */
|
||||
__IO uint32_t crsel : 2; /* [25:24] */
|
||||
__IO uint32_t occoien : 1; /* [26] */
|
||||
__IO uint32_t reserved2 : 5; /* [31:27] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc ctrl2 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t adcen : 1; /* [0] */
|
||||
__IO uint32_t rpen : 1; /* [1] */
|
||||
__IO uint32_t adcal : 1; /* [2] */
|
||||
__IO uint32_t adcalinit : 1; /* [3] */
|
||||
__IO uint32_t adabrt : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 3; /* [7:5] */
|
||||
__IO uint32_t ocdmaen : 1; /* [8] */
|
||||
__IO uint32_t ocdrcen : 1; /* [9] */
|
||||
__IO uint32_t eocsfen : 1; /* [10] */
|
||||
__IO uint32_t dtalign : 1; /* [11] */
|
||||
__IO uint32_t reserved2 : 4; /* [15:12] */
|
||||
__IO uint32_t pctesel_l : 4; /* [19:16] */
|
||||
__IO uint32_t pcete : 2; /* [21:20] */
|
||||
__IO uint32_t pcswtrg : 1; /* [22] */
|
||||
__IO uint32_t pctesel_h : 1; /* [23] */
|
||||
__IO uint32_t octesel_l : 4; /* [27:24] */
|
||||
__IO uint32_t ocete : 2; /* [29:28] */
|
||||
__IO uint32_t ocswtrg : 1; /* [30] */
|
||||
__IO uint32_t octesel_h : 1; /* [31] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc spt1 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t spt1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cspt10 : 3; /* [2:0] */
|
||||
__IO uint32_t cspt11 : 3; /* [5:3] */
|
||||
__IO uint32_t cspt12 : 3; /* [8:6] */
|
||||
__IO uint32_t cspt13 : 3; /* [11:9] */
|
||||
__IO uint32_t cspt14 : 3; /* [14:12] */
|
||||
__IO uint32_t cspt15 : 3; /* [17:15] */
|
||||
__IO uint32_t cspt16 : 3; /* [20:18] */
|
||||
__IO uint32_t cspt17 : 3; /* [23:21] */
|
||||
__IO uint32_t cspt18 : 3; /* [26:24] */
|
||||
__IO uint32_t reserved1 : 5;/* [31:27] */
|
||||
} spt1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc spt2 register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t spt2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cspt0 : 3;/* [2:0] */
|
||||
__IO uint32_t cspt1 : 3;/* [5:3] */
|
||||
__IO uint32_t cspt2 : 3;/* [8:6] */
|
||||
__IO uint32_t cspt3 : 3;/* [11:9] */
|
||||
__IO uint32_t cspt4 : 3;/* [14:12] */
|
||||
__IO uint32_t cspt5 : 3;/* [17:15] */
|
||||
__IO uint32_t cspt6 : 3;/* [20:18] */
|
||||
__IO uint32_t cspt7 : 3;/* [23:21] */
|
||||
__IO uint32_t cspt8 : 3;/* [26:24] */
|
||||
__IO uint32_t cspt9 : 3;/* [29:27] */
|
||||
__IO uint32_t reserved1 : 2;/* [31:30] */
|
||||
} spt2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pcdto1 register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pcdto1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pcdto1 : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} pcdto1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pcdto2 register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pcdto2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pcdto2 : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} pcdto2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pcdto3 register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pcdto3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pcdto3 : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} pcdto3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pcdto4 register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pcdto4;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pcdto4 : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} pcdto4_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc vmhb register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t vmhb;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vmhb : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} vmhb_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc vmlb register, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t vmlb;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vmlb : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} vmlb_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc osq1 register, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t osq1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t osn13 : 5; /* [4:0] */
|
||||
__IO uint32_t osn14 : 5; /* [9:5] */
|
||||
__IO uint32_t osn15 : 5; /* [14:10] */
|
||||
__IO uint32_t osn16 : 5; /* [19:15] */
|
||||
__IO uint32_t oclen : 4; /* [23:20] */
|
||||
__IO uint32_t reserved1 : 8; /* [31:24] */
|
||||
} osq1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc osq2 register, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t osq2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t osn7 : 5; /* [4:0] */
|
||||
__IO uint32_t osn8 : 5; /* [9:5] */
|
||||
__IO uint32_t osn9 : 5; /* [14:10] */
|
||||
__IO uint32_t osn10 : 5; /* [19:15] */
|
||||
__IO uint32_t osn11 : 5; /* [24:20] */
|
||||
__IO uint32_t osn12 : 5; /* [29:25] */
|
||||
__IO uint32_t reserved1 : 2; /* [31:30] */
|
||||
} osq2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc osq3 register, offset:0x34
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t osq3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t osn1 : 5; /* [4:0] */
|
||||
__IO uint32_t osn2 : 5; /* [9:5] */
|
||||
__IO uint32_t osn3 : 5; /* [14:10] */
|
||||
__IO uint32_t osn4 : 5; /* [19:15] */
|
||||
__IO uint32_t osn5 : 5; /* [24:20] */
|
||||
__IO uint32_t osn6 : 5; /* [29:25] */
|
||||
__IO uint32_t reserved1 : 2; /* [31:30] */
|
||||
} osq3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc psq register, offset:0x38
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t psq;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t psn1 : 5; /* [4:0] */
|
||||
__IO uint32_t psn2 : 5; /* [9:5] */
|
||||
__IO uint32_t psn3 : 5; /* [14:10] */
|
||||
__IO uint32_t psn4 : 5; /* [19:15] */
|
||||
__IO uint32_t pclen : 2; /* [21:20] */
|
||||
__IO uint32_t reserved1 : 10;/* [31:22] */
|
||||
} psq_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pdt1 register, offset:0x3C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pdt1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pdt1 : 16; /* [15:0] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} pdt1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pdt2 register, offset:0x40
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pdt2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pdt2 : 16; /* [15:0] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} pdt2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pdt3 register, offset:0x44
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pdt3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pdt3 : 16; /* [15:0] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} pdt3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pdt4 register, offset:0x48
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pdt4;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pdt4 : 16; /* [15:0] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} pdt4_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc odt register, offset:0x4C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t odt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t odt : 16; /* [15:0] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} odt_bit;
|
||||
};
|
||||
|
||||
__IO uint32_t reserved1[12];
|
||||
|
||||
/**
|
||||
* @brief adc ovsp register, offset:0x80
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ovsp;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t oosen : 1; /* [0] */
|
||||
__IO uint32_t posen : 1; /* [1] */
|
||||
__IO uint32_t osrsel : 3; /* [4:2] */
|
||||
__IO uint32_t osssel : 4; /* [8:5] */
|
||||
__IO uint32_t oostren : 1; /* [9] */
|
||||
__IO uint32_t oosrsel : 1; /* [10] */
|
||||
__IO uint32_t reserved1 : 21; /* [31:11] */
|
||||
} ovsp_bit;
|
||||
};
|
||||
|
||||
__IO uint32_t reserved2[12];
|
||||
|
||||
/**
|
||||
* @brief adc calval register, offset:0xB4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t calval;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t calval : 7; /* [6:0] */
|
||||
__IO uint32_t reserved1 : 25; /* [31:7] */
|
||||
} calval_bit;
|
||||
};
|
||||
} adc_type;
|
||||
|
||||
/**
|
||||
* @brief type define adc register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief adc csts register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t csts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vmor1 : 1; /* [0] */
|
||||
__IO uint32_t occe1 : 1; /* [1] */
|
||||
__IO uint32_t pcce1 : 1; /* [2] */
|
||||
__IO uint32_t pccs1 : 1; /* [3] */
|
||||
__IO uint32_t occs1 : 1; /* [4] */
|
||||
__IO uint32_t occo1 : 1; /* [5] */
|
||||
__IO uint32_t rdy1 : 1; /* [6] */
|
||||
__IO uint32_t reserved1 : 1; /* [7] */
|
||||
__IO uint32_t vmor2 : 1; /* [8] */
|
||||
__IO uint32_t occe2 : 1; /* [9] */
|
||||
__IO uint32_t pcce2 : 1; /* [10] */
|
||||
__IO uint32_t pccs2 : 1; /* [11] */
|
||||
__IO uint32_t occs2 : 1; /* [12] */
|
||||
__IO uint32_t occo2 : 1; /* [13] */
|
||||
__IO uint32_t rdy2 : 1; /* [14] */
|
||||
__IO uint32_t reserved2 : 1; /* [15] */
|
||||
__IO uint32_t vmor3 : 1; /* [16] */
|
||||
__IO uint32_t occe3 : 1; /* [17] */
|
||||
__IO uint32_t pcce3 : 1; /* [18] */
|
||||
__IO uint32_t pccs3 : 1; /* [19] */
|
||||
__IO uint32_t occs3 : 1; /* [20] */
|
||||
__IO uint32_t occo3 : 1; /* [21] */
|
||||
__IO uint32_t rdy3 : 1; /* [22] */
|
||||
__IO uint32_t reserved3 : 9; /* [31:23] */
|
||||
} csts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc cctrl register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t mssel : 5; /* [4_0] */
|
||||
__IO uint32_t reserved1 : 3; /* [7:5] */
|
||||
__IO uint32_t asisel : 4; /* [11:8] */
|
||||
__IO uint32_t reserved2 : 1; /* [12] */
|
||||
__IO uint32_t msdrcen : 1; /* [13] */
|
||||
__IO uint32_t msdmasel_l : 2; /* [15:14] */
|
||||
__IO uint32_t adcdiv : 4; /* [19:16] */
|
||||
__IO uint32_t reserved3 : 2; /* [21:20] */
|
||||
__IO uint32_t vbaten : 1; /* [22] */
|
||||
__IO uint32_t itsrven : 1; /* [23] */
|
||||
__IO uint32_t reserved4 : 4; /* [27:24] */
|
||||
__IO uint32_t msdmasel_h : 1; /* [28] */
|
||||
__IO uint32_t reserved5 : 3; /* [31:29] */
|
||||
} cctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc codt register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t codt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t codtl : 16; /* [15:0] */
|
||||
__IO uint32_t codth : 16; /* [31:16] */
|
||||
} codt_bit;
|
||||
};
|
||||
} adccom_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define ADC1 ((adc_type *) ADC1_BASE)
|
||||
#define ADC2 ((adc_type *) ADC2_BASE)
|
||||
#define ADC3 ((adc_type *) ADC3_BASE)
|
||||
#define ADCCOM ((adccom_type *) ADCCOM_BASE)
|
||||
|
||||
/** @defgroup ADC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void adc_reset(void);
|
||||
void adc_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_base_default_para_init(adc_base_config_type *adc_base_struct);
|
||||
void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct);
|
||||
void adc_common_default_para_init(adc_common_config_type *adc_common_struct);
|
||||
void adc_common_config(adc_common_config_type *adc_common_struct);
|
||||
void adc_resolution_set(adc_type *adc_x, adc_resolution_type resolution);
|
||||
void adc_voltage_battery_enable(confirm_state new_state);
|
||||
void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_dma_request_repeat_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state);
|
||||
void adc_calibration_value_set(adc_type *adc_x, uint8_t adc_calibration_value);
|
||||
void adc_calibration_init(adc_type *adc_x);
|
||||
flag_status adc_calibration_init_status_get(adc_type *adc_x);
|
||||
void adc_calibration_start(adc_type *adc_x);
|
||||
flag_status adc_calibration_status_get(adc_type *adc_x);
|
||||
void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring);
|
||||
void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold);
|
||||
void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel);
|
||||
void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
|
||||
void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght);
|
||||
void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
|
||||
void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, adc_ordinary_trig_edge_type adc_ordinary_trig_edge);
|
||||
void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, adc_preempt_trig_edge_type adc_preempt_trig_edge);
|
||||
void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value);
|
||||
void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count);
|
||||
void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_conversion_stop(adc_type *adc_x);
|
||||
flag_status adc_conversion_stop_status_get(adc_type *adc_x);
|
||||
void adc_occe_each_conversion_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
|
||||
flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x);
|
||||
void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
|
||||
flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x);
|
||||
uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
|
||||
uint32_t adc_combine_ordinary_conversion_data_get(void);
|
||||
uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
|
||||
flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
|
||||
void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
|
||||
void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_oversample_ratio_shift_set(adc_type *adc_x, adc_oversample_ratio_type adc_oversample_ratio, adc_oversample_shift_type adc_oversample_shift);
|
||||
void adc_ordinary_oversample_trig_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_ordinary_oversample_restart_set(adc_type *adc_x, adc_ordinary_oversample_restart_type adc_ordinary_oversample_restart);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,172 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_crc.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 crc header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_CRC_H
|
||||
#define __AT32F435_437_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief crc reverse input data
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRC_REVERSE_INPUT_NO_AFFECTE = 0x00, /*!< input data no reverse */
|
||||
CRC_REVERSE_INPUT_BY_BYTE = 0x01, /*!< input data reverse by byte */
|
||||
CRC_REVERSE_INPUT_BY_HALFWORD = 0x02, /*!< input data reverse by half word */
|
||||
CRC_REVERSE_INPUT_BY_WORD = 0x03 /*!< input data reverse by word */
|
||||
} crc_reverse_input_type;
|
||||
|
||||
/**
|
||||
* @brief crc reverse output data
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRC_REVERSE_OUTPUT_NO_AFFECTE = 0x00, /*!< output data no reverse */
|
||||
CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */
|
||||
} crc_reverse_output_type;
|
||||
|
||||
/**
|
||||
* @brief type define crc register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief crc dt register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 32; /* [31:0] */
|
||||
} dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crc cdt register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cdt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cdt : 8 ; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24 ;/* [31:8] */
|
||||
} cdt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crc ctrl register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rst : 1 ; /* [0] */
|
||||
__IO uint32_t reserved1 : 4 ; /* [4:1] */
|
||||
__IO uint32_t revid : 2 ; /* [6:5] */
|
||||
__IO uint32_t revod : 1 ; /* [7] */
|
||||
__IO uint32_t reserved2 : 24 ;/* [31:8] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm reserved1 register, offset:0x0C
|
||||
*/
|
||||
__IO uint32_t reserved1;
|
||||
|
||||
/**
|
||||
* @brief crc idt register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t idt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t idt : 32; /* [31:0] */
|
||||
} idt_bit;
|
||||
};
|
||||
|
||||
} crc_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define CRC ((crc_type *) CRC_BASE)
|
||||
|
||||
/** @defgroup CRC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void crc_data_reset(void);
|
||||
uint32_t crc_one_word_calculate(uint32_t data);
|
||||
uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length);
|
||||
uint32_t crc_data_get(void);
|
||||
void crc_common_data_set(uint8_t cdt_value);
|
||||
uint8_t crc_common_date_get(void);
|
||||
void crc_init_data_set(uint32_t value);
|
||||
void crc_reverse_input_data_set(crc_reverse_input_type value);
|
||||
void crc_reverse_output_data_set(crc_reverse_output_type value);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,394 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_dac.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 dac header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_DAC_H
|
||||
#define __AT32F435_437_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC1_D1DMAUDRF ((uint32_t)(0x00002000))
|
||||
#define DAC2_D2DMAUDRF ((uint32_t)(0x20000000))
|
||||
|
||||
/** @defgroup DAC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief dac select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC1_SELECT = 0x01, /*!< dac1 select */
|
||||
DAC2_SELECT = 0x02 /*!< dac2 select */
|
||||
} dac_select_type;
|
||||
|
||||
/**
|
||||
* @brief dac trigger type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_TMR6_TRGOUT_EVENT = 0x00, /*!< dac trigger selection:timer6 trgout event */
|
||||
DAC_TMR8_TRGOUT_EVENT = 0x01, /*!< dac trigger selection:timer8 trgout event */
|
||||
DAC_TMR7_TRGOUT_EVENT = 0x02, /*!< dac trigger selection:timer7 trgout event */
|
||||
DAC_TMR5_TRGOUT_EVENT = 0x03, /*!< dac trigger selection:timer5 trgout event */
|
||||
DAC_TMR2_TRGOUT_EVENT = 0x04, /*!< dac trigger selection:timer2 trgout event */
|
||||
DAC_TMR4_TRGOUT_EVENT = 0x05, /*!< dac trigger selection:timer4 trgout event */
|
||||
DAC_EXTERNAL_INTERRUPT_LINE_9 = 0x06, /*!< dac trigger selection:external line9 */
|
||||
DAC_SOFTWARE_TRIGGER = 0x07 /*!< dac trigger selection:software trigger */
|
||||
} dac_trigger_type;
|
||||
|
||||
/**
|
||||
* @brief dac wave type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_WAVE_GENERATE_NONE = 0x00, /*!< dac wave generation disabled */
|
||||
DAC_WAVE_GENERATE_NOISE = 0x01, /*!< dac noise wave generation enabled */
|
||||
DAC_WAVE_GENERATE_TRIANGLE = 0x02 /*!< dac triangle wave generation enabled */
|
||||
} dac_wave_type;
|
||||
|
||||
/**
|
||||
* @brief dac mask amplitude type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_LSFR_BIT0_AMPLITUDE_1 = 0x00, /*!< unmask bit0/ triangle amplitude equal to 1 */
|
||||
DAC_LSFR_BIT10_AMPLITUDE_3 = 0x01, /*!< unmask bit[1:0]/ triangle amplitude equal to 3 */
|
||||
DAC_LSFR_BIT20_AMPLITUDE_7 = 0x02, /*!< unmask bit[2:0]/ triangle amplitude equal to 7 */
|
||||
DAC_LSFR_BIT30_AMPLITUDE_15 = 0x03, /*!< unmask bit[3:0]/ triangle amplitude equal to 15 */
|
||||
DAC_LSFR_BIT40_AMPLITUDE_31 = 0x04, /*!< unmask bit[4:0]/ triangle amplitude equal to 31 */
|
||||
DAC_LSFR_BIT50_AMPLITUDE_63 = 0x05, /*!< unmask bit[5:0]/ triangle amplitude equal to 63 */
|
||||
DAC_LSFR_BIT60_AMPLITUDE_127 = 0x06, /*!< unmask bit[6:0]/ triangle amplitude equal to 127 */
|
||||
DAC_LSFR_BIT70_AMPLITUDE_255 = 0x07, /*!< unmask bit[7:0]/ triangle amplitude equal to 255 */
|
||||
DAC_LSFR_BIT80_AMPLITUDE_511 = 0x08, /*!< unmask bit[8:0]/ triangle amplitude equal to 511 */
|
||||
DAC_LSFR_BIT90_AMPLITUDE_1023 = 0x09, /*!< unmask bit[9:0]/ triangle amplitude equal to 1023 */
|
||||
DAC_LSFR_BITA0_AMPLITUDE_2047 = 0x0A, /*!< unmask bit[10:0]/ triangle amplitude equal to 2047 */
|
||||
DAC_LSFR_BITB0_AMPLITUDE_4095 = 0x0B /*!< unmask bit[11:0]/ triangle amplitude equal to 4095 */
|
||||
} dac_mask_amplitude_type;
|
||||
|
||||
/**
|
||||
* @brief dac1 aligned data type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC1_12BIT_RIGHT = 0x40007408, /*!< dac1 12-bit data right-aligned */
|
||||
DAC1_12BIT_LEFT = 0x4000740C, /*!< dac1 12-bit data left-aligned */
|
||||
DAC1_8BIT_RIGHT = 0x40007410 /*!< dac1 8-bit data right-aligned */
|
||||
} dac1_aligned_data_type;
|
||||
|
||||
/**
|
||||
* @brief dac2 aligned data type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC2_12BIT_RIGHT = 0x40007414, /*!< dac2 12-bit data right-aligned */
|
||||
DAC2_12BIT_LEFT = 0x40007418, /*!< dac2 12-bit data left-aligned */
|
||||
DAC2_8BIT_RIGHT = 0x4000741C /*!< dac2 8-bit data right-aligned */
|
||||
} dac2_aligned_data_type;
|
||||
|
||||
/**
|
||||
* @brief dac dual data type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_DUAL_12BIT_RIGHT = 0x40007420, /*!<double dac 12-bit data right-aligned */
|
||||
DAC_DUAL_12BIT_LEFT = 0x40007424, /*!<double dac 12-bit data left-aligned */
|
||||
DAC_DUAL_8BIT_RIGHT = 0x40007428 /*!<double dac 8-bit data right-aligned */
|
||||
} dac_dual_data_type;
|
||||
|
||||
/**
|
||||
* @brief type define dac register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief dac ctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1en : 1; /* [0] */
|
||||
__IO uint32_t d1obdis : 1; /* [1] */
|
||||
__IO uint32_t d1trgen : 1; /* [2] */
|
||||
__IO uint32_t d1trgsel : 3; /* [5:3] */
|
||||
__IO uint32_t d1nm : 2; /* [7:6] */
|
||||
__IO uint32_t d1nbsel : 4; /* [11:8] */
|
||||
__IO uint32_t d1dmaen : 1; /* [12] */
|
||||
__IO uint32_t d1dmaudrien : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 2; /* [15:14] */
|
||||
__IO uint32_t d2en : 1; /* [16] */
|
||||
__IO uint32_t d2obdis : 1; /* [17] */
|
||||
__IO uint32_t d2trgen : 1; /* [18] */
|
||||
__IO uint32_t d2trgsel : 3; /* [21:19] */
|
||||
__IO uint32_t d2nm : 2; /* [23:22] */
|
||||
__IO uint32_t d2nbsel : 4; /* [27:24] */
|
||||
__IO uint32_t d2dmaen : 1; /* [28] */
|
||||
__IO uint32_t d2dmaudrien : 1; /* [29] */
|
||||
__IO uint32_t reserved2 : 2; /* [31:30] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac swtrg register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t swtrg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1swtrg : 1; /* [0] */
|
||||
__IO uint32_t d2swtrg : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 30;/* [31:2] */
|
||||
} swtrg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d1dth12r register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d1dth12r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1dt12r : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:2] */
|
||||
} d1dth12r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d1dth12l register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d1dth12l;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1dt12l : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:2] */
|
||||
} d1dth12l_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d1dth8r register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d1dth8r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1dt8r : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} d1dth8r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d2dth12r register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d2dth12r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d2dt12r : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:2] */
|
||||
} d2dth12r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d2dth12l register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d2dth12l;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d2dt12l : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:2] */
|
||||
} d2dth12l_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d2dth8r register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d2dth8r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d2dt8r : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} d2dth8r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac ddth12r register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ddth12r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dd1dt12r : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 4; /* [15:12] */
|
||||
__IO uint32_t dd2dt12r : 12;/* [27:16] */
|
||||
__IO uint32_t reserved2 : 4; /* [31:28] */
|
||||
} ddth12r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac ddth12l register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ddth12l;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 4; /* [3:0] */
|
||||
__IO uint32_t dd1dt12l : 12;/* [15:4] */
|
||||
__IO uint32_t reserved2 : 4; /* [19:16] */
|
||||
__IO uint32_t dd2dt12l : 12;/* [31:20] */
|
||||
} ddth12l_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac ddth8r register, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ddth8r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dd1dt8r : 8; /* [7:0] */
|
||||
__IO uint32_t dd2dt8r : 8; /* [15:8] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} ddth8r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d1odt register, offset:0x2c
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d1odt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1odt : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} d1odt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d2odt register, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d2odt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d2odt : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} d2odt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac sr register, offset:0x34
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 13;/* [12:0] */
|
||||
__IO uint32_t d1dmaudrf : 1; /* [13] */
|
||||
__IO uint32_t reserved2 : 15;/* [28:14] */
|
||||
__IO uint32_t d2dmaudrf : 1; /* [29] */
|
||||
__IO uint32_t reserved3 : 2;/* [31:30] */
|
||||
} sts_bit;
|
||||
};
|
||||
} dac_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define DAC ((dac_type *) DAC_BASE)
|
||||
|
||||
/** @defgroup DAC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void dac_reset(void);
|
||||
void dac_enable(dac_select_type dac_select, confirm_state new_state);
|
||||
void dac_output_buffer_enable(dac_select_type dac_select, confirm_state new_state);
|
||||
void dac_trigger_enable(dac_select_type dac_select, confirm_state new_state);
|
||||
void dac_trigger_select(dac_select_type dac_select, dac_trigger_type dac_trigger_select);
|
||||
void dac_software_trigger_generate(dac_select_type dac_select);
|
||||
void dac_dual_software_trigger_generate(void);
|
||||
void dac_wave_generate(dac_select_type dac_select, dac_wave_type dac_wave);
|
||||
void dac_mask_amplitude_select(dac_select_type dac_select, dac_mask_amplitude_type dac_mask_amplitude);
|
||||
void dac_dma_enable(dac_select_type dac_select, confirm_state new_state);
|
||||
uint16_t dac_data_output_get(dac_select_type dac_select);
|
||||
void dac_1_data_set(dac1_aligned_data_type dac1_aligned, uint16_t dac1_data);
|
||||
void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data);
|
||||
void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2);
|
||||
void dac_udr_enable(dac_select_type dac_select, confirm_state new_state);
|
||||
flag_status dac_udr_flag_get(dac_select_type dac_select);
|
||||
void dac_udr_flag_clear(dac_select_type dac_select);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,208 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_mcudbg.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 mcudbg header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_MCUDBG_H
|
||||
#define __AT32F435_437_MCUDBG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DEBUG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DEBUG_mode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* debug ctrl register bit */
|
||||
#define DEBUG_SLEEP 0x00000001 /*!< debug sleep mode */
|
||||
#define DEBUG_DEEPSLEEP 0x00000002 /*!< debug deepsleep mode */
|
||||
#define DEBUG_STANDBY 0x00000004 /*!< debug standby mode */
|
||||
|
||||
/* debug apb1 frz register bit */
|
||||
#define DEBUG_TMR2_PAUSE 0x00000001 /*!< debug timer2 pause */
|
||||
#define DEBUG_TMR3_PAUSE 0x00000002 /*!< debug timer3 pause */
|
||||
#define DEBUG_TMR4_PAUSE 0x00000004 /*!< debug timer4 pause */
|
||||
#define DEBUG_TMR5_PAUSE 0x00000008 /*!< debug timer5 pause */
|
||||
#define DEBUG_TMR6_PAUSE 0x00000010 /*!< debug timer6 pause */
|
||||
#define DEBUG_TMR7_PAUSE 0x00000020 /*!< debug timer7 pause */
|
||||
#define DEBUG_TMR12_PAUSE 0x00000040 /*!< debug timer12 pause */
|
||||
#define DEBUG_TMR13_PAUSE 0x00000080 /*!< debug timer13 pause */
|
||||
#define DEBUG_TMR14_PAUSE 0x00000100 /*!< debug timer14 pause */
|
||||
#define DEBUG_ERTC_PAUSE 0x00000400 /*!< debug ertc pause */
|
||||
#define DEBUG_WWDT_PAUSE 0x00000800 /*!< debug watchdog timer pause */
|
||||
#define DEBUG_WDT_PAUSE 0x00001000 /*!< debug window watchdog timer pause */
|
||||
#define DEBUG_ERTC_512_PAUSE 0x00008000 /*!< debug ertc_512 pause */
|
||||
#define DEBUG_I2C1_SMBUS_TIMEOUT 0x01000000 /*!< debug i2c1 smbus timeout */
|
||||
#define DEBUG_I2C2_SMBUS_TIMEOUT 0x08000000 /*!< debug i2c2 smbus timeout */
|
||||
#define DEBUG_I2C3_SMBUS_TIMEOUT 0x10000000 /*!< debug i2c3 smbus timeout */
|
||||
#define DEBUG_CAN1_PAUSE 0x02000000 /*!< debug can1 pause */
|
||||
#define DEBUG_CAN2_PAUSE 0x04000000 /*!< debug can2 pause */
|
||||
|
||||
/* debug apb2 frz register bit */
|
||||
#define DEBUG_TMR1_PAUSE 0x00000001 /*!< debug timer1 pause */
|
||||
#define DEBUG_TMR8_PAUSE 0x00000002 /*!< debug timer8 pause */
|
||||
#define DEBUG_TMR20_PAUSE 0x00000040 /*!< debug timer20 pause */
|
||||
#define DEBUG_TMR9_PAUSE 0x00010000 /*!< debug timer9 pause */
|
||||
#define DEBUG_TMR10_PAUSE 0x00020000 /*!< debug timer10 pause */
|
||||
#define DEBUG_TMR11_PAUSE 0x00040000 /*!< debug timer11 pause */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DEBUG_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief type define debug register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief debug idcode register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pid;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pid : 32;/* [31:0] */
|
||||
} idcode_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief debug ctrl register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t sleep_debug : 1;/* [0] */
|
||||
__IO uint32_t deepsleep_debug : 1;/* [1] */
|
||||
__IO uint32_t standby_debug : 1;/* [2] */
|
||||
__IO uint32_t reserved1 : 29;/* [31:3] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
/**
|
||||
* @brief debug apb1 frz register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t apb1_frz;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmr2_pause : 1;/* [0] */
|
||||
__IO uint32_t tmr3_pause : 1;/* [1] */
|
||||
__IO uint32_t tmr4_pause : 1;/* [2] */
|
||||
__IO uint32_t tim5_pause : 1;/* [3] */
|
||||
__IO uint32_t tim6_pause : 1;/* [4] */
|
||||
__IO uint32_t tim7_pause : 1;/* [5] */
|
||||
__IO uint32_t tim12_pause : 1;/* [6] */
|
||||
__IO uint32_t tim13_pause : 1;/* [7] */
|
||||
__IO uint32_t tim14_pause : 1;/* [8] */
|
||||
__IO uint32_t reserved1 : 1;/* [9] */
|
||||
__IO uint32_t ertc_pause : 1;/* [10] */
|
||||
__IO uint32_t wwdt_pause : 1;/* [11] */
|
||||
__IO uint32_t wdt_pause : 1;/* [12] */
|
||||
__IO uint32_t reserved2 : 2;/* [14:13] */
|
||||
__IO uint32_t ertc_512_pause : 1;/* [15] */
|
||||
__IO uint32_t reserved3 : 8;/* [23:16] */
|
||||
__IO uint32_t i2c1_smbus_timeout : 1;/* [24] */
|
||||
__IO uint32_t can1_pause : 1;/* [25] */
|
||||
__IO uint32_t can2_pause : 1;/* [26] */
|
||||
__IO uint32_t i2c2_smbus_timeout : 1;/* [27] */
|
||||
__IO uint32_t i2c3_smbus_timeout : 1;/* [28] */
|
||||
__IO uint32_t reserved4 : 3;/* [31:29] */
|
||||
} apb1_frz_bit;
|
||||
};
|
||||
/**
|
||||
* @brief debug apb2 frz register, offset:0x0c
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t apb2_frz;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmr1_pause : 1;/* [0] */
|
||||
__IO uint32_t tim8_pause : 1;/* [1] */
|
||||
__IO uint32_t reserved1 : 4;/* [5:2] */
|
||||
__IO uint32_t tim20_pause : 1;/* [6] */
|
||||
__IO uint32_t reserved2 : 9;/* [15:7] */
|
||||
__IO uint32_t tim9_pause : 1;/* [16] */
|
||||
__IO uint32_t tim10_pause : 1;/* [17] */
|
||||
__IO uint32_t tim11_pause : 1;/* [18] */
|
||||
__IO uint32_t reserved3 : 13;/* [31:19] */
|
||||
} apb2_frz_bit;
|
||||
};
|
||||
|
||||
} debug_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define DEBUGMCU ((debug_type *) DEBUG_BASE)
|
||||
|
||||
/** @defgroup DEBUG_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t debug_device_id_get(void);
|
||||
void debug_low_power_mode_set(uint32_t low_power_mode, confirm_state new_state);
|
||||
void debug_apb1_periph_mode_set(uint32_t apb1_periph, confirm_state new_state);
|
||||
void debug_apb2_periph_mode_set(uint32_t apb2_periph, confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,785 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_dma.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 dma header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_DMA_H
|
||||
#define __AT32F435_437_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_interrupts_definition
|
||||
* @brief dma interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_FDT_INT ((uint32_t)0x00000002) /*!< dma full data transfer interrupt */
|
||||
#define DMA_HDT_INT ((uint32_t)0x00000004) /*!< dma half data transfer interrupt */
|
||||
#define DMA_DTERR_INT ((uint32_t)0x00000008) /*!< dma errorr interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flags_definition
|
||||
* @brief edma flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA1_GL1_FLAG ((uint32_t)0x00000001) /*!< dma1 channel1 global flag */
|
||||
#define DMA1_FDT1_FLAG ((uint32_t)0x00000002) /*!< dma1 channel1 full data transfer flag */
|
||||
#define DMA1_HDT1_FLAG ((uint32_t)0x00000004) /*!< dma1 channel1 half data transfer flag */
|
||||
#define DMA1_DTERR1_FLAG ((uint32_t)0x00000008) /*!< dma1 channel1 error flag */
|
||||
#define DMA1_GL2_FLAG ((uint32_t)0x00000010) /*!< dma1 channel2 global flag */
|
||||
#define DMA1_FDT2_FLAG ((uint32_t)0x00000020) /*!< dma1 channel2 full data transfer flag */
|
||||
#define DMA1_HDT2_FLAG ((uint32_t)0x00000040) /*!< dma1 channel2 half data transfer flag */
|
||||
#define DMA1_DTERR2_FLAG ((uint32_t)0x00000080) /*!< dma1 channel2 error flag */
|
||||
#define DMA1_GL3_FLAG ((uint32_t)0x00000100) /*!< dma1 channel3 global flag */
|
||||
#define DMA1_FDT3_FLAG ((uint32_t)0x00000200) /*!< dma1 channel3 full data transfer flag */
|
||||
#define DMA1_HDT3_FLAG ((uint32_t)0x00000400) /*!< dma1 channel3 half data transfer flag */
|
||||
#define DMA1_DTERR3_FLAG ((uint32_t)0x00000800) /*!< dma1 channel3 error flag */
|
||||
#define DMA1_GL4_FLAG ((uint32_t)0x00001000) /*!< dma1 channel4 global flag */
|
||||
#define DMA1_FDT4_FLAG ((uint32_t)0x00002000) /*!< dma1 channel4 full data transfer flag */
|
||||
#define DMA1_HDT4_FLAG ((uint32_t)0x00004000) /*!< dma1 channel4 half data transfer flag */
|
||||
#define DMA1_DTERR4_FLAG ((uint32_t)0x00008000) /*!< dma1 channel4 error flag */
|
||||
#define DMA1_GL5_FLAG ((uint32_t)0x00010000) /*!< dma1 channel5 global flag */
|
||||
#define DMA1_FDT5_FLAG ((uint32_t)0x00020000) /*!< dma1 channel5 full data transfer flag */
|
||||
#define DMA1_HDT5_FLAG ((uint32_t)0x00040000) /*!< dma1 channel5 half data transfer flag */
|
||||
#define DMA1_DTERR5_FLAG ((uint32_t)0x00080000) /*!< dma1 channel5 error flag */
|
||||
#define DMA1_GL6_FLAG ((uint32_t)0x00100000) /*!< dma1 channel6 global flag */
|
||||
#define DMA1_FDT6_FLAG ((uint32_t)0x00200000) /*!< dma1 channel6 full data transfer flag */
|
||||
#define DMA1_HDT6_FLAG ((uint32_t)0x00400000) /*!< dma1 channel6 half data transfer flag */
|
||||
#define DMA1_DTERR6_FLAG ((uint32_t)0x00800000) /*!< dma1 channel6 error flag */
|
||||
#define DMA1_GL7_FLAG ((uint32_t)0x01000000) /*!< dma1 channel7 global flag */
|
||||
#define DMA1_FDT7_FLAG ((uint32_t)0x02000000) /*!< dma1 channel7 full data transfer flag */
|
||||
#define DMA1_HDT7_FLAG ((uint32_t)0x04000000) /*!< dma1 channel7 half data transfer flag */
|
||||
#define DMA1_DTERR7_FLAG ((uint32_t)0x08000000) /*!< dma1 channel7 error flag */
|
||||
|
||||
#define DMA2_GL1_FLAG ((uint32_t)0x10000001) /*!< dma2 channel1 global flag */
|
||||
#define DMA2_FDT1_FLAG ((uint32_t)0x10000002) /*!< dma2 channel1 full data transfer flag */
|
||||
#define DMA2_HDT1_FLAG ((uint32_t)0x10000004) /*!< dma2 channel1 half data transfer flag */
|
||||
#define DMA2_DTERR1_FLAG ((uint32_t)0x10000008) /*!< dma2 channel1 error flag */
|
||||
#define DMA2_GL2_FLAG ((uint32_t)0x10000010) /*!< dma2 channel2 global flag */
|
||||
#define DMA2_FDT2_FLAG ((uint32_t)0x10000020) /*!< dma2 channel2 full data transfer flag */
|
||||
#define DMA2_HDT2_FLAG ((uint32_t)0x10000040) /*!< dma2 channel2 half data transfer flag */
|
||||
#define DMA2_DTERR2_FLAG ((uint32_t)0x10000080) /*!< dma2 channel2 error flag */
|
||||
#define DMA2_GL3_FLAG ((uint32_t)0x10000100) /*!< dma2 channel3 global flag */
|
||||
#define DMA2_FDT3_FLAG ((uint32_t)0x10000200) /*!< dma2 channel3 full data transfer flag */
|
||||
#define DMA2_HDT3_FLAG ((uint32_t)0x10000400) /*!< dma2 channel3 half data transfer flag */
|
||||
#define DMA2_DTERR3_FLAG ((uint32_t)0x10000800) /*!< dma2 channel3 error flag */
|
||||
#define DMA2_GL4_FLAG ((uint32_t)0x10001000) /*!< dma2 channel4 global flag */
|
||||
#define DMA2_FDT4_FLAG ((uint32_t)0x10002000) /*!< dma2 channel4 full data transfer flag */
|
||||
#define DMA2_HDT4_FLAG ((uint32_t)0x10004000) /*!< dma2 channel4 half data transfer flag */
|
||||
#define DMA2_DTERR4_FLAG ((uint32_t)0x10008000) /*!< dma2 channel4 error flag */
|
||||
#define DMA2_GL5_FLAG ((uint32_t)0x10010000) /*!< dma2 channel5 global flag */
|
||||
#define DMA2_FDT5_FLAG ((uint32_t)0x10020000) /*!< dma2 channel5 full data transfer flag */
|
||||
#define DMA2_HDT5_FLAG ((uint32_t)0x10040000) /*!< dma2 channel5 half data transfer flag */
|
||||
#define DMA2_DTERR5_FLAG ((uint32_t)0x10080000) /*!< dma2 channel5 error flag */
|
||||
#define DMA2_GL6_FLAG ((uint32_t)0x10100000) /*!< dma2 channel6 global flag */
|
||||
#define DMA2_FDT6_FLAG ((uint32_t)0x10200000) /*!< dma2 channel6 full data transfer flag */
|
||||
#define DMA2_HDT6_FLAG ((uint32_t)0x10400000) /*!< dma2 channel6 half data transfer flag */
|
||||
#define DMA2_DTERR6_FLAG ((uint32_t)0x10800000) /*!< dma2 channel6 error flag */
|
||||
#define DMA2_GL7_FLAG ((uint32_t)0x11000000) /*!< dma2 channel7 global flag */
|
||||
#define DMA2_FDT7_FLAG ((uint32_t)0x12000000) /*!< dma2 channel7 full data transfer flag */
|
||||
#define DMA2_HDT7_FLAG ((uint32_t)0x14000000) /*!< dma2 channel7 half data transfer flag */
|
||||
#define DMA2_DTERR7_FLAG ((uint32_t)0x18000000) /*!< dma2 channel7 error flag */
|
||||
|
||||
/**
|
||||
* @brief dmamux flag
|
||||
*/
|
||||
#define DMAMUX_SYNC_OV1_FLAG ((uint32_t)0x00000001) /*!< dmamux channel1 synchronization overrun event flag */
|
||||
#define DMAMUX_SYNC_OV2_FLAG ((uint32_t)0x00000002) /*!< dmamux channel2 synchronization overrun event flag */
|
||||
#define DMAMUX_SYNC_OV3_FLAG ((uint32_t)0x00000004) /*!< dmamux channel3 synchronization overrun event flag */
|
||||
#define DMAMUX_SYNC_OV4_FLAG ((uint32_t)0x00000008) /*!< dmamux channel4 synchronization overrun event flag */
|
||||
#define DMAMUX_SYNC_OV5_FLAG ((uint32_t)0x00000010) /*!< dmamux channel5 synchronization overrun event flag */
|
||||
#define DMAMUX_SYNC_OV6_FLAG ((uint32_t)0x00000020) /*!< dmamux channel6 synchronization overrun event flag */
|
||||
#define DMAMUX_SYNC_OV7_FLAG ((uint32_t)0x00000040) /*!< dmamux channel7 synchronization overrun event flag */
|
||||
|
||||
#define DMAMUX_GEN_TRIG_OV1_FLAG ((uint32_t)0x00000001) /*!< dmamux generator channel1 overrun event flag */
|
||||
#define DMAMUX_GEN_TRIG_OV2_FLAG ((uint32_t)0x00000002) /*!< dmamux generator channel2 overrun event flag */
|
||||
#define DMAMUX_GEN_TRIG_OV3_FLAG ((uint32_t)0x00000004) /*!< dmamux generator channel3 overrun event flag */
|
||||
#define DMAMUX_GEN_TRIG_OV4_FLAG ((uint32_t)0x00000008) /*!< dmamux generator channel4 overrun event flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief dma direction type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_DIR_PERIPHERAL_TO_MEMORY = 0x0000, /*!< dma data transfer direction: peripheral to memory */
|
||||
DMA_DIR_MEMORY_TO_PERIPHERAL = 0x0010, /*!< dma data transfer direction: memory to peripheral */
|
||||
DMA_DIR_MEMORY_TO_MEMORY = 0x4000 /*!< dma data transfer direction: memory to memory */
|
||||
} dma_dir_type;
|
||||
|
||||
/**
|
||||
* @brief dma peripheral data size type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_PERIPHERAL_DATA_WIDTH_BYTE = 0x00, /*!< dma peripheral databus width 8bit */
|
||||
DMA_PERIPHERAL_DATA_WIDTH_HALFWORD = 0x01, /*!< dma peripheral databus width 16bit */
|
||||
DMA_PERIPHERAL_DATA_WIDTH_WORD = 0x02 /*!< dma peripheral databus width 32bit */
|
||||
} dma_peripheral_data_size_type;
|
||||
|
||||
/**
|
||||
* @brief dma memory data size type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_MEMORY_DATA_WIDTH_BYTE = 0x00, /*!< dma memory databus width 8bit */
|
||||
DMA_MEMORY_DATA_WIDTH_HALFWORD = 0x01, /*!< dma memory databus width 16bit */
|
||||
DMA_MEMORY_DATA_WIDTH_WORD = 0x02 /*!< dma memory databus width 32bit */
|
||||
} dma_memory_data_size_type;
|
||||
|
||||
/**
|
||||
* @brief dma priority level type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_PRIORITY_LOW = 0x00, /*!< dma channel priority: low */
|
||||
DMA_PRIORITY_MEDIUM = 0x01, /*!< dma channel priority: medium */
|
||||
DMA_PRIORITY_HIGH = 0x02, /*!< dma channel priority: high */
|
||||
DMA_PRIORITY_VERY_HIGH = 0x03 /*!< dma channel priority: very high */
|
||||
} dma_priority_level_type;
|
||||
|
||||
/**
|
||||
* @brief dmamux request type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMAMUX_DMAREQ_ID_REQ_G1 = 0x01, /*!< dmamux channel dma request inputs resources: generator channel1 */
|
||||
DMAMUX_DMAREQ_ID_REQ_G2 = 0x02, /*!< dmamux channel dma request inputs resources: generator channel2 */
|
||||
DMAMUX_DMAREQ_ID_REQ_G3 = 0x03, /*!< dmamux channel dma request inputs resources: generator channel3 */
|
||||
DMAMUX_DMAREQ_ID_REQ_G4 = 0x04, /*!< dmamux channel dma request inputs resources: generator channel4 */
|
||||
DMAMUX_DMAREQ_ID_ADC1 = 0x05, /*!< dmamux channel dma request inputs resources: adc1 */
|
||||
DMAMUX_DMAREQ_ID_ADC2 = 0x24, /*!< dmamux channel dma request inputs resources: adc2 */
|
||||
DMAMUX_DMAREQ_ID_ADC3 = 0x25, /*!< dmamux channel dma request inputs resources: adc3 */
|
||||
DMAMUX_DMAREQ_ID_DAC1 = 0x06, /*!< dmamux channel dma request inputs resources: dac1 */
|
||||
DMAMUX_DMAREQ_ID_DAC2 = 0x29, /*!< dmamux channel dma request inputs resources: dac2 */
|
||||
DMAMUX_DMAREQ_ID_TMR6_OVERFLOW = 0x08, /*!< dmamux channel dma request inputs resources: timer6 overflow */
|
||||
DMAMUX_DMAREQ_ID_TMR7_OVERFLOW = 0x09, /*!< dmamux channel dma request inputs resources: timer7 overflow */
|
||||
DMAMUX_DMAREQ_ID_SPI1_RX = 0x0A, /*!< dmamux channel dma request inputs resources: spi1 rx */
|
||||
DMAMUX_DMAREQ_ID_SPI1_TX = 0x0B, /*!< dmamux channel dma request inputs resources: spi1 tx */
|
||||
DMAMUX_DMAREQ_ID_SPI2_RX = 0x0C, /*!< dmamux channel dma request inputs resources: spi2 rx */
|
||||
DMAMUX_DMAREQ_ID_SPI2_TX = 0x0D, /*!< dmamux channel dma request inputs resources: spi2 tx */
|
||||
DMAMUX_DMAREQ_ID_SPI3_RX = 0x0E, /*!< dmamux channel dma request inputs resources: spi3 rx */
|
||||
DMAMUX_DMAREQ_ID_SPI3_TX = 0x0F, /*!< dmamux channel dma request inputs resources: spi3 tx */
|
||||
DMAMUX_DMAREQ_ID_SPI4_RX = 0x6A, /*!< dmamux channel dma request inputs resources: spi4 rx */
|
||||
DMAMUX_DMAREQ_ID_SPI4_TX = 0x6B, /*!< dmamux channel dma request inputs resources: spi4 tx */
|
||||
DMAMUX_DMAREQ_ID_I2S2_EXT_RX = 0x6E, /*!< dmamux channel dma request inputs resources: i2s2_ext_rx */
|
||||
DMAMUX_DMAREQ_ID_I2S2_EXT_TX = 0x6F, /*!< dmamux channel dma request inputs resources: i2s2_ext_tx */
|
||||
DMAMUX_DMAREQ_ID_I2S3_EXT_RX = 0x70, /*!< dmamux channel dma request inputs resources: i2s3_ext_rx */
|
||||
DMAMUX_DMAREQ_ID_I2S3_EXT_TX = 0x71, /*!< dmamux channel dma request inputs resources: i2s3_ext_tx */
|
||||
DMAMUX_DMAREQ_ID_I2C1_RX = 0x10, /*!< dmamux channel dma request inputs resources: i2c1_rx */
|
||||
DMAMUX_DMAREQ_ID_I2C1_TX = 0x11, /*!< dmamux channel dma request inputs resources: i2c1_tx */
|
||||
DMAMUX_DMAREQ_ID_I2C2_RX = 0x12, /*!< dmamux channel dma request inputs resources: i2c2_rx */
|
||||
DMAMUX_DMAREQ_ID_I2C2_TX = 0x13, /*!< dmamux channel dma request inputs resources: i2c2_tx */
|
||||
DMAMUX_DMAREQ_ID_I2C3_RX = 0x14, /*!< dmamux channel dma request inputs resources: i2c3_rx */
|
||||
DMAMUX_DMAREQ_ID_I2C3_TX = 0x15, /*!< dmamux channel dma request inputs resources: i2c3_tx */
|
||||
DMAMUX_DMAREQ_ID_USART1_RX = 0x18, /*!< dmamux channel dma request inputs resources: usart1_rx */
|
||||
DMAMUX_DMAREQ_ID_USART1_TX = 0x19, /*!< dmamux channel dma request inputs resources: usart1_tx */
|
||||
DMAMUX_DMAREQ_ID_USART2_RX = 0x1A, /*!< dmamux channel dma request inputs resources: usart2_rx */
|
||||
DMAMUX_DMAREQ_ID_USART2_TX = 0x1B, /*!< dmamux channel dma request inputs resources: usart2_tx */
|
||||
DMAMUX_DMAREQ_ID_USART3_RX = 0x1C, /*!< dmamux channel dma request inputs resources: usart3_rx */
|
||||
DMAMUX_DMAREQ_ID_USART3_TX = 0x1D, /*!< dmamux channel dma request inputs resources: usart3_tx */
|
||||
DMAMUX_DMAREQ_ID_UART4_RX = 0x1E, /*!< dmamux channel dma request inputs resources: uart4_rx */
|
||||
DMAMUX_DMAREQ_ID_UART4_TX = 0x1F, /*!< dmamux channel dma request inputs resources: uart4_tx */
|
||||
DMAMUX_DMAREQ_ID_UART5_RX = 0x20, /*!< dmamux channel dma request inputs resources: uart5_rx */
|
||||
DMAMUX_DMAREQ_ID_UART5_TX = 0x21, /*!< dmamux channel dma request inputs resources: uart5_tx */
|
||||
DMAMUX_DMAREQ_ID_USART6_RX = 0x72, /*!< dmamux channel dma request inputs resources: usart6_rx */
|
||||
DMAMUX_DMAREQ_ID_USART6_TX = 0x73, /*!< dmamux channel dma request inputs resources: usart6_tx */
|
||||
DMAMUX_DMAREQ_ID_UART7_RX = 0x74, /*!< dmamux channel dma request inputs resources: uart7_rx */
|
||||
DMAMUX_DMAREQ_ID_UART7_TX = 0x75, /*!< dmamux channel dma request inputs resources: uart7_tx */
|
||||
DMAMUX_DMAREQ_ID_UART8_RX = 0x76, /*!< dmamux channel dma request inputs resources: uart8_rx */
|
||||
DMAMUX_DMAREQ_ID_UART8_TX = 0x77, /*!< dmamux channel dma request inputs resources: uart8_tx */
|
||||
DMAMUX_DMAREQ_ID_SDIO1 = 0x27, /*!< dmamux channel dma request inputs resources: sdio1 */
|
||||
DMAMUX_DMAREQ_ID_SDIO2 = 0x67, /*!< dmamux channel dma request inputs resources: sdio2 */
|
||||
DMAMUX_DMAREQ_ID_QSPI1 = 0x28, /*!< dmamux channel dma request inputs resources: qspi1 */
|
||||
DMAMUX_DMAREQ_ID_QSPI2 = 0x68, /*!< dmamux channel dma request inputs resources: qspi2 */
|
||||
DMAMUX_DMAREQ_ID_TMR1_CH1 = 0x2A, /*!< dmamux channel dma request inputs resources: timer1 ch1 */
|
||||
DMAMUX_DMAREQ_ID_TMR1_CH2 = 0x2B, /*!< dmamux channel dma request inputs resources: timer1 ch2 */
|
||||
DMAMUX_DMAREQ_ID_TMR1_CH3 = 0x2C, /*!< dmamux channel dma request inputs resources: timer1 ch3 */
|
||||
DMAMUX_DMAREQ_ID_TMR1_CH4 = 0x2D, /*!< dmamux channel dma request inputs resources: timer1 ch4 */
|
||||
DMAMUX_DMAREQ_ID_TMR1_OVERFLOW = 0x2E, /*!< dmamux channel dma request inputs resources: timer1 overflow */
|
||||
DMAMUX_DMAREQ_ID_TMR1_TRIG = 0x2F, /*!< dmamux channel dma request inputs resources: timer1 trigger */
|
||||
DMAMUX_DMAREQ_ID_TMR1_HALL = 0x30, /*!< dmamux channel dma request inputs resources: timer1 hall */
|
||||
DMAMUX_DMAREQ_ID_TMR8_CH1 = 0x31, /*!< dmamux channel dma request inputs resources: timer8 ch1 */
|
||||
DMAMUX_DMAREQ_ID_TMR8_CH2 = 0x32, /*!< dmamux channel dma request inputs resources: timer8 ch2 */
|
||||
DMAMUX_DMAREQ_ID_TMR8_CH3 = 0x33, /*!< dmamux channel dma request inputs resources: timer8 ch3 */
|
||||
DMAMUX_DMAREQ_ID_TMR8_CH4 = 0x34, /*!< dmamux channel dma request inputs resources: timer8 ch4 */
|
||||
DMAMUX_DMAREQ_ID_TMR8_UP = 0x35, /*!< dmamux channel dma request inputs resources: timer8 overflow */
|
||||
DMAMUX_DMAREQ_ID_TMR8_TRIG = 0x36, /*!< dmamux channel dma request inputs resources: timer8 trigger */
|
||||
DMAMUX_DMAREQ_ID_TMR8_HALL = 0x37, /*!< dmamux channel dma request inputs resources: timer8 hall */
|
||||
DMAMUX_DMAREQ_ID_TMR2_CH1 = 0x38, /*!< dmamux channel dma request inputs resources: timer2 ch1 */
|
||||
DMAMUX_DMAREQ_ID_TMR2_CH2 = 0x39, /*!< dmamux channel dma request inputs resources: timer2 ch2 */
|
||||
DMAMUX_DMAREQ_ID_TMR2_CH3 = 0x3A, /*!< dmamux channel dma request inputs resources: timer2 ch3 */
|
||||
DMAMUX_DMAREQ_ID_TMR2_CH4 = 0x3B, /*!< dmamux channel dma request inputs resources: timer2 ch4 */
|
||||
DMAMUX_DMAREQ_ID_TMR2_OVERFLOW = 0x3C, /*!< dmamux channel dma request inputs resources: timer2 overflow */
|
||||
DMAMUX_DMAREQ_ID_TMR2_TRIG = 0x7E, /*!< dmamux channel dma request inputs resources: timer2 trigger */
|
||||
DMAMUX_DMAREQ_ID_TMR3_CH1 = 0x3D, /*!< dmamux channel dma request inputs resources: timer3 ch1 */
|
||||
DMAMUX_DMAREQ_ID_TMR3_CH2 = 0x3E, /*!< dmamux channel dma request inputs resources: timer3 ch2 */
|
||||
DMAMUX_DMAREQ_ID_TMR3_CH3 = 0x3F, /*!< dmamux channel dma request inputs resources: timer3 ch3 */
|
||||
DMAMUX_DMAREQ_ID_TMR3_CH4 = 0x40, /*!< dmamux channel dma request inputs resources: timer3 ch4 */
|
||||
DMAMUX_DMAREQ_ID_TMR3_OVERFLOW = 0x41, /*!< dmamux channel dma request inputs resources: timer3 overflow */
|
||||
DMAMUX_DMAREQ_ID_TMR3_TRIG = 0x42, /*!< dmamux channel dma request inputs resources: timer3 trigger */
|
||||
DMAMUX_DMAREQ_ID_TMR4_CH1 = 0x43, /*!< dmamux channel dma request inputs resources: timer4 ch1 */
|
||||
DMAMUX_DMAREQ_ID_TMR4_CH2 = 0x44, /*!< dmamux channel dma request inputs resources: timer4 ch2 */
|
||||
DMAMUX_DMAREQ_ID_TMR4_CH3 = 0x45, /*!< dmamux channel dma request inputs resources: timer4 ch3 */
|
||||
DMAMUX_DMAREQ_ID_TMR4_CH4 = 0x46, /*!< dmamux channel dma request inputs resources: timer4 ch4 */
|
||||
DMAMUX_DMAREQ_ID_TMR4_OVERFLOW = 0x47, /*!< dmamux channel dma request inputs resources: timer4 overflow */
|
||||
DMAMUX_DMAREQ_ID_TMR4_TRIG = 0x7F, /*!< dmamux channel dma request inputs resources: timer4 trigger */
|
||||
DMAMUX_DMAREQ_ID_TMR5_CH1 = 0x48, /*!< dmamux channel dma request inputs resources: timer5 ch1 */
|
||||
DMAMUX_DMAREQ_ID_TMR5_CH2 = 0x49, /*!< dmamux channel dma request inputs resources: timer5 ch2 */
|
||||
DMAMUX_DMAREQ_ID_TMR5_CH3 = 0x4A, /*!< dmamux channel dma request inputs resources: timer5 ch3 */
|
||||
DMAMUX_DMAREQ_ID_TMR5_CH4 = 0x4B, /*!< dmamux channel dma request inputs resources: timer5 ch4 */
|
||||
DMAMUX_DMAREQ_ID_TMR5_OVERFLOW = 0x4C, /*!< dmamux channel dma request inputs resources: timer5 overflow */
|
||||
DMAMUX_DMAREQ_ID_TMR5_TRIG = 0x4D, /*!< dmamux channel dma request inputs resources: timer5 trigger */
|
||||
DMAMUX_DMAREQ_ID_TMR20_CH1 = 0x56, /*!< dmamux channel dma request inputs resources: timer20 ch1 */
|
||||
DMAMUX_DMAREQ_ID_TMR20_CH2 = 0x57, /*!< dmamux channel dma request inputs resources: timer20 ch2 */
|
||||
DMAMUX_DMAREQ_ID_TMR20_CH3 = 0x58, /*!< dmamux channel dma request inputs resources: timer20 ch3 */
|
||||
DMAMUX_DMAREQ_ID_TMR20_CH4 = 0x59, /*!< dmamux channel dma request inputs resources: timer20 ch4 */
|
||||
DMAMUX_DMAREQ_ID_TMR20_OVERFLOW = 0x5A, /*!< dmamux channel dma request inputs resources: timer20 overflow */
|
||||
DMAMUX_DMAREQ_ID_TMR20_TRIG = 0x5D, /*!< dmamux channel dma request inputs resources: timer20 trigger */
|
||||
DMAMUX_DMAREQ_ID_TMR20_HALL = 0x5E, /*!< dmamux channel dma request inputs resources: timer20 hall */
|
||||
DMAMUX_DMAREQ_ID_DVP = 0x69 /*!< dmamux channel dma request inputs resources: dvp */
|
||||
} dmamux_requst_id_sel_type;
|
||||
|
||||
/**
|
||||
* @brief dmamux sync id type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMAMUX_SYNC_ID_EXINT0 = 0x00, /*!< dmamux channel synchronization inputs resources: exint line0 */
|
||||
DMAMUX_SYNC_ID_EXINT1 = 0x01, /*!< dmamux channel synchronization inputs resources: exint line1 */
|
||||
DMAMUX_SYNC_ID_EXINT2 = 0x02, /*!< dmamux channel synchronization inputs resources: exint line2 */
|
||||
DMAMUX_SYNC_ID_EXINT3 = 0x03, /*!< dmamux channel synchronization inputs resources: exint line3 */
|
||||
DMAMUX_SYNC_ID_EXINT4 = 0x04, /*!< dmamux channel synchronization inputs resources: exint line4 */
|
||||
DMAMUX_SYNC_ID_EXINT5 = 0x05, /*!< dmamux channel synchronization inputs resources: exint line5 */
|
||||
DMAMUX_SYNC_ID_EXINT6 = 0x06, /*!< dmamux channel synchronization inputs resources: exint line6 */
|
||||
DMAMUX_SYNC_ID_EXINT7 = 0x07, /*!< dmamux channel synchronization inputs resources: exint line7 */
|
||||
DMAMUX_SYNC_ID_EXINT8 = 0x08, /*!< dmamux channel synchronization inputs resources: exint line8 */
|
||||
DMAMUX_SYNC_ID_EXINT9 = 0x09, /*!< dmamux channel synchronization inputs resources: exint line9 */
|
||||
DMAMUX_SYNC_ID_EXINT10 = 0x0A, /*!< dmamux channel synchronization inputs resources: exint line10 */
|
||||
DMAMUX_SYNC_ID_EXINT11 = 0x0B, /*!< dmamux channel synchronization inputs resources: exint line11 */
|
||||
DMAMUX_SYNC_ID_EXINT12 = 0x0C, /*!< dmamux channel synchronization inputs resources: exint line12 */
|
||||
DMAMUX_SYNC_ID_EXINT13 = 0x0D, /*!< dmamux channel synchronization inputs resources: exint line13 */
|
||||
DMAMUX_SYNC_ID_EXINT14 = 0x0E, /*!< dmamux channel synchronization inputs resources: exint line14 */
|
||||
DMAMUX_SYNC_ID_EXINT15 = 0x0F, /*!< dmamux channel synchronization inputs resources: exint line15 */
|
||||
DMAMUX_SYNC_ID_DMAMUX_CH1_EVT = 0x10, /*!< dmamux channel synchronization inputs resources: dmamux channel1 event */
|
||||
DMAMUX_SYNC_ID_DMAMUX_CH2_EVT = 0x11, /*!< dmamux channel synchronization inputs resources: dmamux channel2 event */
|
||||
DMAMUX_SYNC_ID_DMAMUX_CH3_EVT = 0x12, /*!< dmamux channel synchronization inputs resources: dmamux channel3 event */
|
||||
DMAMUX_SYNC_ID_DMAMUX_CH4_EVT = 0x13, /*!< dmamux channel synchronization inputs resources: dmamux channel4 event */
|
||||
DMAMUX_SYNC_ID_DMAMUX_CH5_EVT = 0x14, /*!< dmamux channel synchronization inputs resources: dmamux channel5 event */
|
||||
DMAMUX_SYNC_ID_DMAMUX_CH6_EVT = 0x15, /*!< dmamux channel synchronization inputs resources: dmamux channel6 event */
|
||||
DMAMUX_SYNC_ID_DMAMUX_CH7_EVT = 0x16 /*!< dmamux channel synchronization inputs resources: dmamux channel7 event */
|
||||
} dmamux_sync_id_sel_type;
|
||||
|
||||
/**
|
||||
* @brief dmamux sync polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMAMUX_SYNC_POLARITY_DISABLE = 0x00, /*!< dmamux channel synchronization inputs resources polarity default value */
|
||||
DMAMUX_SYNC_POLARITY_RISING = 0x01, /*!< dmamux channel synchronization inputs resources polarity: rising */
|
||||
DMAMUX_SYNC_POLARITY_FALLING = 0x02, /*!< dmamux channel synchronization inputs resources polarity: falling */
|
||||
DMAMUX_SYNC_POLARITY_RISING_FALLING = 0x03 /*!< dmamux channel synchronization inputs resources polarity: rising_falling */
|
||||
} dmamux_sync_pol_type;
|
||||
|
||||
/**
|
||||
* @brief dmamux generator id type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMAMUX_GEN_ID_EXINT0 = 0x00, /*!< dmamux generator channel inputs resources: exint line0 */
|
||||
DMAMUX_GEN_ID_EXINT1 = 0x01, /*!< dmamux generator channel inputs resources: exint line1 */
|
||||
DMAMUX_GEN_ID_EXINT2 = 0x02, /*!< dmamux generator channel inputs resources: exint line2 */
|
||||
DMAMUX_GEN_ID_EXINT3 = 0x03, /*!< dmamux generator channel inputs resources: exint line3 */
|
||||
DMAMUX_GEN_ID_EXINT4 = 0x04, /*!< dmamux generator channel inputs resources: exint line4 */
|
||||
DMAMUX_GEN_ID_EXINT5 = 0x05, /*!< dmamux generator channel inputs resources: exint line5 */
|
||||
DMAMUX_GEN_ID_EXINT6 = 0x06, /*!< dmamux generator channel inputs resources: exint line6 */
|
||||
DMAMUX_GEN_ID_EXINT7 = 0x07, /*!< dmamux generator channel inputs resources: exint line7 */
|
||||
DMAMUX_GEN_ID_EXINT8 = 0x08, /*!< dmamux generator channel inputs resources: exint line8 */
|
||||
DMAMUX_GEN_ID_EXINT9 = 0x09, /*!< dmamux generator channel inputs resources: exint line9 */
|
||||
DMAMUX_GEN_ID_EXINT10 = 0x0A, /*!< dmamux generator channel inputs resources: exint line10 */
|
||||
DMAMUX_GEN_ID_EXINT11 = 0x0B, /*!< dmamux generator channel inputs resources: exint line11 */
|
||||
DMAMUX_GEN_ID_EXINT12 = 0x0C, /*!< dmamux generator channel inputs resources: exint line12 */
|
||||
DMAMUX_GEN_ID_EXINT13 = 0x0D, /*!< dmamux generator channel inputs resources: exint line13 */
|
||||
DMAMUX_GEN_ID_EXINT14 = 0x0E, /*!< dmamux generator channel inputs resources: exint line14 */
|
||||
DMAMUX_GEN_ID_EXINT15 = 0x0F, /*!< dmamux generator channel inputs resources: exint line15 */
|
||||
DMAMUX_GEN_ID_DMAMUX_CH1_EVT = 0x10, /*!< dmamux generator channel inputs resources: dmamux channel1 event */
|
||||
DMAMUX_GEN_ID_DMAMUX_CH2_EVT = 0x11, /*!< dmamux generator channel inputs resources: dmamux channel2 event */
|
||||
DMAMUX_GEN_ID_DMAMUX_CH3_EVT = 0x12, /*!< dmamux generator channel inputs resources: dmamux channel3 event */
|
||||
DMAMUX_GEN_ID_DMAMUX_CH4_EVT = 0x13, /*!< dmamux generator channel inputs resources: dmamux channel4 event */
|
||||
DMAMUX_GEN_ID_DMAMUX_CH5_EVT = 0x14, /*!< dmamux generator channel inputs resources: dmamux channel5 event */
|
||||
DMAMUX_GEN_ID_DMAMUX_CH6_EVT = 0x15, /*!< dmamux generator channel inputs resources: dmamux channel6 event */
|
||||
DMAMUX_GEN_ID_DMAMUX_CH7_EVT = 0x16 /*!< dmamux generator channel inputs resources: dmamux channel7 event */
|
||||
} dmamux_gen_id_sel_type;
|
||||
|
||||
/**
|
||||
* @brief dmamux generator polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMAMUX_GEN_POLARITY_DISABLE = 0x00, /*!< dmamux generator channel inputs resources polarity default value */
|
||||
DMAMUX_GEN_POLARITY_RISING = 0x01, /*!< dmamux generator channel inputs resources polarity: rising */
|
||||
DMAMUX_GEN_POLARITY_FALLING = 0x02, /*!< dmamux generator channel inputs resources polarity: falling */
|
||||
DMAMUX_GEN_POLARITY_RISING_FALLING = 0x03 /*!< dmamux generator channel inputs resources polarity: rising_falling */
|
||||
} dmamux_gen_pol_type;
|
||||
|
||||
/**
|
||||
* @brief dma init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t peripheral_base_addr; /*!< base addrress for peripheral */
|
||||
uint32_t memory_base_addr; /*!< base addrress for memory */
|
||||
dma_dir_type direction; /*!< dma transmit direction, peripheral as source or as destnation */
|
||||
uint16_t buffer_size; /*!< counter to transfer (0~0xFFFF) */
|
||||
confirm_state peripheral_inc_enable; /*!< periphera address increment after one transmit */
|
||||
confirm_state memory_inc_enable; /*!< memory address increment after one transmit */
|
||||
dma_peripheral_data_size_type peripheral_data_width; /*!< peripheral data width for transmit */
|
||||
dma_memory_data_size_type memory_data_width; /*!< memory data width for transmit */
|
||||
confirm_state loop_mode_enable; /*!< when loop mode enable, buffer size will reload if count to 0*/
|
||||
dma_priority_level_type priority; /*!< dma priority can choose from very high,high,dedium or low */
|
||||
} dma_init_type;
|
||||
|
||||
/**
|
||||
* @brief dmamux sync init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
dmamux_sync_id_sel_type sync_signal_sel; /*!< dma dmamux synchronization input select */
|
||||
uint32_t sync_polarity; /*!< dma dmamux synchronization polarity */
|
||||
uint32_t sync_request_number; /*!< dma dmamux number of dma requests before an output event is generated */
|
||||
confirm_state sync_event_enable; /*!< dma dmamux event generation disabled */
|
||||
confirm_state sync_enable; /*!< dma dmamux synchronization enable */
|
||||
} dmamux_sync_init_type;
|
||||
|
||||
/**
|
||||
* @brief dmamux generator init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
dmamux_gen_id_sel_type gen_signal_sel; /*!< dma dmamux generator dma request trigger input select */
|
||||
dmamux_gen_pol_type gen_polarity; /*!< dma dmamux generator trigger polarity */
|
||||
uint32_t gen_request_number; /*!< dma dmamux the number of dma requests to be generated after a trigger event */
|
||||
confirm_state gen_enable; /*!< dma dmamux generator enable */
|
||||
} dmamux_gen_init_type;
|
||||
|
||||
/**
|
||||
* @brief type define dma1 register
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief dma sts register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t gf1 : 1; /* [0] */
|
||||
__IO uint32_t fdtf1 : 1; /* [1] */
|
||||
__IO uint32_t hdtf1 : 1; /* [2] */
|
||||
__IO uint32_t dterrf1 : 1; /* [3] */
|
||||
__IO uint32_t gf2 : 1; /* [4] */
|
||||
__IO uint32_t fdtf2 : 1; /* [5] */
|
||||
__IO uint32_t hdtf2 : 1; /* [6] */
|
||||
__IO uint32_t dterrf2 : 1; /* [7] */
|
||||
__IO uint32_t gf3 : 1; /* [8] */
|
||||
__IO uint32_t fdtf3 : 1; /* [9] */
|
||||
__IO uint32_t hdtf3 : 1; /* [10] */
|
||||
__IO uint32_t dterrf3 : 1; /* [11] */
|
||||
__IO uint32_t gf4 : 1; /* [12] */
|
||||
__IO uint32_t fdtf4 : 1; /* [13] */
|
||||
__IO uint32_t hdtf4 : 1; /* [14] */
|
||||
__IO uint32_t dterrf4 : 1; /* [15] */
|
||||
__IO uint32_t gf5 : 1; /* [16] */
|
||||
__IO uint32_t fdtf5 : 1; /* [17] */
|
||||
__IO uint32_t hdtf5 : 1; /* [18] */
|
||||
__IO uint32_t dterrf5 : 1; /* [19] */
|
||||
__IO uint32_t gf6 : 1; /* [20] */
|
||||
__IO uint32_t fdtf6 : 1; /* [21] */
|
||||
__IO uint32_t hdtf6 : 1; /* [22] */
|
||||
__IO uint32_t dterrf6 : 1; /* [23] */
|
||||
__IO uint32_t gf7 : 1; /* [24] */
|
||||
__IO uint32_t fdtf7 : 1; /* [25] */
|
||||
__IO uint32_t hdtf7 : 1; /* [26] */
|
||||
__IO uint32_t dterrf7 : 1; /* [27] */
|
||||
__IO uint32_t reserved1 : 4; /* [31:28] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dma clr register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t clr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t gfc1 : 1; /* [0] */
|
||||
__IO uint32_t fdtfc1 : 1; /* [1] */
|
||||
__IO uint32_t hdtfc1 : 1; /* [2] */
|
||||
__IO uint32_t dterrfc1 : 1; /* [3] */
|
||||
__IO uint32_t gfc2 : 1; /* [4] */
|
||||
__IO uint32_t fdtfc2 : 1; /* [5] */
|
||||
__IO uint32_t hdtfc2 : 1; /* [6] */
|
||||
__IO uint32_t dterrfc2 : 1; /* [7] */
|
||||
__IO uint32_t gfc3 : 1; /* [8] */
|
||||
__IO uint32_t fdtfc3 : 1; /* [9] */
|
||||
__IO uint32_t hdtfc3 : 1; /* [10] */
|
||||
__IO uint32_t dterrfc3 : 1; /* [11] */
|
||||
__IO uint32_t gfc4 : 1; /* [12] */
|
||||
__IO uint32_t fdtfc4 : 1; /* [13] */
|
||||
__IO uint32_t hdtfc4 : 1; /* [14] */
|
||||
__IO uint32_t dterrfc4 : 1; /* [15] */
|
||||
__IO uint32_t gfc5 : 1; /* [16] */
|
||||
__IO uint32_t fdtfc5 : 1; /* [17] */
|
||||
__IO uint32_t hdtfc5 : 1; /* [18] */
|
||||
__IO uint32_t dterrfc5 : 1; /* [19] */
|
||||
__IO uint32_t gfc6 : 1; /* [20] */
|
||||
__IO uint32_t fdtfc6 : 1; /* [21] */
|
||||
__IO uint32_t hdtfc6 : 1; /* [22] */
|
||||
__IO uint32_t dterrfc6 : 1; /* [23] */
|
||||
__IO uint32_t gfc7 : 1; /* [24] */
|
||||
__IO uint32_t fdtfc7 : 1; /* [25] */
|
||||
__IO uint32_t hdtfc7 : 1; /* [26] */
|
||||
__IO uint32_t dterrfc7 : 1; /* [27] */
|
||||
__IO uint32_t reserved1 : 4; /* [31:28] */
|
||||
} clr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief reserved, offset:0x08~0xFC
|
||||
*/
|
||||
__IO uint32_t reserved1[62];
|
||||
|
||||
/**
|
||||
* @brief dmamux sel register, offset:0x100
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t muxsel;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tblsel : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 31;/* [31:1] */
|
||||
}muxsel_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief reserved, offset:0x104~0x12C
|
||||
*/
|
||||
__IO uint32_t reserved2[11];
|
||||
|
||||
/**
|
||||
* @brief dmamux syncsts register, offset:0x130
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t muxsyncsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t syncovf : 7; /* [6:0] */
|
||||
__IO uint32_t reserved1 : 25;/* [31:7] */
|
||||
}muxsyncsts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dmamux syncclr register, offset:0x134
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t muxsyncclr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t syncovfc : 7; /* [6:0] */
|
||||
__IO uint32_t reserved1 : 25;/* [31:7] */
|
||||
}muxsyncclr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dmamux request generator status register, offset:0x138
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t muxgsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t trgovf : 4; /* [3:0] */
|
||||
__IO uint32_t reserved1 : 28;/* [31:4] */
|
||||
}muxgsts_bit;
|
||||
};
|
||||
/**
|
||||
* @brief dmamux request generator status clear register, offset:0x13C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t muxgclr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t trgovfc : 4; /* [3:0] */
|
||||
__IO uint32_t reserved1 : 28;/* [31:4] */
|
||||
}muxgclr_bit;
|
||||
};
|
||||
} dma_type;
|
||||
|
||||
/**
|
||||
* @brief type define dma channel register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief dma ch ctrl0 register, offset:0x08+20*(x-1) x=1...7
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t chen : 1; /* [0] */
|
||||
__IO uint32_t fdtien : 1; /* [1] */
|
||||
__IO uint32_t hdtien : 1; /* [2] */
|
||||
__IO uint32_t dterrien : 1; /* [3] */
|
||||
__IO uint32_t dtd : 1; /* [4] */
|
||||
__IO uint32_t lm : 1; /* [5] */
|
||||
__IO uint32_t pincm : 1; /* [6] */
|
||||
__IO uint32_t mincm : 1; /* [7] */
|
||||
__IO uint32_t pwidth : 2; /* [9:8] */
|
||||
__IO uint32_t mwidth : 2; /* [11:10] */
|
||||
__IO uint32_t chpl : 2; /* [13:12] */
|
||||
__IO uint32_t m2m : 1; /* [14] */
|
||||
__IO uint32_t reserved1 : 17;/* [31:15] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dma tcnt register, offset:0x0C+20*(x-1) x=1...7
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dtcnt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cnt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} dtcnt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dma cpba register, offset:0x10+20*(x-1) x=1...7
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t paddr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t paddr : 32;/* [31:0] */
|
||||
} paddr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dma cmba register, offset:0x14+20*(x-1) x=1...7
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t maddr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t maddr : 32;/* [31:0] */
|
||||
} maddr_bit;
|
||||
};
|
||||
} dma_channel_type;
|
||||
|
||||
/**
|
||||
* @brief type define dmamux muxsctrl register
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief dma muxsctrl register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t muxctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reqsel : 7; /* [6:0] */
|
||||
__IO uint32_t reserved1 : 1; /* [7] */
|
||||
__IO uint32_t syncovien : 1; /* [8] */
|
||||
__IO uint32_t evtgen : 1; /* [9] */
|
||||
__IO uint32_t reserved2 : 6; /* [15:10] */
|
||||
__IO uint32_t syncen : 1; /* [16] */
|
||||
__IO uint32_t syncpol : 2; /* [18:17] */
|
||||
__IO uint32_t reqcnt : 5; /* [23:19] */
|
||||
__IO uint32_t syncsel : 5; /* [28:24] */
|
||||
__IO uint32_t reserved3 : 3; /* [31:29] */
|
||||
}muxctrl_bit;
|
||||
};
|
||||
} dmamux_channel_type;
|
||||
|
||||
/**
|
||||
* @brief type define dmamux request generator register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief dmamux request generator register, offset:0x120+4*(x-1) x=1...4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t gctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t sigsel : 5; /* [4:0] */
|
||||
__IO uint32_t reserved1 : 3; /* [7:5] */
|
||||
__IO uint32_t trgovien : 1; /* [8] */
|
||||
__IO uint32_t reserved2 : 7; /* [15:9] */
|
||||
__IO uint32_t gen : 1; /* [16] */
|
||||
__IO uint32_t gpol : 2; /* [18:17] */
|
||||
__IO uint32_t greqcnt : 5; /* [23:19] */
|
||||
__IO uint32_t reserved3 : 8; /* [31:24] */
|
||||
}gctrl_bit;
|
||||
};
|
||||
} dmamux_generator_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define DMA1 ((dma_type *) DMA1_BASE)
|
||||
#define DMA1_CHANNEL1 ((dma_channel_type *) DMA1_CHANNEL1_BASE)
|
||||
#define DMA1_CHANNEL2 ((dma_channel_type *) DMA1_CHANNEL2_BASE)
|
||||
#define DMA1_CHANNEL3 ((dma_channel_type *) DMA1_CHANNEL3_BASE)
|
||||
#define DMA1_CHANNEL4 ((dma_channel_type *) DMA1_CHANNEL4_BASE)
|
||||
#define DMA1_CHANNEL5 ((dma_channel_type *) DMA1_CHANNEL5_BASE)
|
||||
#define DMA1_CHANNEL6 ((dma_channel_type *) DMA1_CHANNEL6_BASE)
|
||||
#define DMA1_CHANNEL7 ((dma_channel_type *) DMA1_CHANNEL7_BASE)
|
||||
|
||||
#define DMA1MUX_CHANNEL1 ((dmamux_channel_type *) DMA1MUX_CHANNEL1_BASE)
|
||||
#define DMA1MUX_CHANNEL2 ((dmamux_channel_type *) DMA1MUX_CHANNEL2_BASE)
|
||||
#define DMA1MUX_CHANNEL3 ((dmamux_channel_type *) DMA1MUX_CHANNEL3_BASE)
|
||||
#define DMA1MUX_CHANNEL4 ((dmamux_channel_type *) DMA1MUX_CHANNEL4_BASE)
|
||||
#define DMA1MUX_CHANNEL5 ((dmamux_channel_type *) DMA1MUX_CHANNEL5_BASE)
|
||||
#define DMA1MUX_CHANNEL6 ((dmamux_channel_type *) DMA1MUX_CHANNEL6_BASE)
|
||||
#define DMA1MUX_CHANNEL7 ((dmamux_channel_type *) DMA1MUX_CHANNEL7_BASE)
|
||||
|
||||
#define DMA1MUX_GENERATOR1 ((dmamux_generator_type *) DMA1MUX_GENERATOR1_BASE)
|
||||
#define DMA1MUX_GENERATOR2 ((dmamux_generator_type *) DMA1MUX_GENERATOR2_BASE)
|
||||
#define DMA1MUX_GENERATOR3 ((dmamux_generator_type *) DMA1MUX_GENERATOR3_BASE)
|
||||
#define DMA1MUX_GENERATOR4 ((dmamux_generator_type *) DMA1MUX_GENERATOR4_BASE)
|
||||
|
||||
#define DMA2 ((dma_type *) DMA2_BASE)
|
||||
#define DMA2_CHANNEL1 ((dma_channel_type *) DMA2_CHANNEL1_BASE)
|
||||
#define DMA2_CHANNEL2 ((dma_channel_type *) DMA2_CHANNEL2_BASE)
|
||||
#define DMA2_CHANNEL3 ((dma_channel_type *) DMA2_CHANNEL3_BASE)
|
||||
#define DMA2_CHANNEL4 ((dma_channel_type *) DMA2_CHANNEL4_BASE)
|
||||
#define DMA2_CHANNEL5 ((dma_channel_type *) DMA2_CHANNEL5_BASE)
|
||||
#define DMA2_CHANNEL6 ((dma_channel_type *) DMA2_CHANNEL6_BASE)
|
||||
#define DMA2_CHANNEL7 ((dma_channel_type *) DMA2_CHANNEL7_BASE)
|
||||
|
||||
#define DMA2MUX_CHANNEL1 ((dmamux_channel_type *) DMA2MUX_CHANNEL1_BASE)
|
||||
#define DMA2MUX_CHANNEL2 ((dmamux_channel_type *) DMA2MUX_CHANNEL2_BASE)
|
||||
#define DMA2MUX_CHANNEL3 ((dmamux_channel_type *) DMA2MUX_CHANNEL3_BASE)
|
||||
#define DMA2MUX_CHANNEL4 ((dmamux_channel_type *) DMA2MUX_CHANNEL4_BASE)
|
||||
#define DMA2MUX_CHANNEL5 ((dmamux_channel_type *) DMA2MUX_CHANNEL5_BASE)
|
||||
#define DMA2MUX_CHANNEL6 ((dmamux_channel_type *) DMA2MUX_CHANNEL6_BASE)
|
||||
#define DMA2MUX_CHANNEL7 ((dmamux_channel_type *) DMA2MUX_CHANNEL7_BASE)
|
||||
|
||||
#define DMA2MUX_GENERATOR1 ((dmamux_generator_type *) DMA2MUX_GENERATOR1_BASE)
|
||||
#define DMA2MUX_GENERATOR2 ((dmamux_generator_type *) DMA2MUX_GENERATOR2_BASE)
|
||||
#define DMA2MUX_GENERATOR3 ((dmamux_generator_type *) DMA2MUX_GENERATOR3_BASE)
|
||||
#define DMA2MUX_GENERATOR4 ((dmamux_generator_type *) DMA2MUX_GENERATOR4_BASE)
|
||||
|
||||
/** @defgroup DMA_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* dma controller function */
|
||||
void dma_reset(dma_channel_type *dmax_channely);
|
||||
void dma_data_number_set(dma_channel_type *dmax_channely, uint16_t data_number);
|
||||
uint16_t dma_data_number_get(dma_channel_type *dmax_channely);
|
||||
void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state);
|
||||
void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state);
|
||||
flag_status dma_flag_get(uint32_t dmax_flag);
|
||||
void dma_flag_clear(uint32_t dmax_flag);
|
||||
void dma_default_para_init(dma_init_type *dma_init_struct);
|
||||
void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct);
|
||||
|
||||
/* dma requst multiplexer function */
|
||||
void dma_flexible_config(dma_type* dma_x, dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel);
|
||||
void dmamux_enable(dma_type *dma_x, confirm_state new_state);
|
||||
void dmamux_init(dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel);
|
||||
void dmamux_sync_default_para_init(dmamux_sync_init_type *dmamux_sync_init_struct);
|
||||
void dmamux_sync_config(dmamux_channel_type *dmamux_channelx, dmamux_sync_init_type *dmamux_sync_init_struct);
|
||||
void dmamux_generator_default_para_init(dmamux_gen_init_type *dmamux_gen_init_struct);
|
||||
void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_init_type *dmamux_gen_init_struct);
|
||||
void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state);
|
||||
void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state);
|
||||
flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag);
|
||||
void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag);
|
||||
flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag);
|
||||
void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,620 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_dvp.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 dvp header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_DVP_H
|
||||
#define __AT32F435_437_DVP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DVP_event_flags_definition
|
||||
* @brief dvp event flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DVP_CFD_EVT_FLAG ((uint32_t)0x00000001) /*!< capture frame done event status flag */
|
||||
#define DVP_OVR_EVT_FLAG ((uint32_t)0x00000002) /*!< data fifo overrun event status flag */
|
||||
#define DVP_ESE_EVT_FLAG ((uint32_t)0x00000004) /*!< embedded synchronization error event status flag */
|
||||
#define DVP_VS_EVT_FLAG ((uint32_t)0x00000008) /*!< vertical synchonization event status flag */
|
||||
#define DVP_HS_EVT_FLAG ((uint32_t)0x00000010) /*!< horizontal synchonization event status flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DVP_interrupt_flags_definition
|
||||
* @brief dvp interrupt flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DVP_CFD_INT_FLAG ((uint32_t)0x80000001) /*!< capture frame done interrupt status flag */
|
||||
#define DVP_OVR_INT_FLAG ((uint32_t)0x80000002) /*!< data fifo overrun interrupt status flag */
|
||||
#define DVP_ESE_INT_FLAG ((uint32_t)0x80000004) /*!< embedded synchronization error interrupt status flag */
|
||||
#define DVP_VS_INT_FLAG ((uint32_t)0x80000008) /*!< vertical synchonization interrupt status flag */
|
||||
#define DVP_HS_INT_FLAG ((uint32_t)0x80000010) /*!< horizontal synchonization interrupt status flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DVP_interrupts_definition
|
||||
* @brief dvp interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DVP_CFD_INT ((uint32_t)0x00000001) /*!< capture frame done interrupt */
|
||||
#define DVP_OVR_INT ((uint32_t)0x00000002) /*!< data fifo overrun interrupt */
|
||||
#define DVP_ESE_INT ((uint32_t)0x00000004) /*!< embedded synchronization error interrupt */
|
||||
#define DVP_VS_INT ((uint32_t)0x00000008) /*!< vertical synchonization interrupt */
|
||||
#define DVP_HS_INT ((uint32_t)0x00000010) /*!< horizontal synchonization interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DVP_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief dvp cfm type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_CAP_FUNC_MODE_CONTINUOUS = 0x00,
|
||||
DVP_CAP_FUNC_MODE_SINGLE = 0x01
|
||||
} dvp_cfm_type;
|
||||
|
||||
/**
|
||||
* @brief dvp sm type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_SYNC_MODE_HARDWARE = 0x00,
|
||||
DVP_SYNC_MODE_EMBEDDED = 0x01
|
||||
} dvp_sm_type;
|
||||
|
||||
/**
|
||||
* @brief dvp ckp type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_CLK_POLARITY_RISING = 0x00,
|
||||
DVP_CLK_POLARITY_FALLING = 0x01
|
||||
} dvp_ckp_type;
|
||||
|
||||
/**
|
||||
* @brief dvp hsp type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_HSYNC_POLARITY_HIGH = 0x00,
|
||||
DVP_HSYNC_POLARITY_LOW = 0x01
|
||||
} dvp_hsp_type;
|
||||
|
||||
/**
|
||||
* @brief dvp vsp type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_VSYNC_POLARITY_LOW = 0x00,
|
||||
DVP_VSYNC_POLARITY_HIGH = 0x01
|
||||
} dvp_vsp_type;
|
||||
|
||||
/**
|
||||
* @brief dvp bfrc type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_BFRC_ALL = 0x00,
|
||||
DVP_BFRC_HALF = 0x01,
|
||||
DVP_BFRC_QUARTER = 0x02
|
||||
} dvp_bfrc_type;
|
||||
|
||||
/**
|
||||
* @brief dvp pdl type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_PIXEL_DATA_LENGTH_8 = 0x00,
|
||||
DVP_PIXEL_DATA_LENGTH_10 = 0x01,
|
||||
DVP_PIXEL_DATA_LENGTH_12 = 0x02,
|
||||
DVP_PIXEL_DATA_LENGTH_14 = 0x03
|
||||
} dvp_pdl_type;
|
||||
|
||||
/**
|
||||
* @brief dvp pcdc type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_PCDC_ALL = 0x00,
|
||||
DVP_PCDC_ONE_IN_TWO = 0x01,
|
||||
DVP_PCDC_ONE_IN_FOUR = 0x02,
|
||||
DVP_PCDC_TWO_IN_FOUR = 0x03
|
||||
} dvp_pcdc_type;
|
||||
|
||||
/**
|
||||
* @brief dvp pcds type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_PCDS_CAP_FIRST = 0x00,
|
||||
DVP_PCDS_DROP_FIRST = 0x01
|
||||
} dvp_pcds_type;
|
||||
|
||||
/**
|
||||
* @brief dvp lcdc type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_LCDC_ALL = 0x00,
|
||||
DVP_LCDC_ONE_IN_TWO = 0x01
|
||||
} dvp_lcdc_type;
|
||||
|
||||
/**
|
||||
* @brief dvp lcds type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_LCDS_CAP_FIRST = 0x00,
|
||||
DVP_LCDS_DROP_FIRST = 0x01
|
||||
} dvp_lcds_type;
|
||||
|
||||
/**
|
||||
* @brief dvp status basic type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_STATUS_HSYN = 0x00,
|
||||
DVP_STATUS_VSYN = 0x01,
|
||||
DVP_STATUS_OFS = 0x02
|
||||
} dvp_status_basic_type;
|
||||
|
||||
/**
|
||||
* @brief dvp pcdse type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_PCDSE_CAP_FIRST = 0x00,
|
||||
DVP_PCDSE_DROP_FIRST = 0x01
|
||||
} dvp_pcdse_type;
|
||||
|
||||
/**
|
||||
* @brief dvp efdf type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_EFDF_BYPASS = 0x00,
|
||||
DVP_EFDF_YUV422_UYVY = 0x04,
|
||||
DVP_EFDF_YUV422_YUYV = 0x05,
|
||||
DVP_EFDF_YUV444 = 0x06,
|
||||
DVP_EFDF_Y8 = 0x07
|
||||
} dvp_efdf_type;
|
||||
|
||||
/**
|
||||
* @brief dvp iduc type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_IDUC_MSB = 0x00,
|
||||
DVP_IDUC_LSB = 0x01
|
||||
} dvp_iduc_type;
|
||||
|
||||
/**
|
||||
* @brief dvp dmabt type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_DMABT_SINGLE = 0x00,
|
||||
DVP_DMABT_BURST = 0x01
|
||||
} dvp_dmabt_type;
|
||||
|
||||
/**
|
||||
* @brief dvp hseis type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_HSEIS_LINE_END = 0x00,
|
||||
DVP_HSEIS_LINE_START = 0x01
|
||||
} dvp_hseis_type;
|
||||
|
||||
/**
|
||||
* @brief dvp vseis type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_VSEIS_FRAME_END = 0x00,
|
||||
DVP_VSEIS_FRMAE_START = 0x01
|
||||
} dvp_vseis_type;
|
||||
/**
|
||||
* @brief dvp idun type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DVP_IDUN_0 = 0x00,
|
||||
DVP_IDUN_2 = 0x01,
|
||||
DVP_IDUN_4 = 0x02,
|
||||
DVP_IDUN_6 = 0x03
|
||||
} dvp_idun_type;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief dvp ctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cap : 1; /* [0] */
|
||||
__IO uint32_t cfm : 1; /* [1] */
|
||||
__IO uint32_t crp : 1; /* [2] */
|
||||
__IO uint32_t jpeg : 1; /* [3] */
|
||||
__IO uint32_t sm : 1; /* [4] */
|
||||
__IO uint32_t ckp : 1; /* [5] */
|
||||
__IO uint32_t hsp : 1; /* [6] */
|
||||
__IO uint32_t vsp : 1; /* [7] */
|
||||
__IO uint32_t bfrc : 2; /* [9:8] */
|
||||
__IO uint32_t pdl : 2; /* [11:10] */
|
||||
__IO uint32_t reserved1 : 2; /* [13:12] */
|
||||
__IO uint32_t ena : 1; /* [14] */
|
||||
__IO uint32_t reserved2 : 1; /* [15] */
|
||||
__IO uint32_t pcdc : 2; /* [17:16] */
|
||||
__IO uint32_t pcds : 1; /* [18] */
|
||||
__IO uint32_t lcdc : 1; /* [19] */
|
||||
__IO uint32_t lcds : 1; /* [20] */
|
||||
__IO uint32_t : 11;/* [31:21] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp sts register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t hsyn : 1; /* [0] */
|
||||
__IO uint32_t vsyn : 1; /* [1] */
|
||||
__IO uint32_t ofs : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 29;/* [31:3] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp ests register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ests;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cfdes : 1; /* [0] */
|
||||
__IO uint32_t ovres : 1; /* [1] */
|
||||
__IO uint32_t esees : 1; /* [2] */
|
||||
__IO uint32_t vses : 1; /* [3] */
|
||||
__IO uint32_t hses : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 27;/* [31:5] */
|
||||
} ests_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp ier register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ier;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cfdie : 1; /* [0] */
|
||||
__IO uint32_t ovrie : 1; /* [1] */
|
||||
__IO uint32_t eseie : 1; /* [2] */
|
||||
__IO uint32_t vsie : 1; /* [3] */
|
||||
__IO uint32_t hsie : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 27;/* [31:5] */
|
||||
} ier_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp ists register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ists;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cfdis : 1; /* [0] */
|
||||
__IO uint32_t ovris : 1; /* [1] */
|
||||
__IO uint32_t eseis : 1; /* [2] */
|
||||
__IO uint32_t vsis : 1; /* [3] */
|
||||
__IO uint32_t hsis : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 27;/* [31:5] */
|
||||
} ists_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp iclr register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t iclr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cfdic : 1; /* [0] */
|
||||
__IO uint32_t ovric : 1; /* [1] */
|
||||
__IO uint32_t eseic : 1; /* [2] */
|
||||
__IO uint32_t vsic : 1; /* [3] */
|
||||
__IO uint32_t hsic : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 27;/* [31:5] */
|
||||
} iclr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp scr register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t scr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fmsc : 8; /* [7:0] */
|
||||
__IO uint32_t lnsc : 8; /* [15:8] */
|
||||
__IO uint32_t lnec : 8; /* [23:16] */
|
||||
__IO uint32_t fmec : 8; /* [31:24] */
|
||||
} scr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp sur register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sur;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fmsu : 8; /* [7:0] */
|
||||
__IO uint32_t lnsu : 8; /* [15:8] */
|
||||
__IO uint32_t lneu : 8; /* [23:16] */
|
||||
__IO uint32_t fmeu : 8; /* [31:24] */
|
||||
} sur_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp cwst register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cwst;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t chstr : 14;/* [13:0] */
|
||||
__IO uint32_t reserved1 : 2; /* [15:14] */
|
||||
__IO uint32_t cvstr : 13;/* [28:16] */
|
||||
__IO uint32_t reserved2 : 3; /* [31:29] */
|
||||
} cwst_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp cwsz register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cwsz;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t chnum : 14;/* [13:0] */
|
||||
__IO uint32_t reserved1 : 2; /* [15:14] */
|
||||
__IO uint32_t cvnum : 14;/* [29:16] */
|
||||
__IO uint32_t reserved2 : 2; /* [31:30] */
|
||||
} cwsz_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp dt register, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dr0 : 8; /* [7:0] */
|
||||
__IO uint32_t dr1 : 8; /* [15:8] */
|
||||
__IO uint32_t dr2 : 8; /* [23:16] */
|
||||
__IO uint32_t dr3 : 8; /* [31:24] */
|
||||
} dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp reserved1 register, offset:0x2C-0x3C
|
||||
*/
|
||||
__IO uint32_t reserved1[5];
|
||||
|
||||
/**
|
||||
* @brief dvp actrl register, offset:0x40
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t actrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t eisre : 1; /* [0] */
|
||||
__IO uint32_t efrce : 1; /* [1] */
|
||||
__IO uint32_t mibe : 1; /* [2] */
|
||||
__IO uint32_t pcdse : 1; /* [3] */
|
||||
__IO uint32_t efdf : 3; /* [6:4] */
|
||||
__IO uint32_t reserved1 : 1; /* [7] */
|
||||
__IO uint32_t idun : 2; /* [9:8] */
|
||||
__IO uint32_t iduc : 1; /* [10] */
|
||||
__IO uint32_t reserved2 : 1; /* [11] */
|
||||
__IO uint32_t dmabt : 1; /* [12] */
|
||||
__IO uint32_t reserved3 : 1; /* [13] */
|
||||
__IO uint32_t reserved4 : 1; /* [14] */
|
||||
__IO uint32_t reserved5 : 1; /* [15] */
|
||||
__IO uint32_t hseis : 1; /* [16] */
|
||||
__IO uint32_t vseis : 1; /* [17] */
|
||||
__IO uint32_t reserved6 : 1; /* [18] */
|
||||
__IO uint32_t reserved7 : 2; /* [20:19] */
|
||||
__IO uint32_t reserved8 : 11;/* [31:21] */
|
||||
} actrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp reserved2 register, offset:0x44
|
||||
*/
|
||||
__IO uint32_t reserved2;
|
||||
|
||||
/**
|
||||
* @brief dvp hscf register, offset:0x48
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t hscf;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t hsrss : 13;/* [12:0] */
|
||||
__IO uint32_t reserved1 : 3; /* [15:13] */
|
||||
__IO uint32_t hsrts : 13;/* [28:16] */
|
||||
__IO uint32_t reserved2 : 3; /* [31:29] */
|
||||
} hscf_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp vscf register, offset:0x4C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t vscf;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vsrss : 13;/* [12:0] */
|
||||
__IO uint32_t reserved1 : 3; /* [15:13] */
|
||||
__IO uint32_t vsrts : 13;/* [28:16] */
|
||||
__IO uint32_t reserved2 : 3; /* [31:29] */
|
||||
} vscf_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp frf register, offset:0x50
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t frf;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t efrcfm : 5; /* [4:0] */
|
||||
__IO uint32_t reserved1 : 3; /* [7:5] */
|
||||
__IO uint32_t efrcfn : 5; /* [12:8] */
|
||||
__IO uint32_t reserved2 : 19;/* [31:13] */
|
||||
} frf_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dvp bth register, offset:0x54
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t bth;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t mibthd : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} bth_bit;
|
||||
};
|
||||
|
||||
} dvp_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define DVP ((dvp_type *) DVP_BASE)
|
||||
|
||||
/** @defgroup DVP_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void dvp_capture_enable(confirm_state new_state);
|
||||
void dvp_capture_mode_set(dvp_cfm_type cap_mode);
|
||||
void dvp_window_crop_enable(confirm_state new_state);
|
||||
void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h);
|
||||
void dvp_jpeg_enable(confirm_state new_state);
|
||||
void dvp_sync_mode_set(dvp_sm_type sync_mode);
|
||||
void dvp_sync_code_set(uint8_t fmsc, uint8_t fmec, uint8_t lnsc, uint8_t lnec);
|
||||
void dvp_sync_unmask_set(uint8_t fmsu, uint8_t fmeu, uint8_t lnsu, uint8_t lneu);
|
||||
void dvp_pclk_polarity_set(dvp_ckp_type eage);
|
||||
void dvp_hsync_polarity_set(dvp_hsp_type hsync_pol);
|
||||
void dvp_vsync_polarity_set(dvp_vsp_type vsync_pol);
|
||||
void dvp_basic_frame_rate_control_set(dvp_bfrc_type dvp_bfrc);
|
||||
void dvp_pixel_data_length_set(dvp_pdl_type dvp_pdl);
|
||||
void dvp_enable(confirm_state new_state);
|
||||
void dvp_zoomout_select(dvp_pcdse_type dvp_pcdse);
|
||||
void dvp_zoomout_set(dvp_pcdc_type dvp_pcdc, dvp_pcds_type dvp_pcds, dvp_lcdc_type dvp_lcdc, dvp_lcds_type dvp_lcds);
|
||||
flag_status dvp_basic_status_get(dvp_status_basic_type dvp_status_basic);
|
||||
void dvp_interrupt_enable(uint32_t dvp_int, confirm_state new_state);
|
||||
flag_status dvp_flag_get(uint32_t flag);
|
||||
void dvp_flag_clear(uint32_t flag);
|
||||
void dvp_enhanced_scaling_resize_enable(confirm_state new_state);
|
||||
void dvp_enhanced_scaling_resize_set(uint16_t src_w, uint16_t des_w, uint16_t src_h, uint16_t des_h);
|
||||
void dvp_enhanced_framerate_set(uint16_t efrcfm, uint16_t efrcfn, confirm_state new_state);
|
||||
void dvp_monochrome_image_binarization_set(uint8_t mibthd, confirm_state new_state);
|
||||
void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf);
|
||||
void dvp_input_data_unused_set(dvp_iduc_type dvp_iduc, dvp_idun_type dvp_idun);
|
||||
void dvp_dma_burst_set(dvp_dmabt_type dvp_dmabt);
|
||||
void dvp_sync_event_interrupt_set(dvp_hseis_type dvp_hseis, dvp_vseis_type dvp_vseis);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,234 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_exint.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 exint header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_EXINT_H
|
||||
#define __AT32F435_437_EXINT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXINT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXINT_lines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXINT_LINE_NONE ((uint32_t)0x000000)
|
||||
#define EXINT_LINE_0 ((uint32_t)0x000001) /*!< external interrupt line 0 */
|
||||
#define EXINT_LINE_1 ((uint32_t)0x000002) /*!< external interrupt line 1 */
|
||||
#define EXINT_LINE_2 ((uint32_t)0x000004) /*!< external interrupt line 2 */
|
||||
#define EXINT_LINE_3 ((uint32_t)0x000008) /*!< external interrupt line 3 */
|
||||
#define EXINT_LINE_4 ((uint32_t)0x000010) /*!< external interrupt line 4 */
|
||||
#define EXINT_LINE_5 ((uint32_t)0x000020) /*!< external interrupt line 5 */
|
||||
#define EXINT_LINE_6 ((uint32_t)0x000040) /*!< external interrupt line 6 */
|
||||
#define EXINT_LINE_7 ((uint32_t)0x000080) /*!< external interrupt line 7 */
|
||||
#define EXINT_LINE_8 ((uint32_t)0x000100) /*!< external interrupt line 8 */
|
||||
#define EXINT_LINE_9 ((uint32_t)0x000200) /*!< external interrupt line 9 */
|
||||
#define EXINT_LINE_10 ((uint32_t)0x000400) /*!< external interrupt line 10 */
|
||||
#define EXINT_LINE_11 ((uint32_t)0x000800) /*!< external interrupt line 11 */
|
||||
#define EXINT_LINE_12 ((uint32_t)0x001000) /*!< external interrupt line 12 */
|
||||
#define EXINT_LINE_13 ((uint32_t)0x002000) /*!< external interrupt line 13 */
|
||||
#define EXINT_LINE_14 ((uint32_t)0x004000) /*!< external interrupt line 14 */
|
||||
#define EXINT_LINE_15 ((uint32_t)0x008000) /*!< external interrupt line 15 */
|
||||
#define EXINT_LINE_16 ((uint32_t)0x010000) /*!< external interrupt line 16 */
|
||||
#define EXINT_LINE_17 ((uint32_t)0x020000) /*!< external interrupt line 17 */
|
||||
#define EXINT_LINE_18 ((uint32_t)0x040000) /*!< external interrupt line 18 */
|
||||
#define EXINT_LINE_19 ((uint32_t)0x080000) /*!< external interrupt line 19 */
|
||||
#define EXINT_LINE_20 ((uint32_t)0x100000) /*!< external interrupt line 20 */
|
||||
#define EXINT_LINE_21 ((uint32_t)0x200000) /*!< external interrupt line 21 */
|
||||
#define EXINT_LINE_22 ((uint32_t)0x400000) /*!< external interrupt line 22 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXINT_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief exint line mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXINT_LINE_INTERRUPUT = 0x00, /*!< external interrupt line interrupt mode */
|
||||
EXINT_LINE_EVENT = 0x01 /*!< external interrupt line event mode */
|
||||
} exint_line_mode_type;
|
||||
|
||||
/**
|
||||
* @brief exint polarity configuration type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXINT_TRIGGER_RISING_EDGE = 0x00, /*!< external interrupt line rising trigger mode */
|
||||
EXINT_TRIGGER_FALLING_EDGE = 0x01, /*!< external interrupt line falling trigger mode */
|
||||
EXINT_TRIGGER_BOTH_EDGE = 0x02 /*!< external interrupt line both rising and falling trigger mode */
|
||||
} exint_polarity_config_type;
|
||||
|
||||
/**
|
||||
* @brief exint init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
exint_line_mode_type line_mode; /*!< choose mode event or interrupt mode */
|
||||
uint32_t line_select; /*!< select the exint line, availiable for single line or multiple lines */
|
||||
exint_polarity_config_type line_polarity; /*!< select the tregger polarity, with rising edge, falling edge or both edge */
|
||||
confirm_state line_enable; /*!< enable or disable exint */
|
||||
} exint_init_type;
|
||||
|
||||
/**
|
||||
* @brief type define exint register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief exint inten register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t inten;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t intenx : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} inten_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint evten register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t evten;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t evtenx : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} evten_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint polcfg1 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t polcfg1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rpx : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} polcfg1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint polcfg2 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t polcfg2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fpx : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} polcfg2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint swtrg register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t swtrg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t swtx : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} swtrg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint intsts register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t intsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t linex : 23;/* [22:0] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} intsts_bit;
|
||||
};
|
||||
} exint_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define EXINT ((exint_type *) EXINT_BASE)
|
||||
|
||||
/** @defgroup EXINT_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void exint_reset(void);
|
||||
void exint_default_para_init(exint_init_type *exint_struct);
|
||||
void exint_init(exint_init_type *exint_struct);
|
||||
void exint_flag_clear(uint32_t exint_line);
|
||||
flag_status exint_flag_get(uint32_t exint_line);
|
||||
void exint_software_interrupt_event_generate(uint32_t exint_line);
|
||||
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state);
|
||||
void exint_event_enable(uint32_t exint_line, confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,724 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_flash.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 flash header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_FLASH_H
|
||||
#define __AT32F435_437_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_exported_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief flash unlock keys
|
||||
*/
|
||||
#define FLASH_UNLOCK_KEY1 ((uint32_t)0x45670123) /*!< flash operation unlock order key1 */
|
||||
#define FLASH_UNLOCK_KEY2 ((uint32_t)0xCDEF89AB) /*!< flash operation unlock order key2 */
|
||||
#define FAP_RELIEVE_KEY ((uint16_t)0x00A5) /*!< flash fap relieve key val */
|
||||
#define SLIB_UNLOCK_KEY ((uint32_t)0xA35F6D24) /*!< flash slib operation unlock order key */
|
||||
|
||||
/**
|
||||
* @brief flash bank address
|
||||
*/
|
||||
#if defined (AT32F435CMU7) || defined (AT32F435CMT7) || defined (AT32F435RMT7) || \
|
||||
defined (AT32F435VMT7) || defined (AT32F435ZMT7) || defined (AT32F437RMT7) || \
|
||||
defined (AT32F437VMT7) || defined (AT32F437ZMT7)
|
||||
#define FLASH_BANK1_START_ADDR ((uint32_t)0x08000000) /*!< flash start address of bank1 */
|
||||
#define FLASH_BANK1_END_ADDR ((uint32_t)0x081FFFFF) /*!< flash end address of bank1 */
|
||||
#define FLASH_BANK2_START_ADDR ((uint32_t)0x08200000) /*!< flash start address of bank2 */
|
||||
#define FLASH_BANK2_END_ADDR ((uint32_t)0x083EFFFF) /*!< flash end address of bank2 */
|
||||
#else
|
||||
#define FLASH_BANK1_START_ADDR ((uint32_t)0x08000000) /*!< flash start address of bank1 */
|
||||
#define FLASH_BANK1_END_ADDR ((uint32_t)0x0807FFFF) /*!< flash end address of bank1 */
|
||||
#define FLASH_BANK2_START_ADDR ((uint32_t)0x08080000) /*!< flash start address of bank2 */
|
||||
#define FLASH_BANK2_END_ADDR ((uint32_t)0x080FFFFF) /*!< flash end address of bank2 */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief flash flag
|
||||
*/
|
||||
#define FLASH_OBF_FLAG FLASH_BANK1_OBF_FLAG /*!< flash operate busy flag */
|
||||
#define FLASH_ODF_FLAG FLASH_BANK1_ODF_FLAG /*!< flash operate done flag */
|
||||
#define FLASH_PRGMERR_FLAG FLASH_BANK1_PRGMERR_FLAG /*!< flash program error flag */
|
||||
#define FLASH_EPPERR_FLAG FLASH_BANK1_EPPERR_FLAG /*!< flash erase/program protection error flag */
|
||||
#define FLASH_BANK1_OBF_FLAG ((uint32_t)0x00000001) /*!< flash bank1 operate busy flag */
|
||||
#define FLASH_BANK1_ODF_FLAG ((uint32_t)0x00000020) /*!< flash bank1 operate done flag */
|
||||
#define FLASH_BANK1_PRGMERR_FLAG ((uint32_t)0x00000004) /*!< flash bank1 program error flag */
|
||||
#define FLASH_BANK1_EPPERR_FLAG ((uint32_t)0x00000010) /*!< flash bank1 erase/program protection error flag */
|
||||
#define FLASH_BANK2_OBF_FLAG ((uint32_t)0x10000001) /*!< flash bank2 operate busy flag */
|
||||
#define FLASH_BANK2_ODF_FLAG ((uint32_t)0x10000020) /*!< flash bank2 operate done flag */
|
||||
#define FLASH_BANK2_PRGMERR_FLAG ((uint32_t)0x10000004) /*!< flash bank2 program error flag */
|
||||
#define FLASH_BANK2_EPPERR_FLAG ((uint32_t)0x10000010) /*!< flash bank2 erase/program protection error flag */
|
||||
#define FLASH_USDERR_FLAG ((uint32_t)0x40000001) /*!< flash user system data error flag */
|
||||
|
||||
/**
|
||||
* @brief flash interrupts
|
||||
*/
|
||||
#define FLASH_ERR_INT FLASH_BANK1_ERR_INT /*!< flash error interrupt */
|
||||
#define FLASH_ODF_INT FLASH_BANK1_ODF_INT /*!< flash operate done interrupt */
|
||||
#define FLASH_BANK1_ERR_INT ((uint32_t)0x00000001) /*!< flash bank1 error interrupt */
|
||||
#define FLASH_BANK1_ODF_INT ((uint32_t)0x00000002) /*!< flash bank1 operate done interrupt */
|
||||
#define FLASH_BANK2_ERR_INT ((uint32_t)0x00000004) /*!< flash bank2 error interrupt */
|
||||
#define FLASH_BANK2_ODF_INT ((uint32_t)0x00000008) /*!< flash bank2 operate done interrupt */
|
||||
|
||||
/**
|
||||
* @brief flash slib mask
|
||||
*/
|
||||
#define FLASH_SLIB_START_SECTOR ((uint32_t)0x0000FFFF) /*!< flash slib start sector */
|
||||
#define FLASH_SLIB_INST_START_SECTOR ((uint32_t)0x0000FFFF) /*!< flash slib i-bus area start sector */
|
||||
#define FLASH_SLIB_END_SECTOR ((uint32_t)0xFFFF0000) /*!< flash slib end sector */
|
||||
|
||||
/**
|
||||
* @brief user system data wdt_ato
|
||||
*/
|
||||
#define USD_WDT_ATO_DISABLE ((uint16_t)0x0001) /*!< wdt auto start disabled */
|
||||
#define USD_WDT_ATO_ENABLE ((uint16_t)0x0000) /*!< wdt auto start enabled */
|
||||
|
||||
/**
|
||||
* @brief user system data depslp_rst
|
||||
*/
|
||||
#define USD_DEPSLP_NO_RST ((uint16_t)0x0002) /*!< no reset generated when entering in deepsleep */
|
||||
#define USD_DEPSLP_RST ((uint16_t)0x0000) /*!< reset generated when entering in deepsleep */
|
||||
|
||||
/**
|
||||
* @brief user system data stdby_rst
|
||||
*/
|
||||
#define USD_STDBY_NO_RST ((uint16_t)0x0004) /*!< no reset generated when entering in standby */
|
||||
#define USD_STDBY_RST ((uint16_t)0x0000) /*!< reset generated when entering in standby */
|
||||
|
||||
/**
|
||||
* @brief user system data btopt
|
||||
*/
|
||||
#define FLASH_BOOT_FROM_BANK1 ((uint16_t)0x0008) /*!< boot from bank1 */
|
||||
#define FLASH_BOOT_FROM_BANK2 ((uint16_t)0x0000) /*!< boot from bank 2 or bank 1,depending on the activation of the bank */
|
||||
|
||||
/**
|
||||
* @brief user system data wdt_depslp
|
||||
*/
|
||||
#define USD_WDT_DEPSLP_CONTINUE ((uint16_t)0x0020) /*!< wdt continue count when entering in deepsleep */
|
||||
#define USD_WDT_DEPSLP_STOP ((uint16_t)0x0000) /*!< wdt stop count when entering in deepsleep */
|
||||
|
||||
/**
|
||||
* @brief user system data wdt_stdby
|
||||
*/
|
||||
#define USD_WDT_STDBY_CONTINUE ((uint16_t)0x0020) /*!< wdt continue count when entering in standby */
|
||||
#define USD_WDT_STDBY_STOP ((uint16_t)0x0000) /*!< wdt stop count when entering in standby */
|
||||
|
||||
/**
|
||||
* @brief flash timeout definition
|
||||
*/
|
||||
#define ERASE_TIMEOUT ((uint32_t)0x80000000) /*!< internal flash erase operation timeout */
|
||||
#define PROGRAMMING_TIMEOUT ((uint32_t)0x00100000) /*!< internal flash program operation timeout */
|
||||
#define OPERATION_TIMEOUT ((uint32_t)0x10000000) /*!< flash common operation timeout */
|
||||
|
||||
/**
|
||||
* @brief set the flash clock divider definition
|
||||
* @param div: the flash clock divider.
|
||||
* this parameter can be one of the following values:
|
||||
* - FLASH_CLOCK_DIV_2
|
||||
* - FLASH_CLOCK_DIV_3
|
||||
* - FLASH_CLOCK_DIV_4
|
||||
*/
|
||||
#define flash_clock_divider_set(div) (FLASH->divr_bit.fdiv = div)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief flash usd eopb0 type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_EOPB0_SRAM_512K = 0x00, /*!< sram 512k, flash zw area 128k */
|
||||
FLASH_EOPB0_SRAM_448K = 0x01, /*!< sram 448k, flash zw area 192k */
|
||||
FLASH_EOPB0_SRAM_384K = 0x02, /*!< sram 384k, flash zw area 256k */
|
||||
FLASH_EOPB0_SRAM_320K = 0x03, /*!< sram 320k, flash zw area 320k */
|
||||
FLASH_EOPB0_SRAM_256K = 0x04, /*!< sram 256k, flash zw area 384k */
|
||||
FLASH_EOPB0_SRAM_192K = 0x05, /*!< sram 192k, flash zw area 448k */
|
||||
FLASH_EOPB0_SRAM_128K = 0x06 /*!< sram 128k, flash zw area 512k */
|
||||
} flash_usd_eopb0_type;
|
||||
|
||||
/**
|
||||
* @brief flash clock divider type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_CLOCK_DIV_2 = 0x00, /*!< flash clock divide by 2 */
|
||||
FLASH_CLOCK_DIV_3 = 0x01, /*!< flash clock divide by 3 */
|
||||
FLASH_CLOCK_DIV_4 = 0x02 /*!< flash clock divide by 4 */
|
||||
} flash_clock_divider_type;
|
||||
|
||||
/**
|
||||
* @brief flash status type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_OPERATE_BUSY = 0x00, /*!< flash status is operate busy */
|
||||
FLASH_PROGRAM_ERROR = 0x01, /*!< flash status is program error */
|
||||
FLASH_EPP_ERROR = 0x02, /*!< flash status is epp error */
|
||||
FLASH_OPERATE_DONE = 0x03, /*!< flash status is operate done */
|
||||
FLASH_OPERATE_TIMEOUT = 0x04 /*!< flash status is operate timeout */
|
||||
} flash_status_type;
|
||||
|
||||
/**
|
||||
* @brief type define flash register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief flash psr register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t psr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 12;/* [11:0] */
|
||||
__IO uint32_t nzw_bst : 1; /* [12] */
|
||||
__IO uint32_t nzw_bst_sts : 1; /* [13] */
|
||||
__IO uint32_t reserved2 : 18;/* [31:14] */
|
||||
} psr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash unlock register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t unlock;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ukval : 32;/* [31:0] */
|
||||
} unlock_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash usd unlock register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t usd_unlock;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t usd_ukval : 32;/* [31:0] */
|
||||
} usd_unlock_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash sts register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t obf : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 1; /* [1] */
|
||||
__IO uint32_t prgmerr : 1; /* [2] */
|
||||
__IO uint32_t reserved2 : 1; /* [3] */
|
||||
__IO uint32_t epperr : 1; /* [4] */
|
||||
__IO uint32_t odf : 1; /* [5] */
|
||||
__IO uint32_t reserved3 : 26;/* [31:6] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash ctrl register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fprgm : 1; /* [0] */
|
||||
__IO uint32_t secers : 1; /* [1] */
|
||||
__IO uint32_t bankers : 1; /* [2] */
|
||||
__IO uint32_t blkers : 1; /* [3] */
|
||||
__IO uint32_t usdprgm : 1; /* [4] */
|
||||
__IO uint32_t usders : 1; /* [5] */
|
||||
__IO uint32_t erstr : 1; /* [6] */
|
||||
__IO uint32_t oplk : 1; /* [7] */
|
||||
__IO uint32_t reserved1 : 1; /* [8] */
|
||||
__IO uint32_t usdulks : 1; /* [9] */
|
||||
__IO uint32_t errie : 1; /* [10] */
|
||||
__IO uint32_t reserved2 : 1; /* [11] */
|
||||
__IO uint32_t odfie : 1; /* [12] */
|
||||
__IO uint32_t reserved3 : 19;/* [31:13] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash addr register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t addr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fa : 32;/* [31:0] */
|
||||
} addr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved1 register, offset:0x18
|
||||
*/
|
||||
__IO uint32_t reserved1;
|
||||
|
||||
/**
|
||||
* @brief flash usd register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t usd;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t usderr : 1; /* [0] */
|
||||
__IO uint32_t fap : 1; /* [1] */
|
||||
__IO uint32_t wdt_ato_en : 1; /* [2] */
|
||||
__IO uint32_t depslp_rst : 1; /* [3] */
|
||||
__IO uint32_t stdby_rst : 1; /* [4] */
|
||||
__IO uint32_t btopt : 1; /* [5] */
|
||||
__IO uint32_t reserved1 : 1; /* [6] */
|
||||
__IO uint32_t wdt_depslp : 1; /* [7] */
|
||||
__IO uint32_t wdt_stdby : 1; /* [8] */
|
||||
__IO uint32_t reserved2 : 1; /* [9] */
|
||||
__IO uint32_t user_d0 : 8; /* [17:10] */
|
||||
__IO uint32_t user_d1 : 8; /* [25:18] */
|
||||
__IO uint32_t reserved3 : 6; /* [31:26] */
|
||||
} usd_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash epps0 register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t epps0;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t epps : 32;/* [31:0] */
|
||||
} epps0_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved2 register, offset:0x28~0x24
|
||||
*/
|
||||
__IO uint32_t reserved2[2];
|
||||
|
||||
/**
|
||||
* @brief flash epps1 register, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t epps1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t epps : 32;/* [31:0] */
|
||||
} epps1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved3 register, offset:0x40~0x30
|
||||
*/
|
||||
__IO uint32_t reserved3[5];
|
||||
|
||||
/**
|
||||
* @brief flash unlock2 register, offset:0x44
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t unlock2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ukval : 32;/* [31:0] */
|
||||
} unlock2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved4 register, offset:0x48
|
||||
*/
|
||||
__IO uint32_t reserved4;
|
||||
|
||||
/**
|
||||
* @brief flash sts2 register, offset:0x4C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t obf : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 1; /* [1] */
|
||||
__IO uint32_t prgmerr : 1; /* [2] */
|
||||
__IO uint32_t reserved2 : 1; /* [3] */
|
||||
__IO uint32_t epperr : 1; /* [4] */
|
||||
__IO uint32_t odf : 1; /* [5] */
|
||||
__IO uint32_t reserved3 : 26;/* [31:6] */
|
||||
} sts2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash ctrl2 register, offset:0x50
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fprgm : 1; /* [0] */
|
||||
__IO uint32_t secers : 1; /* [1] */
|
||||
__IO uint32_t bankers : 1; /* [2] */
|
||||
__IO uint32_t blkers : 1; /* [3] */
|
||||
__IO uint32_t reserved1 : 2; /* [5:4] */
|
||||
__IO uint32_t erstr : 1; /* [6] */
|
||||
__IO uint32_t oplk : 1; /* [7] */
|
||||
__IO uint32_t reserved2 : 2; /* [9:8] */
|
||||
__IO uint32_t errie : 1; /* [10] */
|
||||
__IO uint32_t reserved3 : 1; /* [11] */
|
||||
__IO uint32_t odfie : 1; /* [12] */
|
||||
__IO uint32_t reserved4 : 19;/* [31:13] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash addr2 register, offset:0x54
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t addr2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fa : 32;/* [31:0] */
|
||||
} addr2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash contr register, offset:0x58
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t contr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 31;/* [30:0] */
|
||||
__IO uint32_t fcontr_en : 1; /* [31] */
|
||||
} contr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved5 register, offset:0x5C
|
||||
*/
|
||||
__IO uint32_t reserved5;
|
||||
|
||||
/**
|
||||
* @brief flash divr register, offset:0x60
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t divr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fdiv : 2; /* [1:0] */
|
||||
__IO uint32_t reserved1 : 2; /* [3:2] */
|
||||
__IO uint32_t fdiv_sts : 2; /* [5:4] */
|
||||
__IO uint32_t reserved2 : 26;/* [31:6] */
|
||||
} divr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved6 register, offset:0xC4~0x64
|
||||
*/
|
||||
__IO uint32_t reserved6[25];
|
||||
|
||||
/**
|
||||
* @brief flash slib_sts2 register, offset:0xC8
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_sts2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_inst_ss : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} slib_sts2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_sts0 register, offset:0xCC
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_sts0;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 3; /* [2:0] */
|
||||
__IO uint32_t slib_enf : 1; /* [3] */
|
||||
__IO uint32_t reserved2 : 28;/* [31:4] */
|
||||
} slib_sts0_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_sts1 register, offset:0xD0
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_sts1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_ss : 16;/* [15:0] */
|
||||
__IO uint32_t slib_es : 16;/* [31:16] */
|
||||
} slib_sts1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_pwd_clr register, offset:0xD4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_pwd_clr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_pclr_val : 32;/* [31:0] */
|
||||
} slib_pwd_clr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_misc_sts register, offset:0xD8
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_misc_sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_pwd_err : 1; /* [0] */
|
||||
__IO uint32_t slib_pwd_ok : 1; /* [1] */
|
||||
__IO uint32_t slib_ulkf : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 13;/* [15:3] */
|
||||
__IO uint32_t slib_rcnt : 9; /* [24:16] */
|
||||
__IO uint32_t reserved2 : 7; /* [31:25] */
|
||||
} slib_misc_sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_set_pwd register, offset:0xDC
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_set_pwd;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_pset_val : 32;/* [31:0] */
|
||||
} slib_set_pwd_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_set_range0 register, offset:0xE0
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_set_range0;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_ss_set : 16;/* [15:0] */
|
||||
__IO uint32_t slib_es_set : 16;/* [31:16] */
|
||||
} slib_set_range0_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_set_range1 register, offset:0xE4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_set_range1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_iss_set : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 15;/* [30:16] */
|
||||
__IO uint32_t set_slib_strt : 1; /* [31] */
|
||||
} slib_set_range1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved7 register, offset:0xEC~0xE8
|
||||
*/
|
||||
__IO uint32_t reserved7[2];
|
||||
|
||||
/**
|
||||
* @brief flash slib_unlock register, offset:0xF0
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_unlock;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_ukval : 32;/* [31:0] */
|
||||
} slib_unlock_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash crc_ctrl register, offset:0xF4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t crc_ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t crc_ss : 12;/* [11:0] */
|
||||
__IO uint32_t crc_sn : 12;/* [23:12] */
|
||||
__IO uint32_t reserved1 : 7; /* [30:24] */
|
||||
__IO uint32_t crc_strt : 1; /* [31] */
|
||||
} crc_ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash crc_chkr register, offset:0xF8
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t crc_chkr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t crc_chkr : 32;/* [31:0] */
|
||||
} crc_chkr_bit;
|
||||
};
|
||||
|
||||
} flash_type;
|
||||
|
||||
/**
|
||||
* @brief user system data
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint16_t fap;
|
||||
__IO uint16_t ssb;
|
||||
__IO uint16_t data0;
|
||||
__IO uint16_t data1;
|
||||
__IO uint16_t epp0;
|
||||
__IO uint16_t epp1;
|
||||
__IO uint16_t epp2;
|
||||
__IO uint16_t epp3;
|
||||
__IO uint16_t eopb0;
|
||||
__IO uint16_t reserved1;
|
||||
__IO uint16_t epp4;
|
||||
__IO uint16_t epp5;
|
||||
__IO uint16_t epp6;
|
||||
__IO uint16_t epp7;
|
||||
__IO uint16_t reserved2[12];
|
||||
__IO uint16_t qspikey[8];
|
||||
} usd_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define FLASH ((flash_type *) FLASH_REG_BASE)
|
||||
#define USD ((usd_type *) USD_BASE)
|
||||
|
||||
/** @defgroup FLASH_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
flag_status flash_flag_get(uint32_t flash_flag);
|
||||
void flash_flag_clear(uint32_t flash_flag);
|
||||
flash_status_type flash_operation_status_get(void);
|
||||
flash_status_type flash_bank1_operation_status_get(void);
|
||||
flash_status_type flash_bank2_operation_status_get(void);
|
||||
flash_status_type flash_operation_wait_for(uint32_t time_out);
|
||||
flash_status_type flash_bank1_operation_wait_for(uint32_t time_out);
|
||||
flash_status_type flash_bank2_operation_wait_for(uint32_t time_out);
|
||||
void flash_unlock(void);
|
||||
void flash_bank1_unlock(void);
|
||||
void flash_bank2_unlock(void);
|
||||
void flash_lock(void);
|
||||
void flash_bank1_lock(void);
|
||||
void flash_bank2_lock(void);
|
||||
flash_status_type flash_sector_erase(uint32_t sector_address);
|
||||
flash_status_type flash_block_erase(uint32_t block_address);
|
||||
flash_status_type flash_internal_all_erase(void);
|
||||
flash_status_type flash_bank1_erase(void);
|
||||
flash_status_type flash_bank2_erase(void);
|
||||
flash_status_type flash_user_system_data_erase(void);
|
||||
flash_status_type flash_eopb0_config(flash_usd_eopb0_type data);
|
||||
flash_status_type flash_word_program(uint32_t address, uint32_t data);
|
||||
flash_status_type flash_halfword_program(uint32_t address, uint16_t data);
|
||||
flash_status_type flash_byte_program(uint32_t address, uint8_t data);
|
||||
flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data);
|
||||
flash_status_type flash_epp_set(uint32_t *sector_bits);
|
||||
void flash_epp_status_get(uint32_t *sector_bits);
|
||||
flash_status_type flash_fap_enable(confirm_state new_state);
|
||||
flag_status flash_fap_status_get(void);
|
||||
flash_status_type flash_ssb_set(uint8_t usd_ssb);
|
||||
uint8_t flash_ssb_status_get(void);
|
||||
void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state);
|
||||
flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t inst_start_sector, uint16_t end_sector);
|
||||
error_status flash_slib_disable(uint32_t pwd);
|
||||
uint32_t flash_slib_remaining_count_get(void);
|
||||
flag_status flash_slib_state_get(void);
|
||||
uint16_t flash_slib_start_sector_get(void);
|
||||
uint16_t flash_slib_inststart_sector_get(void);
|
||||
uint16_t flash_slib_end_sector_get(void);
|
||||
uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt);
|
||||
void flash_nzw_boost_enable(confirm_state new_state);
|
||||
void flash_continue_read_enable(confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,565 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_gpio.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 gpio header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_GPIO_H
|
||||
#define __AT32F435_437_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_number_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_PINS_0 0x0001 /*!< gpio pins number 0 */
|
||||
#define GPIO_PINS_1 0x0002 /*!< gpio pins number 1 */
|
||||
#define GPIO_PINS_2 0x0004 /*!< gpio pins number 2 */
|
||||
#define GPIO_PINS_3 0x0008 /*!< gpio pins number 3 */
|
||||
#define GPIO_PINS_4 0x0010 /*!< gpio pins number 4 */
|
||||
#define GPIO_PINS_5 0x0020 /*!< gpio pins number 5 */
|
||||
#define GPIO_PINS_6 0x0040 /*!< gpio pins number 6 */
|
||||
#define GPIO_PINS_7 0x0080 /*!< gpio pins number 7 */
|
||||
#define GPIO_PINS_8 0x0100 /*!< gpio pins number 8 */
|
||||
#define GPIO_PINS_9 0x0200 /*!< gpio pins number 9 */
|
||||
#define GPIO_PINS_10 0x0400 /*!< gpio pins number 10 */
|
||||
#define GPIO_PINS_11 0x0800 /*!< gpio pins number 11 */
|
||||
#define GPIO_PINS_12 0x1000 /*!< gpio pins number 12 */
|
||||
#define GPIO_PINS_13 0x2000 /*!< gpio pins number 13 */
|
||||
#define GPIO_PINS_14 0x4000 /*!< gpio pins number 14 */
|
||||
#define GPIO_PINS_15 0x8000 /*!< gpio pins number 15 */
|
||||
#define GPIO_PINS_ALL 0xFFFF /*!< gpio all pins */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief gpio mode select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_MODE_INPUT = 0x00, /*!< gpio input mode */
|
||||
GPIO_MODE_OUTPUT = 0x01, /*!< gpio output mode */
|
||||
GPIO_MODE_MUX = 0x02, /*!< gpio mux function mode */
|
||||
GPIO_MODE_ANALOG = 0x03 /*!< gpio analog in/out mode */
|
||||
} gpio_mode_type;
|
||||
|
||||
/**
|
||||
* @brief gpio output drive strength select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_DRIVE_STRENGTH_STRONGER = 0x01, /*!< stronger sourcing/sinking strength */
|
||||
GPIO_DRIVE_STRENGTH_MODERATE = 0x02 /*!< moderate sourcing/sinking strength */
|
||||
} gpio_drive_type;
|
||||
|
||||
/**
|
||||
* @brief gpio output type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_OUTPUT_PUSH_PULL = 0x00, /*!< output push-pull */
|
||||
GPIO_OUTPUT_OPEN_DRAIN = 0x01 /*!< output open-drain */
|
||||
} gpio_output_type;
|
||||
|
||||
/**
|
||||
* @brief gpio pull type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PULL_NONE = 0x00, /*!< floating for input, no pull for output */
|
||||
GPIO_PULL_UP = 0x01, /*!< pull-up */
|
||||
GPIO_PULL_DOWN = 0x02 /*!< pull-down */
|
||||
} gpio_pull_type;
|
||||
|
||||
/**
|
||||
* @brief gpio init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t gpio_pins; /*!< pins number selection */
|
||||
gpio_output_type gpio_out_type; /*!< output type selection */
|
||||
gpio_pull_type gpio_pull; /*!< pull type selection */
|
||||
gpio_mode_type gpio_mode; /*!< mode selection */
|
||||
gpio_drive_type gpio_drive_strength; /*!< drive strength selection */
|
||||
} gpio_init_type;
|
||||
|
||||
/**
|
||||
* @brief gpio pins source type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PINS_SOURCE0 = 0x00, /*!< gpio pins source number 0 */
|
||||
GPIO_PINS_SOURCE1 = 0x01, /*!< gpio pins source number 1 */
|
||||
GPIO_PINS_SOURCE2 = 0x02, /*!< gpio pins source number 2 */
|
||||
GPIO_PINS_SOURCE3 = 0x03, /*!< gpio pins source number 3 */
|
||||
GPIO_PINS_SOURCE4 = 0x04, /*!< gpio pins source number 4 */
|
||||
GPIO_PINS_SOURCE5 = 0x05, /*!< gpio pins source number 5 */
|
||||
GPIO_PINS_SOURCE6 = 0x06, /*!< gpio pins source number 6 */
|
||||
GPIO_PINS_SOURCE7 = 0x07, /*!< gpio pins source number 7 */
|
||||
GPIO_PINS_SOURCE8 = 0x08, /*!< gpio pins source number 8 */
|
||||
GPIO_PINS_SOURCE9 = 0x09, /*!< gpio pins source number 9 */
|
||||
GPIO_PINS_SOURCE10 = 0x0A, /*!< gpio pins source number 10 */
|
||||
GPIO_PINS_SOURCE11 = 0x0B, /*!< gpio pins source number 11 */
|
||||
GPIO_PINS_SOURCE12 = 0x0C, /*!< gpio pins source number 12 */
|
||||
GPIO_PINS_SOURCE13 = 0x0D, /*!< gpio pins source number 13 */
|
||||
GPIO_PINS_SOURCE14 = 0x0E, /*!< gpio pins source number 14 */
|
||||
GPIO_PINS_SOURCE15 = 0x0F /*!< gpio pins source number 15 */
|
||||
} gpio_pins_source_type;
|
||||
|
||||
/**
|
||||
* @brief gpio muxing function selection type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_MUX_0 = 0x00, /*!< gpio muxing function selection 0 */
|
||||
GPIO_MUX_1 = 0x01, /*!< gpio muxing function selection 1 */
|
||||
GPIO_MUX_2 = 0x02, /*!< gpio muxing function selection 2 */
|
||||
GPIO_MUX_3 = 0x03, /*!< gpio muxing function selection 3 */
|
||||
GPIO_MUX_4 = 0x04, /*!< gpio muxing function selection 4 */
|
||||
GPIO_MUX_5 = 0x05, /*!< gpio muxing function selection 5 */
|
||||
GPIO_MUX_6 = 0x06, /*!< gpio muxing function selection 6 */
|
||||
GPIO_MUX_7 = 0x07, /*!< gpio muxing function selection 7 */
|
||||
GPIO_MUX_8 = 0x08, /*!< gpio muxing function selection 8 */
|
||||
GPIO_MUX_9 = 0x09, /*!< gpio muxing function selection 9 */
|
||||
GPIO_MUX_10 = 0x0A, /*!< gpio muxing function selection 10 */
|
||||
GPIO_MUX_11 = 0x0B, /*!< gpio muxing function selection 11 */
|
||||
GPIO_MUX_12 = 0x0C, /*!< gpio muxing function selection 12 */
|
||||
GPIO_MUX_13 = 0x0D, /*!< gpio muxing function selection 13 */
|
||||
GPIO_MUX_14 = 0x0E, /*!< gpio muxing function selection 14 */
|
||||
GPIO_MUX_15 = 0x0F /*!< gpio muxing function selection 15 */
|
||||
} gpio_mux_sel_type;
|
||||
|
||||
/**
|
||||
* @brief type define gpio register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief gpio mode register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cfgr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t iomc0 : 2; /* [1:0] */
|
||||
__IO uint32_t iomc1 : 2; /* [3:2] */
|
||||
__IO uint32_t iomc2 : 2; /* [5:4] */
|
||||
__IO uint32_t iomc3 : 2; /* [7:6] */
|
||||
__IO uint32_t iomc4 : 2; /* [9:8] */
|
||||
__IO uint32_t iomc5 : 2; /* [11:10] */
|
||||
__IO uint32_t iomc6 : 2; /* [13:12] */
|
||||
__IO uint32_t iomc7 : 2; /* [15:14] */
|
||||
__IO uint32_t iomc8 : 2; /* [17:16] */
|
||||
__IO uint32_t iomc9 : 2; /* [19:18] */
|
||||
__IO uint32_t iomc10 : 2; /* [21:20] */
|
||||
__IO uint32_t iomc11 : 2; /* [23:22] */
|
||||
__IO uint32_t iomc12 : 2; /* [25:24] */
|
||||
__IO uint32_t iomc13 : 2; /* [27:26] */
|
||||
__IO uint32_t iomc14 : 2; /* [29:28] */
|
||||
__IO uint32_t iomc15 : 2; /* [31:30] */
|
||||
} cfgr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio output type register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t omode;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t om0 : 1; /* [0] */
|
||||
__IO uint32_t om1 : 1; /* [1] */
|
||||
__IO uint32_t om2 : 1; /* [2] */
|
||||
__IO uint32_t om3 : 1; /* [3] */
|
||||
__IO uint32_t om4 : 1; /* [4] */
|
||||
__IO uint32_t om5 : 1; /* [5] */
|
||||
__IO uint32_t om6 : 1; /* [6] */
|
||||
__IO uint32_t om7 : 1; /* [7] */
|
||||
__IO uint32_t om8 : 1; /* [8] */
|
||||
__IO uint32_t om9 : 1; /* [9] */
|
||||
__IO uint32_t om10 : 1; /* [10] */
|
||||
__IO uint32_t om11 : 1; /* [11] */
|
||||
__IO uint32_t om12 : 1; /* [12] */
|
||||
__IO uint32_t om13 : 1; /* [13] */
|
||||
__IO uint32_t om14 : 1; /* [14] */
|
||||
__IO uint32_t om15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} omode_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio output driver register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t odrvr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t odrv0 : 2; /* [1:0] */
|
||||
__IO uint32_t odrv1 : 2; /* [3:2] */
|
||||
__IO uint32_t odrv2 : 2; /* [5:4] */
|
||||
__IO uint32_t odrv3 : 2; /* [7:6] */
|
||||
__IO uint32_t odrv4 : 2; /* [9:8] */
|
||||
__IO uint32_t odrv5 : 2; /* [11:10] */
|
||||
__IO uint32_t odrv6 : 2; /* [13:12] */
|
||||
__IO uint32_t odrv7 : 2; /* [15:14] */
|
||||
__IO uint32_t odrv8 : 2; /* [17:16] */
|
||||
__IO uint32_t odrv9 : 2; /* [19:18] */
|
||||
__IO uint32_t odrv10 : 2; /* [21:20] */
|
||||
__IO uint32_t odrv11 : 2; /* [23:22] */
|
||||
__IO uint32_t odrv12 : 2; /* [25:24] */
|
||||
__IO uint32_t odrv13 : 2; /* [27:26] */
|
||||
__IO uint32_t odrv14 : 2; /* [29:28] */
|
||||
__IO uint32_t odrv15 : 2; /* [31:30] */
|
||||
} odrvr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio pull up/down register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pull;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pull0 : 2; /* [1:0] */
|
||||
__IO uint32_t pull1 : 2; /* [3:2] */
|
||||
__IO uint32_t pull2 : 2; /* [5:4] */
|
||||
__IO uint32_t pull3 : 2; /* [7:6] */
|
||||
__IO uint32_t pull4 : 2; /* [9:8] */
|
||||
__IO uint32_t pull5 : 2; /* [11:10] */
|
||||
__IO uint32_t pull6 : 2; /* [13:12] */
|
||||
__IO uint32_t pull7 : 2; /* [15:14] */
|
||||
__IO uint32_t pull8 : 2; /* [17:16] */
|
||||
__IO uint32_t pull9 : 2; /* [19:18] */
|
||||
__IO uint32_t pull10 : 2; /* [21:20] */
|
||||
__IO uint32_t pull11 : 2; /* [23:22] */
|
||||
__IO uint32_t pull12 : 2; /* [25:24] */
|
||||
__IO uint32_t pull13 : 2; /* [27:26] */
|
||||
__IO uint32_t pull14 : 2; /* [29:28] */
|
||||
__IO uint32_t pull15 : 2; /* [31:30] */
|
||||
} pull_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio input data register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t idt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t idt0 : 1; /* [0] */
|
||||
__IO uint32_t idt1 : 1; /* [1] */
|
||||
__IO uint32_t idt2 : 1; /* [2] */
|
||||
__IO uint32_t idt3 : 1; /* [3] */
|
||||
__IO uint32_t idt4 : 1; /* [4] */
|
||||
__IO uint32_t idt5 : 1; /* [5] */
|
||||
__IO uint32_t idt6 : 1; /* [6] */
|
||||
__IO uint32_t idt7 : 1; /* [7] */
|
||||
__IO uint32_t idt8 : 1; /* [8] */
|
||||
__IO uint32_t idt9 : 1; /* [9] */
|
||||
__IO uint32_t idt10 : 1; /* [10] */
|
||||
__IO uint32_t idt11 : 1; /* [11] */
|
||||
__IO uint32_t idt12 : 1; /* [12] */
|
||||
__IO uint32_t idt13 : 1; /* [13] */
|
||||
__IO uint32_t idt14 : 1; /* [14] */
|
||||
__IO uint32_t idt15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} idt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio output data register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t odt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t odt0 : 1; /* [0] */
|
||||
__IO uint32_t odt1 : 1; /* [1] */
|
||||
__IO uint32_t odt2 : 1; /* [2] */
|
||||
__IO uint32_t odt3 : 1; /* [3] */
|
||||
__IO uint32_t odt4 : 1; /* [4] */
|
||||
__IO uint32_t odt5 : 1; /* [5] */
|
||||
__IO uint32_t odt6 : 1; /* [6] */
|
||||
__IO uint32_t odt7 : 1; /* [7] */
|
||||
__IO uint32_t odt8 : 1; /* [8] */
|
||||
__IO uint32_t odt9 : 1; /* [9] */
|
||||
__IO uint32_t odt10 : 1; /* [10] */
|
||||
__IO uint32_t odt11 : 1; /* [11] */
|
||||
__IO uint32_t odt12 : 1; /* [12] */
|
||||
__IO uint32_t odt13 : 1; /* [13] */
|
||||
__IO uint32_t odt14 : 1; /* [14] */
|
||||
__IO uint32_t odt15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} odt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio scr register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t scr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t iosb0 : 1; /* [0] */
|
||||
__IO uint32_t iosb1 : 1; /* [1] */
|
||||
__IO uint32_t iosb2 : 1; /* [2] */
|
||||
__IO uint32_t iosb3 : 1; /* [3] */
|
||||
__IO uint32_t iosb4 : 1; /* [4] */
|
||||
__IO uint32_t iosb5 : 1; /* [5] */
|
||||
__IO uint32_t iosb6 : 1; /* [6] */
|
||||
__IO uint32_t iosb7 : 1; /* [7] */
|
||||
__IO uint32_t iosb8 : 1; /* [8] */
|
||||
__IO uint32_t iosb9 : 1; /* [9] */
|
||||
__IO uint32_t iosb10 : 1; /* [10] */
|
||||
__IO uint32_t iosb11 : 1; /* [11] */
|
||||
__IO uint32_t iosb12 : 1; /* [12] */
|
||||
__IO uint32_t iosb13 : 1; /* [13] */
|
||||
__IO uint32_t iosb14 : 1; /* [14] */
|
||||
__IO uint32_t iosb15 : 1; /* [15] */
|
||||
__IO uint32_t iocb0 : 1; /* [16] */
|
||||
__IO uint32_t iocb1 : 1; /* [17] */
|
||||
__IO uint32_t iocb2 : 1; /* [18] */
|
||||
__IO uint32_t iocb3 : 1; /* [19] */
|
||||
__IO uint32_t iocb4 : 1; /* [20] */
|
||||
__IO uint32_t iocb5 : 1; /* [21] */
|
||||
__IO uint32_t iocb6 : 1; /* [22] */
|
||||
__IO uint32_t iocb7 : 1; /* [23] */
|
||||
__IO uint32_t iocb8 : 1; /* [24] */
|
||||
__IO uint32_t iocb9 : 1; /* [25] */
|
||||
__IO uint32_t iocb10 : 1; /* [26] */
|
||||
__IO uint32_t iocb11 : 1; /* [27] */
|
||||
__IO uint32_t iocb12 : 1; /* [28] */
|
||||
__IO uint32_t iocb13 : 1; /* [29] */
|
||||
__IO uint32_t iocb14 : 1; /* [30] */
|
||||
__IO uint32_t iocb15 : 1; /* [31] */
|
||||
} scr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio wpen register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t wpr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t wpen0 : 1; /* [0] */
|
||||
__IO uint32_t wpen1 : 1; /* [1] */
|
||||
__IO uint32_t wpen2 : 1; /* [2] */
|
||||
__IO uint32_t wpen3 : 1; /* [3] */
|
||||
__IO uint32_t wpen4 : 1; /* [4] */
|
||||
__IO uint32_t wpen5 : 1; /* [5] */
|
||||
__IO uint32_t wpen6 : 1; /* [6] */
|
||||
__IO uint32_t wpen7 : 1; /* [7] */
|
||||
__IO uint32_t wpen8 : 1; /* [8] */
|
||||
__IO uint32_t wpen9 : 1; /* [9] */
|
||||
__IO uint32_t wpen10 : 1; /* [10] */
|
||||
__IO uint32_t wpen11 : 1; /* [11] */
|
||||
__IO uint32_t wpen12 : 1; /* [12] */
|
||||
__IO uint32_t wpen13 : 1; /* [13] */
|
||||
__IO uint32_t wpen14 : 1; /* [14] */
|
||||
__IO uint32_t wpen15 : 1; /* [15] */
|
||||
__IO uint32_t wpseq : 1; /* [16] */
|
||||
__IO uint32_t reserved1 : 15;/* [31:17] */
|
||||
} wpr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio muxl register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t muxl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t muxl0 : 4; /* [3:0] */
|
||||
__IO uint32_t muxl1 : 4; /* [7:4] */
|
||||
__IO uint32_t muxl2 : 4; /* [11:8] */
|
||||
__IO uint32_t muxl3 : 4; /* [15:12] */
|
||||
__IO uint32_t muxl4 : 4; /* [19:16] */
|
||||
__IO uint32_t muxl5 : 4; /* [23:20] */
|
||||
__IO uint32_t muxl6 : 4; /* [27:24] */
|
||||
__IO uint32_t muxl7 : 4; /* [31:28] */
|
||||
} muxl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio muxh register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t muxh;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t muxh8 : 4; /* [3:0] */
|
||||
__IO uint32_t muxh9 : 4; /* [7:4] */
|
||||
__IO uint32_t muxh10 : 4; /* [11:8] */
|
||||
__IO uint32_t muxh11 : 4; /* [15:12] */
|
||||
__IO uint32_t muxh12 : 4; /* [19:16] */
|
||||
__IO uint32_t muxh13 : 4; /* [23:20] */
|
||||
__IO uint32_t muxh14 : 4; /* [27:24] */
|
||||
__IO uint32_t muxh15 : 4; /* [31:28] */
|
||||
} muxh_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio clr register, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t clr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t iocb0 : 1; /* [0] */
|
||||
__IO uint32_t iocb1 : 1; /* [1] */
|
||||
__IO uint32_t iocb2 : 1; /* [2] */
|
||||
__IO uint32_t iocb3 : 1; /* [3] */
|
||||
__IO uint32_t iocb4 : 1; /* [4] */
|
||||
__IO uint32_t iocb5 : 1; /* [5] */
|
||||
__IO uint32_t iocb6 : 1; /* [6] */
|
||||
__IO uint32_t iocb7 : 1; /* [7] */
|
||||
__IO uint32_t iocb8 : 1; /* [8] */
|
||||
__IO uint32_t iocb9 : 1; /* [9] */
|
||||
__IO uint32_t iocb10 : 1; /* [10] */
|
||||
__IO uint32_t iocb11 : 1; /* [11] */
|
||||
__IO uint32_t iocb12 : 1; /* [12] */
|
||||
__IO uint32_t iocb13 : 1; /* [13] */
|
||||
__IO uint32_t iocb14 : 1; /* [14] */
|
||||
__IO uint32_t iocb15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} clr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio reserved1 register, offset:0x2C~0x38
|
||||
*/
|
||||
__IO uint32_t reserved1[4];
|
||||
|
||||
/**
|
||||
* @brief gpio hdrv register, offset:0x3C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t hdrv;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t hdrv0 : 1; /* [0] */
|
||||
__IO uint32_t hdrv1 : 1; /* [1] */
|
||||
__IO uint32_t hdrv2 : 1; /* [2] */
|
||||
__IO uint32_t hdrv3 : 1; /* [3] */
|
||||
__IO uint32_t hdrv4 : 1; /* [4] */
|
||||
__IO uint32_t hdrv5 : 1; /* [5] */
|
||||
__IO uint32_t hdrv6 : 1; /* [6] */
|
||||
__IO uint32_t hdrv7 : 1; /* [7] */
|
||||
__IO uint32_t hdrv8 : 1; /* [8] */
|
||||
__IO uint32_t hdrv9 : 1; /* [9] */
|
||||
__IO uint32_t hdrv10 : 1; /* [10] */
|
||||
__IO uint32_t hdrv11 : 1; /* [11] */
|
||||
__IO uint32_t hdrv12 : 1; /* [12] */
|
||||
__IO uint32_t hdrv13 : 1; /* [13] */
|
||||
__IO uint32_t hdrv14 : 1; /* [14] */
|
||||
__IO uint32_t hdrv15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} hdrv_bit;
|
||||
};
|
||||
|
||||
} gpio_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define GPIOA ((gpio_type *) GPIOA_BASE)
|
||||
#define GPIOB ((gpio_type *) GPIOB_BASE)
|
||||
#define GPIOC ((gpio_type *) GPIOC_BASE)
|
||||
#define GPIOD ((gpio_type *) GPIOD_BASE)
|
||||
#define GPIOE ((gpio_type *) GPIOE_BASE)
|
||||
#define GPIOF ((gpio_type *) GPIOF_BASE)
|
||||
#define GPIOG ((gpio_type *) GPIOG_BASE)
|
||||
#define GPIOH ((gpio_type *) GPIOH_BASE)
|
||||
|
||||
/** @defgroup GPIO_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void gpio_reset(gpio_type *gpio_x);
|
||||
void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct);
|
||||
void gpio_default_para_init(gpio_init_type *gpio_init_struct);
|
||||
flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins);
|
||||
uint16_t gpio_input_data_read(gpio_type *gpio_x);
|
||||
flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins);
|
||||
uint16_t gpio_output_data_read(gpio_type *gpio_x);
|
||||
void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
|
||||
void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
|
||||
void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
|
||||
void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value);
|
||||
void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
|
||||
void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state);
|
||||
void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,479 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_i2c.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 i2c header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_I2C_H
|
||||
#define __AT32F435_437_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief maximum number of single transfers
|
||||
*/
|
||||
#define MAX_TRANSFER_CNT 255 /*!< maximum number of single transfers */
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @brief i2c interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_TD_INT ((uint32_t)0x00000002) /*!< i2c transmit data interrupt */
|
||||
#define I2C_RD_INT ((uint32_t)0x00000004) /*!< i2c receive data interrupt */
|
||||
#define I2C_ADDR_INT ((uint32_t)0x00000008) /*!< i2c address match interrupt */
|
||||
#define I2C_ACKFIAL_INT ((uint32_t)0x00000010) /*!< i2c ack fail interrupt */
|
||||
#define I2C_STOP_INT ((uint32_t)0x00000020) /*!< i2c stop detect interrupt */
|
||||
#define I2C_TDC_INT ((uint32_t)0x00000040) /*!< i2c transmit data complete interrupt */
|
||||
#define I2C_ERR_INT ((uint32_t)0x00000080) /*!< i2c bus error interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_flags_definition
|
||||
* @brief i2c flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_TDBE_FLAG ((uint32_t)0x00000001) /*!< i2c transmit data buffer empty flag */
|
||||
#define I2C_TDIS_FLAG ((uint32_t)0x00000002) /*!< i2c send interrupt status */
|
||||
#define I2C_RDBF_FLAG ((uint32_t)0x00000004) /*!< i2c receive data buffer full flag */
|
||||
#define I2C_ADDRF_FLAG ((uint32_t)0x00000008) /*!< i2c 0~7 bit address match flag */
|
||||
#define I2C_ACKFAIL_FLAG ((uint32_t)0x00000010) /*!< i2c acknowledge failure flag */
|
||||
#define I2C_STOPF_FLAG ((uint32_t)0x00000020) /*!< i2c stop condition generation complete flag */
|
||||
#define I2C_TDC_FLAG ((uint32_t)0x00000040) /*!< i2c transmit data complete flag */
|
||||
#define I2C_TCRLD_FLAG ((uint32_t)0x00000080) /*!< i2c transmission is complete, waiting to load data */
|
||||
#define I2C_BUSERR_FLAG ((uint32_t)0x00000100) /*!< i2c bus error flag */
|
||||
#define I2C_ARLOST_FLAG ((uint32_t)0x00000200) /*!< i2c arbitration lost flag */
|
||||
#define I2C_OUF_FLAG ((uint32_t)0x00000400) /*!< i2c overflow or underflow flag */
|
||||
#define I2C_PECERR_FLAG ((uint32_t)0x00000800) /*!< i2c pec receive error flag */
|
||||
#define I2C_TMOUT_FLAG ((uint32_t)0x00001000) /*!< i2c smbus timeout flag */
|
||||
#define I2C_ALERTF_FLAG ((uint32_t)0x00002000) /*!< i2c smbus alert flag */
|
||||
#define I2C_BUSYF_FLAG ((uint32_t)0x00008000) /*!< i2c bus busy flag transmission mode */
|
||||
#define I2C_SDIR_FLAG ((uint32_t)0x00010000) /*!< i2c slave data transmit direction */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief i2c smbus mode set
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_SMBUS_MODE_DEVICE = 0x00, /*!< smbus device mode */
|
||||
I2C_SMBUS_MODE_HOST = 0x01 /*!< smbus host mode */
|
||||
} i2c_smbus_mode_type;
|
||||
|
||||
/**
|
||||
* @brief i2c address mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_ADDRESS_MODE_7BIT = 0x00, /*!< 7bit address mode */
|
||||
I2C_ADDRESS_MODE_10BIT = 0x01 /*!< 10bit address mode */
|
||||
} i2c_address_mode_type;
|
||||
|
||||
/**
|
||||
* @brief i2c transfer direction
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_DIR_TRANSMIT = 0x00, /*!< master request a write transfer */
|
||||
I2C_DIR_RECEIVE = 0x01 /*!< master request a read transfer */
|
||||
} i2c_transfer_dir_type;
|
||||
|
||||
/**
|
||||
* @brief i2c dma requests direction
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_DMA_REQUEST_TX = 0x00, /*!< dma transmit request */
|
||||
I2C_DMA_REQUEST_RX = 0x01 /*!< dma receive request */
|
||||
} i2c_dma_request_type;
|
||||
|
||||
/**
|
||||
* @brief i2c smbus alert pin set
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_SMBUS_ALERT_HIGH = 0x00, /*!< smbus alert pin set high */
|
||||
I2C_SMBUS_ALERT_LOW = 0x01 /*!< smbus alert pin set low */
|
||||
} i2c_smbus_alert_set_type;
|
||||
|
||||
/**
|
||||
* @brief i2c clock timeout detection mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_TIMEOUT_DETCET_LOW = 0x00, /*!< detect low level timeout */
|
||||
I2C_TIMEOUT_DETCET_HIGH = 0x01 /*!< detect high level timeout */
|
||||
} i2c_timeout_detcet_type;
|
||||
|
||||
/**
|
||||
* @brief i2c own address2 mask
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_ADDR2_NOMASK = 0x00, /*!< compare bit [7:1] */
|
||||
I2C_ADDR2_MASK01 = 0x01, /*!< only compare bit [7:2] */
|
||||
I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:2] */
|
||||
I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:3] */
|
||||
I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:4] */
|
||||
I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:5] */
|
||||
I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7:6] */
|
||||
I2C_ADDR2_MASK07 = 0x07 /*!< only compare bit [7] */
|
||||
} i2c_addr2_mask_type;
|
||||
|
||||
/**
|
||||
* @brief i2c reload end mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_AUTO_STOP_MODE = 0x00, /*!< auto generate stop mode */
|
||||
I2C_SOFT_STOP_MODE = 0x01, /*!< soft generate stop mode */
|
||||
I2C_RELOAD_MODE = 0x02 /*!< reload mode */
|
||||
} i2c_reload_stop_mode_type;
|
||||
|
||||
/**
|
||||
* @brief i2c start stop mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_WITHOUT_START = 0x00, /*!< transfer data without start condition */
|
||||
I2C_GEN_START_READ = 0x01, /*!< read data and generate start */
|
||||
I2C_GEN_START_WRITE = 0x02 /*!< send data and generate start */
|
||||
} i2c_start_stop_mode_type;
|
||||
|
||||
/**
|
||||
* @brief type define i2c register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief i2c ctrl1 register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t i2cen : 1; /* [0] */
|
||||
__IO uint32_t tdien : 1; /* [1] */
|
||||
__IO uint32_t rdien : 1; /* [2] */
|
||||
__IO uint32_t addrien : 1; /* [3] */
|
||||
__IO uint32_t ackfailien : 1; /* [4] */
|
||||
__IO uint32_t stopien : 1; /* [5] */
|
||||
__IO uint32_t tdcien : 1; /* [6] */
|
||||
__IO uint32_t errien : 1; /* [7] */
|
||||
__IO uint32_t dflt : 4; /* [11:8] */
|
||||
__IO uint32_t reserved1 : 2; /* [13:12] */
|
||||
__IO uint32_t dmaten : 1; /* [14] */
|
||||
__IO uint32_t dmaren : 1; /* [15] */
|
||||
__IO uint32_t sctrl : 1; /* [16] */
|
||||
__IO uint32_t stretch : 1; /* [17] */
|
||||
__IO uint32_t reserved2 : 1; /* [18] */
|
||||
__IO uint32_t gcaen : 1; /* [19] */
|
||||
__IO uint32_t haddren : 1; /* [20] */
|
||||
__IO uint32_t devaddren : 1; /* [21] */
|
||||
__IO uint32_t smbalert : 1; /* [22] */
|
||||
__IO uint32_t pecen : 1; /* [23] */
|
||||
__IO uint32_t reserved3 : 8; /* [31:24] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c ctrl2 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t saddr : 10;/* [9:0] */
|
||||
__IO uint32_t dir : 1; /* [10] */
|
||||
__IO uint32_t addr10 : 1; /* [11] */
|
||||
__IO uint32_t readh10 : 1; /* [12] */
|
||||
__IO uint32_t genstart : 1; /* [13] */
|
||||
__IO uint32_t genstop : 1; /* [14] */
|
||||
__IO uint32_t nacken : 1; /* [15] */
|
||||
__IO uint32_t cnt : 8; /* [23:16] */
|
||||
__IO uint32_t rlden : 1; /* [24] */
|
||||
__IO uint32_t astopen : 1; /* [25] */
|
||||
__IO uint32_t pecten : 1; /* [26] */
|
||||
__IO uint32_t reserved1 : 5; /* [31:27] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c oaddr1 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t oaddr1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t addr1 : 10;/* [9:0] */
|
||||
__IO uint32_t addr1mode : 1; /* [10] */
|
||||
__IO uint32_t reserved1 : 4; /* [14:11] */
|
||||
__IO uint32_t addr1en : 1; /* [15] */
|
||||
__IO uint32_t reserved2 : 16;/* [31:16] */
|
||||
} oaddr1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c oaddr2 register, offset:0x0c
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t oaddr2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 1; /* [0] */
|
||||
__IO uint32_t addr2 : 7; /* [7:1] */
|
||||
__IO uint32_t addr2mask : 3; /* [10:8] */
|
||||
__IO uint32_t reserved2 : 4; /* [14:11] */
|
||||
__IO uint32_t addr2en : 1; /* [15] */
|
||||
__IO uint32_t reserved3 : 16;/* [31:16] */
|
||||
} oaddr2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c clkctrl register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t clkctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t scll : 8; /* [7:0] */
|
||||
__IO uint32_t sclh : 8; /* [15:8] */
|
||||
__IO uint32_t sdad : 4; /* [19:16] */
|
||||
__IO uint32_t scld : 4; /* [23:20] */
|
||||
__IO uint32_t divh : 4; /* [27:24] */
|
||||
__IO uint32_t divl : 4; /* [31:28] */
|
||||
} clkctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c timeout register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t timeout;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t totime : 12;/* [11:0] */
|
||||
__IO uint32_t tomode : 1; /* [12] */
|
||||
__IO uint32_t reserved1 : 2; /* [14:13] */
|
||||
__IO uint32_t toen : 1; /* [15] */
|
||||
__IO uint32_t exttime : 12;/* [27:16] */
|
||||
__IO uint32_t reserved2 : 3; /* [30:28] */
|
||||
__IO uint32_t exten : 1; /* [31] */
|
||||
} timeout_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c sts register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tdbe : 1; /* [0] */
|
||||
__IO uint32_t tdis : 1; /* [1] */
|
||||
__IO uint32_t rdbf : 1; /* [2] */
|
||||
__IO uint32_t addrf : 1; /* [3] */
|
||||
__IO uint32_t ackfail : 1; /* [4] */
|
||||
__IO uint32_t stopf : 1; /* [5] */
|
||||
__IO uint32_t tdc : 1; /* [6] */
|
||||
__IO uint32_t tcrld : 1; /* [7] */
|
||||
__IO uint32_t buserr : 1; /* [8] */
|
||||
__IO uint32_t arlost : 1; /* [9] */
|
||||
__IO uint32_t ouf : 1; /* [10] */
|
||||
__IO uint32_t pecerr : 1; /* [11] */
|
||||
__IO uint32_t tmout : 1; /* [12] */
|
||||
__IO uint32_t alertf : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 1; /* [14] */
|
||||
__IO uint32_t busyf : 1; /* [15] */
|
||||
__IO uint32_t sdir : 1; /* [16] */
|
||||
__IO uint32_t addr : 7; /* [23:17] */
|
||||
__IO uint32_t reserved2 : 8; /* [31:24] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c clr register, offset:0x1c
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t clr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 3; /* [2:0] */
|
||||
__IO uint32_t addrc : 1; /* [3] */
|
||||
__IO uint32_t ackfailc : 1; /* [4] */
|
||||
__IO uint32_t stopc : 1; /* [5] */
|
||||
__IO uint32_t reserved2 : 2; /* [6:7] */
|
||||
__IO uint32_t buserrc : 1; /* [8] */
|
||||
__IO uint32_t arlostc : 1; /* [9] */
|
||||
__IO uint32_t oufc : 1; /* [10] */
|
||||
__IO uint32_t pecerrc : 1; /* [11] */
|
||||
__IO uint32_t tmoutc : 1; /* [12] */
|
||||
__IO uint32_t alertc : 1; /* [13] */
|
||||
__IO uint32_t reserved3 : 18;/* [31:14] */
|
||||
} clr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c pec register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pec;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pecval : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} pec_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c rxdt register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rxdt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} rxdt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c txdt register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t txdt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} txdt_bit;
|
||||
};
|
||||
|
||||
} i2c_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define I2C1 ((i2c_type *) I2C1_BASE)
|
||||
#define I2C2 ((i2c_type *) I2C2_BASE)
|
||||
#define I2C3 ((i2c_type *) I2C3_BASE)
|
||||
|
||||
/** @defgroup I2C_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void i2c_reset(i2c_type *i2c_x);
|
||||
void i2c_init(i2c_type *i2c_x, uint8_t dfilters, uint32_t clk);
|
||||
void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address);
|
||||
void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask);
|
||||
void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_smbus_enable(i2c_type *i2c_x, i2c_smbus_mode_type mode, confirm_state new_state);
|
||||
void i2c_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_addr10_mode_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_transfer_addr_set(i2c_type *i2c_x, uint16_t address);
|
||||
uint16_t i2c_transfer_addr_get(i2c_type *i2c_x);
|
||||
void i2c_transfer_dir_set(i2c_type *i2c_x, i2c_transfer_dir_type i2c_direction);
|
||||
i2c_transfer_dir_type i2c_transfer_dir_get(i2c_type *i2c_x);
|
||||
uint8_t i2c_matched_addr_get(i2c_type *i2c_x);
|
||||
void i2c_auto_stop_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_reload_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_cnt_set(i2c_type *i2c_x, uint8_t cnt);
|
||||
void i2c_addr10_header_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level);
|
||||
void i2c_slave_data_ctrl_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
uint8_t i2c_pec_value_get(i2c_type *i2c_x);
|
||||
void i2c_timeout_set(i2c_type *i2c_x, uint16_t timeout);
|
||||
void i2c_timeout_detcet_set(i2c_type *i2c_x, i2c_timeout_detcet_type mode);
|
||||
void i2c_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_ext_timeout_set(i2c_type *i2c_x, uint16_t timeout);
|
||||
void i2c_ext_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_interrupt_enable(i2c_type *i2c_x, uint32_t source, confirm_state new_state);
|
||||
flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source);
|
||||
void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state new_state);
|
||||
void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_stop_mode_type start_stop);
|
||||
void i2c_start_generate(i2c_type *i2c_x);
|
||||
void i2c_stop_generate(i2c_type *i2c_x);
|
||||
void i2c_data_send(i2c_type *i2c_x, uint8_t data);
|
||||
uint8_t i2c_data_receive(i2c_type *i2c_x);
|
||||
flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
|
||||
void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,125 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_misc.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 misc header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_MISC_H
|
||||
#define __AT32F435_437_MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_vector_table_base_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< nvic vector table based ram address */
|
||||
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< nvic vector table based flash address */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief nvic interrupt priority group
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
|
||||
NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
|
||||
NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
|
||||
NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
|
||||
NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3) /*!< 4 bits for preemption priority, 0 bits for subpriority */
|
||||
} nvic_priority_group_type;
|
||||
|
||||
/**
|
||||
* @brief nvic low power mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NVIC_LP_SLEEPONEXIT = 0x02, /*!< send event on pending */
|
||||
NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */
|
||||
NVIC_LP_SEVONPEND = 0x10 /*!< enable sleep-on-exit feature */
|
||||
} nvic_lowpower_mode_type;
|
||||
|
||||
/**
|
||||
* @brief systick clock source
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8 = ((uint32_t)0x00000000), /*!< systick clock source from core clock div8 */
|
||||
SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV = ((uint32_t)0x00000004) /*!< systick clock source from core clock */
|
||||
} systick_clock_source_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void nvic_system_reset(void);
|
||||
void nvic_irq_enable(uint32_t irqn, uint32_t preempt_priority, uint32_t sub_priority);
|
||||
void nvic_irq_disable(uint32_t irqn);
|
||||
void nvic_priority_group_config(nvic_priority_group_type priority_group);
|
||||
void nvic_vector_table_set(uint32_t base, uint32_t offset);
|
||||
void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state);
|
||||
void systick_clock_source_config(systick_clock_source_type source);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,230 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_pwc.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 pwr header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_PWC_H
|
||||
#define __AT32F435_437_PWC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWC_flags_definition
|
||||
* @brief pwc flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWC_WAKEUP_FLAG ((uint32_t)0x00000001) /*!< wakeup flag */
|
||||
#define PWC_STANDBY_FLAG ((uint32_t)0x00000002) /*!< standby flag */
|
||||
#define PWC_PVM_OUTPUT_FLAG ((uint32_t)0x00000004) /*!< pvm output flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief pwc wakeup pin num definition
|
||||
*/
|
||||
#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1 */
|
||||
#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00000200) /*!< standby wake-up pin2 */
|
||||
|
||||
/**
|
||||
* @brief select ldo output voltage.
|
||||
* @param val: set the ldo output voltage.
|
||||
* this parameter can be one of the following values:
|
||||
* - PWC_LDO_OUTPUT_1V2
|
||||
* - PWC_LDO_OUTPUT_1V3
|
||||
* - PWC_LDO_OUTPUT_1V1
|
||||
* - PWC_LDO_OUTPUT_1V0
|
||||
*/
|
||||
#define pwc_ldo_output_voltage_set(val) (PWC->ldoov_bit.ldoovsel = val)
|
||||
|
||||
/** @defgroup PWC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief pwc pvm voltage type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_PVM_VOLTAGE_2V3 = 0x01, /*!< power voltage monitoring boundary 2.3v */
|
||||
PWC_PVM_VOLTAGE_2V4 = 0x02, /*!< power voltage monitoring boundary 2.4v */
|
||||
PWC_PVM_VOLTAGE_2V5 = 0x03, /*!< power voltage monitoring boundary 2.5v */
|
||||
PWC_PVM_VOLTAGE_2V6 = 0x04, /*!< power voltage monitoring boundary 2.6v */
|
||||
PWC_PVM_VOLTAGE_2V7 = 0x05, /*!< power voltage monitoring boundary 2.7v */
|
||||
PWC_PVM_VOLTAGE_2V8 = 0x06, /*!< power voltage monitoring boundary 2.8v */
|
||||
PWC_PVM_VOLTAGE_2V9 = 0x07 /*!< power voltage monitoring boundary 2.9v */
|
||||
} pwc_pvm_voltage_type;
|
||||
|
||||
/**
|
||||
* @brief pwc ldo output voltage type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_LDO_OUTPUT_1V2 = 0x00, /*!< ldo output voltage is 1.2v */
|
||||
PWC_LDO_OUTPUT_1V3 = 0x01, /*!< ldo output voltage is 1.3v */
|
||||
PWC_LDO_OUTPUT_1V1 = 0x04, /*!< ldo output voltage is 1.1v */
|
||||
PWC_LDO_OUTPUT_1V0 = 0x05, /*!< ldo output voltage is 1.0v */
|
||||
} pwc_ldo_output_voltage_type;
|
||||
|
||||
/**
|
||||
* @brief pwc sleep enter type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter sleep mode */
|
||||
PWC_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter sleep mode */
|
||||
} pwc_sleep_enter_type ;
|
||||
|
||||
/**
|
||||
* @brief pwc deep sleep enter type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_DEEP_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter deepsleep mode */
|
||||
PWC_DEEP_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter deepsleep mode */
|
||||
} pwc_deep_sleep_enter_type ;
|
||||
|
||||
/**
|
||||
* @brief pwc regulator type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_REGULATOR_ON = 0x00, /*!< voltage regulator state on when deepsleep mode */
|
||||
PWC_REGULATOR_LOW_POWER = 0x01 /*!< voltage regulator state low power when deepsleep mode */
|
||||
} pwc_regulator_type ;
|
||||
|
||||
/**
|
||||
* @brief type define pwc register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief pwc ctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vrsel : 1; /* [0] */
|
||||
__IO uint32_t lpsel : 1; /* [1] */
|
||||
__IO uint32_t clswef : 1; /* [2] */
|
||||
__IO uint32_t clsef : 1; /* [3] */
|
||||
__IO uint32_t pvmen : 1; /* [4] */
|
||||
__IO uint32_t pvmsel : 3; /* [7:5] */
|
||||
__IO uint32_t bpwen : 1; /* [8] */
|
||||
__IO uint32_t reserved1 : 23;/* [31:9] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief pwc ctrlsts register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrlsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t swef : 1; /* [0] */
|
||||
__IO uint32_t sef : 1; /* [1] */
|
||||
__IO uint32_t pvmof : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 5; /* [7:3] */
|
||||
__IO uint32_t swpen1 : 1; /* [8] */
|
||||
__IO uint32_t swpen2 : 1; /* [9] */
|
||||
__IO uint32_t reserved2 : 22;/* [31:10] */
|
||||
} ctrlsts_bit;
|
||||
};
|
||||
|
||||
__IO uint32_t reserved1[2];
|
||||
|
||||
/**
|
||||
* @brief pwc ldoov register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ldoov;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ldoovsel : 3; /* [2:0] */
|
||||
__IO uint32_t reserved1 : 29;/* [31:3] */
|
||||
} ldoov_bit;
|
||||
};
|
||||
|
||||
} pwc_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define PWC ((pwc_type *) PWC_BASE)
|
||||
|
||||
/** @defgroup PWC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void pwc_reset(void);
|
||||
void pwc_battery_powered_domain_access(confirm_state new_state);
|
||||
void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage);
|
||||
void pwc_power_voltage_monitor_enable(confirm_state new_state);
|
||||
void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state);
|
||||
void pwc_flag_clear(uint32_t pwc_flag);
|
||||
flag_status pwc_flag_get(uint32_t pwc_flag);
|
||||
void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter);
|
||||
void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter);
|
||||
void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator);
|
||||
void pwc_standby_mode_enter(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,555 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_qspi.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 qspi header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_QSPI_H
|
||||
#define __AT32F435_437_QSPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_flags_definition
|
||||
* @brief qspi flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define QSPI_CMDSTS_FLAG ((uint32_t)0x00000001) /*!< qspi command complete status flag */
|
||||
#define QSPI_RXFIFORDY_FLAG ((uint32_t)0x00000002) /*!< qspi rxfifo ready status flag */
|
||||
#define QSPI_TXFIFORDY_FLAG ((uint32_t)0x00000004) /*!< qspi txfifo ready status flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief qspi xip read access mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_XIPR_SEL_MODED = 0x00, /*!< qspi xip read select mode d */
|
||||
QSPI_XIPR_SEL_MODET = 0x01 /*!< qspi xip read select mode t */
|
||||
} qspi_xip_read_sel_type;
|
||||
|
||||
/**
|
||||
* @brief qspi xip write access mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_XIPW_SEL_MODED = 0x00, /*!< qspi xip write select mode d */
|
||||
QSPI_XIPW_SEL_MODET = 0x01 /*!< qspi xip write select mode t */
|
||||
} qspi_xip_write_sel_type;
|
||||
|
||||
/**
|
||||
* @brief qspi busy bit offset position in status register type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_BUSY_OFFSET_0 = 0x00, /*!< qspi busy bit offset position 0 */
|
||||
QSPI_BUSY_OFFSET_1 = 0x01, /*!< qspi busy bit offset position 1 */
|
||||
QSPI_BUSY_OFFSET_2 = 0x02, /*!< qspi busy bit offset position 2 */
|
||||
QSPI_BUSY_OFFSET_3 = 0x03, /*!< qspi busy bit offset position 3 */
|
||||
QSPI_BUSY_OFFSET_4 = 0x04, /*!< qspi busy bit offset position 4 */
|
||||
QSPI_BUSY_OFFSET_5 = 0x05, /*!< qspi busy bit offset position 5 */
|
||||
QSPI_BUSY_OFFSET_6 = 0x06, /*!< qspi busy bit offset position 6 */
|
||||
QSPI_BUSY_OFFSET_7 = 0x07 /*!< qspi busy bit offset position 7 */
|
||||
} qspi_busy_pos_type;
|
||||
|
||||
/**
|
||||
* @brief qspi read status configure type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_RSTSC_HW_AUTO = 0x00, /*!< qspi read status by hardware */
|
||||
QSPI_RSTSC_SW_ONCE = 0x01 /*!< qspi read status by software */
|
||||
} qspi_read_status_conf_type;
|
||||
|
||||
/**
|
||||
* @brief qspi operate mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_OPERATE_MODE_111 = 0x00, /*!< qspi serial mode */
|
||||
QSPI_OPERATE_MODE_112 = 0x01, /*!< qspi dual mode */
|
||||
QSPI_OPERATE_MODE_114 = 0x02, /*!< qspi quad mode */
|
||||
QSPI_OPERATE_MODE_122 = 0x03, /*!< qspi dual i/o mode */
|
||||
QSPI_OPERATE_MODE_144 = 0x04, /*!< qspi quad i/o mode */
|
||||
QSPI_OPERATE_MODE_222 = 0x05, /*!< qspi instruction 2-bit mode */
|
||||
QSPI_OPERATE_MODE_444 = 0x06 /*!< qspi instruction 4-bit mode(qpi) */
|
||||
} qspi_operate_mode_type;
|
||||
|
||||
/**
|
||||
* @brief qspi clock division type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_CLK_DIV_2 = 0x00, /*!< qspi clk divide by 2 */
|
||||
QSPI_CLK_DIV_4 = 0x01, /*!< qspi clk divide by 4 */
|
||||
QSPI_CLK_DIV_6 = 0x02, /*!< qspi clk divide by 6 */
|
||||
QSPI_CLK_DIV_8 = 0x03, /*!< qspi clk divide by 8 */
|
||||
QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */
|
||||
QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */
|
||||
QSPI_CLK_DIV_10 = 0x06, /*!< qspi clk divide by 10 */
|
||||
QSPI_CLK_DIV_12 = 0x07 /*!< qspi clk divide by 12 */
|
||||
} qspi_clk_div_type;
|
||||
|
||||
/**
|
||||
* @brief qspi command port address length type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_CMD_ADRLEN_0_BYTE = 0x00, /*!< qspi no address */
|
||||
QSPI_CMD_ADRLEN_1_BYTE = 0x01, /*!< qspi address length 1 byte */
|
||||
QSPI_CMD_ADRLEN_2_BYTE = 0x02, /*!< qspi address length 2 byte */
|
||||
QSPI_CMD_ADRLEN_3_BYTE = 0x03, /*!< qspi address length 3 byte */
|
||||
QSPI_CMD_ADRLEN_4_BYTE = 0x04 /*!< qspi address length 4 byte */
|
||||
} qspi_cmd_adrlen_type;
|
||||
|
||||
/**
|
||||
* @brief qspi command port instruction length type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_CMD_INSLEN_0_BYTE = 0x00, /*!< qspi no instruction code */
|
||||
QSPI_CMD_INSLEN_1_BYTE = 0x01, /*!< qspi instruction code 1 byte */
|
||||
QSPI_CMD_INSLEN_2_BYTE = 0x02 /*!< qspi instruction code 2 byte(repeat) */
|
||||
} qspi_cmd_inslen_type;
|
||||
|
||||
/**
|
||||
* @brief qspi xip r/w address length type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_XIP_ADDRLEN_3_BYTE = 0x00, /*!< qspi xip address length 3 byte */
|
||||
QSPI_XIP_ADDRLEN_4_BYTE = 0x01 /*!< qspi xip address length 4 byte */
|
||||
} qspi_xip_addrlen_type;
|
||||
|
||||
/**
|
||||
* @brief qspi sckout mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_SCK_MODE_0 = 0x00, /*!< qspi sck mode 0 */
|
||||
QSPI_SCK_MODE_3 = 0x01 /*!< qspi sck mode 3 */
|
||||
} qspi_clk_mode_type;
|
||||
|
||||
/**
|
||||
* @brief qspi dma tx/rx fifo threshold type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
QSPI_DMA_FIFO_THOD_WORD08 = 0x00, /*!< qspi dma fifo threshold 8 words */
|
||||
QSPI_DMA_FIFO_THOD_WORD16 = 0x01, /*!< qspi dma fifo threshold 16 words */
|
||||
QSPI_DMA_FIFO_THOD_WORD32 = 0x02 /*!< qspi dma fifo threshold 32 words */
|
||||
} qspi_dma_fifo_thod_type;
|
||||
|
||||
/**
|
||||
* @brief qspi cmd type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
confirm_state pe_mode_enable; /*!< perfornance enhance mode enable */
|
||||
uint8_t pe_mode_operate_code; /*!< performance enhance mode operate code */
|
||||
uint8_t instruction_code; /*!< instruction code */
|
||||
qspi_cmd_inslen_type instruction_length; /*!< instruction code length */
|
||||
uint32_t address_code; /*!< address code */
|
||||
qspi_cmd_adrlen_type address_length; /*!< address legnth */
|
||||
uint32_t data_counter; /*!< read/write data counter */
|
||||
uint8_t second_dummy_cycle_num; /*!< number of second dummy state cycle 0~32 */
|
||||
qspi_operate_mode_type operation_mode; /*!< operation mode */
|
||||
qspi_read_status_conf_type read_status_config; /*!< config to read status */
|
||||
confirm_state read_status_enable; /*!< config to read status */
|
||||
confirm_state write_data_enable; /*!< enable to write data */
|
||||
} qspi_cmd_type;
|
||||
|
||||
/**
|
||||
* @brief qspi xip type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t read_instruction_code; /*!< read instruction code */
|
||||
qspi_xip_addrlen_type read_address_length; /*!< read address legnth */
|
||||
qspi_operate_mode_type read_operation_mode; /*!< read operation mode */
|
||||
uint8_t read_second_dummy_cycle_num; /*!< read number of second dummy state cycle 0~32 */
|
||||
uint8_t write_instruction_code; /*!< write instruction code */
|
||||
qspi_xip_addrlen_type write_address_length; /*!< write address legnth */
|
||||
qspi_operate_mode_type write_operation_mode; /*!< write operation mode */
|
||||
uint8_t write_second_dummy_cycle_num; /*!< write number of second dummy state cycle 0~32 */
|
||||
qspi_xip_write_sel_type write_select_mode; /*!< write mode d or mode t selection */
|
||||
uint8_t write_time_counter; /*!< write count for mode t */
|
||||
uint8_t write_data_counter; /*!< write count for mode d */
|
||||
qspi_xip_read_sel_type read_select_mode; /*!< read mode d or mode t selection */
|
||||
uint8_t read_time_counter; /*!< read count for mode t */
|
||||
uint8_t read_data_counter; /*!< read count for mode d */
|
||||
} qspi_xip_type;
|
||||
|
||||
/**
|
||||
* @brief type define qspi register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief qspi cmd_w0 register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cmd_w0;
|
||||
struct
|
||||
{
|
||||
|
||||
__IO uint32_t spiadr : 32;/* [31:0] */
|
||||
} cmd_w0_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi cmd_w1 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cmd_w1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t adrlen : 3; /* [2:0] */
|
||||
__IO uint32_t reserved1 : 13;/* [15:3] */
|
||||
__IO uint32_t dum2 : 8; /* [23:16] */
|
||||
__IO uint32_t inslen : 2; /* [25:24] */
|
||||
__IO uint32_t reserved2 : 2; /* [27:26] */
|
||||
__IO uint32_t pemen : 1; /* [28] */
|
||||
__IO uint32_t reserved3 : 3; /* [31:29] */
|
||||
} cmd_w1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi cmd_w2 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cmd_w2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dcnt : 32;/* [31:0] */
|
||||
} cmd_w2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi cmd_w3 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cmd_w3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 1; /* [0] */
|
||||
__IO uint32_t wen : 1; /* [1] */
|
||||
__IO uint32_t rstsen : 1; /* [2] */
|
||||
__IO uint32_t rstsc : 1; /* [3] */
|
||||
__IO uint32_t reserved2 : 1; /* [4] */
|
||||
__IO uint32_t opmode : 3; /* [7:5] */
|
||||
__IO uint32_t reserved3 : 8; /* [15:8] */
|
||||
__IO uint32_t pemopc : 8; /* [23:16] */
|
||||
__IO uint32_t insc : 8; /* [31:24] */
|
||||
} cmd_w3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi ctrl register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t clkdiv : 3; /* [2:0] */
|
||||
__IO uint32_t reserved1 : 1; /* [3] */
|
||||
__IO uint32_t sckmode : 1; /* [4] */
|
||||
__IO uint32_t reserved2 : 2; /* [6:5] */
|
||||
__IO uint32_t xipidle : 1; /* [7] */
|
||||
__IO uint32_t abort : 1; /* [8] */
|
||||
__IO uint32_t reserved3 : 7; /* [15:9] */
|
||||
__IO uint32_t busy : 3; /* [18:16] */
|
||||
__IO uint32_t xiprcmdf : 1; /* [19] */
|
||||
__IO uint32_t xipsel : 1; /* [20] */
|
||||
__IO uint32_t keyen : 1; /* [21] */
|
||||
__IO uint32_t reserved4 : 10;/* [31:22] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi actr register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t actr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t csdly : 4; /* [3:0] */
|
||||
__IO uint32_t reserved1 : 28;/* [31:4] */
|
||||
} actr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi fifosts register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t fifosts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t txfifordy : 1; /* [0] */
|
||||
__IO uint32_t rxfifordy : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 30;/* [31:2] */
|
||||
} fifosts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi reserved register, offset:0x1C
|
||||
*/
|
||||
__IO uint32_t reserved1;
|
||||
|
||||
/**
|
||||
* @brief qspi ctrl2 register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dmaen : 1; /* [0] */
|
||||
__IO uint32_t cmdie : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 6; /* [7:2] */
|
||||
__IO uint32_t txfifo_thod : 2; /* [9:8] */
|
||||
__IO uint32_t reserved2 : 2; /* [11:10] */
|
||||
__IO uint32_t rxfifo_thod : 2; /* [13:12] */
|
||||
__IO uint32_t reserved3 : 18;/* [31:14] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi cmdsts register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cmdsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmdsts : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 31;/* [31:1] */
|
||||
} cmdsts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi rsts register, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t spists : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} rsts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi fsize register, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t fsize;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t spifsize : 32;/* [31:0] */
|
||||
} fsize_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi xip_cmd_w0 register, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t xip_cmd_w0;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t xipr_dum2 : 8; /* [7:0] */
|
||||
__IO uint32_t xipr_opmode : 3; /* [10:8] */
|
||||
__IO uint32_t xipr_adrlen : 1; /* [11] */
|
||||
__IO uint32_t xipr_insc : 8; /* [19:12] */
|
||||
__IO uint32_t reserved1 : 12;/* [31:20] */
|
||||
} xip_cmd_w0_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi xip_cmd_w1 register, offset:0x34
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t xip_cmd_w1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t xipr_dum2 : 8; /* [7:0] */
|
||||
__IO uint32_t xipr_opmode : 3; /* [10:8] */
|
||||
__IO uint32_t xipr_adrlen : 1; /* [11] */
|
||||
__IO uint32_t xipr_insc : 8; /* [19:12] */
|
||||
__IO uint32_t reserved1 : 12;/* [31:20] */
|
||||
} xip_cmd_w1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi xip_cmd_w2 register, offset:0x38
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t xip_cmd_w2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t xipr_dcnt : 6; /* [5:0] */
|
||||
__IO uint32_t reserved1 : 2; /* [7:6] */
|
||||
__IO uint32_t xipr_tcnt : 7; /* [14:8] */
|
||||
__IO uint32_t xipr_sel : 1; /* [15] */
|
||||
__IO uint32_t xipw_dcnt : 6; /* [21:16] */
|
||||
__IO uint32_t reserved2 : 2; /* [23:22] */
|
||||
__IO uint32_t xipw_tcnt : 7; /* [30:24] */
|
||||
__IO uint32_t xipw_sel : 1; /* [31] */
|
||||
} xip_cmd_w2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi xip_cmd_w3 register, offset:0x3C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t xip_cmd_w3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t bypassc : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 2; /* [2:1] */
|
||||
__IO uint32_t csts : 1; /* [3] */
|
||||
__IO uint32_t reserved2 : 28;/* [31:4] */
|
||||
} xip_cmd_w3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi reserved register, offset:0x40~4C
|
||||
*/
|
||||
__IO uint32_t reserved2[4];
|
||||
|
||||
/**
|
||||
* @brief qspi rev register, offset:0x50
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rev;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rev : 32;/* [31:0] */
|
||||
} rev_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief qspi reserved register, offset:0x54~FC
|
||||
*/
|
||||
__IO uint32_t reserved3[43];
|
||||
|
||||
/**
|
||||
* @brief qspi dt register, offset:0x100
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint8_t dt_u8;
|
||||
__IO uint16_t dt_u16;
|
||||
__IO uint32_t dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 32;/* [31:0] */
|
||||
} dt_bit;
|
||||
};
|
||||
|
||||
} qspi_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define QSPI1 ((qspi_type*)QSPI1_REG_BASE)
|
||||
#define QSPI2 ((qspi_type*)QSPI2_REG_BASE)
|
||||
|
||||
/** @defgroup QSPI_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state);
|
||||
void qspi_sck_mode_set( qspi_type* qspi_x, qspi_clk_mode_type new_mode);
|
||||
void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv);
|
||||
void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state);
|
||||
void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state);
|
||||
flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag);
|
||||
void qspi_flag_clear( qspi_type* qspi_x, uint32_t flag);
|
||||
void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
|
||||
void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
|
||||
void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state);
|
||||
void qspi_busy_config(qspi_type* qspi_x, qspi_busy_pos_type busy_pos);
|
||||
void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state);
|
||||
void qspi_cmd_operation_kick(qspi_type* qspi_x, qspi_cmd_type* qspi_cmd_struct);
|
||||
void qspi_xip_init(qspi_type* qspi_x, qspi_xip_type* xip_init_struct);
|
||||
uint8_t qspi_byte_read(qspi_type* qspi_x);
|
||||
uint16_t qspi_half_word_read(qspi_type* qspi_x);
|
||||
uint32_t qspi_word_read(qspi_type* qspi_x);
|
||||
void qspi_word_write(qspi_type* qspi_x, uint32_t value);
|
||||
void qspi_half_word_write(qspi_type* qspi_x, uint16_t value);
|
||||
void qspi_byte_write(qspi_type* qspi_x, uint8_t value);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,323 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_scfg.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 system config header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_SCFG_H
|
||||
#define __AT32F435_437_SCFG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SCFG
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SCFG_REG(value) PERIPH_REG(SCFG_BASE, value)
|
||||
#define SCFG_REG_BIT(value) PERIPH_REG_BIT(value)
|
||||
|
||||
/** @defgroup SCFG_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief scfg xmc addres mapping swap type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SCFG_XMC_SWAP_NONE = 0x00, /* no swap */
|
||||
SCFG_XMC_SWAP_MODE1 = 0x01, /* sdram nor psram sram nand2 swap */
|
||||
SCFG_XMC_SWAP_MODE2 = 0x02, /* nand3 qspi2 swap */
|
||||
SCFG_XMC_SWAP_MODE3 = 0x03 /* sdram nor psram sram nand2 nand3 qspi2 swap */
|
||||
} scfg_xmc_swap_type;
|
||||
|
||||
/**
|
||||
* @brief scfg infrared modulation signal source selecting type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SCFG_IR_SOURCE_TMR10 = 0x00, /* infrared signal source select tmr10 */
|
||||
SCFG_IR_SOURCE_USART1 = 0x01, /* infrared signal source select usart1 */
|
||||
SCFG_IR_SOURCE_USART2 = 0x02 /* infrared signal source select usart2 */
|
||||
} scfg_ir_source_type;
|
||||
|
||||
/**
|
||||
* @brief scfg infrared output polarity selecting type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SCFG_IR_POLARITY_NO_AFFECTE = 0x00, /* infrared output polarity no affecte */
|
||||
SCFG_IR_POLARITY_REVERSE = 0x01 /* infrared output polarity reverse */
|
||||
} scfg_ir_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief scfg memory address mapping selecting type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SCFG_MEM_MAP_MAIN_MEMORY = 0x00, /* 0x00000000 address mapping from main memory */
|
||||
SCFG_MEM_MAP_BOOT_MEMORY = 0x01, /* 0x00000000 address mapping from boot memory */
|
||||
SCFG_MEM_MAP_XMC_BANK1 = 0x02, /* 0x00000000 address mapping from xmc bank1 */
|
||||
SCFG_MEM_MAP_INTERNAL_SRAM = 0x03, /* 0x00000000 address mapping from internal sram */
|
||||
SCFG_MEM_MAP_XMC_SDRAM_BANK1 = 0x04 /* 0x00000000 address mapping from xmc sdram bank1 */
|
||||
} scfg_mem_map_type;
|
||||
|
||||
/**
|
||||
* @brief scfg pin source type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SCFG_PINS_SOURCE0 = 0x00,
|
||||
SCFG_PINS_SOURCE1 = 0x01,
|
||||
SCFG_PINS_SOURCE2 = 0x02,
|
||||
SCFG_PINS_SOURCE3 = 0x03,
|
||||
SCFG_PINS_SOURCE4 = 0x04,
|
||||
SCFG_PINS_SOURCE5 = 0x05,
|
||||
SCFG_PINS_SOURCE6 = 0x06,
|
||||
SCFG_PINS_SOURCE7 = 0x07,
|
||||
SCFG_PINS_SOURCE8 = 0x08,
|
||||
SCFG_PINS_SOURCE9 = 0x09,
|
||||
SCFG_PINS_SOURCE10 = 0x0A,
|
||||
SCFG_PINS_SOURCE11 = 0x0B,
|
||||
SCFG_PINS_SOURCE12 = 0x0C,
|
||||
SCFG_PINS_SOURCE13 = 0x0D,
|
||||
SCFG_PINS_SOURCE14 = 0x0E,
|
||||
SCFG_PINS_SOURCE15 = 0x0F
|
||||
} scfg_pins_source_type;
|
||||
|
||||
/**
|
||||
* @brief gpio port source type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SCFG_PORT_SOURCE_GPIOA = 0x00,
|
||||
SCFG_PORT_SOURCE_GPIOB = 0x01,
|
||||
SCFG_PORT_SOURCE_GPIOC = 0x02,
|
||||
SCFG_PORT_SOURCE_GPIOD = 0x03,
|
||||
SCFG_PORT_SOURCE_GPIOE = 0x04,
|
||||
SCFG_PORT_SOURCE_GPIOF = 0x05,
|
||||
SCFG_PORT_SOURCE_GPIOG = 0x06,
|
||||
SCFG_PORT_SOURCE_GPIOH = 0x07
|
||||
} scfg_port_source_type;
|
||||
|
||||
/**
|
||||
* @brief scfg emac interface selecting type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SCFG_EMAC_SELECT_MII = 0x00, /* emac interface select mii mode */
|
||||
SCFG_EMAC_SELECT_RMII = 0x01 /* emac interface select rmii mode */
|
||||
} scfg_emac_interface_type;
|
||||
|
||||
/**
|
||||
* @brief scfg ultra high sourcing/sinking strength pins type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SCFG_ULTRA_DRIVEN_PB3 = MAKE_VALUE(0x2C, 0),
|
||||
SCFG_ULTRA_DRIVEN_PB9 = MAKE_VALUE(0x2C, 1),
|
||||
SCFG_ULTRA_DRIVEN_PB10 = MAKE_VALUE(0x2C, 2),
|
||||
SCFG_ULTRA_DRIVEN_PD12 = MAKE_VALUE(0x2C, 5),
|
||||
SCFG_ULTRA_DRIVEN_PD13 = MAKE_VALUE(0x2C, 6),
|
||||
SCFG_ULTRA_DRIVEN_PD14 = MAKE_VALUE(0x2C, 7),
|
||||
SCFG_ULTRA_DRIVEN_PD15 = MAKE_VALUE(0x2C, 8),
|
||||
SCFG_ULTRA_DRIVEN_PF14 = MAKE_VALUE(0x2C, 9),
|
||||
SCFG_ULTRA_DRIVEN_PF15 = MAKE_VALUE(0x2C, 10)
|
||||
} scfg_ultra_driven_pins_type;
|
||||
|
||||
/**
|
||||
* @brief type define system config register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief scfg cfg1 register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cfg1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t mem_map_sel : 3; /* [2:0] */
|
||||
__IO uint32_t reserved1 : 2; /* [4:3] */
|
||||
__IO uint32_t ir_pol : 1; /* [5] */
|
||||
__IO uint32_t ir_src_sel : 2; /* [7:6] */
|
||||
__IO uint32_t reserved2 : 2; /* [9:8] */
|
||||
__IO uint32_t swap_xmc : 2; /* [11:10] */
|
||||
__IO uint32_t reserved3 : 20;/* [31:12] */
|
||||
} cfg1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief scfg cfg2 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cfg2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 23;/* [22:0] */
|
||||
__IO uint32_t mii_rmii_sel : 1; /* [23] */
|
||||
__IO uint32_t reserved2 : 8; /* [31:24] */
|
||||
} cfg2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief scfg exintc1 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t exintc1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t exint0 : 4; /* [3:0] */
|
||||
__IO uint32_t exint1 : 4; /* [7:4] */
|
||||
__IO uint32_t exint2 : 4; /* [11:8] */
|
||||
__IO uint32_t exint3 : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} exintc1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief scfg exintc2 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t exintc2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t exint4 : 4; /* [3:0] */
|
||||
__IO uint32_t exint5 : 4; /* [7:4] */
|
||||
__IO uint32_t exint6 : 4; /* [11:8] */
|
||||
__IO uint32_t exint7 : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} exintc2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief scfg exintc3 register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t exintc3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t exint8 : 4; /* [3:0] */
|
||||
__IO uint32_t exint9 : 4; /* [7:4] */
|
||||
__IO uint32_t exint10 : 4; /* [11:8] */
|
||||
__IO uint32_t exint11 : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} exintc3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief scfg exintc4 register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t exintc4;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t exint12 : 4; /* [3:0] */
|
||||
__IO uint32_t exint13 : 4; /* [7:4] */
|
||||
__IO uint32_t exint14 : 4; /* [11:8] */
|
||||
__IO uint32_t exint15 : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} exintc4_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm reserved1 register, offset:0x18~0x28
|
||||
*/
|
||||
__IO uint32_t reserved1[5];
|
||||
|
||||
/**
|
||||
* @brief scfg uhdrv register, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t uhdrv;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pb3_uh : 1; /* [0] */
|
||||
__IO uint32_t pb9_uh : 1; /* [1] */
|
||||
__IO uint32_t pb10_uh : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 2; /* [4:3] */
|
||||
__IO uint32_t pd12_uh : 1; /* [5] */
|
||||
__IO uint32_t pd13_uh : 1; /* [6] */
|
||||
__IO uint32_t pd14_uh : 1; /* [7] */
|
||||
__IO uint32_t pd15_uh : 1; /* [8] */
|
||||
__IO uint32_t pf14_uh : 1; /* [9] */
|
||||
__IO uint32_t pf15_uh : 1; /* [10] */
|
||||
__IO uint32_t reserved2 : 21;/* [31:11] */
|
||||
} uhdrv_bit;
|
||||
};
|
||||
|
||||
} scfg_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define SCFG ((scfg_type *) SCFG_BASE)
|
||||
|
||||
/** @defgroup SCFG_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void scfg_reset(void);
|
||||
void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap);
|
||||
void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity);
|
||||
void scfg_mem_map_set(scfg_mem_map_type mem_map);
|
||||
void scfg_emac_interface_set(scfg_emac_interface_type mode);
|
||||
void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source);
|
||||
void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,624 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_sdio.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 sdio header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_SDIO_H
|
||||
#define __AT32F435_437_SDIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_interrupts_definition
|
||||
* @brief sdio interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_CMDFAIL_INT ((uint32_t)0x00000001) /*!< command response received check failed interrupt */
|
||||
#define SDIO_DTFAIL_INT ((uint32_t)0x00000002) /*!< data block sent/received check failed interrupt */
|
||||
#define SDIO_CMDTIMEOUT_INT ((uint32_t)0x00000004) /*!< command response timerout interrupt */
|
||||
#define SDIO_DTTIMEOUT_INT ((uint32_t)0x00000008) /*!< data timeout interrupt */
|
||||
#define SDIO_TXERRU_INT ((uint32_t)0x00000010) /*!< transmit underrun error interrupt */
|
||||
#define SDIO_RXERRO_INT ((uint32_t)0x00000020) /*!< received overrun error interrupt */
|
||||
#define SDIO_CMDRSPCMPL_INT ((uint32_t)0x00000040) /*!< command response received interrupt */
|
||||
#define SDIO_CMDCMPL_INT ((uint32_t)0x00000080) /*!< command sent interrupt */
|
||||
#define SDIO_DTCMP_INT ((uint32_t)0x00000100) /*!< data sent interrupt */
|
||||
#define SDIO_SBITERR_INT ((uint32_t)0x00000200) /*!< start bit not detected on data bus interrupt */
|
||||
#define SDIO_DTBLKCMPL_INT ((uint32_t)0x00000400) /*!< data block sent/received interrupt */
|
||||
#define SDIO_DOCMD_INT ((uint32_t)0x00000800) /*!< command transfer in progress interrupt */
|
||||
#define SDIO_DOTX_INT ((uint32_t)0x00001000) /*!< data transmit in progress interrupt */
|
||||
#define SDIO_DORX_INT ((uint32_t)0x00002000) /*!< data receive in progress interrupt */
|
||||
#define SDIO_TXBUFH_INT ((uint32_t)0x00004000) /*!< transmit buf half empty interrupt */
|
||||
#define SDIO_RXBUFH_INT ((uint32_t)0x00008000) /*!< receive buf half full interrupt */
|
||||
#define SDIO_TXBUFF_INT ((uint32_t)0x00010000) /*!< transmit buf full interrupt */
|
||||
#define SDIO_RXBUFF_INT ((uint32_t)0x00020000) /*!< receive buf full interrupt */
|
||||
#define SDIO_TXBUFE_INT ((uint32_t)0x00040000) /*!< transmit buf empty interrupt */
|
||||
#define SDIO_RXBUFE_INT ((uint32_t)0x00080000) /*!< receive buf empty interrupt */
|
||||
#define SDIO_TXBUF_INT ((uint32_t)0x00100000) /*!< data available in transmit interrupt */
|
||||
#define SDIO_RXBUF_INT ((uint32_t)0x00200000) /*!< data available in receive interrupt */
|
||||
#define SDIO_SDIOIF_INT ((uint32_t)0x00400000) /*!< sdio interface received interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_flags_definition
|
||||
* @brief sdio flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_CMDFAIL_FLAG ((uint32_t)0x00000001) /*!< command response received check failed flag */
|
||||
#define SDIO_DTFAIL_FLAG ((uint32_t)0x00000002) /*!< data block sent/received check failed flag */
|
||||
#define SDIO_CMDTIMEOUT_FLAG ((uint32_t)0x00000004) /*!< command response timerout flag */
|
||||
#define SDIO_DTTIMEOUT_FLAG ((uint32_t)0x00000008) /*!< data timeout flag */
|
||||
#define SDIO_TXERRU_FLAG ((uint32_t)0x00000010) /*!< transmit underrun error flag */
|
||||
#define SDIO_RXERRO_FLAG ((uint32_t)0x00000020) /*!< received overrun error flag */
|
||||
#define SDIO_CMDRSPCMPL_FLAG ((uint32_t)0x00000040) /*!< command response received flag */
|
||||
#define SDIO_CMDCMPL_FLAG ((uint32_t)0x00000080) /*!< command sent flag */
|
||||
#define SDIO_DTCMPL_FLAG ((uint32_t)0x00000100) /*!< data sent flag */
|
||||
#define SDIO_SBITERR_FLAG ((uint32_t)0x00000200) /*!< start bit not detected on data bus flag */
|
||||
#define SDIO_DTBLKCMPL_FLAG ((uint32_t)0x00000400) /*!< data block sent/received flag */
|
||||
#define SDIO_DOCMD_FLAG ((uint32_t)0x00000800) /*!< command transfer in progress flag */
|
||||
#define SDIO_DOTX_FLAG ((uint32_t)0x00001000) /*!< data transmit in progress flag */
|
||||
#define SDIO_DORX_FLAG ((uint32_t)0x00002000) /*!< data receive in progress flag */
|
||||
#define SDIO_TXBUFH_FLAG ((uint32_t)0x00004000) /*!< transmit buf half empty flag */
|
||||
#define SDIO_RXBUFH_FLAG ((uint32_t)0x00008000) /*!< receive buf half full flag */
|
||||
#define SDIO_TXBUFF_FLAG ((uint32_t)0x00010000) /*!< transmit buf full flag */
|
||||
#define SDIO_RXBUFF_FLAG ((uint32_t)0x00020000) /*!< receive buf full flag */
|
||||
#define SDIO_TXBUFE_FLAG ((uint32_t)0x00040000) /*!< transmit buf empty flag */
|
||||
#define SDIO_RXBUFE_FLAG ((uint32_t)0x00080000) /*!< receive buf empty flag */
|
||||
#define SDIO_TXBUF_FLAG ((uint32_t)0x00100000) /*!< data available in transmit flag */
|
||||
#define SDIO_RXBUF_FLAG ((uint32_t)0x00200000) /*!< data available in receive flag */
|
||||
#define SDIO_SDIOIF_FLAG ((uint32_t)0x00400000) /*!< sdio interface received flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief sdio power state
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_POWER_OFF = 0x00, /*!< power-off, clock to card is stopped */
|
||||
SDIO_POWER_ON = 0x03 /*!< power-on, the card is clocked */
|
||||
} sdio_power_state_type;
|
||||
|
||||
/**
|
||||
* @brief sdio edge phase
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_CLOCK_EDGE_RISING = 0x00, /*!< sdio bus clock generated on the rising edge of the master clock */
|
||||
SDIO_CLOCK_EDGE_FALLING = 0x01 /*!< sdio bus clock generated on the falling edge of the master clock */
|
||||
} sdio_edge_phase_type;
|
||||
|
||||
/**
|
||||
* @brief sdio bus width
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_BUS_WIDTH_D1 = 0x00, /*!< sdio wide bus select 1-bit */
|
||||
SDIO_BUS_WIDTH_D4 = 0x01, /*!< sdio wide bus select 4-bit */
|
||||
SDIO_BUS_WIDTH_D8 = 0x02 /*!< sdio wide bus select 8-bit */
|
||||
} sdio_bus_width_type;
|
||||
|
||||
/**
|
||||
* @brief sdio response type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_RESPONSE_NO = 0x00, /*!< no response */
|
||||
SDIO_RESPONSE_SHORT = 0x01, /*!< short response */
|
||||
SDIO_RESPONSE_LONG = 0x03 /*!< long response */
|
||||
} sdio_reponse_type;
|
||||
|
||||
/**
|
||||
* @brief sdio wait type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_WAIT_FOR_NO = 0x00, /*!< no wait */
|
||||
SDIO_WAIT_FOR_INT = 0x01, /*!< wait interrupt request */
|
||||
SDIO_WAIT_FOR_PEND = 0x02 /*!< wait end of transfer */
|
||||
} sdio_wait_type;
|
||||
|
||||
/**
|
||||
* @brief sdio response register index
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_RSP1_INDEX = 0x00, /*!< response index 1, corresponding to sdio_rsp register 1 */
|
||||
SDIO_RSP2_INDEX = 0x01, /*!< response index 2, corresponding to sdio_rsp register 2 */
|
||||
SDIO_RSP3_INDEX = 0x02, /*!< response index 3, corresponding to sdio_rsp register 3 */
|
||||
SDIO_RSP4_INDEX = 0x03 /*!< response index 4, corresponding to sdio_rsp register 4 */
|
||||
} sdio_rsp_index_type;
|
||||
|
||||
/**
|
||||
* @brief sdio data block size
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_DATA_BLOCK_SIZE_1B = 0x00, /*!< data block size 1 byte */
|
||||
SDIO_DATA_BLOCK_SIZE_2B = 0x01, /*!< data block size 2 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_4B = 0x02, /*!< data block size 4 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_8B = 0x03, /*!< data block size 8 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_16B = 0x04, /*!< data block size 16 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_32B = 0x05, /*!< data block size 32 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_64B = 0x06, /*!< data block size 64 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_128B = 0x07, /*!< data block size 128 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_256B = 0x08, /*!< data block size 256 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_512B = 0x09, /*!< data block size 512 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_1024B = 0x0A, /*!< data block size 1024 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_2048B = 0x0B, /*!< data block size 2048 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_4096B = 0x0C, /*!< data block size 4096 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_8192B = 0x0D, /*!< data block size 8192 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_16384B = 0x0E /*!< data block size 16384 bytes */
|
||||
} sdio_block_size_type;
|
||||
|
||||
/**
|
||||
* @brief sdio data transfer mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_DATA_BLOCK_TRANSFER = 0x00, /*!< the sdio block transfer mode */
|
||||
SDIO_DATA_STREAM_TRANSFER = 0x01 /*!< the sdio stream transfer mode */
|
||||
} sdio_transfer_mode_type;
|
||||
|
||||
/**
|
||||
* @brief sdio data transfer direction
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_DATA_TRANSFER_TO_CARD = 0x00, /*!< the sdio controller write */
|
||||
SDIO_DATA_TRANSFER_TO_CONTROLLER = 0x01 /*!< the sdio controller read */
|
||||
} sdio_transfer_direction_type;
|
||||
|
||||
/**
|
||||
* @brief sdio read wait mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_READ_WAIT_CONTROLLED_BY_D2 = 0x00, /*!< the sdio read wait on data2 line */
|
||||
SDIO_READ_WAIT_CONTROLLED_BY_CK = 0x01 /*!< the sdio read wait on clock line */
|
||||
} sdio_read_wait_mode_type;
|
||||
|
||||
/**
|
||||
* @brief sdio command structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t argument; /*!< the sdio command argument is sent to a card as part of command message */
|
||||
uint8_t cmd_index; /*!< the sdio command index */
|
||||
sdio_reponse_type rsp_type; /*!< the sdio response type */
|
||||
sdio_wait_type wait_type; /*!< the sdio wait for interrupt request is enabled or disable */
|
||||
} sdio_command_struct_type;
|
||||
|
||||
/**
|
||||
* @brief sdio data structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t timeout; /*!< the sdio data timeout period in car bus clock periods */
|
||||
uint32_t data_length; /*!< the sdio data length */
|
||||
sdio_block_size_type block_size; /*!< the sdio data block size of block transfer mode */
|
||||
sdio_transfer_mode_type transfer_mode; /*!< the sdio transfer mode, block or stream */
|
||||
sdio_transfer_direction_type transfer_direction; /*!< the sdio data transfer direction */
|
||||
} sdio_data_struct_type;
|
||||
|
||||
/**
|
||||
* @brief type define sdio register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief sdio pwrctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pwrctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ps : 2; /* [1:0] */
|
||||
__IO uint32_t reserved1 : 30;/* [31:2] */
|
||||
} pwrctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio clkctrl register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t clkctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t clkdiv_l : 8; /* [7:0] */
|
||||
__IO uint32_t clkoen : 1; /* [8] */
|
||||
__IO uint32_t pwrsven : 1; /* [9] */
|
||||
__IO uint32_t bypsen : 1; /* [10] */
|
||||
__IO uint32_t busws : 2; /* [12:11] */
|
||||
__IO uint32_t clkegs : 1; /* [13] */
|
||||
__IO uint32_t hfcen : 1; /* [14] */
|
||||
__IO uint32_t clkdiv_h : 2; /* [16:15] */
|
||||
__IO uint32_t reserved1 : 15;/* [31:17] */
|
||||
} clkctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio argu register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t argu;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t argu : 32;/* [31:0] */
|
||||
} argu_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio cmdctrl register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cmdctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmdidx : 6; /* [5:0] */
|
||||
__IO uint32_t rspwt : 2; /* [7:6] */
|
||||
__IO uint32_t intwt : 1; /* [8] */
|
||||
__IO uint32_t pndwt : 1; /* [9] */
|
||||
__IO uint32_t ccsmen : 1; /* [10] */
|
||||
__IO uint32_t iosusp : 1; /* [11] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} cmdctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio rspcmd register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rspcmd;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rspcmd : 6; /* [5:0] */
|
||||
__IO uint32_t reserved1 : 26;/* [31:6] */
|
||||
} rspcmd_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio rsp1 register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rsp1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cardsts1 : 32;/* [31:0] */
|
||||
} rsp1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio rsp2 register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rsp2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cardsts2 : 32;/* [31:0] */
|
||||
} rsp2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio rsp3 register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rsp3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cardsts3 : 32;/* [31:0] */
|
||||
} rsp3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio rsp4 register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rsp4;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cardsts4 : 32;/* [31:0] */
|
||||
} rsp4_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio dttmr register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dttmr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t timeout : 32;/* [31:0] */
|
||||
} dttmr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio dtlen register, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dtlen;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dtlen : 25;/* [24:0] */
|
||||
__IO uint32_t reserved1 : 7; /* [31:25] */
|
||||
} dtlen_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio dtctrl register, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dtctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tfren : 1; /* [0] */
|
||||
__IO uint32_t tfrdir : 1; /* [1] */
|
||||
__IO uint32_t tfrmode : 1; /* [2] */
|
||||
__IO uint32_t dmaen : 1; /* [3] */
|
||||
__IO uint32_t blksize : 4; /* [7:4] */
|
||||
__IO uint32_t rdwtstart : 1; /* [8] */
|
||||
__IO uint32_t rdwtstop : 1; /* [9] */
|
||||
__IO uint32_t rdwtmode : 1; /* [10] */
|
||||
__IO uint32_t ioen : 1; /* [11] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} dtctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio dtcnt register, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dtcnt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cnt : 25;/* [24:0] */
|
||||
__IO uint32_t reserved1 : 7; /* [31:25] */
|
||||
} dtcnt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio sts register, offset:0x34
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmdfail : 1; /* [0] */
|
||||
__IO uint32_t dtfail : 1; /* [1] */
|
||||
__IO uint32_t cmdtimeout : 1; /* [2] */
|
||||
__IO uint32_t dttimeout : 1; /* [3] */
|
||||
__IO uint32_t txerru : 1; /* [4] */
|
||||
__IO uint32_t rxerro : 1; /* [5] */
|
||||
__IO uint32_t cmdrspcmpl : 1; /* [6] */
|
||||
__IO uint32_t cmdcmpl : 1; /* [7] */
|
||||
__IO uint32_t dtcmpl : 1; /* [8] */
|
||||
__IO uint32_t sbiterr : 1; /* [9] */
|
||||
__IO uint32_t dtblkcmpl : 1; /* [10] */
|
||||
__IO uint32_t docmd : 1; /* [11] */
|
||||
__IO uint32_t dotx : 1; /* [12] */
|
||||
__IO uint32_t dorx : 1; /* [13] */
|
||||
__IO uint32_t txbufh : 1; /* [14] */
|
||||
__IO uint32_t rxbufh : 1; /* [15] */
|
||||
__IO uint32_t txbuff : 1; /* [16] */
|
||||
__IO uint32_t rxbuff : 1; /* [17] */
|
||||
__IO uint32_t txbufe : 1; /* [18] */
|
||||
__IO uint32_t rxbufe : 1; /* [19] */
|
||||
__IO uint32_t txbuf : 1; /* [20] */
|
||||
__IO uint32_t rxbuf : 1; /* [21] */
|
||||
__IO uint32_t ioif : 1; /* [22] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio intclr register, offset:0x38
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t intclr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmdfail : 1; /* [0] */
|
||||
__IO uint32_t dtfail : 1; /* [1] */
|
||||
__IO uint32_t cmdtimeout : 1; /* [2] */
|
||||
__IO uint32_t dttimeout : 1; /* [3] */
|
||||
__IO uint32_t txerru : 1; /* [4] */
|
||||
__IO uint32_t rxerro : 1; /* [5] */
|
||||
__IO uint32_t cmdrspcmpl : 1; /* [6] */
|
||||
__IO uint32_t cmdcmpl : 1; /* [7] */
|
||||
__IO uint32_t dtcmpl : 1; /* [8] */
|
||||
__IO uint32_t sbiterr : 1; /* [9] */
|
||||
__IO uint32_t dtblkcmpl : 1; /* [10] */
|
||||
__IO uint32_t reserved1 : 11;/* [21:11] */
|
||||
__IO uint32_t ioif : 1; /* [22] */
|
||||
__IO uint32_t reserved2 : 9; /* [31:23] */
|
||||
} intclr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio inten register, offset:0x3C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t inten;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmdfailien : 1; /* [0] */
|
||||
__IO uint32_t dtfailien : 1; /* [1] */
|
||||
__IO uint32_t cmdtimeoutien : 1; /* [2] */
|
||||
__IO uint32_t dttimeoutien : 1; /* [3] */
|
||||
__IO uint32_t txerruien : 1; /* [4] */
|
||||
__IO uint32_t rxerroien : 1; /* [5] */
|
||||
__IO uint32_t cmdrspcmplien : 1; /* [6] */
|
||||
__IO uint32_t cmdcmplien : 1; /* [7] */
|
||||
__IO uint32_t dtcmplien : 1; /* [8] */
|
||||
__IO uint32_t sbiterrien : 1; /* [9] */
|
||||
__IO uint32_t dtblkcmplien : 1; /* [10] */
|
||||
__IO uint32_t docmdien : 1; /* [11] */
|
||||
__IO uint32_t dotxien : 1; /* [12] */
|
||||
__IO uint32_t dorxien : 1; /* [13] */
|
||||
__IO uint32_t txbufhien : 1; /* [14] */
|
||||
__IO uint32_t rxbufhien : 1; /* [15] */
|
||||
__IO uint32_t txbuffien : 1; /* [16] */
|
||||
__IO uint32_t rxbuffien : 1; /* [17] */
|
||||
__IO uint32_t txbufeien : 1; /* [18] */
|
||||
__IO uint32_t rxbufeien : 1; /* [19] */
|
||||
__IO uint32_t txbufien : 1; /* [20] */
|
||||
__IO uint32_t rxbufien : 1; /* [21] */
|
||||
__IO uint32_t ioifien : 1; /* [22] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} inten_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio reserved1 register, offset:0x40~0x44
|
||||
*/
|
||||
__IO uint32_t reserved1[2];
|
||||
|
||||
/**
|
||||
* @brief sdio bufcnt register, offset:0x48
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t bufcnt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cnt : 24;/* [23:0] */
|
||||
__IO uint32_t reserved1 : 8; /* [31:24] */
|
||||
} bufcnt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio reserved2 register, offset:0x4C~0x7C
|
||||
*/
|
||||
__IO uint32_t reserved2[13];
|
||||
|
||||
/**
|
||||
* @brief sdio buf register, offset:0x80
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t buf;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 32;/* [31:0] */
|
||||
} buf_bit;
|
||||
};
|
||||
|
||||
} sdio_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define SDIO1 ((sdio_type *) SDIO1_BASE)
|
||||
#define SDIO2 ((sdio_type *) SDIO2_BASE)
|
||||
|
||||
/** @defgroup SDIO_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void sdio_reset(sdio_type *sdio_x);
|
||||
void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state);
|
||||
flag_status sdio_power_status_get(sdio_type *sdio_x);
|
||||
void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg);
|
||||
void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width);
|
||||
void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state);
|
||||
flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag);
|
||||
void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag);
|
||||
void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct);
|
||||
void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
uint8_t sdio_command_response_get(sdio_type *sdio_x);
|
||||
uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index);
|
||||
void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct);
|
||||
void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
uint32_t sdio_data_counter_get(sdio_type *sdio_x);
|
||||
uint32_t sdio_data_read(sdio_type *sdio_x);
|
||||
uint32_t sdio_buffer_counter_get(sdio_type *sdio_x);
|
||||
void sdio_data_write(sdio_type *sdio_x, uint32_t data);
|
||||
void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode);
|
||||
void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,505 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_spi.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 spi header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_SPI_H
|
||||
#define __AT32F435_437_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_I2S_flags_definition
|
||||
* @brief spi i2s flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_RDBF_FLAG 0x0001 /*!< spi or i2s receive data buffer full flag */
|
||||
#define SPI_I2S_TDBE_FLAG 0x0002 /*!< spi or i2s transmit data buffer empty flag */
|
||||
#define I2S_ACS_FLAG 0x0004 /*!< i2s audio channel state flag */
|
||||
#define I2S_TUERR_FLAG 0x0008 /*!< i2s transmitter underload error flag */
|
||||
#define SPI_CCERR_FLAG 0x0010 /*!< spi crc calculation error flag */
|
||||
#define SPI_MMERR_FLAG 0x0020 /*!< spi master mode error flag */
|
||||
#define SPI_I2S_ROERR_FLAG 0x0040 /*!< spi or i2s receiver overflow error flag */
|
||||
#define SPI_I2S_BF_FLAG 0x0080 /*!< spi or i2s busy flag */
|
||||
#define SPI_CSPAS_FLAG 0x0100 /*!< spi cs pulse abnormal setting fiag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_I2S_interrupts_definition
|
||||
* @brief spi i2s interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_ERROR_INT 0x0020 /*!< error interrupt */
|
||||
#define SPI_I2S_RDBF_INT 0x0040 /*!< receive data buffer full interrupt */
|
||||
#define SPI_I2S_TDBE_INT 0x0080 /*!< transmit data buffer empty interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief spi frame bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_FRAME_8BIT = 0x00, /*!< 8-bit data frame format */
|
||||
SPI_FRAME_16BIT = 0x01 /*!< 16-bit data frame format */
|
||||
} spi_frame_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief spi master/slave mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_MODE_SLAVE = 0x00, /*!< select as slave mode */
|
||||
SPI_MODE_MASTER = 0x01 /*!< select as master mode */
|
||||
} spi_master_slave_mode_type;
|
||||
|
||||
/**
|
||||
* @brief spi clock polarity (clkpol) type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_CLOCK_POLARITY_LOW = 0x00, /*!< sck keeps low at idle state */
|
||||
SPI_CLOCK_POLARITY_HIGH = 0x01 /*!< sck keeps high at idle state */
|
||||
} spi_clock_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief spi clock phase (clkpha) type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_CLOCK_PHASE_1EDGE = 0x00, /*!< data capture start from the first clock edge */
|
||||
SPI_CLOCK_PHASE_2EDGE = 0x01 /*!< data capture start from the second clock edge */
|
||||
} spi_clock_phase_type;
|
||||
|
||||
/**
|
||||
* @brief spi cs mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_CS_HARDWARE_MODE = 0x00, /*!< cs is hardware mode */
|
||||
SPI_CS_SOFTWARE_MODE = 0x01 /*!< cs is software mode */
|
||||
} spi_cs_mode_type;
|
||||
|
||||
/**
|
||||
* @brief spi master clock frequency division type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_MCLK_DIV_2 = 0x00, /*!< master clock frequency division 2 */
|
||||
SPI_MCLK_DIV_3 = 0x0A, /*!< master clock frequency division 3 */
|
||||
SPI_MCLK_DIV_4 = 0x01, /*!< master clock frequency division 4 */
|
||||
SPI_MCLK_DIV_8 = 0x02, /*!< master clock frequency division 8 */
|
||||
SPI_MCLK_DIV_16 = 0x03, /*!< master clock frequency division 16 */
|
||||
SPI_MCLK_DIV_32 = 0x04, /*!< master clock frequency division 32 */
|
||||
SPI_MCLK_DIV_64 = 0x05, /*!< master clock frequency division 64 */
|
||||
SPI_MCLK_DIV_128 = 0x06, /*!< master clock frequency division 128 */
|
||||
SPI_MCLK_DIV_256 = 0x07, /*!< master clock frequency division 256 */
|
||||
SPI_MCLK_DIV_512 = 0x08, /*!< master clock frequency division 512 */
|
||||
SPI_MCLK_DIV_1024 = 0x09 /*!< master clock frequency division 1024 */
|
||||
} spi_mclk_freq_div_type;
|
||||
|
||||
/**
|
||||
* @brief spi transmit first bit (lsb/msb) type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_FIRST_BIT_MSB = 0x00, /*!< the frame format is msb first */
|
||||
SPI_FIRST_BIT_LSB = 0x01 /*!< the frame format is lsb first */
|
||||
} spi_first_bit_type;
|
||||
|
||||
/**
|
||||
* @brief spi transmission mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_TRANSMIT_FULL_DUPLEX = 0x00, /*!< dual line unidirectional full-duplex mode(slben = 0 and ora = 0) */
|
||||
SPI_TRANSMIT_SIMPLEX_RX = 0x01, /*!< dual line unidirectional simplex receive-only mode(slben = 0 and ora = 1) */
|
||||
SPI_TRANSMIT_HALF_DUPLEX_RX = 0x02, /*!< single line bidirectional half duplex mode-receiving(slben = 1 and slbtd = 0) */
|
||||
SPI_TRANSMIT_HALF_DUPLEX_TX = 0x03 /*!< single line bidirectional half duplex mode-transmitting(slben = 1 and slbtd = 1) */
|
||||
} spi_transmission_mode_type;
|
||||
|
||||
/**
|
||||
* @brief spi crc direction type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_CRC_RX = 0x0014, /*!< crc direction is rx */
|
||||
SPI_CRC_TX = 0x0018 /*!< crc direction is tx */
|
||||
} spi_crc_direction_type;
|
||||
|
||||
/**
|
||||
* @brief spi single line bidirectional direction type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_HALF_DUPLEX_DIRECTION_RX = 0x00, /*!< single line bidirectional half duplex mode direction: receive(slbtd = 0) */
|
||||
SPI_HALF_DUPLEX_DIRECTION_TX = 0x01 /*!< single line bidirectional half duplex mode direction: transmit(slbtd = 1) */
|
||||
} spi_half_duplex_direction_type;
|
||||
|
||||
/**
|
||||
* @brief spi software cs internal level type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_SWCS_INTERNAL_LEVEL_LOW = 0x00, /*!< internal level low */
|
||||
SPI_SWCS_INTERNAL_LEVEL_HIGHT = 0x01 /*!< internal level high */
|
||||
} spi_software_cs_level_type;
|
||||
|
||||
/**
|
||||
* @brief i2s audio protocol type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2S_AUDIO_PROTOCOL_PHILLIPS = 0x00, /*!< i2s philip standard */
|
||||
I2S_AUDIO_PROTOCOL_MSB = 0x01, /*!< msb-justified standard */
|
||||
I2S_AUDIO_PROTOCOL_LSB = 0x02, /*!< lsb-justified standard */
|
||||
I2S_AUDIO_PROTOCOL_PCM_SHORT = 0x03, /*!< pcm standard-short frame */
|
||||
I2S_AUDIO_PROTOCOL_PCM_LONG = 0x04 /*!< pcm standard-long frame */
|
||||
} i2s_audio_protocol_type;
|
||||
|
||||
/**
|
||||
* @brief i2s audio frequency type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2S_AUDIO_FREQUENCY_DEFAULT = 2, /*!< i2s audio sampling frequency default */
|
||||
I2S_AUDIO_FREQUENCY_8K = 8000, /*!< i2s audio sampling frequency 8k */
|
||||
I2S_AUDIO_FREQUENCY_11_025K = 11025, /*!< i2s audio sampling frequency 11.025k */
|
||||
I2S_AUDIO_FREQUENCY_16K = 16000, /*!< i2s audio sampling frequency 16k */
|
||||
I2S_AUDIO_FREQUENCY_22_05K = 22050, /*!< i2s audio sampling frequency 22.05k */
|
||||
I2S_AUDIO_FREQUENCY_32K = 32000, /*!< i2s audio sampling frequency 32k */
|
||||
I2S_AUDIO_FREQUENCY_44_1K = 44100, /*!< i2s audio sampling frequency 44.1k */
|
||||
I2S_AUDIO_FREQUENCY_48K = 48000, /*!< i2s audio sampling frequency 48k */
|
||||
I2S_AUDIO_FREQUENCY_96K = 96000, /*!< i2s audio sampling frequency 96k */
|
||||
I2S_AUDIO_FREQUENCY_192K = 192000 /*!< i2s audio sampling frequency 192k */
|
||||
} i2s_audio_sampling_freq_type;
|
||||
|
||||
/**
|
||||
* @brief i2s data bit num and channel bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2S_DATA_16BIT_CHANNEL_16BIT = 0x01, /*!< 16-bit data packed in 16-bit channel frame */
|
||||
I2S_DATA_16BIT_CHANNEL_32BIT = 0x02, /*!< 16-bit data packed in 32-bit channel frame */
|
||||
I2S_DATA_24BIT_CHANNEL_32BIT = 0x03, /*!< 24-bit data packed in 32-bit channel frame */
|
||||
I2S_DATA_32BIT_CHANNEL_32BIT = 0x04 /*!< 32-bit data packed in 32-bit channel frame */
|
||||
} i2s_data_channel_format_type;
|
||||
|
||||
/**
|
||||
* @brief i2s operation mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2S_MODE_SLAVE_TX = 0x00, /*!< slave transmission mode */
|
||||
I2S_MODE_SLAVE_RX = 0x01, /*!< slave reception mode */
|
||||
I2S_MODE_MASTER_TX = 0x02, /*!< master transmission mode */
|
||||
I2S_MODE_MASTER_RX = 0x03 /*!< master reception mode */
|
||||
} i2s_operation_mode_type;
|
||||
|
||||
/**
|
||||
* @brief i2s clock polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2S_CLOCK_POLARITY_LOW = 0x00, /*!< i2s clock steady state is low level */
|
||||
I2S_CLOCK_POLARITY_HIGH = 0x01 /*!< i2s clock steady state is high level */
|
||||
} i2s_clock_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief spi init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
spi_transmission_mode_type transmission_mode; /*!< transmission mode selection */
|
||||
spi_master_slave_mode_type master_slave_mode; /*!< master or slave mode selection */
|
||||
spi_mclk_freq_div_type mclk_freq_division; /*!< master clock frequency division selection */
|
||||
spi_first_bit_type first_bit_transmission;/*!< transmit lsb or msb selection */
|
||||
spi_frame_bit_num_type frame_bit_num; /*!< frame bit num 8 or 16 bit selection */
|
||||
spi_clock_polarity_type clock_polarity; /*!< clock polarity selection */
|
||||
spi_clock_phase_type clock_phase; /*!< clock phase selection */
|
||||
spi_cs_mode_type cs_mode_selection; /*!< hardware or software cs mode selection */
|
||||
} spi_init_type;
|
||||
|
||||
/**
|
||||
* @brief i2s init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
i2s_operation_mode_type operation_mode; /*!< operation mode selection */
|
||||
i2s_audio_protocol_type audio_protocol; /*!< audio protocol selection */
|
||||
i2s_audio_sampling_freq_type audio_sampling_freq; /*!< audio frequency selection */
|
||||
i2s_data_channel_format_type data_channel_format; /*!< data bit num and channel bit num selection */
|
||||
i2s_clock_polarity_type clock_polarity; /*!< clock polarity selection */
|
||||
confirm_state mclk_output_enable; /*!< mclk_output selection */
|
||||
} i2s_init_type;
|
||||
|
||||
/**
|
||||
* @brief type define spi register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief spi ctrl1 register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t clkpha : 1; /* [0] */
|
||||
__IO uint32_t clkpol : 1; /* [1] */
|
||||
__IO uint32_t msten : 1; /* [2] */
|
||||
__IO uint32_t mdiv_l : 3; /* [5:3] */
|
||||
__IO uint32_t spien : 1; /* [6] */
|
||||
__IO uint32_t ltf : 1; /* [7] */
|
||||
__IO uint32_t swcsil : 1; /* [8] */
|
||||
__IO uint32_t swcsen : 1; /* [9] */
|
||||
__IO uint32_t ora : 1; /* [10] */
|
||||
__IO uint32_t fbn : 1; /* [11] */
|
||||
__IO uint32_t ntc : 1; /* [12] */
|
||||
__IO uint32_t ccen : 1; /* [13] */
|
||||
__IO uint32_t slbtd : 1; /* [14] */
|
||||
__IO uint32_t slben : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi ctrl2 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dmaren : 1; /* [0] */
|
||||
__IO uint32_t dmaten : 1; /* [1] */
|
||||
__IO uint32_t hwcsoe : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 1; /* [3] */
|
||||
__IO uint32_t tien : 1; /* [4] */
|
||||
__IO uint32_t errie : 1; /* [5] */
|
||||
__IO uint32_t rdbfie : 1; /* [6] */
|
||||
__IO uint32_t tdbeie : 1; /* [7] */
|
||||
__IO uint32_t mdiv_h : 1; /* [8] */
|
||||
__IO uint32_t mdiv3en : 1; /* [9] */
|
||||
__IO uint32_t reserved2 : 22;/* [31:10] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi sts register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rdbf : 1; /* [0] */
|
||||
__IO uint32_t tdbe : 1; /* [1] */
|
||||
__IO uint32_t acs : 1; /* [2] */
|
||||
__IO uint32_t tuerr : 1; /* [3] */
|
||||
__IO uint32_t ccerr : 1; /* [4] */
|
||||
__IO uint32_t mmerr : 1; /* [5] */
|
||||
__IO uint32_t roerr : 1; /* [6] */
|
||||
__IO uint32_t bf : 1; /* [7] */
|
||||
__IO uint32_t cspas : 1; /* [8] */
|
||||
__IO uint32_t reserved1 : 23;/* [31:9] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi dt register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi cpoly register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cpoly;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cpoly : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} cpoly_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi rcrc register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rcrc;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rcrc : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} rcrc_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi tcrc register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t tcrc;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tcrc : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} tcrc_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi i2sctrl register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t i2sctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t i2scbn : 1; /* [0] */
|
||||
__IO uint32_t i2sdbn : 2; /* [2:1] */
|
||||
__IO uint32_t i2sclkpol : 1; /* [3] */
|
||||
__IO uint32_t stdsel : 2; /* [5:4] */
|
||||
__IO uint32_t reserved1 : 1; /* [6] */
|
||||
__IO uint32_t pcmfssel : 1; /* [7] */
|
||||
__IO uint32_t opersel : 2; /* [9:8] */
|
||||
__IO uint32_t i2sen : 1; /* [10] */
|
||||
__IO uint32_t i2smsel : 1; /* [11] */
|
||||
__IO uint32_t reserved2 : 20;/* [31:12] */
|
||||
} i2sctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi i2sclk register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t i2sclk;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t i2sdiv_l : 8; /* [7:0] */
|
||||
__IO uint32_t i2sodd : 1; /* [8] */
|
||||
__IO uint32_t i2smclkoe : 1; /* [9] */
|
||||
__IO uint32_t i2sdiv_h : 2; /* [11:10] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} i2sclk_bit;
|
||||
};
|
||||
|
||||
} spi_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define SPI1 ((spi_type *) SPI1_BASE)
|
||||
#define SPI2 ((spi_type *) SPI2_BASE)
|
||||
#define SPI3 ((spi_type *) SPI3_BASE)
|
||||
#define SPI4 ((spi_type *) SPI4_BASE)
|
||||
#define I2S2EXT ((spi_type *) I2S2EXT_BASE)
|
||||
#define I2S3EXT ((spi_type *) I2S3EXT_BASE)
|
||||
|
||||
/** @defgroup SPI_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void spi_i2s_reset(spi_type *spi_x);
|
||||
void spi_default_para_init(spi_init_type* spi_init_struct);
|
||||
void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct);
|
||||
void spi_ti_mode_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void spi_crc_next_transmit(spi_type* spi_x);
|
||||
void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly);
|
||||
uint16_t spi_crc_polynomial_get(spi_type* spi_x);
|
||||
void spi_crc_enable(spi_type* spi_x, confirm_state new_state);
|
||||
uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction);
|
||||
void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level);
|
||||
void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num);
|
||||
void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction);
|
||||
void spi_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void i2s_default_para_init(i2s_init_type* i2s_init_struct);
|
||||
void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct);
|
||||
void i2s_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state);
|
||||
void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data);
|
||||
uint16_t spi_i2s_data_receive(spi_type* spi_x);
|
||||
flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
|
||||
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,412 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_usart.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 usart header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_USART_H
|
||||
#define __AT32F435_437_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USART_flags_definition
|
||||
* @brief usart flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_PERR_FLAG ((uint32_t)0x00000001) /*!< usart parity error flag */
|
||||
#define USART_FERR_FLAG ((uint32_t)0x00000002) /*!< usart framing error flag */
|
||||
#define USART_NERR_FLAG ((uint32_t)0x00000004) /*!< usart noise error flag */
|
||||
#define USART_ROERR_FLAG ((uint32_t)0x00000008) /*!< usart receiver overflow error flag */
|
||||
#define USART_IDLEF_FLAG ((uint32_t)0x00000010) /*!< usart idle flag */
|
||||
#define USART_RDBF_FLAG ((uint32_t)0x00000020) /*!< usart receive data buffer full flag */
|
||||
#define USART_TDC_FLAG ((uint32_t)0x00000040) /*!< usart transmit data complete flag */
|
||||
#define USART_TDBE_FLAG ((uint32_t)0x00000080) /*!< usart transmit data buffer empty flag */
|
||||
#define USART_BFF_FLAG ((uint32_t)0x00000100) /*!< usart break frame flag */
|
||||
#define USART_CTSCF_FLAG ((uint32_t)0x00000200) /*!< usart cts change flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_interrupts_definition
|
||||
* @brief usart interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IDLE_INT MAKE_VALUE(0x0C,0x04) /*!< usart idle interrupt */
|
||||
#define USART_RDBF_INT MAKE_VALUE(0x0C,0x05) /*!< usart receive data buffer full interrupt */
|
||||
#define USART_TDC_INT MAKE_VALUE(0x0C,0x06) /*!< usart transmit data complete interrupt */
|
||||
#define USART_TDBE_INT MAKE_VALUE(0x0C,0x07) /*!< usart transmit data buffer empty interrupt */
|
||||
#define USART_PERR_INT MAKE_VALUE(0x0C,0x08) /*!< usart parity error interrupt */
|
||||
#define USART_BF_INT MAKE_VALUE(0x10,0x06) /*!< usart break frame interrupt */
|
||||
#define USART_ERR_INT MAKE_VALUE(0x14,0x00) /*!< usart error interrupt */
|
||||
#define USART_CTSCF_INT MAKE_VALUE(0x14,0x0A) /*!< usart cts change interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief usart parity selection type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_PARITY_NONE = 0x00, /*!< usart no parity */
|
||||
USART_PARITY_EVEN = 0x01, /*!< usart even parity */
|
||||
USART_PARITY_ODD = 0x02 /*!< usart odd parity */
|
||||
} usart_parity_selection_type;
|
||||
|
||||
/**
|
||||
* @brief usart wakeup mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_WAKEUP_BY_IDLE_FRAME = 0x00, /*!< usart wakeup by idle frame */
|
||||
USART_WAKEUP_BY_MATCHING_ID = 0x01 /*!< usart wakeup by matching id */
|
||||
} usart_wakeup_mode_type;
|
||||
|
||||
/**
|
||||
* @brief usart data bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_DATA_7BITS = 0x00, /*!< usart data size is 7 bits */
|
||||
USART_DATA_8BITS = 0x01, /*!< usart data size is 8 bits */
|
||||
USART_DATA_9BITS = 0x02 /*!< usart data size is 9 bits */
|
||||
} usart_data_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief usart break frame bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_BREAK_10BITS = 0x00, /*!< usart lin mode berak frame detection 10 bits */
|
||||
USART_BREAK_11BITS = 0x01 /*!< usart lin mode berak frame detection 11 bits */
|
||||
} usart_break_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief usart phase of the clock type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_CLOCK_PHASE_1EDGE = 0x00, /*!< usart data capture is done on the clock leading edge */
|
||||
USART_CLOCK_PHASE_2EDGE = 0x01 /*!< usart data capture is done on the clock trailing edge */
|
||||
} usart_clock_phase_type;
|
||||
|
||||
/**
|
||||
* @brief usart polarity of the clock type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_CLOCK_POLARITY_LOW = 0x00, /*!< usart clock stay low level outside transmission window */
|
||||
USART_CLOCK_POLARITY_HIGH = 0x01 /*!< usart clock stay high level outside transmission window */
|
||||
} usart_clock_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief usart last bit clock pulse type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_CLOCK_LAST_BIT_NONE = 0x00, /*!< usart clock pulse of the last data bit is not outputted */
|
||||
USART_CLOCK_LAST_BIT_OUTPUT = 0x01 /*!< usart clock pulse of the last data bit is outputted */
|
||||
} usart_lbcp_type;
|
||||
|
||||
/**
|
||||
* @brief usart stop bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_STOP_1_BIT = 0x00, /*!< usart stop bits num is 1 */
|
||||
USART_STOP_0_5_BIT = 0x01, /*!< usart stop bits num is 0.5 */
|
||||
USART_STOP_2_BIT = 0x02, /*!< usart stop bits num is 2 */
|
||||
USART_STOP_1_5_BIT = 0x03 /*!< usart stop bits num is 1.5 */
|
||||
} usart_stop_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief usart hardware flow control type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_HARDWARE_FLOW_NONE = 0x00, /*!< usart without hardware flow */
|
||||
USART_HARDWARE_FLOW_RTS = 0x01, /*!< usart hardware flow only rts */
|
||||
USART_HARDWARE_FLOW_CTS = 0x02, /*!< usart hardware flow only cts */
|
||||
USART_HARDWARE_FLOW_RTS_CTS = 0x03 /*!< usart hardware flow both rts and cts */
|
||||
} usart_hardware_flow_control_type;
|
||||
|
||||
/**
|
||||
* @brief usart identification bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_ID_FIXED_4_BIT = 0x00, /*!< usart id bit num fixed 4 bits */
|
||||
USART_ID_RELATED_DATA_BIT = 0x01 /*!< usart id bit num related data bits */
|
||||
} usart_identification_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief usart de polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_DE_POLARITY_HIGH = 0x00, /*!< usart de polarity high */
|
||||
USART_DE_POLARITY_LOW = 0x01 /*!< usart de polarity low */
|
||||
} usart_de_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief type define usart register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief usart sts register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t perr : 1; /* [0] */
|
||||
__IO uint32_t ferr : 1; /* [1] */
|
||||
__IO uint32_t nerr : 1; /* [2] */
|
||||
__IO uint32_t roerr : 1; /* [3] */
|
||||
__IO uint32_t idlef : 1; /* [4] */
|
||||
__IO uint32_t rdbf : 1; /* [5] */
|
||||
__IO uint32_t tdc : 1; /* [6] */
|
||||
__IO uint32_t tdbe : 1; /* [7] */
|
||||
__IO uint32_t bff : 1; /* [8] */
|
||||
__IO uint32_t ctscf : 1; /* [9] */
|
||||
__IO uint32_t reserved1 : 22;/* [31:10] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart dt register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 9; /* [8:0] */
|
||||
__IO uint32_t reserved1 : 23;/* [31:9] */
|
||||
} dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart baudr register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t baudr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t div : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} baudr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart ctrl1 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t sbf : 1; /* [0] */
|
||||
__IO uint32_t rm : 1; /* [1] */
|
||||
__IO uint32_t ren : 1; /* [2] */
|
||||
__IO uint32_t ten : 1; /* [3] */
|
||||
__IO uint32_t idleien : 1; /* [4] */
|
||||
__IO uint32_t rdbfien : 1; /* [5] */
|
||||
__IO uint32_t tdcien : 1; /* [6] */
|
||||
__IO uint32_t tdbeien : 1; /* [7] */
|
||||
__IO uint32_t perrien : 1; /* [8] */
|
||||
__IO uint32_t psel : 1; /* [9] */
|
||||
__IO uint32_t pen : 1; /* [10] */
|
||||
__IO uint32_t wum : 1; /* [11] */
|
||||
__IO uint32_t dbn_l : 1; /* [12] */
|
||||
__IO uint32_t uen : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 2; /* [15:14] */
|
||||
__IO uint32_t tcdt : 5; /* [20:16] */
|
||||
__IO uint32_t tsdt : 5; /* [25:21] */
|
||||
__IO uint32_t reserved2 : 2; /* [27:26] */
|
||||
__IO uint32_t dbn_h : 1; /* [28] */
|
||||
__IO uint32_t reserved3 : 3; /* [31:29] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart ctrl2 register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t id_l : 4; /* [3:0] */
|
||||
__IO uint32_t idbn : 1; /* [4] */
|
||||
__IO uint32_t bfbn : 1; /* [5] */
|
||||
__IO uint32_t bfien : 1; /* [6] */
|
||||
__IO uint32_t reserved1 : 1; /* [7] */
|
||||
__IO uint32_t lbcp : 1; /* [8] */
|
||||
__IO uint32_t clkpha : 1; /* [9] */
|
||||
__IO uint32_t clkpol : 1; /* [10] */
|
||||
__IO uint32_t clken : 1; /* [11] */
|
||||
__IO uint32_t stopbn : 2; /* [13:12] */
|
||||
__IO uint32_t linen : 1; /* [14] */
|
||||
__IO uint32_t trpswap : 1; /* [15] */
|
||||
__IO uint32_t reserved2 : 12;/* [27:16] */
|
||||
__IO uint32_t id_h : 4; /* [31:28] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart ctrl3 register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t errien : 1; /* [0] */
|
||||
__IO uint32_t irdaen : 1; /* [1] */
|
||||
__IO uint32_t irdalp : 1; /* [2] */
|
||||
__IO uint32_t slben : 1; /* [3] */
|
||||
__IO uint32_t scnacken : 1; /* [4] */
|
||||
__IO uint32_t scmen : 1; /* [5] */
|
||||
__IO uint32_t dmaren : 1; /* [6] */
|
||||
__IO uint32_t dmaten : 1; /* [7] */
|
||||
__IO uint32_t rtsen : 1; /* [8] */
|
||||
__IO uint32_t ctsen : 1; /* [9] */
|
||||
__IO uint32_t ctscfien : 1; /* [10] */
|
||||
__IO uint32_t reserved1 : 3; /* [13:11] */
|
||||
__IO uint32_t rs485en : 1; /* [14] */
|
||||
__IO uint32_t dep : 1; /* [15] */
|
||||
__IO uint32_t reserved2 : 16;/* [31:16] */
|
||||
} ctrl3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart gdiv register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t gdiv;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t isdiv : 8; /* [7:0] */
|
||||
__IO uint32_t scgt : 8; /* [15:8] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} gdiv_bit;
|
||||
};
|
||||
} usart_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define USART1 ((usart_type *) USART1_BASE)
|
||||
#define USART2 ((usart_type *) USART2_BASE)
|
||||
#define USART3 ((usart_type *) USART3_BASE)
|
||||
#define UART4 ((usart_type *) UART4_BASE)
|
||||
#define UART5 ((usart_type *) UART5_BASE)
|
||||
#define USART6 ((usart_type *) USART6_BASE)
|
||||
#define UART7 ((usart_type *) UART7_BASE)
|
||||
#define UART8 ((usart_type *) UART8_BASE)
|
||||
|
||||
/** @defgroup USART_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void usart_reset(usart_type* usart_x);
|
||||
void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit);
|
||||
void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity);
|
||||
void usart_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_receiver_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb);
|
||||
void usart_clock_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state);
|
||||
void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id);
|
||||
void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode);
|
||||
void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit);
|
||||
void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_data_transmit(usart_type* usart_x, uint16_t data);
|
||||
uint16_t usart_data_receive(usart_type* usart_x);
|
||||
void usart_break_send(usart_type* usart_x);
|
||||
void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val);
|
||||
void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val);
|
||||
void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state);
|
||||
flag_status usart_flag_get(usart_type* usart_x, uint32_t flag);
|
||||
void usart_flag_clear(usart_type* usart_x, uint32_t flag);
|
||||
void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time);
|
||||
void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type id_bit_num);
|
||||
void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity);
|
||||
void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,197 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_wdt.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 wdt header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_WDT_H
|
||||
#define __AT32F435_437_WDT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WDT
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup WDT_flags_definition
|
||||
* @brief wdt flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define WDT_DIVF_UPDATE_FLAG ((uint16_t)0x0001) /*!< wdt division value update complete flag */
|
||||
#define WDT_RLDF_UPDATE_FLAG ((uint16_t)0x0002) /*!< wdt reload value update complete flag */
|
||||
#define WDT_WINF_UPDATE_FLAG ((uint16_t)0x0004) /*!< wdt window value update complete flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WDT_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief wdt division value type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
WDT_CLK_DIV_4 = 0x00, /*!< wdt clock divider value is 4 */
|
||||
WDT_CLK_DIV_8 = 0x01, /*!< wdt clock divider value is 8 */
|
||||
WDT_CLK_DIV_16 = 0x02, /*!< wdt clock divider value is 16 */
|
||||
WDT_CLK_DIV_32 = 0x03, /*!< wdt clock divider value is 32 */
|
||||
WDT_CLK_DIV_64 = 0x04, /*!< wdt clock divider value is 64 */
|
||||
WDT_CLK_DIV_128 = 0x05, /*!< wdt clock divider value is 128 */
|
||||
WDT_CLK_DIV_256 = 0x06 /*!< wdt clock divider value is 256 */
|
||||
} wdt_division_type;
|
||||
|
||||
/**
|
||||
* @brief wdt cmd value type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
WDT_CMD_LOCK = 0x0000, /*!< disable write protection command */
|
||||
WDT_CMD_UNLOCK = 0x5555, /*!< enable write protection command */
|
||||
WDT_CMD_ENABLE = 0xCCCC, /*!< enable wdt command */
|
||||
WDT_CMD_RELOAD = 0xAAAA /*!< reload command */
|
||||
} wdt_cmd_value_type;
|
||||
|
||||
/**
|
||||
* @brief type define wdt register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief wdt cmd register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cmd;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmd : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} cmd_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wdt div register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t div;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t div : 3; /* [2:0] */
|
||||
__IO uint32_t reserved1 : 29;/* [31:3] */
|
||||
} div_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wdt rld register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rld;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rld : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} rld_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wdt sts register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t divf : 1; /* [0] */
|
||||
__IO uint32_t rldf : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 30;/* [31:2] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wdt win register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t win;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t win : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} win_bit;
|
||||
};
|
||||
} wdt_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define WDT ((wdt_type *) WDT_BASE)
|
||||
|
||||
/** @defgroup WDT_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void wdt_enable(void);
|
||||
void wdt_counter_reload(void);
|
||||
void wdt_reload_value_set(uint16_t reload_value);
|
||||
void wdt_divider_set(wdt_division_type division);
|
||||
void wdt_register_write_enable( confirm_state new_state);
|
||||
flag_status wdt_flag_get(uint16_t wdt_flag);
|
||||
void wdt_window_counter_set(uint16_t window_cnt);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,158 +0,0 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_wwdt.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 wwdt header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_WWDT_H
|
||||
#define __AT32F435_437_WWDT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDT_enable_bit_definition
|
||||
* @brief wwdt enable bit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define WWDT_EN_BIT ((uint32_t)0x00000080) /*!< wwdt enable bit */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDT_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief wwdt division type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
WWDT_PCLK1_DIV_4096 = 0x00, /*!< wwdt counter clock = (pclk1/4096)/1) */
|
||||
WWDT_PCLK1_DIV_8192 = 0x01, /*!< wwdt counter clock = (pclk1/4096)/2) */
|
||||
WWDT_PCLK1_DIV_16384 = 0x02, /*!< wwdt counter clock = (pclk1/4096)/4) */
|
||||
WWDT_PCLK1_DIV_32768 = 0x03 /*!< wwdt counter clock = (pclk1/4096)/8) */
|
||||
} wwdt_division_type;
|
||||
|
||||
/**
|
||||
* @brief type define wwdt register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief wwdt ctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cnt : 7; /* [6:0] */
|
||||
__IO uint32_t wwdten : 1; /* [7] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wwdt cfg register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cfg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t win : 7; /* [6:0] */
|
||||
__IO uint32_t div : 2; /* [8:7] */
|
||||
__IO uint32_t rldien : 1; /* [9] */
|
||||
__IO uint32_t reserved1 : 22;/* [31:10] */
|
||||
} cfg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wwdt cfg register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rldf : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 31;/* [31:1] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
} wwdt_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define WWDT ((wwdt_type *) WWDT_BASE)
|
||||
|
||||
/** @defgroup WWDT_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void wwdt_reset(void);
|
||||
void wwdt_divider_set(wwdt_division_type division);
|
||||
void wwdt_flag_clear(void);
|
||||
void wwdt_enable(uint8_t wwdt_cnt);
|
||||
void wwdt_interrupt_enable(void);
|
||||
flag_status wwdt_flag_get(void);
|
||||
void wwdt_counter_set(uint8_t wwdt_cnt);
|
||||
void wwdt_window_counter_set(uint8_t window_cnt);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,375 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_board.c
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief set of firmware functions to manage leds and push-button.
|
||||
* initialize delay function.
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#include "at32f435_437_board.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_board
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BOARD
|
||||
* @brief onboard periph driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* delay macros */
|
||||
#define STEP_DELAY_MS 50
|
||||
|
||||
/* at-start led resouce array */
|
||||
gpio_type *led_gpio_port[LED_NUM] = {LED2_GPIO, LED3_GPIO, LED4_GPIO};
|
||||
uint16_t led_gpio_pin[LED_NUM] = {LED2_PIN, LED3_PIN, LED4_PIN};
|
||||
crm_periph_clock_type led_gpio_crm_clk[LED_NUM] = {LED2_GPIO_CRM_CLK, LED3_GPIO_CRM_CLK, LED4_GPIO_CRM_CLK};
|
||||
|
||||
/* delay variable */
|
||||
static __IO uint32_t fac_us;
|
||||
static __IO uint32_t fac_ms;
|
||||
|
||||
/* support printf function, usemicrolib is unnecessary */
|
||||
#if (__ARMCC_VERSION > 6000000)
|
||||
__asm (".global __use_no_semihosting\n\t");
|
||||
void _sys_exit(int x)
|
||||
{
|
||||
x = x;
|
||||
}
|
||||
/* __use_no_semihosting was requested, but _ttywrch was */
|
||||
void _ttywrch(int ch)
|
||||
{
|
||||
ch = ch;
|
||||
}
|
||||
FILE __stdout;
|
||||
#else
|
||||
#ifdef __CC_ARM
|
||||
#pragma import(__use_no_semihosting)
|
||||
struct __FILE
|
||||
{
|
||||
int handle;
|
||||
};
|
||||
FILE __stdout;
|
||||
void _sys_exit(int x)
|
||||
{
|
||||
x = x;
|
||||
}
|
||||
/* __use_no_semihosting was requested, but _ttywrch was */
|
||||
void _ttywrch(int ch)
|
||||
{
|
||||
ch = ch;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) && !defined (__clang__)
|
||||
#define PUTCHAR_PROTOTYPE int __io_putchar(int ch)
|
||||
#else
|
||||
#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief retargets the c library printf function to the usart.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
PUTCHAR_PROTOTYPE
|
||||
{
|
||||
while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET);
|
||||
usart_data_transmit(PRINT_UART, ch);
|
||||
return ch;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief initialize uart
|
||||
* @param baudrate: uart baudrate
|
||||
* @retval none
|
||||
*/
|
||||
void uart_print_init(uint32_t baudrate)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
|
||||
/* enable the uart and gpio clock */
|
||||
crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE);
|
||||
crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE);
|
||||
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
|
||||
/* configure the uart tx pin */
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(PRINT_UART_TX_GPIO, PRINT_UART_TX_PIN_SOURCE, PRINT_UART_TX_PIN_MUX_NUM);
|
||||
|
||||
/* configure uart param */
|
||||
usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT);
|
||||
usart_transmitter_enable(PRINT_UART, TRUE);
|
||||
usart_enable(PRINT_UART, TRUE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief board initialize interface init led and button
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void at32_board_init()
|
||||
{
|
||||
/* initialize delay function */
|
||||
delay_init();
|
||||
|
||||
/* configure led in at_start_board */
|
||||
at32_led_init(LED2);
|
||||
at32_led_init(LED3);
|
||||
at32_led_init(LED4);
|
||||
at32_led_off(LED2);
|
||||
at32_led_off(LED3);
|
||||
at32_led_off(LED4);
|
||||
|
||||
/* configure button in at_start board */
|
||||
at32_button_init();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief configure button gpio
|
||||
* @param button: specifies the button to be configured.
|
||||
* @retval none
|
||||
*/
|
||||
void at32_button_init(void)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
|
||||
/* enable the button clock */
|
||||
crm_periph_clock_enable(USER_BUTTON_CRM_CLK, TRUE);
|
||||
|
||||
/* set default parameter */
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
|
||||
/* configure button pin as input with pull-up/pull-down */
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
|
||||
gpio_init_struct.gpio_pins = USER_BUTTON_PIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_DOWN;
|
||||
gpio_init(USER_BUTTON_PORT, &gpio_init_struct);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief returns the selected button state
|
||||
* @param none
|
||||
* @retval the button gpio pin value
|
||||
*/
|
||||
uint8_t at32_button_state(void)
|
||||
{
|
||||
return gpio_input_data_bit_read(USER_BUTTON_PORT, USER_BUTTON_PIN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief returns which button have press down
|
||||
* @param none
|
||||
* @retval the button have press down
|
||||
*/
|
||||
button_type at32_button_press()
|
||||
{
|
||||
static uint8_t pressed = 1;
|
||||
/* get button state in at_start board */
|
||||
if((pressed == 1) && (at32_button_state() != RESET))
|
||||
{
|
||||
/* debounce */
|
||||
pressed = 0;
|
||||
delay_ms(10);
|
||||
if(at32_button_state() != RESET)
|
||||
return USER_BUTTON;
|
||||
}
|
||||
else if(at32_button_state() == RESET)
|
||||
{
|
||||
pressed = 1;
|
||||
}
|
||||
return NO_BUTTON;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief configure led gpio
|
||||
* @param led: specifies the led to be configured.
|
||||
* @retval none
|
||||
*/
|
||||
void at32_led_init(led_type led)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
|
||||
/* enable the led clock */
|
||||
crm_periph_clock_enable(led_gpio_crm_clk[led], TRUE);
|
||||
|
||||
/* set default parameter */
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
|
||||
/* configure the led gpio */
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
|
||||
gpio_init_struct.gpio_pins = led_gpio_pin[led];
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init(led_gpio_port[led], &gpio_init_struct);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief turns selected led on.
|
||||
* @param led: specifies the led to be set on.
|
||||
* this parameter can be one of following parameters:
|
||||
* @arg LED2
|
||||
* @arg LED3
|
||||
* @arg LED4
|
||||
* @retval none
|
||||
*/
|
||||
void at32_led_on(led_type led)
|
||||
{
|
||||
if(led > (LED_NUM - 1))
|
||||
return;
|
||||
if(led_gpio_pin[led])
|
||||
led_gpio_port[led]->clr = led_gpio_pin[led];
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief turns selected led off.
|
||||
* @param led: specifies the led to be set off.
|
||||
* this parameter can be one of following parameters:
|
||||
* @arg LED2
|
||||
* @arg LED3
|
||||
* @arg LED4
|
||||
* @retval none
|
||||
*/
|
||||
void at32_led_off(led_type led)
|
||||
{
|
||||
if(led > (LED_NUM - 1))
|
||||
return;
|
||||
if(led_gpio_pin[led])
|
||||
led_gpio_port[led]->scr = led_gpio_pin[led];
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief turns selected led tooggle.
|
||||
* @param led: specifies the led to be set off.
|
||||
* this parameter can be one of following parameters:
|
||||
* @arg LED2
|
||||
* @arg LED3
|
||||
* @arg LED4
|
||||
* @retval none
|
||||
*/
|
||||
void at32_led_toggle(led_type led)
|
||||
{
|
||||
if(led > (LED_NUM - 1))
|
||||
return;
|
||||
if(led_gpio_pin[led])
|
||||
led_gpio_port[led]->odt ^= led_gpio_pin[led];
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief initialize delay function
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void delay_init()
|
||||
{
|
||||
/* configure systick */
|
||||
systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV);
|
||||
fac_us = system_core_clock / (1000000U);
|
||||
fac_ms = fac_us * (1000U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief inserts a delay time.
|
||||
* @param nus: specifies the delay time length, in microsecond.
|
||||
* @retval none
|
||||
*/
|
||||
void delay_us(uint32_t nus)
|
||||
{
|
||||
uint32_t temp = 0;
|
||||
SysTick->LOAD = (uint32_t)(nus * fac_us);
|
||||
SysTick->VAL = 0x00;
|
||||
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk ;
|
||||
do
|
||||
{
|
||||
temp = SysTick->CTRL;
|
||||
}while((temp & 0x01) && !(temp & (1 << 16)));
|
||||
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
SysTick->VAL = 0x00;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief inserts a delay time.
|
||||
* @param nms: specifies the delay time length, in milliseconds.
|
||||
* @retval none
|
||||
*/
|
||||
void delay_ms(uint16_t nms)
|
||||
{
|
||||
uint32_t temp = 0;
|
||||
while(nms)
|
||||
{
|
||||
if(nms > STEP_DELAY_MS)
|
||||
{
|
||||
SysTick->LOAD = (uint32_t)(STEP_DELAY_MS * fac_ms);
|
||||
nms -= STEP_DELAY_MS;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->LOAD = (uint32_t)(nms * fac_ms);
|
||||
nms = 0;
|
||||
}
|
||||
SysTick->VAL = 0x00;
|
||||
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
|
||||
do
|
||||
{
|
||||
temp = SysTick->CTRL;
|
||||
}while((temp & 0x01) && !(temp & (1 << 16)));
|
||||
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
SysTick->VAL = 0x00;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief inserts a delay time.
|
||||
* @param sec: specifies the delay time, in seconds.
|
||||
* @retval none
|
||||
*/
|
||||
void delay_sec(uint16_t sec)
|
||||
{
|
||||
uint16_t index;
|
||||
for(index = 0; index < sec; index++)
|
||||
{
|
||||
delay_ms(500);
|
||||
delay_ms(500);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -0,0 +1,154 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_board.c
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief header file for at-start board. set of firmware functions to
|
||||
* manage leds and push-button. initialize delay function.
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __AT32F435_437_BOARD_H
|
||||
#define __AT32F435_437_BOARD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "stdio.h"
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_board
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup BOARD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BOARD_pins_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* this header include define support list:
|
||||
* 1. at-start-f435 v1.x board
|
||||
* 2. at-start-f437 v1.x board
|
||||
* if define AT_START_F435_V1, the header file support at-start-f437 v1.x board
|
||||
* if define AT_START_F437_V1, the header file support at-start-f437 v1.x board
|
||||
*/
|
||||
|
||||
#if !defined (AT_START_F435_V1) && !defined (AT_START_F437_V1)
|
||||
#error "please select first the board at-start device used in your application (in at32f435_437_board.h file)"
|
||||
#endif
|
||||
|
||||
/******************** define led ********************/
|
||||
typedef enum
|
||||
{
|
||||
LED2 = 0,
|
||||
LED3 = 1,
|
||||
LED4 = 2
|
||||
}led_type;
|
||||
|
||||
#define LED_NUM 3
|
||||
|
||||
#if defined (AT_START_F435_V1) || defined (AT_START_F437_V1)
|
||||
#define LED2_PIN GPIO_PINS_13
|
||||
#define LED2_GPIO GPIOD
|
||||
#define LED2_GPIO_CRM_CLK CRM_GPIOD_PERIPH_CLOCK
|
||||
|
||||
#define LED3_PIN GPIO_PINS_14
|
||||
#define LED3_GPIO GPIOD
|
||||
#define LED3_GPIO_CRM_CLK CRM_GPIOD_PERIPH_CLOCK
|
||||
|
||||
#define LED4_PIN GPIO_PINS_15
|
||||
#define LED4_GPIO GPIOD
|
||||
#define LED4_GPIO_CRM_CLK CRM_GPIOD_PERIPH_CLOCK
|
||||
#endif
|
||||
|
||||
/**************** define print uart ******************/
|
||||
#define PRINT_UART USART1
|
||||
#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK
|
||||
#define PRINT_UART_TX_PIN GPIO_PINS_9
|
||||
#define PRINT_UART_TX_GPIO GPIOA
|
||||
#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK
|
||||
#define PRINT_UART_TX_PIN_SOURCE GPIO_PINS_SOURCE9
|
||||
#define PRINT_UART_TX_PIN_MUX_NUM GPIO_MUX_7
|
||||
|
||||
/******************* define button *******************/
|
||||
typedef enum
|
||||
{
|
||||
USER_BUTTON = 0,
|
||||
NO_BUTTON = 1
|
||||
} button_type;
|
||||
|
||||
#define USER_BUTTON_PIN GPIO_PINS_0
|
||||
#define USER_BUTTON_PORT GPIOA
|
||||
#define USER_BUTTON_CRM_CLK CRM_GPIOA_PERIPH_CLOCK
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BOARD_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/******************** functions ********************/
|
||||
void at32_board_init(void);
|
||||
|
||||
/* led operation function */
|
||||
void at32_led_init(led_type led);
|
||||
void at32_led_on(led_type led);
|
||||
void at32_led_off(led_type led);
|
||||
void at32_led_toggle(led_type led);
|
||||
|
||||
/* button operation function */
|
||||
void at32_button_init(void);
|
||||
button_type at32_button_press(void);
|
||||
uint8_t at32_button_state(void);
|
||||
|
||||
/* delay function */
|
||||
void delay_init(void);
|
||||
void delay_us(uint32_t nus);
|
||||
void delay_ms(uint16_t nms);
|
||||
void delay_sec(uint16_t sec);
|
||||
|
||||
/* printf uart init function */
|
||||
void uart_print_init(uint32_t baudrate);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,136 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file usb_core.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief usb core header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_CORE_H
|
||||
#define __USB_CORE_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#include "usb_std.h"
|
||||
#include "usb_conf.h"
|
||||
|
||||
#ifdef USE_OTG_DEVICE_MODE
|
||||
#include "usbd_core.h"
|
||||
#endif
|
||||
#ifdef USE_OTG_HOST_MODE
|
||||
#include "usbh_core.h"
|
||||
#endif
|
||||
|
||||
/** @addtogroup AT32F435_437_middlewares_usb_drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USB_drivers_core
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_core_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief usb core speed select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USB_LOW_SPEED_CORE_ID, /*!< usb low speed core id */
|
||||
USB_FULL_SPEED_CORE_ID, /*!< usb full speed core id */
|
||||
USB_HIGH_SPEED_CORE_ID, /*!< usb high speed core id */
|
||||
} usb_speed_type;
|
||||
|
||||
/**
|
||||
* @brief usb core cofig struct
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t speed; /*!< otg speed */
|
||||
uint8_t dma_en; /*!< dma enable state, not use*/
|
||||
uint8_t hc_num; /*!< the otg host support number of channel */
|
||||
uint8_t ept_num; /*!< the otg device support number of endpoint */
|
||||
|
||||
uint16_t max_size; /*!< support max packet size */
|
||||
uint16_t fifo_size; /*!< the usb otg total file size */
|
||||
uint8_t phy_itface; /*!< usb phy select */
|
||||
uint8_t core_id; /*!< the usb otg core id */
|
||||
uint8_t low_power; /*!< the usb otg low power option */
|
||||
uint8_t sof_out; /*!< the sof signal output */
|
||||
uint8_t usb_id; /*!< select otgfs1 or otgfs2 */
|
||||
uint8_t vbusig; /*!< vbus ignore */
|
||||
} usb_core_cfg;
|
||||
|
||||
/**
|
||||
* @brief usb otg core struct type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
usb_reg_type *usb_reg; /*!< the usb otg register type */
|
||||
#ifdef USE_OTG_DEVICE_MODE
|
||||
usbd_core_type dev; /*!< the usb device core type */
|
||||
#endif
|
||||
|
||||
#ifdef USE_OTG_HOST_MODE
|
||||
usbh_core_type host; /*!< the usb host core type */
|
||||
#endif
|
||||
|
||||
usb_core_cfg cfg; /*!< the usb otg core config type */
|
||||
|
||||
} otg_core_type;
|
||||
|
||||
usb_sts_type usb_core_config(otg_core_type *otgdev, uint8_t core_id);
|
||||
#ifdef USE_OTG_DEVICE_MODE
|
||||
usb_sts_type usbd_init(otg_core_type *udev,
|
||||
uint8_t core_id, uint8_t usb_id,
|
||||
usbd_class_handler *class_handler,
|
||||
usbd_desc_handler *desc_handler);
|
||||
#endif
|
||||
|
||||
#ifdef USE_OTG_HOST_MODE
|
||||
usb_sts_type usbh_init(otg_core_type *hdev,
|
||||
uint8_t core_id, uint8_t usb_id,
|
||||
usbh_class_handler_type *class_handler,
|
||||
usbh_user_handler_type *user_handler);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,335 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file usb_std.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief usb standard header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_STD_H
|
||||
#define __USB_STD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "usb_conf.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_middlewares_usb_drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USB_standard
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_standard_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief usb request recipient
|
||||
*/
|
||||
#define USB_REQ_RECIPIENT_DEVICE 0x00 /*!< usb request recipient device */
|
||||
#define USB_REQ_RECIPIENT_INTERFACE 0x01 /*!< usb request recipient interface */
|
||||
#define USB_REQ_RECIPIENT_ENDPOINT 0x02 /*!< usb request recipient endpoint */
|
||||
#define USB_REQ_RECIPIENT_OTHER 0x03 /*!< usb request recipient other */
|
||||
#define USB_REQ_RECIPIENT_MASK 0x1F /*!< usb request recipient mask */
|
||||
|
||||
/**
|
||||
* @brief usb request type
|
||||
*/
|
||||
#define USB_REQ_TYPE_STANDARD 0x00 /*!< usb request type standard */
|
||||
#define USB_REQ_TYPE_CLASS 0x20 /*!< usb request type class */
|
||||
#define USB_REQ_TYPE_VENDOR 0x40 /*!< usb request type vendor */
|
||||
#define USB_REQ_TYPE_RESERVED 0x60 /*!< usb request type reserved */
|
||||
|
||||
/**
|
||||
* @brief usb request data transfer direction
|
||||
*/
|
||||
#define USB_REQ_DIR_HTD 0x00 /*!< usb request data transfer direction host to device */
|
||||
#define USB_REQ_DIR_DTH 0x80 /*!< usb request data transfer direction device to host */
|
||||
|
||||
/**
|
||||
* @brief usb standard device requests codes
|
||||
*/
|
||||
#define USB_STD_REQ_GET_STATUS 0 /*!< usb request code status */
|
||||
#define USB_STD_REQ_CLEAR_FEATURE 1 /*!< usb request code clear feature */
|
||||
#define USB_STD_REQ_SET_FEATURE 3 /*!< usb request code feature */
|
||||
#define USB_STD_REQ_SET_ADDRESS 5 /*!< usb request code address */
|
||||
#define USB_STD_REQ_GET_DESCRIPTOR 6 /*!< usb request code get descriptor */
|
||||
#define USB_STD_REQ_SET_DESCRIPTOR 7 /*!< usb request code set descriptor */
|
||||
#define USB_STD_REQ_GET_CONFIGURATION 8 /*!< usb request code get configuration */
|
||||
#define USB_STD_REQ_SET_CONFIGURATION 9 /*!< usb request code set configuration */
|
||||
#define USB_STD_REQ_GET_INTERFACE 10 /*!< usb request code get interface */
|
||||
#define USB_STD_REQ_SET_INTERFACE 11 /*!< usb request code set interface */
|
||||
#define USB_STD_REQ_SYNCH_FRAME 12 /*!< usb request code synch frame */
|
||||
|
||||
/**
|
||||
* @brief usb standard device type
|
||||
*/
|
||||
#define USB_DESCIPTOR_TYPE_DEVICE 1 /*!< usb standard device type device */
|
||||
#define USB_DESCIPTOR_TYPE_CONFIGURATION 2 /*!< usb standard device type configuration */
|
||||
#define USB_DESCIPTOR_TYPE_STRING 3 /*!< usb standard device type string */
|
||||
#define USB_DESCIPTOR_TYPE_INTERFACE 4 /*!< usb standard device type interface */
|
||||
#define USB_DESCIPTOR_TYPE_ENDPOINT 5 /*!< usb standard device type endpoint */
|
||||
#define USB_DESCIPTOR_TYPE_DEVICE_QUALIFIER 6 /*!< usb standard device type qualifier */
|
||||
#define USB_DESCIPTOR_TYPE_OTHER_SPEED 7 /*!< usb standard device type other speed */
|
||||
#define USB_DESCIPTOR_TYPE_INTERFACE_POWER 8 /*!< usb standard device type interface power */
|
||||
|
||||
/**
|
||||
* @brief usb standard string type
|
||||
*/
|
||||
#define USB_LANGID_STRING 0 /*!< usb standard string type lang id */
|
||||
#define USB_MFC_STRING 1 /*!< usb standard string type mfc */
|
||||
#define USB_PRODUCT_STRING 2 /*!< usb standard string type product */
|
||||
#define USB_SERIAL_STRING 3 /*!< usb standard string type serial */
|
||||
#define USB_CONFIG_STRING 4 /*!< usb standard string type config */
|
||||
#define USB_INTERFACE_STRING 5 /*!< usb standard string type interface */
|
||||
|
||||
/**
|
||||
* @brief usb configuration attributes
|
||||
*/
|
||||
#define USB_CONF_REMOTE_WAKEUP 2 /*!< usb configuration attributes remote wakeup */
|
||||
#define USB_CONF_SELF_POWERED 1 /*!< usb configuration attributes self powered */
|
||||
|
||||
/**
|
||||
* @brief usb standard feature selectors
|
||||
*/
|
||||
#define USB_FEATURE_EPT_HALT 0 /*!< usb standard feature selectors endpoint halt */
|
||||
#define USB_FEATURE_REMOTE_WAKEUP 1 /*!< usb standard feature selectors remote wakeup */
|
||||
#define USB_FEATURE_TEST_MODE 2 /*!< usb standard feature selectors test mode */
|
||||
|
||||
/**
|
||||
* @brief usb device connect state
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USB_CONN_STATE_DEFAULT =1, /*!< usb device connect state default */
|
||||
USB_CONN_STATE_ADDRESSED, /*!< usb device connect state address */
|
||||
USB_CONN_STATE_CONFIGURED, /*!< usb device connect state configured */
|
||||
USB_CONN_STATE_SUSPENDED /*!< usb device connect state suspend */
|
||||
}usbd_conn_state;
|
||||
|
||||
/**
|
||||
* @brief endpoint 0 state
|
||||
*/
|
||||
#define USB_EPT0_IDLE 0 /*!< usb endpoint state idle */
|
||||
#define USB_EPT0_SETUP 1 /*!< usb endpoint state setup */
|
||||
#define USB_EPT0_DATA_IN 2 /*!< usb endpoint state data in */
|
||||
#define USB_EPT0_DATA_OUT 3 /*!< usb endpoint state data out */
|
||||
#define USB_EPT0_STATUS_IN 4 /*!< usb endpoint state status in */
|
||||
#define USB_EPT0_STATUS_OUT 5 /*!< usb endpoint state status out */
|
||||
#define USB_EPT0_STALL 6 /*!< usb endpoint state stall */
|
||||
|
||||
/**
|
||||
* @brief usb descriptor length
|
||||
*/
|
||||
#define USB_DEVICE_QUALIFIER_DESC_LEN 0x0A /*!< usb qualifier descriptor length */
|
||||
#define USB_DEVICE_DESC_LEN 0x12 /*!< usb device descriptor length */
|
||||
#define USB_DEVICE_CFG_DESC_LEN 0x09 /*!< usb configuration descriptor length */
|
||||
#define USB_DEVICE_IF_DESC_LEN 0x09 /*!< usb interface descriptor length */
|
||||
#define USB_DEVICE_EPT_LEN 0x07 /*!< usb endpoint descriptor length */
|
||||
#define USB_DEVICE_OTG_DESC_LEN 0x03 /*!< usb otg descriptor length */
|
||||
#define USB_DEVICE_LANGID_STR_DESC_LEN 0x04 /*!< usb lang id string descriptor length */
|
||||
#define USB_DEVICE_OTHER_SPEED_DESC_SIZ_LEN 0x09 /*!< usb other speed descriptor length */
|
||||
|
||||
/**
|
||||
* @brief usb class code
|
||||
*/
|
||||
#define USB_CLASS_CODE_AUDIO 0x01 /*!< usb class code audio */
|
||||
#define USB_CLASS_CODE_CDC 0x02 /*!< usb class code cdc */
|
||||
#define USB_CLASS_CODE_HID 0x03 /*!< usb class code hid */
|
||||
#define USB_CLASS_CODE_PRINTER 0x07 /*!< usb class code printer */
|
||||
#define USB_CLASS_CODE_MSC 0x08 /*!< usb class code msc */
|
||||
#define USB_CLASS_CODE_HUB 0x09 /*!< usb class code hub */
|
||||
#define USB_CLASS_CODE_CDCDATA 0x0A /*!< usb class code cdc data */
|
||||
#define USB_CLASS_CODE_CCID 0x0B /*!< usb class code ccid */
|
||||
#define USB_CLASS_CODE_VIDEO 0x0E /*!< usb class code video */
|
||||
#define USB_CLASS_CODE_VENDOR 0xFF /*!< usb class code vendor */
|
||||
|
||||
/**
|
||||
* @brief usb endpoint type
|
||||
*/
|
||||
#define USB_EPT_DESC_CONTROL 0x00 /*!< usb endpoint description type control */
|
||||
#define USB_EPT_DESC_ISO 0x01 /*!< usb endpoint description type iso */
|
||||
#define USB_EPT_DESC_BULK 0x02 /*!< usb endpoint description type bulk */
|
||||
#define USB_EPT_DESC_INTERRUPT 0x03 /*!< usb endpoint description type interrupt */
|
||||
|
||||
#define USB_EPT_DESC_NSYNC 0x00 /*!< usb endpoint description nsync */
|
||||
#define USB_ETP_DESC_ASYNC 0x04 /*!< usb endpoint description async */
|
||||
#define USB_ETP_DESC_ADAPTIVE 0x08 /*!< usb endpoint description adaptive */
|
||||
#define USB_ETP_DESC_SYNC 0x0C /*!< usb endpoint description sync */
|
||||
|
||||
#define USB_EPT_DESC_DATA_EPT 0x00 /*!< usb endpoint description data */
|
||||
#define USB_EPT_DESC_FD_EPT 0x10 /*!< usb endpoint description fd */
|
||||
#define USB_EPT_DESC_FDDATA_EPT 0x20 /*!< usb endpoint description fddata */
|
||||
|
||||
/**
|
||||
* @brief endpoint 0 max size
|
||||
*/
|
||||
#define USB_MAX_EP0_SIZE 64 /*!< usb endpoint 0 max size */
|
||||
|
||||
/**
|
||||
* @brief usb swap address
|
||||
*/
|
||||
#define SWAPBYTE(addr) (uint16_t)(((uint16_t)(*((uint8_t *)(addr)))) + \
|
||||
(((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8)) /*!< swap address */
|
||||
|
||||
/**
|
||||
* @brief min and max define
|
||||
*/
|
||||
#define MIN(a, b) (uint16_t)(((a) < (b)) ? (a) : (b)) /*!< min define*/
|
||||
#define MAX(a, b) (uint16_t)(((a) > (b)) ? (a) : (b)) /*!< max define*/
|
||||
|
||||
/**
|
||||
* @brief low byte and high byte define
|
||||
*/
|
||||
#define LBYTE(x) ((uint8_t)(x & 0x00FF)) /*!< low byte define */
|
||||
#define HBYTE(x) ((uint8_t)((x & 0xFF00) >>8)) /*!< high byte define*/
|
||||
|
||||
/**
|
||||
* @brief usb return status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USB_OK, /*!< usb status ok */
|
||||
USB_FAIL, /*!< usb status fail */
|
||||
USB_WAIT, /*!< usb status wait */
|
||||
USB_NOT_SUPPORT, /*!< usb status not support */
|
||||
USB_ERROR, /*!< usb status error */
|
||||
}usb_sts_type;
|
||||
|
||||
|
||||
/**
|
||||
* @brief format of usb setup data
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t bmRequestType; /*!< characteristics of request */
|
||||
uint8_t bRequest; /*!< specific request */
|
||||
uint16_t wValue; /*!< word-sized field that varies according to request */
|
||||
uint16_t wIndex; /*!< word-sized field that varies according to request
|
||||
typically used to pass an index or offset */
|
||||
uint16_t wLength; /*!< number of bytes to transfer if there is a data stage */
|
||||
} usb_setup_type;
|
||||
|
||||
/**
|
||||
* @brief format of standard device descriptor
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t bLength; /*!< size of this descriptor in bytes */
|
||||
uint8_t bDescriptorType; /*!< device descriptor type */
|
||||
uint16_t bcdUSB; /*!< usb specification release number */
|
||||
uint8_t bDeviceClass; /*!< class code (assigned by the usb-if) */
|
||||
uint8_t bDeviceSubClass; /*!< subclass code (assigned by the usb-if) */
|
||||
uint8_t bDeviceProtocol; /*!< protocol code ((assigned by the usb-if)) */
|
||||
uint8_t bMaxPacketSize0; /*!< maximum packet size for endpoint zero */
|
||||
uint16_t idVendor; /*!< verndor id ((assigned by the usb-if)) */
|
||||
uint16_t idProduct; /*!< product id ((assigned by the usb-if)) */
|
||||
uint16_t bcdDevice; /*!< device release number in binary-coded decimal */
|
||||
uint8_t iManufacturer; /*!< index of string descriptor describing manufacturer */
|
||||
uint8_t iProduct; /*!< index of string descriptor describing product */
|
||||
uint8_t iSerialNumber; /*!< index of string descriptor describing serial number */
|
||||
uint8_t bNumConfigurations; /*!< number of possible configurations */
|
||||
} usb_device_desc_type;
|
||||
|
||||
/**
|
||||
* @brief format of standard configuration descriptor
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t bLength; /*!< size of this descriptor in bytes */
|
||||
uint8_t bDescriptorType; /*!< configuration descriptor type */
|
||||
uint16_t wTotalLength; /*!< total length of data returned for this configuration */
|
||||
uint8_t bNumInterfaces; /*!< number of interfaces supported by this configuration */
|
||||
uint8_t bConfigurationValue; /*!< value to use as an argument to the SetConfiguration() request */
|
||||
uint8_t iConfiguration; /*!< index of string descriptor describing this configuration */
|
||||
uint8_t bmAttributes; /*!< configuration characteristics
|
||||
D7 reserved
|
||||
D6 self-powered
|
||||
D5 remote wakeup
|
||||
D4~D0 reserved */
|
||||
uint8_t bMaxPower; /*!< maximum power consumption of the usb device from the bus */
|
||||
|
||||
|
||||
}usb_configuration_desc_type;
|
||||
|
||||
/**
|
||||
* @brief format of standard interface descriptor
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t bLength; /*!< size of this descriptor in bytes */
|
||||
uint8_t bDescriptorType; /*!< interface descriptor type */
|
||||
uint8_t bInterfaceNumber; /*!< number of this interface */
|
||||
uint8_t bAlternateSetting; /*!< value used to select this alternate setting for the interface */
|
||||
uint8_t bNumEndpoints; /*!< number of endpoints used by this interface */
|
||||
uint8_t bInterfaceClass; /*!< class code (assigned by the usb-if) */
|
||||
uint8_t bInterfaceSubClass; /*!< subclass code (assigned by the usb-if) */
|
||||
uint8_t bInterfaceProtocol; /*!< protocol code (assigned by the usb-if) */
|
||||
uint8_t iInterface; /*!< index of string descriptor describing this interface */
|
||||
} usb_interface_desc_type;
|
||||
|
||||
/**
|
||||
* @brief format of standard endpoint descriptor
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t bLength; /*!< size of this descriptor in bytes */
|
||||
uint8_t bDescriptorType; /*!< endpoint descriptor type */
|
||||
uint8_t bEndpointAddress; /*!< the address of the endpoint on the usb device described by this descriptor */
|
||||
uint8_t bmAttributes; /*!< describes the endpoints attributes when it is configured using bConfiguration value */
|
||||
uint16_t wMaxPacketSize; /*!< maximum packet size this endpoint */
|
||||
uint8_t bInterval; /*!< interval for polling endpoint for data transfers */
|
||||
} usb_endpoint_desc_type;
|
||||
|
||||
/**
|
||||
* @brief format of header
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t bLength; /*!< size of this descriptor in bytes */
|
||||
uint8_t bDescriptorType; /*!< descriptor type */
|
||||
} usb_header_desc_type;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,186 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file usbd_core.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief usb device core header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USBD_CORE_H
|
||||
#define __USBD_CORE_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#include "usb_conf.h"
|
||||
#include "usb_std.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_middlewares_usbd_drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USBD_drivers_core
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_core_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef USE_OTG_DEVICE_MODE
|
||||
|
||||
/**
|
||||
* @brief usb device event
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USBD_NOP_EVENT, /*!< usb device nop event */
|
||||
USBD_RESET_EVENT, /*!< usb device reset event */
|
||||
USBD_SUSPEND_EVENT, /*!< usb device suspend event */
|
||||
USBD_WAKEUP_EVENT, /*!< usb device wakeup event */
|
||||
USBD_DISCONNECT_EVNET, /*!< usb device disconnect event */
|
||||
USBD_INISOINCOM_EVENT, /*!< usb device inisoincom event */
|
||||
USBD_OUTISOINCOM_EVENT, /*!< usb device outisoincom event */
|
||||
USBD_ERR_EVENT /*!< usb device error event */
|
||||
}usbd_event_type;
|
||||
|
||||
/**
|
||||
* @brief usb device descriptor struct
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t length; /*!< descriptor length */
|
||||
uint8_t *descriptor; /*!< descriptor string */
|
||||
}usbd_desc_t;
|
||||
|
||||
/**
|
||||
* @brief usb device descriptor handler
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
usbd_desc_t *(*get_device_descriptor)(void); /*!< get device descriptor callback */
|
||||
usbd_desc_t *(*get_device_qualifier)(void); /*!< get device qualifier callback */
|
||||
usbd_desc_t *(*get_device_configuration)(void); /*!< get device configuration callback */
|
||||
usbd_desc_t *(*get_device_other_speed)(void); /*!< get device other speed callback */
|
||||
usbd_desc_t *(*get_device_lang_id)(void); /*!< get device lang id callback */
|
||||
usbd_desc_t *(*get_device_manufacturer_string)(void); /*!< get device manufacturer callback */
|
||||
usbd_desc_t *(*get_device_product_string)(void); /*!< get device product callback */
|
||||
usbd_desc_t *(*get_device_serial_string)(void); /*!< get device serial callback */
|
||||
usbd_desc_t *(*get_device_interface_string)(void); /*!< get device interface string callback */
|
||||
usbd_desc_t *(*get_device_config_string)(void); /*!< get device device config callback */
|
||||
}usbd_desc_handler;
|
||||
|
||||
/**
|
||||
* @brief usb device class handler
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
usb_sts_type (*init_handler)(void *udev); /*!< usb class init handler */
|
||||
usb_sts_type (*clear_handler)(void *udev); /*!< usb class clear handler */
|
||||
usb_sts_type (*setup_handler)(void *udev, usb_setup_type *setup); /*!< usb class setup handler */
|
||||
usb_sts_type (*ept0_tx_handler)(void *udev); /*!< usb class endpoint 0 tx complete handler */
|
||||
usb_sts_type (*ept0_rx_handler)(void *udev); /*!< usb class endpoint 0 rx complete handler */
|
||||
usb_sts_type (*in_handler)(void *udev, uint8_t ept_num); /*!< usb class in transfer complete handler */
|
||||
usb_sts_type (*out_handler)(void *udev, uint8_t ept_num); /*!< usb class out transfer complete handler */
|
||||
usb_sts_type (*sof_handler)(void *udev); /*!< usb class sof handler */
|
||||
usb_sts_type (*event_handler)(void *udev, usbd_event_type event); /*!< usb class event handler */
|
||||
}usbd_class_handler;
|
||||
|
||||
/**
|
||||
* @brief usb device core struct type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
usb_reg_type *usb_reg; /*!< usb register pointer */
|
||||
|
||||
usbd_class_handler *class_handler; /*!< usb device class handler pointer */
|
||||
usbd_desc_handler *desc_handler; /*!< usb device descriptor handler pointer */
|
||||
|
||||
usb_ept_info ept_in[USB_EPT_MAX_NUM]; /*!< usb in endpoint infomation struct */
|
||||
usb_ept_info ept_out[USB_EPT_MAX_NUM]; /*!< usb out endpoint infomation struct */
|
||||
|
||||
usb_setup_type setup; /*!< usb setup type struct */
|
||||
uint8_t setup_buffer[12]; /*!< usb setup request buffer */
|
||||
|
||||
uint8_t ept0_sts; /*!< usb control endpoint 0 state */
|
||||
uint8_t speed; /*!< usb speed */
|
||||
uint16_t ept0_wlength; /*!< usb endpoint 0 transfer length */
|
||||
|
||||
usbd_conn_state conn_state; /*!< usb current connect state */
|
||||
usbd_conn_state old_conn_state; /*!< usb save the previous connect state */
|
||||
|
||||
uint8_t device_addr; /*!< device address */
|
||||
uint8_t remote_wakup; /*!< remote wakeup state */
|
||||
uint8_t default_config; /*!< usb default config state */
|
||||
uint8_t dev_config; /*!< usb device config state */
|
||||
uint32_t config_status; /*!< usb configure status */
|
||||
}usbd_core_type;
|
||||
|
||||
void usbd_core_in_handler(usbd_core_type *udev, uint8_t ept_num);
|
||||
void usbd_core_out_handler(usbd_core_type *udev, uint8_t ept_num);
|
||||
void usbd_core_setup_handler(usbd_core_type *udev, uint8_t ept_num);
|
||||
void usbd_ctrl_unsupport(usbd_core_type *udev);
|
||||
void usbd_ctrl_send(usbd_core_type *udev, uint8_t *buffer, uint16_t len);
|
||||
void usbd_ctrl_recv(usbd_core_type *udev, uint8_t *buffer, uint16_t len);
|
||||
void usbd_ctrl_send_status(usbd_core_type *udev);
|
||||
void usbd_ctrl_recv_status(usbd_core_type *udev);
|
||||
void usbd_set_stall(usbd_core_type *udev, uint8_t ept_addr);
|
||||
void usbd_clear_stall(usbd_core_type *udev, uint8_t ept_addr);
|
||||
void usbd_ept_open(usbd_core_type *udev, uint8_t ept_addr, uint8_t ept_type, uint16_t maxpacket);
|
||||
void usbd_ept_close(usbd_core_type *udev, uint8_t ept_addr);
|
||||
void usbd_ept_send(usbd_core_type *udev, uint8_t ept_num, uint8_t *buffer, uint16_t len);
|
||||
void usbd_ept_recv(usbd_core_type *udev, uint8_t ept_num, uint8_t *buffer, uint16_t len);
|
||||
void usbd_connect(usbd_core_type *udev);
|
||||
void usbd_disconnect(usbd_core_type *udev);
|
||||
void usbd_set_device_addr(usbd_core_type *udev, uint8_t address);
|
||||
uint32_t usbd_get_recv_len(usbd_core_type *udev, uint8_t ept_addr);
|
||||
void usb_ept_defaut_init(usbd_core_type *udev);
|
||||
usbd_conn_state usbd_connect_state_get(usbd_core_type *udev);
|
||||
void usbd_remote_wakeup(usbd_core_type *udev);
|
||||
void usbd_enter_suspend(usbd_core_type *udev);
|
||||
void usbd_flush_tx_fifo(usbd_core_type *udev, uint8_t ept_num);
|
||||
void usbd_fifo_alloc(usbd_core_type *udev);
|
||||
usb_sts_type usbd_core_init(usbd_core_type *udev,
|
||||
usb_reg_type *usb_reg,
|
||||
usbd_class_handler *class_handler,
|
||||
usbd_desc_handler *desc_handler,
|
||||
uint8_t core_id);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,82 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file usbd_int.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief usb interrupt header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USBD_INT_H
|
||||
#define __USBD_INT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup AT32F435_437_middlewares_usbd_drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USBD_drivers_int
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_interrupt_exported_types
|
||||
* @{
|
||||
*/
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "usbd_core.h"
|
||||
#include "usb_core.h"
|
||||
|
||||
void usbd_irq_handler(otg_core_type *udev);
|
||||
void usbd_ept_handler(usbd_core_type *udev);
|
||||
void usbd_reset_handler(usbd_core_type *udev);
|
||||
void usbd_sof_handler(usbd_core_type *udev);
|
||||
void usbd_suspend_handler(usbd_core_type *udev);
|
||||
void usbd_wakeup_handler(usbd_core_type *udev);
|
||||
void usbd_inept_handler(usbd_core_type *udev);
|
||||
void usbd_outept_handler(usbd_core_type *udev);
|
||||
void usbd_enumdone_handler(usbd_core_type *udev);
|
||||
void usbd_rxflvl_handler(usbd_core_type *udev);
|
||||
void usbd_incomisioin_handler(usbd_core_type *udev);
|
||||
void usbd_discon_handler(usbd_core_type *udev);
|
||||
void usbd_incomisoout_handler(usbd_core_type *udev);
|
||||
void usb_write_empty_txfifo(usbd_core_type *udev, uint32_t ept_num);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_def.h
|
||||
* @file usb_sdr.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief at32f435_437 macros header file
|
||||
* @brief usb header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
@@ -24,44 +24,48 @@
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_DEF_H
|
||||
#define __AT32F435_437_DEF_H
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_SDR_H
|
||||
#define __USB_SDR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* gnu compiler */
|
||||
#if defined (__GNUC__)
|
||||
#ifndef ALIGNED_HEAD
|
||||
#define ALIGNED_HEAD
|
||||
#endif
|
||||
#ifndef ALIGNED_TAIL
|
||||
#define ALIGNED_TAIL __attribute__ ((aligned (4)))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* arm compiler */
|
||||
#if defined (__CC_ARM)
|
||||
#ifndef ALIGNED_HEAD
|
||||
#define ALIGNED_HEAD __align(4)
|
||||
#endif
|
||||
#ifndef ALIGNED_TAIL
|
||||
#define ALIGNED_TAIL
|
||||
#endif
|
||||
#endif
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "usb_conf.h"
|
||||
#include "usb_core.h"
|
||||
/** @addtogroup AT32F435_437_middlewares_usbd_drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USBD_drivers_standard_request
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* iar compiler */
|
||||
#if defined (__ICCARM__)
|
||||
#ifndef ALIGNED_HEAD
|
||||
#define ALIGNED_HEAD
|
||||
#endif
|
||||
#ifndef ALIGNED_TAIL
|
||||
#define ALIGNED_TAIL
|
||||
#endif
|
||||
#endif
|
||||
/** @defgroup USBD_sdr_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
void usbd_setup_request_parse(usb_setup_type *setup, uint8_t *buf);
|
||||
usb_sts_type usbd_device_request(usbd_core_type *udev);
|
||||
usb_sts_type usbd_interface_request(usbd_core_type *udev);
|
||||
usb_sts_type usbd_endpoint_request(usbd_core_type *udev);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,4 +1,4 @@
|
||||
name=AT32_USB-FS-Device_Driver
|
||||
name=AT32F43x_USB-Device_Driver
|
||||
version=1.0.0
|
||||
author=AT
|
||||
maintainer=AT
|
||||
@@ -0,0 +1,188 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file usb_core.c
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief usb driver
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
#include "usb_core.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_middlewares_usb_drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_drivers_core
|
||||
* @brief usb global drivers core
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_core_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
usb_sts_type usb_core_config(otg_core_type *udev, uint8_t core_id);
|
||||
|
||||
/**
|
||||
* @brief usb core config
|
||||
* @param otgdev: to the structure of otg_core_type
|
||||
* @param core_id: usb core id number (USB_FULL_SPEED_CORE_ID)
|
||||
* @retval usb_sts_type
|
||||
*/
|
||||
usb_sts_type usb_core_config(otg_core_type *otgdev, uint8_t core_id)
|
||||
{
|
||||
/* set usb speed and core id */
|
||||
otgdev->cfg.speed = core_id;
|
||||
otgdev->cfg.core_id = core_id;
|
||||
|
||||
/* default sof out and vbus ignore */
|
||||
otgdev->cfg.sof_out = FALSE;
|
||||
otgdev->cfg.vbusig = FALSE;
|
||||
|
||||
/* set max size */
|
||||
otgdev->cfg.max_size = 64;
|
||||
|
||||
/* set support number of channel and endpoint */
|
||||
#ifdef USE_OTG_HOST_MODE
|
||||
otgdev->cfg.hc_num = USB_HOST_CHANNEL_NUM;
|
||||
#endif
|
||||
#ifdef USE_OTG_DEVICE_MODE
|
||||
otgdev->cfg.ept_num = USB_EPT_MAX_NUM;
|
||||
#endif
|
||||
otgdev->cfg.fifo_size = OTG_FIFO_SIZE;
|
||||
if(core_id == USB_FULL_SPEED_CORE_ID)
|
||||
{
|
||||
otgdev->cfg.phy_itface = 2;
|
||||
}
|
||||
#ifdef USB_SOF_OUTPUT_ENABLE
|
||||
otgdev->cfg.sof_out = TRUE;
|
||||
#endif
|
||||
|
||||
#ifdef USB_VBUS_IGNORE
|
||||
otgdev->cfg.vbusig = TRUE;
|
||||
#endif
|
||||
|
||||
return USB_OK;
|
||||
}
|
||||
|
||||
#ifdef USE_OTG_DEVICE_MODE
|
||||
/**
|
||||
* @brief usb device initialization
|
||||
* @param otgdev: to the structure of otg_core_type
|
||||
* @param core_id: usb core id number (USB_FULL_SPEED_CORE_ID)
|
||||
* @param usb_id: select use OTG1 or OTG2
|
||||
* this parameter can be one of the following values:
|
||||
* - USB_OTG1_ID
|
||||
* - USB_OTG2_ID
|
||||
* @param dev_handler: usb class callback handler
|
||||
* @param desc_handler: device config callback handler
|
||||
* @retval usb_sts_type
|
||||
*/
|
||||
usb_sts_type usbd_init(otg_core_type *otgdev,
|
||||
uint8_t core_id, uint8_t usb_id,
|
||||
usbd_class_handler *class_handler,
|
||||
usbd_desc_handler *desc_handler)
|
||||
{
|
||||
usb_sts_type usb_sts = USB_OK;
|
||||
|
||||
/* select use OTG1 or OTG2 */
|
||||
otgdev->usb_reg = usb_global_select_core(usb_id);
|
||||
|
||||
/* usb device core config */
|
||||
usb_core_config(otgdev, core_id);
|
||||
|
||||
if(otgdev->cfg.sof_out)
|
||||
{
|
||||
otgdev->usb_reg->gccfg_bit.sofouten = TRUE;
|
||||
}
|
||||
|
||||
if(otgdev->cfg.vbusig)
|
||||
{
|
||||
otgdev->usb_reg->gccfg_bit.vbusig = TRUE;
|
||||
}
|
||||
|
||||
/* usb device core init */
|
||||
usbd_core_init(&(otgdev->dev), otgdev->usb_reg,
|
||||
class_handler,
|
||||
desc_handler,
|
||||
core_id);
|
||||
|
||||
return usb_sts;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef USE_OTG_HOST_MODE
|
||||
|
||||
/**
|
||||
* @brief usb host initialization.
|
||||
* @param otgdev: to the structure of otg_core_type
|
||||
* @param core_id: usb core id number (USB_FULL_SPEED_CORE_ID)
|
||||
* @param usb_id: select use OTG1 or OTG2
|
||||
* this parameter can be one of the following values:
|
||||
* - USB_OTG1_ID
|
||||
* - USB_OTG2_ID
|
||||
* @param class_handler: usb class callback handler
|
||||
* @param user_handler: user callback handler
|
||||
* @retval usb_sts_type
|
||||
*/
|
||||
usb_sts_type usbh_init(otg_core_type *otgdev,
|
||||
uint8_t core_id, uint8_t usb_id,
|
||||
usbh_class_handler_type *class_handler,
|
||||
usbh_user_handler_type *user_handler)
|
||||
{
|
||||
usb_sts_type status = USB_OK;
|
||||
|
||||
/* select use otg1 or otg2 */
|
||||
otgdev->usb_reg = usb_global_select_core(usb_id);
|
||||
|
||||
/* usb core config */
|
||||
usb_core_config(otgdev, core_id);
|
||||
|
||||
if(otgdev->cfg.sof_out)
|
||||
{
|
||||
otgdev->usb_reg->gccfg_bit.sofouten = TRUE;
|
||||
}
|
||||
|
||||
if(otgdev->cfg.vbusig)
|
||||
{
|
||||
otgdev->usb_reg->gccfg_bit.vbusig = TRUE;
|
||||
}
|
||||
|
||||
/* usb host core init */
|
||||
usbh_core_init(&otgdev->host, otgdev->usb_reg,
|
||||
class_handler,
|
||||
user_handler,
|
||||
core_id);
|
||||
|
||||
return status;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -0,0 +1,876 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file usbd_core.c
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief usb device driver
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#include "usb_core.h"
|
||||
#include "usbd_core.h"
|
||||
#include "usbd_sdr.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_middlewares_usbd_drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_drivers_core
|
||||
* @brief usb device drivers core
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_core_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief usb core in transfer complete handler
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param ept_addr: endpoint number
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_core_in_handler(usbd_core_type *udev, uint8_t ept_addr)
|
||||
{
|
||||
/* get endpoint info*/
|
||||
usb_ept_info *ept_info = &udev->ept_in[ept_addr & 0x7F];
|
||||
|
||||
if(ept_addr == 0)
|
||||
{
|
||||
if(udev->ept0_sts == USB_EPT0_DATA_IN)
|
||||
{
|
||||
if(ept_info->ept0_slen > ept_info->maxpacket)
|
||||
{
|
||||
ept_info->ept0_slen -= ept_info->maxpacket;
|
||||
usbd_ept_send(udev, 0, ept_info->trans_buf,
|
||||
MIN(ept_info->ept0_slen, ept_info->maxpacket));
|
||||
}
|
||||
/* endpoint 0 */
|
||||
else if(ept_info->last_len == ept_info->maxpacket
|
||||
&& ept_info->ept0_slen <= udev->ept0_wlength)
|
||||
{
|
||||
ept_info->last_len = 0;
|
||||
usbd_ept_send(udev, 0, 0, 0);
|
||||
usbd_ept_recv(udev, ept_addr, 0, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
if(udev->class_handler->ept0_tx_handler != 0 &&
|
||||
udev->conn_state == USB_CONN_STATE_CONFIGURED)
|
||||
{
|
||||
udev->class_handler->ept0_tx_handler(udev);
|
||||
}
|
||||
usbd_ctrl_recv_status(udev);
|
||||
}
|
||||
}
|
||||
}
|
||||
else if(udev->class_handler->in_handler != 0 &&
|
||||
udev->conn_state == USB_CONN_STATE_CONFIGURED)
|
||||
{
|
||||
/* other user define endpoint */
|
||||
udev->class_handler->in_handler(udev, ept_addr);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb core out transfer complete handler
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param ept_addr: endpoint number
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_core_out_handler(usbd_core_type *udev, uint8_t ept_addr)
|
||||
{
|
||||
/* get endpoint info*/
|
||||
usb_ept_info *ept_info = &udev->ept_out[ept_addr & 0x7F];
|
||||
|
||||
if(ept_addr == 0)
|
||||
{
|
||||
/* endpoint 0 */
|
||||
if(udev->ept0_sts == USB_EPT0_DATA_OUT)
|
||||
{
|
||||
if(ept_info->ept0_slen > ept_info->maxpacket)
|
||||
{
|
||||
ept_info->ept0_slen -= ept_info->maxpacket;
|
||||
usbd_ept_recv(udev, ept_addr, ept_info->trans_buf,
|
||||
MIN(ept_info->ept0_slen, ept_info->maxpacket));
|
||||
}
|
||||
else
|
||||
{
|
||||
if(udev->class_handler->ept0_rx_handler != 0)
|
||||
{
|
||||
udev->class_handler->ept0_rx_handler(udev);
|
||||
}
|
||||
usbd_ctrl_send_status(udev);
|
||||
}
|
||||
}
|
||||
}
|
||||
else if(udev->class_handler->out_handler != 0 &&
|
||||
udev->conn_state == USB_CONN_STATE_CONFIGURED)
|
||||
{
|
||||
/* other user define endpoint */
|
||||
udev->class_handler->out_handler(udev, ept_addr);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb core setup transfer complete handler
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param ept_addr: endpoint number
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_core_setup_handler(usbd_core_type *udev, uint8_t ept_num)
|
||||
{
|
||||
/* setup parse */
|
||||
usbd_setup_request_parse(&udev->setup, udev->setup_buffer);
|
||||
|
||||
/* set ept0 status */
|
||||
udev->ept0_sts = USB_EPT0_SETUP;
|
||||
udev->ept0_wlength = udev->setup.wLength;
|
||||
|
||||
switch(udev->setup.bmRequestType & USB_REQ_RECIPIENT_MASK)
|
||||
{
|
||||
case USB_REQ_RECIPIENT_DEVICE:
|
||||
/* recipient device request */
|
||||
usbd_device_request(udev);
|
||||
break;
|
||||
case USB_REQ_RECIPIENT_INTERFACE:
|
||||
/* recipient interface request */
|
||||
usbd_interface_request(udev);
|
||||
break;
|
||||
case USB_REQ_RECIPIENT_ENDPOINT:
|
||||
/* recipient endpoint request */
|
||||
usbd_endpoint_request(udev);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb control endpoint send data
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param ept_addr: endpoint number
|
||||
* @param buffer: send data buffer
|
||||
* @param len: send data length
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_ctrl_send(usbd_core_type *udev, uint8_t *buffer, uint16_t len)
|
||||
{
|
||||
usb_ept_info *ept_info = &udev->ept_in[0];
|
||||
|
||||
ept_info->ept0_slen = len;
|
||||
udev->ept0_sts = USB_EPT0_DATA_IN;
|
||||
|
||||
usbd_ept_send(udev, 0, buffer, len);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb control endpoint recv data
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param ept_addr: endpoint number
|
||||
* @param buffer: recv data buffer
|
||||
* @param len: recv data length
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_ctrl_recv(usbd_core_type *udev, uint8_t *buffer, uint16_t len)
|
||||
{
|
||||
usb_ept_info *ept_info = &udev->ept_out[0];
|
||||
|
||||
ept_info->ept0_slen = len;
|
||||
udev->ept0_sts = USB_EPT0_DATA_OUT;
|
||||
|
||||
usbd_ept_recv(udev, 0, buffer, len);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb control endpoint send in status
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_ctrl_send_status(usbd_core_type *udev)
|
||||
{
|
||||
udev->ept0_sts = USB_EPT0_STATUS_IN;
|
||||
|
||||
usbd_ept_send(udev, 0, 0, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb control endpoint send out status
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_ctrl_recv_status(usbd_core_type *udev)
|
||||
{
|
||||
udev->ept0_sts = USB_EPT0_STATUS_OUT;
|
||||
|
||||
usbd_ept_recv(udev, 0, 0, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear endpoint stall
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param ept_addr: endpoint number
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_clear_stall(usbd_core_type *udev, uint8_t ept_addr)
|
||||
{
|
||||
usb_ept_info *ept_info;
|
||||
usb_reg_type *usbx = udev->usb_reg;
|
||||
|
||||
if(ept_addr & 0x80)
|
||||
{
|
||||
/* in endpoint */
|
||||
ept_info = &udev->ept_in[ept_addr & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
/* out endpoint */
|
||||
ept_info = &udev->ept_out[ept_addr & 0x7F];
|
||||
}
|
||||
usb_ept_clear_stall(usbx, ept_info);
|
||||
ept_info->stall = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb set endpoint to stall status
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param ept_addr: endpoint number
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_set_stall(usbd_core_type *udev, uint8_t ept_addr)
|
||||
{
|
||||
usb_ept_info *ept_info;
|
||||
usb_reg_type *usbx = udev->usb_reg;
|
||||
|
||||
if(ept_addr & 0x80)
|
||||
{
|
||||
/* in endpoint */
|
||||
ept_info = &udev->ept_in[ept_addr & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
/* out endpoint */
|
||||
ept_info = &udev->ept_out[ept_addr & 0x7F];
|
||||
}
|
||||
usb_ept_stall(usbx, ept_info);
|
||||
|
||||
ept_info->stall = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief un-support device request
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_ctrl_unsupport(usbd_core_type *udev)
|
||||
{
|
||||
/* return stall status */
|
||||
usbd_set_stall(udev, 0x00);
|
||||
usbd_set_stall(udev, 0x80);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get endpoint receive data length
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param ept_addr: endpoint number
|
||||
* @retval data receive len
|
||||
*/
|
||||
uint32_t usbd_get_recv_len(usbd_core_type *udev, uint8_t ept_addr)
|
||||
{
|
||||
usb_ept_info *ept = &udev->ept_out[ept_addr & 0x7F];
|
||||
return ept->trans_len;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb open endpoint
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param ept_addr: endpoint number
|
||||
* @param ept_type: endpoint type
|
||||
* @param maxpacket: endpoint support max buffer size
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_ept_open(usbd_core_type *udev, uint8_t ept_addr, uint8_t ept_type, uint16_t maxpacket)
|
||||
{
|
||||
usb_reg_type *usbx = udev->usb_reg;
|
||||
usb_ept_info *ept_info;
|
||||
|
||||
if((ept_addr & 0x80) == 0)
|
||||
{
|
||||
/* out endpoint info */
|
||||
ept_info = &udev->ept_out[ept_addr & 0x7F];
|
||||
ept_info->inout = EPT_DIR_OUT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* in endpoint info */
|
||||
ept_info = &udev->ept_in[ept_addr & 0x7F];
|
||||
ept_info->inout = EPT_DIR_IN;
|
||||
}
|
||||
|
||||
/* set endpoint maxpacket and type */
|
||||
ept_info->maxpacket = maxpacket;
|
||||
ept_info->trans_type = ept_type;
|
||||
|
||||
/* open endpoint */
|
||||
usb_ept_open(usbx, ept_info);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb close endpoint
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param ept_addr: endpoint number
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_ept_close(usbd_core_type *udev, uint8_t ept_addr)
|
||||
{
|
||||
usb_ept_info *ept_info;
|
||||
if(ept_addr & 0x80)
|
||||
{
|
||||
/* in endpoint */
|
||||
ept_info = &udev->ept_in[ept_addr & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
/* out endpoint */
|
||||
ept_info = &udev->ept_out[ept_addr & 0x7F];
|
||||
}
|
||||
|
||||
/* close endpoint */
|
||||
usb_ept_close(udev->usb_reg, ept_info);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device connect to host
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_connect(usbd_core_type *udev)
|
||||
{
|
||||
usb_connect(udev->usb_reg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device disconnect to host
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_disconnect(usbd_core_type *udev)
|
||||
{
|
||||
usb_disconnect(udev->usb_reg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device set device address.
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param address: host assignment address
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_set_device_addr(usbd_core_type *udev, uint8_t address)
|
||||
{
|
||||
usb_set_address(udev->usb_reg, address);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb endpoint structure initialization
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usb_ept_default_init(usbd_core_type *udev)
|
||||
{
|
||||
uint8_t i_index = 0;
|
||||
/* init in endpoint info structure */
|
||||
for(i_index = 0; i_index < USB_EPT_MAX_NUM; i_index ++)
|
||||
{
|
||||
udev->ept_in[i_index].eptn = i_index;
|
||||
udev->ept_in[i_index].ept_address = i_index;
|
||||
udev->ept_in[i_index].inout = EPT_DIR_IN;
|
||||
udev->ept_in[i_index].maxpacket = 0;
|
||||
udev->ept_in[i_index].trans_buf = 0;
|
||||
udev->ept_in[i_index].total_len = 0;
|
||||
}
|
||||
|
||||
/* init out endpoint info structure */
|
||||
for(i_index = 0; i_index < USB_EPT_MAX_NUM; i_index ++)
|
||||
{
|
||||
udev->ept_out[i_index].eptn = i_index;
|
||||
udev->ept_out[i_index].ept_address = i_index;
|
||||
udev->ept_out[i_index].inout = EPT_DIR_OUT;
|
||||
udev->ept_out[i_index].maxpacket = 0;
|
||||
udev->ept_out[i_index].trans_buf = 0;
|
||||
udev->ept_out[i_index].total_len = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief endpoint send data
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param ept_addr: endpoint number
|
||||
* @param buffer: send data buffer
|
||||
* @param len: send data length
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_ept_send(usbd_core_type *udev, uint8_t ept_addr, uint8_t *buffer, uint16_t len)
|
||||
{
|
||||
/* get endpoint info struct and register */
|
||||
usb_reg_type *usbx = udev->usb_reg;
|
||||
usb_ept_info *ept_info = &udev->ept_in[ept_addr & 0x7F];
|
||||
otg_eptin_type *ept_in = USB_INEPT(usbx, ept_info->eptn);
|
||||
otg_device_type *dev = OTG_DEVICE(usbx);
|
||||
uint32_t pktcnt;
|
||||
|
||||
/* set send data buffer and length */
|
||||
ept_info->trans_buf = buffer;
|
||||
ept_info->total_len = len;
|
||||
ept_info->trans_len = 0;
|
||||
|
||||
/* transfer data len is zero */
|
||||
if(ept_info->total_len == 0)
|
||||
{
|
||||
ept_in->dieptsiz_bit.pktcnt = 1;
|
||||
ept_in->dieptsiz_bit.xfersize = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
if((ept_addr & 0x7F) == 0) // endpoint 0
|
||||
{
|
||||
/* endpoint 0 */
|
||||
if(ept_info->total_len > ept_info->maxpacket)
|
||||
{
|
||||
ept_info->total_len = ept_info->maxpacket;
|
||||
}
|
||||
|
||||
/* set transfer size */
|
||||
ept_in->dieptsiz_bit.xfersize = ept_info->total_len;
|
||||
|
||||
/* set packet count */
|
||||
ept_in->dieptsiz_bit.pktcnt = 1;
|
||||
|
||||
ept_info->last_len = ept_info->total_len;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* other endpoint */
|
||||
|
||||
/* packet count */
|
||||
pktcnt = (ept_info->total_len + ept_info->maxpacket - 1) / ept_info->maxpacket;
|
||||
|
||||
/* set transfer size */
|
||||
ept_in->dieptsiz_bit.xfersize = ept_info->total_len;
|
||||
|
||||
/* set packet count */
|
||||
ept_in->dieptsiz_bit.pktcnt = pktcnt;
|
||||
|
||||
if(ept_info->trans_type == EPT_ISO_TYPE)
|
||||
{
|
||||
ept_in->dieptsiz_bit.mc = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(ept_info->trans_type != EPT_ISO_TYPE)
|
||||
{
|
||||
if(ept_info->total_len > 0)
|
||||
{
|
||||
/* set in endpoint tx fifo empty interrupt mask */
|
||||
dev->diepempmsk |= 1 << ept_info->eptn;
|
||||
}
|
||||
}
|
||||
|
||||
if(ept_info->trans_type == EPT_ISO_TYPE)
|
||||
{
|
||||
if((dev->dsts_bit.soffn & 0x1) == 0)
|
||||
{
|
||||
ept_in->diepctl_bit.setd1pid = TRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
ept_in->diepctl_bit.setd0pid = TRUE;
|
||||
}
|
||||
}
|
||||
|
||||
/* clear endpoint nak */
|
||||
ept_in->diepctl_bit.cnak = TRUE;
|
||||
|
||||
/* endpoint enable */
|
||||
ept_in->diepctl_bit.eptena = TRUE;
|
||||
|
||||
if(ept_info->trans_type == EPT_ISO_TYPE)
|
||||
{
|
||||
/* write data to fifo */
|
||||
usb_write_packet(usbx, ept_info->trans_buf, ept_info->eptn, ept_info->total_len);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief endpoint receive data
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param ept_addr: endpoint number
|
||||
* @param buffer: receive data buffer
|
||||
* @param len: receive data length
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_ept_recv(usbd_core_type *udev, uint8_t ept_addr, uint8_t *buffer, uint16_t len)
|
||||
{
|
||||
/* get endpoint info struct and register */
|
||||
usb_reg_type *usbx = udev->usb_reg;
|
||||
usb_ept_info *ept_info = &udev->ept_out[ept_addr & 0x7F];
|
||||
otg_eptout_type *ept_out = USB_OUTEPT(usbx, ept_info->eptn);
|
||||
otg_device_type *dev = OTG_DEVICE(usbx);
|
||||
uint32_t pktcnt;
|
||||
|
||||
/* set receive data buffer and length */
|
||||
ept_info->trans_buf = buffer;
|
||||
ept_info->total_len = len;
|
||||
ept_info->trans_len = 0;
|
||||
|
||||
if((ept_addr & 0x7F) == 0)
|
||||
{
|
||||
/* endpoint 0 */
|
||||
ept_info->total_len = ept_info->maxpacket;
|
||||
}
|
||||
|
||||
if(ept_info->total_len == 0 || ((ept_addr & 0x7F) == 0))
|
||||
{
|
||||
/* set transfer size */
|
||||
ept_out->doeptsiz_bit.xfersize = ept_info->maxpacket;
|
||||
|
||||
/* set packet count */
|
||||
ept_out->doeptsiz_bit.pktcnt = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
pktcnt = (ept_info->total_len + ept_info->maxpacket - 1) / ept_info->maxpacket;
|
||||
|
||||
/* set transfer size */
|
||||
ept_out->doeptsiz_bit.xfersize = ept_info->maxpacket * pktcnt;
|
||||
|
||||
/* set packet count */
|
||||
ept_out->doeptsiz_bit.pktcnt = pktcnt;
|
||||
}
|
||||
|
||||
if(ept_info->trans_type == EPT_ISO_TYPE)
|
||||
{
|
||||
if((dev->dsts_bit.soffn & 0x01) == 0)
|
||||
{
|
||||
ept_out->doepctl_bit.setd1pid = TRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
ept_out->doepctl_bit.setd0pid = TRUE;
|
||||
}
|
||||
}
|
||||
|
||||
/* clear endpoint nak */
|
||||
ept_out->doepctl_bit.cnak = TRUE;
|
||||
|
||||
/* endpoint enable */
|
||||
ept_out->doepctl_bit.eptena = TRUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get usb connect state
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval usb connect state
|
||||
*/
|
||||
usbd_conn_state usbd_connect_state_get(usbd_core_type *udev)
|
||||
{
|
||||
return udev->conn_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device remote wakeup
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_remote_wakeup(usbd_core_type *udev)
|
||||
{
|
||||
/* check device is in suspend mode */
|
||||
if(usb_suspend_status_get(udev->usb_reg) == 1)
|
||||
{
|
||||
/* set connect state */
|
||||
udev->conn_state = udev->old_conn_state;
|
||||
|
||||
/* open phy clock */
|
||||
usb_open_phy_clk(udev->usb_reg);
|
||||
|
||||
/* set remote wakeup */
|
||||
usb_remote_wkup_set(udev->usb_reg);
|
||||
|
||||
/* delay 10 ms */
|
||||
usb_delay_ms(10);
|
||||
|
||||
/* clear remote wakup */
|
||||
usb_remote_wkup_clear(udev->usb_reg);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device enter suspend mode
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_enter_suspend(usbd_core_type *udev)
|
||||
{
|
||||
/* check device is in suspend mode */
|
||||
if(usb_suspend_status_get(udev->usb_reg) == 1)
|
||||
{
|
||||
/* stop phy clk */
|
||||
usb_stop_phy_clk(udev->usb_reg);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device flush in endpoint fifo
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param ept_num: endpoint number
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_flush_tx_fifo(usbd_core_type *udev, uint8_t ept_num)
|
||||
{
|
||||
/* flush endpoint tx fifo */
|
||||
usb_flush_tx_fifo(udev->usb_reg, ept_num & 0x1F);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device endpoint fifo alloc
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_fifo_alloc(usbd_core_type *udev)
|
||||
{
|
||||
usb_reg_type *usbx = udev->usb_reg;
|
||||
|
||||
if(usbx == OTG1_GLOBAL)
|
||||
{
|
||||
/* set receive fifo size */
|
||||
usb_set_rx_fifo(usbx, USBD_RX_SIZE);
|
||||
|
||||
/* set endpoint0 tx fifo size */
|
||||
usb_set_tx_fifo(usbx, USB_EPT0, USBD_EP0_TX_SIZE);
|
||||
|
||||
/* set endpoint1 tx fifo size */
|
||||
usb_set_tx_fifo(usbx, USB_EPT1, USBD_EP1_TX_SIZE);
|
||||
|
||||
/* set endpoint2 tx fifo size */
|
||||
usb_set_tx_fifo(usbx, USB_EPT2, USBD_EP2_TX_SIZE);
|
||||
|
||||
/* set endpoint3 tx fifo size */
|
||||
usb_set_tx_fifo(usbx, USB_EPT3, USBD_EP3_TX_SIZE);
|
||||
|
||||
if(USB_EPT_MAX_NUM == 8)
|
||||
{
|
||||
/* set endpoint4 tx fifo size */
|
||||
usb_set_tx_fifo(usbx, USB_EPT4, USBD_EP4_TX_SIZE);
|
||||
|
||||
/* set endpoint5 tx fifo size */
|
||||
usb_set_tx_fifo(usbx, USB_EPT5, USBD_EP5_TX_SIZE);
|
||||
|
||||
/* set endpoint6 tx fifo size */
|
||||
usb_set_tx_fifo(usbx, USB_EPT6, USBD_EP6_TX_SIZE);
|
||||
|
||||
/* set endpoint7 tx fifo size */
|
||||
usb_set_tx_fifo(usbx, USB_EPT7, USBD_EP7_TX_SIZE);
|
||||
}
|
||||
}
|
||||
#ifdef OTG2_GLOBAL
|
||||
if(usbx == OTG2_GLOBAL)
|
||||
{
|
||||
/* set receive fifo size */
|
||||
usb_set_rx_fifo(usbx, USBD2_RX_SIZE);
|
||||
|
||||
/* set endpoint0 tx fifo size */
|
||||
usb_set_tx_fifo(usbx, USB_EPT0, USBD2_EP0_TX_SIZE);
|
||||
|
||||
/* set endpoint1 tx fifo size */
|
||||
usb_set_tx_fifo(usbx, USB_EPT1, USBD2_EP1_TX_SIZE);
|
||||
|
||||
/* set endpoint2 tx fifo size */
|
||||
usb_set_tx_fifo(usbx, USB_EPT2, USBD2_EP2_TX_SIZE);
|
||||
|
||||
/* set endpoint3 tx fifo size */
|
||||
usb_set_tx_fifo(usbx, USB_EPT3, USBD2_EP3_TX_SIZE);
|
||||
|
||||
if(USB_EPT_MAX_NUM == 8)
|
||||
{
|
||||
/* set endpoint4 tx fifo size */
|
||||
usb_set_tx_fifo(usbx, USB_EPT4, USBD2_EP4_TX_SIZE);
|
||||
|
||||
/* set endpoint5 tx fifo size */
|
||||
usb_set_tx_fifo(usbx, USB_EPT5, USBD2_EP5_TX_SIZE);
|
||||
|
||||
/* set endpoint6 tx fifo size */
|
||||
usb_set_tx_fifo(usbx, USB_EPT6, USBD2_EP6_TX_SIZE);
|
||||
|
||||
/* set endpoint7 tx fifo size */
|
||||
usb_set_tx_fifo(usbx, USB_EPT7, USBD2_EP7_TX_SIZE);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device core initialization
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param usb_reg: usb otgfs peripheral global register
|
||||
* this parameter can be one of the following values:
|
||||
* OTG1_GLOBAL , OTG2_GLOBAL
|
||||
* @param class_handler: usb class handler
|
||||
* @param desc_handler: device config handler
|
||||
* @param core_id: usb core id number
|
||||
* @retval usb_sts_type
|
||||
*/
|
||||
usb_sts_type usbd_core_init(usbd_core_type *udev,
|
||||
usb_reg_type *usb_reg,
|
||||
usbd_class_handler *class_handler,
|
||||
usbd_desc_handler *desc_handler,
|
||||
uint8_t core_id)
|
||||
{
|
||||
usb_reg_type *usbx;
|
||||
otg_device_type *dev;
|
||||
otg_eptin_type *ept_in;
|
||||
otg_eptout_type *ept_out;
|
||||
uint32_t i_index;
|
||||
|
||||
udev->usb_reg = usb_reg;
|
||||
usbx = usb_reg;
|
||||
dev = OTG_DEVICE(usbx);
|
||||
|
||||
/* set connect state */
|
||||
udev->conn_state = USB_CONN_STATE_DEFAULT;
|
||||
|
||||
/* device class config */
|
||||
udev->device_addr = 0;
|
||||
udev->class_handler = class_handler;
|
||||
udev->desc_handler = desc_handler;
|
||||
/* set device disconnect */
|
||||
usbd_disconnect(udev);
|
||||
|
||||
/* set endpoint to default status */
|
||||
usb_ept_default_init(udev);
|
||||
|
||||
/* disable usb global interrupt */
|
||||
usb_interrupt_disable(usbx);
|
||||
|
||||
/* init global register */
|
||||
usb_global_init(usbx);
|
||||
|
||||
/* set device mode */
|
||||
usb_global_set_mode(usbx, OTG_DEVICE_MODE);
|
||||
|
||||
/* open phy clock */
|
||||
usb_open_phy_clk(udev->usb_reg);
|
||||
|
||||
/* set periodic frame interval */
|
||||
dev->dcfg_bit.perfrint = DCFG_PERFRINT_80;
|
||||
|
||||
/* set device speed to full-speed */
|
||||
dev->dcfg_bit.devspd = USB_DCFG_FULL_SPEED;
|
||||
|
||||
/* flush all tx fifo */
|
||||
usb_flush_tx_fifo(usbx, 16);
|
||||
|
||||
/* flush share rx fifo */
|
||||
usb_flush_rx_fifo(usbx);
|
||||
|
||||
/* clear all endpoint interrupt flag and mask */
|
||||
dev->daint = 0xFFFFFFFF;
|
||||
dev->daintmsk = 0;
|
||||
dev->diepmsk = 0;
|
||||
dev->doepmsk = 0;
|
||||
|
||||
for(i_index = 0; i_index < USB_EPT_MAX_NUM; i_index ++)
|
||||
{
|
||||
usbx->dieptxfn[i_index] = 0;
|
||||
}
|
||||
|
||||
/* endpoint fifo alloc */
|
||||
usbd_fifo_alloc(udev);
|
||||
|
||||
/* disable all in endpoint */
|
||||
for(i_index = 0; i_index < USB_EPT_MAX_NUM; i_index ++)
|
||||
{
|
||||
ept_in = USB_INEPT(usbx, i_index);
|
||||
if(ept_in->diepctl_bit.eptena)
|
||||
{
|
||||
ept_in->diepctl = 0;
|
||||
ept_in->diepctl_bit.eptdis = TRUE;
|
||||
ept_in->diepctl_bit.snak = TRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
ept_in->diepctl = 0;
|
||||
}
|
||||
ept_in->dieptsiz = 0;
|
||||
ept_in->diepint = 0xFF;
|
||||
}
|
||||
|
||||
/* disable all out endpoint */
|
||||
for(i_index = 0; i_index < USB_EPT_MAX_NUM; i_index ++)
|
||||
{
|
||||
ept_out = USB_OUTEPT(usbx, i_index);
|
||||
if(ept_out->doepctl_bit.eptena)
|
||||
{
|
||||
ept_out->doepctl = 0;
|
||||
ept_out->doepctl_bit.eptdis = TRUE;
|
||||
ept_out->doepctl_bit.snak = TRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
ept_out->doepctl = 0;
|
||||
}
|
||||
ept_out->doeptsiz = 0;
|
||||
ept_out->doepint = 0xFF;
|
||||
}
|
||||
dev->diepmsk_bit.txfifoudrmsk = TRUE;
|
||||
|
||||
/* clear global interrupt and mask */
|
||||
usbx->gintmsk = 0;
|
||||
usbx->gintsts = 0xBFFFFFFF;
|
||||
|
||||
/* enable global interrupt mask */
|
||||
usbx->gintmsk = USB_OTG_SOF_INT | USB_OTG_RXFLVL_INT |
|
||||
USB_OTG_USBSUSP_INT | USB_OTG_USBRST_INT |
|
||||
USB_OTG_ENUMDONE_INT | USB_OTG_IEPT_INT |
|
||||
USB_OTG_OEPT_INT | USB_OTG_INCOMISOIN_INT |
|
||||
USB_OTG_INCOMPIP_INCOMPISOOUT_INT | USB_OTG_WKUP_INT |
|
||||
USB_OTG_OTGINT_INT;
|
||||
|
||||
/* usb connect */
|
||||
usbd_connect(udev);
|
||||
|
||||
/* enable global interrupt */
|
||||
usb_interrupt_enable(usbx);
|
||||
|
||||
return USB_OK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -0,0 +1,538 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file usbd_int.c
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief usb interrupt request
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
#include "usbd_int.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_middlewares_usbd_drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_drivers_interrupt
|
||||
* @brief usb device interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_int_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief usb device interrput request handler.
|
||||
* @param otgdev: to the structure of otg_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_irq_handler(otg_core_type *otgdev)
|
||||
{
|
||||
otg_global_type *usbx = otgdev->usb_reg;
|
||||
usbd_core_type *udev = &otgdev->dev;
|
||||
uint32_t intsts = usb_global_get_all_interrupt(usbx);
|
||||
|
||||
/* check current device mode */
|
||||
if(usbx->gintsts_bit.curmode == 0)
|
||||
{
|
||||
/* mode mismatch interrupt */
|
||||
if(intsts & USB_OTG_MODEMIS_FLAG)
|
||||
{
|
||||
usb_global_clear_interrupt(usbx, USB_OTG_MODEMIS_FLAG);
|
||||
}
|
||||
|
||||
/* in endpoint interrupt */
|
||||
if(intsts & USB_OTG_IEPT_FLAG)
|
||||
{
|
||||
usbd_inept_handler(udev);
|
||||
}
|
||||
|
||||
/* out endpoint interrupt */
|
||||
if(intsts & USB_OTG_OEPT_FLAG)
|
||||
{
|
||||
usbd_outept_handler(udev);
|
||||
}
|
||||
|
||||
/* usb reset interrupt */
|
||||
if(intsts & USB_OTG_USBRST_FLAG)
|
||||
{
|
||||
usbd_reset_handler(udev);
|
||||
usb_global_clear_interrupt(usbx, USB_OTG_USBRST_FLAG);
|
||||
}
|
||||
|
||||
/* sof interrupt */
|
||||
if(intsts & USB_OTG_SOF_FLAG)
|
||||
{
|
||||
usbd_sof_handler(udev);
|
||||
usb_global_clear_interrupt(usbx, USB_OTG_SOF_FLAG);
|
||||
}
|
||||
|
||||
/* enumeration done interrupt */
|
||||
if(intsts & USB_OTG_ENUMDONE_FLAG)
|
||||
{
|
||||
usbd_enumdone_handler(udev);
|
||||
usb_global_clear_interrupt(usbx, USB_OTG_ENUMDONE_FLAG);
|
||||
}
|
||||
|
||||
/* rx non-empty interrupt, indicates that there is at least one
|
||||
data packet pending to be read in rx fifo */
|
||||
if(intsts & USB_OTG_RXFLVL_FLAG)
|
||||
{
|
||||
usbd_rxflvl_handler(udev);
|
||||
}
|
||||
|
||||
/* incomplete isochronous in transfer interrupt */
|
||||
if(intsts & USB_OTG_INCOMISOIN_FLAG)
|
||||
{
|
||||
usbd_incomisioin_handler(udev);
|
||||
usb_global_clear_interrupt(usbx, USB_OTG_INCOMISOIN_FLAG);
|
||||
}
|
||||
#ifndef USB_VBUS_IGNORE
|
||||
/* disconnect detected interrupt */
|
||||
if(intsts & USB_OTG_OTGINT_FLAG)
|
||||
{
|
||||
uint32_t tmp = udev->usb_reg->gotgint;
|
||||
if(udev->usb_reg->gotgint_bit.sesenddet)
|
||||
usbd_discon_handler(udev);
|
||||
udev->usb_reg->gotgint = tmp;
|
||||
usb_global_clear_interrupt(usbx, USB_OTG_OTGINT_FLAG);
|
||||
}
|
||||
#endif
|
||||
/* incomplete isochronous out transfer interrupt */
|
||||
if(intsts & USB_OTG_INCOMPIP_INCOMPISOOUT_FLAG)
|
||||
{
|
||||
usbd_incomisoout_handler(udev);
|
||||
usb_global_clear_interrupt(usbx, USB_OTG_INCOMPIP_INCOMPISOOUT_FLAG);
|
||||
}
|
||||
|
||||
/* resume/remote wakeup interrupt */
|
||||
if(intsts & USB_OTG_WKUP_FLAG)
|
||||
{
|
||||
usbd_wakeup_handler(udev);
|
||||
usb_global_clear_interrupt(usbx, USB_OTG_WKUP_FLAG);
|
||||
}
|
||||
|
||||
/* usb suspend interrupt */
|
||||
if(intsts & USB_OTG_USBSUSP_FLAG)
|
||||
{
|
||||
usbd_suspend_handler(udev);
|
||||
usb_global_clear_interrupt(usbx, USB_OTG_USBSUSP_FLAG);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb write tx fifo.
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param ept_num: endpoint number
|
||||
* @retval none
|
||||
*/
|
||||
void usb_write_empty_txfifo(usbd_core_type *udev, uint32_t ept_num)
|
||||
{
|
||||
otg_global_type *usbx = udev->usb_reg;
|
||||
usb_ept_info *ept_info = &udev->ept_in[ept_num];
|
||||
uint32_t length = ept_info->total_len - ept_info->trans_len;
|
||||
uint32_t wlen = 0;
|
||||
|
||||
if(length > ept_info->maxpacket)
|
||||
{
|
||||
length = ept_info->maxpacket;
|
||||
}
|
||||
wlen = (length + 3) / 4;
|
||||
|
||||
while((USB_INEPT(usbx, ept_num)->dtxfsts & USB_OTG_DTXFSTS_INEPTFSAV) > wlen &&
|
||||
(ept_info->trans_len < ept_info->total_len) && (ept_info->total_len != 0))
|
||||
{
|
||||
length = ept_info->total_len - ept_info->trans_len;
|
||||
if(length > ept_info->maxpacket)
|
||||
{
|
||||
length = ept_info->maxpacket;
|
||||
}
|
||||
wlen = (length + 3) / 4;
|
||||
usb_write_packet(usbx, ept_info->trans_buf, ept_num, length);
|
||||
|
||||
ept_info->trans_buf += length;
|
||||
ept_info->trans_len += length;
|
||||
|
||||
}
|
||||
if(length <= 0)
|
||||
{
|
||||
OTG_DEVICE(usbx)->diepempmsk &= ~(0x1 << ept_num);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief usb in endpoint handler
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_inept_handler(usbd_core_type *udev)
|
||||
{
|
||||
otg_global_type *usbx = udev->usb_reg;
|
||||
uint32_t ept_num = 0, ept_int;
|
||||
uint32_t intsts;
|
||||
|
||||
/*get all endpoint interrut */
|
||||
intsts = usb_get_all_in_interrupt(usbx);
|
||||
while(intsts)
|
||||
{
|
||||
if(intsts & 0x1)
|
||||
{
|
||||
/* get endpoint interrupt flag */
|
||||
ept_int = usb_ept_in_interrupt(usbx, ept_num);
|
||||
|
||||
/* transfer completed interrupt */
|
||||
if(ept_int & USB_OTG_DIEPINT_XFERC_FLAG)
|
||||
{
|
||||
OTG_DEVICE(usbx)->diepempmsk &= ~(1 << ept_num);
|
||||
usb_ept_in_clear(usbx, ept_num , USB_OTG_DIEPINT_XFERC_FLAG);
|
||||
usbd_core_in_handler(udev, ept_num);
|
||||
}
|
||||
|
||||
/* timeout condition interrupt */
|
||||
if(ept_int & USB_OTG_DIEPINT_TIMEOUT_FLAG)
|
||||
{
|
||||
usb_ept_in_clear(usbx, ept_num , USB_OTG_DIEPINT_TIMEOUT_FLAG);
|
||||
}
|
||||
|
||||
/* in token received when tx fifo is empty */
|
||||
if(ept_int & USB_OTG_DIEPINT_INTKNTXFEMP_FLAG)
|
||||
{
|
||||
usb_ept_in_clear(usbx, ept_num , USB_OTG_DIEPINT_INTKNTXFEMP_FLAG);
|
||||
}
|
||||
|
||||
/* in endpoint nak effective */
|
||||
if(ept_int & USB_OTG_DIEPINT_INEPTNAK_FLAG)
|
||||
{
|
||||
usb_ept_in_clear(usbx, ept_num , USB_OTG_DIEPINT_INEPTNAK_FLAG);
|
||||
}
|
||||
|
||||
/* endpoint disable interrupt */
|
||||
if(ept_int & USB_OTG_DIEPINT_EPTDISD_FLAG)
|
||||
{
|
||||
usb_ept_in_clear(usbx, ept_num , USB_OTG_DIEPINT_EPTDISD_FLAG);
|
||||
}
|
||||
|
||||
/* transmit fifo empty interrupt */
|
||||
if(ept_int & USB_OTG_DIEPINT_TXFEMP_FLAG)
|
||||
{
|
||||
usb_write_empty_txfifo(udev, ept_num);
|
||||
}
|
||||
}
|
||||
ept_num ++;
|
||||
intsts >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb out endpoint handler
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_outept_handler(usbd_core_type *udev)
|
||||
{
|
||||
otg_global_type *usbx = udev->usb_reg;
|
||||
uint32_t ept_num = 0, ept_int;
|
||||
uint32_t intsts;
|
||||
|
||||
/* get all out endpoint interrupt */
|
||||
intsts = usb_get_all_out_interrupt(usbx);
|
||||
|
||||
while(intsts)
|
||||
{
|
||||
if(intsts & 0x1)
|
||||
{
|
||||
/* get out endpoint interrupt */
|
||||
ept_int = usb_ept_out_interrupt(usbx, ept_num);
|
||||
|
||||
/* transfer completed interrupt */
|
||||
if(ept_int & USB_OTG_DOEPINT_XFERC_FLAG)
|
||||
{
|
||||
usb_ept_out_clear(usbx, ept_num , USB_OTG_DOEPINT_XFERC_FLAG);
|
||||
usbd_core_out_handler(udev, ept_num);
|
||||
}
|
||||
|
||||
/* setup phase done interrupt */
|
||||
if(ept_int & USB_OTG_DOEPINT_SETUP_FLAG)
|
||||
{
|
||||
usb_ept_out_clear(usbx, ept_num , USB_OTG_DOEPINT_SETUP_FLAG);
|
||||
usbd_core_setup_handler(udev, ept_num);
|
||||
if(udev->device_addr != 0)
|
||||
{
|
||||
OTG_DEVICE(udev->usb_reg)->dcfg_bit.devaddr = udev->device_addr;
|
||||
udev->device_addr = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* endpoint disable interrupt */
|
||||
if(ept_int & USB_OTG_DOEPINT_OUTTEPD_FLAG)
|
||||
{
|
||||
usb_ept_out_clear(usbx, ept_num , USB_OTG_DOEPINT_OUTTEPD_FLAG);
|
||||
}
|
||||
}
|
||||
ept_num ++;
|
||||
intsts >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb enumeration done handler
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_enumdone_handler(usbd_core_type *udev)
|
||||
{
|
||||
otg_global_type *usbx = udev->usb_reg;
|
||||
|
||||
usb_ept0_setup(usbx);
|
||||
|
||||
usbx->gusbcfg_bit.usbtrdtim = USB_TRDTIM_16;
|
||||
|
||||
/* open endpoint 0 out */
|
||||
usbd_ept_open(udev, 0x00, EPT_CONTROL_TYPE, 0x40);
|
||||
|
||||
/* open endpoint 0 in */
|
||||
usbd_ept_open(udev, 0x80, EPT_CONTROL_TYPE, 0x40);
|
||||
|
||||
/* usb connect state set to default */
|
||||
udev->conn_state = USB_CONN_STATE_DEFAULT;
|
||||
|
||||
/* clear callback */
|
||||
if(udev->class_handler->clear_handler != 0)
|
||||
udev->class_handler->clear_handler(udev);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb rx non-empty handler
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_rxflvl_handler(usbd_core_type *udev)
|
||||
{
|
||||
otg_global_type *usbx = udev->usb_reg;
|
||||
uint32_t stsp;
|
||||
uint32_t count;
|
||||
uint32_t pktsts;
|
||||
usb_ept_info *ept_info;
|
||||
|
||||
/* disable rxflvl interrupt */
|
||||
usb_global_interrupt_enable(usbx, USB_OTG_RXFLVL_INT, FALSE);
|
||||
|
||||
/* get rx status */
|
||||
stsp = usbx->grxstsp;
|
||||
|
||||
/*get the byte count of receive */
|
||||
count = (stsp & USB_OTG_GRXSTSP_BCNT) >> 4;
|
||||
|
||||
/* get packet status */
|
||||
pktsts = (stsp &USB_OTG_GRXSTSP_PKTSTS) >> 17;
|
||||
|
||||
/* get endpoint infomation struct */
|
||||
ept_info = &udev->ept_out[stsp & USB_OTG_GRXSTSP_EPTNUM];
|
||||
|
||||
/* received out data packet */
|
||||
if(pktsts == USB_OUT_STS_DATA)
|
||||
{
|
||||
if(count != 0)
|
||||
{
|
||||
/* read packet to buffer */
|
||||
usb_read_packet(usbx, ept_info->trans_buf, (stsp & USB_OTG_GRXSTSP_EPTNUM), count);
|
||||
ept_info->trans_buf += count;
|
||||
ept_info->trans_len += count;
|
||||
|
||||
}
|
||||
}
|
||||
/* setup data received */
|
||||
else if ( pktsts == USB_SETUP_STS_DATA)
|
||||
{
|
||||
/* read packet to buffer */
|
||||
usb_read_packet(usbx, udev->setup_buffer, (stsp & USB_OTG_GRXSTSP_EPTNUM), count);
|
||||
ept_info->trans_len += count;
|
||||
}
|
||||
|
||||
/* enable rxflvl interrupt */
|
||||
usb_global_interrupt_enable(usbx, USB_OTG_RXFLVL_INT, TRUE);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb disconnect handler
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_discon_handler(usbd_core_type *udev)
|
||||
{
|
||||
/* disconnect callback handler */
|
||||
if(udev->class_handler->event_handler != 0)
|
||||
udev->class_handler->event_handler(udev, USBD_DISCONNECT_EVNET);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief usb incomplete out handler
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_incomisoout_handler(usbd_core_type *udev)
|
||||
{
|
||||
if(udev->class_handler->event_handler != 0)
|
||||
udev->class_handler->event_handler(udev, USBD_OUTISOINCOM_EVENT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb incomplete in handler
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_incomisioin_handler(usbd_core_type *udev)
|
||||
{
|
||||
if(udev->class_handler->event_handler != 0)
|
||||
udev->class_handler->event_handler(udev, USBD_INISOINCOM_EVENT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device reset interrupt request handler.
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_reset_handler(usbd_core_type *udev)
|
||||
{
|
||||
otg_global_type *usbx = udev->usb_reg;
|
||||
otg_device_type *dev = OTG_DEVICE(usbx);
|
||||
uint32_t i_index = 0;
|
||||
|
||||
/* disable remote wakeup singal */
|
||||
dev->dctl_bit.rwkupsig = FALSE;
|
||||
|
||||
/* endpoint fifo alloc */
|
||||
usbd_fifo_alloc(udev);
|
||||
|
||||
/* flush all tx fifo */
|
||||
usb_flush_tx_fifo(usbx, 0x10);
|
||||
|
||||
/* clear in and out endpoint interrupt flag */
|
||||
for(i_index = 0; i_index < USB_EPT_MAX_NUM; i_index ++)
|
||||
{
|
||||
USB_INEPT(usbx, i_index)->diepint = 0xFF;
|
||||
USB_OUTEPT(usbx, i_index)->doepint = 0xFF;
|
||||
}
|
||||
|
||||
/* clear endpoint flag */
|
||||
dev->daint = 0xFFFFFFFF;
|
||||
|
||||
/*clear endpoint interrupt mask */
|
||||
dev->daintmsk = 0x10001;
|
||||
|
||||
/* enable out endpoint xfer, eptdis, setup interrupt mask */
|
||||
dev->doepmsk_bit.xfercmsk = TRUE;
|
||||
dev->doepmsk_bit.eptdismsk = TRUE;
|
||||
dev->doepmsk_bit.setupmsk = TRUE;
|
||||
|
||||
/* enable in endpoint xfer, eptdis, timeout interrupt mask */
|
||||
dev->diepmsk_bit.xfercmsk = TRUE;
|
||||
dev->diepmsk_bit.eptdismsk = TRUE;
|
||||
dev->diepmsk_bit.timeoutmsk = TRUE;
|
||||
|
||||
/* set device address to 0 */
|
||||
usb_set_address(usbx, 0);
|
||||
|
||||
/* enable endpoint 0 */
|
||||
usb_ept0_start(usbx);
|
||||
|
||||
/* usb connect state set to default */
|
||||
udev->conn_state = USB_CONN_STATE_DEFAULT;
|
||||
|
||||
/* user define reset event */
|
||||
if(udev->class_handler->event_handler)
|
||||
udev->class_handler->event_handler(udev, USBD_RESET_EVENT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device sof interrupt request handler.
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_sof_handler(usbd_core_type *udev)
|
||||
{
|
||||
/* user sof handler in class define */
|
||||
if(udev->class_handler->sof_handler)
|
||||
udev->class_handler->sof_handler(udev);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device suspend interrupt request handler.
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_suspend_handler(usbd_core_type *udev)
|
||||
{
|
||||
otg_global_type *usbx = udev->usb_reg;
|
||||
|
||||
if(OTG_DEVICE(usbx)->dsts_bit.suspsts)
|
||||
{
|
||||
/* save connect state */
|
||||
udev->old_conn_state = udev->conn_state;
|
||||
|
||||
/* set current state to suspend */
|
||||
udev->conn_state = USB_CONN_STATE_SUSPENDED;
|
||||
|
||||
/* enter suspend mode */
|
||||
usbd_enter_suspend(udev);
|
||||
|
||||
/* user suspend handler */
|
||||
if(udev->class_handler->event_handler != 0)
|
||||
udev->class_handler->event_handler(udev, USBD_SUSPEND_EVENT);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device wakup interrupt request handler.
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_wakeup_handler(usbd_core_type *udev)
|
||||
{
|
||||
otg_global_type *usbx = udev->usb_reg;
|
||||
|
||||
/* clear remote wakeup bit */
|
||||
OTG_DEVICE(usbx)->dctl_bit.rwkupsig = FALSE;
|
||||
|
||||
/* exit suspend mode */
|
||||
usb_open_phy_clk(udev->usb_reg);
|
||||
|
||||
/* restore connect state */
|
||||
udev->conn_state = udev->old_conn_state;
|
||||
|
||||
/* user suspend handler */
|
||||
if(udev->class_handler->event_handler != 0)
|
||||
udev->class_handler->event_handler(udev, USBD_WAKEUP_EVENT);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -0,0 +1,534 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file usbd_sdr.c
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief usb standard device request
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
#include "usbd_sdr.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_middlewares_usbd_drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_drivers_standard_request
|
||||
* @brief usb device standard_request
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_sdr_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
static usb_sts_type usbd_get_descriptor(usbd_core_type *udev);
|
||||
static usb_sts_type usbd_set_address(usbd_core_type *udev);
|
||||
static usb_sts_type usbd_get_status(usbd_core_type *udev);
|
||||
static usb_sts_type usbd_clear_feature(usbd_core_type *udev);
|
||||
static usb_sts_type usbd_set_feature(usbd_core_type *udev);
|
||||
static usb_sts_type usbd_get_configuration(usbd_core_type *udev);
|
||||
static usb_sts_type usbd_set_configuration(usbd_core_type *udev);
|
||||
|
||||
/**
|
||||
* @brief usb parse standard setup request
|
||||
* @param setup: setup structure
|
||||
* @param buf: setup buffer
|
||||
* @retval none
|
||||
*/
|
||||
void usbd_setup_request_parse(usb_setup_type *setup, uint8_t *buf)
|
||||
{
|
||||
setup->bmRequestType = *(uint8_t *) buf;
|
||||
setup->bRequest = *(uint8_t *) (buf + 1);
|
||||
setup->wValue = SWAPBYTE(buf + 2);
|
||||
setup->wIndex = SWAPBYTE(buf + 4);
|
||||
setup->wLength = SWAPBYTE(buf + 6);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get usb standard device description request
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
static usb_sts_type usbd_get_descriptor(usbd_core_type *udev)
|
||||
{
|
||||
usb_sts_type ret = USB_OK;
|
||||
uint16_t len = 0;
|
||||
usbd_desc_t *desc = NULL;
|
||||
uint8_t desc_type = udev->setup.wValue >> 8;
|
||||
switch(desc_type)
|
||||
{
|
||||
case USB_DESCIPTOR_TYPE_DEVICE:
|
||||
desc = udev->desc_handler->get_device_descriptor();
|
||||
break;
|
||||
case USB_DESCIPTOR_TYPE_CONFIGURATION:
|
||||
desc = udev->desc_handler->get_device_configuration();
|
||||
break;
|
||||
case USB_DESCIPTOR_TYPE_STRING:
|
||||
{
|
||||
uint8_t str_desc = (uint8_t)udev->setup.wValue;
|
||||
switch(str_desc)
|
||||
{
|
||||
case USB_LANGID_STRING:
|
||||
desc = udev->desc_handler->get_device_lang_id();
|
||||
break;
|
||||
case USB_MFC_STRING:
|
||||
desc = udev->desc_handler->get_device_manufacturer_string();
|
||||
break;
|
||||
case USB_PRODUCT_STRING:
|
||||
desc = udev->desc_handler->get_device_product_string();
|
||||
break;
|
||||
case USB_SERIAL_STRING:
|
||||
desc = udev->desc_handler->get_device_serial_string();
|
||||
break;
|
||||
case USB_CONFIG_STRING:
|
||||
desc = udev->desc_handler->get_device_config_string();
|
||||
break;
|
||||
case USB_INTERFACE_STRING:
|
||||
desc = udev->desc_handler->get_device_interface_string();
|
||||
break;
|
||||
default:
|
||||
usbd_ctrl_unsupport(udev);
|
||||
return ret;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case USB_DESCIPTOR_TYPE_DEVICE_QUALIFIER:
|
||||
usbd_ctrl_unsupport(udev);
|
||||
break;
|
||||
case USB_DESCIPTOR_TYPE_OTHER_SPEED:
|
||||
usbd_ctrl_unsupport(udev);
|
||||
return ret;
|
||||
default:
|
||||
usbd_ctrl_unsupport(udev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if(desc != NULL)
|
||||
{
|
||||
if((desc->length != 0) && (udev->setup.wLength != 0))
|
||||
{
|
||||
len = MIN(desc->length , udev->setup.wLength);
|
||||
usbd_ctrl_send(udev, desc->descriptor, len);
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this request sets the device address
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
static usb_sts_type usbd_set_address(usbd_core_type *udev)
|
||||
{
|
||||
usb_sts_type ret = USB_OK;
|
||||
usb_setup_type *setup = &udev->setup;
|
||||
uint8_t dev_addr;
|
||||
|
||||
/* if wIndex or wLength are non-zero, then the behavior of
|
||||
the device is not specified
|
||||
*/
|
||||
if(setup->wIndex == 0 && setup->wLength == 0)
|
||||
{
|
||||
dev_addr = (uint8_t)(setup->wValue) & 0x7f;
|
||||
|
||||
/* device behavior when this request is received
|
||||
while the device is in the configured state is not specified.*/
|
||||
if(udev->conn_state == USB_CONN_STATE_CONFIGURED )
|
||||
{
|
||||
usbd_ctrl_unsupport(udev);
|
||||
}
|
||||
else
|
||||
{
|
||||
udev->device_addr = dev_addr;
|
||||
|
||||
if(dev_addr != 0)
|
||||
{
|
||||
udev->conn_state = USB_CONN_STATE_ADDRESSED;
|
||||
}
|
||||
else
|
||||
{
|
||||
udev->conn_state = USB_CONN_STATE_DEFAULT;
|
||||
}
|
||||
usbd_ctrl_send_status(udev);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
usbd_ctrl_unsupport(udev);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get usb status request
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
static usb_sts_type usbd_get_status(usbd_core_type *udev)
|
||||
{
|
||||
usb_sts_type ret = USB_OK;
|
||||
switch(udev->conn_state)
|
||||
{
|
||||
case USB_CONN_STATE_ADDRESSED:
|
||||
case USB_CONN_STATE_CONFIGURED:
|
||||
if(udev->remote_wakup)
|
||||
{
|
||||
udev->config_status |= USB_CONF_REMOTE_WAKEUP;
|
||||
}
|
||||
usbd_ctrl_send(udev, (uint8_t *)(&udev->config_status), 2);
|
||||
break;
|
||||
default:
|
||||
usbd_ctrl_unsupport(udev);
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear usb feature request
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
static usb_sts_type usbd_clear_feature(usbd_core_type *udev)
|
||||
{
|
||||
usb_sts_type ret = USB_OK;
|
||||
usb_setup_type *setup = &udev->setup;
|
||||
switch(udev->conn_state)
|
||||
{
|
||||
case USB_CONN_STATE_ADDRESSED:
|
||||
case USB_CONN_STATE_CONFIGURED:
|
||||
if(setup->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
||||
{
|
||||
udev->remote_wakup = 0;
|
||||
udev->config_status &= ~USB_CONF_REMOTE_WAKEUP;
|
||||
udev->class_handler->setup_handler(udev, &udev->setup);
|
||||
usbd_ctrl_send_status(udev);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
usbd_ctrl_unsupport(udev);
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set usb feature request
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
static usb_sts_type usbd_set_feature(usbd_core_type *udev)
|
||||
{
|
||||
usb_sts_type ret = USB_OK;
|
||||
usb_setup_type *setup = &udev->setup;
|
||||
if(setup->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
||||
{
|
||||
udev->remote_wakup = 1;
|
||||
udev->class_handler->setup_handler(udev, &udev->setup);
|
||||
usbd_ctrl_send_status(udev);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get usb configuration request
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
static usb_sts_type usbd_get_configuration(usbd_core_type *udev)
|
||||
{
|
||||
usb_sts_type ret = USB_OK;
|
||||
usb_setup_type *setup = &udev->setup;
|
||||
if(setup->wLength != 1)
|
||||
{
|
||||
usbd_ctrl_unsupport(udev);
|
||||
}
|
||||
else
|
||||
{
|
||||
switch(udev->conn_state)
|
||||
{
|
||||
case USB_CONN_STATE_ADDRESSED:
|
||||
udev->default_config = 0;
|
||||
usbd_ctrl_send(udev, (uint8_t *)(&udev->default_config), 1);
|
||||
break;
|
||||
case USB_CONN_STATE_CONFIGURED:
|
||||
usbd_ctrl_send(udev, (uint8_t *)(&udev->dev_config), 1);
|
||||
break;
|
||||
default:
|
||||
usbd_ctrl_unsupport(udev);
|
||||
break;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief sets the usb device configuration request
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
static usb_sts_type usbd_set_configuration(usbd_core_type *udev)
|
||||
{
|
||||
usb_sts_type ret = USB_OK;
|
||||
static uint8_t config_value;
|
||||
usb_setup_type *setup = &udev->setup;
|
||||
config_value = (uint8_t)setup->wValue;
|
||||
|
||||
if(setup->wIndex == 0 && setup->wLength == 0)
|
||||
{
|
||||
switch(udev->conn_state)
|
||||
{
|
||||
case USB_CONN_STATE_ADDRESSED:
|
||||
if(config_value)
|
||||
{
|
||||
udev->dev_config = config_value;
|
||||
udev->conn_state = USB_CONN_STATE_CONFIGURED;
|
||||
udev->class_handler->init_handler(udev);
|
||||
usbd_ctrl_send_status(udev);
|
||||
}
|
||||
else
|
||||
{
|
||||
usbd_ctrl_send_status(udev);
|
||||
}
|
||||
|
||||
break;
|
||||
case USB_CONN_STATE_CONFIGURED:
|
||||
if(config_value == 0)
|
||||
{
|
||||
udev->conn_state = USB_CONN_STATE_ADDRESSED;
|
||||
udev->dev_config = config_value;
|
||||
udev->class_handler->clear_handler(udev);
|
||||
usbd_ctrl_send_status(udev);
|
||||
}
|
||||
else if(config_value == udev->dev_config)
|
||||
{
|
||||
udev->class_handler->clear_handler(udev);
|
||||
udev->dev_config = config_value;
|
||||
udev->class_handler->init_handler(udev);
|
||||
usbd_ctrl_send_status(udev);
|
||||
}
|
||||
else
|
||||
{
|
||||
usbd_ctrl_send_status(udev);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
usbd_ctrl_unsupport(udev);
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
usbd_ctrl_unsupport(udev);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief standard usb device requests
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
usb_sts_type usbd_device_request(usbd_core_type *udev)
|
||||
{
|
||||
usb_sts_type ret = USB_OK;
|
||||
usb_setup_type *setup = &udev->setup;
|
||||
if((setup->bmRequestType & USB_REQ_TYPE_RESERVED) != USB_REQ_TYPE_STANDARD)
|
||||
{
|
||||
udev->class_handler->setup_handler(udev, &udev->setup);
|
||||
return ret;
|
||||
}
|
||||
switch(udev->setup.bRequest)
|
||||
{
|
||||
case USB_STD_REQ_GET_STATUS:
|
||||
usbd_get_status(udev);
|
||||
break;
|
||||
case USB_STD_REQ_CLEAR_FEATURE:
|
||||
usbd_clear_feature(udev);
|
||||
break;
|
||||
case USB_STD_REQ_SET_FEATURE:
|
||||
usbd_set_feature(udev);
|
||||
break;
|
||||
case USB_STD_REQ_SET_ADDRESS:
|
||||
usbd_set_address(udev);
|
||||
break;
|
||||
case USB_STD_REQ_GET_DESCRIPTOR:
|
||||
usbd_get_descriptor(udev);
|
||||
break;
|
||||
case USB_STD_REQ_GET_CONFIGURATION:
|
||||
usbd_get_configuration(udev);
|
||||
break;
|
||||
case USB_STD_REQ_SET_CONFIGURATION:
|
||||
usbd_set_configuration(udev);
|
||||
break;
|
||||
default:
|
||||
usbd_ctrl_unsupport(udev);
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief standard usb interface requests
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
usb_sts_type usbd_interface_request(usbd_core_type *udev)
|
||||
{
|
||||
usb_sts_type ret = USB_OK;
|
||||
usb_setup_type *setup = &udev->setup;
|
||||
switch(udev->conn_state)
|
||||
{
|
||||
case USB_CONN_STATE_CONFIGURED:
|
||||
udev->class_handler->setup_handler(udev, &udev->setup);
|
||||
if(setup->wLength == 0)
|
||||
{
|
||||
usbd_ctrl_send_status(udev);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
usbd_ctrl_unsupport(udev);
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief standard usb endpoint requests
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
usb_sts_type usbd_endpoint_request(usbd_core_type *udev)
|
||||
{
|
||||
usb_sts_type ret = USB_OK;
|
||||
usb_setup_type *setup = &udev->setup;
|
||||
uint8_t ept_addr = LBYTE(setup->wIndex);
|
||||
usb_ept_info *ept_info;
|
||||
|
||||
if((setup->bmRequestType & USB_REQ_TYPE_RESERVED) == USB_REQ_TYPE_CLASS)
|
||||
{
|
||||
udev->class_handler->setup_handler(udev, &udev->setup);
|
||||
}
|
||||
switch(setup->bRequest)
|
||||
{
|
||||
case USB_STD_REQ_GET_STATUS:
|
||||
switch(udev->conn_state)
|
||||
{
|
||||
case USB_CONN_STATE_ADDRESSED:
|
||||
if((ept_addr & 0x7F) != 0)
|
||||
{
|
||||
usbd_set_stall(udev, ept_addr);
|
||||
}
|
||||
break;
|
||||
case USB_CONN_STATE_CONFIGURED:
|
||||
{
|
||||
if((ept_addr & 0x80) != 0)
|
||||
{
|
||||
ept_info = &udev->ept_in[ept_addr & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
ept_info = &udev->ept_out[ept_addr & 0x7F];
|
||||
}
|
||||
if(ept_info->stall == 1)
|
||||
{
|
||||
ept_info->status = 0x0001;
|
||||
}
|
||||
else
|
||||
{
|
||||
ept_info->status = 0x0000;
|
||||
}
|
||||
usbd_ctrl_send(udev, (uint8_t *)(&ept_info->status), 2);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
usbd_ctrl_unsupport(udev);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case USB_STD_REQ_CLEAR_FEATURE:
|
||||
switch(udev->conn_state)
|
||||
{
|
||||
case USB_CONN_STATE_ADDRESSED:
|
||||
if((ept_addr != 0x00) && (ept_addr != 0x80))
|
||||
{
|
||||
usbd_set_stall(udev, ept_addr);
|
||||
}
|
||||
break;
|
||||
case USB_CONN_STATE_CONFIGURED:
|
||||
if(setup->wValue == USB_FEATURE_EPT_HALT)
|
||||
{
|
||||
if((ept_addr & 0x7F) != 0x00 )
|
||||
{
|
||||
usbd_clear_stall(udev, ept_addr);
|
||||
udev->class_handler->setup_handler(udev, &udev->setup);
|
||||
}
|
||||
usbd_ctrl_send_status(udev);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
usbd_ctrl_unsupport(udev);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case USB_STD_REQ_SET_FEATURE:
|
||||
switch(udev->conn_state)
|
||||
{
|
||||
case USB_CONN_STATE_ADDRESSED:
|
||||
if((ept_addr != 0x00) && (ept_addr != 0x80))
|
||||
{
|
||||
usbd_set_stall(udev, ept_addr);
|
||||
}
|
||||
break;
|
||||
case USB_CONN_STATE_CONFIGURED:
|
||||
if(setup->wValue == USB_FEATURE_EPT_HALT)
|
||||
{
|
||||
if((ept_addr != 0x00) && (ept_addr != 0x80))
|
||||
{
|
||||
usbd_set_stall(udev, ept_addr);
|
||||
}
|
||||
}
|
||||
udev->class_handler->setup_handler(udev, &udev->setup);
|
||||
usbd_ctrl_send_status(udev);
|
||||
break;
|
||||
default:
|
||||
usbd_ctrl_unsupport(udev);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
usbd_ctrl_unsupport(udev);
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -1,241 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* File : usb_core.h
|
||||
* Version: V1.2.2
|
||||
* Date : 2020-07-01
|
||||
* Brief : Standard protocol processing functions prototypes
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_CORE_H
|
||||
#define __USB_CORE_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
typedef enum _CONTROL_STATE
|
||||
{
|
||||
WAIT_SETUP, /* 0 */
|
||||
SETTING_UP, /* 1 */
|
||||
IN_DATA, /* 2 */
|
||||
OUT_DATA, /* 3 */
|
||||
LAST_IN_DATA, /* 4 */
|
||||
LAST_OUT_DATA, /* 5 */
|
||||
WAIT_STATUS_IN, /* 7 */
|
||||
WAIT_STATUS_OUT, /* 8 */
|
||||
STALLED, /* 9 */
|
||||
PAUSE /* 10 */
|
||||
} CONTROL_STATE; /* The state machine states of a control pipe */
|
||||
|
||||
typedef struct OneDescriptor
|
||||
{
|
||||
uint8_t *Descriptor;
|
||||
uint16_t Descriptor_Size;
|
||||
}
|
||||
ONE_DESCRIPTOR, *PONE_DESCRIPTOR;
|
||||
/* All the request process routines return a value of this type
|
||||
If the return value is not SUCCESS or NOT_READY,
|
||||
the software will STALL the correspond endpoint */
|
||||
typedef enum _RESULT
|
||||
{
|
||||
USB_SUCCESS = 0, /* Process successfully */
|
||||
USB_ERROR,
|
||||
USB_UNSUPPORT,
|
||||
USB_NOT_READY /* The process has not been finished, endpoint will be
|
||||
NAK to further request */
|
||||
} RESULT;
|
||||
|
||||
|
||||
/*-*-*-*-*-*-*-*-*-*-* Definitions for endpoint level -*-*-*-*-*-*-*-*-*-*-*-*/
|
||||
typedef struct _ENDPOINT_INFO
|
||||
{
|
||||
/* When send data out of the device,
|
||||
CopyData() is used to get data buffer 'Length' bytes data
|
||||
if Length is 0,
|
||||
CopyData() returns the total length of the data
|
||||
if the request is not supported, returns 0
|
||||
(NEW Feature )
|
||||
if CopyData() returns -1, the calling routine should not proceed
|
||||
further and will resume the SETUP process by the class device
|
||||
if Length is not 0,
|
||||
CopyData() returns a pointer to indicate the data location
|
||||
Usb_wLength is the data remain to be sent,
|
||||
Usb_wOffset is the Offset of original data
|
||||
When receive data from the host,
|
||||
CopyData() is used to get user data buffer which is capable
|
||||
of Length bytes data to copy data from the endpoint buffer.
|
||||
if Length is 0,
|
||||
CopyData() returns the available data length,
|
||||
if Length is not 0,
|
||||
CopyData() returns user buffer address
|
||||
Usb_rLength is the data remain to be received,
|
||||
Usb_rPointer is the Offset of data buffer
|
||||
*/
|
||||
uint16_t Usb_wLength;
|
||||
uint16_t Usb_wOffset;
|
||||
uint16_t PacketSize;
|
||||
uint8_t *(*CopyData)(uint16_t Length);
|
||||
}ENDPOINT_INFO;
|
||||
|
||||
/*-*-*-*-*-*-*-*-*-*-*-* Definitions for device level -*-*-*-*-*-*-*-*-*-*-*-*/
|
||||
|
||||
typedef struct _DEVICE
|
||||
{
|
||||
uint8_t Total_Endpoint; /* Number of endpoints that are used */
|
||||
uint8_t Total_Configuration;/* Number of configuration available */
|
||||
}
|
||||
DEVICE;
|
||||
|
||||
typedef union
|
||||
{
|
||||
uint16_t w;
|
||||
struct BW
|
||||
{
|
||||
uint8_t bb1;
|
||||
uint8_t bb0;
|
||||
}
|
||||
bw;
|
||||
} uint16_t_uint8_t;
|
||||
|
||||
typedef struct _DEVICE_INFO
|
||||
{
|
||||
uint8_t USBbmRequestType; /* bmRequestType */
|
||||
uint8_t USBbRequest; /* bRequest */
|
||||
uint16_t_uint8_t USBwValues; /* wValue */
|
||||
uint16_t_uint8_t USBwIndexs; /* wIndex */
|
||||
uint16_t_uint8_t USBwLengths; /* wLength */
|
||||
|
||||
uint8_t ControlState; /* of type CONTROL_STATE */
|
||||
uint8_t Current_Feature;
|
||||
uint8_t Current_Configuration; /* Selected configuration */
|
||||
uint8_t Current_Interface; /* Selected interface of current configuration */
|
||||
uint8_t Current_AlternateSetting;/* Selected Alternate Setting of current
|
||||
interface*/
|
||||
|
||||
ENDPOINT_INFO Ctrl_Info;
|
||||
}DEVICE_INFO;
|
||||
|
||||
typedef struct _DEVICE_PROP
|
||||
{
|
||||
void (*Init)(void); /* Initialize the device */
|
||||
void (*Reset)(void); /* Reset routine of this device */
|
||||
|
||||
/* Device dependent process after the status stage */
|
||||
void (*Process_Status_IN)(void);
|
||||
void (*Process_Status_OUT)(void);
|
||||
|
||||
/* Procedure of process on setup stage of a class specified request with data stage */
|
||||
/* All class specified requests with data stage are processed in Class_Data_Setup
|
||||
Class_Data_Setup()
|
||||
responses to check all special requests and fills ENDPOINT_INFO
|
||||
according to the request
|
||||
If IN tokens are expected, then wLength & wOffset will be filled
|
||||
with the total transferring bytes and the starting position
|
||||
If OUT tokens are expected, then rLength & rOffset will be filled
|
||||
with the total expected bytes and the starting position in the buffer
|
||||
|
||||
If the request is valid, Class_Data_Setup returns SUCCESS, else UNSUPPORT
|
||||
|
||||
CAUTION:
|
||||
Since GET_CONFIGURATION & GET_INTERFACE are highly related to
|
||||
the individual classes, they will be checked and processed here.
|
||||
*/
|
||||
RESULT (*Class_Data_Setup)(uint8_t RequestNo);
|
||||
|
||||
/* Procedure of process on setup stage of a class specified request without data stage */
|
||||
/* All class specified requests without data stage are processed in Class_NoData_Setup
|
||||
Class_NoData_Setup
|
||||
responses to check all special requests and perform the request
|
||||
|
||||
CAUTION:
|
||||
Since SET_CONFIGURATION & SET_INTERFACE are highly related to
|
||||
the individual classes, they will be checked and processed here.
|
||||
*/
|
||||
RESULT (*Class_NoData_Setup)(uint8_t RequestNo);
|
||||
|
||||
/*Class_Get_Interface_Setting
|
||||
This function is used by the file usb_core.c to test if the selected Interface
|
||||
and Alternate Setting (uint8_t Interface, uint8_t AlternateSetting) are supported by
|
||||
the application.
|
||||
This function is writing by user. It should return "SUCCESS" if the Interface
|
||||
and Alternate Setting are supported by the application or "UNSUPPORT" if they
|
||||
are not supported. */
|
||||
|
||||
RESULT (*Class_Get_Interface_Setting)(uint8_t Interface, uint8_t AlternateSetting);
|
||||
|
||||
uint8_t* (*GetDeviceDescriptor)(uint16_t Length);
|
||||
uint8_t* (*GetConfigDescriptor)(uint16_t Length);
|
||||
uint8_t* (*GetStringDescriptor)(uint16_t Length);
|
||||
|
||||
/* This field is not used in current library version. It is kept only for
|
||||
compatibility with previous versions */
|
||||
void* RxEP_buffer;
|
||||
|
||||
uint8_t MaxPacketSize;
|
||||
|
||||
}DEVICE_PROP;
|
||||
|
||||
typedef struct _USER_STANDARD_REQUESTS
|
||||
{
|
||||
void (*User_GetConfiguration)(void); /* Get Configuration */
|
||||
void (*User_SetConfiguration)(void); /* Set Configuration */
|
||||
void (*User_GetInterface)(void); /* Get Interface */
|
||||
void (*User_SetInterface)(void); /* Set Interface */
|
||||
void (*User_GetStatus)(void); /* Get Status */
|
||||
void (*User_ClearFeature)(void); /* Clear Feature */
|
||||
void (*User_SetEndPointFeature)(void); /* Set Endpoint Feature */
|
||||
void (*User_SetDeviceFeature)(void); /* Set Device Feature */
|
||||
void (*User_SetDeviceAddress)(void); /* Set Device Address */
|
||||
}
|
||||
USER_STANDARD_REQUESTS;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
#define Type_Recipient (pInformation->USBbmRequestType & (REQUEST_TYPE | RECIPIENT))
|
||||
|
||||
#define Usb_rLength Usb_wLength
|
||||
#define Usb_rOffset Usb_wOffset
|
||||
|
||||
#define USBwValue USBwValues.w
|
||||
#define USBwValue0 USBwValues.bw.bb0
|
||||
#define USBwValue1 USBwValues.bw.bb1
|
||||
#define USBwIndex USBwIndexs.w
|
||||
#define USBwIndex0 USBwIndexs.bw.bb0
|
||||
#define USBwIndex1 USBwIndexs.bw.bb1
|
||||
#define USBwLength USBwLengths.w
|
||||
#define USBwLength0 USBwLengths.bw.bb0
|
||||
#define USBwLength1 USBwLengths.bw.bb1
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
uint8_t Setup0_Process(void);
|
||||
uint8_t Post0_Process(void);
|
||||
uint8_t Out0_Process(void);
|
||||
uint8_t In0_Process(void);
|
||||
|
||||
RESULT Standard_SetEndPointFeature(void);
|
||||
RESULT Standard_SetDeviceFeature(void);
|
||||
|
||||
uint8_t *Standard_GetConfiguration(uint16_t Length);
|
||||
RESULT Standard_SetConfiguration(void);
|
||||
uint8_t *Standard_GetInterface(uint16_t Length);
|
||||
RESULT Standard_SetInterface(void);
|
||||
uint8_t *Standard_GetDescriptorData(uint16_t Length, PONE_DESCRIPTOR pDesc);
|
||||
|
||||
uint8_t *Standard_GetStatus(uint16_t Length);
|
||||
RESULT Standard_ClearFeature(void);
|
||||
void SetDeviceAddress(uint8_t);
|
||||
void NOP_Process(void);
|
||||
|
||||
extern DEVICE_PROP Device_Property;
|
||||
extern USER_STANDARD_REQUESTS User_Standard_Requests;
|
||||
extern DEVICE Device_Table;
|
||||
extern DEVICE_INFO Device_Info;
|
||||
|
||||
/* cells saving status during interrupt servicing */
|
||||
extern __IO uint16_t SaveRState;
|
||||
extern __IO uint16_t SaveTState;
|
||||
|
||||
#endif /* __USB_CORE_H */
|
||||
|
||||
|
||||
@@ -1,75 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* File : usb_def.h
|
||||
* Version: V1.2.2
|
||||
* Date : 2020-07-01
|
||||
* Brief : Definitions related to USB Core
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_DEF_H
|
||||
#define __USB_DEF_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
typedef enum _RECIPIENT_TYPE
|
||||
{
|
||||
DEVICE_RECIPIENT, /* Recipient device */
|
||||
INTERFACE_RECIPIENT, /* Recipient interface */
|
||||
ENDPOINT_RECIPIENT, /* Recipient endpoint */
|
||||
OTHER_RECIPIENT
|
||||
} RECIPIENT_TYPE;
|
||||
|
||||
|
||||
typedef enum _STANDARD_REQUESTS
|
||||
{
|
||||
GET_STATUS = 0,
|
||||
CLEAR_FEATURE,
|
||||
RESERVED1,
|
||||
SET_FEATURE,
|
||||
RESERVED2,
|
||||
SET_ADDRESS,
|
||||
GET_DESCRIPTOR,
|
||||
SET_DESCRIPTOR,
|
||||
GET_CONFIGURATION,
|
||||
SET_CONFIGURATION,
|
||||
GET_INTERFACE,
|
||||
SET_INTERFACE,
|
||||
TOTAL_sREQUEST, /* Total number of Standard request */
|
||||
SYNCH_FRAME = 12
|
||||
} STANDARD_REQUESTS;
|
||||
|
||||
/* Definition of "USBwValue" */
|
||||
typedef enum _DESCRIPTOR_TYPE
|
||||
{
|
||||
DEVICE_DESCRIPTOR = 1,
|
||||
CONFIG_DESCRIPTOR,
|
||||
STRING_DESCRIPTOR,
|
||||
INTERFACE_DESCRIPTOR,
|
||||
ENDPOINT_DESCRIPTOR
|
||||
} DESCRIPTOR_TYPE;
|
||||
|
||||
/* Feature selector of a SET_FEATURE or CLEAR_FEATURE */
|
||||
typedef enum _FEATURE_SELECTOR
|
||||
{
|
||||
ENDPOINT_STALL,
|
||||
DEVICE_REMOTE_WAKEUP
|
||||
} FEATURE_SELECTOR;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Definition of "USBbmRequestType" */
|
||||
#define REQUEST_TYPE 0x60 /* Mask to get request type */
|
||||
#define STANDARD_REQUEST 0x00 /* Standard request */
|
||||
#define CLASS_REQUEST 0x20 /* Class request */
|
||||
#define VENDOR_REQUEST 0x40 /* Vendor request */
|
||||
|
||||
#define RECIPIENT 0x1F /* Mask to get recipient */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
#endif /* __USB_DEF_H */
|
||||
|
||||
|
||||
|
||||
@@ -1,51 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* File : usb_init.h
|
||||
* Version: V1.2.2
|
||||
* Date : 2020-07-01
|
||||
* Brief : Initialization routines & global variables
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_INIT_H
|
||||
#define __USB_INIT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void USB_Init(void);
|
||||
|
||||
/* External variables --------------------------------------------------------*/
|
||||
/* The number of current endpoint, it will be used to specify an endpoint */
|
||||
extern uint8_t EPindex;
|
||||
/* The number of current device, it is an index to the Device_Table */
|
||||
/*extern uint8_t Device_no; */
|
||||
/* Points to the DEVICE_INFO structure of current device */
|
||||
/* The purpose of this register is to speed up the execution */
|
||||
extern DEVICE_INFO* pInformation;
|
||||
/* Points to the DEVICE_PROP structure of current device */
|
||||
/* The purpose of this register is to speed up the execution */
|
||||
extern DEVICE_PROP* pProperty;
|
||||
/* Temporary save the state of Rx & Tx status. */
|
||||
/* Whenever the Rx or Tx state is changed, its value is saved */
|
||||
/* in this variable first and will be set to the EPRB or EPRA */
|
||||
/* at the end of interrupt process */
|
||||
extern USER_STANDARD_REQUESTS *pUser_Standard_Requests;
|
||||
|
||||
extern uint16_t SaveState ;
|
||||
extern uint16_t wInterrupt_Mask;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __USB_INIT_H */
|
||||
|
||||
|
||||
@@ -1,28 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* File : usb_int.h
|
||||
* Version: V1.2.2
|
||||
* Date : 2020-07-01
|
||||
* Brief : Endpoint CTRF (Low and High) interrupt's service routines prototypes
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_INT_H
|
||||
#define __USB_INT_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void CTR_LP(void);
|
||||
void CTR_HP(void);
|
||||
|
||||
/* External variables --------------------------------------------------------*/
|
||||
|
||||
#endif /* __USB_INT_H */
|
||||
|
||||
|
||||
@@ -1,35 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* File : usb_lib.h
|
||||
* Version: V1.2.2
|
||||
* Date : 2020-07-01
|
||||
* Brief : USB library include files
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_LIB_H
|
||||
#define __USB_LIB_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "hw_config.h"
|
||||
#include "usb_type.h"
|
||||
#include "usb_regs.h"
|
||||
#include "usb_def.h"
|
||||
#include "usb_core.h"
|
||||
#include "usb_init.h"
|
||||
#include "usb_sil.h"
|
||||
#include "usb_mem.h"
|
||||
#include "usb_int.h"
|
||||
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* External variables --------------------------------------------------------*/
|
||||
|
||||
#endif /* __USB_LIB_H */
|
||||
|
||||
|
||||
@@ -1,34 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* File : usb_mem.h
|
||||
* Version: V1.2.2
|
||||
* Date : 2020-07-01
|
||||
* Brief : Utility prototypes functions for memory/PMA transfers
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_MEM_H
|
||||
#define __USB_MEM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void UserToPMABufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
void PMAToUserBufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
|
||||
/* External variables --------------------------------------------------------*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__USB_MEM_H*/
|
||||
|
||||
|
||||
@@ -1,672 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* File : usb_reg.h
|
||||
* Version: V1.2.2
|
||||
* Date : 2020-07-01
|
||||
* Brief : Interface prototype functions to USB cell registers
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_REGS_H
|
||||
#define __USB_REGS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
typedef enum _EP_DBUF_DIR
|
||||
{
|
||||
/* double buffered endpoint direction */
|
||||
EP_DBUF_ERR,
|
||||
EP_DBUF_OUT,
|
||||
EP_DBUF_IN
|
||||
}EP_DBUF_DIR;
|
||||
|
||||
/* endpoint buffer number */
|
||||
enum EP_BUF_NUM
|
||||
{
|
||||
EP_NOBUF,
|
||||
EP_BUF0,
|
||||
EP_BUF1
|
||||
};
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
#define RegBase (0x40005C00L) /* USB_IP Peripheral Registers base address */
|
||||
extern int PMAAddr; /* USB_IP Packet Memory Area base address, default is 0x40006000*/
|
||||
|
||||
/******************************************************************************/
|
||||
/* General registers */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Control register */
|
||||
#define CTRL ((__IO unsigned *)(RegBase + 0x40))
|
||||
/* Interrupt status register */
|
||||
#define INTSTS ((__IO unsigned *)(RegBase + 0x44))
|
||||
/* Frame number register */
|
||||
#define FRNUM ((__IO unsigned *)(RegBase + 0x48))
|
||||
/* Device address register */
|
||||
#define DEVADR ((__IO unsigned *)(RegBase + 0x4C))
|
||||
/* Buffer Table address register */
|
||||
#define BUFTBL ((__IO unsigned *)(RegBase + 0x50))
|
||||
/******************************************************************************/
|
||||
/* Endpoint registers */
|
||||
/******************************************************************************/
|
||||
#define EP0REG ((__IO unsigned *)(RegBase)) /* endpoint 0 register address */
|
||||
|
||||
/* Endpoint Addresses (w/direction) */
|
||||
#define EP0_OUT ((uint8_t)0x00)
|
||||
#define EP0_IN ((uint8_t)0x80)
|
||||
#define EP1_OUT ((uint8_t)0x01)
|
||||
#define EP1_IN ((uint8_t)0x81)
|
||||
#define EP2_OUT ((uint8_t)0x02)
|
||||
#define EP2_IN ((uint8_t)0x82)
|
||||
#define EP3_OUT ((uint8_t)0x03)
|
||||
#define EP3_IN ((uint8_t)0x83)
|
||||
#define EP4_OUT ((uint8_t)0x04)
|
||||
#define EP4_IN ((uint8_t)0x84)
|
||||
#define EP5_OUT ((uint8_t)0x05)
|
||||
#define EP5_IN ((uint8_t)0x85)
|
||||
#define EP6_OUT ((uint8_t)0x06)
|
||||
#define EP6_IN ((uint8_t)0x86)
|
||||
#define EP7_OUT ((uint8_t)0x07)
|
||||
#define EP7_IN ((uint8_t)0x87)
|
||||
|
||||
/* endpoints enumeration */
|
||||
#define ENDP0 ((uint8_t)0)
|
||||
#define ENDP1 ((uint8_t)1)
|
||||
#define ENDP2 ((uint8_t)2)
|
||||
#define ENDP3 ((uint8_t)3)
|
||||
#define ENDP4 ((uint8_t)4)
|
||||
#define ENDP5 ((uint8_t)5)
|
||||
#define ENDP6 ((uint8_t)6)
|
||||
#define ENDP7 ((uint8_t)7)
|
||||
|
||||
/******************************************************************************/
|
||||
/* INTSTS interrupt events */
|
||||
/******************************************************************************/
|
||||
#define INTSTS_CTFR (0x8000) /* Correct TRansfer (clear-only bit) */
|
||||
#define INTSTS_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */
|
||||
#define INTSTS_ERRF (0x2000) /* ERRor (clear-only bit) */
|
||||
#define INTSTS_WKUPF (0x1000) /* WaKe UP (clear-only bit) */
|
||||
#define INTSTS_SUSPF (0x0800) /* SUSPend (clear-only bit) */
|
||||
#define INTSTS_RSTF (0x0400) /* RESET (clear-only bit) */
|
||||
#define INTSTS_SOFF (0x0200) /* Start Of Frame (clear-only bit) */
|
||||
#define INTSTS_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */
|
||||
|
||||
|
||||
#define INTSTS_DIR (0x0010) /* DIRection of transaction (read-only bit) */
|
||||
#define INTSTS_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */
|
||||
|
||||
#define CLR_CTFR (~INTSTS_CTFR) /* clear Correct TRansfer bit */
|
||||
#define CLR_DOVR (~INTSTS_DOVR) /* clear DMA OVeR/underrun bit*/
|
||||
#define CLR_ERRF (~INTSTS_ERRF) /* clear ERRor bit */
|
||||
#define CLR_WKUPF (~INTSTS_WKUPF) /* clear WaKe UP bit */
|
||||
#define CLR_SUSPF (~INTSTS_SUSPF) /* clear SUSPend bit */
|
||||
#define CLR_RSTF (~INTSTS_RSTF) /* clear RESET bit */
|
||||
#define CLR_SOFF (~INTSTS_SOFF) /* clear Start Of Frame bit */
|
||||
#define CLR_ESOF (~INTSTS_ESOF) /* clear Expected Start Of Frame bit */
|
||||
|
||||
/******************************************************************************/
|
||||
/* CTRL control register bits definitions */
|
||||
/******************************************************************************/
|
||||
#define CTRL_CTFR_IEN (0x8000) /* Correct TRansfer Mask */
|
||||
#define CTRL_DOVR_IEN (0x4000) /* DMA OVeR/underrun Mask */
|
||||
#define CTRL_ERR_IEN (0x2000) /* ERRor Mask */
|
||||
#define CTRL_WKUP_IEN (0x1000) /* WaKe UP Mask */
|
||||
#define CTRL_SUSP_IEN (0x0800) /* SUSPend Mask */
|
||||
#define CTRL_RST_IEN (0x0400) /* RESET Mask */
|
||||
#define CTRL_SOF_IEN (0x0200) /* Start Of Frame Mask */
|
||||
#define CTRL_ESOF_IEN (0x0100) /* Expected Start Of Frame Mask */
|
||||
|
||||
|
||||
#define CTRL_RESUME (0x0010) /* RESUME request */
|
||||
#define CTRL_FSUSP (0x0008) /* Force SUSPend */
|
||||
#define CTRL_LPWR (0x0004) /* Low-power MODE */
|
||||
#define CTRL_PDWN (0x0002) /* Power DoWN */
|
||||
#define CTRL_FRST (0x0001) /* Force USB RESet */
|
||||
|
||||
/******************************************************************************/
|
||||
/* FRNUM Frame Number Register bit definitions */
|
||||
/******************************************************************************/
|
||||
#define FRNUM_RXDP (0x8000) /* status of D+ data line */
|
||||
#define FRNUM_RXDM (0x4000) /* status of D- data line */
|
||||
#define FRNUM_LCK (0x2000) /* LoCKed */
|
||||
#define FRNUM_LSOF (0x1800) /* Lost SOF */
|
||||
#define FRNUM_FN (0x07FF) /* Frame Number */
|
||||
/******************************************************************************/
|
||||
/* DEVADR Device ADDRess bit definitions */
|
||||
/******************************************************************************/
|
||||
#define DEVADR_EN (0x80)
|
||||
#define DEVADR_ADR (0x7F)
|
||||
/******************************************************************************/
|
||||
/* Endpoint register */
|
||||
/******************************************************************************/
|
||||
/* bit positions */
|
||||
#define EP_CTFR_RX (0x8000) /* EndPoint Correct TRansfer RX */
|
||||
#define EP_DTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */
|
||||
#define EP_STS_RX (0x3000) /* EndPoint RX STATus bit field */
|
||||
#define EP_SETUP (0x0800) /* EndPoint SETUP */
|
||||
#define EP_T_FIELD (0x0600) /* EndPoint TYPE */
|
||||
#define EP_SUBTYPE (0x0100) /* EndPoint KIND */
|
||||
#define EP_CTFR_TX (0x0080) /* EndPoint Correct TRansfer TX */
|
||||
#define EP_DTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */
|
||||
#define EP_STS_TX (0x0030) /* EndPoint TX STATus bit field */
|
||||
#define EPADR_FIELD (0x000F) /* EndPoint ADDRess FIELD */
|
||||
|
||||
/* EndPoint REGister MASK (no toggle fields) */
|
||||
#define EPREG_MASK (EP_CTFR_RX|EP_SETUP|EP_T_FIELD|EP_SUBTYPE|EP_CTFR_TX|EPADR_FIELD)
|
||||
|
||||
/* EP_TYPE[1:0] EndPoint TYPE */
|
||||
#define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */
|
||||
#define EP_BULK (0x0000) /* EndPoint BULK */
|
||||
#define EP_CONTROL (0x0200) /* EndPoint CONTROL */
|
||||
#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
|
||||
#define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */
|
||||
#define EP_T_MASK (~EP_T_FIELD & EPREG_MASK)
|
||||
|
||||
|
||||
/* EP_SUBTYPE EndPoint KIND */
|
||||
#define EPKIND_MASK (~EP_SUBTYPE & EPREG_MASK)
|
||||
|
||||
/* STAT_TX[1:0] STATus for TX transfer */
|
||||
#define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */
|
||||
#define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */
|
||||
#define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */
|
||||
#define EP_TX_VALID (0x0030) /* EndPoint TX VALID */
|
||||
#define EPTX_DTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */
|
||||
#define EPTX_DTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */
|
||||
#define EPTX_DTOGMASK (EP_STS_TX|EPREG_MASK)
|
||||
|
||||
/* STAT_RX[1:0] STATus for RX transfer */
|
||||
#define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */
|
||||
#define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */
|
||||
#define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */
|
||||
#define EP_RX_VALID (0x3000) /* EndPoint RX VALID */
|
||||
#define EPRX_DTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */
|
||||
#define EPRX_DTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */
|
||||
#define EPRX_DTOGMASK (EP_STS_RX|EPREG_MASK)
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* SetCTRL */
|
||||
#define _SetCTRL(wRegValue) (*CTRL = (uint16_t)wRegValue)
|
||||
|
||||
/* SetINTSTS */
|
||||
#define _SetINTSTS(wRegValue) (*INTSTS = (uint16_t)wRegValue)
|
||||
|
||||
/* SetDEVADR */
|
||||
#define _SetDEVADR(wRegValue) (*DEVADR = (uint16_t)wRegValue)
|
||||
|
||||
/* SetBUFTBL */
|
||||
#define _SetBUFTBL(wRegValue)(*BUFTBL = (uint16_t)(wRegValue & 0xFFF8))
|
||||
|
||||
/* GetCTRL */
|
||||
#define _GetCTRL() ((uint16_t) *CTRL)
|
||||
|
||||
/* GetINTSTS */
|
||||
#define _GetINTSTS() ((uint16_t) *INTSTS)
|
||||
|
||||
/* GetFRNUM */
|
||||
#define _GetFRNUM() ((uint16_t) *FRNUM)
|
||||
|
||||
/* GetDEVADR */
|
||||
#define _GetDEVADR() ((uint16_t) *DEVADR)
|
||||
|
||||
/* GetBUFTBL */
|
||||
#define _GetBUFTBL() ((uint16_t) *BUFTBL)
|
||||
|
||||
/* SetENDPOINT */
|
||||
#define _SetENDPOINT(bEpNum,wRegValue) (*(EP0REG + bEpNum)= \
|
||||
(uint16_t)wRegValue)
|
||||
|
||||
/* GetENDPOINT */
|
||||
#define _GetENDPOINT(bEpNum) ((uint16_t)(*(EP0REG + bEpNum)))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEPType
|
||||
* Description : sets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* wType
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\
|
||||
((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType )))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : GetEPType
|
||||
* Description : gets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : Endpoint Type
|
||||
*******************************************************************************/
|
||||
#define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD)
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEPTxStatus
|
||||
* Description : sets the status for tx transfer (bits STAT_TX[1:0]).
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* wState: new state
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPTxStatus(bEpNum,wState) {\
|
||||
register uint16_t _wRegVal; \
|
||||
_wRegVal = _GetENDPOINT(bEpNum) & EPTX_DTOGMASK;\
|
||||
/* toggle first bit ? */ \
|
||||
if((EPTX_DTOG1 & wState)!= 0) \
|
||||
_wRegVal ^= EPTX_DTOG1; \
|
||||
/* toggle second bit ? */ \
|
||||
if((EPTX_DTOG2 & wState)!= 0) \
|
||||
_wRegVal ^= EPTX_DTOG2; \
|
||||
_SetENDPOINT(bEpNum, (_wRegVal | EP_CTFR_RX|EP_CTFR_TX)); \
|
||||
} /* _SetEPTxStatus */
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEPRxStatus
|
||||
* Description : sets the status for rx transfer (bits STAT_TX[1:0])
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* wState: new state.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPRxStatus(bEpNum,wState) {\
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = _GetENDPOINT(bEpNum) & EPRX_DTOGMASK;\
|
||||
/* toggle first bit ? */ \
|
||||
if((EPRX_DTOG1 & wState)!= 0) \
|
||||
_wRegVal ^= EPRX_DTOG1; \
|
||||
/* toggle second bit ? */ \
|
||||
if((EPRX_DTOG2 & wState)!= 0) \
|
||||
_wRegVal ^= EPRX_DTOG2; \
|
||||
_SetENDPOINT(bEpNum, (_wRegVal | EP_CTFR_RX|EP_CTFR_TX)); \
|
||||
} /* _SetEPRxStatus */
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEPRxTxStatus
|
||||
* Description : sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* wStaterx: new state.
|
||||
* wStatetx: new state.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPRxTxStatus(bEpNum,wStaterx,wStatetx) {\
|
||||
register uint32_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DTOGMASK |EP_STS_TX) ;\
|
||||
/* toggle first bit ? */ \
|
||||
if((EPRX_DTOG1 & wStaterx)!= 0) \
|
||||
_wRegVal ^= EPRX_DTOG1; \
|
||||
/* toggle second bit ? */ \
|
||||
if((EPRX_DTOG2 & wStaterx)!= 0) \
|
||||
_wRegVal ^= EPRX_DTOG2; \
|
||||
/* toggle first bit ? */ \
|
||||
if((EPTX_DTOG1 & wStatetx)!= 0) \
|
||||
_wRegVal ^= EPTX_DTOG1; \
|
||||
/* toggle second bit ? */ \
|
||||
if((EPTX_DTOG2 & wStatetx)!= 0) \
|
||||
_wRegVal ^= EPTX_DTOG2; \
|
||||
_SetENDPOINT(bEpNum, _wRegVal | EP_CTFR_RX|EP_CTFR_TX); \
|
||||
} /* _SetEPRxTxStatus */
|
||||
/*******************************************************************************
|
||||
* Macro Name : GetEPTxStatus / GetEPRxStatus
|
||||
* Description : gets the status for tx/rx transfer (bits STAT_TX[1:0]
|
||||
* /STAT_RX[1:0])
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : status .
|
||||
*******************************************************************************/
|
||||
#define _GetEPTxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EP_STS_TX)
|
||||
|
||||
#define _GetEPRxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EP_STS_RX)
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEPTxValid / SetEPRxValid
|
||||
* Description : sets directly the VALID tx/rx-status into the enpoint register
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID))
|
||||
|
||||
#define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : GetTxStallStatus / GetRxStallStatus.
|
||||
* Description : checks stall condition in an endpoint.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : TRUE = endpoint in stall condition.
|
||||
*******************************************************************************/
|
||||
#define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) \
|
||||
== EP_TX_STALL)
|
||||
#define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) \
|
||||
== EP_RX_STALL)
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEP_SUBTYPE / ClearEP_SUBTYPE.
|
||||
* Description : set & clear EP_SUBTYPE bit.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEP_SUBTYPE(bEpNum) (_SetENDPOINT(bEpNum, \
|
||||
(EP_CTFR_RX|EP_CTFR_TX|((_GetENDPOINT(bEpNum) | EP_SUBTYPE) & EPREG_MASK))))
|
||||
#define _ClearEP_SUBTYPE(bEpNum) (_SetENDPOINT(bEpNum, \
|
||||
(EP_CTFR_RX|EP_CTFR_TX|(_GetENDPOINT(bEpNum) & EPKIND_MASK))))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : Set_Status_Out / Clear_Status_Out.
|
||||
* Description : Sets/clears directly STATUS_OUT bit in the endpoint register.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _Set_Status_Out(bEpNum) _SetEP_SUBTYPE(bEpNum)
|
||||
#define _Clear_Status_Out(bEpNum) _ClearEP_SUBTYPE(bEpNum)
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEPDoubleBuff / ClearEPDoubleBuff.
|
||||
* Description : Sets/clears directly EP_SUBTYPE bit in the endpoint register.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPDoubleBuff(bEpNum) _SetEP_SUBTYPE(bEpNum)
|
||||
#define _ClearEPDoubleBuff(bEpNum) _ClearEP_SUBTYPE(bEpNum)
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : ClearEP_CTFR_RX / ClearEP_CTFR_TX.
|
||||
* Description : Clears bit CTR_RX / CTR_TX in the endpoint register.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _ClearEP_CTFR_RX(bEpNum) (_SetENDPOINT(bEpNum,\
|
||||
_GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK))
|
||||
#define _ClearEP_CTFR_TX(bEpNum) (_SetENDPOINT(bEpNum,\
|
||||
_GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : ToggleDTOG_RX / ToggleDTOG_TX .
|
||||
* Description : Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _ToggleDTOG_RX(bEpNum) (_SetENDPOINT(bEpNum, \
|
||||
EP_CTFR_RX|EP_CTFR_TX|EP_DTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
|
||||
#define _ToggleDTOG_TX(bEpNum) (_SetENDPOINT(bEpNum, \
|
||||
EP_CTFR_RX|EP_CTFR_TX|EP_DTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : ClearDTOG_RX / ClearDTOG_TX.
|
||||
* Description : Clears DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _ClearDTOG_RX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_RX) != 0)\
|
||||
_ToggleDTOG_RX(bEpNum)
|
||||
#define _ClearDTOG_TX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_TX) != 0)\
|
||||
_ToggleDTOG_TX(bEpNum)
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEPAddress.
|
||||
* Description : Sets address in an endpoint register.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* bAddr: Address.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\
|
||||
EP_CTFR_RX|EP_CTFR_TX|(_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr)
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : GetEPAddress.
|
||||
* Description : Gets address in an endpoint register.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _GetEPAddress(bEpNum) ((uint8_t)(_GetENDPOINT(bEpNum) & EPADR_FIELD))
|
||||
|
||||
#define _pEPTxAddr(bEpNum) ((uint32_t *)((_GetBUFTBL()+bEpNum*8 )*2 + PMAAddr))
|
||||
#define _pEPTxCount(bEpNum) ((uint32_t *)((_GetBUFTBL()+bEpNum*8+2)*2 + PMAAddr))
|
||||
#define _pEPRxAddr(bEpNum) ((uint32_t *)((_GetBUFTBL()+bEpNum*8+4)*2 + PMAAddr))
|
||||
#define _pEPRxCount(bEpNum) ((uint32_t *)((_GetBUFTBL()+bEpNum*8+6)*2 + PMAAddr))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEPTxAddr / SetEPRxAddr.
|
||||
* Description : sets address of the tx/rx buffer.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* wAddr: address to be set (must be word aligned).
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPTxAddr(bEpNum,wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1))
|
||||
#define _SetEPRxAddr(bEpNum,wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : GetEPTxAddr / GetEPRxAddr.
|
||||
* Description : Gets address of the tx/rx buffer.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : address of the buffer.
|
||||
*******************************************************************************/
|
||||
#define _GetEPTxAddr(bEpNum) ((uint16_t)*_pEPTxAddr(bEpNum))
|
||||
#define _GetEPRxAddr(bEpNum) ((uint16_t)*_pEPRxAddr(bEpNum))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEPCountRxReg.
|
||||
* Description : Sets counter of rx buffer with no. of blocks.
|
||||
* Input : pdwReg: pointer to counter.
|
||||
* wCount: Counter.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _BlocksOf32(dwReg,wCount,wNBlocks) {\
|
||||
wNBlocks = wCount >> 5;\
|
||||
if((wCount & 0x1f) == 0)\
|
||||
wNBlocks--;\
|
||||
*pdwReg = (uint32_t)((wNBlocks << 10) | 0x8000);\
|
||||
}/* _BlocksOf32 */
|
||||
|
||||
#define _BlocksOf2(dwReg,wCount,wNBlocks) {\
|
||||
wNBlocks = wCount >> 1;\
|
||||
if((wCount & 0x1) != 0)\
|
||||
wNBlocks++;\
|
||||
*pdwReg = (uint32_t)(wNBlocks << 10);\
|
||||
}/* _BlocksOf2 */
|
||||
|
||||
#define _SetEPCountRxReg(dwReg,wCount) {\
|
||||
uint16_t wNBlocks;\
|
||||
if(wCount > 62){_BlocksOf32(dwReg,wCount,wNBlocks);}\
|
||||
else {_BlocksOf2(dwReg,wCount,wNBlocks);}\
|
||||
}/* _SetEPCountRxReg */
|
||||
|
||||
|
||||
|
||||
#define _SetEPRxDblBuf0Count(bEpNum,wCount) {\
|
||||
uint32_t *pdwReg = _pEPTxCount(bEpNum); \
|
||||
_SetEPCountRxReg(pdwReg, wCount);\
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEPTxCount / SetEPRxCount.
|
||||
* Description : sets counter for the tx/rx buffer.
|
||||
* Input : bEpNum: endpoint number.
|
||||
* wCount: Counter value.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPTxCount(bEpNum,wCount) (*_pEPTxCount(bEpNum) = wCount)
|
||||
#define _SetEPRxCount(bEpNum,wCount) {\
|
||||
uint32_t *pdwReg = _pEPRxCount(bEpNum); \
|
||||
_SetEPCountRxReg(pdwReg, wCount);\
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Macro Name : GetEPTxCount / GetEPRxCount.
|
||||
* Description : gets counter of the tx buffer.
|
||||
* Input : bEpNum: endpoint number.
|
||||
* Output : None.
|
||||
* Return : Counter value.
|
||||
*******************************************************************************/
|
||||
#define _GetEPTxCount(bEpNum)((uint16_t)(*_pEPTxCount(bEpNum)) & 0x3ff)
|
||||
#define _GetEPRxCount(bEpNum)((uint16_t)(*_pEPRxCount(bEpNum)) & 0x3ff)
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEPDblBuf0Addr / SetEPDblBuf1Addr.
|
||||
* Description : Sets buffer 0/1 address in a double buffer endpoint.
|
||||
* Input : bEpNum: endpoint number.
|
||||
* : wBuf0Addr: buffer 0 address.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPDblBuf0Addr(bEpNum,wBuf0Addr) {_SetEPTxAddr(bEpNum, wBuf0Addr);}
|
||||
#define _SetEPDblBuf1Addr(bEpNum,wBuf1Addr) {_SetEPRxAddr(bEpNum, wBuf1Addr);}
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEPDblBuffAddr.
|
||||
* Description : Sets addresses in a double buffer endpoint.
|
||||
* Input : bEpNum: endpoint number.
|
||||
* : wBuf0Addr: buffer 0 address.
|
||||
* : wBuf1Addr = buffer 1 address.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPDblBuffAddr(bEpNum,wBuf0Addr,wBuf1Addr) { \
|
||||
_SetEPDblBuf0Addr(bEpNum, wBuf0Addr);\
|
||||
_SetEPDblBuf1Addr(bEpNum, wBuf1Addr);\
|
||||
} /* _SetEPDblBuffAddr */
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : GetEPDblBuf0Addr / GetEPDblBuf1Addr.
|
||||
* Description : Gets buffer 0/1 address of a double buffer endpoint.
|
||||
* Input : bEpNum: endpoint number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum))
|
||||
#define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEPDblBuffCount / SetEPDblBuf0Count / SetEPDblBuf1Count.
|
||||
* Description : Gets buffer 0/1 address of a double buffer endpoint.
|
||||
* Input : bEpNum: endpoint number.
|
||||
* : bDir: endpoint dir EP_DBUF_OUT = OUT
|
||||
* EP_DBUF_IN = IN
|
||||
* : wCount: Counter value
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPDblBuf0Count(bEpNum, bDir, wCount) { \
|
||||
if(bDir == EP_DBUF_OUT)\
|
||||
/* OUT endpoint */ \
|
||||
{_SetEPRxDblBuf0Count(bEpNum,wCount);} \
|
||||
else if(bDir == EP_DBUF_IN)\
|
||||
/* IN endpoint */ \
|
||||
*_pEPTxCount(bEpNum) = (uint32_t)wCount; \
|
||||
} /* SetEPDblBuf0Count*/
|
||||
|
||||
#define _SetEPDblBuf1Count(bEpNum, bDir, wCount) { \
|
||||
if(bDir == EP_DBUF_OUT)\
|
||||
/* OUT endpoint */ \
|
||||
{_SetEPRxCount(bEpNum,wCount);}\
|
||||
else if(bDir == EP_DBUF_IN)\
|
||||
/* IN endpoint */\
|
||||
*_pEPRxCount(bEpNum) = (uint32_t)wCount; \
|
||||
} /* SetEPDblBuf1Count */
|
||||
|
||||
#define _SetEPDblBuffCount(bEpNum, bDir, wCount) {\
|
||||
_SetEPDblBuf0Count(bEpNum, bDir, wCount); \
|
||||
_SetEPDblBuf1Count(bEpNum, bDir, wCount); \
|
||||
} /* _SetEPDblBuffCount */
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : GetEPDblBuf0Count / GetEPDblBuf1Count.
|
||||
* Description : Gets buffer 0/1 rx/tx counter for double buffering.
|
||||
* Input : bEpNum: endpoint number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum))
|
||||
#define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum))
|
||||
|
||||
|
||||
/* External variables --------------------------------------------------------*/
|
||||
extern __IO uint16_t wIstr; /* INTSTS register last read value */
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void SetCTRL(uint16_t /*wRegValue*/);
|
||||
void SetINTSTS(uint16_t /*wRegValue*/);
|
||||
void SetDEVADR(uint16_t /*wRegValue*/);
|
||||
void SetBUFTBL(uint16_t /*wRegValue*/);
|
||||
void SetBUFTBL(uint16_t /*wRegValue*/);
|
||||
uint16_t GetCTRL(void);
|
||||
uint16_t GetINTSTS(void);
|
||||
uint16_t GetFRNUM(void);
|
||||
uint16_t GetDEVADR(void);
|
||||
uint16_t GetBUFTBL(void);
|
||||
void SetENDPOINT(uint8_t /*bEpNum*/, uint16_t /*wRegValue*/);
|
||||
uint16_t GetENDPOINT(uint8_t /*bEpNum*/);
|
||||
void SetEPType(uint8_t /*bEpNum*/, uint16_t /*wType*/);
|
||||
uint16_t GetEPType(uint8_t /*bEpNum*/);
|
||||
void SetEPTxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
|
||||
void SetEPRxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
|
||||
void SetDouBleBuffEPStall(uint8_t /*bEpNum*/, uint8_t bDir);
|
||||
uint16_t GetEPTxStatus(uint8_t /*bEpNum*/);
|
||||
uint16_t GetEPRxStatus(uint8_t /*bEpNum*/);
|
||||
void SetEPTxValid(uint8_t /*bEpNum*/);
|
||||
void SetEPRxValid(uint8_t /*bEpNum*/);
|
||||
uint16_t GetTxStallStatus(uint8_t /*bEpNum*/);
|
||||
uint16_t GetRxStallStatus(uint8_t /*bEpNum*/);
|
||||
void SetEP_SUBTYPE(uint8_t /*bEpNum*/);
|
||||
void ClearEP_SUBTYPE(uint8_t /*bEpNum*/);
|
||||
void Set_Status_Out(uint8_t /*bEpNum*/);
|
||||
void Clear_Status_Out(uint8_t /*bEpNum*/);
|
||||
void SetEPDoubleBuff(uint8_t /*bEpNum*/);
|
||||
void ClearEPDoubleBuff(uint8_t /*bEpNum*/);
|
||||
void ClearEP_CTFR_RX(uint8_t /*bEpNum*/);
|
||||
void ClearEP_CTFR_TX(uint8_t /*bEpNum*/);
|
||||
void ToggleDTOG_RX(uint8_t /*bEpNum*/);
|
||||
void ToggleDTOG_TX(uint8_t /*bEpNum*/);
|
||||
void ClearDTOG_RX(uint8_t /*bEpNum*/);
|
||||
void ClearDTOG_TX(uint8_t /*bEpNum*/);
|
||||
void SetEPAddress(uint8_t /*bEpNum*/, uint8_t /*bAddr*/);
|
||||
uint8_t GetEPAddress(uint8_t /*bEpNum*/);
|
||||
void SetEPTxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
|
||||
void SetEPRxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
|
||||
uint16_t GetEPTxAddr(uint8_t /*bEpNum*/);
|
||||
uint16_t GetEPRxAddr(uint8_t /*bEpNum*/);
|
||||
void SetEPCountRxReg(uint32_t * /*pdwReg*/, uint16_t /*wCount*/);
|
||||
void SetEPTxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
|
||||
void SetEPRxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
|
||||
uint16_t GetEPTxCount(uint8_t /*bEpNum*/);
|
||||
uint16_t GetEPRxCount(uint8_t /*bEpNum*/);
|
||||
void SetEPDblBuf0Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/);
|
||||
void SetEPDblBuf1Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf1Addr*/);
|
||||
void SetEPDblBuffAddr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/, uint16_t /*wBuf1Addr*/);
|
||||
uint16_t GetEPDblBuf0Addr(uint8_t /*bEpNum*/);
|
||||
uint16_t GetEPDblBuf1Addr(uint8_t /*bEpNum*/);
|
||||
void SetEPDblBuffCount(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
|
||||
void SetEPDblBuf0Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
|
||||
void SetEPDblBuf1Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
|
||||
uint16_t GetEPDblBuf0Count(uint8_t /*bEpNum*/);
|
||||
uint16_t GetEPDblBuf1Count(uint8_t /*bEpNum*/);
|
||||
EP_DBUF_DIR GetEPDblBufDir(uint8_t /*bEpNum*/);
|
||||
void FreeUserBuffer(uint8_t bEpNum/*bEpNum*/, uint8_t bDir);
|
||||
uint16_t ToWord(uint8_t, uint8_t);
|
||||
uint16_t ByteSwap(uint16_t);
|
||||
void Set_USB768ByteMode(void);
|
||||
void Clear_USB768ByteMode(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __USB_REGS_H */
|
||||
|
||||
|
||||
@@ -1,37 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* File : usb_type.h
|
||||
* Version: V1.2.2
|
||||
* Date : 2020-07-01
|
||||
* Brief : Type definitions used by the USB Library
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_TYPE_H
|
||||
#define __USB_TYPE_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
#ifndef NULL
|
||||
#define NULL ((void *)0)
|
||||
#endif
|
||||
|
||||
#ifndef __cplusplus
|
||||
typedef enum
|
||||
{
|
||||
FALSE = 0, TRUE = !FALSE
|
||||
}
|
||||
bool;
|
||||
#endif
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* External variables --------------------------------------------------------*/
|
||||
|
||||
#endif /* __USB_TYPE_H */
|
||||
|
||||
|
||||
@@ -1,973 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* File : usb_core.c
|
||||
* Version: V1.2.2
|
||||
* Date : 2020-07-01
|
||||
* Brief : Standard protocol processing (USB v2.0)
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_lib.h"
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define ValBit(VAR,Place) (VAR & (1 << Place))
|
||||
#define SetBit(VAR,Place) (VAR |= (1 << Place))
|
||||
#define ClrBit(VAR,Place) (VAR &= ((1 << Place) ^ 255))
|
||||
#define Send0LengthData() { _SetEPTxCount(ENDP0, 0); \
|
||||
vSetEPTxStatus(EP_TX_VALID); \
|
||||
}
|
||||
|
||||
#define vSetEPRxStatus(st) (SaveRState = st)
|
||||
#define vSetEPTxStatus(st) (SaveTState = st)
|
||||
|
||||
#define USB_StatusIn() Send0LengthData()
|
||||
#define USB_StatusOut() vSetEPRxStatus(EP_RX_VALID)
|
||||
|
||||
#define StatusInfo0 StatusInfo.bw.bb1 /* Reverse bb0 & bb1 */
|
||||
#define StatusInfo1 StatusInfo.bw.bb0
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
uint16_t_uint8_t StatusInfo;
|
||||
|
||||
bool Data_Mul_MaxPacketSize = FALSE;
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static void DataStageOut(void);
|
||||
static void DataStageIn(void);
|
||||
static void NoData_Setup0(void);
|
||||
static void Data_Setup0(void);
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Return the current configuration variable address.
|
||||
* @param Length: How many bytes are needed.
|
||||
* @retval 0 if the request is invalid when Length is 0.
|
||||
* Buffer address if the Length is not 0.
|
||||
*/
|
||||
uint8_t *Standard_GetConfiguration(uint16_t Length)
|
||||
{
|
||||
if (Length == 0)
|
||||
{
|
||||
pInformation->Ctrl_Info.Usb_wLength =
|
||||
sizeof(pInformation->Current_Configuration);
|
||||
return 0;
|
||||
}
|
||||
pUser_Standard_Requests->User_GetConfiguration();
|
||||
return (uint8_t *)&pInformation->Current_Configuration;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This routine is called to set the configuration value
|
||||
* Then each class should configure device itself.
|
||||
* @param None.
|
||||
* @retval USB_SUCCESS if the request is performed.
|
||||
* USB_UNSUPPORT if the request is invalid.
|
||||
*/
|
||||
RESULT Standard_SetConfiguration(void)
|
||||
{
|
||||
|
||||
if ((pInformation->USBwValue0 <=
|
||||
Device_Table.Total_Configuration) && (pInformation->USBwValue1 == 0)
|
||||
&& (pInformation->USBwIndex == 0)) /*call Back usb spec 2.0*/
|
||||
{
|
||||
pInformation->Current_Configuration = pInformation->USBwValue0;
|
||||
pUser_Standard_Requests->User_SetConfiguration();
|
||||
return USB_SUCCESS;
|
||||
}
|
||||
else
|
||||
{
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Alternate Setting of the current interface.
|
||||
* @param Length: How many bytes are needed.
|
||||
* @retval 0 if the request is invalid when Length is 0.
|
||||
* Buffer address if the Length is not 0.
|
||||
*/
|
||||
uint8_t *Standard_GetInterface(uint16_t Length)
|
||||
{
|
||||
if (Length == 0)
|
||||
{
|
||||
pInformation->Ctrl_Info.Usb_wLength =
|
||||
sizeof(pInformation->Current_AlternateSetting);
|
||||
return 0;
|
||||
}
|
||||
pUser_Standard_Requests->User_GetInterface();
|
||||
return (uint8_t *)&pInformation->Current_AlternateSetting;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This routine is called to set the interface.
|
||||
* Then each class should configure the interface them self.
|
||||
* @param None.
|
||||
* @retval USB_SUCCESS if the request is performed.
|
||||
* USB_UNSUPPORT if the request is invalid.
|
||||
*/
|
||||
RESULT Standard_SetInterface(void)
|
||||
{
|
||||
RESULT Re;
|
||||
/*Test if the specified Interface and Alternate Setting are supported by
|
||||
the application Firmware*/
|
||||
Re = (*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, pInformation->USBwValue0);
|
||||
|
||||
if (pInformation->Current_Configuration != 0)
|
||||
{
|
||||
if ((Re != USB_SUCCESS) || (pInformation->USBwIndex1 != 0)
|
||||
|| (pInformation->USBwValue1 != 0))
|
||||
{
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
else if (Re == USB_SUCCESS)
|
||||
{
|
||||
pUser_Standard_Requests->User_SetInterface();
|
||||
pInformation->Current_Interface = pInformation->USBwIndex0;
|
||||
pInformation->Current_AlternateSetting = pInformation->USBwValue0;
|
||||
return USB_SUCCESS;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Copy the device request data to "StatusInfo buffer".
|
||||
* @param Length: How many bytes are needed.
|
||||
* @retval 0 if the Length is 0.
|
||||
* status address if Length is valid.
|
||||
*/
|
||||
uint8_t *Standard_GetStatus(uint16_t Length)
|
||||
{
|
||||
if (Length == 0)
|
||||
{
|
||||
pInformation->Ctrl_Info.Usb_wLength = 2;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Reset Status Information */
|
||||
StatusInfo.w = 0;
|
||||
|
||||
if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
|
||||
{
|
||||
/*Get Device Status */
|
||||
uint8_t Feature = pInformation->Current_Feature;
|
||||
|
||||
/* Remote Wakeup enabled */
|
||||
if (ValBit(Feature, 5))
|
||||
{
|
||||
SetBit(StatusInfo0, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
ClrBit(StatusInfo0, 1);
|
||||
}
|
||||
|
||||
/* Bus-powered */
|
||||
if (ValBit(Feature, 6))
|
||||
{
|
||||
SetBit(StatusInfo0, 0);
|
||||
}
|
||||
else /* Self-powered */
|
||||
{
|
||||
ClrBit(StatusInfo0, 0);
|
||||
}
|
||||
}
|
||||
/*Interface Status*/
|
||||
else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
|
||||
{
|
||||
return (uint8_t *)&StatusInfo;
|
||||
}
|
||||
/*Get EndPoint Status*/
|
||||
else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
|
||||
{
|
||||
uint8_t Related_Endpoint;
|
||||
uint8_t wIndex0 = pInformation->USBwIndex0;
|
||||
|
||||
Related_Endpoint = (wIndex0 & 0x0f);
|
||||
if (ValBit(wIndex0, 7))
|
||||
{
|
||||
/* IN endpoint */
|
||||
if (_GetTxStallStatus(Related_Endpoint))
|
||||
{
|
||||
SetBit(StatusInfo0, 0); /* IN Endpoint stalled */
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* OUT endpoint */
|
||||
if (_GetRxStallStatus(Related_Endpoint))
|
||||
{
|
||||
SetBit(StatusInfo0, 0); /* OUT Endpoint stalled */
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
pUser_Standard_Requests->User_GetStatus();
|
||||
return (uint8_t *)&StatusInfo;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear or disable a specific feature.
|
||||
* @param None.
|
||||
* @retval USB_SUCCESS if the request is performed.
|
||||
* USB_UNSUPPORT if the request is invalid.
|
||||
*/
|
||||
RESULT Standard_ClearFeature(void)
|
||||
{
|
||||
uint32_t Type_Rec = Type_Recipient;
|
||||
uint32_t Status;
|
||||
|
||||
|
||||
if (Type_Rec == (STANDARD_REQUEST | DEVICE_RECIPIENT))
|
||||
{/*Device Clear Feature*/
|
||||
ClrBit(pInformation->Current_Feature, 5);
|
||||
return USB_SUCCESS;
|
||||
}
|
||||
else if (Type_Rec == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
|
||||
{/*EndPoint Clear Feature*/
|
||||
DEVICE* pDev;
|
||||
uint32_t Related_Endpoint;
|
||||
uint32_t wIndex0;
|
||||
uint32_t rEP;
|
||||
|
||||
if ((pInformation->USBwValue != ENDPOINT_STALL)
|
||||
|| (pInformation->USBwIndex1 != 0))
|
||||
{
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
|
||||
pDev = &Device_Table;
|
||||
wIndex0 = pInformation->USBwIndex0;
|
||||
rEP = wIndex0 & ~0x80;
|
||||
Related_Endpoint = ENDP0 + rEP;
|
||||
|
||||
if (ValBit(pInformation->USBwIndex0, 7))
|
||||
{
|
||||
/*Get Status of endpoint & stall the request if the related_ENdpoint
|
||||
is Disabled*/
|
||||
Status = _GetEPTxStatus(Related_Endpoint);
|
||||
}
|
||||
else
|
||||
{
|
||||
Status = _GetEPRxStatus(Related_Endpoint);
|
||||
}
|
||||
|
||||
if ((rEP >= pDev->Total_Endpoint) || (Status == 0)
|
||||
|| (pInformation->Current_Configuration == 0))
|
||||
{
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
|
||||
|
||||
if (wIndex0 & 0x80)
|
||||
{
|
||||
/* IN endpoint */
|
||||
if (_GetTxStallStatus(Related_Endpoint ))
|
||||
{
|
||||
ClearDTOG_TX(Related_Endpoint);
|
||||
SetEPTxStatus(Related_Endpoint, EP_TX_VALID);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* OUT endpoint */
|
||||
if (_GetRxStallStatus(Related_Endpoint))
|
||||
{
|
||||
if (Related_Endpoint == ENDP0)
|
||||
{
|
||||
/* After clear the STALL, enable the default endpoint receiver */
|
||||
SetEPRxCount(Related_Endpoint, Device_Property.MaxPacketSize);
|
||||
_SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
|
||||
}
|
||||
else
|
||||
{
|
||||
ClearDTOG_RX(Related_Endpoint);
|
||||
_SetEPRxStatus(Related_Endpoint, EP_RX_VALID);
|
||||
}
|
||||
}
|
||||
}
|
||||
pUser_Standard_Requests->User_ClearFeature();
|
||||
return USB_SUCCESS;
|
||||
}
|
||||
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set or enable a specific feature of EndPoint.
|
||||
* @param None.
|
||||
* @retval USB_SUCCESS if the request is performed.
|
||||
* USB_UNSUPPORT if the request is invalid.
|
||||
*/
|
||||
RESULT Standard_SetEndPointFeature(void)
|
||||
{
|
||||
uint32_t wIndex0;
|
||||
uint32_t Related_Endpoint;
|
||||
uint32_t rEP;
|
||||
uint32_t Status;
|
||||
|
||||
wIndex0 = pInformation->USBwIndex0;
|
||||
rEP = wIndex0 & ~0x80;
|
||||
Related_Endpoint = ENDP0 + rEP;
|
||||
|
||||
if (ValBit(pInformation->USBwIndex0, 7))
|
||||
{
|
||||
/* get Status of endpoint & stall the request if the related_ENdpoint
|
||||
is Disabled*/
|
||||
Status = _GetEPTxStatus(Related_Endpoint);
|
||||
}
|
||||
else
|
||||
{
|
||||
Status = _GetEPRxStatus(Related_Endpoint);
|
||||
}
|
||||
|
||||
if (Related_Endpoint >= Device_Table.Total_Endpoint
|
||||
|| pInformation->USBwValue != 0 || Status == 0
|
||||
|| pInformation->Current_Configuration == 0)
|
||||
{
|
||||
return USB_UNSUPPORT;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (wIndex0 & 0x80)
|
||||
{
|
||||
/* IN endpoint */
|
||||
_SetEPTxStatus(Related_Endpoint, EP_TX_STALL);
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
/* OUT endpoint */
|
||||
_SetEPRxStatus(Related_Endpoint, EP_RX_STALL);
|
||||
}
|
||||
}
|
||||
pUser_Standard_Requests->User_SetEndPointFeature();
|
||||
return USB_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set or enable a specific feature of Device.
|
||||
* @param None.
|
||||
* @retval USB_SUCCESS if the request is performed.
|
||||
* USB_UNSUPPORT if the request is invalid.
|
||||
*/
|
||||
RESULT Standard_SetDeviceFeature(void)
|
||||
{
|
||||
SetBit(pInformation->Current_Feature, 5);
|
||||
pUser_Standard_Requests->User_SetDeviceFeature();
|
||||
return USB_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Standard_GetDescriptorData is used for descriptors transfer.
|
||||
This routine is used for the descriptors resident in Flash
|
||||
* or RAM
|
||||
* pDesc can be in either Flash or RAM
|
||||
* The purpose of this routine is to have a versatile way to
|
||||
* response descriptors request. It allows user to generate
|
||||
* certain descriptors with software or read descriptors from
|
||||
* external storage part by part.
|
||||
* @param Length: Length of the data in this transfer.
|
||||
* @param pDesc: A pointer points to descriptor struct.
|
||||
* The structure gives the initial address of the descriptor and its original size
|
||||
* @retval Address of a part of the descriptor pointed by the Usb_wOffset the buffer pointed
|
||||
* by this address contains at least Length bytes.
|
||||
*/
|
||||
uint8_t *Standard_GetDescriptorData(uint16_t Length, ONE_DESCRIPTOR *pDesc)
|
||||
{
|
||||
uint32_t wOffset;
|
||||
|
||||
wOffset = pInformation->Ctrl_Info.Usb_wOffset;
|
||||
if (Length == 0)
|
||||
{
|
||||
pInformation->Ctrl_Info.Usb_wLength = pDesc->Descriptor_Size - wOffset;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return pDesc->Descriptor + wOffset;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Data stage of a Control Write Transfer.
|
||||
* @param None.
|
||||
* @retval None.
|
||||
*/
|
||||
void DataStageOut(void)
|
||||
{
|
||||
ENDPOINT_INFO *pEPinfo = &pInformation->Ctrl_Info;
|
||||
uint32_t save_rLength;
|
||||
|
||||
save_rLength = pEPinfo->Usb_rLength;
|
||||
|
||||
if (pEPinfo->CopyData && save_rLength)
|
||||
{
|
||||
uint8_t *Buffer;
|
||||
uint32_t Length;
|
||||
|
||||
Length = pEPinfo->PacketSize;
|
||||
if (Length > save_rLength)
|
||||
{
|
||||
Length = save_rLength;
|
||||
}
|
||||
|
||||
Buffer = (*pEPinfo->CopyData)(Length);
|
||||
pEPinfo->Usb_rLength -= Length;
|
||||
pEPinfo->Usb_rOffset += Length;
|
||||
PMAToUserBufferCopy(Buffer, GetEPRxAddr(ENDP0), Length);
|
||||
}
|
||||
|
||||
if (pEPinfo->Usb_rLength != 0)
|
||||
{
|
||||
vSetEPRxStatus(EP_RX_VALID);/* re-enable for next data reception */
|
||||
// SetEPTxCount(ENDP0, 0);
|
||||
// vSetEPTxStatus(EP_TX_VALID);/* Expect the host to abort the data OUT stage */
|
||||
}
|
||||
/* Set the next State*/
|
||||
if (pEPinfo->Usb_rLength >= pEPinfo->PacketSize)
|
||||
{
|
||||
pInformation->ControlState = OUT_DATA;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (pEPinfo->Usb_rLength > 0)
|
||||
{
|
||||
pInformation->ControlState = LAST_OUT_DATA;
|
||||
}
|
||||
else if (pEPinfo->Usb_rLength == 0)
|
||||
{
|
||||
(*pEPinfo->CopyData)(0); //added to notify write to array finished
|
||||
pInformation->ControlState = WAIT_STATUS_IN;
|
||||
USB_StatusIn();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Data stage of a Control Read Transfer.
|
||||
* @param None.
|
||||
* @retval None.
|
||||
*/
|
||||
void DataStageIn(void)
|
||||
{
|
||||
ENDPOINT_INFO *pEPinfo = &pInformation->Ctrl_Info;
|
||||
uint32_t save_wLength = pEPinfo->Usb_wLength;
|
||||
uint32_t ControlState = pInformation->ControlState;
|
||||
|
||||
uint8_t *DataBuffer;
|
||||
uint32_t Length;
|
||||
|
||||
if ((save_wLength == 0) && (ControlState == LAST_IN_DATA))
|
||||
{
|
||||
if(Data_Mul_MaxPacketSize == TRUE)
|
||||
{
|
||||
/* No more data to send and empty packet */
|
||||
Send0LengthData();
|
||||
ControlState = LAST_IN_DATA;
|
||||
Data_Mul_MaxPacketSize = FALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No more data to send so STALL the TX Status*/
|
||||
ControlState = WAIT_STATUS_OUT;
|
||||
vSetEPTxStatus(EP_TX_STALL);
|
||||
}
|
||||
goto Expect_Status_Out;
|
||||
}
|
||||
|
||||
Length = pEPinfo->PacketSize;
|
||||
ControlState = (save_wLength <= Length) ? LAST_IN_DATA : IN_DATA;
|
||||
|
||||
if (Length > save_wLength)
|
||||
{
|
||||
Length = save_wLength;
|
||||
}
|
||||
|
||||
DataBuffer = (*pEPinfo->CopyData)(Length);
|
||||
|
||||
UserToPMABufferCopy(DataBuffer, GetEPTxAddr(ENDP0), Length);
|
||||
|
||||
SetEPTxCount(ENDP0, Length);
|
||||
|
||||
pEPinfo->Usb_wLength -= Length;
|
||||
pEPinfo->Usb_wOffset += Length;
|
||||
vSetEPTxStatus(EP_TX_VALID);
|
||||
|
||||
USB_StatusOut();/* Expect the host to abort the data IN stage */
|
||||
|
||||
Expect_Status_Out:
|
||||
pInformation->ControlState = ControlState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Proceed the processing of setup request without data stage.
|
||||
* @param None.
|
||||
* @retval None.
|
||||
*/
|
||||
void NoData_Setup0(void)
|
||||
{
|
||||
RESULT Result = USB_UNSUPPORT;
|
||||
uint32_t RequestNo = pInformation->USBbRequest;
|
||||
uint32_t ControlState;
|
||||
|
||||
/* Device Request*/
|
||||
if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
|
||||
{
|
||||
/* Device Request*/
|
||||
/* SET_CONFIGURATION*/
|
||||
if (RequestNo == SET_CONFIGURATION)
|
||||
{
|
||||
Result = Standard_SetConfiguration();
|
||||
}
|
||||
|
||||
/*SET ADDRESS*/
|
||||
else if (RequestNo == SET_ADDRESS)
|
||||
{
|
||||
if ((pInformation->USBwValue0 > 127) || (pInformation->USBwValue1 != 0)
|
||||
|| (pInformation->USBwIndex != 0)
|
||||
|| (pInformation->Current_Configuration != 0))
|
||||
/* Device Address should be 127 or less*/
|
||||
{
|
||||
ControlState = STALLED;
|
||||
goto exit_NoData_Setup0;
|
||||
}
|
||||
else
|
||||
{
|
||||
Result = USB_SUCCESS;
|
||||
}
|
||||
}
|
||||
/*SET FEATURE for Device*/
|
||||
else if (RequestNo == SET_FEATURE)
|
||||
{
|
||||
if ((pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP) \
|
||||
&& (pInformation->USBwIndex == 0))
|
||||
{
|
||||
Result = Standard_SetDeviceFeature();
|
||||
}
|
||||
else
|
||||
{
|
||||
Result = USB_UNSUPPORT;
|
||||
}
|
||||
}
|
||||
/*Clear FEATURE for Device */
|
||||
else if (RequestNo == CLEAR_FEATURE)
|
||||
{
|
||||
if (pInformation->USBwValue0 == DEVICE_REMOTE_WAKEUP
|
||||
&& pInformation->USBwIndex == 0
|
||||
&& ValBit(pInformation->Current_Feature, 5))
|
||||
{
|
||||
Result = Standard_ClearFeature();
|
||||
}
|
||||
else
|
||||
{
|
||||
Result = USB_UNSUPPORT;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Interface Request*/
|
||||
else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
|
||||
{
|
||||
/*SET INTERFACE*/
|
||||
if (RequestNo == SET_INTERFACE)
|
||||
{
|
||||
Result = Standard_SetInterface();
|
||||
}
|
||||
}
|
||||
|
||||
/* EndPoint Request*/
|
||||
else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
|
||||
{
|
||||
/*CLEAR FEATURE for EndPoint*/
|
||||
if (RequestNo == CLEAR_FEATURE)
|
||||
{
|
||||
Result = Standard_ClearFeature();
|
||||
}
|
||||
/* SET FEATURE for EndPoint*/
|
||||
else if (RequestNo == SET_FEATURE)
|
||||
{
|
||||
Result = Standard_SetEndPointFeature();
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
Result = USB_UNSUPPORT;
|
||||
}
|
||||
|
||||
|
||||
if (Result != USB_SUCCESS)
|
||||
{
|
||||
Result = (*pProperty->Class_NoData_Setup)(RequestNo);
|
||||
if (Result == USB_NOT_READY)
|
||||
{
|
||||
ControlState = PAUSE;
|
||||
goto exit_NoData_Setup0;
|
||||
}
|
||||
}
|
||||
|
||||
if (Result != USB_SUCCESS)
|
||||
{
|
||||
ControlState = STALLED;
|
||||
goto exit_NoData_Setup0;
|
||||
}
|
||||
|
||||
ControlState = WAIT_STATUS_IN;/* After no data stage SETUP */
|
||||
|
||||
USB_StatusIn();
|
||||
|
||||
exit_NoData_Setup0:
|
||||
pInformation->ControlState = ControlState;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Proceed the processing of setup request with data stage.
|
||||
* @param None.
|
||||
* @retval None.
|
||||
*/
|
||||
void Data_Setup0(void)
|
||||
{
|
||||
uint8_t *(*CopyRoutine)(uint16_t);
|
||||
RESULT Result;
|
||||
uint32_t Request_No = pInformation->USBbRequest;
|
||||
|
||||
uint32_t Related_Endpoint, Reserved;
|
||||
uint32_t wOffset, Status;
|
||||
|
||||
|
||||
|
||||
CopyRoutine = NULL;
|
||||
wOffset = 0;
|
||||
|
||||
/*GET DESCRIPTOR*/
|
||||
if (Request_No == GET_DESCRIPTOR)
|
||||
{
|
||||
if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
|
||||
{
|
||||
uint8_t wValue1 = pInformation->USBwValue1;
|
||||
if (wValue1 == DEVICE_DESCRIPTOR)
|
||||
{
|
||||
CopyRoutine = pProperty->GetDeviceDescriptor;
|
||||
}
|
||||
else if (wValue1 == CONFIG_DESCRIPTOR)
|
||||
{
|
||||
CopyRoutine = pProperty->GetConfigDescriptor;
|
||||
}
|
||||
else if (wValue1 == STRING_DESCRIPTOR)
|
||||
{
|
||||
CopyRoutine = pProperty->GetStringDescriptor;
|
||||
} /* End of GET_DESCRIPTOR */
|
||||
}
|
||||
}
|
||||
|
||||
/*GET STATUS*/
|
||||
else if ((Request_No == GET_STATUS) && (pInformation->USBwValue == 0)
|
||||
&& (pInformation->USBwLength == 0x0002)
|
||||
&& (pInformation->USBwIndex1 == 0))
|
||||
{
|
||||
/* GET STATUS for Device*/
|
||||
if ((Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
|
||||
&& (pInformation->USBwIndex == 0))
|
||||
{
|
||||
CopyRoutine = Standard_GetStatus;
|
||||
}
|
||||
|
||||
/* GET STATUS for Interface*/
|
||||
else if (Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
|
||||
{
|
||||
if (((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == USB_SUCCESS)
|
||||
&& (pInformation->Current_Configuration != 0))
|
||||
{
|
||||
CopyRoutine = Standard_GetStatus;
|
||||
}
|
||||
}
|
||||
|
||||
/* GET STATUS for EndPoint*/
|
||||
else if (Type_Recipient == (STANDARD_REQUEST | ENDPOINT_RECIPIENT))
|
||||
{
|
||||
Related_Endpoint = (pInformation->USBwIndex0 & 0x0f);
|
||||
Reserved = pInformation->USBwIndex0 & 0x70;
|
||||
|
||||
if (ValBit(pInformation->USBwIndex0, 7))
|
||||
{
|
||||
/*Get Status of endpoint & stall the request if the related_ENdpoint
|
||||
is Disabled*/
|
||||
Status = _GetEPTxStatus(Related_Endpoint);
|
||||
}
|
||||
else
|
||||
{
|
||||
Status = _GetEPRxStatus(Related_Endpoint);
|
||||
}
|
||||
|
||||
if ((Related_Endpoint < Device_Table.Total_Endpoint) && (Reserved == 0)
|
||||
&& (Status != 0))
|
||||
{
|
||||
CopyRoutine = Standard_GetStatus;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*GET CONFIGURATION*/
|
||||
else if (Request_No == GET_CONFIGURATION)
|
||||
{
|
||||
if (Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT))
|
||||
{
|
||||
CopyRoutine = Standard_GetConfiguration;
|
||||
}
|
||||
}
|
||||
/*GET INTERFACE*/
|
||||
else if (Request_No == GET_INTERFACE)
|
||||
{
|
||||
if ((Type_Recipient == (STANDARD_REQUEST | INTERFACE_RECIPIENT))
|
||||
&& (pInformation->Current_Configuration != 0) && (pInformation->USBwValue == 0)
|
||||
&& (pInformation->USBwIndex1 == 0) && (pInformation->USBwLength == 0x0001)
|
||||
&& ((*pProperty->Class_Get_Interface_Setting)(pInformation->USBwIndex0, 0) == USB_SUCCESS))
|
||||
{
|
||||
CopyRoutine = Standard_GetInterface;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if (CopyRoutine)
|
||||
{
|
||||
pInformation->Ctrl_Info.Usb_wOffset = wOffset;
|
||||
pInformation->Ctrl_Info.CopyData = CopyRoutine;
|
||||
/* sb in the original the cast to word was directly */
|
||||
/* now the cast is made step by step */
|
||||
(*CopyRoutine)(0);
|
||||
Result = USB_SUCCESS;
|
||||
}
|
||||
else
|
||||
{
|
||||
Result = (*pProperty->Class_Data_Setup)(pInformation->USBbRequest);
|
||||
if (Result == USB_NOT_READY)
|
||||
{
|
||||
pInformation->ControlState = PAUSE;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if (pInformation->Ctrl_Info.Usb_wLength == 0xFFFF)
|
||||
{
|
||||
/* Data is not ready, wait it */
|
||||
pInformation->ControlState = PAUSE;
|
||||
return;
|
||||
}
|
||||
if ((Result == USB_UNSUPPORT) || (pInformation->Ctrl_Info.Usb_wLength == 0))
|
||||
{
|
||||
/* Unsupported request */
|
||||
pInformation->ControlState = STALLED;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
if (ValBit(pInformation->USBbmRequestType, 7))
|
||||
{
|
||||
/* Device ==> Host */
|
||||
__IO uint32_t wLength = pInformation->USBwLength;
|
||||
|
||||
/* Restrict the data length to be the one host asks for */
|
||||
if (pInformation->Ctrl_Info.Usb_wLength > wLength)
|
||||
{
|
||||
pInformation->Ctrl_Info.Usb_wLength = wLength;
|
||||
}
|
||||
|
||||
else if (pInformation->Ctrl_Info.Usb_wLength < pInformation->USBwLength)
|
||||
{
|
||||
if (pInformation->Ctrl_Info.Usb_wLength < pProperty->MaxPacketSize)
|
||||
{
|
||||
Data_Mul_MaxPacketSize = FALSE;
|
||||
}
|
||||
else if ((pInformation->Ctrl_Info.Usb_wLength % pProperty->MaxPacketSize) == 0)
|
||||
{
|
||||
Data_Mul_MaxPacketSize = TRUE;
|
||||
}
|
||||
}
|
||||
|
||||
pInformation->Ctrl_Info.PacketSize = pProperty->MaxPacketSize;
|
||||
DataStageIn();
|
||||
}
|
||||
else
|
||||
{
|
||||
pInformation->ControlState = OUT_DATA;
|
||||
vSetEPRxStatus(EP_RX_VALID); /* enable for next data reception */
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the device request data and dispatch to individual process.
|
||||
* @param None.
|
||||
* @retval None.
|
||||
*/
|
||||
uint8_t Setup0_Process(void)
|
||||
{
|
||||
|
||||
union
|
||||
{
|
||||
uint8_t* b;
|
||||
uint16_t* w;
|
||||
} pBuf;
|
||||
uint16_t offset = 1;
|
||||
|
||||
pBuf.b = PMAAddr + (uint8_t *)(_GetEPRxAddr(ENDP0) * 2); /* *2 for 32 bits addr */
|
||||
|
||||
if (pInformation->ControlState != PAUSE)
|
||||
{
|
||||
pInformation->USBbmRequestType = *pBuf.b++; /* bmRequestType */
|
||||
pInformation->USBbRequest = *pBuf.b++; /* bRequest */
|
||||
pBuf.w += offset; /* word not accessed because of 32 bits addressing */
|
||||
pInformation->USBwValue = ByteSwap(*pBuf.w++); /* wValue */
|
||||
pBuf.w += offset; /* word not accessed because of 32 bits addressing */
|
||||
pInformation->USBwIndex = ByteSwap(*pBuf.w++); /* wIndex */
|
||||
pBuf.w += offset; /* word not accessed because of 32 bits addressing */
|
||||
pInformation->USBwLength = *pBuf.w; /* wLength */
|
||||
}
|
||||
|
||||
pInformation->ControlState = SETTING_UP;
|
||||
if (pInformation->USBwLength == 0)
|
||||
{
|
||||
/* Setup with no data stage */
|
||||
NoData_Setup0();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Setup with data stage */
|
||||
Data_Setup0();
|
||||
}
|
||||
return Post0_Process();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Process the IN token on all default endpoint.
|
||||
* @param None.
|
||||
* @retval None.
|
||||
*/
|
||||
uint8_t In0_Process(void)
|
||||
{
|
||||
uint32_t ControlState = pInformation->ControlState;
|
||||
|
||||
if ((ControlState == IN_DATA) || (ControlState == LAST_IN_DATA))
|
||||
{
|
||||
DataStageIn();
|
||||
/* ControlState may be changed outside the function */
|
||||
ControlState = pInformation->ControlState;
|
||||
}
|
||||
|
||||
else if (ControlState == WAIT_STATUS_IN)
|
||||
{
|
||||
if ((pInformation->USBbRequest == SET_ADDRESS) &&
|
||||
(Type_Recipient == (STANDARD_REQUEST | DEVICE_RECIPIENT)))
|
||||
{
|
||||
SetDeviceAddress(pInformation->USBwValue0);
|
||||
pUser_Standard_Requests->User_SetDeviceAddress();
|
||||
}
|
||||
(*pProperty->Process_Status_IN)();
|
||||
ControlState = STALLED;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
ControlState = STALLED;
|
||||
}
|
||||
|
||||
pInformation->ControlState = ControlState;
|
||||
|
||||
return Post0_Process();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Process the OUT token on all default endpoint.
|
||||
* @param None.
|
||||
* @retval None.
|
||||
*/
|
||||
uint8_t Out0_Process(void)
|
||||
{
|
||||
uint32_t ControlState = pInformation->ControlState;
|
||||
|
||||
if ((ControlState == IN_DATA) || (ControlState == LAST_IN_DATA))
|
||||
{
|
||||
/* host aborts the transfer before finish */
|
||||
ControlState = STALLED;
|
||||
}
|
||||
else if ((ControlState == OUT_DATA) || (ControlState == LAST_OUT_DATA))
|
||||
{
|
||||
DataStageOut();
|
||||
ControlState = pInformation->ControlState; /* may be changed outside the function */
|
||||
}
|
||||
|
||||
else if (ControlState == WAIT_STATUS_OUT)
|
||||
{
|
||||
(*pProperty->Process_Status_OUT)();
|
||||
ControlState = STALLED;
|
||||
}
|
||||
|
||||
|
||||
/* Unexpect state, STALL the endpoint */
|
||||
else
|
||||
{
|
||||
ControlState = STALLED;
|
||||
}
|
||||
|
||||
pInformation->ControlState = ControlState;
|
||||
|
||||
return Post0_Process();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stall the Endpoint 0 in case of error.
|
||||
* @param None.
|
||||
* @retval 0 if the control state is in PAUSE.
|
||||
* 1 if not.
|
||||
*/
|
||||
uint8_t Post0_Process(void)
|
||||
{
|
||||
|
||||
SetEPRxCount(ENDP0, Device_Property.MaxPacketSize);
|
||||
/*no need set to STALL*/
|
||||
if (pInformation->ControlState == STALLED)
|
||||
{
|
||||
vSetEPRxStatus(EP_RX_STALL);
|
||||
vSetEPTxStatus(EP_TX_STALL);
|
||||
}
|
||||
|
||||
return (pInformation->ControlState == PAUSE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the device and all the used Endpoints addresses.
|
||||
* @param Val: the device address
|
||||
* @retval None.
|
||||
*/
|
||||
void SetDeviceAddress(uint8_t Val)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t nEP = Device_Table.Total_Endpoint;
|
||||
|
||||
/* set address in every used endpoint */
|
||||
for (i = 0; i < nEP; i++)
|
||||
{
|
||||
_SetEPAddress((uint8_t)i, (uint8_t)i);
|
||||
} /* for */
|
||||
_SetDEVADR(Val | DEVADR_EN); /* set device address and enable function */
|
||||
}
|
||||
/**
|
||||
* @brief No operation function.
|
||||
* @param None.
|
||||
* @retval None.
|
||||
*/
|
||||
void NOP_Process(void)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
@@ -1,103 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* File : usb_init.c
|
||||
* Version: V1.2.2
|
||||
* Date : 2020-07-01
|
||||
* Brief : Initialization routines & global variables
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_lib.h"
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* The number of current endpoint, it will be used to specify an endpoint */
|
||||
uint8_t EPindex;
|
||||
/* The number of current device, it is an index to the Device_Table */
|
||||
/* uint8_t Device_no; */
|
||||
/* Points to the DEVICE_INFO structure of current device */
|
||||
/* The purpose of this register is to speed up the execution */
|
||||
DEVICE_INFO *pInformation;
|
||||
/* Points to the DEVICE_PROP structure of current device */
|
||||
/* The purpose of this register is to speed up the execution */
|
||||
DEVICE_PROP *pProperty;
|
||||
/* Temporary save the state of Rx & Tx status. */
|
||||
/* Whenever the Rx or Tx state is changed, its value is saved */
|
||||
/* in this variable first and will be set to the EPRB or EPRA */
|
||||
/* at the end of interrupt process */
|
||||
uint16_t SaveState ;
|
||||
uint16_t wInterrupt_Mask;
|
||||
DEVICE_INFO Device_Info;
|
||||
USER_STANDARD_REQUESTS *pUser_Standard_Requests;
|
||||
|
||||
/* Extern variables ----------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : USB_Init
|
||||
* Description : USB system initialization
|
||||
* Input : None.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
|
||||
/* Re-enumerate the USB */
|
||||
void reenumerate() {
|
||||
// pinMode(PA12, OUTPUT);
|
||||
GPIO_InitType GPIO_InitStruct = {0};
|
||||
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_12;
|
||||
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_PU;
|
||||
GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
GPIO_WriteBit(GPIOA, GPIO_Pins_12, Bit_RESET); //Blue Pill
|
||||
for(int i=0;i<1512;i++){};
|
||||
|
||||
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_12;
|
||||
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
for(int i=0;i<512;i++){};
|
||||
}
|
||||
|
||||
void USB_BluePill_Reenumerate()
|
||||
{
|
||||
//__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
|
||||
GPIO_InitType GPIO_InitStruct = {0};
|
||||
|
||||
GPIO_InitStruct.GPIO_Pins = GPIO_Pins_12;
|
||||
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT_OD;
|
||||
GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
GPIO_WriteBit(GPIOA, GPIO_Pins_12, Bit_RESET);
|
||||
//HAL_Delay(1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB system initialization.
|
||||
* @param None.
|
||||
* @retval None.
|
||||
*/
|
||||
void USB_Init(void)
|
||||
{
|
||||
//reenumerate();
|
||||
//USB_BluePill_Reenumerate();
|
||||
pInformation = &Device_Info;
|
||||
pInformation->ControlState = 2;
|
||||
pProperty = &Device_Property;
|
||||
pUser_Standard_Requests = &User_Standard_Requests;
|
||||
/* Initialize devices one by one */
|
||||
pProperty->Init();
|
||||
//reenumerate();
|
||||
//USB_BluePill_Reenumerate();
|
||||
}
|
||||
|
||||
|
||||
@@ -1,176 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* File : usb_int.c
|
||||
* Version: V1.2.2
|
||||
* Date : 2020-07-01
|
||||
* Brief : Endpoint CTRF (Low and High) interrupt's service routines
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_lib.h"
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
__IO uint16_t SaveRState;
|
||||
__IO uint16_t SaveTState;
|
||||
|
||||
/* Extern variables ----------------------------------------------------------*/
|
||||
extern void (*pEpInt_IN[7])(void); /* Handles IN interrupts */
|
||||
extern void (*pEpInt_OUT[7])(void); /* Handles OUT interrupts */
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Low priority Endpoint Correct Transfer interrupt's service.
|
||||
* routine.
|
||||
* @param None.
|
||||
* @retval None.
|
||||
*/
|
||||
void CTR_LP(void)
|
||||
{
|
||||
__IO uint16_t wEPVal = 0;
|
||||
/* stay in loop while pending interrupts */
|
||||
while (((wIstr = _GetINTSTS()) & INTSTS_CTFR) != 0)
|
||||
{
|
||||
/* extract highest priority endpoint number */
|
||||
EPindex = (uint8_t)(wIstr & INTSTS_EP_ID);
|
||||
if (EPindex != 0 )
|
||||
{
|
||||
/* Decode and service non control endpoints interrupt */
|
||||
|
||||
/* process related endpoint register */
|
||||
wEPVal = _GetENDPOINT(EPindex);
|
||||
if ((wEPVal & EP_CTFR_TX) != 0)
|
||||
{
|
||||
/* clear int flag */
|
||||
_ClearEP_CTFR_TX(EPindex);
|
||||
|
||||
/* call IN service function */
|
||||
(*pEpInt_IN[EPindex-1])();
|
||||
continue;
|
||||
} /* if((wEPVal & EP_CTFR_TX) != 0) */
|
||||
|
||||
if ((wEPVal & EP_CTFR_RX) != 0)
|
||||
{
|
||||
/* clear int flag */
|
||||
_ClearEP_CTFR_RX(EPindex);
|
||||
|
||||
/* call OUT service function */
|
||||
(*pEpInt_OUT[EPindex-1])();
|
||||
|
||||
} /* if((wEPVal & EP_CTFR_RX) */
|
||||
|
||||
}/* if(EPindex != 0) */
|
||||
else
|
||||
{
|
||||
/* Decode and service control endpoint interrupt */
|
||||
/* calling related service routine */
|
||||
/* (Setup0_Process, In0_Process, Out0_Process) */
|
||||
|
||||
/* save RX & TX status */
|
||||
/* and set both to NAK */
|
||||
|
||||
SaveRState = _GetENDPOINT(ENDP0);
|
||||
SaveTState = SaveRState & EP_STS_TX;
|
||||
SaveRState &= EP_STS_RX;
|
||||
|
||||
_SetEPRxTxStatus(ENDP0,EP_RX_NAK,EP_TX_NAK);
|
||||
|
||||
/* DIR bit = origin of the interrupt */
|
||||
|
||||
if ((wIstr & INTSTS_DIR) == 0)
|
||||
{
|
||||
/* DIR = 0 */
|
||||
|
||||
/* DIR = 0 => IN int */
|
||||
/* DIR = 0 implies that (EP_CTFR_TX = 1) always */
|
||||
|
||||
_ClearEP_CTFR_TX(ENDP0);
|
||||
In0_Process();
|
||||
|
||||
/* before terminate set Tx & Rx status */
|
||||
|
||||
_SetEPRxTxStatus(ENDP0,SaveRState,SaveTState);
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DIR = 1 */
|
||||
|
||||
/* DIR = 1 & CTR_RX => SETUP or OUT int */
|
||||
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
|
||||
|
||||
wEPVal = _GetENDPOINT(ENDP0);
|
||||
|
||||
if ((wEPVal &EP_SETUP) != 0)
|
||||
{
|
||||
_ClearEP_CTFR_RX(ENDP0); /* SETUP bit kept frozen while CTR_RX = 1 */
|
||||
Setup0_Process();
|
||||
/* before terminate set Tx & Rx status */
|
||||
|
||||
_SetEPRxTxStatus(ENDP0,SaveRState,SaveTState);
|
||||
return;
|
||||
}
|
||||
|
||||
else if ((wEPVal & EP_CTFR_RX) != 0)
|
||||
{
|
||||
_ClearEP_CTFR_RX(ENDP0);
|
||||
Out0_Process();
|
||||
/* before terminate set Tx & Rx status */
|
||||
|
||||
_SetEPRxTxStatus(ENDP0,SaveRState,SaveTState);
|
||||
return;
|
||||
}
|
||||
}
|
||||
}/* if(EPindex != 0) else */
|
||||
|
||||
}/* while(...) */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief High Priority Endpoint Correct Transfer interrupt's service.
|
||||
* routine.
|
||||
* @param None.
|
||||
* @retval None.
|
||||
*/
|
||||
void CTR_HP(void)
|
||||
{
|
||||
uint32_t wEPVal = 0;
|
||||
|
||||
while (((wIstr = _GetINTSTS()) & INTSTS_CTFR) != 0)
|
||||
{
|
||||
_SetINTSTS((uint16_t)CLR_CTFR); /* clear CTR flag */
|
||||
/* extract highest priority endpoint number */
|
||||
EPindex = (uint8_t)(wIstr & INTSTS_EP_ID);
|
||||
if ( EPindex == 0 )
|
||||
return;
|
||||
/* process related endpoint register */
|
||||
wEPVal = _GetENDPOINT(EPindex);
|
||||
if ((wEPVal & EP_CTFR_RX) != 0)
|
||||
{
|
||||
/* clear int flag */
|
||||
_ClearEP_CTFR_RX(EPindex);
|
||||
|
||||
/* call OUT service function */
|
||||
(*pEpInt_OUT[EPindex-1])();
|
||||
|
||||
} /* if((wEPVal & EP_CTFR_RX) */
|
||||
else if ((wEPVal & EP_CTFR_TX) != 0)
|
||||
{
|
||||
/* clear int flag */
|
||||
_ClearEP_CTFR_TX(EPindex);
|
||||
|
||||
/* call IN service function */
|
||||
(*pEpInt_IN[EPindex-1])();
|
||||
|
||||
|
||||
} /* if((wEPVal & EP_CTFR_TX) != 0) */
|
||||
|
||||
}/* while(...) */
|
||||
}
|
||||
|
||||
|
||||
@@ -1,65 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* File : usb_mem.c
|
||||
* Version: V1.2.2
|
||||
* Date : 2020-07-01
|
||||
* Brief : Utility functions for memory transfers to/from PMA
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_lib.h"
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Extern variables ----------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Copy a buffer from user memory area to packet memory area (PMA).
|
||||
* @param pbUsrBuf: pointer to user memory area.
|
||||
* @param wPMABufAddr: address into PMA.
|
||||
* @param wNBytes: number of bytes to be copied.
|
||||
* @retval None.
|
||||
*/
|
||||
void UserToPMABufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
|
||||
{
|
||||
uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */
|
||||
uint32_t i, temp1, temp2;
|
||||
uint16_t *pdwVal;
|
||||
pdwVal = (uint16_t *)(wPMABufAddr * 2 + PMAAddr);
|
||||
for (i = n; i != 0; i--)
|
||||
{
|
||||
temp1 = (uint16_t) * pbUsrBuf;
|
||||
pbUsrBuf++;
|
||||
temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
|
||||
*pdwVal++ = temp2;
|
||||
pdwVal++;
|
||||
pbUsrBuf++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Copy a buffer from packet memory area (PMA) to user memory area.
|
||||
* @param pbUsrBuf: pointer to user memory area.
|
||||
* @param wPMABufAddr: address into PMA.
|
||||
* @param wNBytes: number of bytes to be copied.
|
||||
* @retval None.
|
||||
*/
|
||||
void PMAToUserBufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
|
||||
{
|
||||
uint32_t n = (wNBytes + 1) >> 1;/* /2*/
|
||||
uint32_t i;
|
||||
uint32_t *pdwVal;
|
||||
pdwVal = (uint32_t *)(wPMABufAddr * 2 + PMAAddr);
|
||||
for (i = n; i != 0; i--)
|
||||
{
|
||||
*(uint16_t*)pbUsrBuf++ = *pdwVal++;
|
||||
pbUsrBuf++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -1,692 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* File : usb_reg.c
|
||||
* Version: V1.2.2
|
||||
* Date : 2020-07-01
|
||||
* Brief : Interface functions to USB cell registers
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_lib.h"
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Extern variables ----------------------------------------------------------*/
|
||||
int PMAAddr = 0x40006000;
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Set the CTRL register value.
|
||||
* @param wRegValue: new register value.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetCTRL(uint16_t wRegValue)
|
||||
{
|
||||
_SetCTRL(wRegValue);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief returns the CTRL register value.
|
||||
* @param None.
|
||||
* @retval CTRL register Value..
|
||||
*/
|
||||
uint16_t GetCTRL(void)
|
||||
{
|
||||
return(_GetCTRL());
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the INTSTS register value.
|
||||
* @param wRegValue: new register value.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetINTSTS(uint16_t wRegValue)
|
||||
{
|
||||
_SetINTSTS(wRegValue);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the INTSTS register value.
|
||||
* @param None.
|
||||
* @retval INTSTS register Value.
|
||||
*/
|
||||
uint16_t GetINTSTS(void)
|
||||
{
|
||||
return(_GetINTSTS());
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the FRNUM register value.
|
||||
* @param None.
|
||||
* @retval FRNUM register Value.
|
||||
*/
|
||||
uint16_t GetFRNUM(void)
|
||||
{
|
||||
return(_GetFRNUM());
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the DEVADR register value.
|
||||
* @param wRegValue: new register value.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetDEVADR(uint16_t wRegValue)
|
||||
{
|
||||
_SetDEVADR(wRegValue);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the DEVADR register value.
|
||||
* @param None.
|
||||
* @retval DEVADR register Value.
|
||||
*/
|
||||
uint16_t GetDEVADR(void)
|
||||
{
|
||||
return(_GetDEVADR());
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the BUFTBL.
|
||||
* @param wRegValue: New register value.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetBUFTBL(uint16_t wRegValue)
|
||||
{
|
||||
_SetBUFTBL(wRegValue);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the BUFTBL register value.
|
||||
* @param None
|
||||
* @retval BUFTBL address.
|
||||
*/
|
||||
uint16_t GetBUFTBL(void)
|
||||
{
|
||||
return(_GetBUFTBL());
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Endpoint register value.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wRegValue: New register value.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetENDPOINT(uint8_t bEpNum, uint16_t wRegValue)
|
||||
{
|
||||
_SetENDPOINT(bEpNum, wRegValue);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the Endpoint register value.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval Endpoint register value.
|
||||
*/
|
||||
uint16_t GetENDPOINT(uint8_t bEpNum)
|
||||
{
|
||||
return(_GetENDPOINT(bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief sets the type in the endpoint register.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wType: type definition.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPType(uint8_t bEpNum, uint16_t wType)
|
||||
{
|
||||
_SetEPType(bEpNum, wType);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the endpoint type.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval Endpoint Type.
|
||||
*/
|
||||
uint16_t GetEPType(uint8_t bEpNum)
|
||||
{
|
||||
return(_GetEPType(bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the status of Tx endpoint.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wState: new state.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPTxStatus(uint8_t bEpNum, uint16_t wState)
|
||||
{
|
||||
_SetEPTxStatus(bEpNum, wState);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the status of Rx endpoint.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wState: new state.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPRxStatus(uint8_t bEpNum, uint16_t wState)
|
||||
{
|
||||
_SetEPRxStatus(bEpNum, wState);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief sets the status for Double Buffer Endpoint to STALL
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param bDir: Endpoint direction.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetDouBleBuffEPStall(uint8_t bEpNum, uint8_t bDir)
|
||||
{
|
||||
uint16_t Endpoint_DTOG_Status;
|
||||
Endpoint_DTOG_Status = GetENDPOINT(bEpNum);
|
||||
if (bDir == EP_DBUF_OUT)
|
||||
{ /* OUT double buffered endpoint */
|
||||
_SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPRX_DTOG1);
|
||||
}
|
||||
else if (bDir == EP_DBUF_IN)
|
||||
{ /* IN double buffered endpoint */
|
||||
_SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPTX_DTOG1);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the endpoint Tx status.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval Endpoint TX Status.
|
||||
*/
|
||||
uint16_t GetEPTxStatus(uint8_t bEpNum)
|
||||
{
|
||||
return(_GetEPTxStatus(bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the endpoint Rx status.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval Endpoint RX Status.
|
||||
*/
|
||||
uint16_t GetEPRxStatus(uint8_t bEpNum)
|
||||
{
|
||||
return(_GetEPRxStatus(bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Valid the endpoint Tx Status.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPTxValid(uint8_t bEpNum)
|
||||
{
|
||||
_SetEPTxStatus(bEpNum, EP_TX_VALID);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Valid the endpoint Rx Status.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPRxValid(uint8_t bEpNum)
|
||||
{
|
||||
_SetEPRxStatus(bEpNum, EP_RX_VALID);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the EP_SUBTYPE bit.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEP_SUBTYPE(uint8_t bEpNum)
|
||||
{
|
||||
_SetEP_SUBTYPE(bEpNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set the EP_SUBTYPE bit.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None.
|
||||
*/
|
||||
void ClearEP_SUBTYPE(uint8_t bEpNum)
|
||||
{
|
||||
_ClearEP_SUBTYPE(bEpNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the Status Out of the related Endpoint
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None.
|
||||
*/
|
||||
void Clear_Status_Out(uint8_t bEpNum)
|
||||
{
|
||||
_ClearEP_SUBTYPE(bEpNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Status Out of the related Endpoint
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None.
|
||||
*/
|
||||
void Set_Status_Out(uint8_t bEpNum)
|
||||
{
|
||||
_SetEP_SUBTYPE(bEpNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the double buffer feature for the endpoint.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPDoubleBuff(uint8_t bEpNum)
|
||||
{
|
||||
_SetEP_SUBTYPE(bEpNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the double buffer feature for the endpoint.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None.
|
||||
*/
|
||||
void ClearEPDoubleBuff(uint8_t bEpNum)
|
||||
{
|
||||
_ClearEP_SUBTYPE(bEpNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the Stall status of the Tx endpoint.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval Tx Stall status.
|
||||
*/
|
||||
uint16_t GetTxStallStatus(uint8_t bEpNum)
|
||||
{
|
||||
return(_GetTxStallStatus(bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the Stall status of the Rx endpoint.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval Rx Stall status.
|
||||
*/
|
||||
uint16_t GetRxStallStatus(uint8_t bEpNum)
|
||||
{
|
||||
return(_GetRxStallStatus(bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the CTRF_RX bit.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None.
|
||||
*/
|
||||
void ClearEP_CTFR_RX(uint8_t bEpNum)
|
||||
{
|
||||
_ClearEP_CTFR_RX(bEpNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the CTRF_TX bit.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None.
|
||||
*/
|
||||
void ClearEP_CTFR_TX(uint8_t bEpNum)
|
||||
{
|
||||
_ClearEP_CTFR_TX(bEpNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggle the DTOG_RX bit.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None.
|
||||
*/
|
||||
void ToggleDTOG_RX(uint8_t bEpNum)
|
||||
{
|
||||
_ToggleDTOG_RX(bEpNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggle the DTOG_TX bit.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None.
|
||||
*/
|
||||
void ToggleDTOG_TX(uint8_t bEpNum)
|
||||
{
|
||||
_ToggleDTOG_TX(bEpNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the DTOG_RX bit.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None.
|
||||
*/
|
||||
void ClearDTOG_RX(uint8_t bEpNum)
|
||||
{
|
||||
_ClearDTOG_RX(bEpNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the DTOG_TX bit.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None.
|
||||
*/
|
||||
void ClearDTOG_TX(uint8_t bEpNum)
|
||||
{
|
||||
_ClearDTOG_TX(bEpNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the endpoint address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param bAddr: New endpoint address.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPAddress(uint8_t bEpNum, uint8_t bAddr)
|
||||
{
|
||||
_SetEPAddress(bEpNum, bAddr);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the endpoint address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval Endpoint address.
|
||||
*/
|
||||
uint8_t GetEPAddress(uint8_t bEpNum)
|
||||
{
|
||||
return(_GetEPAddress(bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the endpoint Tx buffer address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wAddr: New address.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPTxAddr(uint8_t bEpNum, uint16_t wAddr)
|
||||
{
|
||||
_SetEPTxAddr(bEpNum, wAddr);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the endpoint Rx buffer address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wAddr: New address.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPRxAddr(uint8_t bEpNum, uint16_t wAddr)
|
||||
{
|
||||
_SetEPRxAddr(bEpNum, wAddr);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the endpoint Tx buffer address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval Tx buffer address.
|
||||
*/
|
||||
uint16_t GetEPTxAddr(uint8_t bEpNum)
|
||||
{
|
||||
return(_GetEPTxAddr(bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the endpoint Rx buffer address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval Rx buffer address.
|
||||
*/
|
||||
uint16_t GetEPRxAddr(uint8_t bEpNum)
|
||||
{
|
||||
return(_GetEPRxAddr(bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Tx count.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wCount: new count value.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPTxCount(uint8_t bEpNum, uint16_t wCount)
|
||||
{
|
||||
_SetEPTxCount(bEpNum, wCount);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Count Rx Register value.
|
||||
* @param *pdwReg: point to the register.
|
||||
* @param wCount: the new register value.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPCountRxReg(uint32_t *pdwReg, uint16_t wCount)
|
||||
{
|
||||
_SetEPCountRxReg(dwReg, wCount);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Rx count.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wCount: the new count value.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPRxCount(uint8_t bEpNum, uint16_t wCount)
|
||||
{
|
||||
_SetEPRxCount(bEpNum, wCount);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Tx count.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval Tx count value.
|
||||
*/
|
||||
uint16_t GetEPTxCount(uint8_t bEpNum)
|
||||
{
|
||||
return(_GetEPTxCount(bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the Rx count.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval Rx count value.
|
||||
*/
|
||||
uint16_t GetEPRxCount(uint8_t bEpNum)
|
||||
{
|
||||
return(_GetEPRxCount(bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the addresses of the buffer 0 and 1.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wBuf0Addr: new address of buffer 0.
|
||||
* @param wBuf1Addr: new address of buffer 1.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPDblBuffAddr(uint8_t bEpNum, uint16_t wBuf0Addr, uint16_t wBuf1Addr)
|
||||
{
|
||||
_SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Buffer 0 address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wBuf0Addr: new address of buffer 0.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPDblBuf0Addr(uint8_t bEpNum, uint16_t wBuf0Addr)
|
||||
{
|
||||
_SetEPDblBuf0Addr(bEpNum, wBuf0Addr);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Buffer 1 address.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param wBuf1Addr: new address of buffer 1.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPDblBuf1Addr(uint8_t bEpNum, uint16_t wBuf1Addr)
|
||||
{
|
||||
_SetEPDblBuf1Addr(bEpNum, wBuf1Addr);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the address of the Buffer 0.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval buffer 0 address.
|
||||
*/
|
||||
uint16_t GetEPDblBuf0Addr(uint8_t bEpNum)
|
||||
{
|
||||
return(_GetEPDblBuf0Addr(bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the address of the Buffer 1.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval buffer 1 address.
|
||||
*/
|
||||
uint16_t GetEPDblBuf1Addr(uint8_t bEpNum)
|
||||
{
|
||||
return(_GetEPDblBuf1Addr(bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the number of bytes for a double Buffer endpoint.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param bDin: Endpoint dir (IN/OUT).
|
||||
* @param wCount: buffer count.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPDblBuffCount(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
|
||||
{
|
||||
_SetEPDblBuffCount(bEpNum, bDir, wCount);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the number of bytes for a double Buffer0 endpoint.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param bDin: Endpoint dir (IN/OUT).
|
||||
* @param wCount: buffer count.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPDblBuf0Count(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
|
||||
{
|
||||
_SetEPDblBuf0Count(bEpNum, bDir, wCount);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the number of bytes for a double Buffer1 endpoint.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param bDin: Endpoint dir (IN/OUT).
|
||||
* @param wCount: buffer count.
|
||||
* @retval None.
|
||||
*/
|
||||
void SetEPDblBuf1Count(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
|
||||
{
|
||||
_SetEPDblBuf1Count(bEpNum, bDir, wCount);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of byte received in the buffer 0
|
||||
of a double Buffer endpoint.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval Endpoint Buffer 0 count.
|
||||
*/
|
||||
uint16_t GetEPDblBuf0Count(uint8_t bEpNum)
|
||||
{
|
||||
return(_GetEPDblBuf0Count(bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of byte received in the buffer 1
|
||||
of a double Buffer endpoint.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval Endpoint Buffer 1 count.
|
||||
*/
|
||||
uint16_t GetEPDblBuf1Count(uint8_t bEpNum)
|
||||
{
|
||||
return(_GetEPDblBuf1Count(bEpNum));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief gets direction of the double buffered endpoint.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @retval EP_DBUF_OUT, EP_DBUF_IN,
|
||||
* EP_DBUF_ERR if the endpoint counter not yet programmed.
|
||||
*/
|
||||
EP_DBUF_DIR GetEPDblBufDir(uint8_t bEpNum)
|
||||
{
|
||||
if ((uint16_t)(*_pEPRxCount(bEpNum) & 0xFC00) != 0)
|
||||
return(EP_DBUF_OUT);
|
||||
else if (((uint16_t)(*_pEPTxCount(bEpNum)) & 0x03FF) != 0)
|
||||
return(EP_DBUF_IN);
|
||||
else
|
||||
return(EP_DBUF_ERR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief free buffer used from the application realizing it to the line
|
||||
toggles bit SW_BUF in the double buffered endpoint register.
|
||||
* @param bEpNum: Endpoint Number.
|
||||
* @param bDir: Endpoint dir (IN/OUT).
|
||||
* @retval None.
|
||||
*/
|
||||
void FreeUserBuffer(uint8_t bEpNum, uint8_t bDir)
|
||||
{
|
||||
if (bDir == EP_DBUF_OUT)
|
||||
{ /* OUT double buffered endpoint */
|
||||
_ToggleDTOG_TX(bEpNum);
|
||||
}
|
||||
else if (bDir == EP_DBUF_IN)
|
||||
{ /* IN double buffered endpoint */
|
||||
_ToggleDTOG_RX(bEpNum);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief merge two byte in a word.
|
||||
* @param bh: byte high.
|
||||
* @param bl: bytes low.
|
||||
* @retval resulted word..
|
||||
*/
|
||||
uint16_t ToWord(uint8_t bh, uint8_t bl)
|
||||
{
|
||||
uint16_t wRet;
|
||||
wRet = (uint16_t)bl | ((uint16_t)bh << 8);
|
||||
return(wRet);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Swap two byte in a word.
|
||||
* @param wSwW: word to Swap.
|
||||
* @retval resulted word..
|
||||
*/
|
||||
uint16_t ByteSwap(uint16_t wSwW)
|
||||
{
|
||||
uint8_t bTemp;
|
||||
uint16_t wRet;
|
||||
bTemp = (uint8_t)(wSwW & 0xff);
|
||||
wRet = (wSwW >> 8) | ((uint16_t)bTemp << 8);
|
||||
return(wRet);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set USB SRAM size to 768 byte.
|
||||
* @param None.
|
||||
* @retval None..
|
||||
*/
|
||||
void Set_USB768ByteMode(void)
|
||||
{
|
||||
/*Enable 768 Byte, Enable RCC->MISC*/
|
||||
RCC->MISC |= 0x1 << 24;
|
||||
|
||||
/*USB SRAM Base address*/
|
||||
PMAAddr = 0x40007800;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear USB 768 byte mode, USB SRAM size is 512 byte.
|
||||
* @param None.
|
||||
* @retval None..
|
||||
*/
|
||||
void Clear_USB768ByteMode(void)
|
||||
{
|
||||
/*Clear 768 byte mode*/
|
||||
RCC->MISC &= ~(0x1 << 24);
|
||||
|
||||
/*USB SRAM Base address*/
|
||||
PMAAddr = 0x40006000;
|
||||
}
|
||||
@@ -59,6 +59,9 @@ env.Append(
|
||||
"-fno-exceptions",
|
||||
],
|
||||
CPPPATH=[
|
||||
join(FRAMEWORK_DIR, "libraries", "AT32F43x_StdPeriph_Driver", "include"),
|
||||
join(FRAMEWORK_DIR, "libraries", "AT32F43x_USB-Device_Driver", "include"),
|
||||
join(FRAMEWORK_DIR, "libraries", "AT32F435_437_board"),
|
||||
],
|
||||
LIBS=[
|
||||
"c",
|
||||
@@ -86,18 +89,20 @@ env.Append(ASFLAGS=env.get("CCFLAGS", [])[:])
|
||||
# Target: Build Core Library
|
||||
#
|
||||
|
||||
|
||||
libs = []
|
||||
|
||||
libs.append(
|
||||
env.BuildLibrary(
|
||||
libs.append(env.BuildLibrary(
|
||||
join("$BUILD_DIR", "AT32F43x_StdPeriph"), join(FRAMEWORK_DIR, "libraries", "AT32F43x_StdPeriph_Driver")
|
||||
)
|
||||
)
|
||||
))
|
||||
libs.append(env.BuildLibrary(
|
||||
join("$BUILD_DIR", "AT32F43x_USB-Device"), join(FRAMEWORK_DIR, "libraries", "AT32F43x_USB-Device_Driver")
|
||||
))
|
||||
libs.append(env.BuildLibrary(
|
||||
join("$BUILD_DIR", "AT32F435_437_board"), join(FRAMEWORK_DIR, "libraries", "AT32F435_437_board")
|
||||
))
|
||||
|
||||
#libs.append(
|
||||
#env.BuildLibrary(
|
||||
#join("$BUILD_DIR", "AT32_USB-FS-Device"), join(FRAMEWORK_DIR, "libraries", "AT32_USB-FS-Device_Driver")
|
||||
#)
|
||||
#)
|
||||
|
||||
#print("BuildLibrary(): " + env.subst(join(FRAMEWORK_DIR, "libraries", "AT32F43x_USB-FS-Device_Driver")) )
|
||||
|
||||
env.Prepend(LIBS=libs)
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
"build": {
|
||||
"core": "at32",
|
||||
"cpu": "cortex-m4",
|
||||
"extra_flags": "-DAT32F435CGT7",
|
||||
"extra_flags": "-DAT32F435CGT7 -DAT_START_F435_V1",
|
||||
"f_cpu": "288000000L",
|
||||
"hwids": [
|
||||
[
|
||||
|
||||
@@ -2,10 +2,23 @@
|
||||
#include "at32f435_437_clock.h"
|
||||
#include "delay.h"
|
||||
|
||||
#define LEDPERIPH CRM_GPIOB_PERIPH_CLOCK
|
||||
#define LEDPORT (GPIOB)
|
||||
#define LEDPIN (GPIO_PINS_12)
|
||||
#define BLACKPILL // BLUEPILL BLACKPILL QFP48_FLASHER
|
||||
|
||||
#ifdef BLUEPILL
|
||||
#define LEDPERIPH CRM_GPIOC_PERIPH_CLOCK
|
||||
#define LEDPORT (GPIOC)
|
||||
#define LEDPIN (GPIO_PINS_13)
|
||||
#endif
|
||||
#ifdef BLACKPILL
|
||||
#define LEDPERIPH CRM_GPIOB_PERIPH_CLOCK
|
||||
#define LEDPORT (GPIOB)
|
||||
#define LEDPIN (GPIO_PINS_12)
|
||||
#endif
|
||||
#ifdef QFP48_FLASHER
|
||||
#define LEDPERIPH CRM_GPIOB_PERIPH_CLOCK
|
||||
#define LEDPORT (GPIOB)
|
||||
#define LEDPIN (GPIO_PINS_14)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief gpio configuration.
|
||||
1
.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/.gitignore
vendored
Normal file
1
.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/.gitignore
vendored
Normal file
@@ -0,0 +1 @@
|
||||
.pio
|
||||
@@ -0,0 +1,67 @@
|
||||
# Continuous Integration (CI) is the practice, in software
|
||||
# engineering, of merging all developer working copies with a shared mainline
|
||||
# several times a day < https://docs.platformio.org/page/ci/index.html >
|
||||
#
|
||||
# Documentation:
|
||||
#
|
||||
# * Travis CI Embedded Builds with PlatformIO
|
||||
# < https://docs.travis-ci.com/user/integration/platformio/ >
|
||||
#
|
||||
# * PlatformIO integration with Travis CI
|
||||
# < https://docs.platformio.org/page/ci/travis.html >
|
||||
#
|
||||
# * User Guide for `platformio ci` command
|
||||
# < https://docs.platformio.org/page/userguide/cmd_ci.html >
|
||||
#
|
||||
#
|
||||
# Please choose one of the following templates (proposed below) and uncomment
|
||||
# it (remove "# " before each line) or use own configuration according to the
|
||||
# Travis CI documentation (see above).
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# Template #1: General project. Test it using existing `platformio.ini`.
|
||||
#
|
||||
|
||||
# language: python
|
||||
# python:
|
||||
# - "2.7"
|
||||
#
|
||||
# sudo: false
|
||||
# cache:
|
||||
# directories:
|
||||
# - "~/.platformio"
|
||||
#
|
||||
# install:
|
||||
# - pip install -U platformio
|
||||
# - platformio update
|
||||
#
|
||||
# script:
|
||||
# - platformio run
|
||||
|
||||
|
||||
#
|
||||
# Template #2: The project is intended to be used as a library with examples.
|
||||
#
|
||||
|
||||
# language: python
|
||||
# python:
|
||||
# - "2.7"
|
||||
#
|
||||
# sudo: false
|
||||
# cache:
|
||||
# directories:
|
||||
# - "~/.platformio"
|
||||
#
|
||||
# env:
|
||||
# - PLATFORMIO_CI_SRC=path/to/test/file.c
|
||||
# - PLATFORMIO_CI_SRC=examples/file.ino
|
||||
# - PLATFORMIO_CI_SRC=path/to/test/directory
|
||||
#
|
||||
# install:
|
||||
# - pip install -U platformio
|
||||
# - platformio update
|
||||
#
|
||||
# script:
|
||||
# - platformio ci --lib="." --board=ID_1 --board=ID_2 --board=ID_N
|
||||
@@ -0,0 +1,55 @@
|
||||
//
|
||||
// !!! WARNING !!! AUTO-GENERATED FILE!
|
||||
// PLEASE DO NOT MODIFY IT AND USE "platformio.ini":
|
||||
// https://docs.platformio.org/page/projectconf/section_env_build.html#build-flags
|
||||
//
|
||||
{
|
||||
"configurations": [
|
||||
{
|
||||
"name": "PlatformIO",
|
||||
"includePath": [
|
||||
"c:/Users/Xliloz/.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/include",
|
||||
"c:/Users/Xliloz/.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/src",
|
||||
"c:/Users/Xliloz/.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/lib/cdc",
|
||||
"C:/Users/Xliloz/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include",
|
||||
"C:/Users/Xliloz/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_USB-Device_Driver/include",
|
||||
"C:/Users/Xliloz/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F435_437_board",
|
||||
"C:/Users/Xliloz/.platformio/packages/framework-cmsis@2.50501.200527/CMSIS/Include",
|
||||
"C:/Users/Xliloz/.platformio/packages/framework-cmsis-at32f43/Include",
|
||||
""
|
||||
],
|
||||
"browse": {
|
||||
"limitSymbolsToIncludedHeaders": true,
|
||||
"path": [
|
||||
"c:/Users/Xliloz/.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/include",
|
||||
"c:/Users/Xliloz/.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/src",
|
||||
"c:/Users/Xliloz/.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/lib/cdc",
|
||||
"C:/Users/Xliloz/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_StdPeriph_Driver/include",
|
||||
"C:/Users/Xliloz/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F43x_USB-Device_Driver/include",
|
||||
"C:/Users/Xliloz/.platformio/packages/framework-cmsis-at32f43/libraries/AT32F435_437_board",
|
||||
"C:/Users/Xliloz/.platformio/packages/framework-cmsis@2.50501.200527/CMSIS/Include",
|
||||
"C:/Users/Xliloz/.platformio/packages/framework-cmsis-at32f43/Include",
|
||||
""
|
||||
]
|
||||
},
|
||||
"defines": [
|
||||
"PLATFORMIO=50205",
|
||||
"AT32F435CGT7",
|
||||
"AT_START_F435_V1",
|
||||
""
|
||||
],
|
||||
"cStandard": "c11",
|
||||
"compilerPath": "C:/Users/Xliloz/.platformio/packages/toolchain-gccarmnoneeabi@1.70201.0/bin/arm-none-eabi-gcc.exe",
|
||||
"compilerArgs": [
|
||||
"-mfpu=fpv4-sp-d16",
|
||||
"-mfloat-abi=hard",
|
||||
"-mcpu=cortex-m4",
|
||||
"-mthumb",
|
||||
"-mfpu=fpv4-sp-d16",
|
||||
"-mfloat-abi=hard",
|
||||
""
|
||||
]
|
||||
}
|
||||
],
|
||||
"version": 4
|
||||
}
|
||||
10
.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/.vscode/extensions.json
vendored
Normal file
10
.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/.vscode/extensions.json
vendored
Normal file
@@ -0,0 +1,10 @@
|
||||
{
|
||||
// See http://go.microsoft.com/fwlink/?LinkId=827846
|
||||
// for the documentation about the extensions.json format
|
||||
"recommendations": [
|
||||
"platformio.platformio-ide"
|
||||
],
|
||||
"unwantedRecommendations": [
|
||||
"ms-vscode.cpptools-extension-pack"
|
||||
]
|
||||
}
|
||||
44
.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/.vscode/launch.json
vendored
Normal file
44
.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/.vscode/launch.json
vendored
Normal file
@@ -0,0 +1,44 @@
|
||||
// AUTOMATICALLY GENERATED FILE. PLEASE DO NOT MODIFY IT MANUALLY
|
||||
//
|
||||
// PIO Unified Debugger
|
||||
//
|
||||
// Documentation: https://docs.platformio.org/page/plus/debugging.html
|
||||
// Configuration: https://docs.platformio.org/page/projectconf/section_env_debug.html
|
||||
|
||||
{
|
||||
"version": "0.2.0",
|
||||
"configurations": [
|
||||
{
|
||||
"type": "platformio-debug",
|
||||
"request": "launch",
|
||||
"name": "PIO Debug",
|
||||
"executable": "c:/Users/Xliloz/.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/.pio/build/vcp_loopback/firmware.elf",
|
||||
"projectEnvName": "vcp_loopback",
|
||||
"toolchainBinDir": "C:/Users/Xliloz/.platformio/packages/toolchain-gccarmnoneeabi@1.70201.0/bin",
|
||||
"internalConsoleOptions": "openOnSessionStart",
|
||||
"preLaunchTask": {
|
||||
"type": "PlatformIO",
|
||||
"task": "Pre-Debug"
|
||||
}
|
||||
},
|
||||
{
|
||||
"type": "platformio-debug",
|
||||
"request": "launch",
|
||||
"name": "PIO Debug (skip Pre-Debug)",
|
||||
"executable": "c:/Users/Xliloz/.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/.pio/build/vcp_loopback/firmware.elf",
|
||||
"projectEnvName": "vcp_loopback",
|
||||
"toolchainBinDir": "C:/Users/Xliloz/.platformio/packages/toolchain-gccarmnoneeabi@1.70201.0/bin",
|
||||
"internalConsoleOptions": "openOnSessionStart"
|
||||
},
|
||||
{
|
||||
"type": "platformio-debug",
|
||||
"request": "launch",
|
||||
"name": "PIO Debug (without uploading)",
|
||||
"executable": "c:/Users/Xliloz/.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/.pio/build/vcp_loopback/firmware.elf",
|
||||
"projectEnvName": "vcp_loopback",
|
||||
"toolchainBinDir": "C:/Users/Xliloz/.platformio/packages/toolchain-gccarmnoneeabi@1.70201.0/bin",
|
||||
"internalConsoleOptions": "openOnSessionStart",
|
||||
"loadMode": "manual"
|
||||
}
|
||||
]
|
||||
}
|
||||
5
.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/.vscode/settings.json
vendored
Normal file
5
.platformio/platforms/at32/examples/AT32F435/usb_device/vcp_loopback/.vscode/settings.json
vendored
Normal file
@@ -0,0 +1,5 @@
|
||||
{
|
||||
"files.associations": {
|
||||
"at32f4xx.h": "c"
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,46 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_clock.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief header file of clock program
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_CLOCK_H
|
||||
#define __AT32F435_437_CLOCK_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/* exported functions ------------------------------------------------------- */
|
||||
void system_clock_config(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -32,12 +32,13 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief in the following line adjust the value of high speed exernal crystal (hext)
|
||||
* used in your application
|
||||
*
|
||||
* tip: to avoid modifying this file each time you need to use different hext, you
|
||||
* can define the hext value in your toolchain compiler preprocessor.
|
||||
*
|
||||
*/
|
||||
#if !defined HEXT_VALUE
|
||||
#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed exernal crystal in hz */
|
||||
@@ -165,11 +166,9 @@ extern "C" {
|
||||
#ifdef USB_MODULE_ENABLED
|
||||
#include "at32f435_437_usb.h"
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __AT32F435_437_CONF_H */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,58 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_int.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief header file of main interrupt service routines.
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F435_437_INT_H
|
||||
#define __AT32F435_437_INT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437.h"
|
||||
|
||||
/* exported types ------------------------------------------------------------*/
|
||||
/* exported constants --------------------------------------------------------*/
|
||||
/* exported macro ------------------------------------------------------------*/
|
||||
/* exported functions ------------------------------------------------------- */
|
||||
|
||||
void NMI_Handler(void);
|
||||
void HardFault_Handler(void);
|
||||
void MemManage_Handler(void);
|
||||
void BusFault_Handler(void);
|
||||
void UsageFault_Handler(void);
|
||||
void SVC_Handler(void);
|
||||
void DebugMon_Handler(void);
|
||||
void PendSV_Handler(void);
|
||||
void SysTick_Handler(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,218 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file usb_conf.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief usb config header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_CONF_H
|
||||
#define __USB_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "at32f435_437_usb.h"
|
||||
#include "at32f435_437.h"
|
||||
#include "stdio.h"
|
||||
|
||||
/** @addtogroup AT32F435_periph_examples
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup 435_USB_device_vcp_loopback
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief enable usb device mode
|
||||
*/
|
||||
#define USE_OTG_DEVICE_MODE
|
||||
|
||||
/**
|
||||
* @brief enable usb host mode
|
||||
*/
|
||||
/* #define USE_OTG_HOST_MODE */
|
||||
|
||||
/**
|
||||
* @brief select otgfs1 or otgfs2 define
|
||||
*/
|
||||
|
||||
/* use otgfs1 */
|
||||
#define OTG_USB_ID 1
|
||||
|
||||
/* use otgfs2 */
|
||||
//#define OTG_USB_ID 2
|
||||
|
||||
#if (OTG_USB_ID == 1)
|
||||
#define USB_ID 0
|
||||
#define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK
|
||||
#define OTG_IRQ OTGFS1_IRQn
|
||||
#define OTG_IRQ_HANDLER OTGFS1_IRQHandler
|
||||
#define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn
|
||||
#define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler
|
||||
#define OTG_WKUP_EXINT_LINE EXINT_LINE_18
|
||||
|
||||
#define OTG_PIN_GPIO GPIOA
|
||||
#define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK
|
||||
|
||||
#define OTG_PIN_DP GPIO_PINS_12
|
||||
#define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE12
|
||||
|
||||
#define OTG_PIN_DM GPIO_PINS_11
|
||||
#define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE11
|
||||
|
||||
#define OTG_PIN_VBUS GPIO_PINS_9
|
||||
#define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9
|
||||
|
||||
#define OTG_PIN_ID GPIO_PINS_10
|
||||
#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10
|
||||
|
||||
#define OTG_PIN_SOF_GPIO GPIOA
|
||||
#define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK
|
||||
#define OTG_PIN_SOF GPIO_PINS_8
|
||||
#define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8
|
||||
|
||||
#define OTG_PIN_MUX GPIO_MUX_10
|
||||
#endif
|
||||
|
||||
#if (OTG_USB_ID == 2)
|
||||
#define USB_ID 1
|
||||
#define OTG_CLOCK CRM_OTGFS2_PERIPH_CLOCK
|
||||
#define OTG_IRQ OTGFS2_IRQn
|
||||
#define OTG_IRQ_HANDLER OTGFS2_IRQHandler
|
||||
#define OTG_WKUP_IRQ OTGFS2_WKUP_IRQn
|
||||
#define OTG_WKUP_HANDLER OTGFS2_WKUP_IRQHandler
|
||||
#define OTG_WKUP_EXINT_LINE EXINT_LINE_20
|
||||
|
||||
#define OTG_PIN_GPIO GPIOB
|
||||
#define OTG_PIN_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK
|
||||
|
||||
#define OTG_PIN_DP GPIO_PINS_15
|
||||
#define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE15
|
||||
|
||||
#define OTG_PIN_DM GPIO_PINS_14
|
||||
#define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE14
|
||||
|
||||
#define OTG_PIN_VBUS GPIO_PINS_13
|
||||
#define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13
|
||||
|
||||
#define OTG_PIN_ID GPIO_PINS_12
|
||||
#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10
|
||||
|
||||
#define OTG_PIN_SOF_GPIO GPIOA
|
||||
#define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK
|
||||
#define OTG_PIN_SOF GPIO_PINS_4
|
||||
#define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE4
|
||||
|
||||
#define OTG_PIN_MUX GPIO_MUX_12
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief usb device mode config
|
||||
*/
|
||||
#ifdef USE_OTG_DEVICE_MODE
|
||||
/**
|
||||
* @brief usb device mode fifo
|
||||
*/
|
||||
/* otg1 device fifo */
|
||||
#define USBD_RX_SIZE 128
|
||||
#define USBD_EP0_TX_SIZE 24
|
||||
#define USBD_EP1_TX_SIZE 20
|
||||
#define USBD_EP2_TX_SIZE 20
|
||||
#define USBD_EP3_TX_SIZE 20
|
||||
#define USBD_EP4_TX_SIZE 20
|
||||
#define USBD_EP5_TX_SIZE 20
|
||||
#define USBD_EP6_TX_SIZE 20
|
||||
#define USBD_EP7_TX_SIZE 20
|
||||
|
||||
/* otg2 device fifo */
|
||||
#define USBD2_RX_SIZE 128
|
||||
#define USBD2_EP0_TX_SIZE 24
|
||||
#define USBD2_EP1_TX_SIZE 20
|
||||
#define USBD2_EP2_TX_SIZE 20
|
||||
#define USBD2_EP3_TX_SIZE 20
|
||||
#define USBD2_EP4_TX_SIZE 20
|
||||
#define USBD2_EP5_TX_SIZE 20
|
||||
#define USBD2_EP6_TX_SIZE 20
|
||||
#define USBD2_EP7_TX_SIZE 20
|
||||
|
||||
/**
|
||||
* @brief usb endpoint max num define
|
||||
*/
|
||||
#ifndef USB_EPT_MAX_NUM
|
||||
#define USB_EPT_MAX_NUM 8
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief usb host mode config
|
||||
*/
|
||||
#ifdef USE_OTG_HOST_MODE
|
||||
#ifndef USB_HOST_CHANNEL_NUM
|
||||
#define USB_HOST_CHANNEL_NUM 16
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief usb host mode fifo
|
||||
*/
|
||||
/* otg1 host fifo */
|
||||
#define USBH_RX_FIFO_SIZE 128
|
||||
#define USBH_NP_TX_FIFO_SIZE 96
|
||||
#define USBH_P_TX_FIFO_SIZE 96
|
||||
|
||||
/* otg2 host fifo */
|
||||
#define USBH2_RX_FIFO_SIZE 128
|
||||
#define USBH2_NP_TX_FIFO_SIZE 96
|
||||
#define USBH2_P_TX_FIFO_SIZE 96
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief usb sof output enable
|
||||
*/
|
||||
/* #define USB_SOF_OUTPUT_ENABLE */
|
||||
|
||||
/**
|
||||
* @brief usb vbus ignore, not use vbus pin
|
||||
*/
|
||||
#define USB_VBUS_IGNORE
|
||||
|
||||
/**
|
||||
* @brief usb low power wakeup handler enable
|
||||
*/
|
||||
/* #define USB_LOW_POWER_WAKUP */
|
||||
|
||||
void usb_delay_ms(uint32_t ms);
|
||||
void usb_delay_us(uint32_t us);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,46 @@
|
||||
|
||||
This directory is intended for project specific (private) libraries.
|
||||
PlatformIO will compile them to static libraries and link into executable file.
|
||||
|
||||
The source code of each library should be placed in a an own separate directory
|
||||
("lib/your_library_name/[here are source files]").
|
||||
|
||||
For example, see a structure of the following two libraries `Foo` and `Bar`:
|
||||
|
||||
|--lib
|
||||
| |
|
||||
| |--Bar
|
||||
| | |--docs
|
||||
| | |--examples
|
||||
| | |--src
|
||||
| | |- Bar.c
|
||||
| | |- Bar.h
|
||||
| | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html
|
||||
| |
|
||||
| |--Foo
|
||||
| | |- Foo.c
|
||||
| | |- Foo.h
|
||||
| |
|
||||
| |- README --> THIS FILE
|
||||
|
|
||||
|- platformio.ini
|
||||
|--src
|
||||
|- main.c
|
||||
|
||||
and a contents of `src/main.c`:
|
||||
```
|
||||
#include <Foo.h>
|
||||
#include <Bar.h>
|
||||
|
||||
int main (void)
|
||||
{
|
||||
...
|
||||
}
|
||||
|
||||
```
|
||||
|
||||
PlatformIO Library Dependency Finder will find automatically dependent
|
||||
libraries scanning project source files.
|
||||
|
||||
More information about PlatformIO Library Dependency Finder
|
||||
- https://docs.platformio.org/page/librarymanager/ldf.html
|
||||
@@ -0,0 +1,413 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file cdc_class.c
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief usb cdc class type
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
#include "usbd_core.h"
|
||||
#include "cdc_class.h"
|
||||
#include "cdc_desc.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_middlewares_usbd_class
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_cdc_class
|
||||
* @brief usb device class cdc demo
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_cdc_class_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
usb_sts_type class_init_handler(void *udev);
|
||||
usb_sts_type class_clear_handler(void *udev);
|
||||
usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup);
|
||||
usb_sts_type class_ept0_tx_handler(void *udev);
|
||||
usb_sts_type class_ept0_rx_handler(void *udev);
|
||||
usb_sts_type class_in_handler(void *udev, uint8_t ept_num);
|
||||
usb_sts_type class_out_handler(void *udev, uint8_t ept_num);
|
||||
usb_sts_type class_sof_handler(void *udev);
|
||||
usb_sts_type class_event_handler(void *udev, usbd_event_type event);
|
||||
|
||||
void usb_vcp_cmd_process(void *udev, uint8_t cmd, uint8_t *buff, uint16_t len);
|
||||
/* usb rx and tx buffer */
|
||||
static uint32_t alt_setting = 0;
|
||||
static uint8_t g_rx_buff[USBD_OUT_MAXPACKET_SIZE];
|
||||
//static uint8_t g_tx_buff[USBD_IN_MAXPACKET_SIZE];
|
||||
static uint8_t g_cmd[USBD_CMD_MAXPACKET_SIZE];
|
||||
static uint8_t g_req;
|
||||
static uint16_t g_len, g_rxlen;
|
||||
__IO uint8_t g_tx_completed = 1, g_rx_completed = 0;
|
||||
|
||||
linecoding_type linecoding =
|
||||
{
|
||||
115200,
|
||||
0x00,
|
||||
0x00,
|
||||
0x08
|
||||
};
|
||||
|
||||
/* static variable */
|
||||
|
||||
|
||||
/* usb device class handler */
|
||||
usbd_class_handler class_handler =
|
||||
{
|
||||
class_init_handler,
|
||||
class_clear_handler,
|
||||
class_setup_handler,
|
||||
class_ept0_tx_handler,
|
||||
class_ept0_rx_handler,
|
||||
class_in_handler,
|
||||
class_out_handler,
|
||||
class_sof_handler,
|
||||
class_event_handler,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief initialize usb custom hid endpoint
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
usb_sts_type class_init_handler(void *udev)
|
||||
{
|
||||
usb_sts_type status = USB_OK;
|
||||
usbd_core_type *pudev = (usbd_core_type *)udev;
|
||||
|
||||
/* open in endpoint */
|
||||
usbd_ept_open(pudev, USBD_CDC_INT_EPT, EPT_INT_TYPE, USBD_CMD_MAXPACKET_SIZE);
|
||||
|
||||
/* open in endpoint */
|
||||
usbd_ept_open(pudev, USBD_CDC_BULK_IN_EPT, EPT_BULK_TYPE, USBD_IN_MAXPACKET_SIZE);
|
||||
|
||||
/* open out endpoint */
|
||||
usbd_ept_open(pudev, USBD_CDC_BULK_OUT_EPT, EPT_BULK_TYPE, USBD_OUT_MAXPACKET_SIZE);
|
||||
|
||||
/* set out endpoint to receive status */
|
||||
usbd_ept_recv(pudev, USBD_CDC_BULK_OUT_EPT, g_rx_buff, USBD_OUT_MAXPACKET_SIZE);
|
||||
|
||||
g_tx_completed = 1;
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear endpoint or other state
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
usb_sts_type class_clear_handler(void *udev)
|
||||
{
|
||||
usb_sts_type status = USB_OK;
|
||||
usbd_core_type *pudev = (usbd_core_type *)udev;
|
||||
|
||||
/* close in endpoint */
|
||||
usbd_ept_close(pudev, USBD_CDC_INT_EPT);
|
||||
|
||||
/* close in endpoint */
|
||||
usbd_ept_close(pudev, USBD_CDC_BULK_IN_EPT);
|
||||
|
||||
/* close out endpoint */
|
||||
usbd_ept_close(pudev, USBD_CDC_BULK_OUT_EPT);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device class setup request handler
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param setup: setup packet
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
usb_sts_type class_setup_handler(void *udev, usb_setup_type *setup)
|
||||
{
|
||||
usb_sts_type status = USB_OK;
|
||||
usbd_core_type *pudev = (usbd_core_type *)udev;
|
||||
|
||||
switch(setup->bmRequestType & USB_REQ_TYPE_RESERVED)
|
||||
{
|
||||
/* class request */
|
||||
case USB_REQ_TYPE_CLASS:
|
||||
if(setup->wLength)
|
||||
{
|
||||
if(setup->bmRequestType & USB_REQ_DIR_DTH)
|
||||
{
|
||||
usb_vcp_cmd_process(udev, setup->bRequest, g_cmd, setup->wLength);
|
||||
usbd_ctrl_send(pudev, g_cmd, setup->wLength);
|
||||
}
|
||||
else
|
||||
{
|
||||
g_req = setup->bRequest;
|
||||
g_len = setup->wLength;
|
||||
usbd_ctrl_recv(pudev, g_cmd, g_len);
|
||||
|
||||
}
|
||||
}
|
||||
break;
|
||||
/* standard request */
|
||||
case USB_REQ_TYPE_STANDARD:
|
||||
switch(setup->bRequest)
|
||||
{
|
||||
case USB_STD_REQ_GET_DESCRIPTOR:
|
||||
usbd_ctrl_unsupport(pudev);
|
||||
break;
|
||||
case USB_STD_REQ_GET_INTERFACE:
|
||||
usbd_ctrl_send(pudev, (uint8_t *)&alt_setting, 1);
|
||||
break;
|
||||
case USB_STD_REQ_SET_INTERFACE:
|
||||
alt_setting = setup->wValue;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
usbd_ctrl_unsupport(pudev);
|
||||
break;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device endpoint 0 in status stage complete
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
usb_sts_type class_ept0_tx_handler(void *udev)
|
||||
{
|
||||
usb_sts_type status = USB_OK;
|
||||
|
||||
/* ...user code... */
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device endpoint 0 out status stage complete
|
||||
* @param udev: usb device core handler type
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
usb_sts_type class_ept0_rx_handler(void *udev)
|
||||
{
|
||||
usb_sts_type status = USB_OK;
|
||||
usbd_core_type *pudev = (usbd_core_type *)udev;
|
||||
uint32_t recv_len = usbd_get_recv_len(pudev, 0);
|
||||
/* ...user code... */
|
||||
if( g_req == SET_LINE_CODING)
|
||||
{
|
||||
/* class process */
|
||||
usb_vcp_cmd_process(udev, g_req, g_cmd, recv_len);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device transmision complete handler
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param ept_num: endpoint number
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
usb_sts_type class_in_handler(void *udev, uint8_t ept_num)
|
||||
{
|
||||
usbd_core_type *pudev = (usbd_core_type *)udev;
|
||||
usb_sts_type status = USB_OK;
|
||||
|
||||
/* ...user code...
|
||||
trans next packet data
|
||||
*/
|
||||
usbd_flush_tx_fifo(pudev, ept_num);
|
||||
g_tx_completed = 1;
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device endpoint receive data
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param ept_num: endpoint number
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
usb_sts_type class_out_handler(void *udev, uint8_t ept_num)
|
||||
{
|
||||
usb_sts_type status = USB_OK;
|
||||
usbd_core_type *pudev = (usbd_core_type *)udev;
|
||||
|
||||
/* get endpoint receive data length */
|
||||
g_rxlen = usbd_get_recv_len(pudev, ept_num);
|
||||
|
||||
/*set recv flag*/
|
||||
g_rx_completed = 1;
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device sof handler
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
usb_sts_type class_sof_handler(void *udev)
|
||||
{
|
||||
usb_sts_type status = USB_OK;
|
||||
|
||||
/* ...user code... */
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device event handler
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param event: usb device event
|
||||
* @retval status of usb_sts_type
|
||||
*/
|
||||
usb_sts_type class_event_handler(void *udev, usbd_event_type event)
|
||||
{
|
||||
usb_sts_type status = USB_OK;
|
||||
switch(event)
|
||||
{
|
||||
case USBD_RESET_EVENT:
|
||||
|
||||
/* ...user code... */
|
||||
|
||||
break;
|
||||
case USBD_SUSPEND_EVENT:
|
||||
|
||||
/* ...user code... */
|
||||
|
||||
break;
|
||||
case USBD_WAKEUP_EVENT:
|
||||
/* ...user code... */
|
||||
|
||||
break;
|
||||
case USBD_INISOINCOM_EVENT:
|
||||
break;
|
||||
case USBD_OUTISOINCOM_EVENT:
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device class rx data process
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param recv_data: receive buffer
|
||||
* @retval receive data len
|
||||
*/
|
||||
uint16_t usb_vcp_get_rxdata(void *udev, uint8_t *recv_data)
|
||||
{
|
||||
uint16_t i_index = 0;
|
||||
uint16_t tmp_len = g_rxlen;
|
||||
usbd_core_type *pudev = (usbd_core_type *)udev;
|
||||
|
||||
if(g_rx_completed == 0)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
g_rx_completed = 0;
|
||||
tmp_len = g_rxlen;
|
||||
for(i_index = 0; i_index < g_rxlen; i_index ++)
|
||||
{
|
||||
recv_data[i_index] = g_rx_buff[i_index];
|
||||
}
|
||||
|
||||
usbd_ept_recv(pudev, USBD_CDC_BULK_OUT_EPT, g_rx_buff, USBD_OUT_MAXPACKET_SIZE);
|
||||
|
||||
return tmp_len;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb device class send data
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param send_data: send data buffer
|
||||
* @param len: send length
|
||||
* @retval error status
|
||||
*/
|
||||
error_status usb_vcp_send_data(void *udev, uint8_t *send_data, uint16_t len)
|
||||
{
|
||||
error_status status = SUCCESS;
|
||||
usbd_core_type *pudev = (usbd_core_type *)udev;
|
||||
if(g_tx_completed)
|
||||
{
|
||||
g_tx_completed = 0;
|
||||
usbd_ept_send(pudev, USBD_CDC_BULK_IN_EPT, send_data, len);
|
||||
}
|
||||
else
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief usb device function
|
||||
* @param udev: to the structure of usbd_core_type
|
||||
* @param cmd: request number
|
||||
* @param buff: request buffer
|
||||
* @param len: buffer length
|
||||
* @retval none
|
||||
*/
|
||||
void usb_vcp_cmd_process(void *udev, uint8_t cmd, uint8_t *buff, uint16_t len)
|
||||
{
|
||||
switch(cmd)
|
||||
{
|
||||
case SET_LINE_CODING:
|
||||
linecoding.bitrate = (uint32_t)(buff[0] | (buff[1] << 8) | (buff[2] << 16) | (buff[3] <<24));
|
||||
linecoding.format = buff[4];
|
||||
linecoding.parity = buff[5];
|
||||
linecoding.data = buff[6];
|
||||
break;
|
||||
|
||||
case GET_LINE_CODING:
|
||||
buff[0] = (uint8_t)linecoding.bitrate;
|
||||
buff[1] = (uint8_t)(linecoding.bitrate >> 8);
|
||||
buff[2] = (uint8_t)(linecoding.bitrate >> 16);
|
||||
buff[3] = (uint8_t)(linecoding.bitrate >> 24);
|
||||
buff[4] = (uint8_t)(linecoding.format);
|
||||
buff[5] = (uint8_t)(linecoding.parity);
|
||||
buff[6] = (uint8_t)(linecoding.data);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -0,0 +1,119 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file cdc_class.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief usb cdc class file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __CDC_CLASS_H
|
||||
#define __CDC_CLASS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "usb_std.h"
|
||||
#include "usbd_core.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_middlewares_usbd_class
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USB_cdc_class
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_cdc_class_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief usb cdc use endpoint define
|
||||
*/
|
||||
#define USBD_CDC_INT_EPT 0x82
|
||||
#define USBD_CDC_BULK_IN_EPT 0x81
|
||||
#define USBD_CDC_BULK_OUT_EPT 0x01
|
||||
|
||||
/**
|
||||
* @brief usb cdc in and out max packet size define
|
||||
*/
|
||||
#define USBD_IN_MAXPACKET_SIZE 0x40
|
||||
#define USBD_OUT_MAXPACKET_SIZE 0x40
|
||||
#define USBD_CMD_MAXPACKET_SIZE 0x08
|
||||
|
||||
/**
|
||||
* @brief usb cdc class request code define
|
||||
*/
|
||||
#define SET_LINE_CODING 0x20
|
||||
#define GET_LINE_CODING 0x21
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_cdc_class_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief usb cdc class set line coding struct
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t bitrate; /* line coding baud rate */
|
||||
uint8_t format; /* line coding foramt */
|
||||
uint8_t parity; /* line coding parity */
|
||||
uint8_t data; /* line coding data bit */
|
||||
}linecoding_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_cdc_class_exported_functions
|
||||
* @{
|
||||
*/
|
||||
extern usbd_class_handler class_handler;
|
||||
uint16_t usb_vcp_get_rxdata(void *udev, uint8_t *recv_data);
|
||||
error_status usb_vcp_send_data(void *udev, uint8_t *send_data, uint16_t len);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,446 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file cdc_desc.c
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief usb cdc device descriptor
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
#include "stdio.h"
|
||||
#include "usb_std.h"
|
||||
#include "usbd_sdr.h"
|
||||
#include "usbd_core.h"
|
||||
#include "cdc_desc.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_middlewares_usbd_class
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_cdc_desc
|
||||
* @brief usb device cdc descriptor
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_cdc_desc_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
usbd_desc_t *get_device_descriptor(void);
|
||||
usbd_desc_t *get_device_qualifier(void);
|
||||
usbd_desc_t *get_device_configuration(void);
|
||||
usbd_desc_t *get_device_other_speed(void);
|
||||
usbd_desc_t *get_device_lang_id(void);
|
||||
usbd_desc_t *get_device_manufacturer_string(void);
|
||||
usbd_desc_t *get_device_product_string(void);
|
||||
usbd_desc_t *get_device_serial_string(void);
|
||||
usbd_desc_t *get_device_interface_string(void);
|
||||
usbd_desc_t *get_device_config_string(void);
|
||||
|
||||
uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf);
|
||||
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len);
|
||||
static void get_serial_num(void);
|
||||
static uint8_t g_usbd_desc_buffer[256];
|
||||
|
||||
/**
|
||||
* @brief device descriptor handler structure
|
||||
*/
|
||||
usbd_desc_handler desc_handler =
|
||||
{
|
||||
get_device_descriptor,
|
||||
get_device_qualifier,
|
||||
get_device_configuration,
|
||||
get_device_other_speed,
|
||||
get_device_lang_id,
|
||||
get_device_manufacturer_string,
|
||||
get_device_product_string,
|
||||
get_device_serial_string,
|
||||
get_device_interface_string,
|
||||
get_device_config_string,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usb device standard descriptor
|
||||
*/
|
||||
#if defined ( __ICCARM__ ) /* iar compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
ALIGNED_HEAD uint8_t g_usbd_descriptor[USB_DEVICE_DESC_LEN] ALIGNED_TAIL =
|
||||
{
|
||||
USB_DEVICE_DESC_LEN, /* bLength */
|
||||
USB_DESCIPTOR_TYPE_DEVICE, /* bDescriptorType */
|
||||
0x00, /* bcdUSB */
|
||||
0x02,
|
||||
0x02, /* bDeviceClass */
|
||||
0x00, /* bDeviceSubClass */
|
||||
0x00, /* bDeviceProtocol */
|
||||
USB_MAX_EP0_SIZE, /* bMaxPacketSize */
|
||||
LBYTE(USBD_VENDOR_ID), /* idVendor */
|
||||
HBYTE(USBD_VENDOR_ID), /* idVendor */
|
||||
LBYTE(USBD_PRODUCT_ID), /* idProduct */
|
||||
HBYTE(USBD_PRODUCT_ID), /* idProduct */
|
||||
0x00, /* bcdDevice rel. 2.00 */
|
||||
0x02,
|
||||
USB_MFC_STRING, /* Index of manufacturer string */
|
||||
USB_PRODUCT_STRING, /* Index of product string */
|
||||
USB_SERIAL_STRING, /* Index of serial number string */
|
||||
1 /* bNumConfigurations */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usb configuration standard descriptor
|
||||
*/
|
||||
#if defined ( __ICCARM__ ) /* iar compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
ALIGNED_HEAD uint8_t g_usbd_configuration[USBD_CONFIG_DESC_SIZE] ALIGNED_TAIL =
|
||||
{
|
||||
USB_DEVICE_CFG_DESC_LEN, /* bLength: configuration descriptor size */
|
||||
USB_DESCIPTOR_TYPE_CONFIGURATION, /* bDescriptorType: configuration */
|
||||
LBYTE(USBD_CONFIG_DESC_SIZE), /* wTotalLength: bytes returned */
|
||||
HBYTE(USBD_CONFIG_DESC_SIZE), /* wTotalLength: bytes returned */
|
||||
0x02, /* bNumInterfaces: 2 interface */
|
||||
0x01, /* bConfigurationValue: configuration value */
|
||||
0x00, /* iConfiguration: index of string descriptor describing
|
||||
the configuration */
|
||||
0xC0, /* bmAttributes: self powered */
|
||||
0x32, /* MaxPower 100 mA: this current is used for detecting vbus */
|
||||
|
||||
USB_DEVICE_IF_DESC_LEN, /* bLength: interface descriptor size */
|
||||
USB_DESCIPTOR_TYPE_INTERFACE, /* bDescriptorType: interface descriptor type */
|
||||
0x00, /* bInterfaceNumber: number of interface */
|
||||
0x00, /* bAlternateSetting: alternate set */
|
||||
0x01, /* bNumEndpoints: number of endpoints */
|
||||
USB_CLASS_CODE_CDC, /* bInterfaceClass: CDC class code */
|
||||
0x02, /* bInterfaceSubClass: subclass code, Abstract Control Model*/
|
||||
0x01, /* bInterfaceProtocol: protocol code, AT Command */
|
||||
0x00, /* iInterface: index of string descriptor */
|
||||
|
||||
0x05, /* bFunctionLength: size of this descriptor in bytes */
|
||||
USBD_CDC_CS_INTERFACE, /* bDescriptorType: CDC interface descriptor type */
|
||||
USBD_CDC_SUBTYPE_HEADER, /* bDescriptorSubtype: Header function Descriptor 0x00*/
|
||||
LBYTE(BCD_NUM),
|
||||
HBYTE(BCD_NUM), /* bcdCDC: USB class definitions for communications */
|
||||
|
||||
0x05, /* bFunctionLength: size of this descriptor in bytes */
|
||||
USBD_CDC_CS_INTERFACE, /* bDescriptorType: CDC interface descriptor type */
|
||||
USBD_CDC_SUBTYPE_CMF, /* bDescriptorSubtype: Call Management function descriptor subtype 0x01 */
|
||||
0x00, /* bmCapabilities: 0x00*/
|
||||
0x01, /* bDataInterface: interface number of data class interface optionally used for call management */
|
||||
|
||||
0x04, /* bFunctionLength: size of this descriptor in bytes */
|
||||
USBD_CDC_CS_INTERFACE, /* bDescriptorType: CDC interface descriptor type */
|
||||
USBD_CDC_SUBTYPE_ACM, /* bDescriptorSubtype: Abstract Control Management functional descriptor subtype 0x02 */
|
||||
0x02, /* bmCapabilities: Support Set_Line_Coding and Get_Line_Coding 0x02 */
|
||||
|
||||
0x05, /* bFunctionLength: size of this descriptor in bytes */
|
||||
USBD_CDC_CS_INTERFACE, /* bDescriptorType: CDC interface descriptor type */
|
||||
USBD_CDC_SUBTYPE_UFD, /* bDescriptorSubtype: Union Function Descriptor subtype 0x06 */
|
||||
0x00, /* bControlInterface: The interface number of the communications or data class interface 0x00 */
|
||||
0x01, /* bSubordinateInterface0: interface number of first subordinate interface in the union */
|
||||
|
||||
USB_DEVICE_EPT_LEN, /* bLength: size of endpoint descriptor in bytes */
|
||||
USB_DESCIPTOR_TYPE_ENDPOINT, /* bDescriptorType: endpoint descriptor type */
|
||||
USBD_CDC_INT_EPT, /* bEndpointAddress: the address of endpoint on usb device described by this descriptor */
|
||||
USB_EPT_DESC_INTERRUPT, /* bmAttributes: endpoint attributes */
|
||||
LBYTE(USBD_CMD_MAXPACKET_SIZE),
|
||||
HBYTE(USBD_CMD_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
|
||||
HID_BINTERVAL_TIME, /* bInterval: interval for polling endpoint for data transfers */
|
||||
|
||||
|
||||
USB_DEVICE_IF_DESC_LEN, /* bLength: interface descriptor size */
|
||||
USB_DESCIPTOR_TYPE_INTERFACE, /* bDescriptorType: interface descriptor type */
|
||||
0x01, /* bInterfaceNumber: number of interface */
|
||||
0x00, /* bAlternateSetting: alternate set */
|
||||
0x02, /* bNumEndpoints: number of endpoints */
|
||||
USB_CLASS_CODE_CDCDATA, /* bInterfaceClass: CDC-data class code */
|
||||
0x00, /* bInterfaceSubClass: Data interface subclass code 0x00*/
|
||||
0x00, /* bInterfaceProtocol: data class protocol code 0x00 */
|
||||
0x00, /* iInterface: index of string descriptor */
|
||||
|
||||
USB_DEVICE_EPT_LEN, /* bLength: size of endpoint descriptor in bytes */
|
||||
USB_DESCIPTOR_TYPE_ENDPOINT, /* bDescriptorType: endpoint descriptor type */
|
||||
USBD_CDC_BULK_IN_EPT, /* bEndpointAddress: the address of endpoint on usb device described by this descriptor */
|
||||
USB_EPT_DESC_BULK, /* bmAttributes: endpoint attributes */
|
||||
LBYTE(USBD_IN_MAXPACKET_SIZE),
|
||||
HBYTE(USBD_IN_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
|
||||
0x00, /* bInterval: interval for polling endpoint for data transfers */
|
||||
|
||||
USB_DEVICE_EPT_LEN, /* bLength: size of endpoint descriptor in bytes */
|
||||
USB_DESCIPTOR_TYPE_ENDPOINT, /* bDescriptorType: endpoint descriptor type */
|
||||
USBD_CDC_BULK_OUT_EPT, /* bEndpointAddress: the address of endpoint on usb device described by this descriptor */
|
||||
USB_EPT_DESC_BULK, /* bmAttributes: endpoint attributes */
|
||||
LBYTE(USBD_OUT_MAXPACKET_SIZE),
|
||||
HBYTE(USBD_OUT_MAXPACKET_SIZE), /* wMaxPacketSize: maximum packe size this endpoint */
|
||||
0x00, /* bInterval: interval for polling endpoint for data transfers */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usb string lang id
|
||||
*/
|
||||
#if defined ( __ICCARM__ ) /* iar compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
ALIGNED_HEAD uint8_t g_string_lang_id[USBD_SIZ_STRING_LANGID] ALIGNED_TAIL =
|
||||
{
|
||||
USBD_SIZ_STRING_LANGID,
|
||||
USB_DESCIPTOR_TYPE_STRING,
|
||||
0x09,
|
||||
0x04,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usb string serial
|
||||
*/
|
||||
#if defined ( __ICCARM__ ) /* iar compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
ALIGNED_HEAD uint8_t g_string_serial[USBD_SIZ_STRING_SERIAL] ALIGNED_TAIL =
|
||||
{
|
||||
USBD_SIZ_STRING_SERIAL,
|
||||
USB_DESCIPTOR_TYPE_STRING,
|
||||
};
|
||||
|
||||
|
||||
/* device descriptor */
|
||||
usbd_desc_t device_descriptor =
|
||||
{
|
||||
USB_DEVICE_DESC_LEN,
|
||||
g_usbd_descriptor
|
||||
};
|
||||
|
||||
/* config descriptor */
|
||||
usbd_desc_t config_descriptor =
|
||||
{
|
||||
USBD_CONFIG_DESC_SIZE,
|
||||
g_usbd_configuration
|
||||
};
|
||||
|
||||
/* langid descriptor */
|
||||
usbd_desc_t langid_descriptor =
|
||||
{
|
||||
USBD_SIZ_STRING_LANGID,
|
||||
g_string_lang_id
|
||||
};
|
||||
|
||||
/* serial descriptor */
|
||||
usbd_desc_t serial_descriptor =
|
||||
{
|
||||
USBD_SIZ_STRING_SERIAL,
|
||||
g_string_serial
|
||||
};
|
||||
|
||||
usbd_desc_t vp_desc;
|
||||
|
||||
/**
|
||||
* @brief standard usb unicode convert
|
||||
* @param string: source string
|
||||
* @param unicode_buf: unicode buffer
|
||||
* @retval length
|
||||
*/
|
||||
uint16_t usbd_unicode_convert(uint8_t *string, uint8_t *unicode_buf)
|
||||
{
|
||||
uint16_t str_len = 0, id_pos = 2;
|
||||
uint8_t *tmp_str = string;
|
||||
|
||||
while(*tmp_str != '\0')
|
||||
{
|
||||
str_len ++;
|
||||
unicode_buf[id_pos ++] = *tmp_str ++;
|
||||
unicode_buf[id_pos ++] = 0x00;
|
||||
}
|
||||
|
||||
str_len = str_len * 2 + 2;
|
||||
unicode_buf[0] = (uint8_t)str_len;
|
||||
unicode_buf[1] = USB_DESCIPTOR_TYPE_STRING;
|
||||
|
||||
return str_len;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb int convert to unicode
|
||||
* @param value: int value
|
||||
* @param pbus: unicode buffer
|
||||
* @param len: length
|
||||
* @retval none
|
||||
*/
|
||||
static void usbd_int_to_unicode (uint32_t value , uint8_t *pbuf , uint8_t len)
|
||||
{
|
||||
uint8_t idx = 0;
|
||||
|
||||
for( idx = 0 ; idx < len ; idx ++)
|
||||
{
|
||||
if( ((value >> 28)) < 0xA )
|
||||
{
|
||||
pbuf[ 2 * idx] = (value >> 28) + '0';
|
||||
}
|
||||
else
|
||||
{
|
||||
pbuf[2 * idx] = (value >> 28) + 'A' - 10;
|
||||
}
|
||||
|
||||
value = value << 4;
|
||||
|
||||
pbuf[2 * idx + 1] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb get serial number
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
static void get_serial_num(void)
|
||||
{
|
||||
uint32_t serial0, serial1, serial2;
|
||||
|
||||
serial0 = *(uint32_t*)MCU_ID1;
|
||||
serial1 = *(uint32_t*)MCU_ID2;
|
||||
serial2 = *(uint32_t*)MCU_ID3;
|
||||
|
||||
serial0 += serial2;
|
||||
|
||||
if (serial0 != 0)
|
||||
{
|
||||
usbd_int_to_unicode (serial0, &g_string_serial[2] ,8);
|
||||
usbd_int_to_unicode (serial1, &g_string_serial[18] ,4);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get device descriptor
|
||||
* @param none
|
||||
* @retval usbd_desc
|
||||
*/
|
||||
usbd_desc_t *get_device_descriptor(void)
|
||||
{
|
||||
return &device_descriptor;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get device qualifier
|
||||
* @param none
|
||||
* @retval usbd_desc
|
||||
*/
|
||||
usbd_desc_t * get_device_qualifier(void)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get config descriptor
|
||||
* @param none
|
||||
* @retval usbd_desc
|
||||
*/
|
||||
usbd_desc_t *get_device_configuration(void)
|
||||
{
|
||||
return &config_descriptor;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get other speed descriptor
|
||||
* @param none
|
||||
* @retval usbd_desc
|
||||
*/
|
||||
usbd_desc_t *get_device_other_speed(void)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get lang id descriptor
|
||||
* @param none
|
||||
* @retval usbd_desc
|
||||
*/
|
||||
usbd_desc_t *get_device_lang_id(void)
|
||||
{
|
||||
return &langid_descriptor;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief get manufacturer descriptor
|
||||
* @param none
|
||||
* @retval usbd_desc
|
||||
*/
|
||||
usbd_desc_t *get_device_manufacturer_string(void)
|
||||
{
|
||||
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_DESC_MANUFACTURER_STRING, g_usbd_desc_buffer);
|
||||
vp_desc.descriptor = g_usbd_desc_buffer;
|
||||
return &vp_desc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get product descriptor
|
||||
* @param none
|
||||
* @retval usbd_desc
|
||||
*/
|
||||
usbd_desc_t *get_device_product_string(void)
|
||||
{
|
||||
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_DESC_PRODUCT_STRING, g_usbd_desc_buffer);
|
||||
vp_desc.descriptor = g_usbd_desc_buffer;
|
||||
return &vp_desc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get serial descriptor
|
||||
* @param none
|
||||
* @retval usbd_desc
|
||||
*/
|
||||
usbd_desc_t *get_device_serial_string(void)
|
||||
{
|
||||
get_serial_num();
|
||||
return &serial_descriptor;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get interface descriptor
|
||||
* @param none
|
||||
* @retval usbd_desc
|
||||
*/
|
||||
usbd_desc_t *get_device_interface_string(void)
|
||||
{
|
||||
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_DESC_INTERFACE_STRING, g_usbd_desc_buffer);
|
||||
vp_desc.descriptor = g_usbd_desc_buffer;
|
||||
return &vp_desc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get device config descriptor
|
||||
* @param none
|
||||
* @retval usbd_desc
|
||||
*/
|
||||
usbd_desc_t *get_device_config_string(void)
|
||||
{
|
||||
vp_desc.length = usbd_unicode_convert((uint8_t *)USBD_DESC_CONFIGURATION_STRING, g_usbd_desc_buffer);
|
||||
vp_desc.descriptor = g_usbd_desc_buffer;
|
||||
return &vp_desc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -0,0 +1,122 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file cdc_desc.h
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief usb cdc descriptor header file
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __CDC_DESC_H
|
||||
#define __CDC_DESC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "cdc_class.h"
|
||||
#include "usbd_core.h"
|
||||
|
||||
/** @addtogroup AT32F435_437_middlewares_usbd_class
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USB_cdc_desc
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_cdc_desc_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief usb bcd number define
|
||||
*/
|
||||
#define BCD_NUM 0x0110
|
||||
|
||||
/**
|
||||
* @brief usb vendor id and product id define
|
||||
*/
|
||||
#define USBD_VENDOR_ID 0x2E3C
|
||||
#define USBD_PRODUCT_ID 0x5740
|
||||
|
||||
/**
|
||||
* @brief usb descriptor size define
|
||||
*/
|
||||
#define USBD_CONFIG_DESC_SIZE 67
|
||||
#define USBD_SIZ_STRING_LANGID 4
|
||||
#define USBD_SIZ_STRING_SERIAL 0x1A
|
||||
|
||||
/**
|
||||
* @brief usb string define(vendor, product configuration, interface)
|
||||
*/
|
||||
#define USBD_DESC_MANUFACTURER_STRING "Artery"
|
||||
#define USBD_DESC_PRODUCT_STRING "AT32 Virtual Com Port "
|
||||
#define USBD_DESC_CONFIGURATION_STRING "Virtual ComPort Config"
|
||||
#define USBD_DESC_INTERFACE_STRING "Virtual ComPort Interface"
|
||||
|
||||
/**
|
||||
* @brief usb endpoint interval define
|
||||
*/
|
||||
#define HID_BINTERVAL_TIME 0xFF
|
||||
|
||||
/**
|
||||
* @brief usb hid class descriptor define
|
||||
*/
|
||||
#define USBD_CDC_CS_INTERFACE 0x24
|
||||
#define USBD_CDC_CS_ENDPOINT 0x25
|
||||
|
||||
/**
|
||||
* @brief usb hid class sub-type define
|
||||
*/
|
||||
#define USBD_CDC_SUBTYPE_HEADER 0x00
|
||||
#define USBD_CDC_SUBTYPE_CMF 0x01
|
||||
#define USBD_CDC_SUBTYPE_ACM 0x02
|
||||
#define USBD_CDC_SUBTYPE_UFD 0x06
|
||||
|
||||
/**
|
||||
* @brief usb mcu id address deine
|
||||
*/
|
||||
#define MCU_ID1 (0x1FFFF7E8)
|
||||
#define MCU_ID2 (0x1FFFF7EC)
|
||||
#define MCU_ID3 (0x1FFFF7F0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
extern uint8_t g_usbd_descriptor[USB_DEVICE_DESC_LEN];
|
||||
extern uint8_t g_usbd_configuration[USBD_CONFIG_DESC_SIZE];
|
||||
extern usbd_desc_handler desc_handler;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,36 @@
|
||||
; PlatformIO Project Configuration File
|
||||
;
|
||||
; Build options: build flags, source filter, extra scripting
|
||||
; Upload options: custom port, speed and extra flags
|
||||
; Library options: dependencies, extra library storages
|
||||
;
|
||||
; Please visit documentation for the other options and examples
|
||||
; http://docs.platformio.org/page/projectconf.html
|
||||
|
||||
[env:vcp_loopback]
|
||||
platform = at32
|
||||
framework = cmsis
|
||||
board = generic_f435
|
||||
build_flags = -I include
|
||||
monitor_speed = 115200 ;serial monitor baudrate
|
||||
|
||||
;Use the following for jlink upload
|
||||
upload_protocol = jlink
|
||||
|
||||
;Use the following for serial upload via bootloader (PA9, PA10)
|
||||
;upload_protocol = serial
|
||||
;upload_speed = 115200 ;default: 115200
|
||||
|
||||
;Use the following for DFU upload via USB port
|
||||
;upload_protocol = dfu
|
||||
;build_flags =
|
||||
; -DDFU_MODE
|
||||
; -UVECT_TAB_OFFSET
|
||||
; -DUSER_VECT_TAB_ADDRESS
|
||||
; -DVECT_TAB_OFFSET=0x2000 ; override default vector tale to support ISR table for DFU mode
|
||||
|
||||
;Use the following for custom uploader
|
||||
;upload_protocol = custom
|
||||
;upload_port = COM16
|
||||
;upload_speed = 115200
|
||||
;upload_command = ${platformio.packages_dir}/framework-cmsis-at32f40/tools/stm32flash/stm32flash -b $UPLOAD_SPEED -w $SOURCE -g 0x8000000 $UPLOAD_PORT
|
||||
@@ -0,0 +1,11 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file readme.txt
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief readme
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
this demo is based on the at-start board, in this demo, show how to build
|
||||
a device of usb cdc class protocol.
|
||||
@@ -0,0 +1,106 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_clock.c
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief system clock config program
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437_clock.h"
|
||||
|
||||
/**
|
||||
* @brief system clock config program
|
||||
* @note the system clock is configured as follow:
|
||||
* - system clock = (hext * pll_ns)/(pll_ms * pll_fr)
|
||||
* - system clock source = pll (hext)
|
||||
* - hext = 8000000
|
||||
* - sclk = 288000000
|
||||
* - ahbdiv = 1
|
||||
* - ahbclk = 288000000
|
||||
* - apb2div = 2
|
||||
* - apb2clk = 144000000
|
||||
* - apb1div = 2
|
||||
* - apb1clk = 144000000
|
||||
* - pll_ns = 72
|
||||
* - pll_ms = 1
|
||||
* - pll_fr = 2
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void system_clock_config(void)
|
||||
{
|
||||
/* enable pwc periph clock */
|
||||
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
|
||||
|
||||
/* config ldo voltage */
|
||||
pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3);
|
||||
|
||||
/* set the flash clock divider */
|
||||
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
|
||||
|
||||
/* reset crm */
|
||||
crm_reset();
|
||||
|
||||
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
|
||||
|
||||
/* wait till hext is ready */
|
||||
while(crm_hext_stable_wait() == ERROR)
|
||||
{
|
||||
}
|
||||
|
||||
/* config pll clock resource */
|
||||
crm_pll_config(CRM_PLL_SOURCE_HEXT, 72, 1, CRM_PLL_FR_2);
|
||||
|
||||
/* enable pll */
|
||||
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
|
||||
|
||||
/* wait till pll is ready */
|
||||
while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
|
||||
{
|
||||
}
|
||||
|
||||
/* config ahbclk */
|
||||
crm_ahb_div_set(CRM_AHB_DIV_1);
|
||||
|
||||
/* config apb2clk */
|
||||
crm_apb2_div_set(CRM_APB2_DIV_2);
|
||||
|
||||
/* config apb1clk */
|
||||
crm_apb1_div_set(CRM_APB1_DIV_2);
|
||||
|
||||
/* enable auto step mode */
|
||||
crm_auto_step_mode_enable(TRUE);
|
||||
|
||||
/* select pll as system clock source */
|
||||
crm_sysclk_switch(CRM_SCLK_PLL);
|
||||
|
||||
/* wait till pll is used as system clock source */
|
||||
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
|
||||
{
|
||||
}
|
||||
|
||||
/* disable auto step mode */
|
||||
crm_auto_step_mode_enable(FALSE);
|
||||
|
||||
/* update system_core_clock global variable */
|
||||
system_core_clock_update();
|
||||
}
|
||||
@@ -0,0 +1,142 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file at32f435_437_int.c
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief main interrupt service routines.
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f435_437_int.h"
|
||||
|
||||
/** @addtogroup AT32F435_periph_examples
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup 435_USB_device_vcp_loopback
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief this function handles nmi exception.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles hard fault exception.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
/* go to infinite loop when hard fault exception occurs */
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles memory manage exception.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void MemManage_Handler(void)
|
||||
{
|
||||
/* go to infinite loop when memory manage exception occurs */
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles bus fault exception.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void BusFault_Handler(void)
|
||||
{
|
||||
/* go to infinite loop when bus fault exception occurs */
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles usage fault exception.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void UsageFault_Handler(void)
|
||||
{
|
||||
/* go to infinite loop when usage fault exception occurs */
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles svcall exception.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void SVC_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles debug monitor exception.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void DebugMon_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles pendsv_handler exception.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void PendSV_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles systick handler.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -0,0 +1,326 @@
|
||||
/**
|
||||
**************************************************************************
|
||||
* @file main.c
|
||||
* @version v2.0.4
|
||||
* @date 2021-12-31
|
||||
* @brief main program
|
||||
**************************************************************************
|
||||
* Copyright notice & Disclaimer
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#include "at32f435_437_board.h"
|
||||
#include "at32f435_437_clock.h"
|
||||
#include "usb_conf.h"
|
||||
#include "usb_core.h"
|
||||
#include "usbd_int.h"
|
||||
#include "cdc_class.h"
|
||||
#include "cdc_desc.h"
|
||||
|
||||
/** @addtogroup AT32F435_periph_examples
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup 435_USB_device_vcp_loopback USB_device_vcp_loopback
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* usb global struct define */
|
||||
otg_core_type otg_core_struct;
|
||||
uint8_t usb_buffer[256];
|
||||
void usb_clock48m_select(usb_clk48_s clk_s);
|
||||
void usb_gpio_config(void);
|
||||
void usb_low_power_wakeup_config(void);
|
||||
|
||||
/**
|
||||
* @brief main function.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
uint16_t data_len;
|
||||
|
||||
uint32_t timeout;
|
||||
|
||||
uint8_t send_zero_packet = 0;
|
||||
|
||||
nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
|
||||
|
||||
system_clock_config();
|
||||
|
||||
at32_board_init();
|
||||
|
||||
/* usb gpio config */
|
||||
usb_gpio_config();
|
||||
|
||||
#ifdef USB_LOW_POWER_WAKUP
|
||||
usb_low_power_wakeup_config();
|
||||
#endif
|
||||
|
||||
/* enable otgfs clock */
|
||||
crm_periph_clock_enable(OTG_CLOCK, TRUE);
|
||||
|
||||
/* select usb 48m clcok source */
|
||||
usb_clock48m_select(USB_CLK_HEXT);
|
||||
|
||||
/* enable otgfs irq */
|
||||
nvic_irq_enable(OTG_IRQ, 0, 0);
|
||||
|
||||
/* init usb */
|
||||
usbd_init(&otg_core_struct,
|
||||
USB_FULL_SPEED_CORE_ID,
|
||||
USB_ID,
|
||||
&class_handler,
|
||||
&desc_handler);
|
||||
while(1)
|
||||
{
|
||||
/* get usb vcp receive data */
|
||||
data_len = usb_vcp_get_rxdata(&otg_core_struct.dev, usb_buffer);
|
||||
|
||||
if(data_len > 0 || send_zero_packet == 1)
|
||||
{
|
||||
|
||||
/* bulk transfer is complete when the endpoint does one of the following
|
||||
1 has transferred exactly the amount of data expected
|
||||
2 transfers a packet with a payload size less than wMaxPacketSize or transfers a zero-length packet
|
||||
*/
|
||||
if(data_len > 0)
|
||||
send_zero_packet = 1;
|
||||
|
||||
if(data_len == 0)
|
||||
send_zero_packet = 0;
|
||||
|
||||
timeout = 50000;
|
||||
do
|
||||
{
|
||||
/* send data to host */
|
||||
if(usb_vcp_send_data(&otg_core_struct.dev, usb_buffer, data_len) == SUCCESS)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}while(timeout --);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb 48M clock select
|
||||
* @param clk_s:USB_CLK_HICK, USB_CLK_HEXT
|
||||
* @retval none
|
||||
*/
|
||||
void usb_clock48m_select(usb_clk48_s clk_s)
|
||||
{
|
||||
if(clk_s == USB_CLK_HICK)
|
||||
{
|
||||
crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK);
|
||||
|
||||
/* enable the acc calibration ready interrupt */
|
||||
crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE);
|
||||
|
||||
/* update the c1\c2\c3 value */
|
||||
acc_write_c1(7980);
|
||||
acc_write_c2(8000);
|
||||
acc_write_c3(8020);
|
||||
#if (USB_ID == 0)
|
||||
acc_sof_select(ACC_SOF_OTG1);
|
||||
#else
|
||||
acc_sof_select(ACC_SOF_OTG2);
|
||||
#endif
|
||||
/* open acc calibration */
|
||||
acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE);
|
||||
}
|
||||
else
|
||||
{
|
||||
switch(system_core_clock)
|
||||
{
|
||||
/* 48MHz */
|
||||
case 48000000:
|
||||
crm_usb_clock_div_set(CRM_USB_DIV_1);
|
||||
break;
|
||||
|
||||
/* 72MHz */
|
||||
case 72000000:
|
||||
crm_usb_clock_div_set(CRM_USB_DIV_1_5);
|
||||
break;
|
||||
|
||||
/* 96MHz */
|
||||
case 96000000:
|
||||
crm_usb_clock_div_set(CRM_USB_DIV_2);
|
||||
break;
|
||||
|
||||
/* 120MHz */
|
||||
case 120000000:
|
||||
crm_usb_clock_div_set(CRM_USB_DIV_2_5);
|
||||
break;
|
||||
|
||||
/* 144MHz */
|
||||
case 144000000:
|
||||
crm_usb_clock_div_set(CRM_USB_DIV_3);
|
||||
break;
|
||||
|
||||
/* 168MHz */
|
||||
case 168000000:
|
||||
crm_usb_clock_div_set(CRM_USB_DIV_3_5);
|
||||
break;
|
||||
|
||||
/* 192MHz */
|
||||
case 192000000:
|
||||
crm_usb_clock_div_set(CRM_USB_DIV_4);
|
||||
break;
|
||||
|
||||
/* 216MHz */
|
||||
case 216000000:
|
||||
crm_usb_clock_div_set(CRM_USB_DIV_4_5);
|
||||
break;
|
||||
|
||||
/* 240MHz */
|
||||
case 240000000:
|
||||
crm_usb_clock_div_set(CRM_USB_DIV_5);
|
||||
break;
|
||||
|
||||
/* 264MHz */
|
||||
case 264000000:
|
||||
crm_usb_clock_div_set(CRM_USB_DIV_5_5);
|
||||
break;
|
||||
|
||||
/* 288MHz */
|
||||
case 288000000:
|
||||
crm_usb_clock_div_set(CRM_USB_DIV_6);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function config gpio.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void usb_gpio_config(void)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
|
||||
crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE);
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
|
||||
/* dp and dm */
|
||||
gpio_init_struct.gpio_pins = OTG_PIN_DP | OTG_PIN_DM;
|
||||
gpio_init(OTG_PIN_GPIO, &gpio_init_struct);
|
||||
|
||||
gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_DP_SOURCE, OTG_PIN_MUX);
|
||||
gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_DM_SOURCE, OTG_PIN_MUX);
|
||||
|
||||
#ifdef USB_SOF_OUTPUT_ENABLE
|
||||
crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE);
|
||||
gpio_init_struct.gpio_pins = OTG_PIN_SOF;
|
||||
gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct);
|
||||
gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX);
|
||||
#endif
|
||||
|
||||
/* otgfs use vbus pin */
|
||||
#ifndef USB_VBUS_IGNORE
|
||||
gpio_init_struct.gpio_pins = OTG_PIN_VBUS;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_DOWN;
|
||||
gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX);
|
||||
gpio_init(OTG_PIN_GPIO, &gpio_init_struct);
|
||||
#endif
|
||||
|
||||
|
||||
}
|
||||
#ifdef USB_LOW_POWER_WAKUP
|
||||
/**
|
||||
* @brief usb low power wakeup interrupt config
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void usb_low_power_wakeup_config(void)
|
||||
{
|
||||
exint_init_type exint_init_struct;
|
||||
|
||||
crm_periph_clock_enable(CRM_SCFG_PERIPH_CLOCK, TRUE);
|
||||
exint_default_para_init(&exint_init_struct);
|
||||
|
||||
exint_init_struct.line_enable = TRUE;
|
||||
exint_init_struct.line_mode = EXINT_LINE_INTERRUPUT;
|
||||
exint_init_struct.line_select = OTG_WKUP_EXINT_LINE;
|
||||
exint_init_struct.line_polarity = EXINT_TRIGGER_RISING_EDGE;
|
||||
exint_init(&exint_init_struct);
|
||||
|
||||
nvic_irq_enable(OTG_WKUP_IRQ, 0, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief this function handles otgfs wakup interrupt.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void OTG_WKUP_HANDLER(void)
|
||||
{
|
||||
exint_flag_clear(OTG_WKUP_EXINT_LINE);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief this function handles otgfs interrupt.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void OTG_IRQ_HANDLER(void)
|
||||
{
|
||||
usbd_irq_handler(&otg_core_struct);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb delay millisecond function.
|
||||
* @param ms: number of millisecond delay
|
||||
* @retval none
|
||||
*/
|
||||
void usb_delay_ms(uint32_t ms)
|
||||
{
|
||||
/* user can define self delay function */
|
||||
delay_ms(ms);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usb delay microsecond function.
|
||||
* @param us: number of microsecond delay
|
||||
* @retval none
|
||||
*/
|
||||
void usb_delay_us(uint32_t us)
|
||||
{
|
||||
delay_us(us);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -20,7 +20,7 @@ void Delay_init()
|
||||
{
|
||||
/*Config Systick*/
|
||||
SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
|
||||
fac_us=(float)SystemCoreClock/(240 * 1000000);
|
||||
fac_us=(float)SystemCoreClock/(8 * 1000000);
|
||||
fac_ms=fac_us*1000;
|
||||
}
|
||||
|
||||
|
||||
@@ -3,11 +3,33 @@
|
||||
#include "at32f4xx.h"
|
||||
#include "delay.h"
|
||||
|
||||
#define LEDPORT (GPIOC)
|
||||
#define LED1 (13)
|
||||
#define ENABLE_GPIO_CLOCK (RCC->APB2EN |= RCC_APB2EN_GPIOCEN) //RCC_APB2ENR_IOPCEN)
|
||||
#define _MODER CTRLH
|
||||
#define GPIOMODER (GPIO_CTRLH_MDE13_0)
|
||||
|
||||
#define BLUEPILL // BLUEPILL BLACKPILL QFP48_FLASHER
|
||||
|
||||
#ifdef BLUEPILL
|
||||
#define LEDPORT (GPIOC)
|
||||
#define LED1 (13)
|
||||
#define ENABLE_GPIO_CLOCK (RCC->APB2EN |= RCC_APB2EN_GPIOCEN) //RCC_APB2ENR_IOPCEN)
|
||||
#define _MODER CTRLH
|
||||
#define GPIOMODER (GPIO_CTRLH_MDE13_0)
|
||||
#endif
|
||||
#ifdef BLACKPILL
|
||||
#define LEDPORT (GPIOB)
|
||||
#define LED1 (12)
|
||||
#define ENABLE_GPIO_CLOCK (RCC->APB2EN |= RCC_APB2EN_GPIOBEN) //RCC_APB2ENR_IOPCEN)
|
||||
#define _MODER CTRLH
|
||||
#define GPIOMODER (GPIO_CTRLH_MDE12_0)
|
||||
#endif
|
||||
#ifdef QFP48_FLASHER
|
||||
#define LEDPORT (GPIOB)
|
||||
#define LED1 (15)
|
||||
#define ENABLE_GPIO_CLOCK (RCC->APB2EN |= RCC_APB2EN_GPIOBEN) //RCC_APB2ENR_IOPCEN)
|
||||
#define _MODER CTRLH
|
||||
#define GPIOMODER (GPIO_CTRLH_MDE15_0)
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//Alternates blue and green LEDs quickly
|
||||
|
||||
@@ -118,8 +118,8 @@
|
||||
|
||||
#if defined (AT32F403Axx)|| defined (AT32F407xx)
|
||||
/* #define SYSCLK_FREQ_224MHz 224000000 */
|
||||
#define SYSCLK_FREQ_240MHz 240000000
|
||||
/* #define SYSCLK_FREQ_224MHz_HSI 224000000 */
|
||||
//#define SYSCLK_FREQ_240MHz 240000000
|
||||
#define SYSCLK_FREQ_224MHz_HSI 224000000
|
||||
/* #define SYSCLK_FREQ_240MHz_HSI 240000000 */
|
||||
#endif
|
||||
|
||||
|
||||
14
README.md
14
README.md
@@ -39,14 +39,20 @@ C/C++ 编译
|
||||
224K 最大SRAM (AT32F403A)
|
||||
|
||||
# TO-DO List 待办事项清单
|
||||
- Add more examples (USB)<br>
|
||||
增加更多示例 (USB)
|
||||
- Provide Bluepill board example?
|
||||
- none
|
||||
|
||||
# Screenshots 屏幕截图
|
||||
|
||||
|
||||
|
||||
# Available Examples
|
||||
**AT32F435**
|
||||
- LED Blink
|
||||
- USB vcp loopback
|
||||
|
||||
**AT32F403A**
|
||||
- LED BLink
|
||||
|
||||
# AT32F403A on Bluepill PCB - 在 Bluepill PCB 上使用 AT32F403A
|
||||
You can replace the MCU on the Bluepill board with the AT32F403A. It is pin fully compatible.
|
||||
Just need to replace BOOT0 resistor from the present value of 100K with the value of 10K. This will allow the MCU to enter in Bootloader mode and flash it via UART1.<br>
|
||||
@@ -56,5 +62,5 @@ Just need to replace BOOT0 resistor from the present value of 100K with the valu
|
||||
# AT32F435 on Blackpill PCB
|
||||
You can mount the AT32F435 on the [Blackpill PCB](https://item.taobao.com/item.htm?spm=a230r.1.14.44.458014682yTbFh&id=661526858750&ns=1&abbucket=11#detail) for STM32F103. It works without any other modification requied.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user